AGESA F15tn: AMD family15 AGESA code for Trinity

AMD AGESA code for trinity.

Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

668 files changed, 267702 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c
new file mode 100644
index 0000000000..738cf3955e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c
@@ -0,0 +1,234 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 P-state HPC mode Initialization
+ *
+ * Enables High performance Computing mode.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "cpuF15PowerMgmt.h"
+#include "CommonReturns.h"
+#include "cpuPstateHpcMode.h"
+#include "cpuPstateTables.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * entry point for enabling High Performance Computing.
+ *
+ * This function must be run after P-states initialization and before enabling low power P-states
+ *
+ * @param[in]  PstateHpcModeServices   The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15InitializePstateHpcMode (
+  IN       PSTATE_HPC_MODE_FAMILY_SERVICES  *PstateHpcModeServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT8   OriginalPstate;
+  UINT8   X;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  Core;
+  UINT32  SocketCount;
+  UINT32  i;
+  UINT64  MsrData;
+  PCI_ADDR  PciAddr;
+  AGESA_STATUS IgnoredSts;
+  AGESA_STATUS Flag;
+  F15_CPB_CTRL_REGISTER CpbCtrl;
+  CLK_PWR_TIMING_CTRL2_REGISTER CPTC2;
+  HTC_REGISTER Htc;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  LOCATE_HEAP_PTR        LocateHeapParams;
+  PSTATE_LEVELING        *PStateLevelingBuffer;
+  PSTATE_LEVELING        *PStateLevelingBufferTemp;
+
+  Flag = AGESA_SUCCESS;
+  // Locate P-State data buffer
+  LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    Flag = AGESA_ERROR;
+    PStateLevelingBuffer = NULL;
+    SocketCount = 1;
+  } else {
+    PStateLevelingBuffer = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->PStateLevelingStruc;
+    SocketCount = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->TotalSocketInSystem;
+  }
+
+  // Step1. Read MSRC001_0063[CurPstate] and store the value in OriginalPstate.
+  LibAmdMsrRead (MSR_PSTATE_STS, &MsrData, StdHeader);
+  OriginalPstate = (UINT8) (((PSTATE_STS_MSR *) &MsrData)->CurPstate);
+  // Step2. Write 0 to MSRC001_0062[PstateCmd].
+  // Step3. Wait for MSRC001_0063[CurPstate] == 0.
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+  // Step4. If D18F4x15C[NumBoostStates] != D18F3xDC[PstateMaxVal], execute the following sequence
+  //   4.A  Set X = D18F4x15C[NumBoostStates].
+  //   4.B  If X+1 == D18F3xDC[PstateMaxVal], go to step 5.
+  //   4.C  Copy MSRC001_00[6B:64] indexed by P-state X to MSRC001_00[6B:64] indexed by P-state X+1.
+  //   4.D  Write 0b to PstateEn from MSRC001_00[6B:64] indexed by P-state X+1.
+  //   4.E  Set X = X+1 and go to step B.
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoredSts);
+  PciAddr.Address.Function = FUNC_4;
+  PciAddr.Address.Register = CPB_CTRL_REG;
+  LibAmdPciRead (AccessWidth32, PciAddr, &CpbCtrl, StdHeader);  // F4x15C
+
+  PciAddr.Address.Function = FUNC_3;
+  PciAddr.Address.Register = CPTC2_REG;
+  LibAmdPciRead (AccessWidth32, PciAddr, &CPTC2, StdHeader);    // F3xDC
+
+  // In case that F3xDC[PstateMaxVal] was increased by Low Power Pstate function during the first time of running that function.
+  // Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable]
+  while (CPTC2.PstateMaxVal != 0) {
+    LibAmdMsrRead ((PS_REG_BASE + CPTC2.PstateMaxVal), &MsrData, StdHeader);
+    if ((MsrData & BIT63) == BIT63) {
+      break;
+    }
+    CPTC2.PstateMaxVal--;
+  }
+
+  if (CpbCtrl.NumBoostStates != CPTC2.PstateMaxVal) {
+    X = (UINT8) CpbCtrl.NumBoostStates;
+    while ((X + 1) < (UINT8) CPTC2.PstateMaxVal) {
+      LibAmdMsrRead ((PS_REG_BASE + X), &MsrData, StdHeader);
+      MsrData &= ~BIT63;
+      LibAmdMsrWrite ((PS_REG_BASE + X + 1), &MsrData, StdHeader);
+      // Make sure Agesa doesn't declared the P-states modified by these algorithms to the OS
+      if (PStateLevelingBuffer != NULL) {
+        PStateLevelingBufferTemp = PStateLevelingBuffer;
+        for (i = 0; i < SocketCount; i++) {
+          PStateLevelingBufferTemp->PStateCoreStruct[0].PStateStruct[X + 1].PStateEnable = 0;
+          //Calculate next node buffer address
+          PStateLevelingBufferTemp = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferTemp + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferTemp->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+        }
+      }
+      X++;
+    }
+  }
+  // Step5. Write OriginalPstate to MSRC001_0062[PstateCmd].
+  // Step6. Wait for MSRC001_0063[CurPstate] == OriginalPstate.
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, OriginalPstate, (BOOLEAN) TRUE, StdHeader);
+  // Step7. Write D18F3x64[HtcPstateLimit] with the value from D18F3xDC[PstateMaxVal]
+  PciAddr.Address.Register = HTC_REG;
+  LibAmdPciRead (AccessWidth32, PciAddr, &Htc, StdHeader);      // F3x64
+  Htc.HtcPstateLimit = CPTC2.PstateMaxVal;
+  LibAmdPciWrite (AccessWidth32, PciAddr, &Htc, StdHeader);     // F3x64
+
+  return Flag;
+}
+
+
+
+CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport =
+{
+  0,
+  F15InitializePstateHpcMode
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c
new file mode 100644
index 0000000000..77243c2d7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c
@@ -0,0 +1,224 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity C6 C-state feature support functions.
+ *
+ * Provides the functions necessary to initialize the C6 feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#include "cpuApicUtilities.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuEarlyInit.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+F15TnReloadMicrocodePatchAfterMemInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Is C6 supported on this CPU
+ *
+ * @param[in]    C6Services         Pointer to this CPU's C6 family services.
+ * @param[in]    Socket             This core's zero-based socket number.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 state is supported.
+ * @retval       FALSE              C6 state is not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F15TnIsC6Supported (
+  IN       C6_FAMILY_SERVICES      *C6Services,
+  IN       UINT32                  Socket,
+  IN       PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  ASSERT (IsFeatureEnabled (CacheFlushOnHalt, PlatformConfig, StdHeader) == TRUE);
+  // Assuming CFOH is always enabled.
+  return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable C6 on a family 15h CPU.
+ *
+ * @param[in]    C6Services         Pointer to this CPU's C6 family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15TnInitializeC6 (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR                PciAddress;
+  CSTATE_CTRL1_REGISTER   CstateCtrl1;
+  POPUP_PSTATE_REGISTER   PopDownPstate;
+  CLK_PWR_TIMING_CTRL2_REGISTER   ClkPwrTimingCtrl2;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
+    // Initialize F4x118
+    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+    // Set C-state Action Field 0
+    CstateCtrl1.PwrGateEnCstAct0 = 1;
+    CstateCtrl1.PwrOffEnCstAct0 = 1;
+    CstateCtrl1.NbPwrGate0 = 1;
+    CstateCtrl1.NbClkGate0 = 1;
+    CstateCtrl1.SelfRefr0 = 1;
+    CstateCtrl1.CpuPrbEnCstAct0 = 1;
+    // Set C-state Action Field 1
+    CstateCtrl1.PwrGateEnCstAct1 = 1;
+    CstateCtrl1.PwrOffEnCstAct1 = 1;
+    CstateCtrl1.NbPwrGate1 = 1;
+    CstateCtrl1.NbClkGate1 = 1;
+    CstateCtrl1.SelfRefr1 = 1;
+    CstateCtrl1.CpuPrbEnCstAct1 = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+
+    // Initialize F3xA8[PopDownPstate] = F3xDC[PstateMaxVal]
+    PciAddress.AddressValue = CPTC2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+    PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
+    PopDownPstate.PopDownPstate = ClkPwrTimingCtrl2.PstateMaxVal;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/**
+ *  Reload microcode patch after memory is initialized.
+ *
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+F15TnReloadMicrocodePatchAfterMemInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LoadMicrocodePatch (StdHeader);
+}
+
+CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support =
+{
+  0,
+  F15TnIsC6Supported,
+  F15TnInitializeC6,
+  F15TnReloadMicrocodePatchAfterMemInit
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
new file mode 100644
index 0000000000..0089c04960
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
@@ -0,0 +1,204 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 CPB Initialization
+ *
+ * Enables core performance boost.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "cpuCpb.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for checking whether or not CPB is supported.
+ *
+ * @param[in]  CpbServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  Socket                  Zero based socket number to check.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     TRUE                    CPB is supported.
+ * @retval     FALSE                   CPB is not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F15TnIsCpbSupported (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPB_CTRL_REGISTER     CpbControl;
+  PCI_ADDR              PciAddress;
+
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+  return (BOOLEAN) (CpbControl.NumBoostStates != 0);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for for enabling Core Performance Boost.
+ *
+ * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
+ *
+ * @param[in]  CpbServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  EntryPoint              Current CPU feature dispatch point.
+ * @param[in]  Socket                  Zero based socket number to check.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15TnInitializeCpb (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT64                 EntryPoint,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPB_CTRL_REGISTER     CpbControl;
+  PCI_ADDR              PciAddress;
+  F15_PSTATE_MSR        PstateMsrData;
+  UINT32                Pbx;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+    if (CpbControl.NumBoostStates == 0) {
+      CpbControl.ApmMasterEn = 0;
+    } else {
+      CpbControl.ApmMasterEn = 1;
+    }
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+
+  } else if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+    if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) {
+      // If any boosted P-state is still enabled, set BoostSrc = 1.
+      for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
+        LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
+        if (PstateMsrData.PsEnable == 1) {
+          CpbControl.BoostSrc = 1;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+          break;
+        }
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport =
+{
+  0,
+  F15TnIsCpbSupported,
+  F15TnInitializeCpb
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
new file mode 100644
index 0000000000..407455b7dc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
@@ -0,0 +1,155 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF15TnMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **TnEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] =
+{
+  0x6101, 0x6101,
+  0x6100, 0x6100
+};
+
+// Unencrypted equivalent
+STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] =
+{
+  0x6101, 0x6901,
+  0x6100, 0x6900
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  TnEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF15TnMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **TnEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrDeCfg;
+
+  LibAmdMsrRead (MSR_DE_CFG, &MsrDeCfg, StdHeader);
+  if ((MsrDeCfg & 0x80000) == 0) {
+    *NumberOfElements = ((sizeof (CpuF15TnUnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+    *TnEquivalenceTablePtr = CpuF15TnUnEncryptedMicrocodeEquivalenceTable;
+  } else {
+    *NumberOfElements = ((sizeof (CpuF15TnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+    *TnEquivalenceTablePtr = CpuF15TnMicrocodeEquivalenceTable;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
new file mode 100644
index 0000000000..8a41eb86a3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
@@ -0,0 +1,315 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize the Family 15h Trinity specific way of running early initialization.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x15/TN
+ * @e \$Revision: 64491 $   @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "Fch.h"
+#include "Gnb.h"
+#include "GnbLib.h"
+#include "cpuEarlyInit.h"
+#include "cpuF15TnPowerMgmt.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+F15TnLoadMicrocodePatchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+GetF15TnEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+
+VOID
+ApplyWorkaroundForFchErratum39 (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F15TnNbPstateForceBeforeApLaunchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE F15SetBrandIdRegistersAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+
+CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15TnEarlyInitOnCoreTable[] =
+{
+  {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {F15SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {F15TnLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {F15TnNbPstateForceBeforeApLaunchAtEarly, PERFORM_EARLY_WARM_RESET},
+  {NULL, 0}
+};
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
+ * processor that uses the standard initialization steps should take.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetF15TnEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  *Table = F15TnEarlyInitOnCoreTable;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Update microcode patch in current processor for Family15h TN.
+ *
+ * This function acts as a wrapper for calling the LoadMicrocodePatch
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+F15TnLoadMicrocodePatchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN        IsPatchLoaded;
+
+  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
+
+  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    IsPatchLoaded = LoadMicrocodePatch (StdHeader);
+  }
+
+  // After microcode patch has been loaded, apply the workaround for FCH erratum 39
+  ApplyWorkaroundForFchErratum39 (StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Apply the workaround for FCH H2/H3 erratum #39.
+ *
+ * This function detects the FCH version and applies the appropriate workaround, if
+ * required.
+ *
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+ApplyWorkaroundForFchErratum39 (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT8          MiscReg51;
+  UINT8          RevisionId;
+  UINT16         AcpiPmTmrBlk;
+  UINT32         VendorIdDeviceId;
+  UINT64         MsrValue;
+  PCI_ADDR       PciAddress;
+  AGESA_STATUS   IgnoredSts;
+  CPU_LOGICAL_ID LogicalId;
+
+  // Read Vendor ID / Device ID
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
+  LibAmdPciRead (AccessWidth32, PciAddress, &VendorIdDeviceId, StdHeader);
+
+  // For Hudson based system, perform workaround
+  if (VendorIdDeviceId == 0x780B1022) {
+    PciAddress.Address.Register = 0x8;
+    LibAmdPciRead (AccessWidth8, PciAddress, &RevisionId, StdHeader);
+    if ((RevisionId == 0x14) && IsBsp (StdHeader, &IgnoredSts)) {
+      // Enable hardware workaround by setting Misc_reg x51[0]
+      LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader);
+      MiscReg51 |= BIT0;
+      LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader);
+    } else if (RevisionId == 0x13) {
+      GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+      if ((LogicalId.Revision & AMD_F15_TN_GT_A0) != 0) {
+        // For revs A1+, set up the C0010055 MSR
+        GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x64, 2, &AcpiPmTmrBlk, StdHeader);
+        LibAmdMsrRead (0xC0010055, &MsrValue, StdHeader);
+        MsrValue |= BIT30;
+        MsrValue |= AcpiPmTmrBlk;
+        LibAmdMsrWrite (0xC0010055, &MsrValue, StdHeader);
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Prevent NB P-state transitions prior to AP launch on Family 15h TN.
+ *
+ * This function determines the current NB P-state and forces the NB to remain
+ * in that P-state.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+F15TnNbPstateForceBeforeApLaunchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64                    MsrValue;
+  UINT64                    PerfCtrlSave;
+  UINT64                    PerfStsSave;
+  PCI_ADDR                  PciAddress;
+  AGESA_STATUS              IgnoredSts;
+  ALLOCATE_HEAP_PARAMS      Alloc;
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrl;
+
+  if (IsBsp (StdHeader, &IgnoredSts) && FamilyServices->IsNbPstateEnabled (FamilyServices, &EarlyParams->PlatformConfig, StdHeader)) {
+    LibAmdMsrRead (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader);
+    MsrValue = 0x00000006004004E9;
+    LibAmdMsrRead (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader);
+    LibAmdMsrWrite (MSR_NB_PERF_CTL3, &MsrValue, StdHeader);
+    MsrValue = 0;
+    LibAmdMsrWrite (MSR_NB_PERF_CTR3, &MsrValue, StdHeader);
+    PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    Alloc.RequestedBufferSize = sizeof (NB_PSTATE_CTRL_REGISTER);
+    Alloc.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE;
+    Alloc.Persist = 0;
+    if (HeapAllocateBuffer (&Alloc, StdHeader) == AGESA_SUCCESS) {
+      *((NB_PSTATE_CTRL_REGISTER *) Alloc.BufferPtr) = NbPsCtrl;
+    } else {
+      ASSERT (FALSE);
+    }
+    LibAmdMsrRead (MSR_NB_PERF_CTR3, &MsrValue, StdHeader);
+    if (MsrValue == 0) {
+      NbPsCtrl.SwNbPstateLoDis = 1;
+    } else {
+      NbPsCtrl.SwNbPstateLoDis = 0;
+      NbPsCtrl.NbPstateDisOnP0 = 0;
+      NbPsCtrl.NbPstateThreshold = 0;
+    }
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    LibAmdMsrWrite (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader);
+    LibAmdMsrWrite (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
new file mode 100644
index 0000000000..acbf23edb1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
@@ -0,0 +1,402 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity IO C-state feature support functions.
+ *
+ * Provides the functions necessary to initialize the IO C-state feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "cpuIoCstate.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F15TnInitializeIoCstateOnCore (
+  IN       VOID *CstateBaseMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F15TnIsCsdObjGenerated (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            IoCstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable IO Cstate on a family 15h Trinity CPU.
+ *  Implement BIOS Requirements for Initialization of C-states
+ *
+ * @param[in]    IoCstateServices   Pointer to this CPU's IO Cstate family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15TnInitializeIoCstate (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT64                    EntryPoint,
+  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64                              LocalMsrRegister;
+  AP_TASK                             TaskPtr;
+  PCI_ADDR                            PciAddress;
+  CSTATE_POLICY_CTRL1_REGISTER        CstatePolicyCtrl1;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
+    // Initialize F4x128
+    // bit[1]   CoreCstatePolicy = 0
+    // bit[4:2] HaltCstateIndex = 0
+    // bit[31]  CstateMsgDis = 1
+    PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
+    CstatePolicyCtrl1.CoreCstatePolicy = 0;
+    CstatePolicyCtrl1.HaltCstateIndex = 0;
+    CstatePolicyCtrl1.CstateMsgDis = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
+
+    // Initialize MSRC001_0073[CstateAddr] on each core to a region of
+    // the IO address map with 8 consecutive available addresses.
+    LocalMsrRegister = 0;
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "    Init IO C-state Base at 0x%x\n", PlatformConfig->CStateIoBaseAddress);
+    ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+
+    TaskPtr.FuncAddress.PfApTaskI = F15TnInitializeIoCstateOnCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable CState on a family 15h Trinity core.
+ *
+ * @param[in]    CstateBaseMsr      MSR value to write to C001_0073 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F15TnInitializeIoCstateOnCore (
+  IN       VOID *CstateBaseMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // Initialize MSRC001_0073[CstateAddr] on each core
+  LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the size of CST object
+ *
+ * @param[in]    IoCstateServices   IO Cstate services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       CstObjSize         Size of CST Object
+ *
+ */
+UINT32
+STATIC
+F15TnGetAcpiCstObj (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  BOOLEAN                   GenerateCsdObj;
+  UINT32                    CStateAcpiObjSize;
+  IO_CSTATE_FAMILY_SERVICES *FamilyServices;
+  ACPI_CST_GET_INPUT CstGetInput;
+
+  CstGetInput.IoCstateServices = IoCstateServices;
+  CstGetInput.PlatformConfig = PlatformConfig;
+  CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize;
+
+  IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) {
+    CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE;
+
+    // If CSD Object is generated, add the size of CSD Object to the total size of
+    // CState ACPI Object size
+    GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
+
+    if (GenerateCsdObj) {
+      CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE;
+    }
+  }
+  return CStateAcpiObjSize;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Routine to generate the C-State ACPI objects
+ *
+ * @param[in]      IoCstateServices       IO Cstate services.
+ * @param[in]      LocalApicId            Local Apic Id for each core.
+ * @param[in, out] **PstateAcpiBufferPtr  Pointer to the Acpi Buffer Pointer.
+ * @param[in]      StdHeader              Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F15TnCreateAcpiCstObj (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT8                     LocalApicId,
+  IN OUT   VOID                      **PstateAcpiBufferPtr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64                MsrData;
+  BOOLEAN               GenerateCsdObj;
+  CST_HEADER_STRUCT     *CstHeaderPtr;
+  CST_BODY_STRUCT       *CstBodyPtr;
+  CSD_HEADER_STRUCT     *CsdHeaderPtr;
+  CSD_BODY_STRUCT       *CsdBodyPtr;
+  IO_CSTATE_FAMILY_SERVICES    *FamilyServices;
+  ACPI_CST_CREATE_INPUT  CstInput;
+
+  CstInput.IoCstateServices = IoCstateServices;
+  CstInput.LocalApicId = LocalApicId;
+  CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr;
+
+  IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) {
+    // Read from MSR C0010073 to obtain CstateAddr
+    LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
+
+    // Typecast the pointer
+    CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
+
+    // Set CST Header
+    CstHeaderPtr->NameOpcode  = NAME_OPCODE;
+    CstHeaderPtr->CstName_a__ = CST_NAME__;
+    CstHeaderPtr->CstName_a_C = CST_NAME_C;
+    CstHeaderPtr->CstName_a_S = CST_NAME_S;
+    CstHeaderPtr->CstName_a_T = CST_NAME_T;
+
+    // Typecast the pointer
+    CstHeaderPtr++;
+    CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
+
+    // Set CST Body
+    CstBodyPtr->PkgOpcode      = PACKAGE_OPCODE;
+    CstBodyPtr->PkgLength      = CST_LENGTH;
+    CstBodyPtr->PkgElements    = CST_NUM_OF_ELEMENTS;
+    CstBodyPtr->BytePrefix     = BYTE_PREFIX_OPCODE;
+    CstBodyPtr->Count          = CST_COUNT;
+    CstBodyPtr->PkgOpcode2     = PACKAGE_OPCODE;
+    CstBodyPtr->PkgLength2     = CST_PKG_LENGTH;
+    CstBodyPtr->PkgElements2   = CST_PKG_ELEMENTS;
+    CstBodyPtr->BufferOpcode   = BUFFER_OPCODE;
+    CstBodyPtr->BufferLength   = CST_SUBPKG_LENGTH;
+    CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
+    CstBodyPtr->BufferOpcode2  = BUFFER_OPCODE;
+    CstBodyPtr->GdrOpcode      = GENERIC_REG_DESCRIPTION;
+    CstBodyPtr->GdrLength      = CST_GDR_LENGTH;
+    CstBodyPtr->AddrSpaceId    = GDR_ASI_SYSTEM_IO;
+    CstBodyPtr->RegBitWidth    = 0x08;
+    CstBodyPtr->RegBitOffset   = 0x00;
+    CstBodyPtr->AddressSize    = GDR_ASZ_BYTE_ACCESS;
+    CstBodyPtr->RegisterAddr   = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
+    CstBodyPtr->EndTag         = 0x0079;
+    CstBodyPtr->BytePrefix2    = BYTE_PREFIX_OPCODE;
+    CstBodyPtr->Type           = CST_C2_TYPE;
+    CstBodyPtr->WordPrefix     = WORD_PREFIX_OPCODE;
+    CstBodyPtr->Latency        = 100;
+    CstBodyPtr->DWordPrefix    = DWORD_PREFIX_OPCODE;
+    CstBodyPtr->Power          = 0;
+
+    CstBodyPtr++;
+    //Update the pointer
+    *PstateAcpiBufferPtr = CstBodyPtr;
+
+
+  // Check whether CSD object should be generated
+    GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
+
+    if (GenerateCsdObj) {
+      CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr;
+
+      // Set CSD Header
+      CsdHeaderPtr->NameOpcode  = NAME_OPCODE;
+      CsdHeaderPtr->CsdName_a__ = CST_NAME__;
+      CsdHeaderPtr->CsdName_a_C = CST_NAME_C;
+      CsdHeaderPtr->CsdName_a_S = CST_NAME_S;
+      CsdHeaderPtr->CsdName_a_D = CSD_NAME_D;
+
+      CsdHeaderPtr++;
+      CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr;
+
+      // Set CSD Body
+      CsdBodyPtr->PkgOpcode         = PACKAGE_OPCODE;
+      CsdBodyPtr->PkgLength         = CSD_BODY_SIZE - 1;
+      CsdBodyPtr->PkgElements       = 1;
+      CsdBodyPtr->PkgOpcode2        = PACKAGE_OPCODE;
+      CsdBodyPtr->PkgLength2        = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode
+      CsdBodyPtr->PkgElements2      = 6;
+      CsdBodyPtr->BytePrefix        = BYTE_PREFIX_OPCODE;
+      CsdBodyPtr->NumEntries        = 6;
+      CsdBodyPtr->BytePrefix2       = BYTE_PREFIX_OPCODE;
+      CsdBodyPtr->Revision          = 0;
+      CsdBodyPtr->DWordPrefix       = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->Domain            = (LocalApicId & 0xFE) >> 1;
+      CsdBodyPtr->DWordPrefix2      = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->CoordType         = CSD_COORD_TYPE_HW_ALL;
+      CsdBodyPtr->DWordPrefix3      = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->NumProcessors     = 0x2;
+      CsdBodyPtr->DWordPrefix4      = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->Index             = 0x0;
+
+      CsdBodyPtr++;
+
+      // Update the pointer
+      *PstateAcpiBufferPtr = CsdBodyPtr;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Routine to check whether CSD object should be created.
+ *
+ * @param[in]      IoCstateServices      IO Cstate services.
+ * @param[in]      StdHeader             Config Handle for library, services.
+ *
+ * @retval         TRUE                  CSD Object should be created.
+ * @retval         FALSE                 CSD Object should not be created.
+ *
+ */
+BOOLEAN
+F15TnIsCsdObjGenerated (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  // CSD Object should only be created when there are two cores per compute unit
+  if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport =
+{
+  0,
+  (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
+  F15TnInitializeIoCstate,
+  F15TnGetAcpiCstObj,
+  F15TnCreateAcpiCstObj,
+  F15TnIsCsdObjGenerated
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
new file mode 100644
index 0000000000..931f27f2ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF15TnLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **TnIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15TnLogicalIdAndRevArray[] =
+{
+  {
+    0x6101,
+    AMD_F15_TN_A1
+  },
+  {
+    0x6100,
+    0x0000000000000100ull
+  }
+};
+
+VOID
+GetF15TnLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **TnIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF15TnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *TnIdPtr = CpuF15TnLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_15_TN;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c
new file mode 100644
index 0000000000..dbd9ee2020
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c
@@ -0,0 +1,2701 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD F15Tn Microcode patch.
+ *
+ * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 64060 $   @e \$Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+UCODE_VS_FLAG (0600110F_Enc)
+
+// Encrypt Patch code 0600110F for 6101 and equivalent
+
+CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] =
+{
+  0x12,
+  0x20,
+  0x11,
+  0x01,
+  0x0f,
+  0x11,
+  0x00,
+  0x06,
+  0x02,
+  0x80,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x01,
+  0x61,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0xd4,
+  0x3d,
+  0x97,
+  0xf0,
+  0xd2,
+  0x1a,
+  0xcf,
+  0x44,
+  0x1d,
+  0x45,
+  0x82,
+  0x13,
+  0xec,
+  0xcd,
+  0x52,
+  0x24,
+  0x2d,
+  0x26,
+  0x73,
+  0x9f,
+  0x0e,
+  0x38,
+  0x80,
+  0x5b,
+  0x02,
+  0x6a,
+  0xd3,
+  0x80,
+  0x97,
+  0xc0,
+  0xe8,
+  0x08,
+  0xaf,
+  0x52,
+  0x2e,
+  0xe4,
+  0x54,
+  0xa6,
+  0xb3,
+  0xb3,
+  0x9b,
+  0x21,
+  0xb9,
+  0xe1,
+  0xa8,
+  0xa4,
+  0xed,
+  0x9a,
+  0x76,
+  0xf7,
+  0x62,
+  0x13,
+  0x3b,
+  0xf8,
+  0x21,
+  0xc4,
+  0xf3,
+  0xff,
+  0xb5,
+  0x20,
+  0xbd,
+  0x8c,
+  0x3a,
+  0x4b,
+  0x7e,
+  0x44,
+  0x88,
+  0x9e,
+  0x21,
+  0xf3,
+  0x32,
+  0xad,
+  0x96,
+  0xf9,
+  0x1d,
+  0xe4,
+  0xce,
+  0xdd,
+  0xb7,
+  0x58,
+  0x6c,
+  0x3c,
+  0x78,
+  0x00,
+  0x9f,
+  0x9f,
+  0x76,
+  0x6e,
+  0x92,
+  0x80,
+  0xb9,
+  0x6a,
+  0xcf,
+  0x66,
+  0x2b,
+  0x7e,
+  0x1d,
+  0xbf,
+  0x2d,
+  0xca,
+  0xde,
+  0x58,
+  0x1b,
+  0xc6,
+  0xb8,
+  0x5e,
+  0x82,
+  0xc3,
+  0xdf,
+  0x8b,
+  0xd8,
+  0xdb,
+  0xca,
+  0x43,
+  0xf2,
+  0x75,
+  0x40,
+  0xb6,
+  0xbf,
+  0xdb,
+  0x5f,
+  0xb8,
+  0xd2,
+  0xdd,
+  0x81,
+  0xeb,
+  0xa6,
+  0x7f,
+  0x01,
+  0xbc,
+  0x37,
+  0x07,
+  0x4e,
+  0x73,
+  0x13,
+  0xcf,
+  0x08,
+  0xb9,
+  0xd6,
+  0xda,
+  0xe6,
+  0x10,
+  0xd7,
+  0x2c,
+  0xfe,
+  0x49,
+  0x3e,
+  0x4b,
+  0xa0,
+  0xfa,
+  0xc1,
+  0x81,
+  0xe9,
+  0xdb,
+  0x70,
+  0xfd,
+  0x46,
+  0xc4,
+  0x44,
+  0x4c,
+  0x14,
+  0xc2,
+  0x1a,
+  0x46,
+  0xa5,
+  0x2c,
+  0xb3,
+  0x04,
+  0x15,
+  0xda,
+  0x53,
+  0x74,
+  0x41,
+  0x61,
+  0xcc,
+  0xda,
+  0x40,
+  0x53,
+  0x03,
+  0x4a,
+  0x51,
+  0xc2,
+  0x4f,
+  0x81,
+  0x34,
+  0x89,
+  0x4f,
+  0x7c,
+  0x7e,
+  0xa0,
+  0x50,
+  0x7a,
+  0xc8,
+  0xf3,
+  0xd0,
+  0xfc,
+  0x7f,
+  0xda,
+  0xa8,
+  0x61,
+  0x6c,
+  0x46,
+  0xb3,
+  0xc9,
+  0x05,
+  0x0b,
+  0x9f,
+  0x5e,
+  0xb1,
+  0x43,
+  0x9d,
+  0xc0,
+  0x3a,
+  0xbe,
+  0x6e,
+  0x05,
+  0x30,
+  0x3d,
+  0xf1,
+  0xee,
+  0x0e,
+  0xcf,
+  0x63,
+  0x40,
+  0xe9,
+  0xd3,
+  0x27,
+  0x2c,
+  0x0a,
+  0x48,
+  0xe8,
+  0xae,
+  0xc0,
+  0x38,
+  0xae,
+  0x3b,
+  0x41,
+  0x21,
+  0x5a,
+  0xa2,
+  0xc0,
+  0x20,
+  0x77,
+  0x18,
+  0x9b,
+  0x7f,
+  0xdd,
+  0x95,
+  0x4b,
+  0x8b,
+  0x83,
+  0x2c,
+  0xfb,
+  0x49,
+  0xd8,
+  0x25,
+  0xf2,
+  0x21,
+  0x6e,
+  0x54,
+  0xe5,
+  0x01,
+  0x22,
+  0xd5,
+  0xf8,
+  0x99,
+  0x1f,
+  0x83,
+  0x69,
+  0x52,
+  0xa1,
+  0x9a,
+  0x67,
+  0x73,
+  0x55,
+  0xa2,
+  0x98,
+  0x82,
+  0x8c,
+  0xff,
+  0xed,
+  0x9c,
+  0x0a,
+  0x07,
+  0x33,
+  0x6f,
+  0x16,
+  0x39,
+  0x79,
+  0xcc,
+  0xe3,
+  0x5a,
+  0xa0,
+  0x2d,
+  0xa6,
+  0xdf,
+  0x2e,
+  0x4b,
+  0xab,
+  0x6c,
+  0x6f,
+  0xd4,
+  0x6e,
+  0x70,
+  0x9b,
+  0x9a,
+  0xf3,
+  0xb3,
+  0x52,
+  0xb8,
+  0x05,
+  0x53,
+  0xba,
+  0x79,
+  0x08,
+  0x6a,
+  0xb1,
+  0x5e,
+  0xf7,
+  0x85,
+  0xc1,
+  0xfc,
+  0xd8,
+  0xb5,
+  0x3d,
+  0xbb,
+  0xb9,
+  0x3d,
+  0xa3,
+  0x98,
+  0x13,
+  0x61,
+  0xed,
+  0x1e,
+  0xc0,
+  0x45,
+  0x6c,
+  0x98,
+  0xfc,
+  0x87,
+  0x2c,
+  0xb8,
+  0x99,
+  0x97,
+  0xb8,
+  0xc7,
+  0x5f,
+  0x2e,
+  0x6d,
+  0x28,
+  0x79,
+  0xaf,
+  0x0b,
+  0xf9,
+  0x84,
+  0x7e,
+  0x34,
+  0xd8,
+  0x86,
+  0x61,
+  0x22,
+  0xdb,
+  0xf4,
+  0xef,
+  0x58,
+  0x0d,
+  0x4e,
+  0xcf,
+  0x02,
+  0x8a,
+  0xf8,
+  0x17,
+  0xab,
+  0x7d,
+  0x79,
+  0x98,
+  0x38,
+  0x35,
+  0x59,
+  0xdf,
+  0x03,
+  0xff,
+  0xed,
+  0xc7,
+  0x1f,
+  0x25,
+  0xe3,
+  0x26,
+  0x05,
+  0xde,
+  0x7f,
+  0xbb,
+  0xe4,
+  0xff,
+  0xbf,
+  0x6d,
+  0xc6,
+  0xc2,
+  0x2e,
+  0x02,
+  0x45,
+  0x85,
+  0x5f,
+  0x43,
+  0xdb,
+  0xb8,
+  0xd2,
+  0x13,
+  0xd7,
+  0x52,
+  0xde,
+  0x53,
+  0x49,
+  0xda,
+  0x7f,
+  0x0b,
+  0xb8,
+  0x76,
+  0x70,
+  0xf9,
+  0xfe,
+  0xf0,
+  0x27,
+  0xb7,
+  0xc9,
+  0xd4,
+  0x83,
+  0x6d,
+  0x80,
+  0xaa,
+  0x34,
+  0x46,
+  0xf5,
+  0xe3,
+  0x1f,
+  0xd7,
+  0x0f,
+  0xf2,
+  0xee,
+  0x5a,
+  0xb2,
+  0xcd,
+  0x08,
+  0x47,
+  0xe6,
+  0xf7,
+  0x99,
+  0xd1,
+  0x05,
+  0x55,
+  0x0f,
+  0x5f,
+  0x1d,
+  0xab,
+  0xd6,
+  0xb3,
+  0x32,
+  0xaf,
+  0xa1,
+  0x57,
+  0x4d,
+  0x32,
+  0x00,
+  0x4f,
+  0xf6,
+  0x6f,
+  0x6e,
+  0x79,
+  0x8a,
+  0x7c,
+  0xc2,
+  0xef,
+  0x7e,
+  0xcd,
+  0x83,
+  0xac,
+  0x85,
+  0x0e,
+  0x53,
+  0x2c,
+  0xd9,
+  0x92,
+  0xf5,
+  0x55,
+  0xf6,
+  0xc9,
+  0x41,
+  0xed,
+  0xf5,
+  0x4e,
+  0x41,
+  0xea,
+  0x97,
+  0xca,
+  0x3b,
+  0x14,
+  0xca,
+  0x0d,
+  0x4e,
+  0xb9,
+  0x5f,
+  0x54,
+  0x23,
+  0xf1,
+  0xdc,
+  0x8b,
+  0xa4,
+  0xc1,
+  0x52,
+  0xe2,
+  0x7a,
+  0x8f,
+  0xdf,
+  0x3f,
+  0x93,
+  0xa1,
+  0x84,
+  0x5c,
+  0xca,
+  0x6a,
+  0x3a,
+  0x42,
+  0x95,
+  0x2e,
+  0x71,
+  0xf6,
+  0xa2,
+  0x88,
+  0x56,
+  0x32,
+  0xe8,
+  0x98,
+  0x2a,
+  0xb8,
+  0xf0,
+  0x65,
+  0x95,
+  0x01,
+  0xb8,
+  0xc8,
+  0x23,
+  0xe9,
+  0x30,
+  0x52,
+  0x94,
+  0xeb,
+  0xfa,
+  0x9f,
+  0x67,
+  0x53,
+  0xf0,
+  0x63,
+  0x10,
+  0x70,
+  0x1b,
+  0x01,
+  0x71,
+  0x21,
+  0xb3,
+  0x27,
+  0x4e,
+  0x37,
+  0x04,
+  0xdc,
+  0x74,
+  0x6f,
+  0xf3,
+  0x08,
+  0x00,
+  0x72,
+  0x21,
+  0x96,
+  0xe5,
+  0xc6,
+  0x75,
+  0xa8,
+  0x14,
+  0x6f,
+  0xcf,
+  0xd8,
+  0x86,
+  0xe3,
+  0xb7,
+  0xf3,
+  0x8c,
+  0xe4,
+  0x71,
+  0x03,
+  0x60,
+  0xd4,
+  0x53,
+  0xff,
+  0x5a,
+  0x07,
+  0xc4,
+  0xe5,
+  0x6b,
+  0xf4,
+  0x8d,
+  0x80,
+  0x55,
+  0x78,
+  0x4f,
+  0xf5,
+  0x55,
+  0x04,
+  0x2e,
+  0x61,
+  0x05,
+  0x46,
+  0x51,
+  0x56,
+  0xf8,
+  0x0a,
+  0xf5,
+  0x6e,
+  0x08,
+  0x85,
+  0xfd,
+  0x01,
+  0x9a,
+  0x90,
+  0x5a,
+  0xed,
+  0x0e,
+  0x44,
+  0x49,
+  0xff,
+  0x48,
+  0xbe,
+  0x5b,
+  0xc4,
+  0xea,
+  0xbb,
+  0x38,
+  0xa9,
+  0x04,
+  0xf3,
+  0x6c,
+  0x6b,
+  0x41,
+  0x85,
+  0x59,
+  0x18,
+  0x38,
+  0xd5,
+  0x52,
+  0x18,
+  0x1d,
+  0xdd,
+  0xab,
+  0x28,
+  0xd9,
+  0x05,
+  0xfe,
+  0xd9,
+  0xc6,
+  0xa9,
+  0x25,
+  0xf4,
+  0xb5,
+  0xcb,
+  0x9c,
+  0x1d,
+  0xe8,
+  0x6f,
+  0x21,
+  0xd3,
+  0x5b,
+  0x88,
+  0x44,
+  0x2c,
+  0x10,
+  0xaf,
+  0x43,
+  0xcc,
+  0xe8,
+  0x10,
+  0x9d,
+  0xc1,
+  0xb2,
+  0x14,
+  0xae,
+  0xa3,
+  0x1d,
+  0x05,
+  0x97,
+  0xca,
+  0x45,
+  0xef,
+  0x5c,
+  0x57,
+  0x60,
+  0x49,
+  0x75,
+  0x7d,
+  0x80,
+  0xd2,
+  0x9e,
+  0x44,
+  0xf0,
+  0xed,
+  0x7e,
+  0x32,
+  0x3a,
+  0x12,
+  0xc6,
+  0xff,
+  0x07,
+  0x0d,
+  0xbf,
+  0xcf,
+  0x42,
+  0xe5,
+  0xde,
+  0x44,
+  0x19,
+  0x70,
+  0x22,
+  0x76,
+  0x6b,
+  0x30,
+  0x6f,
+  0x8d,
+  0x69,
+  0x75,
+  0x5d,
+  0xc4,
+  0x7e,
+  0xf7,
+  0x99,
+  0xe1,
+  0x37,
+  0x84,
+  0xee,
+  0x97,
+  0x5c,
+  0x83,
+  0xdf,
+  0xd0,
+  0xe9,
+  0x1c,
+  0xb0,
+  0x9f,
+  0x13,
+  0x81,
+  0x51,
+  0x51,
+  0xaf,
+  0x61,
+  0xb4,
+  0x35,
+  0x1f,
+  0xe2,
+  0x54,
+  0xe9,
+  0x68,
+  0x75,
+  0x3c,
+  0xcc,
+  0x51,
+  0x9c,
+  0x75,
+  0x27,
+  0x66,
+  0xe7,
+  0x95,
+  0x7d,
+  0x91,
+  0xd8,
+  0xf0,
+  0xff,
+  0x47,
+  0xc6,
+  0x51,
+  0xb3,
+  0xef,
+  0x03,
+  0xaf,
+  0x61,
+  0x59,
+  0x95,
+  0x43,
+  0x14,
+  0xce,
+  0xdf,
+  0x48,
+  0xc8,
+  0xea,
+  0xbc,
+  0x13,
+  0x98,
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+  0x5f,
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+  0x95,
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+  0x45,
+  0xdc,
+  0xda,
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+  0xba,
+  0xf3,
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+  0xe2,
+  0x43,
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+  0x16,
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+  0xfc,
+  0xee,
+  0x6b,
+  0x52,
+  0x9b,
+  0xd0,
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+  0x02,
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+  0xb4,
+  0xb5,
+  0x12,
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+  0x65,
+  0x48,
+  0xfd,
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+  0x3e,
+  0x55,
+  0xff,
+  0x14,
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+  0x18,
+  0x0f,
+  0x2f,
+  0x20,
+  0x52,
+  0x20,
+  0xde,
+  0x15,
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+  0x23,
+  0x10,
+  0xa2,
+  0x1c,
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+  0x84,
+  0x81,
+  0x21,
+  0xb0,
+  0x6b,
+  0x25,
+  0xa8,
+  0x3e,
+  0xc6,
+  0xa4,
+  0xc2,
+  0x0a,
+  0x46,
+  0x52,
+  0x4f,
+  0x72,
+  0x56,
+  0x06,
+  0xec,
+  0x76,
+  0xda,
+  0x7e,
+  0x09,
+  0x45,
+  0x05,
+  0x9b,
+  0xdb,
+  0x31,
+  0x90,
+  0x63,
+  0xdf,
+  0x98,
+  0x47,
+  0x4a,
+  0x9e,
+  0x28,
+  0x3d,
+  0x0d,
+  0x64,
+  0xfb,
+  0x44,
+  0xc5,
+  0xfb,
+  0xe2,
+  0x56,
+  0xe9,
+  0x08,
+  0x98,
+  0x79,
+  0x2f,
+  0xaf,
+  0x15,
+  0xb5,
+  0xea,
+  0x7e,
+  0x61,
+  0x89,
+  0x16,
+  0x5e,
+  0x9c,
+  0x6e,
+  0xca,
+  0x90,
+  0x90,
+  0x4a,
+  0x5f,
+  0x14,
+  0x83,
+  0x67,
+  0x47,
+  0x44,
+  0xae,
+  0x0a,
+  0x83,
+  0xc4,
+  0x95,
+  0xf6,
+  0x88,
+  0xc2,
+  0xfb,
+  0xa3,
+  0x9b,
+  0x7a,
+  0xf9,
+  0x32,
+  0x80,
+  0x94,
+  0xf4,
+  0x16,
+  0x5a,
+  0xd4,
+  0xef,
+  0x39,
+  0xe8,
+  0x86,
+  0xe1,
+  0xcd,
+  0x6a,
+  0x7e,
+  0xca,
+  0x33,
+  0xa1,
+  0xd4,
+  0xcb,
+  0xe9,
+  0x5a,
+  0xca,
+  0xc6,
+  0xb0,
+  0xd9,
+  0x68,
+  0x27,
+  0x8c,
+  0x93,
+  0x47,
+  0x3e,
+  0x4f,
+  0xc0,
+  0xa8,
+  0x86,
+  0x68,
+  0x4b,
+  0x1a,
+  0xf5,
+  0x93,
+  0xdd,
+  0x16,
+  0xed,
+  0x8e,
+  0x27,
+  0x66,
+  0x4d,
+  0x59,
+  0xf0,
+  0x27,
+  0x1b,
+  0x37,
+  0xa0,
+  0x25,
+  0x9a,
+  0x62,
+  0xb4,
+  0x6f,
+  0xbd,
+  0x83,
+  0x28,
+  0x0b,
+  0x26,
+  0xa9,
+  0x07,
+  0xac,
+  0xb5,
+  0x91,
+  0x93,
+  0x91,
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
new file mode 100644
index 0000000000..c2ea312fb9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
@@ -0,0 +1,138 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity microcode patches
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15TnMicroCodePatchArray[];
+extern CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF15TnMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **TnUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  TnUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF15TnMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **TnUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = CpuF15TnNumberOfMicrocodePatches;
+  *TnUcodePtr = &CpuF15TnMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
new file mode 100644
index 0000000000..1be61540cc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
@@ -0,0 +1,324 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63495 $   @e \$Date: 2011-12-23 01:30:59 -0600 (Fri, 23 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "F15TnPackageType.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SetTopologyExtensions (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+SetForceSmcCheckFlwStDis (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_NB_CFG (0xC001001F)
+// bit[23] = 1, erratum #663
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_NB_CFG,                            // MSR Address
+      0x0000000000800000,                    // OR Mask
+      0x0000000000800000,                    // NAND Mask
+    }}
+  },
+
+// MSR_LS_CFG2 (0xC001102D)
+// bit[23] DisScbThreshold = 1
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_LS_CFG2,                           // MSR Address
+      0x0000000000800000,                    // OR Mask
+      0x0000000000800000,                    // NAND Mask
+    }}
+  },
+// MSR_HWCR (0xC0010015)
+// bit[27] EffFreqReadOnlyLock = 1
+// bit[12] HltXSpCycEn = 1
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_HWCR,                              // MSR Address
+      0x0000000008001000,                    // OR Mask
+      0x0000000008001000,                    // NAND Mask
+    }}
+  },
+// MSR_OSVW_ID_Length (0xC0010140)
+// bit[15:0] = 4
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_OSVW_ID_Length,                    // MSR Address
+      0x0000000000000004,                    // OR Mask
+      0x000000000000FFFF,                    // NAND Mask
+    }}
+  },
+// MSR 0xC0011000
+// bit[17] = 1, Disable Erratum #671
+// bit[16] = 1, Erratum #608 for all TN revisions
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                         // platformFeatures
+    {{
+      0xC0011000,                            // MSR Address
+      0x0000000000030000,                    // OR Mask
+      0x0000000000030000,                    // NAND Mask
+    }}
+  },
+// MSR_CPUID_EXT_FEATS (0xC0011005)
+// bit[51]  NodeId = 1
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                         // platformFeatures
+    {{
+      MSR_CPUID_EXT_FEATS,                   // MSR Address
+      0x0008000000000000,                    // OR Mask
+      0x0008000000000000,                    // NAND Mask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable = {
+  AllCores,
+  (sizeof (F15TnMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F15TnMsrRegisters,
+};
+
+// MSR with Special Programming Requirements Table
+
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrWorkarounds[] =
+{
+// MSR_C001_1005
+  {
+    FamSpecificWorkaround,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                        // CpuFamily
+      AMD_F15_TN_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      SetTopologyExtensions,                // function call
+      0x00000000,                           // data
+    }}
+  },
+// MSR_C001_102D
+  {
+    FamSpecificWorkaround,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                        // CpuFamily
+      AMD_F15_TN_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      SetForceSmcCheckFlwStDis,             // function call
+      0x00000000,                           // data
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable = {
+  AllCores,
+  (sizeof (F15TnMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F15TnMsrWorkarounds,
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  MSR special programming requirements for MSR_C001_1005
+ *
+ *  AGESA should program MSR_C001_1005[54, TopologyExtensions] as follows:
+ *  IF (CPUID Fn8000_0001_EBX[PkgType]==0010b) THEN 0 ELSE 1 ENDIF.
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+SetTopologyExtensions (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PkgType;
+  UINT64 CpuMsrData;
+
+  PkgType = LibAmdGetPackageType (StdHeader);
+  LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
+  CpuMsrData &= ~(BIT54);
+  if (PkgType == PACKAGE_TYPE_FM2) {
+    CpuMsrData |= BIT54;
+  }
+  LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  MSR special programming requirements for MSR_C001_102D
+ *
+ *  AGESA should program MSR_C001_102D[14] with the fused value from F3x1FC[23]
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+SetForceSmcCheckFlwStDis (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR PciAddress;
+  PRODUCT_INFO_REGISTER ProductInfo;
+  LS_CFG2_MSR LsCfg2;
+
+  PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &ProductInfo, StdHeader);
+
+  LibAmdMsrRead (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader);
+
+  LsCfg2.ForceSmcCheckFlwStDis = ProductInfo.ForceSmcCheckFlwStDis;
+  LibAmdMsrWrite (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader);
+
+  return;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h
new file mode 100644
index 0000000000..bb8a04a6f8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity Package Type Definitions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _F15_TN_PACKAGE_TYPE_H_
+#define _F15_TN_PACKAGE_TYPE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+// Below equates are defined to cooperate with LibAmdGetPackageType.
+#define PACKAGE_TYPE_FP2                    (1 << 0)
+#define PACKAGE_TYPE_FS1r2                  (1 << 1)
+#define PACKAGE_TYPE_FM2                    (1 << 2)
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif  // _F15_TN_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
new file mode 100644
index 0000000000..c04ce1e109
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
@@ -0,0 +1,849 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 64462 $   @e \$Date: 2012-01-21 10:59:15 -0600 (Sat, 21 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+SetEnCstateBoostBlockCC6Exit (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+Erratum687Workaround (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15TnPciRegisters[] =
+{
+// F0x68 - Link Transaction Control
+// bits[22:21] DsNpReqLmt = 01b
+// bit [19]    ApicExtSpur = 1
+// bit [18]    ApicExtId = 1
+// bit [17]    ApicExtBrdCst = 1
+// bit [15]    LimitCldtCfg = 1
+// bit [10]    DisFillP = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x002E8000,                           // regData
+      0x006E8400,                           // regMask
+    }}
+  },
+// F0x6C - Link Initialization Control
+// bit[0] RouteTblDis = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
+      0x00000000,                           // regData
+      0x00000001,                           // regMask
+    }}
+  },
+// F0x84 - Link Control
+// bit [12] IsocEn = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x84),  // Address
+      0x00001000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+// F0x90 - Upstream Base Channel Buffer Count
+// bits[27:25] FreeData = 0
+// bits[24:20] FreeCmd = 0
+// bits[19:18] RspData = 1
+// bits[17:16] NpReqData = 1
+// bits[15:12] ProbeCmd = 0
+// bits[11:8]  RspCmd = 2
+// bits[7:5]   PReq = 5
+// bits[4:0]   NpReqCmd = 8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90),  // Address
+      0x000502A8,                           // regData
+      0x0FFFFFFF,                           // regMask
+    }}
+  },
+// F0x94 - Link Isochronous Channel Buffer Count
+// bits[28:27] IsocRspData = 0
+// bits[26:25] IsocNpReqData = 1
+// bits[24:22] IsocRspCmd = 0
+// bits[21:19] IsocpReq = 0
+// bits[18:16] IsocNpReqCmd = 1
+// bits[15:8]  SecBusNum = 0 (F1XE0 [BaseBusNum])
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94),  // Address
+      0x02010000,                           // regData
+      0x1FFFFF00,                           // regMask
+    }}
+  },
+// F1xE0 - Configuration Map
+// bits[31:24] BusNumLimit = F8
+// bits[23:16] BaseBusNum = 0
+// bit [1]     WE = 1
+// bit [0]     RE = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+        MAKE_SBDFO (0, 0, 24, FUNC_1, 0xE0),// Address
+        0xF8000003,                         // regData
+        0xFFFF0003,                         // regMask
+    }}
+  },
+// F3x44 - MCA NB Configuration
+//
+// bit[30] SyncFloodOnDramAdrParErr = 1
+// bit[27] NbMcaToMstCpuEn = 1
+// bit[21] SyncFloodOnAnyUcErr = 1
+// bit[20] SyncFloodOnWDT = 1
+
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
+      0x48300000,                           // regData
+      0x48300000,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[30:28] IsocRspCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[22:20] IsocReqCBC = 1
+// bits[18:16] UpRspCBC = 7
+// bits[14:12] DnPreqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[2:0]   UpReqCBC = 7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x10171157,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[31:28] DRReqCBC = 0
+// bits[26:24] IsocPreqCBC = 1
+// bits[23:20] IsocReqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[14:12] DnPreqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[2:0]   UpReqCBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x01180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[26:23] ExtSrqFreeList = 8
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 5
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[11:8]  Sri2XbarFreeXreqCBC = 0xE
+// bits[4:0]   Xbar2SriFreeListCBC = 18h
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x04050E18,                           // regData
+      0x07FFFF1F,                           // regMask
+    }}
+  },
+// F3x84 - ACPI Power State Control High
+// ACPI State S3
+// bit[1] NbLowPwrEnSmafAct4 = 1
+// bit[7:5] ClkDivisorSmafAct4 = 7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
+      0x000000E2,                           // regData
+      0x000000E2,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bit[14] Svi2HighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_15_TN,                     // CpuFamily
+      AMD_F15_TN_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00004000,                           // regData
+      0x00004000,                           // regMask
+    }}
+  },
+// F3xD4 - Clock Power Timing Control 0
+// bit [31]    NbClkDivApplyAll = 1
+// bits[30:28] NbClkDiv = 4
+// bits[27:24] PowerStepUp = 8
+// bits[23:20] PowerStepDown = 8
+// bit [14]    CacheFlushImmOnAllHalt = 0
+// bit [12]    ClkRampHystCtl = 0
+// bits[11:8]  ClkRampHystSel = 0xF
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0xC8800F00,                           // regData
+      0xFFF05F00,                           // regMask
+    }}
+  },
+// F3xD8 - Clock Power Timing Control 1
+// bits[6:4]   VSRampSlamTime = 100b
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8),  // Address
+      0x00000040,                           // regData
+      0x00000070,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[23:20] FreeTok = 0xA
+// bits[17:16] IsocRspTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[13:12] IsocReqTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[9:8]   UpRspTok = 1
+// bits[7:6]   DnPreqTok = 1
+// bits[5:4]   UpPreqTok = 1
+// bits[3:2]   DnReqTok = 1
+// bits[1:0]   UpReqTok = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A11555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x144 - MCT_to_XCS Token Count
+// bits[7:4] ProbeTok = 7
+// bits[3:0] RspTok = 7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000077,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x148 - Link_to_XCS Token Count
+// bits[31:30] FreeTok[3:2] = FreeTok[1:0] = 0
+// bit [28]    IsocRspTok1 = 0
+// bit [26]    IsocPreqTok1 = 0
+// bit [24]    IsocReqTok1 = 0
+// bits[23:22] ProbeTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[17:16] ReqTok1 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[11:10] IsocPreqTok0 = 1
+// bits[9:8]   IsocReqTok0 = 1
+// bits[7:6]   ProbeTok0 = 0
+// bits[5:4]   RspTok0 = 2
+// bits[3:2]   PReqTok0 = 2
+// bits[1:0]   ReqTok0 = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000052A,                           // regData
+      0xD5FFFFFF                            // regMask
+    }}
+  },
+// F3x17C - Extended Freelist Buffer Count
+// bits[3:0] SPQPrbFreeCBC = 4
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address
+      0x00000004,                           // regData
+      0x0000000F                            // regMask
+    }}
+  },
+// F3x180 - NB Extended Configuration
+// bit[24] McaLogErrAddrWdtErr = 1
+// bit[22] SyncFloodOnTblWalkErr = 1
+// bit[21] SyncFloodOnCpuLeakErr = 1
+// bit[20] SyncFloodOnL3LeakErr = 1
+// bit[9]  SyncFloodOnUCNbAry = 1
+// bit[8]  SyncFloodOnHtProt = 1
+// bit[7]  SyncFloodOnTgtAbortErr = 1
+// bit[6]  SyncFloodOnDatErr = 1
+// bit[5]  DisPciCfgCpuMstAbortRsp = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x017003E0,                           // regData
+      0x017003E0,                           // regMask
+    }}
+  },
+// F3x1A0 - Core to NB Buffer Count
+// bit[17:16] CpuToNbFreeBufCnt = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
+      0x00030000,                           // regData
+      0x00030000,                           // regMask
+    }}
+  },
+// F4x110 - Sample and Residency Timer
+// bits[11:0] CSampleTimer = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address
+      0x00000002,                           // regData
+      0x00000FFF,                           // regMask
+    }}
+  },
+// F4x124 - C-state Interrupt Control
+// bits[26:23] IntMonPC6Limit = 0
+// bit [22]    IntMonPC6En = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
+      0x00400000,                           // regData
+      0x07C00000,                           // regMask
+    }}
+  },
+// F4x16C - Erratum #667
+// bit [1] = 1
+// bit [4] = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address
+      0x00000012,                           // regData
+      0x00000012,                           // regMask
+    }}
+  },
+// F5xAC - Erratum #667
+// bit [3] = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0xAC),  // Address
+      0x00000008,                           // regData
+      0x00000008,                           // regMask
+    }}
+  },
+// F5x88 - Northbridge Configuration 4
+// bit[24] DisHbNpReqBusLock   = 1
+// bit[2]  IntStpClkHaltExitEn = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88),  // Address
+      0x01000004,                           // regData
+      0x01000004,                           // regMask
+    }}
+  },
+// F5xE0 - Processor TDP Running Average
+// bits[3:0] RunAvgRange = 0x2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0),  // Address
+      0x00000002,                           // regData
+      0x0000000F,                           // regMask
+    }}
+  },
+// F5x128 - Clock Power/Timing Control 3
+// bits[13:12] PwrGateTmr = 1
+// bits[11:10] PllVddOutUpTime = 3
+// bit [9]     FastSlamTimeDown = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x128), // Address
+      0x00001E00,                           // regData
+      0x00003E00,                           // regMask
+    }}
+  },
+// F5x12C - Clock Power/Timing Control 4
+// bit [5] CorePsi1En = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x12C), // Address
+      0x00000020,                           // regData
+      0x00000020,                           // regMask
+    }}
+  },
+// F5x178 - Northbridge Fusion Configuration
+// bit [18] CstateFusionHsDis = 1
+// bit [17] Dis2ndGnbAllowPsWait = 1
+// bit [11] AllowSelfRefrS3Dis = 1
+// bit [10] InbWakeS3Dis = 1
+// bit [2]  CstateFusionDis = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x178), // Address
+      0x00060C04,                           // regData
+      0x00060C04,                           // regMask
+    }}
+  },
+// F0x90 - Upstream Base Channel Buffer Count
+// bit [31] LockBc = 1
+//
+// NOTE: The entry is intended to be programmed after other bits of D18F0x[90, 94] is programmed and before D18F0x6C[30] is programmed.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90),  // Address
+      0x80000000,                           // regData
+      0x80000000,                           // regMask
+    }}
+  },
+// F0x6C - Link Initialization Control
+// bit [30] RlsLnkFullTokCntImm = 1
+// bit [28] RlsIntFullTokCntImm = 1
+//
+// NOTE: The entry is intended to be after D18F0x[90, 94] and D18F0x[70, 74, 78, 7C, 140, 144, 148, 17C, 1A0] are programmed.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
+      0x50000000,                           // regData
+      0x50000000,                           // regMask
+    }}
+  },
+// F0x6C - Link Initialization Control
+// bit [27] ApplyIsocModeEnNow = 1
+//
+// NOTE: The entry is intended to be after D18F0x6C[30, 28] are programmed.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
+      0x08000000,                           // regData
+      0x08000000,                           // regMask
+    }}
+  },
+};
+
+
+// PCI with Special Programming Requirements Table
+
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPciWorkarounds[] =
+{
+// D18F5x88
+  {
+    FamSpecificWorkaround,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                        // CpuFamily
+      AMD_F15_TN_GT_A0                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      SetEnCstateBoostBlockCC6Exit,         // function call
+      0x00000000,                           // data
+    }}
+  },
+// D18F5x88 and D18F2x408
+  {
+    FamSpecificWorkaround,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                        // CpuFamily
+      AMD_F15_TN_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      Erratum687Workaround,                 // function call
+      0x00000000,                           // data
+    }}
+  },
+};
+
+
+CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F15TnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F15TnPciRegisters,
+};
+
+
+CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable = {
+  PrimaryCores,
+  (sizeof (F15TnPciWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F15TnPciWorkarounds,
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Workaround for Non-A0 TN processors.
+ *
+ *  AGESA should program F5x88[18] with the fused value from F3x1FC[20] for non-RevA0 parts.
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+SetEnCstateBoostBlockCC6Exit (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR PciAddress;
+  PRODUCT_INFO_REGISTER ProductInfo;
+  NB_CFG_4_REGISTER NbCfg4;
+
+  PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
+
+  PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
+
+  NbCfg4.EnCstateBoostBlockCC6Exit = ProductInfo.EnCstateBoostBlockCC6Exit;
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Workaround for Erratum #687 for TN processors.
+ *
+ *  AGESA should program F5x88[14] with the fused value from F3x1FC[29] and
+ *  program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29]  for all TN parts.
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+Erratum687Workaround (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR                  PciAddress;
+  PRODUCT_INFO_REGISTER     ProductInfo;
+  NB_CFG_4_REGISTER         NbCfg4;
+  GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
+  UINT32                    DctSelCnt;
+  DCT_CFG_SEL_REGISTER      DctCfgSel;
+
+  PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
+
+  PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
+  NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh;
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
+
+  for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
+    PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
+    GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh;
+    LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
+
+    PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
+    DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
+    LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
new file mode 100644
index 0000000000..c9b6b6b04b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
@@ -0,0 +1,195 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Models 0x10 - 0x1F Power Management related initialization table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63692 $   @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuF15TnCoreAfterReset.h"
+#include "cpuF15TnNbAfterReset.h"
+#include "F15TnPowerPlane.h"
+#include "cpuF15TnPowerCheck.h"
+#include "F15TnUtilities.h"
+#include "IdsF15TnAllService.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF15TnSysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*  Family 15h Only Table */
+/* ---------------------- */
+CONST SYS_PM_TBL_STEP ROMDATA CpuF15TnSysPmTableArray[] =
+{
+  IDS_INITIAL_F15_TN_PM_STEP
+
+  // Step 1 - Configure F3x[84:80].  Handled by PCI register table.
+  // Step 2 - Power Plane Initialization
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F15TnPmPwrPlaneInit                               // Function Pointer
+  },
+
+  // Step 3 - Adjust NB VID
+  //   Execute only after cold reset
+  {
+    PM_EXEFLAGS_COLD_ONLY,                            // ExeFlags
+    F15TnNbPstateVidAdjustAfterReset                  // Function Pointer
+  },
+
+  // Step 4 - Disable NB Pstate, if required
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F15TnNbPstateDis                                  // Function Pointer
+  },
+
+  // Step 5 - Core Minimum P-state Transition Sequence After Warm Reset
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F15TnPmCoreAfterReset                             // Function Pointer
+  },
+
+  // Step 6 - NB P-state COF and VID Synchronization After Warm Reset
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F15TnPmNbAfterReset                               // Function Pointer
+  },
+
+  // Step 7 - Power Check
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F15TnPmPwrCheck                                     // Function Pointer
+  },
+
+  IDS_F15_TN_PM_CUSTOM_STEP
+
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate table of steps to perform to initialize the power management
+ *  subsystem.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  SysPmTblPtr              Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF15TnSysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF15TnSysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
+  *SysPmTblPtr = CpuF15TnSysPmTableArray;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
new file mode 100644
index 0000000000..dbf0ab9626
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
@@ -0,0 +1,207 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Models 0x10 - 0x1F Power Plane Initialization
+ *
+ * Performs the "BIOS Requirements for Power Plane Initialization" as described
+ * in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Table.h"
+#include "F15TnPowerPlane.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Register encodings for D18F3xD8[VSRampSlamTime]
+STATIC CONST UINT32 ROMDATA F15TnVSRampSlamWaitTimes[8] =
+{
+  500,    // 000b: 5.00us
+  375,    // 001b: 3.75us
+  300,    // 010b: 3.00us
+  240,    // 011b: 2.40us
+  200,    // 100b: 2.00us
+  150,    // 101b: 1.50us
+  120,    // 110b: 1.20us
+  100     // 111b: 1.00us
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 15h core 0 entry point for performing power plane initialization.
+ *
+ * The steps are as follows:
+ *    1. Configure D18F3xD8[VSRampSlamTime] based on platform
+ *       requirements.
+ *    2. Configure F3xD4[PowerStepUp & PowerStepDown]
+ *    3. Optionally configure F3xA0[PsiVidEn & PsiVid]
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F15TnPmPwrPlaneInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PCI_ADDR              PciAddress;
+  UINT32                SystemSlewRate;
+  UINT32                WaitTime;
+  UINT32                VSRampSlamTime;
+  UINT32                LocalPciRegister;
+  CLK_PWR_TIMING_CTRL1_REGISTER   ClkPwrTimingCtrl1;
+  BOOLEAN               SkipPowerPlan;
+
+
+  SkipPowerPlan = FALSE;
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_POWER_PLAN_INIT, &SkipPowerPlan, StdHeader);
+  if (!SkipPowerPlan) {
+    // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
+    // Voltage Ramp Time = maximum time to change voltage by 15mV rounded to the next higher encoding.
+    SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
+                      CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
+                      CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
+                      CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
+
+    ASSERT (SystemSlewRate != 0);
+
+    // First, calculate the time it takes to change 15mV using the VRM slew rate.
+    WaitTime = (15000 * 100) / SystemSlewRate;
+    if (((15000 * 100) % SystemSlewRate) != 0) {
+      WaitTime++;
+    }
+
+    // Next, round it to the appropriate encoded value.  We will start from encoding 111b which corresponds
+    // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
+    // VRM can be.
+    for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
+      if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) {
+        break;
+      }
+    }
+
+    if (WaitTime > F15TnVSRampSlamWaitTimes[0]) {
+      // The VRMs on this motherboard are too slow for this CPU.
+      IDS_ERROR_TRAP;
+    }
+
+    // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
+    PciAddress.AddressValue = CPTC1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader);
+    ClkPwrTimingCtrl1.VSRampSlamTime = VSRampSlamTime;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader);
+
+    // Configure PowerStepUp/PowerStepDown
+    PciAddress.AddressValue = CPTC0_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp = 8;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown = 8;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  }
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h
new file mode 100644
index 0000000000..df17667925
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h
@@ -0,0 +1,103 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Models 0x10 - 0x1F Power Plane related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _F15_TN_POWER_PLANE_H_
+#define _F15_TN_POWER_PLANE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F15TnPmPwrPlaneInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _F15_TN_POWER_PLANE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
new file mode 100644
index 0000000000..b603800ced
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
@@ -0,0 +1,415 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity Shared MSR table with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 64491 $   @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+F15TnFpCfgInit (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+STATIC
+Update800MHzHtcPstateTo900MHz (
+  IN       UINT32             Data,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_TOM2 (0xC001001D)
+// bits[63:0] TOP_MEM2 = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_TOM2,                           // MSR Address - Shared
+      0x0000000000000000,                 // OR Mask
+      0xFFFFFFFFFFFFFFFF,                 // NAND Mask
+    }}
+  },
+
+// MSR_SYS_CFG (0xC0010010)
+// bit[21] MtrrTom2En = 1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_SYS_CFG,                        // MSR Address - Shared
+      (1 << 21),                          // OR Mask
+      (1 << 21),                          // NAND Mask
+    }}
+  },
+
+// MSR_IC_CFG (0xC0011021)
+// bit[39] DisLoopPredictor = 1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_IC_CFG,                         // MSR Address - Shared
+      (1ull << 39),                       // OR Mask
+      (1ull << 39),                       // NAND Mask
+    }}
+  },
+
+// MSR_CU_CFG (0xC0011023)
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_CU_CFG,                         // MSR Address - Shared
+      0,                                  // OR Mask
+      0x00000400,                         // NAND Mask
+    }}
+  },
+
+// MSR_CU_CFG2 (0xC001102A)
+// bit[50] RdMmExtCfgQwEn = 1
+// bit[10] VicResyncChkEn = 1
+
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_CU_CFG2,                        // MSR Address - Shared
+      0x0004000000000400,                 // OR Mask
+      0x0004000000000400,                 // NAND Mask
+    }}
+  },
+// MSR_CU_CFG3 (0xC001102B)
+// bit[42] PwcDisableWalkerSharing = 0
+// bit[22] PfcDoubleStride = 1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_CU_CFG3,                        // MSR Address
+      0x0000000000400000,                 // OR Mask
+      0x0000040000400000,                 // NAND Mask
+    }}
+  },
+};
+
+
+// Compute Unit Count Dependent MSR Table
+
+STATIC CONST MSR_CU_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrCuRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+  // MSR_CU_CFG2 (0xC001102A)
+  // bits[37:36] - ThrottleNbInterface[3:2] = 0
+  // bits[7:6] - ThrottleNbInterface[1:0] = 0
+  {
+    CompUnitCountsMsr,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      {(COMPUTE_UNIT_RANGE_0 (1, 1) | COUNT_RANGE_NONE)}, // 1 compute unit
+      {
+        MSR_CU_CFG2,                      // MSR Address - Shared
+        0x0000000000000000,               // OR Mask
+        0x00000030000000C0,               // NAND Mask
+      }
+    }}
+  },
+
+  // MSR_CU_CFG2 (0xC001102A)
+  // bits[37:36] - ThrottleNbInterface[3:2] = 0
+  // bits[7:6] - ThrottleNbInterface[1:0] = 1
+  {
+    CompUnitCountsMsr,
+    {
+      AMD_FAMILY_15_TN,                   // CpuFamily
+      AMD_F15_TN_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      {(COMPUTE_UNIT_RANGE_0 (2, 2) | COUNT_RANGE_NONE)}, // 2 compute units
+      {
+        MSR_CU_CFG2,                      // MSR Address - Shared
+        0x0000000000000040,               // OR Mask
+        0x00000030000000C0,               // NAND Mask
+      }
+    }}
+  }
+
+};
+
+
+// Shared MSRs with Special Programming Requirements Table
+
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrWorkarounds[] =
+{
+  // MSR_FP_CFG (0xC0011028)
+  // bit[16] -     DiDtMode = F3x1FC[0]
+  // bits[22:18] - DiDtCfg0 = F3x1FC[5:1]
+  // bits[34:27] - DiDtCfg1 = F3x1FC[13:6]
+  // bits[26:25] - DiDtCfg2 = F3x1FC[15:14]
+  // bits[44:42] - DiDtCfg4 = F3x1FC[19:17]
+  {
+    FamSpecificWorkaround,
+    {
+      AMD_FAMILY_15_TN,
+      AMD_F15_TN_ALL
+    },
+    {AMD_PF_ALL},
+    {{
+      F15TnFpCfgInit,
+      0x00000000
+    }}
+  },
+};
+
+
+CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable = {
+  CorePairPrimary,
+  (sizeof (F15TnSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrRegisters,
+};
+
+
+CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable = {
+  CorePairPrimary,
+  (sizeof (F15TnSharedMsrCuRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrCuRegisters,
+};
+
+CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable = {
+  CorePairPrimary,
+  (sizeof (F15TnSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrWorkarounds,
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Update the FP_CFG MSR in current processor for Family15h TN.
+ *
+ * This function satisfies the programming requirements for the FP_CFG MSR.
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+F15TnFpCfgInit (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32       ProductInfo;
+  UINT64       FpCfg;
+  PCI_ADDR     PciAddress;
+
+  PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader);
+
+  LibAmdMsrRead (MSR_FP_CFG, &FpCfg, StdHeader);
+  ((FP_CFG_MSR *) &FpCfg)->DiDtMode = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtMode;
+  ((FP_CFG_MSR *) &FpCfg)->DiDtCfg0 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg0;
+  ((FP_CFG_MSR *) &FpCfg)->DiDtCfg1 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg1;
+  ((FP_CFG_MSR *) &FpCfg)->DiDtCfg2 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg2;
+  ((FP_CFG_MSR *) &FpCfg)->DiDtCfg4 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg4;
+  ((FP_CFG_MSR *) &FpCfg)->DiDtCfg5 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg5;
+  LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader);
+}
+
+
+// Per-Node MSR with Special Programming Requirements Table
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPerNodeMsrWorkarounds[] =
+{
+// MSR C001_00[6B:64]
+  {
+    FamSpecificWorkaround,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                        // CpuFamily
+      AMD_F15_TN_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      Update800MHzHtcPstateTo900MHz,         // function call
+      0x00000000,                           // data
+    }}
+  }
+};
+
+
+CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable = {
+  PrimaryCores,
+  (sizeof (F15TnPerNodeMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F15TnPerNodeMsrWorkarounds,
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Workaround for CPUs with a minimum P-state = 800MHz.
+ *
+ *  AGESA should change the frequency of 800MHz P-states to 900MHz.
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+Update800MHzHtcPstateTo900MHz (
+  IN       UINT32             Data,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  PCI_ADDR      PciAddress;
+  PSTATE_MSR    HtcPstate;
+  PSTATE_MSR    HtcPstateMinus1;
+  HTC_REGISTER  HtcRegister;
+
+  PciAddress.AddressValue = HTC_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &HtcRegister, StdHeader);
+
+  LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);
+
+  if (HtcPstate.CpuFid == 0 && HtcPstate.CpuDid == 1) {
+    if (HtcRegister.HtcPstateLimit == 0) {
+      HtcPstateMinus1 = HtcPstate;
+    } else {
+      LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0 - 1), (UINT64 *) &HtcPstateMinus1, StdHeader);
+    }
+    HtcPstate.CpuVid = HtcPstateMinus1.CpuVid;
+    HtcPstate.CpuFid = 2;
+    LibAmdMsrWrite ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
new file mode 100644
index 0000000000..022d1b4f7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
@@ -0,0 +1,1031 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 models 10h - 1Fh specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 15h TN.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 65284 $   @e \$Date: 2012-02-12 23:29:39 -0600 (Sun, 12 Feb 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "F15TnUtilities.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+F15TnNbPstateDisCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F15TnGetNbFreqNumeratorInMHz (
+  IN       UINT32                NbFid,
+     OUT   UINT32                *FreqNumeratorInMHz,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+F15TnGetNbFreqDivisor (
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FreqDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+STATIC
+F15TnCalculateNbFrequencyInMHz (
+  IN       UINT32                NbFid,
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F15TnCovertVidInuV (
+  IN       UINT32                Vid,
+     OUT   UINT32                *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+F15TnCmnGetIddDivisor (
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *IddDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+F15TnCmnCalculateCurrentInmA (
+  IN       UINT32                IddValue,
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *CurrentInmA,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+BOOLEAN
+F15TnSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F15TnGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       MsrAddress;
+  PSTATE_MSR   PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+  NB_CAPS_2_REGISTER  NbCap2;
+  UINT32       ProcIddMaxPerCore;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetProcIddMax - P%d\n", Pstate);
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, (UINT64 *) &PstateMsr, StdHeader);
+  F15TnCmnCalculateCurrentInmA ((UINT32) PstateMsr.IddValue, (UINT32) PstateMsr.IddDiv, &ProcIddMaxPerCore, StdHeader);
+  PciAddress.AddressValue = NB_CAPS_REG2_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbCap2, StdHeader);
+  *ProcIddMax = (UINT32) ProcIddMaxPerCore * (NbCap2.CmpCap + 1);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Pstate %d ProcIddMax %d CmpCap %d\n", Pstate, *ProcIddMax, NbCap2.CmpCap);
+  if (PstateMsr.PsEnable == 1) {
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on Trinity
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   CoreLevelMode            Core level mode.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ * @retval      TRUE                     Down Core register is updated.
+ * @retval      FALSE                    Down Core register is not updated.
+ */
+BOOLEAN
+F15TnSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    LocalPciRegister;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   IsUpdated;
+  AGESA_STATUS AgesaStatus;
+
+  IsUpdated = FALSE;
+  CoreDisableBits = 0;
+
+  if (CoreLevelMode == CORE_LEVEL_COMPUTE_UNIT) {
+    // CoreLevelMode == CORE_LVEL_COMPUTE_UNIT is not supported.
+  } else {
+    switch (*LeveledCores) {
+    // Only down core to 2 cores will take effect through a warm reset.
+    case 2:
+      CoreDisableBits = DOWNCORE_MASK_DUAL;
+      break;
+    }
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_5;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LocalPciRegister = (LocalPciRegister & 0xFF) + 1;
+      LocalPciRegister = (1 << LocalPciRegister) - 1;
+      CoreDisableBits &= LocalPciRegister;
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      if ((LocalPciRegister | CoreDisableBits) != LocalPciRegister) {
+        LocalPciRegister |= CoreDisableBits;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+        IsUpdated = TRUE;
+      }
+    }
+  }
+
+  return IsUpdated;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling =
+{
+  0,
+  F15TnSetDownCoreRegister
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ *  @return      AGESA_SUCCESS            FrequencyInMHz is valid.
+ */
+AGESA_STATUS
+F15TnGetCurrentNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  NB_PSTATE_STS_REGISTER NbPstateStsReg;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS ReturnCode;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetCurrentNbFrequency\n");
+
+  PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateStsReg, StdHeader);
+  ReturnCode = F15TnCalculateNbFrequencyInMHz (
+                 NbPstateStsReg.CurNbFid,
+                 NbPstateStsReg.CurNbDid,
+                 FrequencyInMHz,
+                 StdHeader
+                 );
+  return ReturnCode;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the node's minimum and maximum northbridge frequency.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[out]    MinFreqInMHz            The node's minimum northbridge frequency.
+ *  @param[out]    MaxFreqInMHz            The node's maximum northbridge frequency.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        AGESA_SUCCESS           Northbridge frequency is valid
+ */
+AGESA_STATUS
+F15TnGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *MinFreqInMHz,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  INT8         NbPsMaxVal;
+  UINT8        i;
+  UINT32       LocalPciRegister;
+  AGESA_STATUS AgesaStatus;
+
+  AgesaStatus = AGESA_ERROR;
+
+  // Obtain the max NB frequency on the node
+  PciAddress->Address.Function = FUNC_5;
+  PciAddress->Address.Register = NB_PSTATE_CTRL;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+  NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal;
+
+  // Starting from NB Pmax
+  for (i = 0; i <= NbPsMaxVal; i++) {
+    PciAddress->Address.Function = FUNC_5;
+    PciAddress->Address.Register = (NB_PSTATE_0 + (4 * i));
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+
+    // Ensure that the NB Pstate is enabled
+    if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) {
+      AgesaStatus = F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid,
+                                                    ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid,
+                                                    MaxFreqInMHz,
+                                                    StdHeader);
+      break;
+    }
+  }
+  // If all of NbPstates are disabled, get MaxFreqInMHz from CurNbPstate
+  if (i > NbPsMaxVal) {
+    PciAddress->Address.Register = NB_PSTATE_STATUS;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+    F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid,
+                                      ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid,
+                                      MaxFreqInMHz,
+                                      StdHeader);
+    // No one NbPstate is enabled, so set Min = Max
+    *MinFreqInMHz = *MaxFreqInMHz;
+    ASSERT (FALSE);
+  } else {
+    // If platform configuration disable NB P-states, return the NB P0 frequency
+    // as both the min and max frequency on the node.
+    if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) {
+      *MinFreqInMHz = *MaxFreqInMHz;
+    } else {
+      PciAddress->Address.Function = FUNC_5;
+      PciAddress->Address.Register = NB_PSTATE_CTRL;
+      LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+      NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal;
+
+      // Obtain the min NB frequency on the node, starting from NB Pmin
+      for (/* NbPsMaxVal */; NbPsMaxVal >= 0; NbPsMaxVal--) {
+        PciAddress->Address.Function = FUNC_5;
+        PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPsMaxVal));
+        LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+
+        // Ensure that the NB Pstate is enabled
+        if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) {
+          AgesaStatus = F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid,
+                                                        ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid,
+                                                        MinFreqInMHz,
+                                                        StdHeader);
+          break;
+        }
+      }
+    }
+  }
+  IDS_OPTION_HOOK (IDS_NBPS_MIN_FREQ, MinFreqInMHz, StdHeader);
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[in]     NbPstate                The NB P-state number to check.
+ *  @param[out]    FreqNumeratorInMHz      The desired node's frequency numerator in megahertz.
+ *  @param[out]    FreqDivisor             The desired node's frequency divisor.
+ *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    NbPstate is valid
+ *  @retval        FALSE                   NbPstate is disabled or invalid
+ */
+BOOLEAN
+F15TnGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   NbVid;
+  BOOLEAN  PstateIsValid;
+  NB_PSTATE_CTRL_REGISTER   NbPstateCtrlReg;
+  NB_PSTATE_REGISTER        NbPstateReg;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetNbPstateInfo - NB P%d\n", NbPstate);
+
+  ASSERT ((PciAddress->Address.Segment == 0) && (PciAddress->Address.Bus == 0) && (PciAddress->Address.Device == 0x18));
+
+  PstateIsValid = FALSE;
+
+  // If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled
+  if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) {
+    PciAddress->AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateCtrlReg, StdHeader);
+
+    ASSERT ((NbPstate < NM_NB_PS_REG) && (NbPstateCtrlReg.NbPstateMaxVal < NM_NB_PS_REG));
+    if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) {
+      PciAddress->Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
+      LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateReg, StdHeader);
+      IDS_HDT_CONSOLE (CPU_TRACE, "    En:%d Fid:%x Did:%x Vid:%x\n", NbPstateReg.NbPstateEn, NbPstateReg.NbFid, NbPstateReg.NbDid, GetF15TnNbVid (&NbPstateReg));
+
+      // Check if at least NB P0 is enabled.
+      ASSERT ((NbPstate == 0) ? (NbPstateReg.NbPstateEn == 1) : TRUE);
+      // Ensure that requested NbPstate is enabled
+      if (NbPstateReg.NbPstateEn == 1) {
+        // Check for P-state Bandwidth Requirements on
+        // "All NB P-states must be defined such that D18F5x1[6C:60][NbFid] <= 2Eh"
+        ASSERT (NbPstateReg.NbFid <= 0x2E);
+        F15TnGetNbFreqNumeratorInMHz (NbPstateReg.NbFid, FreqNumeratorInMHz, StdHeader);
+        F15TnGetNbFreqDivisor (NbPstateReg.NbDid, FreqDivisor, StdHeader);
+        // Check for P-state Bandwidth Requirements on
+        // "NBCOF >= 700MHz"
+        ASSERT ((*FreqNumeratorInMHz / *FreqDivisor) >= 700);
+
+        NbVid = GetF15TnNbVid (&NbPstateReg);
+        F15TnCovertVidInuV  (NbVid, VoltageInuV, StdHeader);
+        PstateIsValid = TRUE;
+        IDS_HDT_CONSOLE (CPU_TRACE, "    NB Pstate %d is Valid. NbVid=%d VoltageInuV=%d\n", NbPstate, NbVid, *VoltageInuV);
+      }
+    }
+  }
+  return PstateIsValid;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get NB pstate current.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_IDD_MAX}.
+ *
+ *    This function returns the NbIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     NbPstate                  The NB P-state to check.
+ *  @param[out]    NbIddMax                  NB P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      NB P-state is enabled, and NbIddMax is valid.
+ *  @retval        FALSE                     NB P-state is disabled
+ */
+BOOLEAN
+F15TnGetNbIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  NbPstate,
+     OUT   UINT32                 *NbIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN      IsNbPsEnabled;
+  PCI_ADDR     PciAddress;
+  NB_PSTATE_CTRL_REGISTER   NbPstateCtrlReg;
+  NB_PSTATE_REGISTER        NbPstateReg;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetNbIddMax - NB P%d\n", NbPstate);
+
+  IsNbPsEnabled = FALSE;
+
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateCtrlReg, StdHeader);
+
+  ASSERT (NbPstate < NM_NB_PS_REG);
+  if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) {
+    PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader);
+
+    // Ensure that requested NbPstate is enabled
+    if (NbPstateReg.NbPstateEn == 1) {
+      F15TnCmnCalculateCurrentInmA (NbPstateReg.NbIddValue, NbPstateReg.NbIddDiv, NbIddMax, StdHeader);
+      IsNbPsEnabled = TRUE;
+      IDS_HDT_CONSOLE (CPU_TRACE, "  NB Pstate %d is Valid. NbIddMax %d\n", NbPstate, *NbIddMax);
+    }
+  }
+  return IsNbPsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the number of physical cores of current processor.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of physical cores.
+ */
+UINT8
+F15TnGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPUID_DATA    CpuId;
+
+  //
+  //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc.
+  //
+  LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader);
+  return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Use the Mailbox Register to get the Ap Mailbox info for the current core.
+ *
+ *  @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
+ *
+ *  Access the mailbox register used with this NB family.  This is valid until the
+ *  point that some init code initializes the mailbox register for its normal use.
+ *  The Machine Check Misc (Thresholding) register is available as both a PCI config
+ *  register and a MSR, so it can be used as a mailbox from HT to other functions.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    ApMailboxInfo           The AP Mailbox info
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F15TnGetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  // For Family 15h Trinity, we will return socket 0, node 0, module 0, module type 0, and 0 for
+  // the system degree
+  ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000;
+  ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get this AP's system core number from hardware.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
+ *
+ *  Returns the system core number from the scratch MSR, where
+ *  it was saved at heap initialization.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+UINT32
+F15TnGetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPUID_DATA Cpuid;
+
+  LibAmdCpuidRead (0x1, &Cpuid, StdHeader);
+  return ((Cpuid.EBX_Reg >> 24) & 0xFF);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      PlatformConfig                 Platform profile/build option config structure.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F15TnIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR PciAddress;
+  BOOLEAN  PowerMode;
+  BOOLEAN  SkipHwCfg;
+  NB_PSTATE_STS_REGISTER   NbPstateSts;
+  NB_PSTATE_CTRL_REGISTER  NbPstateCtrl;
+
+
+  PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateSts, StdHeader);
+  if (NbPstateSts.NbPstateDis == 1) {
+    return FALSE;
+  }
+
+  SkipHwCfg = FALSE;
+  IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader);
+  if (!SkipHwCfg) {
+  }
+
+  // Defaults to Power Optimized Mode
+  PowerMode = TRUE;
+
+  // If system is optimized for performance, disable NB P-States
+  if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) {
+    PowerMode = FALSE;
+  }
+
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateCtrl, StdHeader);
+  if (((NbPstateCtrl.NbPstateMaxVal != 0) || SkipHwCfg) && (PowerMode)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Disable NB P-state.
+ *   - clear F5x1[6C:64]
+ *   - clear F5x170[NbPstateMaxVal]
+ *   - set   F5x170[SwNbPstateLoDis]
+ *   - clear MSRC001_00[6B:64][NbPstate]
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services
+ * @param[in]     CpuEarlyParamsPtr       Service Parameters
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+F15TnNbPstateDis (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       i;
+  UINT32       PciData;
+  UINT32       NbPsCtrl;
+  UINT32       NbPsCtrlOrg;
+  UINT32       AndMask;
+  BOOLEAN      SkipNbPsLoPart;
+  AP_TASK      TaskPtr;
+  PCI_ADDR     PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnNbPstateDis\n");
+
+  // Check whether NB P-state is disabled
+  if (!FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "  NB Pstates disabled\n");
+
+    PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    NbPsCtrlOrg = NbPsCtrl;
+
+    AndMask = 0x00000000;
+    // If CurNbPstate is not NB P0, get the Pstate pointed to by CurNbPstate and copy it's value to NB P0 to P3 and clear NbPstateHi
+    PciAddress.Address.Register = NB_PSTATE_STATUS;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+    SkipNbPsLoPart = FALSE;
+
+    if (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0) {
+      PciAddress.Address.Register = NB_PSTATE_0 + (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate * 4);
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+      for (i = 1; i < NM_NB_PS_REG; i++) {
+        PciAddress.Address.Register = NB_PSTATE_0 + (i * 4);
+        OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader);
+      }
+
+      if (!SkipNbPsLoPart) {
+        // Program D18F5x170 to transition the NB P-state:
+        // 1) NbPstateLo = NbPstateMaxVal.
+        // 2) SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0.
+
+        PciAddress.Address.Register = NB_PSTATE_CTRL;
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 0;
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateDisOnP0 = 0;
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateThreshold = 0;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+        // Wait for D18F5x174[CurNbPstate] to equal NbPstateLo.
+        PciAddress.Address.Register = NB_PSTATE_STATUS;
+        do {
+          LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+        } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo);
+      }
+    }
+
+    // Program D18F5x170 to force the NB P-state:
+    // 1) NbPstateHi = target NB P-state.
+    // 2) SwNbPstateLoDis = 1
+    // And clear F5x170[NbPstateMaxVal]
+    PciAddress.Address.Register = NB_PSTATE_CTRL;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi = 0;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+    // Wait for D18F5x174[CurNbPstate] to equal the target NB P-state.
+    PciAddress.Address.Register = NB_PSTATE_STATUS;
+    do {
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0);
+
+    // Clear F5x1[6C:64]
+    AndMask = 0x00000000;
+    for (i = 1; i < NM_NB_PS_REG; i++) {
+      PciAddress.Address.Register = NB_PSTATE_0 + (i * 4);
+      OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, AndMask, StdHeader);
+    }
+
+    // Clear MSRC001_00[6B:64][NbPstate] on cores
+    TaskPtr.FuncAddress.PfApTask = F15TnNbPstateDisCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.DataTransfer.DataPtr = NULL;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+
+    // BIOS performs the following to release the NB P-state force:
+    // 1. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateLo] values.
+    // 2. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values.
+    PciAddress.Address.Register = NB_PSTATE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateLo = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->SwNbPstateLoDis;
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateDisOnP0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi = 0;
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateMaxVal = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateThreshold;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Disable NB P-state on core.
+ *   - clear MSRC001_00[6B:64][NbPstate].
+ *
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F15TnNbPstateDisCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 i;
+  UINT64 MsrData;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnNbPstateDisCore\n");
+
+  // Only one core per compute unit needs to clear NbPstate in P-state MSRs
+  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    for (i = MSR_PSTATE_0; i <= MSR_PSTATE_7; i++) {
+      LibAmdMsrRead (i, &MsrData, StdHeader);
+      ((PSTATE_MSR *) &MsrData)->NbPstate = 0;
+      LibAmdMsrWrite (i, &MsrData, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get NB Frequency Numerator in MHz
+ *
+ * @param[in]     NbFid                   NB Frequency ID to convert
+ * @param[out]    FreqNumeratorInMHz      The desire NB FID's frequency numerator in megahertz.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F15TnGetNbFreqNumeratorInMHz (
+  IN       UINT32                NbFid,
+     OUT   UINT32                *FreqNumeratorInMHz,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetNbFreqNumeratorInMHz - NbFid=%d\n", NbFid);
+  *FreqNumeratorInMHz = (NbFid + 4) * 100;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FreqNumeratorInMHz=%d\n", *FreqNumeratorInMHz);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get NB Frequency Divisor
+ *
+ * @param[in]     NbDid                   NB Divisor ID to convert.
+ * @param[out]    FreqDivisor             The desire NB DID's frequency divisor.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F15TnGetNbFreqDivisor (
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FreqDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetNbFreqDivisor - NbDid=%d\n", NbDid);
+  *FreqDivisor = (1 << NbDid);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FreqDivisor=%d\n", *FreqDivisor);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate NB Frequency in MHz
+ *
+ * @param[in]     NbFid                   NB Frequency ID to convert
+ * @param[in]     NbDid                   NB Divisor ID to convert.
+ * @param[out]    FrequencyInMHz          The Northbridge clock frequency in megahertz.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @return        AGESA_SUCCESS           FrequencyInMHz is valid.
+ */
+AGESA_STATUS
+STATIC
+F15TnCalculateNbFrequencyInMHz (
+  IN       UINT32                NbFid,
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32        FreqNumeratorInMHz;
+  UINT32        FreqDivisor;
+  AGESA_STATUS  ReturnStatus;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnCalculateNbFrequencyInMHz - NbFid=%x, NbDid=%x\n", NbFid, NbDid);
+
+  ReturnStatus = AGESA_SUCCESS;
+  F15TnGetNbFreqNumeratorInMHz (NbFid, &FreqNumeratorInMHz, StdHeader);
+  F15TnGetNbFreqDivisor (NbDid, &FreqDivisor, StdHeader);
+  *FrequencyInMHz = FreqNumeratorInMHz / FreqDivisor;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FrequencyInMHz=%d\n", *FrequencyInMHz);
+
+  return ReturnStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Convert VID to microvolts(uV)
+ *
+ * @param[in]     Vid                     The voltage ID of SVI2 encoding to be converted.
+ * @param[out]    VoltageInuV             The voltage in microvolts.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F15TnCovertVidInuV (
+  IN       UINT32                Vid,
+     OUT   UINT32                *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnCovertVidInuV\n");
+  // Maximum 1.55V, 6.25mV per stpe
+  *VoltageInuV = ConvertVidInuV(Vid);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Vid=%x, VoltageInuV=%d\n", Vid, *VoltageInuV);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get Core/NB Idd Divisor
+ *
+ * @param[in]     IddDiv                  Core/NB current divisor to convert.
+ * @param[out]    IddDivisor              The desire Core/NB current divisor.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+STATIC
+F15TnCmnGetIddDivisor (
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *IddDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnCmnGetIddDivisor - IddDiv=%d\n", IddDiv);
+
+  switch (IddDiv) {
+  case 0:
+    *IddDivisor = 1000;
+    break;
+  case 1:
+    *IddDivisor = 100;
+    break;
+  case 2:
+    *IddDivisor = 10;
+    break;
+  default:  // IddDiv = 3 is reserved. Use 10
+    *IddDivisor = 10;
+    ASSERT (FALSE);
+    break;
+  }
+  IDS_HDT_CONSOLE (CPU_TRACE, "    IddDivisor=%d\n", *IddDivisor);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate Core/NB current in mA
+ *
+ * @param[in]     IddValue                Core/NB current value.
+ * @param[in]     IddDiv                  Core/NB current divisor.
+ * @param[out]    CurrentInmA             The Core/NB current in milliampere.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+STATIC
+F15TnCmnCalculateCurrentInmA (
+  IN       UINT32                IddValue,
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *CurrentInmA,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32        IddDivisor;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnCmnCalculateCurrentInmA - IddValue=%x, IddDiv=%x\n", IddValue, IddDiv);
+
+  F15TnCmnGetIddDivisor (IddDiv, &IddDivisor, StdHeader);
+  *CurrentInmA = IddValue * IddDivisor;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    CurrentInmA=%d\n", *CurrentInmA);
+}
+
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h
new file mode 100644
index 0000000000..1b971fb8b8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h
@@ -0,0 +1,177 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 15h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _F15_TN_UTILITES_H_
+#define _F15_TN_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT8
+F15TnGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F15TnGetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F15TnIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F15TnNbPstateDis (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+BOOLEAN
+F15TnGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F15TnGetNbIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  NbPstate,
+     OUT   UINT32                 *NbIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetCurrentNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *MinFreqInMHz,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F15TnGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+F15TnGetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
new file mode 100644
index 0000000000..2235eedd2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
@@ -0,0 +1,191 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function for Family 15h Trinity.
+ *
+ * Contains code to initialize Cache Flush On Halt feature for Family 15h Trinity.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+SetF15TnCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in]       EntryPoint               Timepoint designator.
+ *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
+ *    @param[in]       StdHeader                Config Handle for library, services.
+ */
+VOID
+SetF15TnCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  PCI_ADDR                              PciAddress;
+  CLK_PWR_TIMING_CTRL2_REGISTER         ClkPwrTimingCtrl2;
+  CSTATE_POLICY_CTRL1_REGISTER          CstatePolicyCtrl1;
+  CSTATE_CTRL1_REGISTER                 CstateCtrl1;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    // Set D18F3xDC[CacheFlushOnHaltCtl] != 0
+    // Set D18F3xDC[CacheFlushOnHaltTmr]
+    PciAddress.AddressValue = CPTC2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+    ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7;
+    ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x14;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+
+    // Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold]
+    PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
+    CstatePolicyCtrl1.CacheFlushTmr = 0x14;
+    CstatePolicyCtrl1.CacheFlushSucMonThreshold = 7;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
+
+    // Set cache flush bits in D18F4x118
+    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+    // Set C-state Action Field 0
+    CstateCtrl1.CacheFlushEnCstAct0 = 1;
+    CstateCtrl1.CacheFlushTmrSelCstAct0 = 2;
+    CstateCtrl1.ClkDivisorCstAct0 = 0;
+    // Set C-state Action Field 1
+    CstateCtrl1.CacheFlushEnCstAct1 = 1;
+    CstateCtrl1.CacheFlushTmrSelCstAct1 = 1;
+    CstateCtrl1.ClkDivisorCstAct1 = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+
+    //Override the default setting
+    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt =
+{
+  0,
+  SetF15TnCacheFlushOnHaltRegister
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
new file mode 100644
index 0000000000..64e82ef434
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
@@ -0,0 +1,280 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity after warm reset sequence for core P-states
+ *
+ * Performs the "Core Minimum P-State Transition Sequence After Warm Reset"
+ * as described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMultiSocket.h"
+#include "cpuF15TnCoreAfterReset.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F15TnPmCoreAfterResetPhase1OnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F15TnPmCoreAfterResetPhase2OnCore (
+  IN       VOID              *HwPsMaxVal,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 15h Trinity core 0 entry point for performing the necessary steps for core
+ * P-states after a warm reset has occurred.
+ *
+ * The steps are as follows:
+ *    1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
+ *    2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+ *       MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
+ *    3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
+ *       cores in the processor.
+ *    4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+ *       MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal].
+ *    5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
+ *       MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
+ *       MSRC001_0061[PstateMaxVal].
+ *    6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F15TnPmCoreAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32       Core;
+  UINT32       HwPsMaxVal;
+  PCI_ADDR     PciAddress;
+  AP_TASK      TaskPtr;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnPmCoreAfterReset\n");
+
+  GetCurrentCore (&Core, StdHeader);
+  ASSERT (Core == 0);
+
+  OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = CPTC2_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
+  HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal;
+
+  // Launch each local core to perform steps 1 through 3.
+  TaskPtr.FuncAddress.PfApTask = F15TnPmCoreAfterResetPhase1OnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+  // Launch each local core to perform steps 4 through 6.
+  TaskPtr.FuncAddress.PfApTaskI = F15TnPmCoreAfterResetPhase2OnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 1;
+  TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all
+ * cores of a family 15h socket.
+ *
+ * This function implements steps 1 - 3 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F15TnPmCoreAfterResetPhase1OnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 CofvidSts;
+  UINT64 LocalMsrRegister;
+  UINT64 PstateCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnPmCoreAfterResetPhase1OnCore\n");
+
+  // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
+  PstateCtrl = 0;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
+
+  // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+  //    MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
+  do {
+    LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
+    LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader);
+  } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) ||
+           (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid));
+
+  // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
+  //    cores in the processor.
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+  ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all
+ * cores of a family 15h socket.
+ *
+ * This function implements steps 4 - 6 on each core.
+ *
+ * @param[in]  HwPsMaxVal         Index of the highest enabled HW P-state.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F15TnPmCoreAfterResetPhase2OnCore (
+  IN       VOID              *HwPsMaxVal,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 TargetPsMsr;
+  UINT64 LocalMsrRegister;
+  UINT64 PstateCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnPmCoreAfterResetPhase2OnCore\n");
+
+  // 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+  //    MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal].
+  LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader);
+  do {
+    LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+  } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
+           (((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
+
+  // 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
+  //    MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
+  //    MSRC001_0061[PstateMaxVal].
+  if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) {
+    do {
+      LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+    } while (GetF15TnCurCpuVid (&LocalMsrRegister) != GetF15TnCpuVid (&TargetPsMsr));
+  }
+
+  // 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
+  LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
+  do {
+    LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+  } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h
new file mode 100644
index 0000000000..1e5b1ba3a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity after warm reset sequence for core P-states
+ *
+ * Contains code that provide power management functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_TN_CORE_AFTER_RESET_H_
+#define _CPU_F15_TN_CORE_AFTER_RESET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F15TnPmCoreAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F15_TN_CORE_AFTER_RESET_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
new file mode 100644
index 0000000000..e0240bdeb6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
@@ -0,0 +1,430 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions for Family15h Trinity.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 64351 $   @e \$Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuLateInit.h"
+#include "cpuF15Dmi.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST CHAR8 ROMDATA str_A10[] = "AMD A10-";
+CONST CHAR8 ROMDATA str_A8[] = "AMD A8-";
+CONST CHAR8 ROMDATA str_A6[] = "AMD A6-";
+CONST CHAR8 ROMDATA str_A4[] = "AMD A4-";
+CONST CHAR8 ROMDATA str_PhenomII[] = "AMD Phenom(TM) II";
+CONST CHAR8 ROMDATA str_AthlonII[] = "AMD Athlon(TM) II";
+CONST CHAR8 ROMDATA str_SempronII[] = "AMD Sempron(TM) II";
+CONST CHAR8 ROMDATA str_Sempron[] = "AMD Sempron(TM)";
+/*---------------------------------------------------------------------------------------
+ * Processor Family Table
+ *
+ *       048h = "A-Series"
+ *       0ECh = "AMD Phenom(TM) II Processor Family"
+ *       0EDh = "AMD Athlon(tm) II"
+ *       085h = "AMD Sempron(tm)"
+ *       0E5h = "AMD Sempron(tm) II"
+
+ *-------------------------------------------------------------------------------------*/
+
+CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFP2T4ProcFamily[] =
+{
+  {str_A10, 0x48},
+  {str_A8, 0x48},
+  {str_A6, 0x48},
+  {str_A4, 0x48},
+};
+
+CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFS1T4ProcFamily[] =
+{
+  {str_A10, 0x48},
+  {str_A8, 0x48},
+  {str_A6, 0x48},
+  {str_A4, 0x48},
+};
+
+CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFM2T4ProcFamily[] =
+{
+  {str_A10, 0x48},
+  {str_A8, 0x48},
+  {str_A6, 0x48},
+  {str_A4, 0x48},
+  {str_PhenomII, 0xEC},
+  {str_AthlonII, 0xED},
+  {str_SempronII, 0xE5},
+  {str_Sempron, 0x85},
+};
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+DmiF15TnGetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+DmiF15TnGetT4ProcFamily (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT8
+DmiF15TnGetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+DmiF15TnGetMemInfo (
+  IN OUT   CPU_GET_MEM_INFO  *CpuGetMemInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT16
+DmiF15TnGetExtClock (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF15TnGetInfo
+ *
+ *    Get CPU type information
+ *
+ *    @param[in,out]  CpuInfoPtr     Pointer to CPU_TYPE_INFO struct.
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ */
+VOID
+DmiF15TnGetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 NumOfCoresPerCU;
+  CPUID_DATA CpuId;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+  CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
+  CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
+  CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
+  CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4)  & 0xF; // bit 7:4
+  CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
+
+  CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber--;
+
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
+  CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
+
+  switch (CpuInfoPtr->PackageType) {
+  case TN_SOCKET_FP2:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
+    break;
+  case TN_SOCKET_FS1:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_FS1;
+    break;
+  case TN_SOCKET_FM2:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_FM2;
+    break;
+  default:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
+    break;
+  }
+
+  switch (GetComputeUnitMapping (StdHeader)) {
+  case AllCoresMapping:
+    NumOfCoresPerCU = 1;
+    break;
+  case EvenCoresMapping:
+    NumOfCoresPerCU = 2;
+    break;
+  default:
+    NumOfCoresPerCU = 2;
+  }
+  // L1 Size & Associativity
+  LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader);
+  CpuInfoPtr->CacheInfo.L1CacheSize = (UINT32) (((UINT8) ((CpuId.ECX_Reg >> 24) * NumOfCoresPerCU) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU);
+
+  CpuInfoPtr->CacheInfo.L1CacheAssoc = DMI_ASSOCIATIVE_2_WAY; // Per the BKDG, this is hard-coded to 2-Way.
+
+  // L2 Size & Associativity
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader);
+  CpuInfoPtr->CacheInfo.L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU);
+
+  CpuInfoPtr->CacheInfo.L2CacheAssoc = DMI_ASSOCIATIVE_16_WAY; // Per the BKDG, this is hard-coded to 16-Way.
+
+  // L3 Size & Associativity
+  CpuInfoPtr->CacheInfo.L3CacheSize = 0;
+  CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN;
+  }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF15TnGetT4ProcFamily
+ *
+ *    Get type 4 processor family information
+ *
+ *    @param[in,out]  T4ProcFamily   Pointer to type 4 processor family information.
+ *    @param[in]      *CpuDmiProcFamilyTable  Pointer to DMI family special service
+ *    @param[in]      *CpuInfo       Pointer to CPU_TYPE_INFO struct
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ */
+VOID
+DmiF15TnGetT4ProcFamily (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CHAR8 NameString[49];
+  CONST CHAR8 *DmiString;
+  CONST VOID  *DmiStringTable;
+  UINT8 NumberOfDmiString;
+  UINT8 i;
+
+  // Get name string from MSR_C001_00[30:35]
+  GetNameString (NameString, StdHeader);
+  // Get DMI String
+  DmiStringTable = NULL;
+  switch (CpuInfo->PackageType) {
+  case TN_SOCKET_FP2:
+    DmiStringTable = (CONST VOID *) &F15TnFP2T4ProcFamily[0];
+    NumberOfDmiString = sizeof (F15TnFP2T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY);
+    break;
+  case TN_SOCKET_FS1:
+    DmiStringTable = (CONST VOID *) &F15TnFS1T4ProcFamily[0];
+    NumberOfDmiString = sizeof (F15TnFS1T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY);
+    break;
+  case TN_SOCKET_FM2:
+    DmiStringTable = (CONST VOID *) &F15TnFM2T4ProcFamily[0];
+    NumberOfDmiString = sizeof (F15TnFM2T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY);
+    break;
+  default:
+    DmiStringTable = NULL;
+    NumberOfDmiString = 0;
+    break;
+  }
+
+  // Find out which DMI string matches current processor's name string
+  *T4ProcFamily = P_FAMILY_UNKNOWN;
+  if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) {
+    for (i = 0; i < NumberOfDmiString; i++) {
+      DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart;
+      if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) {
+        *T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting;
+        break;
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF15TnGetVoltage
+ *
+ *    Get the voltage value according to SMBIOS SPEC's requirement.
+ *
+ *    @param[in]       StdHeader      Standard Head Pointer
+ *
+ *    @retval  Voltage   - CPU Voltage.
+ *
+ */
+UINT8
+DmiF15TnGetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8     MaxVid;
+  UINT8     Voltage;
+  UINT8     NumberBoostStates;
+  UINT64    MsrData;
+  PCI_ADDR  TempAddr;
+  CPB_CTRL_REGISTER CpbCtrl;
+
+  // Voltage = 0x80 + (voltage at boot time * 10)
+  TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader);  // F4x15C
+  NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+
+  LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
+  MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+
+  if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) {
+    Voltage = 0;
+  } else {
+    Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000);
+  }
+
+  Voltage += 0x80;
+  return (Voltage);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF15TnGetMemInfo
+ *
+ *    Get memory information.
+ *
+ *    @param[in,out]  CpuGetMemInfoPtr      Pointer to CPU_GET_MEM_INFO struct.
+ *    @param[in]      StdHeader             Standard Head Pointer
+ *
+ */
+VOID
+DmiF15TnGetMemInfo (
+  IN OUT   CPU_GET_MEM_INFO  *CpuGetMemInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CpuGetMemInfoPtr->EccCapable = FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF15TnGetExtClock
+ *
+ *    Get the external clock Speed
+ *
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ *    @retval  ExtClock   - CPU external clock Speed.
+ *
+ */
+UINT16
+DmiF15TnGetExtClock (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  return (EXTERNAL_CLOCK_100MHZ);
+}
+
+/* -----------------------------------------------------------------------------*/
+CONST PROC_FAMILY_TABLE ROMDATA ProcFamily15TnDmiTable =
+{
+// This table is for Processor family 15h Trinity
+  AMD_FAMILY_15_TN,               // ID for Family 15h Trinity
+  DmiF15TnGetInfo,                // Transfer vectors for family
+  DmiF15TnGetT4ProcFamily,        // Get type 4 processor family information
+  DmiF15TnGetVoltage,             //   specific routines (above)
+  DmiF15GetMaxSpeed,
+  DmiF15TnGetExtClock,
+  DmiF15TnGetMemInfo,             // Get memory information
+  0,
+  NULL
+};
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
new file mode 100644
index 0000000000..b1ac32f212
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
@@ -0,0 +1,204 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 TN HTC Initialization
+ *
+ * Enables Hardware Thermal Control (HTC) feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63692 $   @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "CommonReturns.h"
+#include "cpuHtc.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNHTC_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+F15TnHtcInit (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR                PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION   OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Entry point for enabling Hardware Thermal Control
+ *
+ * This function must be run after all P-State routines have been executed
+ *
+ * @param[in]  HtcServices             The current CPU's family services.
+ * @param[in]  EntryPoint              Timepoint designator.
+ * @param[in]  PlatformConfig          Platform profile/build option config structure.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15TnInitializeHtc (
+  IN       HTC_FAMILY_SERVICES    *HtcServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR                  PciAddress;
+  CPU_SPECIFIC_SERVICES     *FamilySpecificServices;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    F15TnHtcInit (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *    Main entry point for initializing the Thermal Control
+ *    safety net feature.
+ *
+ *    This must be run by all Family 15h Trinity core 0s in the system.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  PlatformConfig          Platform profile/build option config structure
+ * @param[in]  PciAddress              Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader               Config handle for library and services.
+ */
+VOID
+F15TnHtcInit (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR                PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32    LocalPciRegister;
+
+  PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
+    // Enable HTC
+    PciAddress.Address.Register = HTC_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
+      // Enable HTC
+      ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
+    } else {
+      // Disable HTC
+      ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0;
+    }
+    IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader);
+    LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  }
+}
+
+CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport =
+{
+  0,
+  (PF_HTC_IS_SUPPORTED) CommonReturnTrue,
+  F15TnInitializeHtc
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
new file mode 100644
index 0000000000..1f23cc5948
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
@@ -0,0 +1,496 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity after warm reset sequence for NB P-states
+ *
+ * Performs the "NB COF and VID Transition Sequence After Warm Reset"
+ * as described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 64197 $   @e \$Date: 2012-01-17 16:18:33 -0600 (Tue, 17 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "cpuF15TnNbAfterReset.h"
+#include "GnbRegisterAccTN.h"
+#include "GnbRegistersTN.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F15TnPmNbAfterResetOnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+TransitionToNbLow (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+STATIC
+TransitionToNbHigh (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+STATIC
+WaitForNbTransitionToComplete (
+  IN       PCI_ADDR           PciAddress,
+  IN       UINT32             PstateIndex,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 15h Trinity core 0 entry point for performing the necessary steps after
+ * a warm reset has occurred.
+ *
+ * The steps are as follows:
+ *
+ *   1.    Temp1=D18F5x170[SwNbPstateLoDis].
+ *   2.    Temp2=D18F5x170[NbPstateDisOnP0].
+ *   3.    Temp3=D18F5x170[NbPstateThreshold].
+ *   4.    Temp4=D18F5x170[NbPstateGnbSlowDis].
+ *   5.    If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11.
+ *   6.    Write 1 to D18F5x170[NbPstateGnbSlowDis].
+ *   7.    Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+ *   8.    Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+ *   9.    Set D18F5x170[SwNbPstateLoDis]=1.
+ *   10.   Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15.
+ *   11.   Write 1 to D18F5x170[SwNbPstateLoDis].
+ *   12.   Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+ *   13.   Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+ *   14.   Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+ *   15.   Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
+ *         stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F15TnPmNbAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Core;
+  UINT32    TaskedCore;
+  UINT32    Ignored;
+  AP_TASK   TaskPtr;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+  LOCATE_HEAP_PTR Locate;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnPmNbAfterReset\n");
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+
+  ASSERT (Core == 0);
+
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
+    PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    Locate.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE;
+    if (HeapLocateBuffer (&Locate, StdHeader) == AGESA_SUCCESS) {
+      LibAmdPciWrite (AccessWidth32, PciAddress, Locate.BufferPtr, StdHeader);
+    } else {
+      ASSERT (FALSE);
+    }
+  }
+
+  // Launch one core per node.
+  TaskPtr.FuncAddress.PfApTask = F15TnPmNbAfterResetOnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) {
+      if (TaskedCore != 0) {
+        ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader);
+      }
+    }
+  }
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 15h Trinity core 0 entry point for performing the necessary Nb P-state VID adjustment
+ * after a cold reset has occurred.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F15TnNbPstateVidAdjustAfterReset (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR                  PciAddress;
+  BOOLEAN                   NeitherHiNorLo;
+  NB_PSTATE_REGISTER        NbPsReg;
+  UINT32                    NbPsVid;
+  UINT32                    i;
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrl;
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrlSave;
+  NB_PSTATE_STS_REGISTER    NbPsSts;
+  CLK_PWR_TIMING_CTRL_5_REGISTER  ClkPwrTimgCtrl5;
+  D0F0xBC_x1F400_STRUCT     D0F0xBC_x1F400;
+
+  // Check if D18F5x188[NbOffsetTrim] has been programmed to 01b (-25mV)
+  PciAddress.AddressValue = CPTC5_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader);
+  if (ClkPwrTimgCtrl5.NbOffsetTrim == 1) {
+    return;
+  }
+
+  // Add 25mV (-4 VID steps) to all VddNb VIDs.
+  PciAddress.AddressValue = NB_PSTATE_0_PCI_ADDR;
+
+  for (i = 0; i < NM_NB_PS_REG; i++) {
+    PciAddress.Address.Register = NB_PSTATE_0 + (i * 4);
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsReg, StdHeader);
+    if (NbPsReg.NbPstateEn == 1) {
+      NbPsVid = GetF15TnNbVid (&NbPsReg);
+      NbPsVid -= 4;
+      SetF15TnNbVid (&NbPsReg, &NbPsVid);
+      LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsReg, StdHeader);
+    }
+  }
+
+  // Check if D18F5x174[CurNbPstate] equals NbPstateHi or NbPstateLo
+  PciAddress.Address.Register = NB_PSTATE_STATUS;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader);
+  PciAddress.Address.Register = NB_PSTATE_CTRL;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+  // Save NB P-state control setting
+  NbPsCtrlSave = NbPsCtrl;
+
+  // Force a NB P-state Transition.
+  NeitherHiNorLo = FALSE;
+  if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi) {
+    TransitionToNbLow (PciAddress, StdHeader);
+  } else if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) {
+    TransitionToNbHigh (PciAddress, StdHeader);
+  } else {
+    NeitherHiNorLo = TRUE;
+  }
+
+  // Set OffsetTrim to -25mV:
+  //   D18F5x188[NbOffsetTrim]=01b (-25mV)
+  //   D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV)
+  PciAddress.Address.Register = CPTC5_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader);
+  ClkPwrTimgCtrl5.NbOffsetTrim = 1;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader);
+
+  GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+  D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+
+  // Unforce NB P-state back to CurNbPstate value upon entry.
+  if (NeitherHiNorLo || (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi)) {
+    TransitionToNbHigh (PciAddress, StdHeader);
+  } else {
+    // if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo)
+    TransitionToNbLow (PciAddress, StdHeader);
+  }
+
+  // Restore NB P-state control setting
+  PciAddress.Address.Register = NB_PSTATE_CTRL;
+  NbPsCtrl = NbPsCtrlSave;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F15TnPmNbAfterReset to perform MSR initialization on one
+ * core of each die in a family 15h socket.
+ *
+ * This function implements steps 1 - 15 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F15TnPmNbAfterResetOnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    NbPsCtrlOnEntry;
+  UINT32    NbPsCtrlOnExit;
+  UINT64    LocalMsrRegister;
+  PCI_ADDR  PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnPmNbAfterResetOnCore\n");
+
+  // 1. Temp1 = D18F5x170[SwNbPstateLoDis].
+  // 2. Temp2 = D18F5x170[NbPstateDisOnP0].
+  // 3. Temp3 = D18F5x170[NbPstateThreshold].
+  // 4. Temp4 = D18F5x170[NbPstateGnbSlowDis].
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
+
+  // Check if NB P-states were disabled, and if so, prevent any changes from occurring.
+  if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) {
+    // 5. If MSRC001_0070[NbPstate] = 1, go to step 11
+    LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
+    if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
+      // 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
+      PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+      ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+
+      // 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+      // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
+      //    CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+      TransitionToNbLow (PciAddress, StdHeader);
+
+      // 9. Set D18F5x170[SwNbPstateLoDis] = 1.
+      // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
+      //     CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+      //     Go to step 15.
+      TransitionToNbHigh (PciAddress, StdHeader);
+    } else {
+      // 11. Set D18F5x170[SwNbPstateLoDis] = 1.
+      // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
+      //     CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+      TransitionToNbHigh (PciAddress, StdHeader);
+
+      // 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+      // 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
+      //     CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+      TransitionToNbLow (PciAddress, StdHeader);
+    }
+
+    // 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
+    //     stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F15TnPmNbAfterResetOnCore to transition to the low NB P-state.
+ *
+ * This function implements steps 7, 8, 13, and 14 as needed.
+ *
+ * @param[in]  PciAddress         Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+TransitionToNbLow (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  TransitionToNbLow\n");
+
+  // 7/13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+  NbPsCtrl.SwNbPstateLoDis = 0;
+  NbPsCtrl.NbPstateDisOnP0 = 0;
+  NbPsCtrl.NbPstateThreshold = 0;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+  // 8/14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
+  //       CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+  WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F15TnPmNbAfterResetOnCore to transition to the high NB P-state.
+ *
+ * This function implements steps 9, 10, 11, and 12 as needed.
+ *
+ * @param[in]  PciAddress         Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+TransitionToNbHigh (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  TransitionToNbHigh\n");
+
+  // 9/10. Set D18F5x170[SwNbPstateLoDis] = 1.
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+  NbPsCtrl.SwNbPstateLoDis = 1;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+  // 11/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
+  //       CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+  WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F15TnPmAfterResetCore to wait for NB FID and DID to
+ * match a specific P-state.
+ *
+ * This function implements steps 8, 10, 12, and 14 as needed.
+ *
+ * @param[in]  PciAddress         Segment, bus, device number of the node to transition.
+ * @param[in]  PstateIndex        P-state settings to match.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+WaitForNbTransitionToComplete (
+  IN       PCI_ADDR           PciAddress,
+  IN       UINT32             PstateIndex,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  NB_PSTATE_REGISTER       TargetNbPs;
+  NB_PSTATE_STS_REGISTER   NbPsSts;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  WaitForNbTransitionToComplete\n");
+
+  PciAddress.Address.Function = FUNC_5;
+  PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2);
+  LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader);
+  PciAddress.Address.Register = NB_PSTATE_STATUS;
+  do {
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader);
+  } while ((NbPsSts.CurNbPstate != PstateIndex ||
+           (NbPsSts.CurNbFid != TargetNbPs.NbFid)) ||
+           (NbPsSts.CurNbDid != TargetNbPs.NbDid));
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h
new file mode 100644
index 0000000000..8fe1fdfb8e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h
@@ -0,0 +1,112 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity after warm reset sequence for NB P-states
+ *
+ * Contains code that provide power management functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_TN_NB_AFTER_RESET_H_
+#define _CPU_F15_TN_NB_AFTER_RESET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F15TnPmNbAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+F15TnNbPstateVidAdjustAfterReset (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif  // _CPU_F15_TN_NB_AFTER_RESET_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
new file mode 100644
index 0000000000..8d050b078e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
@@ -0,0 +1,486 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Tn P-State power check
+ *
+ * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF15PowerCheck.h"
+#include "cpuF15TnPowerCheck.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPOWERCHECK_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F15TnPmPwrCheckCore (
+  IN     VOID *ErrorData,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F15TnPmPwrChkCopyPstate (
+  IN     UINT8 Dest,
+  IN     UINT8 Src,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 15h core 0 entry point for performing the family 15h Processor-
+ * Systemboard Power Delivery Check.
+ *
+ * The steps are as follows:
+ *    1. Starting with P0, loop through all P-states until a passing state is
+ *       found.  A passing state is one in which the current required by the
+ *       CPU is less than the maximum amount of current that the system can
+ *       provide to the CPU.  If P0 is under the limit, no further action is
+ *       necessary.
+ *    2. If at least one P-State is under the limit & at least one P-State is
+ *       over the limit, the BIOS must:
+ *       a. If the processor's current P-State is disabled by the power check,
+ *          then the BIOS must request a transition to an enabled P-state
+ *          using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
+ *          to reflect the new value.
+ *       b. Copy the contents of the enabled P-state MSRs to the highest
+ *          performance P-state locations.
+ *       c. Request a P-state transition to the P-state MSR containing the
+ *          COF/VID values currently applied.
+ *       d. If a subset of boosted P-states are disabled, then copy the contents
+ *          of the highest performance boosted P-state still enabled to the
+ *          boosted P-states that have been disabled.
+ *       e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc]
+ *          to zero.
+ *       f. Adjust the following P-state parameters affected by the P-state
+ *          MSR copy by subtracting the number of P-states that are disabled
+ *          by the power check.
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[SwPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *    3. If all P-States are over the limit, the BIOS must:
+ *       a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
+ *          write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
+ *          MSRC001_0063[CurPstate] to reflect the new value.
+ *       b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state
+ *          MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR.
+ *          Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
+ *          [CurPstate] to reflect the new value.
+ *       c. Adjust the following P-state parameters to zero:
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[SwPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *       d. Program D18F4x15C[BoostSrc] to zero.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F15TnPmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8       DisPsNum;
+  UINT8       PsMaxVal;
+  UINT8       Pstate;
+  UINT32      ProcIddMax;
+  UINT32      LocalPciRegister;
+  UINT32      Socket;
+  UINT32      Module;
+  UINT32      Core;
+  UINT32      AndMask;
+  UINT32      OrMask;
+  UINT32      PstateLimit;
+  PCI_ADDR    PciAddress;
+  UINT64      LocalMsrRegister;
+  AP_TASK     TaskPtr;
+  AGESA_STATUS IgnoredSts;
+  PWRCHK_ERROR_DATA ErrorData;
+  UINT32      NumModules;
+  UINT32      HighCore;
+  UINT32      LowCore;
+  UINT32      ModuleIndex;
+  NB_CAPS_REGISTER              NbCaps;
+  HTC_REGISTER                  HtcReg;
+  CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
+
+  // update PstateMaxVal if warranted by HtcPstateLimit
+  PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // D18F3xE8
+  if (NbCaps.HtcCapable == 1) {
+    PciAddress.AddressValue = (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG));
+    LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
+    if (HtcReg.HtcTmpLmt != 0) {
+      PciAddress.AddressValue = CPTC2_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+      if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) {
+        ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+      }
+    }
+  }
+
+  // get the socket number
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  ErrorData.SocketNumber = (UINT8) Socket;
+
+  ASSERT (Core == 0);
+
+  // get the Max P-state value
+  for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
+    if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+
+  ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
+
+ // Starting with P0, loop through all P-states until a passing state is
+ // found.  A passing state is one in which the current required by the
+ // CPU is less than the maximum amount of current that the system can
+ // provide to the CPU.  If P0 is under the limit, no further action is
+ // necessary.
+  DisPsNum = 0;
+  for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
+    if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
+      if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
+        // Add to event log the Pstate that exceeded the current limit
+        PutEventLog (AGESA_WARNING,
+                     CPU_EVENT_PM_PSTATE_OVERCURRENT,
+                     Socket, Pstate, 0, 0, StdHeader);
+        DisPsNum++;
+      } else {
+        break;
+      }
+    }
+  }
+
+  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+
+  if (ErrorData.AllowablePstateNumber == 0) {
+    PutEventLog (AGESA_FATAL,
+                 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
+                 Socket, 0, 0, 0, StdHeader);
+  }
+
+  if (DisPsNum != 0) {
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_4;
+    PciAddress.Address.Register = CPB_CTRL_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+    ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+
+    if (DisPsNum >= ErrorData.NumberOfBoostStates) {
+      // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero.
+      AndMask = 0xFFFFFFFF;
+      ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0;
+      OrMask = 0x00000000;
+      OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C
+
+      ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates;
+    } else {
+      ErrorData.NumberOfSwPstatesDisabled = 0;
+    }
+
+    NumModules = GetPlatformNumberOfModules ();
+
+    // Only execute this loop if this is an MCM.
+    if (NumModules > 1) {
+
+      // Since the P-State MSRs are shared across a
+      // node, we only need to set one core in the node for the modified number of supported p-states
+      // to be reported across all of the cores in the module.
+      TaskPtr.FuncAddress.PfApTaskI = F15TnPmPwrCheckCore;
+      TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
+      TaskPtr.DataTransfer.DataPtr = &ErrorData;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+      for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) {
+        // Execute the P-State reduction code on the module's primary core only.
+        // Skip this code for the BSC's module.
+        if (ModuleIndex != Module) {
+          if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) {
+            ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader);
+          }
+        }
+      }
+  }
+
+    // Path for SCM and the BSC
+    F15TnPmPwrCheckCore (&ErrorData, StdHeader);
+
+    // Final Step
+    //    F3x64[HtPstatelimit] -= disPsNum
+    //    F3x68[SwPstateLimit] -= disPsNum
+    //    F3xDC[PstateMaxVal] -= disPsNum
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = HTC_REG;
+    AndMask = 0xFFFFFFFF;
+    ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
+    PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
+    if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+      PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
+    }
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
+
+    PciAddress.Address.Register = SW_PS_LIMIT_REG;
+    AndMask = 0xFFFFFFFF;
+    ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
+    PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit;
+    if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+      PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit;
+    }
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
+
+    PciAddress.Address.Register = CPTC2_REG;
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
+    PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
+    if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+      PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
+    }
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Core-level error handler called if any p-states were determined to be out
+ * of range for the mother board.
+ *
+ * This function implements steps 2a-c and 3a-c on each core.
+ *
+ * @param[in]  ErrorData            Details about the error condition.
+ * @param[in]  StdHeader            Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F15TnPmPwrCheckCore (
+  IN       VOID *ErrorData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  i;
+  UINT8  HwPsMaxVal;
+  UINT8  SwPsMaxVal;
+  UINT8  HwDisPsNum;
+  UINT8  CurrentSwPs;
+  UINT8  PsDisableCount;
+  UINT64 LocalMsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    // P-state MSRs are shared, so only 1 core per compute unit needs to perform this
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+    HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+                  ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
+
+    LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+    CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
+    LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+    SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal);
+    PsDisableCount = 0;
+
+    if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+      // All P-States are over the limit.
+
+      // Step 1
+      // Transition to Pstate Max if not there already
+      if (CurrentSwPs != SwPsMaxVal) {
+        FamilySpecificServices->TransitionPstate (FamilySpecificServices, SwPsMaxVal, (BOOLEAN) TRUE, StdHeader);
+      }
+
+      // Step 2
+      // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+      // to P0.
+      if (SwPsMaxVal != 0) {
+        F15TnPmPwrChkCopyPstate (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates, HwPsMaxVal, StdHeader);
+        FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+      }
+
+      // Disable all SW P-states except P0
+      PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1;
+    } else {
+      // At least one P-State is under the limit & at least one P-State is
+      // over the limit.
+      if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) {
+        // A subset of boosted P-states are disabled.  Copy the contents of the
+        // highest performance boosted P-state still enabled to the boosted
+        // P-states that have been disabled.
+        for (i = 0; i < HwDisPsNum; i++) {
+          F15TnPmPwrChkCopyPstate (i, HwDisPsNum, StdHeader);
+        }
+      } else if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) {
+        // Move remaining P-state register(s) up
+        // Step 1
+        // Transition to a valid Pstate if current Pstate has been disabled
+        if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) {
+          FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader);
+          CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+        }
+
+        // Step 2
+        // Move enabled Pstates up and disable the remainder
+        for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) {
+          F15TnPmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader);
+        }
+
+        // Step 3
+        // Transition to current COF/VID at shifted location
+        CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled);
+        FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSwPs, (BOOLEAN) TRUE, StdHeader);
+
+        // Disable the appropriate number of P-states
+        PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+      }
+    }
+    // Disable the appropriate P-states if any, starting from HW Pmin
+    for (i = 0; i < PsDisableCount; i++) {
+      FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copies the contents of one P-State MSR to another.
+ *
+ * @param[in]  Dest              Destination p-state number
+ * @param[in]  Src               Source p-state number
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+F15TnPmPwrChkCopyPstate (
+  IN       UINT8 Dest,
+  IN       UINT8 Src,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h
new file mode 100644
index 0000000000..a9d940cd61
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 TN Power related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_TN_POWER_CHECK_H_
+#define _CPU_F15_TN_POWER_CHECK_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F15TnPmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F15_TN_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h
new file mode 100644
index 0000000000..f192c19b03
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h
@@ -0,0 +1,609 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity Power Management related registers defination
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63661 $   @e \$Date: 2012-01-03 01:02:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_TN_POWERMGMT_H_
+#define _CPU_F15_TN_POWERMGMT_H_
+
+/*
+ * Family 15h Trinity CPU Power Management MSR definitions
+ *
+ */
+
+
+/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */
+#define MSR_INTPEND 0xC0010055ul
+
+/// Interrupt Pending and CMP-Halt MSR Register
+typedef struct {
+  UINT64 IoMsgAddr:16;               ///< IO message address
+  UINT64 Intpend1 :8;
+  UINT64 Intpend2 :1;
+  UINT64 Intpend3 :1;
+  UINT64 Intpend4 :1;
+  UINT64 :37;                        ///< Reserved
+} INTPEND_MSR;
+
+/* P-state Registers 0xC00100[6B:64] */
+
+/// P-state MSR
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid:8;                   ///< CpuVid
+  UINT64 :5;                         ///< Reserved
+  UINT64 NbPstate:1;                 ///< NbPstate
+  UINT64 :9;                         ///< Reserved
+  UINT64 IddValue:8;                 ///< IddValue
+  UINT64 IddDiv:2;                   ///< IddDiv
+  UINT64 :21;                        ///< Reserved
+  UINT64 PsEnable:1;                 ///< Pstate Enable
+} PSTATE_MSR;
+
+#define GetF15TnCpuVid(PstateMsr) (((PSTATE_MSR *) PstateMsr)->CpuVid)
+
+
+/* VID operation related macros */
+#define ConvertVidInuV(Vid)   (1550000 - (6250 * Vid)) ///< Convert VID in uV.
+
+/* COFVID Control Register 0xC0010070 */
+#define MSR_COFVID_CTL 0xC0010070ul
+
+/// COFVID Control MSR Register
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid_6_0:7;               ///< CpuVid[6:0]
+  UINT64 PstateId:3;                 ///< Pstate ID
+  UINT64 :1;                         ///< Reserved
+  UINT64 CpuVid_7:1;                 ///< CpuVid[7]
+  UINT64 :1;                         ///< Reserved
+  UINT64 NbPstate:1;                 ///< Northbridge P-state
+  UINT64 :1;                         ///< Reserved
+  UINT64 NbVid:8;                    ///< NbVid
+  UINT64 :32;                        ///< Reserved
+} COFVID_CTRL_MSR;
+
+#define COFVID_CTRL_MSR_CurCpuVid_6_0_OFFSET       9
+#define COFVID_CTRL_MSR_CurCpuVid_6_0_WIDTH        7
+#define COFVID_CTRL_MSR_CurCpuVid_6_0_MASK         0xfe00
+#define COFVID_CTRL_MSR_CurCpuVid_7_OFFSET         20
+#define COFVID_CTRL_MSR_CurCpuVid_7_WIDTH          1
+#define COFVID_CTRL_MSR_CurCpuVid_7_MASK           0x100000ul
+
+/* SVI VID Encoding */
+
+///< Union structure of VID in SVI1/SVI2 modes
+typedef union {
+  UINT32     RawVid;                 ///< Raw VID value
+  struct {                           ///< SVI2 mode VID structure
+    UINT32   Vid_6_0:7;              ///< Vid[6:0] of SVI2 mode
+    UINT32   Vid_7:1;                ///< Vid[7] of SVI2 mode
+  } SVI2;
+  struct {                           ///< SVI1 mode VID structure
+    UINT32   Vid_LSB_Ignore:1;       ///< Ignored LSB of 8bit VID encoding in SVI1 mode
+    UINT32   Vid_6_0:1;              ///< Vid[6:0] of SVI mode
+  } SVI1;
+} SVI_VID;
+
+
+#define SetF15TnCpuVid(CofVidStsMsr, NewCpuVid) ( \
+  ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_6_0) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_6_0; \
+  ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_7) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_7; \
+)
+
+
+/* COFVID Status Register 0xC0010071 */
+#define MSR_COFVID_STS 0xC0010071ul
+
+/// COFVID Status MSR Register
+typedef struct {
+  UINT64 CurCpuFid:6;                ///< Current CpuFid
+  UINT64 CurCpuDid:3;                ///< Current CpuDid
+  UINT64 CurCpuVid_6_0:7;            ///< Current CpuVid[6:0]
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :1;                         ///< Reserved
+  UINT64 CurCpuVid_7:1;              ///< Current CpuVid[7]
+  UINT64 :2;                         ///< Reserved
+  UINT64 NbPstateDis:1;              ///< NbPstate Disable
+  UINT64 CurNbVid:8;                 ///< Current NbVid[7:0]    <<<------- check where use it
+  UINT64 StartupPstate:3;            ///< Startup Pstate
+  UINT64 :14;                        ///< Reserved
+  UINT64 MaxCpuCof:6;                ///< MaxCpuCof
+  UINT64 :1;                         ///< Reserved
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 MaxNbCof:5;                 ///< MaxNbCof
+} COFVID_STS_MSR;
+
+#define COFVID_STS_MSR_CurCpuVid_6_0_OFFSET       9
+#define COFVID_STS_MSR_CurCpuVid_6_0_WIDTH        7
+#define COFVID_STS_MSR_CurCpuVid_6_0_MASK         0xfe00
+#define COFVID_STS_MSR_CurCpuVid_7_OFFSET         20
+#define COFVID_STS_MSR_CurCpuVid_7_WIDTH          1
+#define COFVID_STS_MSR_CurCpuVid_7_MASK           0x100000ul
+
+#define GetF15TnCurCpuVid(CofVidStsMsr) ( \
+  (((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_7 << COFVID_STS_MSR_CurCpuVid_6_0_WIDTH) \
+  | ((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_6_0)
+
+
+/* Floating Point Configuration Register 0xC0011028 */
+#define MSR_FP_CFG 0xC0011028ul
+
+/// Floating Point Configuration MSR Register
+typedef struct {
+  UINT64 :16;                        ///< Reserved
+  UINT64 DiDtMode:1;                 ///< Di/Dt Mode
+  UINT64 :1;                         ///< Reserved
+  UINT64 DiDtCfg0:5;                 ///< Di/Dt Config 0
+  UINT64 :2;                         ///< Reserved
+  UINT64 DiDtCfg2:2;                 ///< Di/Dt Config 2
+  UINT64 DiDtCfg1:8;                 ///< Di/Dt Config 1
+  UINT64 :6;                         ///< Reserved
+  UINT64 DiDtCfg5:1;                 ///< Di/Dt Config 5
+  UINT64 DiDtCfg4:3;                 ///< Di/Dt Config 4
+  UINT64 :19;                        ///< Reserved
+} FP_CFG_MSR;
+
+/* Load-Store Configuration 2 0xC001102D */
+
+/// Load-Store Configuration 2 MSR Register
+typedef struct {
+  UINT64 :14;                        ///< Reserved
+  UINT64 ForceSmcCheckFlwStDis:1;    ///< ForceSmcCheckFlwStDis
+  UINT64 :8;                         ///< Reserved
+  UINT64 DisScbThreshold:1;          ///< DisScbThreshold
+  UINT64 :40;                        ///< Reserved
+} LS_CFG2_MSR;
+
+/*
+ * Family 15h Trinity CPU Power Management PCI definitions
+ *
+ */
+
+
+/* DRAM Configuration High Register F2x[1,0]94 */
+#define DRAM_CFG_HI_REG0 0x94
+#define DRAM_CFG_HI_REG1 0x194
+
+/// DRAM Configuration High PCI Register
+typedef struct {
+  UINT32 MemClkFreq:5;               ///< Memory clock frequency
+  UINT32 :2;                         ///< Reserved
+  UINT32 MemClkFreqVal:1;            ///< Memory clock frequency valid
+  UINT32 :2;                         ///< Reserved
+  UINT32 ZqcsInterval:2;             ///< ZQ calibration short interval
+  UINT32 :2;                         ///< Reserved
+  UINT32 DisDramInterface:1;         ///< Disable the DRAM interface
+  UINT32 PowerDownEn:1;              ///< Power down mode enable
+  UINT32 PowerDownMode:1;            ///< Power down mode
+  UINT32 :2;                         ///< Reserved
+  UINT32 DcqArbBypassEn:1;           ///< DRAM controller arbiter bypass enable
+  UINT32 SlowAccessMode:1;           ///< Slow access mode
+  UINT32 FreqChgInProg:1;            ///< Frequency change in progress
+  UINT32 BankSwizzleMode:1;          ///< Bank swizzle mode
+  UINT32 ProcOdtDis:1;               ///< Processor on-die termination disable
+  UINT32 DcqBypassMax:5;             ///< DRAM controller queue bypass maximum
+  UINT32 :3;                         ///< Reserved
+} DRAM_CFG_HI_REGISTER;
+
+/* DCT Configuration Select D18F1x10C */
+#define DCT_CFG_SEL_REG 0x10C
+#define DCT_CFG_SEL_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_1, DCT_CFG_SEL_REG))
+
+/// DCT Configuration Select
+typedef struct {
+  UINT32 DctCfgSel:1;                ///< DRAM controller configuration select
+  UINT32 :31;                        ///< Reserved
+} DCT_CFG_SEL_REGISTER;
+
+
+/* GMC to DCT Control 2 D18F2x408_dct[1:0] */
+#define GMC_TO_DCT_CTL_2_REG 0x408
+#define GMC_TO_DCT_CTL_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, GMC_TO_DCT_CTL_2_REG))
+
+/// GMC to DCT Control 2 PCI Register
+typedef struct {
+  UINT32 CpuElevPrioDis:1;           ///< Cpu elevate priority disable
+  UINT32 :31;                        ///< Reserved
+} GMC_TO_DCT_CTL_2_REGISTER;
+
+
+/* Power Control Miscellaneous Register F3xA0 */
+#define PW_CTL_MISC_REG 0xA0
+#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
+
+/// Power Control Miscellaneous PCI Register
+typedef struct {
+  UINT32 PsiVid:7;                   ///< PSI_L VID threshold VID[6:0]
+  UINT32 PsiVidEn:1;                 ///< PSI_L VID enable
+  UINT32 PsiVid_7:1;                 ///< PSI_L VID threshold VID[7]
+  UINT32 :2;                         ///< Reserved
+  UINT32 PllLockTime:3;              ///< PLL synchronization lock time
+  UINT32 Svi2HighFreqSel:1;          ///< SVI2 high frequency select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ConfigId:12;                ///< Configuration ID
+  UINT32 :3;                         ///< Reserved
+  UINT32 CofVidProg:1;               ///< COF and VID of Pstate programmed
+} POWER_CTRL_MISC_REGISTER;
+
+
+/* Clock Power/Timing Control 0 Register F3xD4 */
+#define CPTC0_REG 0xD4
+#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
+
+/// Clock Power Timing Control PCI Register
+typedef struct {
+  UINT32 MaxSwPstateCpuCof:6;        ///< Maximum software P-state core COF
+  UINT32 :2;                         ///< Reserved
+  UINT32 ClkRampHystSel:4;           ///< Clock Ramp Hysteresis Select
+  UINT32 ClkRampHystCtl:1;           ///< Clock Ramp Hysteresis Control
+  UINT32 :1;                         ///< Reserved
+  UINT32 CacheFlushImmOnAllHalt:1;   ///< Cache Flush Immediate on All Halt
+  UINT32 :1;                         ///< Reserved
+  UINT32 clkpwr0 :2;
+  UINT32 :2;                         ///< Reserved
+  UINT32 PowerStepDown:4;            ///< Power Step Down
+  UINT32 PowerStepUp:4;              ///< Power Step Up
+  UINT32 NbClkDiv:3;                 ///< NbClkDiv
+  UINT32 NbClkDivApplyAll:1;         ///< NbClkDivApplyAll
+} CLK_PWR_TIMING_CTRL_REGISTER;
+
+
+/* Clock Power/Timing Control 1 Register F3xD8 */
+#define CPTC1_REG 0xD8
+#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
+
+/// Clock Power Timing Control 1 PCI Register
+typedef struct {
+  UINT32 :4;                         ///< Reserved
+  UINT32 VSRampSlamTime:3;           ///< Voltage stabilization ramp time
+  UINT32 :25;                        ///< Reserved
+} CLK_PWR_TIMING_CTRL1_REGISTER;
+
+
+/* Northbridge Capabilities Register F3xE8 */
+#define NB_CAPS_REG 0xE8
+#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
+
+/// Northbridge Capabilities PCI Register
+typedef struct {
+  UINT32 :1;                         ///< Reserved
+  UINT32 DualNode:1;                 ///< Dual-node multi-processor capable
+  UINT32 EightNode:1;                ///< Eight-node multi-processor capable
+  UINT32 Ecc:1;                      ///< ECC capable
+  UINT32 Chipkill:1;                 ///< Chipkill ECC capable
+  UINT32 :3;                         ///< Reserved
+  UINT32 MctCap:1;                   ///< Memory controller capable
+  UINT32 SvmCapable:1;               ///< SVM capable
+  UINT32 HtcCapable:1;               ///< HTC capable
+  UINT32 :3;                         ///< Reserved
+  UINT32 MultVidPlane:1;             ///< Multiple VID plane capable
+  UINT32 :4;                         ///< Reserved
+  UINT32 x2Apic:1;                   ///< x2Apic capability
+  UINT32 :4;                         ///< Reserved
+  UINT32 MemPstateCap:1;             ///< Memory P-state capable
+  UINT32 L3Capable:1;                ///< L3 capable
+  UINT32 :6;                         ///< Reserved
+} NB_CAPS_REGISTER;
+
+
+/* Product Info Register F3x1FC */
+#define PRCT_INFO_REG 0x1FC
+#define PRCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRCT_INFO_REG))
+
+/// Product Information PCI Register
+typedef struct {
+  UINT32 DiDtMode:1;                 ///< DiDtMode
+  UINT32 DiDtCfg0:5;                 ///< DiDtCfg0
+  UINT32 DiDtCfg1:8;                 ///< DiDtCfg1
+  UINT32 DiDtCfg2:2;                 ///< DiDtCfg2
+  UINT32 :1;                         ///< Reserved
+  UINT32 DiDtCfg4:3;                 ///< DiDtCfg4
+  UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit
+  UINT32 :1;                         ///< Reserved
+  UINT32 DiDtCfg5:1;                 ///< DiDtCfg5
+  UINT32 ForceSmcCheckFlwStDis:1;    ///< ForceSmcCheckFlwStDis
+  UINT32 SWDllCapTableEn:1;          ///< SWDllCapTableEn
+  UINT32 DllProcessFreqCtlIndex2Rate50:4; ///< DllProcessFreqCtlIndex2Rate50
+  UINT32 EnDcqChgPriToHigh:1;        ///< EnDcqChgPriToHigh
+  UINT32 :2;                         ///< Reserved
+} PRODUCT_INFO_REGISTER;
+
+
+/* C-state Control 1 Register D18F4x118 */
+#define CSTATE_CTRL1_REG 0x118
+#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
+
+/// C-state Control 1 Register
+typedef struct {
+  UINT32 CpuPrbEnCstAct0:1;          ///< Core direct probe enable
+  UINT32 CacheFlushEnCstAct0:1;      ///< Cache flush enable
+  UINT32 CacheFlushTmrSelCstAct0:2;  ///< Cache flush timer select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ClkDivisorCstAct0:3;        ///< Clock divisor
+  UINT32 PwrGateEnCstAct0:1;         ///< Power gate enable
+  UINT32 PwrOffEnCstAct0:1;          ///< C-state action field 3
+  UINT32 NbPwrGate0:1;               ///< NB power-gating 0
+  UINT32 NbClkGate0:1;               ///< NB clock-gating 0
+  UINT32 SelfRefr0:1;                ///< Self-refresh 0
+  UINT32 SelfRefrEarly0:1;           ///< Allow early self-refresh 0
+  UINT32 :2;                         ///< Reserved
+  UINT32 CpuPrbEnCstAct1:1;          ///< Core direct probe enable
+  UINT32 CacheFlushEnCstAct1:1;      ///< Cache flush eable
+  UINT32 CacheFlushTmrSelCstAct1:2;  ///< Cache flush timer select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ClkDivisorCstAct1:3;        ///< Clock divisor
+  UINT32 PwrGateEnCstAct1:1;         ///< Power gate enable
+  UINT32 PwrOffEnCstAct1:1;          ///< C-state action field 3
+  UINT32 NbPwrGate1:1;               ///< NB power-gating 1
+  UINT32 NbClkGate1:1;               ///< NB clock-gating 1
+  UINT32 SelfRefr1:1;                ///< Self-refresh 1
+  UINT32 SelfRefrEarly1:1;           ///< Allow early self-refresh 1
+  UINT32 :2;                         ///< Reserved
+} CSTATE_CTRL1_REGISTER;
+
+
+/* C-state Control 2 Register D18F4x11C */
+#define CSTATE_CTRL2_REG 0x11C
+#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
+
+/// C-state Control 2 Register
+typedef struct {
+  UINT32 CpuPrbEnCstAct2:1;          ///< Core direct probe enable
+  UINT32 CacheFlushEnCstAct2:1;      ///< Cache flush eable
+  UINT32 CacheFlushTmrSelCstAct2:2;  ///< Cache flush timer select
+  UINT32 cstate0 :1;
+  UINT32 ClkDivisorCstAct2:3;        ///< Clock divisor
+  UINT32 PwrGateEnCstAct2:1;         ///< Power gate enable
+  UINT32 PwrOffEnCstAct2:1;          ///< C-state action field 3
+  UINT32 NbPwrGate2:1;               ///< NB power-gating 2
+  UINT32 NbClkGate2:1;               ///< NB clock-gating 2
+  UINT32 SelfRefr2:1;                ///< Self-refresh 2
+  UINT32 SelfRefrEarly2:1;           ///< Allow early self-refresh 2
+  UINT32 :18;                        ///< Reserved
+} CSTATE_CTRL2_REGISTER;
+
+
+/* Cstate Policy Control 1 Register D18F4x128 */
+#define CSTATE_POLICY_CTRL1_REG 0x128
+#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG))
+
+/// Cstate Policy Control 1 Register
+typedef struct {
+  UINT32 cstplyc0 :1;
+  UINT32 CoreCstatePolicy:1;          ///< Specified processor arbitration of voltage and frequency
+  UINT32 HaltCstateIndex:3;           ///< Specifies the IO-based C-state that is invoked by a HLT instruction
+  UINT32 CacheFlushTmr:7;             ///< Cache flush timer
+  UINT32 :6;                          ///< Reserved
+  UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold
+  UINT32 :10;                         ///< Reserved
+  UINT32 CstateMsgDis:1;              ///< C-state messaging disable
+} CSTATE_POLICY_CTRL1_REGISTER;
+
+
+/* Core Performance Boost Control Register D18F4x15C */
+
+/// Core Performance Boost Control Register
+typedef struct {
+  UINT32 BoostSrc:2;                 ///< Boost source
+  UINT32 NumBoostStates:3;           ///< Number of boosted states
+  UINT32 :2;                         ///< Reserved
+  UINT32 ApmMasterEn:1;              ///< APM master enable
+  UINT32 :23;                        ///< Reserved
+  UINT32 BoostLock:1;                ///<
+} CPB_CTRL_REGISTER;
+
+
+/* Northbridge Capabilities 2  F5x84*/
+#define NB_CAPS_REG2 0x84
+#define NB_CAPS_REG2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CAPS_REG2))
+
+/// Northbridge Capabilities 2 PCI Register
+typedef struct {
+  UINT32 CmpCap:8;                   ///< CMP capable
+  UINT32 :4;                         ///< Reserved
+  UINT32 DctEn:2;                    ///< DCT enabled
+  UINT32 :2;                         ///< Reserved
+  UINT32 DdrMaxRate:5;               ///< maximum DDR rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 DdrMaxRateEnf:5;            ///< enforced maximum DDR rate:
+  UINT32 :3;                         ///< Reserved
+} NB_CAPS_2_REGISTER;
+
+/* Northbridge Configuration 4  F5x88*/
+#define NB_CFG_REG4 0x88
+#define NB_CFG_REG4_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CFG_REG4))
+
+/// Northbridge Configuration 4 PCI Register
+typedef struct {
+  UINT32 :2;                         ///< Reserved
+  UINT32 IntStpClkHaltExitEn:1;      ///< IntStpClkHaltExitEn
+  UINT32 :11;                        ///< Reserved
+  UINT32 Bit14:1;                    ///< Reserved
+  UINT32 :3;                         ///< Reserved
+  UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit
+  UINT32 :13;                        ///< Reserved
+} NB_CFG_4_REGISTER;
+
+/* Northbridge P-state [3:0] F5x1[6C:60]  */
+
+/// Northbridge P-state Register
+typedef struct {
+  UINT32 NbPstateEn:1;               ///< NB P-state enable
+  UINT32 NbFid:6;                    ///< NB frequency ID
+  UINT32 NbDid:1;                    ///< NB divisor ID
+  UINT32 :2;                         ///< Reserved
+  UINT32 NbVid_6_0:7;                ///< NB VID[6:0]
+  UINT32 :1;                         ///< Reserved
+  UINT32 MemPstate:1;                ///< Memory P-State
+  UINT32 :2;                         ///< Reserved
+  UINT32 NbVid_7:1;                  ///< NB VID[7]
+  UINT32 NbIddDiv:2;                 ///< northbridge current divisor
+  UINT32 NbIddValue:8;               ///< northbridge current value
+} NB_PSTATE_REGISTER;
+
+#define NB_PSTATE_REGISTER_NbVid_6_0_OFFSET      10
+#define NB_PSTATE_REGISTER_NbVid_6_0_WIDTH       7
+#define NB_PSTATE_REGISTER_NbVid_6_0_MASK        0x0001FC00ul
+#define NB_PSTATE_REGISTER_NbVid_7_OFFSET        21
+#define NB_PSTATE_REGISTER_NbVid_7_WIDTH         1
+#define NB_PSTATE_REGISTER_NbVid_7_MASK          0x00200000ul
+
+#define GetF15TnNbVid(NbPstateRegister) ( \
+  (((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 << NB_PSTATE_REGISTER_NbVid_6_0_WIDTH) \
+  | ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0)
+
+#define SetF15TnNbVid(NbPstateRegister, NewNbVid) { \
+  ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0 = ((SVI_VID *) NewNbVid)->SVI2.Vid_6_0; \
+  ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 = ((SVI_VID *) NewNbVid)->SVI2.Vid_7; \
+}
+
+/* Northbridge P-state Status */
+#define NB_PSTATE_CTRL 0x170
+#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL))
+
+/// Northbridge P-state Control Register
+typedef struct {
+  UINT32 NbPstateMaxVal:2;           ///< NB P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateLo:2;               ///< NB P-state low
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateHi:2;               ///< NB P-state high
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateThreshold:3;        ///< NB P-state threshold
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateDisOnP0:1;          ///< NB P-state disable on P0
+  UINT32 SwNbPstateLoDis:1;          ///< Software NB P-state low disable
+  UINT32 :8;                         ///< Reserved
+  UINT32 NbPstateGnbSlowDis:1;       ///< Disable NB P-state transition take GnbSlow into account.
+  UINT32 NbPstateLoRes:3;            ///< NB P-state low residency timer
+  UINT32 NbPstateHiRes:3;            ///< NB P-state high residency timer
+  UINT32 :1;                         ///< Reserved
+  UINT32 MemPstateDis:1;             ///< Memory P-state disable
+} NB_PSTATE_CTRL_REGISTER;
+
+
+/* Northbridge P-state Status */
+#define NB_PSTATE_STATUS 0x174
+#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS))
+
+/// Northbridge P-state Status Register
+typedef struct {
+  UINT32 NbPstateDis:1;              ///< Nb pstate disable
+  UINT32 StartupNbPstate:2;          ///< startup northbridge Pstate number
+  UINT32 CurNbFid:6;                 ///< Current NB FID
+  UINT32 CurNbDid:1;                 ///< Current NB DID
+  UINT32 :2;                         ///< Reserved
+  UINT32 CurNbVid_6_0:7;             ///< Current NB VID[6:0]
+  UINT32 CurNbPstate:2;              ///< Current NB Pstate
+  UINT32 :2;                         ///< Reserved
+  UINT32 CurNbVid_7:1;               ///< Current NB VID[7]
+  UINT32 CurMemPstate:1;             ///< Current memory P-state
+  UINT32 :7;                         ///< Reserved
+} NB_PSTATE_STS_REGISTER;
+
+#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_OFFSET      12
+#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH       7
+#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_MASK        0x0007F000ul
+#define NB_PSTATE_STS_REGISTER_CurNbVid_7_OFFSET        23
+#define NB_PSTATE_STS_REGISTER_CurNbVid_7_WIDTH         1
+#define NB_PSTATE_STS_REGISTER_CurNbVid_7_MASK          0x00800000ul
+
+#define GetF15TnCurNbVid(NbPstateStsRegister) ( \
+  (((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_7 << NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH) \
+  | ((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_6_0)
+
+/* Miscellaneous Voltages */
+#define MISC_VOLTAGES 0x17C
+#define MISC_VOLTAGES_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, MISC_VOLTAGES))
+
+/// Miscellaneous Voltages Register
+typedef struct {
+  UINT32 MaxVid:8;                   ///< Maximum Voltage
+  UINT32 :2;                         ///< Reserved
+  UINT32 MinVid:8;                   ///< Minimum Voltage
+  UINT32 :5;                         ///< Reserved
+  UINT32 NbPsi0Vid:8;                ///< Northbridge PSI0_L VID threshold
+  UINT32 NbPsi0VidEn:1;              ///< Northbridge PSI0_L VID enable
+} MISC_VOLTAGE_REGISTER;
+
+
+/* Clock Power/Timing Control 5 Register F5x188 */
+#define CPTC5_REG 0x188
+#define CPTC5_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, CPTC5_REG))
+
+/// Clock Power Timing Control 5 Register
+typedef struct {
+  UINT32 NbOffsetTrim:2;             ///< Northbridge offset trim
+  UINT32 NbLoadLineTrim:3;           ///< Northbridge load line trim
+  UINT32 NbPsi1:1;                   ///< Northbridge PSI1_L
+  UINT32 :26;                        ///< Reserved
+} CLK_PWR_TIMING_CTRL_5_REGISTER;
+
+#endif /* _CPU_F15_TN_POWERMGMT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
new file mode 100644
index 0000000000..d808c50d6b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
@@ -0,0 +1,308 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 TN PSI Initialization
+ *
+ * Enables Power Status Indicator (PSI) feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 65284 $   @e \$Date: 2012-02-12 23:29:39 -0600 (Sun, 12 Feb 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "CommonReturns.h"
+#include "cpuPsi.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSI_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+F15TnPmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES    *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION   *PlatformConfig,
+  IN       PCI_ADDR                 PciAddress,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION   OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Entry point for enabling Power Status Indicator
+ *
+ * This function must be run after all P-State routines have been executed
+ *
+ * @param[in]  PsiServices             The current CPU's family services.
+ * @param[in]  EntryPoint              Timepoint designator.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15TnInitializePsi (
+  IN       PSI_FAMILY_SERVICES    *PsiServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR                  PciAddress;
+  CPU_SPECIFIC_SERVICES     *FamilySpecificServices;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    // Configure PsiVid
+    F15TnPmVrmLowPowerModeEnable (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Sets up PSI_L operation.
+ *
+ * This function implements the LowPowerThreshold parameter.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  PciAddress              Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F15TnPmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES    *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION   *PlatformConfig,
+  IN       PCI_ADDR                 PciAddress,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PSTATE_MSR                     PstateMsr;
+  CLK_PWR_TIMING_CTRL2_REGISTER  ClkPwrTimingCtrl2;
+  POWER_CTRL_MISC_REGISTER       PwrCtrlMisc;
+  UINT32                         CoreVrmLowPowerThreshold;
+  UINT32                         Pstate;
+  UINT32                         HwPstateMaxVal;
+  UINT32                         PstateCurrent;
+  UINT32                         NextPstateCurrent;
+  UINT32                         PreviousVid;
+  UINT32                         CurrentVid;
+
+  NB_PSTATE_REGISTER             NbPstateReg;
+  NB_PSTATE_CTRL_REGISTER        NbPsCtrl;
+  MISC_VOLTAGE_REGISTER          MiscVoltageReg;
+  UINT32                         NbVrmLowPowerThreshold;
+  UINT32                         NbPstate;
+  UINT32                         NbPstateMaxVal;
+  UINT32                         NbPstateCurrent;
+  UINT32                         NextNbPstateCurrent;
+  UINT32                         PreviousNbVid;
+  UINT32                         CurrentNbVid;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnPmVrmLowPowerModeEnable\n");
+
+  if (PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold != 0) {
+    // Set up PSI0_L for VDD
+    CoreVrmLowPowerThreshold = PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold;
+    IDS_HDT_CONSOLE (CPU_TRACE, "    Core VRM - LowPowerThreshold: %d\n", CoreVrmLowPowerThreshold);
+    PreviousVid = 0xFF;
+    CurrentVid = 0xFF;
+
+    PciAddress.AddressValue = CPTC2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+    HwPstateMaxVal = ClkPwrTimingCtrl2.PstateMaxVal;
+    ASSERT (HwPstateMaxVal < NM_PS_REG);
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "    HwPstateMaxVal %d\n", HwPstateMaxVal);
+    // Check P-state from P0 to HwPstateMaxVal
+    for (Pstate = 0; Pstate <= HwPstateMaxVal; Pstate++) {
+      FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader);
+
+      LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), (UINT64 *) &PstateMsr, StdHeader);
+      CurrentVid = (UINT32) PstateMsr.CpuVid;
+
+      if (Pstate == HwPstateMaxVal) {
+        NextPstateCurrent = 0;
+      } else {
+        // Check P-state from P1 to HwPstateMaxVal
+        FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader);
+      }
+
+      if ((PstateCurrent <= CoreVrmLowPowerThreshold) &&
+          (NextPstateCurrent <= CoreVrmLowPowerThreshold) &&
+          (CurrentVid != PreviousVid)) {
+        // Program PsiVid and PsiVidEn if PSI state is found and stop searching.
+        PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
+        LibAmdPciRead (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader);
+        PwrCtrlMisc.PsiVid = CurrentVid;
+        PwrCtrlMisc.PsiVidEn = 1;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader);
+        IDS_HDT_CONSOLE (CPU_TRACE, "    PsiVid is enabled at P-state %d. PsiVid: %d\n", Pstate, CurrentVid);
+        break;
+      } else {
+        PstateCurrent = NextPstateCurrent;
+        PreviousVid = CurrentVid;
+      }
+    }
+  }
+
+  if (PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold != 0) {
+    // Set up NBPSI0_L for VDDNB
+    NbVrmLowPowerThreshold = PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold;
+    IDS_HDT_CONSOLE (CPU_TRACE, "    NB VRM - LowPowerThreshold: %d\n", NbVrmLowPowerThreshold);
+    PreviousNbVid = 0xFF;
+    CurrentNbVid = 0xFF;
+
+    PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    NbPstateMaxVal = NbPsCtrl.NbPstateMaxVal;
+    ASSERT (NbPstateMaxVal < NM_NB_PS_REG);
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "    NbPstateMaxVal %d\n", NbPstateMaxVal);
+    for (NbPstate = 0; NbPstate <= NbPstateMaxVal; NbPstate++) {
+      // Check only valid NB P-state
+      if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) NbPstate, &NbPstateCurrent, StdHeader) != TRUE) {
+        continue;
+      }
+
+      PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
+      LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader);
+      CurrentNbVid = (UINT32) GetF15TnNbVid (&NbPstateReg);
+
+      if (NbPstate == NbPstateMaxVal) {
+        NextNbPstateCurrent = 0;
+      } else {
+        // Check only valid NB P-state
+        if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) (NbPstate + 1), &NextNbPstateCurrent, StdHeader) != TRUE) {
+          continue;
+        }
+      }
+
+      if ((NbPstateCurrent <= NbVrmLowPowerThreshold) &&
+          (NextNbPstateCurrent <= NbVrmLowPowerThreshold) &&
+          (CurrentNbVid != PreviousNbVid)) {
+        // Program NbPsi0Vid and NbPsi0VidEn if PSI state is found and stop searching.
+        PciAddress.AddressValue = MISC_VOLTAGES_PCI_ADDR;
+        LibAmdPciRead (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader);
+        MiscVoltageReg.NbPsi0Vid = CurrentNbVid;
+        MiscVoltageReg.NbPsi0VidEn = 1;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader);
+        IDS_HDT_CONSOLE (CPU_TRACE, "    NbPsi0Vid is enabled at NB P-state %d. NbPsi0Vid: %d\n", NbPstate, CurrentNbVid);
+        break;
+      } else {
+        PreviousNbVid = CurrentNbVid;
+      }
+    }
+  }
+}
+
+
+CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport =
+{
+  0,
+  (PF_PSI_IS_SUPPORTED) CommonReturnTrue,
+  F15TnInitializePsi
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
new file mode 100644
index 0000000000..7b6321e67a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
@@ -0,0 +1,766 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Trinity Pstate feature support functions.
+ *
+ * Provides the functions necessary to initialize the Pstate feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15/TN
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuPstateTables.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+#include "cpuF15Utilities.h"
+#include "F15TnUtilities.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F15TnGetPowerStepValueInTime (
+  IN OUT   UINT32  *PowerStepPtr
+  );
+
+VOID
+STATIC
+F15TnGetPllValueInTime (
+  IN OUT   UINT32  *PllLockTimePtr
+  );
+
+AGESA_STATUS
+STATIC
+F15TnGetFrequencyXlatRegInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES  *PstateCpuServices,
+  IN       UINT8                  PStateNumber,
+  IN       UINT32                 Frequency,
+     OUT   UINT32                 *CpuFidPtr,
+     OUT   UINT32                 *CpuDidPtr1,
+     OUT   UINT32                 *CpuDidPtr2,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetPstateTransLatency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetPstateFrequency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetPstatePower (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetPstateMaxState (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+     OUT   UINT32              *MaxPStateNumber,
+     OUT   UINT8               *NumberOfBoostStates,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F15TnGetPstateRegisterInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+     OUT   UINT32              *SwPstateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+BOOLEAN
+STATIC
+F15TnIsPstatePsdDependent (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN                PsdIsDependent;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnIsPstatePsdDependent\n");
+
+  // Family 15h Trinity defaults to dependent PSD; allow Platform Configuration to
+  // overwrite the default setting.
+  PsdIsDependent = TRUE;
+  if (PlatformConfig->ForcePstateIndependent == TRUE) {
+    PsdIsDependent = FALSE;
+  }
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    P-state PSD is dependent: %d\n", PsdIsDependent);
+  return PsdIsDependent;
+}
+
+/**
+ *  Family specific call to set core TscFreqSel.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F15TnSetTscFreqSel (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "    F15TnSetTscFreqSel\n");
+
+  //TscFreqSel: TSC frequency select. Read-only. Reset: 1. 1=The TSC increments at the P0 frequency.
+  //This field uses software P-state numbering.
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to get Pstate Transition Latency.
+ *
+ *  Calculate TransitionLatency by power step value and pll value.
+ *
+ *  @param[in]     PstateCpuServices                 Pstate CPU services.
+ *  @param[in]     PStateLevelingBufferStructPtr     Pstate row data buffer pointer
+ *  @param[in]     PciAddress                        Pci address
+ *  @param[out]    TransitionLatency                 The transition latency.
+ *  @param[in]     StdHeader                         Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F15TnGetPstateTransLatency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32               TempVar_b;
+  UINT32               TempVar_c;
+  UINT32               TempVar_d;
+  UINT32               TempVar8_a;
+  UINT32               TempVar8_b;
+  UINT32               Ignored;
+  UINT32               k;
+  UINT32               CpuFidSameFlag;
+  UINT8                PStateMaxValueOnCurrentCore;
+  UINT32               TransAndBusMastLatency;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPstateTransLatency\n");
+
+  CpuFidSameFlag = 1;
+
+  F15TnGetFrequencyXlatRegInfo (
+    PstateCpuServices,
+    0,
+    PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq,
+    &TempVar_b,
+    &TempVar_c,
+    &Ignored,
+    StdHeader
+    );
+
+  TempVar_d = TempVar_b;
+  PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue;
+
+  //
+  //Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states where
+  //MSRC001_00[6B:64][PstateEn]=1
+  //
+  for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) {
+    if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+      F15TnGetFrequencyXlatRegInfo (
+        PstateCpuServices,
+        (UINT8) k,
+        PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq,
+        &TempVar_b,
+        &TempVar_c,
+        &Ignored,
+        StdHeader
+        );
+    }
+
+    if (TempVar_d != TempVar_b) {
+      CpuFidSameFlag = 0;
+      break;
+    }
+  }
+
+  PciAddress->Address.Register = 0xD4;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
+
+  // PowerStepDown - Bits 20:23
+  TempVar8_a = (TempVar_d & 0x00F00000) >> 20;
+
+  // PowerStepUp   - Bits 24:27
+  TempVar8_b = (TempVar_d & 0x0F000000) >> 24;
+
+  // Convert the raw numbers in TempVar8_a and TempVar8_b into time
+  F15TnGetPowerStepValueInTime (&TempVar8_a);
+  F15TnGetPowerStepValueInTime (&TempVar8_b);
+
+  //
+  //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us
+  //
+  TransAndBusMastLatency =
+  (12 * (TempVar8_a + TempVar8_b) + 999) / 1000;
+
+  if (CpuFidSameFlag == 0) {
+    //
+    //+ F3xA0[PllLockTime]
+    //
+    PciAddress->Address.Register = 0xA0;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
+
+    TempVar8_a = (0x00003800 & TempVar_d) >> 11;
+    F15TnGetPllValueInTime (&TempVar8_a);
+    TransAndBusMastLatency += TempVar8_a;
+  }
+
+  *TransitionLatency = TransAndBusMastLatency;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to calculates the frequency in megahertz of the desired P-state.
+ *
+ *  @param[in]   PstateCpuServices        Pstate CPU services.
+ *  @param[in]   StateNumber              The P-State to analyze.
+ *  @param[out]  FrequencyInMHz           The P-State's frequency in MegaHertz
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS   Always Succeeds.
+ */
+AGESA_STATUS
+F15TnGetPstateFrequency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempValue;
+  UINT32 CpuDid;
+  UINT32 CpuFid;
+  UINT64 LocalMsrRegister;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPstateFrequency - P%d\n", StateNumber);
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1);
+  CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid);
+  CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid);
+
+  switch (CpuDid) {
+  case 0:
+    TempValue = 1;
+    break;
+  case 1:
+    TempValue = 2;
+    break;
+  case 2:
+    TempValue = 4;
+    break;
+  case 3:
+    TempValue = 8;
+    break;
+  case 4:
+    TempValue  =  16;
+    break;
+  default:
+    // CpuDid is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    TempValue = 1;
+    break;
+  }
+  *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FrequencyInMHz=%d, CpuFid=%d, CpuDid=%d\n", *FrequencyInMHz, CpuFid, CpuDid);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to calculates the power in milliWatts of the desired P-state.
+ *
+ *  @param[in]     PstateCpuServices      Pstate CPU services.
+ *  @param[in]   StateNumber              Which P-state to analyze
+ *  @param[out]  PowerInMw                The Power in milliWatts of that P-State
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F15TnGetPstatePower (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  CpuVid;
+  UINT32  IddValue;
+  UINT32  IddDiv;
+  UINT32  V_x100000;
+  UINT32  Power;
+  UINT64  LocalMsrRegister;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPstatePower - P%d\n", StateNumber);
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1);
+  CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid);
+  IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue);
+  IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv);
+
+  if (CpuVid >= 0xF8) {
+    V_x100000 = 0;
+  } else {
+    V_x100000 = 155000L - (625L * CpuVid);
+  }
+
+  Power = V_x100000 * IddValue;
+
+  switch (IddDiv) {
+  case 0:
+    *PowerInMw = Power / 100L;
+    break;
+  case 1:
+    *PowerInMw = Power / 1000L;
+    break;
+  case 2:
+    *PowerInMw = Power / 10000L;
+    break;
+  default:
+    // IddDiv is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    *PowerInMw = 0;
+    break;
+  }
+  IDS_HDT_CONSOLE (CPU_TRACE, "  PowerInMw=%d, CpuVid=%d, IddValue=%d, IddDiv=%d\n", *PowerInMw, CpuVid, IddValue, IddDiv);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to get CPU pstate max state.
+ *
+ *  @param[in]     PstateCpuServices      Pstate CPU services.
+ *  @param[out]    MaxPStateNumber        The max hw pstate value on the current socket.
+ *  @param[out]    NumberOfBoostStates    The number of boosted P-states on the current socket.
+ *  @param[in]     StdHeader              Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F15TnGetPstateMaxState (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+     OUT   UINT32              *MaxPStateNumber,
+     OUT   UINT8               *NumberOfBoostStates,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32               NumBoostStates;
+  UINT64               MsrValue;
+  UINT32               LocalPciRegister;
+  PCI_ADDR             PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPstateMaxState\n");
+
+  LocalPciRegister = 0;
+
+  // For F15 Trinity CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+
+  NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+  *NumberOfBoostStates = (UINT8) NumBoostStates;
+
+  //
+  // Read PstateMaxVal [6:4] from MSR C001_0061
+  // So, we will know the max pstate state in this socket.
+  //
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
+  *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    MaxPStateNumber=%d, NumBoostStates=%d\n", *MaxPStateNumber, NumBoostStates);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to get CPU pstate register information.
+ *
+ *  @param[in]     PstateCpuServices         Pstate CPU services.
+ *  @param[in]     PState                    Input Pstate number for query.
+ *  @param[out]    PStateEnabled             Boolean flag return pstate enable.
+ *  @param[in,out] IddVal                    Pstate current value.
+ *  @param[in,out] IddDiv                    Pstate current divisor.
+ *  @param[out]    SwPstateNumber            Software P-state number.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F15TnGetPstateRegisterInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+     OUT   UINT32              *SwPstateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32    LocalPciRegister;
+  UINT64    LocalMsrRegister;
+  PCI_ADDR  PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPstateRegisterInfo - P%d\n", PState);
+
+  ASSERT (PState < NM_PS_REG);
+
+  // For F15 Trinity CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+
+  // Read PSTATE MSRs
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader);
+
+  *SwPstateNumber = PState;
+
+  if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+    // PState enable = bit 63
+    *PStateEnabled = TRUE;
+    //
+    // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
+    //
+    if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) {
+      *PStateEnabled = FALSE;
+    } else {
+      *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+    }
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Pstate %d is enabled. SwPstateNumber=%d\n", PState, *SwPstateNumber);
+  } else {
+    *PStateEnabled = FALSE;
+  }
+
+  // Bits 39:32 (high 32 bits [7:0])
+  *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue;
+  // Bits 41:40 (high 32 bits [9:8])
+  *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    IddVal=%d, IddDiv=%d\n", *IddVal, *IddDiv);
+  return (AGESA_SUCCESS);
+}
+
+
+CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices =
+{
+  0,
+  (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
+  F15TnIsPstatePsdDependent,
+  F15TnSetTscFreqSel,
+  F15TnGetPstateTransLatency,
+  F15TnGetPstateFrequency,
+  (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
+  F15TnGetPstatePower,
+  F15TnGetPstateMaxState,
+  F15TnGetPstateRegisterInfo
+};
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F15TnGetPowerStepValueInTime
+ *
+ *  Description:
+ *    Convert power step value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PowerStepPtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+F15TnGetPowerStepValueInTime (
+  IN OUT   UINT32  *PowerStepPtr
+  )
+{
+  UINT32 TempVar_a;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPowerStepValueInTime\n");
+
+  TempVar_a = *PowerStepPtr;
+
+  if (TempVar_a < 0x4) {
+    *PowerStepPtr = 400 - (TempVar_a * 100);
+  } else if (TempVar_a <  0x9) {
+    *PowerStepPtr = 130 - (TempVar_a * 10);
+  } else {
+    *PowerStepPtr = 90 - (TempVar_a * 5);
+  }
+  IDS_HDT_CONSOLE (CPU_TRACE, "  PowerStepPtr=%d\n", *PowerStepPtr);
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F15TnGetPllValueInTime
+ *
+ *  Description:
+ *    Convert PLL Value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PllLockTimePtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+F15TnGetPllValueInTime (
+  IN OUT   UINT32  *PllLockTimePtr
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetPllValueInTime\n");
+
+  if (*PllLockTimePtr < 4) {
+    *PllLockTimePtr = *PllLockTimePtr + 1;
+  } else if (*PllLockTimePtr == 4) {
+    *PllLockTimePtr = 8;
+  } else if (*PllLockTimePtr == 5) {
+    *PllLockTimePtr = 16;
+  } else
+    *PllLockTimePtr = 0;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    PllLockTimePtr=%d\n", *PllLockTimePtr);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will return the CpuFid and CpuDid in MHz, using the formula
+ *    described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
+ *
+ *    @param[in]       PstateCpuServices        The current Family Specific Services.
+ *    @param[in]       PStateNumber             P-state number to check.
+ *    @param[in]       Frequency                Leveled target frequency for PStateNumber.
+ *    @param[out]      *CpuFidPtr               New leveled FID.
+ *    @param[out]      *CpuDidPtr1              New leveled DID info 1.
+ *    @param[out]      *CpuDidPtr2              New leveled DID info 2.
+ *    @param[in]       *StdHeader               Header for library and services.
+ *
+ *    @retval       AGESA_WARNING           This P-State does not need to be modified.
+ *    @retval       AGESA_SUCCESS           This P-State must be modified to be level.
+ */
+AGESA_STATUS
+STATIC
+F15TnGetFrequencyXlatRegInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES  *PstateCpuServices,
+  IN       UINT8                  PStateNumber,
+  IN       UINT32                 Frequency,
+     OUT   UINT32                 *CpuFidPtr,
+     OUT   UINT32                 *CpuDidPtr1,
+     OUT   UINT32                 *CpuDidPtr2,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 i;
+  UINT32 j;
+  AGESA_STATUS Status;
+  UINT32 FrequencyInMHz;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F15TnGetFrequencyXlatRegInfo - PstateNumber=%d, Frequency=%d\n", PStateNumber, Frequency);
+
+  FrequencyInMHz = 0;
+  *CpuDidPtr2 = 0xFFFF;
+
+  Status = AGESA_SUCCESS;
+
+  PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader);
+  if (FrequencyInMHz == Frequency) {
+    Status |= AGESA_WARNING;
+  }
+
+  // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid)
+  // In this for loop i = 2^CpuDid
+
+
+  for (i = 1; i < 17; (i += i)) {
+    for (j = 0; j < 64; j++) {
+      if (Frequency == ((100 * (j + 0x10)) / i )) {
+        *CpuFidPtr = j;
+        if (i == 1) {
+          *CpuDidPtr1 = 0;
+        } else if (i == 2) {
+          *CpuDidPtr1 = 1;
+        } else if (i == 4) {
+          *CpuDidPtr1 = 2;
+        } else if (i == 8) {
+          *CpuDidPtr1 = 3;
+        } else if (i == 16) {
+          *CpuDidPtr1 = 4;
+        } else {
+          *CpuFidPtr = 0xFFFF;
+          *CpuDidPtr1 = 0xFFFF;
+        }
+        IDS_HDT_CONSOLE (CPU_TRACE, "  CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2);
+        // Success
+        return Status;
+      }
+    }
+  }
+
+  // Error Condition
+  *CpuFidPtr = 0x00FF;
+  *CpuDidPtr1 = 0x00FF;
+  *CpuDidPtr2 = 0x00FF;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2);
+  return AGESA_ERROR;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
new file mode 100644
index 0000000000..6ffed12323
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
@@ -0,0 +1,207 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 15h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCommonF15Utilities.h"
+#include "cpuF15PowerMgmt.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
+ *
+ *  This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Handle of Header for calling lib functions and services.
+ *  @param[in]  Request                  Indicate warm reset status
+ *
+ */
+VOID
+F15SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  PciData &= ~(HT_INIT_BIOS_RST_DET_0);
+  PciData = PciData | (Request->RequestBit << 5);
+
+  // bit[10,9] - indicate warm reset status and count
+  PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
+  PciData |= Request->StateBits << 9;
+
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
+ *
+ *  This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Config handle for library and services
+ *  @param[out] Request                  Indicate warm reset status
+ *
+ */
+VOID
+F15GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
+  // bit[10,9] - indicate warm reset status and count
+  Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Return a number zero or one, based on the Core ID position in the initial APIC Id.
+ *
+ * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @retval        CoreIdPositionZero      Core Id is not low
+ * @retval        CoreIdPositionOne       Core Id is low
+ */
+CORE_ID_POSITION
+F15CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64 InitApicIdCpuIdLo;
+
+  //  Check bit_54 [InitApicIdCpuIdLo] to find core id position.
+  LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
+  InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
+  return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h
new file mode 100644
index 0000000000..c802f8be6a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 15h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_COMMON_F15_UTILITES_H_
+#define _CPU_COMMON_F15_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+CORE_ID_POSITION
+F15CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F15SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+VOID
+F15GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  );
+
+#endif  // _CPU_COMMON_F15_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c
new file mode 100644
index 0000000000..439a6ef6d9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 APM Initialization
+ *
+ * Enables Application Power Management feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF15PowerMgmt.h"
+#include "CommonReturns.h"
+#include "cpuApm.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Entry point for enabling Application Power Management
+ *
+ * This function must be run after all P-State routines have been executed
+ *
+ * @param[in]  ApmServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F15InitializeApm (
+  IN       APM_FAMILY_SERVICES    *ApmServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   LocalPciRegister;
+  PCI_ADDR PciAddress;
+
+  PciAddress.Address.Function = FUNC_4;
+  PciAddress.Address.Register = CPB_CTRL_REG;
+  LocalPciRegister = 0;
+  ((F15_CPB_CTRL_REGISTER *) (&LocalPciRegister))->ApmMasterEn = 1;
+  OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0xFFFFFFFF, LocalPciRegister, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+
+CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport =
+{
+  0,
+  (PF_APM_IS_SUPPORTED) CommonReturnTrue,
+  F15InitializeApm
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
new file mode 100644
index 0000000000..006111f611
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
@@ -0,0 +1,249 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuEarlyInit.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NAME_STRING_ADDRESS_PORT 0x194
+#define NAME_STRING_DATA_PORT 0x198
+
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// A structure containing brand string
+typedef struct {
+  CONST CHAR8 *Stringstart;  ///< The literal string
+} CPU_F15_EXCEPTION_BRAND;
+
+/// FAM15_BRAND_STRING_MSR
+typedef struct _PROCESSOR_NAME_STRING {
+  UINT32 lo;                 ///< lower 32-bits of 64-bit value
+  UINT32 hi;                 ///< highest 32-bits of 64-bit value
+} PROCESSOR_NAME_STRING;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+IsException (
+     OUT   UINT32             *ExceptionId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F15SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+// This is an example, need to be updated once Processor Revision Guide define brand string exception
+// Brand string is always 48 bytes
+CONST CHAR8 ROMDATA str_Exception_0[48] = "AMD Phenom(tm) Octal-Core";
+CONST CHAR8 ROMDATA str_Unprogrammed_Sample[48] = "AMD Unprogrammed Engineering Sample";
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+CONST CPU_F15_EXCEPTION_BRAND ROMDATA CpuF15ExceptionBrandIdString[] =
+{
+  {str_Exception_0}
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the Processor Name String register based on F5x194/198
+ *
+ * This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+F15SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 PciData;
+  UINT32 ExceptionId;
+  UINT32 MsrIndex;
+  UINT64 MsrData;
+  UINT64 *MsrNameStringPtrPtr;
+  PCI_ADDR PciAddress;
+
+  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    if (IsException (&ExceptionId, StdHeader)) {
+      ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0])));
+
+      MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart;
+    } else {
+      OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+      PciAddress.Address.Function = FUNC_5;
+      PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
+      // check if D18F5x198_x0 is 00000000h.
+      PciData = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+      PciAddress.Address.Register = NAME_STRING_DATA_PORT;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+      if (PciData != 0) {
+        for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
+          PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
+          PciData = MsrIndex * 2;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+          PciAddress.Address.Register = NAME_STRING_DATA_PORT;
+          LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+          ((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
+
+          PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
+          PciData = (MsrIndex * 2) + 1;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+          PciAddress.Address.Register = NAME_STRING_DATA_PORT;
+          LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+          ((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
+
+          LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
+        }
+        return;
+      } else {
+        // It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
+        MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
+      }
+    }
+    // Put values into name MSRs,  Always write the full 48 bytes
+    for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
+      LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
+      MsrNameStringPtrPtr++;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Check if it's an exception
+ *
+ * For family 15h, brand string is obtained from F5x198_x[B:0], but there may be exceptions.
+ * This function checks if it's an exception.
+ *
+ *  @param[out]  ExceptionId         Id of exception
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ *  @retval      TRUE                It's an exception
+ *  @retval      FALSE               It's NOT an exception
+ */
+BOOLEAN
+STATIC
+IsException (
+     OUT   UINT32                 *ExceptionId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  // This function will be updated, once Processor Revision Guide defines Fam15 brand string exception
+  *ExceptionId = 0xFFFF;
+
+  return FALSE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
new file mode 100644
index 0000000000..9870ec7ab4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
@@ -0,0 +1,224 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 ROM Execution Cache Defaults
+ *
+ * Contains default values for ROM execution cache setup
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF15CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+#define MEM_TRAINING_BUFFER_SIZE  16384
+#define VAR_MTRR_MASK             0x0000FFFFFFFFFFFFul
+#define VAR_MTRR_MASK_CP          0x0000FFFFFFFEFFFFul
+
+#define HEAP_BASE_MASK_CP         0x0000FFFFFFFEFF00ul
+#define HEAP_BASE_MASK            0x0000FFFFFFFFFFFFul
+
+#define SHARED_MEM_SIZE       0
+
+CONST CACHE_INFO ROMDATA CpuF15CacheInfo =
+{
+  BSP_STACK_SIZE_64K,
+  CORE0_STACK_SIZE,
+  CORE1_STACK_SIZE,
+  MEM_TRAINING_BUFFER_SIZE,
+  SHARED_MEM_SIZE,
+  VAR_MTRR_MASK,
+  VAR_MTRR_MASK,
+  HEAP_BASE_MASK,
+  InfiniteExe
+};
+
+CONST CACHE_INFO ROMDATA CpuF15CacheInfoCP =
+{
+  BSP_STACK_SIZE_64K,
+  CORE0_STACK_SIZE,
+  CORE1_STACK_SIZE,
+  MEM_TRAINING_BUFFER_SIZE,
+  SHARED_MEM_SIZE,
+  VAR_MTRR_MASK,
+  VAR_MTRR_MASK_CP,
+  HEAP_BASE_MASK_CP,
+  InfiniteExe
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific properties of the cache, and its usage.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  CacheInfoPtr             Points to the cache info properties on exit.
+ *  @param[out]  NumberOfElements         Will be one to indicate one entry.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF15CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Enabled;
+  UINT32 DualCore;
+  UINT32 Node;
+  PCI_ADDR  PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+  AP_MAILBOXES     ApMailboxes;
+  CORE_PAIR_MAP *CorePairMap;
+  AGESA_STATUS IgnoredStatus;
+
+  if (!IsBsp (StdHeader, &IgnoredStatus)) {
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+
+    FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
+    Node = ApMailboxes.ApMailInfo.Fields.Node;
+
+    // Since pre-heap, get compute unit status from hardware, using mailbox info.
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    PciAddress.Address.Device = PciAddress.Address.Device + Node;
+    PciAddress.Address.Function = FUNC_5;
+    PciAddress.Address.Register = COMPUTE_UNIT_STATUS;
+    LibAmdPciReadBits (PciAddress, 3, 0, &Enabled, StdHeader);
+    LibAmdPciReadBits (PciAddress, 19, 16, &DualCore, StdHeader);
+
+    // Find the core to compute unit mapping for this node.
+    CorePairMap = FamilyServices->CorePairMap;
+    if ((Enabled != 0) && (CorePairMap != NULL)) {
+      while (CorePairMap->Enabled != 0xFF) {
+        if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) {
+          break;
+        }
+        CorePairMap++;
+      }
+      // The assert is for finding a processor configured in a way the core pair map doesn't support.
+      ASSERT (CorePairMap->Enabled != 0xFF);
+      switch (CorePairMap->Mapping) {
+      case AllCoresMapping:
+        // No cores are sharing a compute unit
+        *CacheInfoPtr = &CpuF15CacheInfo;
+        break;
+      case EvenCoresMapping:
+        // Cores are paired into compute units
+        *CacheInfoPtr = &CpuF15CacheInfoCP;
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+    }
+  } else {
+    // the BSC is always just the first slice, we could return either one. Return the non for safest.
+    *CacheInfoPtr = &CpuF15CacheInfo;
+  }
+  *NumberOfElements = 1;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
new file mode 100644
index 0000000000..1f4efa797c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
@@ -0,0 +1,278 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CRAT Record Creation API, and related functions for Family 15h.
+ *
+ * Contains code that produce the CRAT related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuLateInit.h"
+#include "OptionCrat.h"
+#include "cpuCrat.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST UINT8 ROMDATA L2L3Associativity[];
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  generate CRAT cache entry for F15 processor
+ *
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+VOID
+STATIC
+F15GenerateCratCacheEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8     i;
+  UINT8     NodeNum;
+  UINT8     NodeCount;
+  UINT8     CoreNumPerCU;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    CoreNum;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    RegVal;
+  CPUID_DATA L1CpuId;
+  CPUID_DATA L2L3CpuId;
+  CRAT_CACHE *EntryPtr;
+  AMD_APIC_PARAMS ApicParams;
+  PCI_ADDR  PciAddress;
+
+  // Get Node count
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, 0x60);
+  LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader);
+  NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1);
+
+  // Get compute unit info
+  switch (GetComputeUnitMapping (StdHeader)) {
+  case AllCoresMapping:
+    CoreNumPerCU = 1;
+    break;
+  case EvenCoresMapping:
+    CoreNumPerCU = 2;
+    break;
+  default:
+    CoreNumPerCU = 1;
+  }
+  // Get L1 L2 cache information from CPUID
+  LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &L1CpuId, StdHeader);
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &L2L3CpuId, StdHeader);
+
+  NodeNum = 0;
+  ApicParams.StdHeader = *StdHeader;
+  while (NodeNum < NodeCount) {
+    GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader);
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+
+    for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) {
+      ApicParams.Socket = (UINT8) Socket;
+      ApicParams.Core = (UINT8) CoreNum;
+      AmdGetApicId (&ApicParams);
+      if (ApicParams.IsPresent) {
+        // L1 Data cache
+        EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader);
+        EntryPtr->Flags.Enabled = 1;
+        EntryPtr->Flags.DataCache = 1;
+        EntryPtr->Flags.CpuCache = 1;
+        EntryPtr->ProcessorIdLow = ApicParams.ApicAddress;
+        i = ApicParams.ApicAddress / 8;
+        EntryPtr->SiblingMap[i] = 1 << (ApicParams.ApicAddress % 8);
+        EntryPtr->CacheSize = L1CpuId.ECX_Reg >> 24; // bits[31:24] L1 data cache size
+        EntryPtr->CacheLevel = 1;
+        EntryPtr->LinesPerTag = (UINT8) ((L1CpuId.ECX_Reg >> 8) & 0xFF); // bits[15:8] L1 data cache lines per tag;
+        EntryPtr->CacheLineSize = (UINT16) (L1CpuId.ECX_Reg & 0xFF); // bits[7:0] L1 data cache line size;
+        EntryPtr->Associativity = (UINT8) ((L1CpuId.ECX_Reg >> 16) & 0xFF); // bits[23:16] L1 data cache associativity;
+        /// @todo which value should set here?
+        //EntryPtr->CacheProperties = ;
+        EntryPtr->CacheLatency = 1;
+
+        if (CoreNum % CoreNumPerCU == 0) {
+          // L1 Instruction cache, shared by compute unit
+          EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader);
+          EntryPtr->Flags.Enabled = 1;
+          EntryPtr->Flags.DataCache = 1;
+          EntryPtr->Flags.CpuCache = 1;
+          EntryPtr->ProcessorIdLow = ApicParams.ApicAddress;
+          i = ApicParams.ApicAddress / 8;
+          EntryPtr->SiblingMap[i] = 3 << (ApicParams.ApicAddress % 8);
+          EntryPtr->CacheSize = L1CpuId.EDX_Reg >> 24; // bits[31:24] L1 instruction cache size
+          EntryPtr->CacheLevel = 1;
+          EntryPtr->LinesPerTag = (UINT8) ((L1CpuId.EDX_Reg >> 8) & 0xFF); // bits[15:8] L1 instruction cache lines per tag
+          EntryPtr->CacheLineSize = (UINT16) (L1CpuId.EDX_Reg & 0xFF); // bits[7:0] L1 data instruction line size
+          EntryPtr->Associativity = (UINT8) ((L1CpuId.EDX_Reg >> 16) & 0xFF); // bits[23:16] L1 instruction cache associativity
+          /// @todo which value should be set here?
+          //EntryPtr->CacheProperties = ;
+          EntryPtr->CacheLatency = 1;
+
+          // L2 cache, shared by compute unit
+          EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader);
+          EntryPtr->Flags.Enabled = 1;
+          EntryPtr->Flags.CpuCache = 1;
+          EntryPtr->ProcessorIdLow = ApicParams.ApicAddress;
+          i = ApicParams.ApicAddress / 8;
+          EntryPtr->SiblingMap[i] = 3 << (ApicParams.ApicAddress % 8);
+          EntryPtr->CacheSize = L2L3CpuId.ECX_Reg >> 16; // bits[31:16] L2 cache size
+          EntryPtr->CacheLevel = 2;
+          EntryPtr->LinesPerTag = (UINT8) ((L2L3CpuId.ECX_Reg >> 8) & 0xF); // bits[11:8] L2 cache lines per tag
+          EntryPtr->CacheLineSize = (UINT16) (L2L3CpuId.ECX_Reg & 0xFF); // bits[7:0] L2 cache line size
+          EntryPtr->Associativity = L2L3Associativity[(L2L3CpuId.ECX_Reg >> 12) & 0xF]; // bits[15:12] L2 cache associativity
+        }
+        // L3 cache, shared by node
+        // bits[31:18] L3 cache size
+        if (((L2L3CpuId.EDX_Reg & 0xFFFC0000) != 0) && (CoreNum == 0)) {
+          EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader);
+          EntryPtr->Flags.Enabled = 1;
+          EntryPtr->Flags.CpuCache = 1;
+          EntryPtr->ProcessorIdLow = ApicParams.ApicAddress;
+          i = ApicParams.ApicAddress / 8;
+          EntryPtr->SiblingMap[i] = ((1 << (UINT8) (HighCore - LowCore + 1)) - 1) << (ApicParams.ApicAddress % 8);
+          EntryPtr->CacheSize = (L2L3CpuId.EDX_Reg >> 18) * 512; // bits[31:18] L3 cache size
+          EntryPtr->CacheLevel = 3;
+          EntryPtr->LinesPerTag = (UINT8) ((L2L3CpuId.EDX_Reg >> 8) & 0xF); // bits[11:8] L3 cache lines per tag
+          EntryPtr->CacheLineSize = (UINT16) (L2L3CpuId.EDX_Reg & 0xFF); // bits[7:0] L3 cache line size
+          EntryPtr->Associativity = L2L3Associativity[(L2L3CpuId.EDX_Reg >> 12) & 0xF]; // bits[15:12] L3 cache associativity
+
+        }
+      }
+    }
+
+    NodeNum++;
+  }
+
+  return;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  generate CRAT TLB entry for F15 processor
+ *
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+VOID
+STATIC
+F15GenerateCratTLBEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  return;
+}
+
+CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport =
+{
+    0,
+    F15GenerateCratCacheEntry,
+    F15GenerateCratTLBEntry
+};
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c
new file mode 100644
index 0000000000..c2f1e3322f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c
@@ -0,0 +1,150 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions for Family 15h.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuLateInit.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuServices.h"
+#include "cpuF15Dmi.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF15GetMaxSpeed
+ *
+ *    Get the Max Speed
+ *
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ *    @retval  MaxSpeed   - CPU Max Speed.
+ *
+ */
+UINT16
+DmiF15GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 NumBoostStates;
+  UINT32 P0Frequency;
+  UINT32 PciData;
+  PCI_ADDR PciAddress;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+
+  FamilyServices = NULL;
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+  NumBoostStates = (UINT8) ((PciData >> 2) & 7);
+
+  FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
+  return ((UINT16) P0Frequency);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.h
new file mode 100644
index 0000000000..41202ec3ce
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.h
@@ -0,0 +1,103 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions for Family 15h.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_DMI_H_
+#define _CPU_F15_DMI_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT16
+DmiF15GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#endif  // _CPU_F15_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
new file mode 100644
index 0000000000..9e19d80865
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
@@ -0,0 +1,392 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 MMIO map manager
+ *
+ * manage MMIO base/limit registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F15
+ * @e \$Revision: 63522 $   @e \$Date: 2011-12-25 20:25:03 -0600 (Sun, 25 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "mmioMapManager.h"
+#include "cpuF15MmioMap.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST UINT16 ROMDATA MmioBaseLowRegOffset[MMIO_REG_PAIR_NUM] = {0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8, 0x1A0, 0x1A8, 0x1B0, 0x1B8};
+STATIC CONST UINT16 ROMDATA MmioLimitLowRegOffset[MMIO_REG_PAIR_NUM] = {0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0x1A4, 0x1AC, 0x1B4, 0x1BC};
+STATIC CONST UINT16 ROMDATA MmioBaseLimitHiRegOffset[MMIO_REG_PAIR_NUM] = {0x180, 0x184, 0x188, 0x18C, 0x190, 0x194, 0x198, 0x19C, 0x1C0, 0x1C4, 0x1C8, 0x1CC};
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for for adding MMIO map
+ *
+ * program MMIO base/limit registers
+ *
+ * @param[in]    MmioMapServices    MMIO map manager services.
+ * @param[in]    AmdAddMmioParams   Pointer to a data structure containing the parameter information.
+ *
+ * @retval       AGESA_STATUS       AGESA_ERROR       - The requested range could not be added because there are not
+ *                                                      enough mapping resources.
+ *                                  AGESA_BOUNDS_CHK  - One or more input parameters are invalid. For example, the
+ *                                                      TargetAddress does not correspond to any device in the system.
+ *                                  AGESA_SUCCESS     - Adding MMIO map succeeds
+ */
+AGESA_STATUS
+STATIC
+cpuF15AddingMmioMap (
+  IN       MMIO_MAP_FAMILY_SERVICES *MmioMapServices,
+  IN       AMD_ADD_MMIO_PARAMS AmdAddMmioParams
+  )
+{
+  UINT8               i;
+  UINT8               j;
+  UINT8               Socket;
+  UINT8               Module;
+  UINT8               MmioPair;
+  UINT8               ConfMapRange;
+  AGESA_STATUS        IgnoredSts;
+  PCI_ADDR            PciAddress;
+  MMIO_BASE_LOW       MmioBaseLow;
+  MMIO_LIMIT_LOW      MmioLimitLow;
+  MMIO_BASE_LIMIT_HI  MmioBaseLimitHi;
+  MMIO_RANGE          MmioRange[MMIO_REG_PAIR_NUM];
+  MMIO_RANGE          MmioRangeTemp;
+  MMIO_RANGE          NewMmioRange;
+  CONFIGURATION_MAP   ConfMapRegister;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, FUNC_1, MmioBaseLowRegOffset[0]);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "MMIO map configuration before merging:\n");
+  IDS_HDT_CONSOLE (MAIN_FLOW, "    Base                 Limit               NP RE WE Lock DstNode DstLink DstSubLink\n");
+  for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+    // MMIO base low
+    PciAddress.Address.Register = MmioBaseLowRegOffset[MmioPair];
+    LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+    // MMIO limit low
+    PciAddress.Address.Register = MmioLimitLowRegOffset[MmioPair];
+    LibAmdPciRead (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader));
+    // MMIO base/limit high
+    PciAddress.Address.Register = MmioBaseLimitHiRegOffset[MmioPair];
+    LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLimitHi, &(AmdAddMmioParams.StdHeader));
+    // get MMIO info
+    MmioRange[MmioPair].Base = (MmioBaseLow.MmioBase << 16) | (((UINT64) MmioBaseLimitHi.MmioBase) << 40);
+    MmioRange[MmioPair].Limit = ((MmioLimitLow.MmioLimit << 16) | (((UINT64) MmioBaseLimitHi.MmioLimit) << 40)) + 0x10000;
+    MmioRange[MmioPair].Attribute.MmioPostedRange =  (UINT8) MmioLimitLow.NP;
+    MmioRange[MmioPair].Attribute.MmioReadableRange = (UINT8) MmioBaseLow.RE;
+    MmioRange[MmioPair].Attribute.MmioWritableRange =  (UINT8) MmioBaseLow.WE;
+    MmioRange[MmioPair].Attribute.MmioSecuredRange =  (UINT8) MmioBaseLow.Lock;
+    MmioRange[MmioPair].Destination.DstNode = MmioLimitLow.DstNode;
+    MmioRange[MmioPair].Destination.DstLink = MmioLimitLow.DstLink;
+    MmioRange[MmioPair].Destination.DstSubLink = MmioLimitLow.DstSubLink;
+    MmioRange[MmioPair].RangeNum = MmioPair;
+    MmioRange[MmioPair].Modified = FALSE;
+    IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
+    IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x    %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
+                                                         MmioRange[MmioPair].Base & 0xFFFFFFFF,
+                                                        (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
+                                                         MmioRange[MmioPair].Limit & 0xFFFFFFFF);
+    IDS_HDT_CONSOLE (MAIN_FLOW, "    %s  %s  %s  %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N",
+                                                      MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N",
+                                                      MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N",
+                                                      MmioRange[MmioPair].Attribute.MmioSecuredRange ? "Y" : "N");
+    IDS_HDT_CONSOLE (MAIN_FLOW, "    %02d      %02d      %02d\n", MmioRange[MmioPair].Destination.DstNode,
+                                                                  MmioRange[MmioPair].Destination.DstLink,
+                                                                  MmioRange[MmioPair].Destination.DstSubLink);
+  }
+
+  // parse requirement
+  NewMmioRange.Base = AmdAddMmioParams.BaseAddress;
+  NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length + 0x10000;
+  NewMmioRange.Attribute = AmdAddMmioParams.Attributes;
+  IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x    %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF,
+                                                         NewMmioRange.Base & 0xFFFFFFFF,
+                                                        (NewMmioRange.Limit >> 32) & 0xFFFFFFFF,
+                                                         NewMmioRange.Limit & 0xFFFFFFFF);
+  for (ConfMapRange = 0; ConfMapRange < CONF_MAP_NUM; ConfMapRange++) {
+    PciAddress.Address.Register = (CONF_MAP_RANGE_0 + ConfMapRange * 4);
+    LibAmdPciRead (AccessWidth32, PciAddress, &ConfMapRegister, &(AmdAddMmioParams.StdHeader));
+    if ((ConfMapRegister.BusNumBase <= AmdAddMmioParams.TargetAddress.Address.Bus) &&
+        (ConfMapRegister.BusNumLimit >= AmdAddMmioParams.TargetAddress.Address.Bus)) {
+      NewMmioRange.Destination.DstNode = ConfMapRegister.DstNode;
+      NewMmioRange.Destination.DstLink = ConfMapRegister.DstLink;
+      NewMmioRange.Destination.DstSubLink = ConfMapRegister.DstSubLink;
+      break;
+    }
+  }
+
+  if (ConfMapRange == CONF_MAP_NUM) {
+    // AmdAddMmioParams.TargetAddress doesn't belong to any node
+    return AGESA_BOUNDS_CHK;
+  }
+
+  // sort by base address
+  //    range0, range1, range2, non used, non used...
+  for (i = 0; i < (MMIO_REG_PAIR_NUM - 1); i++) {
+    for (j = 0; j < (MMIO_REG_PAIR_NUM - i - 1); j++) {
+      if (((MmioRange[j].Base > MmioRange[j + 1].Base) && ((MmioRange[j + 1].Attribute.MmioReadableRange != 0) || (MmioRange[j + 1].Attribute.MmioWritableRange != 0))) ||
+          (((MmioRange[j].Attribute.MmioReadableRange == 0) && (MmioRange[j].Attribute.MmioWritableRange == 0)) &&
+          ((MmioRange[j + 1].Attribute.MmioReadableRange != 0) || (MmioRange[j + 1].Attribute.MmioWritableRange != 0)))) {
+        MmioRangeTemp = MmioRange[j];
+        MmioRange[j] = MmioRange[j + 1];
+        MmioRange[j + 1] = MmioRangeTemp;
+      }
+    }
+  }
+
+  // merge the request to current setting
+  for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+    if (MmioRange[MmioPair].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair].Attribute.MmioWritableRange != 0) {
+      if (((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Base)) ||
+          ((MmioRange[MmioPair].Base <= NewMmioRange.Base) && (MmioRange[MmioPair].Limit >= NewMmioRange.Base))) {
+        if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair].Attribute.MmioPostedRange) &&
+            (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair].Attribute.MmioReadableRange) &&
+            (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair].Attribute.MmioWritableRange) &&
+            (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair].Attribute.MmioSecuredRange) &&
+            (NewMmioRange.Destination.DstNode == MmioRange[MmioPair].Destination.DstNode) &&
+            (NewMmioRange.Destination.DstLink == MmioRange[MmioPair].Destination.DstLink) &&
+            (NewMmioRange.Destination.DstSubLink == MmioRange[MmioPair].Destination.DstSubLink)) {
+
+//  Original sorted MMIO register pair defined ranges:
+//                                          ____________            ________          ____________
+//                                          |          |            |      |          |          |
+//                                        base0      limit0       base1  limit1     base2      limit2
+//  Requested MMIO range:
+//    case 1:
+//     ((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Base))
+//                                                              __________
+//                                                              |        |
+//                                                         new base   new limit
+//                                                              ____________________
+//                                                              |                  |
+//                                                         new base             new limit
+//    case 2:
+//    ((MmioRange[MmioPair].Base <= NewMmioRange.Base) && (MmioRange[MmioPair].Limit >= NewMmioRange.Base))
+//                                                                                       ____________
+//                                                                                       |          |
+//                                                                                   new base   new limit
+
+          MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base;
+          MmioRange[MmioPair].Modified = TRUE;
+          for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) {
+            if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) &&
+            (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) &&
+            (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) &&
+            (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair + i].Attribute.MmioSecuredRange) &&
+            (NewMmioRange.Destination.DstNode == MmioRange[MmioPair + i].Destination.DstNode) &&
+            (NewMmioRange.Destination.DstLink == MmioRange[MmioPair + i].Destination.DstLink) &&
+            (NewMmioRange.Destination.DstSubLink == MmioRange[MmioPair + i].Destination.DstSubLink)) {
+              MmioRange[MmioPair + i].Base = 0;
+              MmioRange[MmioPair + i].Limit = 0x10000;
+              MmioRange[MmioPair + i].Attribute.MmioReadableRange = 0;
+              MmioRange[MmioPair + i].Attribute.MmioWritableRange = 0;
+              MmioRange[MmioPair + i].Modified = TRUE;
+            } else if (MmioRange[MmioPair + i].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair + i].Attribute.MmioWritableRange != 0) {
+              // Overlapped MMIO regions with different attributes are not allowed
+              return AGESA_ERROR;
+            }
+          }
+          MmioRange[MmioPair].Limit = (MmioRange[MmioPair + i - 1].Limit >= NewMmioRange.Limit) ? MmioRange[MmioPair + i - 1].Limit : NewMmioRange.Limit;
+          break;
+        } else {
+          // Overlapped MMIO regions with different attributes are not allowed
+          return AGESA_ERROR;
+        }
+      }
+    } else {
+
+//  Original sorted MMIO register pair defined ranges:
+//                                          ____________            ________          ____________
+//                                          |          |            |      |          |          |
+//                                        base0      limit0       base1  limit1     base2      limit2
+//  Requested MMIO range:
+//    case 3:
+//     No overlapping area with the original ranges
+//                    ____________
+//                    |          |
+//                new base   new limit
+//                                                                                                        ______________
+//                                                                                                        |            |
+//                                                                                                    new base     new limit
+
+      MmioRange[MmioPair].Base = NewMmioRange.Base;
+      MmioRange[MmioPair].Limit = NewMmioRange.Limit;
+      MmioRange[MmioPair].Attribute = NewMmioRange.Attribute;
+      MmioRange[MmioPair].Destination = NewMmioRange.Destination;
+      MmioRange[MmioPair].Modified = TRUE;
+
+      break;
+    }
+  }
+
+  if (MmioPair == MMIO_REG_PAIR_NUM) {
+    return AGESA_ERROR;
+  }
+
+  // write back MMIO base/limit
+  IDS_HDT_CONSOLE (MAIN_FLOW, "MMIO map configuration after merging:\n");
+  IDS_HDT_CONSOLE (MAIN_FLOW, "    Base                 Limit               NP RE WE Lock DstNode DstLink DstSubLink\n");
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, &(AmdAddMmioParams.StdHeader))) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (&(AmdAddMmioParams.StdHeader), Socket, Module, &PciAddress, &IgnoredSts)) {
+          PciAddress.Address.Function = FUNC_1;
+          for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+            IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
+            IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x    %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
+                                                                 MmioRange[MmioPair].Base & 0xFFFFFFFF,
+                                                                (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
+                                                                 MmioRange[MmioPair].Limit & 0xFFFFFFFF);
+            IDS_HDT_CONSOLE (MAIN_FLOW, "    %s  %s  %s  %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N",
+                                                              MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N",
+                                                              MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N",
+                                                              MmioRange[MmioPair].Attribute.MmioSecuredRange ? "Y" : "N");
+            IDS_HDT_CONSOLE (MAIN_FLOW, "    %02d      %02d      %02d\n", MmioRange[MmioPair].Destination.DstNode,
+                                                                          MmioRange[MmioPair].Destination.DstLink,
+                                                                          MmioRange[MmioPair].Destination.DstSubLink);
+            if (MmioRange[MmioPair].Modified) {
+              // MMIO base low
+              PciAddress.Address.Register = MmioBaseLowRegOffset[MmioRange[MmioPair].RangeNum];
+              LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+              if (MmioBaseLow.Lock == 1) {
+                return AGESA_ERROR;
+              }
+              // Disable RE/WE before changing the address range
+              MmioBaseLow.RE = 0;
+              MmioBaseLow.WE = 0;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLow);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+
+              IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioBaseLowRegOffset[MmioRange[MmioPair].RangeNum]);
+              MmioBaseLow.MmioBase = (UINT32) (MmioRange[MmioPair].Base >> 16) & 0xFFFFFFul;
+              MmioBaseLow.RE = MmioRange[MmioPair].Attribute.MmioReadableRange;
+              MmioBaseLow.WE = MmioRange[MmioPair].Attribute.MmioWritableRange;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLow);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+
+              // MMIO limit low
+              IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioLimitLowRegOffset[MmioRange[MmioPair].RangeNum]);
+              PciAddress.Address.Register = MmioLimitLowRegOffset[MmioRange[MmioPair].RangeNum];
+              LibAmdPciRead (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader));
+              MmioLimitLow.MmioLimit = (UINT32) ((MmioRange[MmioPair].Limit - 1) >> 16) & 0xFFFFFFul;
+              MmioLimitLow.NP = MmioRange[MmioPair].Attribute.MmioPostedRange;
+              MmioLimitLow.DstNode = MmioRange[MmioPair].Destination.DstNode;
+              MmioLimitLow.DstLink = MmioRange[MmioPair].Destination.DstLink;
+              MmioLimitLow.DstSubLink = MmioRange[MmioPair].Destination.DstSubLink;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioLimitLow);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader));
+
+              // MMIO base/limit high
+              IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioBaseLimitHiRegOffset[MmioRange[MmioPair].RangeNum]);
+              PciAddress.Address.Register = MmioBaseLimitHiRegOffset[MmioRange[MmioPair].RangeNum];
+              LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLimitHi, &(AmdAddMmioParams.StdHeader));
+              MmioBaseLimitHi.MmioBase = (UINT32) (MmioRange[MmioPair].Base >> 40) & 0xFFul;
+              MmioBaseLimitHi.MmioLimit = (UINT32) ((MmioRange[MmioPair].Limit - 1) >> 40) & 0xFFul;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLimitHi);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLimitHi, &(AmdAddMmioParams.StdHeader));
+            }
+          }
+        }
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport =
+{
+  0,
+  cpuF15AddingMmioMap
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.h
new file mode 100644
index 0000000000..ae74ee8687
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.h
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 MMIO map manager
+ *
+ * manage MMIO base/limit registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_MMIO_MAP_H_
+#define _CPU_F15_MMIO_MAP_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define MMIO_REG_PAIR_NUM     12
+
+#define CONF_MAP_RANGE_0      0xE0
+#define CONF_MAP_RANGE_1      0xE4
+#define CONF_MAP_RANGE_2      0xE8
+#define CONF_MAP_RANGE_3      0xEC
+#define CONF_MAP_NUM          4
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// MMIO base low
+typedef struct {
+  UINT32 RE:1;          ///< Read enable
+  UINT32 WE:1;          ///< Write enable
+  UINT32 CpuDis:1;      ///< CPU Disable
+  UINT32 Lock:1;        ///< Lock
+  UINT32 :4;            ///< Reserved
+  UINT32 MmioBase:24;   ///< MMIO base address register bits[39:16]
+} MMIO_BASE_LOW;
+
+/// MMIO limit low
+typedef struct {
+  UINT32 DstNode:3;     ///< Destination node ID bits
+  UINT32 :1;            ///< Reserved
+  UINT32 DstLink:2;     ///< Destination link ID
+  UINT32 DstSubLink:1;  ///< Destination sublink
+  UINT32 NP:1;          ///< Non-posted
+  UINT32 MmioLimit:24;  ///< MMIO limit address register bits[39:16]
+} MMIO_LIMIT_LOW;
+
+/// MMIO base/limit high
+typedef struct {
+  UINT32 MmioBase:8;    ///< MMIO base address register bits[47:40]
+  UINT32 :8;            ///< Reserved
+  UINT32 MmioLimit:8;   ///< MMIO limit address register bits[47:40]
+  UINT32 :8;            ///< Reserved
+} MMIO_BASE_LIMIT_HI;
+
+/// MMIO base/limit high
+typedef struct {
+  UINT32 RE:1;          ///< Read enable
+  UINT32 WE:1;          ///< Write enable
+  UINT32 DevCmpEn:1;    ///< Device number compare mode enable
+  UINT32 :1;            ///< Reserved
+  UINT32 DstNode:3;     ///< Destination node ID bits
+  UINT32 :1;            ///< Reserved
+  UINT32 DstLink:2;     ///< Destination link ID
+  UINT32 DstSubLink:1;  ///< Destination sublink
+  UINT32 :5;            ///< Reserved
+  UINT32 BusNumBase:8;  ///< Bus number base bits
+  UINT32 BusNumLimit:8; ///< Bus number limit bits
+} CONFIGURATION_MAP;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_F15_MMIO_MAP_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c
new file mode 100644
index 0000000000..8c7474f459
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c
@@ -0,0 +1,161 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15MsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_HWCR (0xC0010015)
+// bit[4] = 1
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_HWCR,                              // MSR Address
+      0x0000000000000010,                    // OR Mask
+      0x0000000000000010,                    // NAND Mask
+    }}
+  },
+// MSR_NB_CFG (0xC001001F)
+// bit[54] InitApicIdCpuIdLo = 1
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_NB_CFG,                            // MSR Address
+      0x0040000000000000,                    // OR Mask
+      0x0040000000000000,                    // NAND Mask
+    }}
+  },
+// This MSR should be set after the code that most errata would be applied in
+// MSR_MC0_CTL (0x00000400)
+// bits[63:0]  = 0xFFFFFFFFFFFFFFFF
+  {
+    MsrRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_MC0_CTL,                           // MSR Address
+      0xFFFFFFFFFFFFFFFF,                    // OR Mask
+      0xFFFFFFFFFFFFFFFF,                    // NAND Mask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable = {
+  AllCores,
+  (sizeof (F15MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *)F15MsrRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PciTables.c
new file mode 100644
index 0000000000..6ef2ef5e01
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PciTables.c
@@ -0,0 +1,216 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15  PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15PciRegisters[] =
+{
+// F2x1B0 - Extended Memory Controller Configuration Low
+// bits[10:8], CohPrefPrbLmt = 1
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0),  // Address
+      0x00000100,                           // regData
+      0x00000700,                           // regMask
+    }}
+  },
+
+// Function 3 - Misc. Control
+
+// F3x6C - Data Buffer Count
+// bits[30:28] IsocRspDBC = 1
+// bits[18:16] UpRspDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[2:0]   UpReqDBC = 2
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10010052,                           // regData
+      0x700700F7,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 1
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00000800,                           // regData
+      0x00003800,                           // regMask
+    }}
+  },
+// F3xA4 - Reported Temperature Control
+// bits[12:8] PerStepTimeDn = 0x0F
+// bits[7] TmpSlewDnEn = 1
+// bits[6:5] TmpMaxDiffUp = 3
+// bits[4:0] PerStepTimeUp = 0x0F
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),  // Address
+      0x00000FEF,                           // regData
+      0x00001FFF,                           // regMask
+    }}
+  },
+// F3x1CC - IBS Control
+// bits[8] LvtOffsetVal = 1
+// bits[3:0] LvtOffset = 0
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
+      0x00000100,                           // regData
+      0x0000010F,                           // regMask
+    }}
+  },
+// F4x15C - Core Performance Boost Control
+// bits[1:0] BoostSrc = 0
+  {
+    PciRegister,
+    {
+      (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) ,                      // CpuFamily
+      (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
+      0x00000000,                           // regData
+      0x00000003,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F15PciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F15PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F15PciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
new file mode 100644
index 0000000000..b52931a66f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
@@ -0,0 +1,466 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 P-State power check
+ *
+ * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF15PowerCheck.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F15PmPwrCheckCore (
+  IN     VOID *ErrorData,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F15PmPwrChkCopyPstate (
+  IN     UINT8 Dest,
+  IN     UINT8 Src,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 15h core 0 entry point for performing the family 15h Processor-
+ * Systemboard Power Delivery Check.
+ *
+ * The steps are as follows:
+ *    1. Starting with P0, loop through all P-states until a passing state is
+ *       found.  A passing state is one in which the current required by the
+ *       CPU is less than the maximum amount of current that the system can
+ *       provide to the CPU.  If P0 is under the limit, no further action is
+ *       necessary.
+ *    2. If at least one P-State is under the limit & at least one P-State is
+ *       over the limit, the BIOS must:
+ *       a. If the processor's current P-State is disabled by the power check,
+ *          then the BIOS must request a transition to an enabled P-state
+ *          using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
+ *          to reflect the new value.
+ *       b. Copy the contents of the enabled P-state MSRs to the highest
+ *          performance P-state locations.
+ *       c. Request a P-state transition to the P-state MSR containing the
+ *          COF/VID values currently applied.
+ *       d. If a subset of boosted P-states are disabled, then copy the contents
+ *          of the highest performance boosted P-state still enabled to the
+ *          boosted P-states that have been disabled.
+ *       e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc]
+ *          to zero.
+ *       f. Adjust the following P-state parameters affected by the P-state
+ *          MSR copy by subtracting the number of P-states that are disabled
+ *          by the power check.
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[SwPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *    3. If all P-States are over the limit, the BIOS must:
+ *       a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
+ *          write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
+ *          MSRC001_0063[CurPstate] to reflect the new value.
+ *       b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state
+ *          MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR.
+ *          Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
+ *          [CurPstate] to reflect the new value.
+ *       c. Adjust the following P-state parameters to zero:
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[SwPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *       d. Program D18F4x15C[BoostSrc] to zero.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F15PmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8       DisPsNum;
+  UINT8       PsMaxVal;
+  UINT8       Pstate;
+  UINT32      ProcIddMax;
+  UINT32      LocalPciRegister;
+  UINT32      Socket;
+  UINT32      Module;
+  UINT32      Core;
+  UINT32      AndMask;
+  UINT32      OrMask;
+  UINT32      PstateLimit;
+  PCI_ADDR    PciAddress;
+  UINT64      LocalMsrRegister;
+  AP_TASK     TaskPtr;
+  AGESA_STATUS IgnoredSts;
+  PWRCHK_ERROR_DATA ErrorData;
+  UINT32      NumModules;
+  UINT32      HighCore;
+  UINT32      LowCore;
+  UINT32      ModuleIndex;
+
+
+  // get the socket number
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  ErrorData.SocketNumber = (UINT8) Socket;
+
+  ASSERT (Core == 0);
+
+  // get the Max P-state value
+  for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
+    if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+
+  ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
+
+ // Starting with P0, loop through all P-states until a passing state is
+ // found.  A passing state is one in which the current required by the
+ // CPU is less than the maximum amount of current that the system can
+ // provide to the CPU.  If P0 is under the limit, no further action is
+ // necessary.
+  DisPsNum = 0;
+  for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
+    if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
+      if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
+        // Add to event log the Pstate that exceeded the current limit
+        PutEventLog (AGESA_WARNING,
+                     CPU_EVENT_PM_PSTATE_OVERCURRENT,
+                     Socket, Pstate, 0, 0, StdHeader);
+        DisPsNum++;
+      } else {
+        break;
+      }
+    }
+  }
+
+  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+
+  if (ErrorData.AllowablePstateNumber == 0) {
+    PutEventLog (AGESA_FATAL,
+                 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
+                 Socket, 0, 0, 0, StdHeader);
+  }
+
+  if (DisPsNum != 0) {
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_4;
+    PciAddress.Address.Register = CPB_CTRL_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+    ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+
+    if (DisPsNum >= ErrorData.NumberOfBoostStates) {
+      // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero.
+      AndMask = 0xFFFFFFFF;
+      ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0;
+      OrMask = 0x00000000;
+      OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C
+
+      ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates;
+    } else {
+      ErrorData.NumberOfSwPstatesDisabled = 0;
+    }
+
+    NumModules = GetPlatformNumberOfModules ();
+
+    // Only execute this loop if this is an MCM.
+    if (NumModules > 1) {
+
+      // Since the P-State MSRs are shared across a
+      // node, we only need to set one core in the node for the modified number of supported p-states
+      // to be reported across all of the cores in the module.
+      TaskPtr.FuncAddress.PfApTaskI = F15PmPwrCheckCore;
+      TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
+      TaskPtr.DataTransfer.DataPtr = &ErrorData;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+      for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) {
+        // Execute the P-State reduction code on the module's primary core only.
+        // Skip this code for the BSC's module.
+        if (ModuleIndex != Module) {
+          if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) {
+            ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader);
+          }
+        }
+      }
+  }
+
+    // Path for SCM and the BSC
+    F15PmPwrCheckCore (&ErrorData, StdHeader);
+
+    // Final Step
+    //    F3x64[HtPstatelimit] -= disPsNum
+    //    F3x68[SwPstateLimit] -= disPsNum
+    //    F3xDC[PstateMaxVal] -= disPsNum
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = HTC_REG;
+    AndMask = 0xFFFFFFFF;
+    ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
+    PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
+    if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+      PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
+    }
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
+
+    PciAddress.Address.Register = SW_PS_LIMIT_REG;
+    AndMask = 0xFFFFFFFF;
+    ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
+    PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit;
+    if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+      PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit;
+    }
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
+
+    PciAddress.Address.Register = CPTC2_REG;
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
+    PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
+    if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+      PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
+    }
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Core-level error handler called if any p-states were determined to be out
+ * of range for the mother board.
+ *
+ * This function implements steps 2a-c and 3a-c on each core.
+ *
+ * @param[in]  ErrorData            Details about the error condition.
+ * @param[in]  StdHeader            Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F15PmPwrCheckCore (
+  IN       VOID *ErrorData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  i;
+  UINT8  HwPsMaxVal;
+  UINT8  SwPsMaxVal;
+  UINT8  HwDisPsNum;
+  UINT8  CurrentSwPs;
+  UINT8  PsDisableCount;
+  UINT64 LocalMsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    // P-state MSRs are shared, so only 1 core per compute unit needs to perform this
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+    HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+                  ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
+
+    LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+    CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
+    LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+    SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal);
+    PsDisableCount = 0;
+
+    if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+      // All P-States are over the limit.
+
+      // Step 1
+      // Transition to Pstate Max if not there already
+      if (CurrentSwPs != SwPsMaxVal) {
+        FamilySpecificServices->TransitionPstate (FamilySpecificServices, SwPsMaxVal, (BOOLEAN) TRUE, StdHeader);
+      }
+
+      // Step 2
+      // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+      // to P0.
+      if (SwPsMaxVal != 0) {
+        F15PmPwrChkCopyPstate (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates, HwPsMaxVal, StdHeader);
+        FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+      }
+
+      // Disable all SW P-states except P0
+      PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1;
+    } else {
+      // At least one P-State is under the limit & at least one P-State is
+      // over the limit.
+      if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) {
+        // A subset of boosted P-states are disabled.  Copy the contents of the
+        // highest performance boosted P-state still enabled to the boosted
+        // P-states that have been disabled.
+        for (i = 0; i < HwDisPsNum; i++) {
+          F15PmPwrChkCopyPstate (i, HwDisPsNum, StdHeader);
+        }
+      } else if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) {
+        // Move remaining P-state register(s) up
+        // Step 1
+        // Transition to a valid Pstate if current Pstate has been disabled
+        if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) {
+          FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader);
+          CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+        }
+
+        // Step 2
+        // Move enabled Pstates up and disable the remainder
+        for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) {
+          F15PmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader);
+        }
+
+        // Step 3
+        // Transition to current COF/VID at shifted location
+        CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled);
+        FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSwPs, (BOOLEAN) TRUE, StdHeader);
+
+        // Disable the appropriate number of P-states
+        PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+      }
+    }
+    // Disable the appropriate P-states if any, starting from HW Pmin
+    for (i = 0; i < PsDisableCount; i++) {
+      FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copies the contents of one P-State MSR to another.
+ *
+ * @param[in]  Dest              Destination p-state number
+ * @param[in]  Src               Source p-state number
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+F15PmPwrChkCopyPstate (
+  IN       UINT8 Dest,
+  IN       UINT8 Src,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.h
new file mode 100644
index 0000000000..3993eafe9d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Power related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_POWER_CHECK_H_
+#define _CPU_F15_POWER_CHECK_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Power Check Error Data
+typedef struct {
+  UINT8 SocketNumber;                 ///< Socket Number
+  UINT8 HwPstateNumber;               ///< Number of hardware P-states
+  UINT8 AllowablePstateNumber;        ///< Number of allowable P-states
+  UINT8 NumberOfBoostStates;          ///< Number of boosted P-states
+  UINT8 NumberOfSwPstatesDisabled;    ///< Number of software P-states disabled
+} PWRCHK_ERROR_DATA;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F15PmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F15_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h
new file mode 100644
index 0000000000..7586898d5b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h
@@ -0,0 +1,320 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 Power Management related registers defination
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 64491 $   @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPUF15POWERMGMT_H_
+#define _CPUF15POWERMGMT_H_
+
+/*
+ * Family 15h CPU Power Management MSR definitions
+ *
+ */
+
+
+/* Last Branch From IP Register 0x000001DB */
+#define MSR_BR_FROM                 0x000001DBul
+
+/* P-state Current Limit Register 0xC0010061 */
+#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061ul // F15 Shared
+
+/// Pstate Current Limit MSR Register
+typedef struct {
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 :1;                         ///< Reserved
+  UINT64 PstateMaxVal:3;             ///< Pstate Max Value
+  UINT64 :57;                        ///< Reserved
+} PSTATE_CURLIM_MSR;
+
+
+/* P-state Control Register 0xC0010062 */
+#define MSR_PSTATE_CTL 0xC0010062ul    // F15 Shared
+
+/// Pstate Control MSR Register
+typedef struct {
+  UINT64 PstateCmd:3;                ///< Pstate change command
+  UINT64 :61;                        ///< Reserved
+} PSTATE_CTRL_MSR;
+
+
+/* P-state Status Register 0xC0010063 */
+#define MSR_PSTATE_STS 0xC0010063ul
+
+/// Pstate Status MSR Register
+typedef struct {
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :61;                        ///< Reserved
+} PSTATE_STS_MSR;
+
+
+/* P-state Registers 0xC001006[B:4] */
+#define MSR_PSTATE_0 0xC0010064ul
+#define MSR_PSTATE_1 0xC0010065ul
+#define MSR_PSTATE_2 0xC0010066ul
+#define MSR_PSTATE_3 0xC0010067ul
+#define MSR_PSTATE_4 0xC0010068ul
+#define MSR_PSTATE_5 0xC0010069ul
+#define MSR_PSTATE_6 0xC001006Aul
+#define MSR_PSTATE_7 0xC001006Bul
+
+#define PS_REG_BASE MSR_PSTATE_0     /* P-state Register base */
+#define PS_MAX_REG  MSR_PSTATE_7     /* Maximum P-State Register */
+#define PS_MIN_REG  MSR_PSTATE_0     /* Minimum P-State Register */
+#define NM_PS_REG 8                  /* number of P-state MSR registers */
+
+/// P-state MSR with common field
+typedef struct {
+  UINT64 :63;                        ///< CpuFid
+  UINT64 PsEnable:1;                 ///< Pstate Enable
+} F15_PSTATE_MSR;
+
+
+/* C-state Address Register 0xC0010073 */
+#define MSR_CSTATE_ADDRESS 0xC0010073ul
+
+/// C-state Address MSR Register
+typedef struct {
+  UINT64 CstateAddr:16;              ///< C-state address
+  UINT64 :48;                        ///< Reserved
+} CSTATE_ADDRESS_MSR;
+
+
+/*
+ * Family 15h CPU Power Management PCI definitions
+ *
+ */
+
+/* Extended Memory Controller Configuration Low Register F2x1B0 */
+#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0
+
+/// Extended Memory Controller Configuration Low PCI Register
+typedef struct {
+  UINT32 AdapPrefMissRatio:2;        ///< Adaptive prefetch miss ratio
+  UINT32 AdapPrefPositiveStep:2;     ///< Adaptive prefetch positive step
+  UINT32 AdapPrefNegativeStep:2;     ///< Adaptive prefetch negative step
+  UINT32 :2;                         ///< Reserved
+  UINT32 CohPrefPrbLmt:3;            ///< Coherent prefetch probe limit
+  UINT32 DisIoCohPref:1;             ///< Disable coherent prefetched for IO
+  UINT32 EnSplitDctLimits:1;         ///< Split DCT write limits enable
+  UINT32 SpecPrefDis:1;              ///< Speculative prefetch disable
+  UINT32 SpecPrefMis:1;              ///< Speculative prefetch predict miss
+  UINT32 SpecPrefThreshold:3;        ///< Speculative prefetch threshold
+  UINT32 :4;                         ///< Reserved
+  UINT32 PrefFourConf:3;             ///< Prefetch four-ahead confidence
+  UINT32 PrefFiveConf:3;             ///< Prefetch five-ahead confidence
+  UINT32 DcqBwThrotWm:4;             ///< Dcq bandwidth throttle watermark
+} EXT_MEMCTRL_CFG_LOW_REGISTER;
+
+
+/* Hardware thermal control register F3x64 */
+#define HTC_REG 0x64
+#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
+
+/// Hardware Thermal Control PCI Register
+typedef struct {
+  UINT32 HtcEn:1;                    ///< HTC Enable
+  UINT32 :3;                         ///< Reserved
+  UINT32 HtcAct:1;                   ///< HTC Active State
+  UINT32 HtcActSts:1;                ///< HTC Active Status
+  UINT32 PslApicHiEn:1;              ///< P-state limit higher APIC interrupt enable
+  UINT32 PslApicLoEn:1;              ///< P-state limit lower APIC interrupt enable
+  UINT32 :8;                         ///< Reserved
+  UINT32 HtcTmpLmt:7;                ///< HTC temperature limit
+  UINT32 HtcSlewSel:1;               ///< HTC slew-controlled temp select
+  UINT32 HtcHystLmt:4;               ///< HTC hysteresis
+  UINT32 HtcPstateLimit:3;           ///< HTC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} HTC_REGISTER;
+
+
+/* Software P-state limit register F3x68 */
+#define SW_PS_LIMIT_REG 0x68
+
+/// Software P-state Limit PCI Register
+typedef struct {
+  UINT32 :5;                         ///< Reserved
+  UINT32 SwPstateLimitEn:1;          ///< Software P-state limit enable
+  UINT32 :22;                        ///< Reserved
+  UINT32 SwPstateLimit:3;            ///< HTC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} SW_PS_LIMIT_REGISTER;
+
+/* ACPI Power State Control Registers F3x84:80 */
+
+/// System Management Action Field (SMAF) Register
+typedef struct {
+  UINT8 CpuPrbEn:1;                  ///< CPU direct probe enable
+  UINT8 NbLowPwrEn:1;                ///< Northbridge low-power enable
+  UINT8 NbGateEn:1;                  ///< Northbridge gate enable
+  UINT8 Reserved:2;                  ///< Reserved
+  UINT8 ClkDivisor:3;                ///< Clock divisor
+} SMAF_REGISTER;
+
+/// union type for ACPI State SMAF setting
+typedef union {
+  UINT8 SMAFValue;                   ///< SMAF raw value
+  SMAF_REGISTER SMAF;                ///< SMAF structure
+} ACPI_STATE_SMAF;
+
+/// ACPI Power State Control Register F3x80
+typedef struct {
+  ACPI_STATE_SMAF C2;                ///< [7:0]   SMAF Code 000b - C2
+  ACPI_STATE_SMAF C1eLinkInit;       ///< [15:8]  SMAF Code 001b - C1e or Link init
+  ACPI_STATE_SMAF SmafAct2;          ///< [23:16] SMAF Code 010b
+  ACPI_STATE_SMAF S1;                ///< [31:24] SMAF Code 011b - S1
+} ACPI_PSC_0_REGISTER;
+
+/// ACPI Power State Control Register F3x84
+typedef struct {
+  ACPI_STATE_SMAF S3;                 ///< [7:0]   SMAF Code 100b - S3
+  ACPI_STATE_SMAF Throttling;         ///< [15:8]  SMAF Code 101b - Throttling
+  ACPI_STATE_SMAF S4S5;               ///< [23:16] SMAF Code 110b - S4/S5
+  ACPI_STATE_SMAF C1;                 ///< [31:24] SMAF Code 111b - C1
+} ACPI_PSC_4_REGISTER;
+
+
+/* Popup P-state Register F3xA8 */
+#define POPUP_PSTATE_REG 0xA8
+#define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG))
+
+/// Popup P-state Register
+typedef struct {
+  UINT32 :29;                        ///< Reserved
+  UINT32 PopDownPstate:3;            ///< PopDownPstate
+} POPUP_PSTATE_REGISTER;
+
+
+/* Clock Power/Timing Control 2 Register F3xDC */
+#define CPTC2_REG 0xDC
+#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
+
+/// Clock Power Timing Control 2 PCI Register
+typedef struct {
+  UINT32 :8;                         ///< Reserved
+  UINT32 PstateMaxVal:3;             ///< P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbsynPtrAdj:3;              ///< NB/Core sync FIFO ptr adjust
+  UINT32 :1;                         ///< Reserved
+  UINT32 CacheFlushOnHaltCtl:3;      ///< Cache flush on halt control
+  UINT32 CacheFlushOnHaltTmr:7;      ///< Cache flush on halt timer
+  UINT32 IgnCpuPrbEn:1;              ///< ignore CPU probe enable
+  UINT32 :5;                         ///< Reserved
+} CLK_PWR_TIMING_CTRL2_REGISTER;
+
+
+/* Core Performance Boost Control Register D18F4x15C */
+#define CPB_CTRL_REG 0x15C
+#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
+
+/// Core Performance Boost Control Register of Family 15h common aceess
+typedef struct {
+  UINT32 BoostSrc:2;                 ///< Boost source
+  UINT32 NumBoostStates:3;           ///< Number of boosted states
+  UINT32 :2;                         ///< Reserved
+  UINT32 ApmMasterEn:1;              ///< APM master enable
+  UINT32 :23;                        ///< Reserved
+  UINT32 BoostLock:1;                ///<
+} F15_CPB_CTRL_REGISTER;
+
+
+#define NM_NB_PS_REG 4               /* Number of NB P-state registers */
+
+/* Northbridge P-state */
+#define NB_PSTATE_0 0x160
+#define NB_PSTATE_0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_0))
+
+#define NB_PSTATE_1 0x164
+#define NB_PSTATE_1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_1))
+
+#define NB_PSTATE_2 0x168
+#define NB_PSTATE_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_2))
+
+#define NB_PSTATE_3 0x16C
+#define NB_PSTATE_3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_3))
+
+
+/* Northbridge P-state Status */
+#define F15_NB_PSTATE_CTRL 0x170
+#define F15_NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, F15_NB_PSTATE_CTRL))
+
+/// Northbridge P-state Control Register
+typedef struct {
+  UINT32 NbPstateMaxVal:2;           ///< NB P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateLo:2;               ///< NB P-state low
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateHi:2;               ///< NB P-state high
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateThreshold:3;        ///< NB P-state threshold
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateDisOnP0:1;          ///< NB P-state disable on P0
+  UINT32 SwNbPstateLoDis:1;          ///< Software NB P-state low disable
+  UINT32 :17;                        ///< Reserved
+} F15_NB_PSTATE_CTRL_REGISTER;
+
+
+#endif /* _CPUF15POWERMGMT_H */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c
new file mode 100644
index 0000000000..c319a817de
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c
@@ -0,0 +1,1204 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 15h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuF15Utilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuPostInit.h"
+#include "cpuFeatures.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION    OptionMultiSocketConfiguration;
+
+// HT Phy registers used in code.
+#define HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL0 0x4011
+#define HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL1 0x4411
+#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_RD  0x400F
+#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL0 0x520F
+#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL1 0x530F
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * HT PHY DLL Process Compensation Lookup Table.
+ *
+ * If the hardware provides compensation values, the value is provided by accessing the bitfield
+ * [HiBit:LoBit].  Otherwise, a default value will be used.
+ *
+ */
+typedef struct {
+  UINT32   DefaultComp;                       ///< The default compensation value if not provided by hardware.
+  UINT8    CtlIndexLoBit;                     ///< The low bit position of the compensation value.
+  UINT8    CtlIndexHiBit;                     ///< The high bit position of the compensation value.
+} HT_PHY_DLL_COMP_LOOKUP_TABLE;
+
+/**
+ * Process Compensation Fuses for HT PHY, Link Phy Receiver Process Fuse Control Register.
+ */
+typedef struct {
+  UINT32   :11;
+  UINT32   DllProcessComp10:2;                     ///< [12:11] DLL Process Comp bits [1:0], this phy's adjustment.
+  UINT32   DllProcessComp2:1;                      ///< [13] DLL Process Comp bit 2, Increment or Decrement.
+  UINT32   : (31 - 13);
+} LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL_FIELDS;
+
+/// Access register as fields or uint32 value.
+typedef union {
+  UINT32   Value;                                         ///< 32 bit value for register access
+  LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL_FIELDS Fields;   ///< The register bit fields
+} LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL;
+
+/**
+ * Link Phy Receiver Process DLL Control Register.
+ */
+typedef struct {
+  UINT32   DllProcessFreqCtlIndex2:4;              ///< [3:0] The DLL Compensation override.
+  UINT32   : (12 - 4);
+  UINT32   DllProcessFreqCtlOverride:1;            ///< [12] Enable DLL Compensation overriding.
+  UINT32   : (31 - 12);
+} LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_FIELDS;
+
+/// Access register as fields or uint32 value.
+typedef union {
+  UINT32    Value;                                       ///< 32 bit value for register access
+  LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_FIELDS Fields;   ///< The register bit fields
+} LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL;
+
+/**
+ * Provide the HT PHY DLL compensation value for each HT Link frequency.
+ *
+ * The HT Frequency enum is not contiguous, there are skipped values.  Rather than complicate
+ * index calculations, add Invalid entries here marked with an invalid compensation value (invalid
+ * because real compensation values are 0 .. 15).
+ */
+CONST STATIC HT_PHY_DLL_COMP_LOOKUP_TABLE ROMDATA HtPhyDllCompLookupTable[] = {
+  {0xAul, 0, 3},               //   HT_FREQUENCY_1200M
+  {0xAul, 0, 3},               //   HT_FREQUENCY_1400M
+  {0x7ul, 4, 7},               //   HT_FREQUENCY_1600M
+  {0x7ul, 4, 7},               //   HT_FREQUENCY_1800M
+  {0x5ul, 8, 11},              //   HT_FREQUENCY_2000M
+  {0x5ul, 8, 11},              //   HT_FREQUENCY_2200M
+  {0x4ul, 12, 15},             //   HT_FREQUENCY_2400M
+  {0x3ul, 16, 19},             //   HT_FREQUENCY_2600M
+  {0xFFFFFFFFul, 0, 0},        //   Invalid
+  {0xFFFFFFFFul, 0, 0},        //   Invalid
+  {0x3ul, 20, 23},             //   HT_FREQUENCY_2800M
+  {0x2ul, 24, 27},             //   HT_FREQUENCY_3000M
+  {0x2ul, 28, 31}              //   HT_FREQUENCY_3200M
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Disables the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The P-State to disable.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F15DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  ((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0;
+  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Transitions the executing core to the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The new P-State to make effective.
+ *  @param[in]   WaitForTransition        True if the caller wants the transition completed upon return.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS       Always Succeeds
+ */
+AGESA_STATUS
+F15TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64       LocalMsrRegister;
+
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+  ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber);
+  LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader);
+  ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader);
+  if (WaitForTransition) {
+    do {
+      LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+    } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber);
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the rate at which the executing core's time stamp counter is
+ *  incrementing.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  FrequencyInMHz           TSC actual frequency.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ *  @return      The most severe status of all called services
+ */
+AGESA_STATUS
+F15GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8        NumBoostStates;
+  UINT32       LocalPciRegister;
+  UINT64       LocalMsrRegister;
+  PCI_ADDR     PciAddress;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+
+  LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader);
+  if ((LocalMsrRegister & 0x01000000) != 0) {
+    FamilyServices = NULL;
+    GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+    PciAddress.Address.Function = FUNC_4;
+    PciAddress.Address.Register = CPB_CTRL_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    NumBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+    return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader));
+  } else {
+    return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initially launches the desired core to run from the reset vector.
+ *
+ * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   SocketNum                The Processor on which the core is to be launched
+ * @param[in]   ModuleNum                The Module in that processor containing that core
+ * @param[in]   CoreNum                  The Core to launch
+ * @param[in]   PrimaryCoreNum           The id of the module's primary core.
+ * @param[in]   StdHeader                Header for library and services
+ *
+ * @retval      TRUE          The core was launched
+ * @retval      FALSE         The core was previously launched
+ */
+BOOLEAN
+F15LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    NodeRelativeCoreNum;
+  UINT32    LocalPciRegister;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   LaunchFlag;
+  AGESA_STATUS Ignored;
+
+  // Code Start
+  LaunchFlag = FALSE;
+  NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
+  GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored);
+  PciAddress.Address.Function = FUNC_0;
+
+  switch (NodeRelativeCoreNum) {
+  case 0:
+    PciAddress.Address.Register = HT_INIT_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & HT_INIT_CTRL_REQ_DIS) != 0) {
+      LocalPciRegister &= ~HT_INIT_CTRL_REQ_DIS;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 1:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE1_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE1_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 2:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+    if ((LocalPciRegister & CORE_CTRL_CORE2_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE2_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister,
+                      StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 3:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE3_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE3_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 4:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE4_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE4_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 5:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE5_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE5_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 6:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE6_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE6_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 7:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE7_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE7_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+      break;
+
+  case 8:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE8_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE8_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 9:
+    PciAddress.Address.Register = CORE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if ((LocalPciRegister & CORE_CTRL_CORE9_EN) == 0) {
+      LocalPciRegister |= CORE_CTRL_CORE9_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+      break;
+
+  default:
+    break;
+  }
+
+  return (LaunchFlag);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the features of the next HT link.
+ *
+ *  @CpuServiceMethod{::F_GET_NEXT_HT_LINK_FEATURES}.
+ *
+ * This method is different than the HT Phy Features method, because for the phy registers
+ * sublink 1 matches and should be programmed if the link is ganged but for PCI config
+ * registers sublink 1 is reserved if the link is ganged.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[in,out] Link                      Initially zero, each call returns the link number;
+ *                                          caller passes it back unmodified each call.
+ * @param[in,out] LinkBase                  Initially the PCI bus, device, function=0, offset=0;
+ *                                          Each call returns the HT Host Capability function and offset;
+ *                                          Caller may use it to access registers, but must @b not modify it;
+ *                                          Each new call passes the previous value as input.
+ * @param[out]    HtHostFeats               The link's features.
+ * @param[in]     StdHeader                 Standard Head Pointer
+ *
+ * @retval        TRUE                      Valid link and features found.
+ * @retval        FALSE                     No more links.
+ */
+BOOLEAN
+F15GetNextHtLinkFeatures (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   UINTN                  *Link,
+  IN OUT   PCI_ADDR               *LinkBase,
+     OUT   HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    RegValue;
+  UINT32    ExtendedFreq;
+  UINTN     LinkOffset;
+  BOOLEAN   Result;
+
+  ASSERT (FamilySpecificServices != NULL);
+
+  // No features present unless link is good and connected.
+  HtHostFeats->HtHostValue = 0;
+
+  Result = TRUE;
+
+  // Find next link.
+  if (LinkBase->Address.Register == 0) {
+    // Beginning iteration now.
+    LinkBase->Address.Register = HT_CAPABILITIES_POINTER;
+    LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader);
+  } else {
+    // Get next link offset.
+    LibAmdPciReadBits (*LinkBase, 15, 8, &RegValue, StdHeader);
+  }
+  if (RegValue == 0) {
+    // Are we at the end?  Check if we can move to another function.
+    if (LinkBase->Address.Function == 0) {
+      LinkBase->Address.Function = 4;
+      LinkBase->Address.Register = HT_CAPABILITIES_POINTER;
+      LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader);
+    }
+  }
+
+  if (RegValue != 0) {
+    // Not at end, process the found link.
+    LinkBase->Address.Register = RegValue;
+    // Compute link number
+    *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5));
+
+    // Handle pending link power off, check End of Chain, Xmit Off.
+    PciAddress = *LinkBase;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET;
+    LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader);
+    if (RegValue == 0) {
+      // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+      PciAddress = *LinkBase;
+      PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+      LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader);
+      if (RegValue  == 3) {
+        HtHostFeats->HtHostFeatures.Coherent = 1;
+      } else if (RegValue == 7) {
+        HtHostFeats->HtHostFeatures.NonCoherent = 1;
+      }
+    }
+
+    // If link was not connected, don't check other attributes, make sure
+    // to return zero, no match.
+    if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) {
+      // Check gen3
+      PciAddress = *LinkBase;
+      PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+      PciAddress = *LinkBase;
+      PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+      LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+      RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+      if (RegValue > 6) {
+        HtHostFeats->HtHostFeatures.Ht3 = 1;
+      } else {
+        HtHostFeats->HtHostFeatures.Ht1 = 1;
+      }
+      // Check ganged. Must check the bit for sublink 0.
+      LinkOffset = (*Link > 3) ? ((*Link - 4) * 4) : (*Link * 4);
+      PciAddress = *LinkBase;
+      PciAddress.Address.Function = 0;
+      PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170);
+      LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader);
+      if (RegValue == 0) {
+        HtHostFeats->HtHostFeatures.UnGanged = 1;
+      } else {
+        if (*Link < 4) {
+          HtHostFeats->HtHostFeatures.Ganged = 1;
+        } else {
+          // If this is a sublink 1 but it will be ganged, clear all features.
+          HtHostFeats->HtHostValue = 0;
+        }
+      }
+    }
+  } else {
+    // end of links.
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks to see if the HT phy register table entry should be applied
+ *
+ * @CpuServiceMethod{::F_NEXT_LINK_HAS_HTFPY_FEATS}.
+ *
+ * Find the next link which matches, if any.
+ * This method will match for sublink 1 if the link is ganged and sublink 0 matches.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0;
+ *                                         Each call returns the HT Host Capability function and offset;
+ *                                         Caller may use it to access registers, but must @b not modify it;
+ *                                         Each new call passes the previous value as input.
+ * @param[in,out] Link             Initially zero, each call returns the link number; caller passes it back unmodified each call.
+ * @param[in]     HtPhyLinkType    Link type field from a register table entry to compare against
+ * @param[out]    MatchedSublink1  TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
+ * @param[out]    Frequency0       The frequency of sublink0 (200 MHz if not connected).
+ * @param[out]    Frequency1       The frequency of sublink1 (200 MHz if not connected).
+ * @param[in]     StdHeader        Standard Head Pointer
+ *
+ * @retval        TRUE             Link matches
+ * @retval        FALSE            No more links
+ *
+ */
+BOOLEAN
+F15NextLinkHasHtPhyFeats (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PCI_ADDR           *HtHostCapability,
+  IN OUT   UINT32             *Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+     OUT   BOOLEAN            *MatchedSublink1,
+     OUT   HT_FREQUENCIES     *Frequency0,
+     OUT   HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32    RegValue;
+  UINT32    ExtendedFreq;
+  UINT32    InternalLinks;
+  UINT32    Width;
+  PCI_ADDR  PciAddress;
+  PCI_ADDR  SubLink1Address;
+  HT_PHY_LINK_FEATS LinkType;
+  BOOLEAN   IsReallyCheckingBoth;
+  BOOLEAN   IsFound;
+  BOOLEAN   Result;
+
+  ASSERT (*Link < 4);
+  ASSERT (HtPhyLinkType != NULL);
+  // error checks: No unknown link type bits set and not a "match none"
+  ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0);
+  ASSERT (HtPhyLinkType->HtPhyLinkValue != 0);
+
+  Result = FALSE;
+  IsFound = FALSE;
+  while (!IsFound) {
+    *Frequency0 = 0;
+    *Frequency1 = 0;
+    IsReallyCheckingBoth = FALSE;
+    *MatchedSublink1 = FALSE;
+    LinkType.HtPhyLinkValue = 0;
+
+    // Find next link.
+    PciAddress = *HtHostCapability;
+    if (PciAddress.Address.Register == 0) {
+      // Beginning iteration now.
+      PciAddress.Address.Register = HT_CAPABILITIES_POINTER;
+      LibAmdPciReadBits (PciAddress, 7, 0, &RegValue, StdHeader);
+    } else {
+      // Get next link offset.
+      LibAmdPciReadBits (PciAddress, 15, 8, &RegValue, StdHeader);
+    }
+    if (RegValue != 0) {
+      HtHostCapability->Address.Register = RegValue;
+      // Compute link number of this sublink pair (so we don't need to account for function).
+      *Link = ((HtHostCapability->Address.Register - 0x80) >> 5);
+
+      // Set the link indicators.  This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4.
+      LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << *Link);
+      LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << *Link);
+
+      // Read IntLnkRoute from the Link Initialization Status register.
+      PciAddress = *HtHostCapability;
+      PciAddress.Address.Function = 0;
+      PciAddress.Address.Register = 0x1A0;
+      LibAmdPciReadBits (PciAddress, 23, 16, &InternalLinks, StdHeader);
+
+      // if ganged, don't read sublink 1, but use sublink 0 to check.
+      SubLink1Address = *HtHostCapability;
+
+      // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also,
+      // but only access it if it is also unganged.
+      PciAddress = *HtHostCapability;
+      PciAddress.Address.Function = 0;
+      PciAddress.Address.Register = ((*Link * 4) + 0x170);
+      LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+      RegValue = (RegValue & 0x01);
+      if (RegValue == 0) {
+        // Then really read sublink1, rather than using sublink0
+        SubLink1Address.Address.Function = 4;
+        IsReallyCheckingBoth = TRUE;
+      }
+
+      // Checks for Sublink 0
+
+      // Handle pending link power off, check End of Chain, Xmit Off.
+      PciAddress = *HtHostCapability;
+      PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET;
+      LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader);
+      if (RegValue == 0) {
+        // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+        PciAddress = *HtHostCapability;
+        PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+        LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+        if ((RegValue & 0x1F) == 3) {
+          LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1;
+        } else if ((RegValue & 0x1F) == 7) {
+          LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1;
+        }
+      }
+
+      // If link was not connected, don't check other attributes, make sure
+      // to return zero, no match. (Phy may be powered off.)
+      if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) {
+        // Check gen3
+        PciAddress = *HtHostCapability;
+        PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+        LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+        PciAddress = *HtHostCapability;
+        PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+        LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+        RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+        *Frequency0 = RegValue;
+        if (RegValue > 6) {
+          LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1;
+        } else {
+          LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1;
+        }
+        // Check internal / external
+        if ((InternalLinks & (1 << *Link)) == 0) {
+          // External
+          LinkType.HtPhyLinkFeatures.HtPhySL0External = 1;
+        } else {
+          // Internal
+          LinkType.HtPhyLinkFeatures.HtPhySL0Internal = 1;
+        }
+      } else {
+        LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL);
+      }
+
+      // Checks for Sublink 1
+      // Handle pending link power off, check End of Chain, Xmit Off.
+      // Also, if the links are ganged but the width is not 16 bits, treat it is an inactive lane.
+      PciAddress = SubLink1Address;
+      PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET;
+      LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader);
+      LibAmdPciReadBits (PciAddress, 31, 24, &Width, StdHeader);
+      if ((RegValue == 0) && (IsReallyCheckingBoth || (Width == 0x11))) {
+        // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+        PciAddress = SubLink1Address;
+        PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+        LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+        if ((RegValue & 0x1F) == 3) {
+          LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1;
+        } else if ((RegValue & 0x1F) == 7) {
+          LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1;
+        }
+      }
+
+      if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) {
+        // Check gen3
+        PciAddress = SubLink1Address;
+        PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+        LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+        PciAddress = SubLink1Address;
+        PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+        LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+        RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+        *Frequency1 = RegValue;
+        if (RegValue > 6) {
+          LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1;
+        } else {
+          LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1;
+        }
+        // Check internal / external.  Note that we do really check sublink 1 regardless of ganging.
+        if ((InternalLinks & (1 << (*Link + 4))) == 0) {
+          // External
+          LinkType.HtPhyLinkFeatures.HtPhySL1External = 1;
+        } else {
+          // Internal
+          LinkType.HtPhyLinkFeatures.HtPhySL1Internal = 1;
+        }
+      } else {
+        LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL);
+      }
+
+      // Determine if the link matches the entry criteria.
+      // For Deemphasis checking, indicate whether it was actually sublink 1 that matched.
+      // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false.
+      if (((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL0_AND) == 0) &&
+          ((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL1_AND) == 0)) {
+        // Match if any feature matches (OR)
+        Result = (BOOLEAN) ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0);
+      } else {
+        // Match if all features match (AND)
+        Result = (BOOLEAN) ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) ==
+                           (LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue));
+      }
+      if (Result) {
+        if (IsReallyCheckingBoth &&
+            (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) {
+          *MatchedSublink1 = TRUE;
+        }
+        IsFound = TRUE;
+      } else {
+        // Go to next link
+      }
+    } else {
+      // No more links
+      IsFound = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
+ *
+ * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}.
+ *
+ * This function performs the necessary sequence of PCI reads, writes, and waits
+ * necessary to program an HT Phy register.
+ *
+ * @param[in]  FamilySpecificServices    The current Family Specific Services.
+ * @param[in]  HtPhyEntry    HT Phy register table entry to apply
+ * @param[in]  CapabilitySet The link's HT Host base address.
+ * @param[in]  Link          Zero based, node, link number (not package link).
+ * @param[in]  StdHeader     Config handle for library and services
+ *
+ */
+VOID
+F15SetHtPhyRegister (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  UINT32    Temp;
+  UINT32    PhyReg;
+  PCI_ADDR  PhyBase;
+
+  // Determine the PCI config address of the HT Phy portal
+  PhyBase = CapabilitySet;
+  PhyBase.Address.Function = FUNC_4;
+  PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180);
+
+  LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+
+  // Handle direct map registers if needed
+  PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK);
+  if ((HtPhyEntry->Address > 0x3FF) || ((HtPhyEntry->Address >= 0xE) && (HtPhyEntry->Address <= 0x11))) {
+    PhyReg |= HTPHY_DIRECT_MAP;
+  }
+
+  PhyReg |= (HtPhyEntry->Address);
+  // Ask the portal to read the HT Phy Register contents
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+
+  // Get the current register contents and do the update requested by the table
+  PhyBase.AddressValue += 4;
+  LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  Temp &= ~(HtPhyEntry->Mask);
+  Temp |= (HtPhyEntry->Data);
+  LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader);
+
+  PhyBase.AddressValue -= 4;
+  // Ask the portal to write our updated value to the HT Phy
+  PhyReg |= HTPHY_WRITE_CMD;
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Applies an HT Phy write to a specified Phy register.
+ *
+ * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}.
+ *
+ * The caller is responsible for performing any read and modify steps.
+ * This function performs the necessary sequence of PCI reads, writes, and waits
+ * necessary to program an HT Phy register.
+ *
+ * @param[in]  CapabilitySet The link's HT Host base address.
+ * @param[in]  Link          Zero based, node, link number (not package link).
+ * @param[in]  Address       The HT Phy register address
+ * @param[in]  Data          The data to write to the register
+ * @param[in]  StdHeader     Config handle for library and services
+ *
+ */
+VOID
+STATIC
+F15WriteOnlyHtPhyRegister (
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       UINT32                   Address,
+  IN       UINT32                   Data,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  UINT32    Temp;
+  UINT32    PhyReg;
+  PCI_ADDR  PhyBase;
+
+  // Determine the PCI config address of the HT Phy portal
+  PhyBase = CapabilitySet;
+  PhyBase.Address.Function = FUNC_4;
+  PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180);
+
+  LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+
+  // Handle direct map registers if needed
+  PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK);
+  if ((Address > 0x3FF) || ((Address >= 0xE) && (Address <= 0x11))) {
+    PhyReg |= HTPHY_DIRECT_MAP;
+  }
+
+  PhyReg |= (Address);
+
+  // Get the current register contents and do the update requested by the table
+  PhyBase.AddressValue += 4;
+  LibAmdPciWrite (AccessWidth32, PhyBase, &Data, StdHeader);
+
+  PhyBase.AddressValue -= 4;
+  // Ask the portal to write our updated value to the HT Phy
+  PhyReg |= HTPHY_WRITE_CMD;
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the value of an HT PHY register.
+ *
+ * Reading HT Phy registers is not generally useful, because they return the effective value,
+ * not the currently written value.  So be warned, this function is dangerous if used to read
+ * a register that will be udpated subsequently elsewhere.
+ *
+ * This routine is useful for reading hardware status from the HT Phy that can be used to set
+ * other phy registers.
+ *
+ * @param[in]  CapabilitySet The link's HT Host base address.
+ * @param[in]  Link          Zero based, node link number (not package link).
+ * @param[in]  Address       The HT Phy register address to read
+ * @param[in]  StdHeader     Config handle for library and services
+ *
+ * @return     The register content (in most cases, the effective content not the pending content)
+ *
+ */
+UINT32
+STATIC
+F15GetHtPhyRegister (
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       UINT32                   Address,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  UINT32    Temp;
+  UINT32    PhyReg;
+  PCI_ADDR  PhyBase;
+
+  // Determine the PCI config address of the HT Phy portal
+  PhyBase = CapabilitySet;
+  PhyBase.Address.Function = FUNC_4;
+  PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180);
+
+  LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+
+  // Handle direct map registers if needed
+  PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK);
+  if ((Address > 0x3FF) || ((Address >= 0xE) && (Address <= 0x11))) {
+    PhyReg |= HTPHY_DIRECT_MAP;
+  }
+
+  PhyReg |= Address;
+  // Ask the portal to read the HT Phy Register contents
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+
+  // Get the current register contents
+  PhyBase.AddressValue += 4;
+  LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+
+  return Temp;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * A Family Specific Workaround method, to override HT DLL Compensation.
+ *
+ * \@TableTypeFamSpecificInstances.
+ *
+ * The Link Product Information register can be fused to contain an HT PHY DLL Compensation Override table.
+ * Based on link frequency, a compensation override can be selected from the value.
+ * To accomodate individual link differences in the package, each link can also have a DLL process compensation
+ * value set.  This value can apply an adjustment to the compensation value.
+ *
+ * @param[in]     Data       The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]     StdHeader  Config params for library, services.
+ */
+VOID
+F15HtPhyOverrideDllCompensation (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                ProductLinkInfo;
+  UINT32                Link;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              StartingCapabilitySet;
+  PCI_ADDR              CapabilitySet;
+  PCI_ADDR              PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+  UINTN                 Sublink;
+  HT_PHY_LINK_FEATS     DesiredLinkFeats;
+  BOOLEAN               IsEarlyRevProcessor;
+  BOOLEAN               IsHardwareReportingComp;
+  UINTN                 LinkFrequency;
+  UINT32                Compensation;
+  UINT32                Adjustment;
+  BOOLEAN               IsIncrementAdjust;
+  LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL LinkPhyReceiverProcessFuseControl;
+  LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL  LinkPhyReceiverProcessDllControl;
+
+  OptionMultiSocketConfiguration.GetCurrPciAddr (&StartingCapabilitySet, StdHeader);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+
+  // Check if the hardware reported any compensation values.
+  IsEarlyRevProcessor = (BOOLEAN) ((Data == 0) ? TRUE : FALSE);
+  PciAddress = StartingCapabilitySet;
+  PciAddress.Address.Function = FUNC_5;
+  PciAddress.Address.Register = 0x190;
+  LibAmdPciRead (AccessWidth32, PciAddress, &ProductLinkInfo, StdHeader);
+  IsHardwareReportingComp = (BOOLEAN) (ProductLinkInfo != 0);
+
+  if (!IsEarlyRevProcessor || IsHardwareReportingComp) {
+    // Process all the sublink 0's and then all the sublink 1's that are at HT3 frequency.
+    for (Sublink = 0; Sublink < 2; Sublink++) {
+      CapabilitySet = StartingCapabilitySet;
+      Link = 0;
+      DesiredLinkFeats.HtPhyLinkValue = ((Sublink == 0) ? HTPHY_LINKTYPE_SL0_HT3 : HTPHY_LINKTYPE_SL0_HT3);
+      while (FamilySpecificServices->NextLinkHasHtPhyFeats (
+               FamilySpecificServices,
+               &CapabilitySet,
+               &Link,
+               &DesiredLinkFeats,
+               &MatchedSublink1,
+               &Freq0,
+               &Freq1,
+               StdHeader)) {
+
+        // Look up compensation value.  Remember that we matched links which are at HT3 frequency, so Freq[1,0]
+        // should safely be greater than or equal to 1.2 GHz.
+        if (Sublink == 0) {
+          LinkFrequency = Freq0 - HT_FREQUENCY_1200M;
+        } else {
+          LinkFrequency = (MatchedSublink1 ? Freq1 : Freq0) - HT_FREQUENCY_1200M;
+        }
+        // This assert would catch frequencies higher than we know how to support, or any table overrun bug.
+        ASSERT (LinkFrequency < (sizeof (HtPhyDllCompLookupTable) / sizeof (HT_PHY_DLL_COMP_LOOKUP_TABLE)));
+        // Since there are invalid entries in the table, for frequency enum skipped values, ensure we did not
+        // pick one of those entries.  This should be impossible from real hardware.
+        ASSERT (HtPhyDllCompLookupTable[LinkFrequency].DefaultComp != 0xFFFFFFFFul);
+
+        if (IsHardwareReportingComp) {
+          LibAmdPciReadBits (
+            PciAddress,
+            HtPhyDllCompLookupTable[LinkFrequency].CtlIndexHiBit,
+            HtPhyDllCompLookupTable[LinkFrequency].CtlIndexLoBit,
+            &Compensation,
+            StdHeader);
+        } else {
+          Compensation = HtPhyDllCompLookupTable[LinkFrequency].DefaultComp;
+        }
+
+        // Apply any per PHY adjustment
+        LinkPhyReceiverProcessFuseControl.Value = F15GetHtPhyRegister (
+          CapabilitySet,
+          Link,
+          ((Sublink == 0) ? HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL0 : HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL1),
+          StdHeader);
+        Adjustment = LinkPhyReceiverProcessFuseControl.Fields.DllProcessComp10;
+        IsIncrementAdjust = (BOOLEAN) ((LinkPhyReceiverProcessFuseControl.Fields.DllProcessComp2 == 0) ? TRUE : FALSE);
+        if (IsIncrementAdjust) {
+          Compensation = (((Compensation + Adjustment) > 0x000F) ? 0x000F : (Compensation + Adjustment));
+        } else {
+          // decrement adjustment
+          Compensation = ((Compensation < Adjustment) ? 0 : (Compensation - Adjustment));
+        }
+
+        // Update the DLL Compensation
+        LinkPhyReceiverProcessDllControl.Value = F15GetHtPhyRegister (
+          CapabilitySet,
+          Link,
+          HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_RD,
+          StdHeader);
+        LinkPhyReceiverProcessDllControl.Fields.DllProcessFreqCtlOverride = 1;
+        LinkPhyReceiverProcessDllControl.Fields.DllProcessFreqCtlIndex2 = Compensation;
+        F15WriteOnlyHtPhyRegister (
+          CapabilitySet,
+          Link,
+          ((Sublink == 0) ? HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL0 : HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL1),
+          LinkPhyReceiverProcessDllControl.Value,
+          StdHeader);
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F15CommonGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NbVidUpdateAll = FALSE;
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      PlatformConfig                 Platform profile/build option config structure.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F15IsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   LocalPciRegister;
+  PCI_ADDR PciAddress;
+  BOOLEAN  PowerMode;
+  BOOLEAN  SkipHwCfg;
+
+  SkipHwCfg = FALSE;
+
+  IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader);
+
+  // Defaults to Power Optimized Mode
+  PowerMode = TRUE;
+
+  // If system is optimized for performance, disable NB P-States
+  if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) {
+    PowerMode = FALSE;
+  }
+
+  PciAddress.AddressValue = F15_NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  if ((((((F15_NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal != 0) &&
+      (!IsNonCoherentHt1 (StdHeader))) || SkipHwCfg) && (PowerMode)) {
+    return TRUE;
+  }
+  return FALSE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.h
new file mode 100644
index 0000000000..5414ba9da0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.h
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 15h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F15_UTILITES_H_
+#define _CPU_F15_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// The structure for Software Initiated NB Voltage Transitions
+typedef struct {
+  UINT32  VidCode;          ///< VID code to transition to
+  BOOLEAN SlamMode;         ///< Whether voltage is to be slammed, or stepped
+} SW_VOLT_TRANS_NB;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+F15DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F15TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F15GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F15LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F15HtPhyOverrideDllCompensation (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+BOOLEAN
+F15GetNextHtLinkFeatures (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   UINTN                  *Link,
+  IN OUT   PCI_ADDR               *LinkBase,
+     OUT   HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F15NextLinkHasHtPhyFeats (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PCI_ADDR           *HtHostCapability,
+  IN OUT   UINT32             *Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+     OUT   BOOLEAN            *MatchedSublink1,
+     OUT   HT_FREQUENCIES     *Frequency0,
+     OUT   HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+F15SetHtPhyRegister (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+BOOLEAN
+F15CommonGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F15IsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif  // _CPU_F15_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
new file mode 100644
index 0000000000..ffa56c39ba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
@@ -0,0 +1,154 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_15 WHEA initial Data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x15
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF15WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F15WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AMD_HEST_BANK_INIT_DATA F15HestBankInitData[] = {
+  {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
+  {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
+  {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
+  {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
+  {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
+  {0xFFFFFFFF,0xFFFFFFFF,0x418,0x419,0x41A,0x41B},
+};
+
+AMD_WHEA_INIT_DATA F15WheaInitData = {
+  0x000000000,              // AmdGlobCapInitDataLsd
+  0x000000000,              // AmdGlobCapInitDataMsd
+  0x000000077,              // AmdGlobCtrlInitDataLsd
+  0x000000000,              // AmdGlobCtrlInitDataMsd
+  0x00,                     // AmdMcbClrStatusOnInit
+  0x02,                     // AmdMcbStatusDataFormat
+  0x00,                     // AmdMcbConfWriteEn
+  (sizeof (F15HestBankInitData) / sizeof (F15HestBankInitData[0])), // HestBankNum
+  &F15HestBankInitData[0]   // Pointer to Initial data of HEST Bank
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific WHEA table properties.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  F15WheaInitDataPtr       Points to the family 15h WHEA properties.
+ *  @param[out]  NumberOfElements         Will be one to indicate one structure.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF15WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F15WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *F15WheaInitDataPtr = &F15WheaInitData;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h
new file mode 100644
index 0000000000..1f288fc180
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h
@@ -0,0 +1,275 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FAM_REGISTERS_H_
+#define _CPU_FAM_REGISTERS_H_
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      M O D U L E S    U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      D E F I N I T I O N S  /  M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+// This define should be equal to the total number of families
+// in the cpuFamily enum.
+#define MAX_CPU_FAMILIES    64
+#define MAX_CPU_REVISIONS   63    // Max Cpu Revisions Per Family
+
+// CPU_LOGICAL_ID.Family equates
+// Family 10h equates
+#define AMD_FAMILY_10_RB  0x0000000000000001ull
+#define AMD_FAMILY_10_BL  0x0000000000000002ull
+#define AMD_FAMILY_10_DA  0x0000000000000004ull
+#define AMD_FAMILY_10_HY  0x0000000000000008ull
+#define AMD_FAMILY_10_PH  0x0000000000000010ull
+#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
+
+#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)
+#define AMD_FAMILY_GH    (AMD_FAMILY_10)
+
+// Family 12h equates
+#define AMD_FAMILY_12_LN  0x0000000000000020ull
+#define AMD_FAMILY_12     (AMD_FAMILY_12_LN)
+#define AMD_FAMILY_LN     (AMD_FAMILY_12_LN)
+
+// Family 14h equates
+#define AMD_FAMILY_14_ON  0x0000000000000040ull
+#define AMD_FAMILY_ON     (AMD_FAMILY_14_ON)
+#define AMD_FAMILY_14_KR  0x0000000000000080ull
+#define AMD_FAMILY_KR     (AMD_FAMILY_14_KR)
+#define AMD_FAMILY_14     (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR)
+
+// Family 15h equates
+#define AMD_FAMILY_15_OR  0x0000000000000100ull
+#define AMD_FAMILY_OR     (AMD_FAMILY_15_OR)
+#define AMD_FAMILY_15_TN  0x0000000000000200ull
+#define AMD_FAMILY_TN     (AMD_FAMILY_15_TN)
+
+
+// Family Unknown
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
+
+// Family Group equates
+#define AMD_FAMILY_GE_12   (AMD_FAMILY_12 | AMD_FAMILY_14 | (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull)  | 0x0000000000010000ull )
+
+// Family 10h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+  // Family 10h RB steppings
+#define AMD_F10_RB_C0      0x0000000000000001ull
+#define AMD_F10_RB_C1      0x0000000000000002ull
+#define AMD_F10_RB_C2      0x0000000000000004ull
+#define AMD_F10_RB_C3      0x0000000000000008ull
+  // Family 10h BL steppings
+#define AMD_F10_BL_C2      0x0000000000000010ull
+#define AMD_F10_BL_C3      0x0000000000000020ull
+  // Family 10h DA steppings
+#define AMD_F10_DA_C2      0x0000000000000040ull
+#define AMD_F10_DA_C3      0x0000000000000080ull
+  // Family 10h HY SCM steppings
+#define AMD_F10_HY_SCM_D0  0x0000000000000100ull
+#define AMD_F10_HY_SCM_D1  0x0000000000000400ull
+  // Family 10h HY MCM steppings
+#define AMD_F10_HY_MCM_D0  0x0000000000000200ull
+#define AMD_F10_HY_MCM_D1  0x0000000000000800ull
+  // Family 10h PH steppings
+#define AMD_F10_PH_E0      0x0000000000001000ull
+
+  // Family 10h Unknown stepping
+  // * This equate is used to ensure that unknown CPU revisions are       *
+  // * identified as the last known revision of the silicon family:       *
+  // * - Update AMD_F10_UNKNOWN whenever newer F10h steppings are added   *
+#define AMD_F10_UNKNOWN    (AMD_FAMILY_UNKNOWN | AMD_F10_C3 | AMD_F10_D1 | AMD_F10_PH_E0)
+
+  // Family 10h Miscellaneous equates
+#define AMD_F10_C0 (AMD_F10_RB_C0)
+#define AMD_F10_C1 (AMD_F10_RB_C1)
+#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2)
+#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3)
+#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3)
+
+#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3)
+
+#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3)
+#define AMD_F10_BL_Cx  (AMD_F10_BL_C2 | AMD_F10_BL_C3)
+
+#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3)
+#define AMD_F10_DA_Cx  (AMD_F10_DA_C2 | AMD_F10_DA_C3)
+
+#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0)
+#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1)
+#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1)
+
+#define AMD_F10_PH_ALL (AMD_F10_PH_E0)
+#define AMD_F10_Ex (AMD_F10_PH_E0)
+
+#define AMD_F10_HY_ALL (AMD_F10_Dx)
+#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1)
+
+#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
+#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
+#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
+#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
+#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex)
+#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex)
+
+#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx  | AMD_F10_Ex)
+
+// Family 12h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+  // Family 12h LN steppings
+#define AMD_F12_LN_A0    0x0000000000000001ull
+#define AMD_F12_LN_A1    0x0000000000000002ull
+#define AMD_F12_LN_B0    0x0000000000000004ull
+
+  // Family 12h Unknown stepping
+  // * This equate is used to ensure that unknown CPU revisions are       *
+  // * identified as the last known revision of the silicon family:       *
+  // * - Update AMD_F12_UNKNOWN whenever newer F12h steppings are added   *
+#define AMD_F12_UNKNOWN  (AMD_FAMILY_UNKNOWN | AMD_F12_LN_B0)
+
+#define AMD_F12_LN_Ax    (AMD_F12_LN_A0 | AMD_F12_LN_A1)
+#define AMD_F12_LN_Bx    (AMD_F12_LN_B0)
+
+#define AMD_F12_ALL      (AMD_F12_LN_Ax | AMD_F12_LN_Bx)
+
+// Family 14h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+  // Family 14h ON steppings
+#define AMD_F14_ON_A0    0x0000000000000001ull
+#define AMD_F14_ON_A1    0x0000000000000002ull
+#define AMD_F14_ON_B0    0x0000000000000004ull
+#define AMD_F14_ON_C0    0x0000000000000008ull
+  // Family 14h KR steppings
+#define AMD_F14_KR_A0    0x0000000000000100ull
+#define AMD_F14_KR_A1    0x0000000000000200ull
+#define AMD_F14_KR_B0    0x0000000000000400ull
+
+  // Family 14h Unknown stepping
+  // * This equate is used to ensure that unknown CPU revisions are       *
+  // * identified as the last known revision of the silicon family:       *
+  // * - Update AMD_F14_UNKNOWN whenever newer F14h steppings are added   *
+#define AMD_F14_UNKNOWN  (AMD_FAMILY_UNKNOWN | AMD_F14_KR_B0 | AMD_F14_ON_C0)
+
+#define AMD_F14_ON_Ax    (AMD_F14_ON_A0 | AMD_F14_ON_A1)
+#define AMD_F14_ON_Bx    (AMD_F14_ON_B0)
+#define AMD_F14_ON_Cx    (AMD_F14_ON_C0)
+#define AMD_F14_ON_ALL   (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
+
+#define AMD_F14_KR_Ax    (AMD_F14_KR_A0 | AMD_F14_KR_A1)
+#define AMD_F14_KR_Bx    AMD_F14_KR_B0
+#define AMD_F14_KR_ALL   (AMD_F14_KR_Ax | AMD_F14_KR_Bx)
+
+#define AMD_F14_ALL      (AMD_F14_ON_ALL | AMD_F14_KR_ALL)
+
+// Family 15h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+  // Family 15h OROCHI steppings
+#define AMD_F15_OR_A0    0x0000000000000001ull
+#define AMD_F15_OR_A1    0x0000000000000002ull
+#define AMD_F15_OR_B0    0x0000000000000004ull
+#define AMD_F15_OR_B1    0x0000000000000008ull
+#define AMD_F15_OR_B2    0x0000000000000010ull
+  // Family 15h TN steppings
+#define AMD_F15_TN_A0    0x0000000000000100ull
+#define AMD_F15_TN_A1    0x0000000000000200ull
+  // Family 15h Unknown stepping
+  // * This equate is used to ensure that unknown CPU revisions are       *
+  // * identified as the last known revision of the silicon family:       *
+  // * - Update AMD_F15_UNKNOWN whenever newer F15h steppings are added   *
+
+#define AMD_F15_OR_Ax    (AMD_F15_OR_A0 | AMD_F15_OR_A1)
+#define AMD_F15_OR_Bx    (AMD_F15_OR_B0 | AMD_F15_OR_B1 | AMD_F15_OR_B2)
+#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx)
+#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
+#define AMD_F15_OR_ALL   (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
+
+#define AMD_F15_TN_Ax    (AMD_F15_TN_A0 | AMD_F15_TN_A1)
+#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0)
+#define AMD_F15_TN_ALL   (AMD_F15_TN_Ax)
+
+
+
+
+#endif      // _CPU_FAM_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c
new file mode 100644
index 0000000000..b728c6d1bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c
@@ -0,0 +1,245 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Preserve Registers used for AP Mailbox.
+ *
+ * Save and Restore the normal feature content of the registers being used for
+ * the AP Mailbox.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "PreserveMailbox.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  The contents of the mailbox registers should always be preserved.
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Always TRUE
+ *
+ */
+BOOLEAN
+STATIC
+IsPreserveAroundMailboxEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Save and Restore or Initialize the content of the mailbox registers.
+ *
+ * The registers used for AP mailbox should have the content related to their function
+ * preserved.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+PreserveMailboxes (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;
+  UINT32 Socket;
+  UINT32 Module;
+  PCI_ADDR BaseAddress;
+  PCI_ADDR MailboxRegister;
+  PRESERVE_MAILBOX_FAMILY_REGISTER *NextRegister;
+  AGESA_STATUS IgnoredStatus;
+  AGESA_STATUS HeapStatus;
+  UINT32 Value;
+  ALLOCATE_HEAP_PARAMS AllocateParams;
+  LOCATE_HEAP_PTR LocateParams;
+  UINT32 RegisterEntryIndex;
+
+  BaseAddress.AddressValue = ILLEGAL_SBDFO;
+
+  if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {
+    // The save step.  Save either the register content or zero (for cold boot, if family specifies that).
+    AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
+    AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));
+    AllocateParams.Persist = HEAP_SYSTEM_MEM;
+    HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);
+    ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));
+    LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);
+    RegisterEntryIndex = 0;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
+          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+          ASSERT (FamilySpecificServices != NULL);
+          NextRegister = FamilySpecificServices->RegisterList;
+          while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) {
+            ASSERT (RegisterEntryIndex <
+                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
+            if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {
+              Value = 0;
+            } else {
+              MailboxRegister = BaseAddress;
+              MailboxRegister.Address.Function = NextRegister->Register.Address.Function;
+              MailboxRegister.Address.Register = NextRegister->Register.Address.Register;
+              LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
+              Value &= NextRegister->Mask;
+            }
+            (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;
+            RegisterEntryIndex++;
+            NextRegister++;
+          }
+        }
+      }
+    }
+  } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {
+    // The restore step.  Just write out the saved content in the buffer.
+    LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
+    HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);
+    ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));
+    RegisterEntryIndex = 0;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
+          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+          NextRegister = FamilySpecificServices->RegisterList;
+          while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) {
+            ASSERT (RegisterEntryIndex <
+                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
+            MailboxRegister = BaseAddress;
+            MailboxRegister.Address.Function = NextRegister->Register.Address.Function;
+            MailboxRegister.Address.Register = NextRegister->Register.Address.Register;
+            LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
+            Value = ((Value & ~NextRegister->Mask) | (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex]);
+            LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);
+            RegisterEntryIndex++;
+            NextRegister++;
+          }
+        }
+      }
+    }
+    HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox =
+{
+  PreserveAroundMailbox,
+  (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsPreserveAroundMailboxEnabled,
+  PreserveMailboxes
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.h
new file mode 100644
index 0000000000..5debbd55bb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.h
@@ -0,0 +1,124 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Preserve Registers used for AP Mailbox.
+ *
+ * Save and Restore the normal feature content of the registers being used for
+ * the AP Mailbox.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _PRESERVE_MAILBOX_H_
+#define _PRESERVE_MAILBOX_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#define MAX_PRESERVE_REGISTER_ENTRIES 2      ///< There is room on the heap for up to this per node.
+
+/// Reference to a save buffer.
+typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES];
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Family specific mailbox register descriptor.
+ *
+ * Describes a register and bits within the register used as the mailbox.
+ */
+typedef struct  {
+  PCI_ADDR Register;                          ///< The PCI address of a mailbox register.
+  UINT32   Mask;                              ///< The mask of bits used in Register as the mailbox.
+} PRESERVE_MAILBOX_FAMILY_REGISTER;
+
+/**
+ * Descriptor for family specific save-restore.
+ *
+ * Provide a list of the register offsets to save-restore on each node.  Optionally, zero the
+ * register instead of restoring it.
+ */
+typedef struct  {
+  UINT16          Revision;                        ///< Interface version
+  // Public Data.
+  BOOLEAN                           IsZeroOnCold;  ///< On a cold boot, zero the register instead of restore.
+  PRESERVE_MAILBOX_FAMILY_REGISTER *RegisterList;  ///< The list of registers, terminated by ILLEGAL_SBDFO.
+} PRESERVE_MAILBOX_FAMILY_SERVICES;
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _PRESERVE_MAILBOX_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c
new file mode 100644
index 0000000000..da34905afd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c
@@ -0,0 +1,231 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Application Power Management (APM) feature support code.
+ *
+ * Contains code that declares the AGESA CPU APM related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "cpuFeatures.h"
+#include "cpuApm.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUAPM_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableApmOnSocket (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE ApmFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should Application Power Management (APM) be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               APM is supported.
+ * @retval       FALSE              APM cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsApmFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32              Socket;
+  BOOLEAN             IsEnabled;
+  APM_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&ApmFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+      if (FamilyServices != NULL) {
+        if (FamilyServices->IsApmSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
+          IsEnabled = TRUE;
+          break;
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Application Power Management (APM)
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeApmFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       BscSocket;
+  UINT32       Ignored;
+  UINT32       Socket;
+  UINT32       NumberOfSockets;
+  AP_TASK      TaskPtr;
+  AGESA_STATUS IgnoredSts;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    APM mode is enabled\n");
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  TaskPtr.FuncAddress.PfApTaskI = EnableApmOnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = PlatformConfig;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      if (Socket != BscSocket) {
+        ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader);
+      }
+    }
+  }
+
+  EnableApmOnSocket (PlatformConfig, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  AP task to enable APM
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+EnableApmOnSocket (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  APM_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&ApmFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->EnableApmOnSocket (FamilyServices,
+                                     PlatformConfig,
+                                     StdHeader);
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm =
+{
+  CpuApm,
+  CPU_FEAT_BEFORE_RELINQUISH_AP,
+  IsApmFeatureEnabled,
+  InitializeApmFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h
new file mode 100644
index 0000000000..7fd18142a3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h
@@ -0,0 +1,156 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Application Power Management (APM) Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU APM related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_APM_H_
+#define _CPU_APM_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (APM_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Application Power Management (APM) is supported.
+ *
+ * @param[in]    ApmServices        APM services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               APM is supported.
+ * @retval       FALSE              APM is not supported.
+ *
+ */
+typedef BOOLEAN F_APM_IS_SUPPORTED (
+  IN       APM_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_APM_IS_SUPPORTED *PF_APM_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable APM.
+ *
+ * @param[in]    ApmServices        APM services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_APM_INIT (
+  IN       APM_FAMILY_SERVICES    *ApmServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_APM_INIT *PF_APM_INIT;
+
+/**
+ * Provide the interface to the APM Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _APM_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_APM_IS_SUPPORTED IsApmSupported;                                   ///< Method: Family specific call to check if APM is supported.
+  PF_APM_INIT         EnableApmOnSocket;                                ///< Method: Family specific call to enable APM.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_APM_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c
new file mode 100644
index 0000000000..0e55e48a19
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c
@@ -0,0 +1,287 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU C6 feature support code.
+ *
+ * Contains code that declares the AGESA CPU C6 related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMultiSocket.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableC6OnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should C6 be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 is supported.
+ * @retval       FALSE              C6 cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsC6FeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32             Socket;
+  BOOLEAN            IsEnabled;
+  C6_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->CStateMode == CStateModeC6) {
+    IsEnabled = TRUE;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) {
+          IsEnabled = FALSE;
+          break;
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the C6 C-state
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeC6Feature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  BscSocket;
+  UINT32  Ignored;
+  UINT32  BscCoreNum;
+  UINT32  Core;
+  UINT32  Socket;
+  UINT32  NumberOfSockets;
+  UINT32  NumberOfCores;
+  AP_TASK TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+  C6_FAMILY_SERVICES  *C6FamilyServices;
+  AGESA_STATUS IgnoredSts;
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    // Load any required microcode patches on both normal boot and resume from S3.
+    IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+    GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader);
+    if (C6FamilyServices != NULL) {
+      C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
+    }
+
+    // run code on all APs
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.ExeFlags = 0;
+
+    NumberOfSockets = GetPlatformNumberOfSockets ();
+
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader);
+        if (C6FamilyServices != NULL) {
+          // run code on all APs
+          TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
+          if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+            for (Core = 0; Core < NumberOfCores; Core++) {
+              if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+                ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable C6 on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableC6OnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+
+  C6_FAMILY_SERVICES *FamilyServices;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    C6 is enabled\n");
+
+  GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeC6 (FamilyServices,
+                                *((UINT64 *) EntryPoint),
+                                &CpuEarlyParams->PlatformConfig,
+                                StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Reload microcode patch after memory is initialized.
+ *
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+ReloadMicrocodePatchAfterMemInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LoadMicrocodePatch (StdHeader);
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State =
+{
+  C6Cstate,
+  (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsC6FeatureEnabled,
+  InitializeC6Feature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h
new file mode 100644
index 0000000000..68a61b9d98
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h
@@ -0,0 +1,183 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU C6 Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C6 related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_C6_STATE_H_
+#define _CPU_C6_STATE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if C6 is supported.
+ *
+ * @param[in]    C6Services         C6 C-state services.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 is supported.
+ * @retval       FALSE              C6 is not supported.
+ *
+ */
+typedef BOOLEAN F_C6_IS_SUPPORTED (
+  IN       C6_FAMILY_SERVICES      *C6Services,
+  IN       UINT32                  Socket,
+  IN       PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable C6.
+ *
+ * @param[in]    C6Services         C6 services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_C6_INIT (
+  IN       C6_FAMILY_SERVICES      *C6Services,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_INIT             *PF_C6_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to reload microcode patch after memory is initialized.
+ *
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+typedef VOID F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT (
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT    *PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT;
+
+/**
+ * Provide the interface to the C6 Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _C6_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_C6_IS_SUPPORTED     IsC6Supported;                                 ///< Method: Family specific call to check if C6 is supported.
+  PF_C6_INIT             InitializeC6;                                  ///< Method: Family specific call to enable C6.
+  PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT  ReloadMicrocodePatchAfterMemInit;   ///< Method: Family specific call to reload microcode patch after memory is initialized.
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Reload microcode patch after memory is initialized.
+ *
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+ReloadMicrocodePatchAfterMemInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_C6_STATE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
new file mode 100644
index 0000000000..3f95f5248b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -0,0 +1,226 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to initialize Cache Flush On Halt feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableCacheFlushOnHaltOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+AGESA_STATUS
+InitializeCacheFlushOnHaltFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should cache flush on halt be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               core leveling is supported.
+ * @retval       FALSE              core leveling cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCFOHEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return (TRUE);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  InitializeCacheFlushOnHaltFeature
+ *
+ *    CPU feature leveling. Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       EntryPoint       Timepoint designator.
+ *    @param[in]       PlatformConfig   Contains the runtime modifiable feature input data.
+ *    @param[in,out]   StdHeader        Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @return          The most severe status of any family specific service.
+ */
+AGESA_STATUS
+InitializeCacheFlushOnHaltFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+
+  AP_TASK      TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Cache flush on hlt feature is enabled\n");
+  TaskPtr.FuncAddress.PfApTaskIC = EnableCacheFlushOnHaltOnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable Cache Flush On Halt on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableCacheFlushOnHaltOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  CPU_CFOH_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  if (FamilyServices != NULL) {
+    FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader);
+  }
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt =
+{
+  CacheFlushOnHalt,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsCFOHEnabled,
+  InitializeCacheFlushOnHaltFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
new file mode 100644
index 0000000000..3c37dd500d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
@@ -0,0 +1,778 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Topology.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCacheInit.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+// 4G - 1, ~max ROM space
+#define SIZE_INFINITE_EXE_CACHE 0xFFFFFFFFul
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *             L2 cache Association to Way translation table
+ *----------------------------------------------------------------------------
+ */
+CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] =
+{
+  0,
+  1,
+  2,
+  0xFF,
+  4,
+  0xFF,
+  8,
+  0xFF,
+  16,
+  0xFF,
+  32,
+  48,
+  64,
+  96,
+  128,
+  0xFF,
+};
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT8
+STATIC
+Ceiling (
+  IN UINT32 Divisor,
+  IN UINT32 Dividend
+  );
+
+UINT32
+STATIC
+CalculateOccupiedExeCache (
+  IN AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+CompareRegions (
+  IN      EXECUTION_CACHE_REGION  ARegion,
+  IN      EXECUTION_CACHE_REGION  BRegion,
+  IN OUT  MERGED_CACHE_REGION     *CRegion,
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN      UINT32                  TestNumber
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will setup ROM execution cache.
+ *
+ * The execution cache regions are passed in, the max number of execution cache regions
+ * is three.  Several rules are checked for compliance. If a rule test fails then one of
+ * these error suffixes will be added to the general CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR
+ * in the SubReason field
+ *   -1  available cache size is less than requested, the ROM execution cache
+ *       region has been reduced or eliminated.
+ *   -2  at least one execution cache region crosses the 1MB line, the ROM execution
+ *       cache size has been reduced.
+ *   -3  at least one execution cache region crosses the 4GB line, the ROM execution
+ *       cache size has been reduced.
+ *   -4  the start address of a region is not at the boundary of cache size,
+ *        the starting address has been adjusted downward
+ *   -5  execution cache start address less than D0000, request is ignored
+ *   -6  more than 2 execution cache regions are above 1MB, request is ignored
+ * If the start address of all three regions are zero, then no execution cache is allocated.
+ *
+ * @param[in]   StdHeader          Handle to config for library and services
+ * @param[in]   AmdExeAddrMapPtr   Pointer to the start of EXECUTION_CACHE_REGION array
+ *
+ * @retval      AGESA_SUCCESS      No error
+ * @retval      AGESA_WARNING      AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB;
+ *                                 AGESA_CACHE_REGIONS_ACROSS_4GB;
+ * @retval      AGESA_ERROR        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY;
+ *                                 AGESA_CACHE_START_ADDRESS_LESS_D0000;
+ *                                 AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
+ *
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+  IN AMD_CONFIG_PARAMS *StdHeader,
+  IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  AGESA_STATUS               AgesaStatus;
+  AMD_GET_EXE_SIZE_PARAMS    AmdGetExeSize;
+  UINT32                     CurrentAllocatedExeCacheSize;
+  UINT32                     RemainingExecutionCacheSize;
+  UINT64                     MsrData;
+  UINT64                     SecondMsrData;
+  UINT32                     RequestStartAddr;
+  UINT32                     RequestSize;
+  UINT32                     StartFixMtrr;
+  UINT32                     CurrentMtrr;
+  UINT32                     EndFixMtrr;
+  UINT8                      i;
+  UINT8                      Ignored;
+  CACHE_INFO                 *CacheInfoPtr;
+  CPU_SPECIFIC_SERVICES      *FamilySpecificServices;
+  EXECUTION_CACHE_REGION      MtrrV6;
+  EXECUTION_CACHE_REGION      MtrrV7;
+  MERGED_CACHE_REGION         Result;
+
+  //
+  // If start addresses of all three regions are zero, then return early
+  //
+  if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) {
+    if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) {
+      if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) {
+        // No regions defined by the caller
+        return AGESA_SUCCESS;
+      }
+    }
+  }
+
+  // Get available cache size for ROM execution
+  AmdGetExeSize.StdHeader = *StdHeader;
+  AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize);
+  CurrentAllocatedExeCacheSize = CalculateOccupiedExeCache (StdHeader);
+  ASSERT (CurrentAllocatedExeCacheSize <= AmdGetExeSize.AvailableExeCacheSize);
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize);
+  RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
+
+  // Process each request entry 0 to 2
+  for (i = 0; i < 3; i++) {
+    // Exit if no more cache available
+    if (RemainingExecutionCacheSize == 0) {
+      break;
+    }
+
+    // Skip the region if ExeCacheSize = 0
+    if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) {
+      continue;
+    }
+
+    // Align starting addresses on 32K boundary
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr =
+      AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000;
+
+    // Adjust size to multiple of 32K (rounding up)
+    if ((AmdExeAddrMapPtr[i].ExeCacheSize % 0x8000) != 0) {
+      AmdExeAddrMapPtr[i].ExeCacheSize = ((AmdExeAddrMapPtr[i].ExeCacheSize + 0x8000) & 0xFFFF8000);
+    }
+
+    // Boundary alignment check and confirm size is an even power of two
+    if ( !IsPowerOfTwo (AmdExeAddrMapPtr[i].ExeCacheSize) ||
+    ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) ) {
+      AgesaStatus = AGESA_ERROR;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      break;
+    }
+
+    // Check start address boundary
+    if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) {
+      AgesaStatus = AGESA_ERROR;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_START_ADDRESS_LESS_D0000),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      break;
+    }
+
+    if (CacheInfoPtr->CarExeType == LimitedByL2Size) {
+      // Verify available execution cache size for region 0 to 2 request
+      if (RemainingExecutionCacheSize < AmdExeAddrMapPtr[i].ExeCacheSize) {
+        // Request is larger than available, reduce the allocation & report the change
+        AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize;
+        RemainingExecutionCacheSize = 0;
+        AgesaStatus = AGESA_WARNING;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_SIZE_REDUCED),
+                     i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      } else {
+        RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize;
+      }
+    }
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Exe cache allocated: Base 0x%x, Size 0x%x\n", AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize);
+
+    RequestStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
+    RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
+
+    if (RequestStartAddr < 0x100000) {
+      // Region starts below 1MB - Fixed MTTR region,
+      // turn on modification bit: MtrrFixDramModEn
+      LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+      MsrData |= 0x80000;
+      LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+
+      // Check for 1M boundary crossing
+      if ((RequestStartAddr + RequestSize) > 0x100000) {
+        // Request spans the 1M boundary, reduce the size & report the change
+        RequestSize = 0x100000 - RequestStartAddr;
+        AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize;
+        AgesaStatus = AGESA_WARNING;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_1MB),
+                     i, RequestStartAddr, RequestSize, 0, StdHeader);
+      }
+
+      // Find start MTTR and end MTTR for the requested region
+      StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
+      EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
+
+      //
+      //Check Mtrr before we use it,
+      //  if Mtrr has been used, we need to recover the previously allocated size.
+      //    (only work in blocks of 32K size - no splitting of ways)
+      for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
+        LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader);
+        if ((CacheInfoPtr->CarExeType == LimitedByL2Size) && (MsrData != 0)) {
+          // MTRR previously allocated, recover size
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000;
+        } else {
+          // Allocate this MTRR
+          MsrData = WP_IO;
+          LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader);
+        }
+      }
+      // Turn off modification bit: MtrrFixDramModEn
+      LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+      MsrData &= 0xFFFFFFFFFFF7FFFFULL;
+      LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+
+    } else {
+      // Region above 1MB -  Variable MTTR region
+      //    Need to check both VarMTRRs for each requested region for match or overlap
+      //
+
+      // Check for 4G boundary crossing   (using size-1 to keep in 32bit math range)
+      if ((0xFFFFFFFFUL - RequestStartAddr) < (RequestSize - 1)) {
+        RequestSize = (0xFFFFFFFFUL - RequestStartAddr) + 1;
+        AgesaStatus = AGESA_WARNING;
+        AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_4GB),
+                     i, RequestStartAddr, RequestSize, 0, StdHeader);
+      }
+      LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6, &MsrData, StdHeader);
+      MtrrV6.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL;
+      LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6 + 1, &MsrData, StdHeader);
+      MtrrV6.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1;
+
+      LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7, &MsrData, StdHeader);
+      MtrrV7.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL;
+      LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7 + 1, &MsrData, StdHeader);
+      MtrrV7.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1;
+
+      CompareRegions (AmdExeAddrMapPtr[i], MtrrV6, &Result, StdHeader);
+      if (Result.OverlapType == EmptySet) {
+        // MTRR6 is empty. Allocate request into MTRR6.
+        // Note: since all merges are moved down to MTRR6, if MTRR6 is empty so should MTRR7 also be empty
+        MtrrV6.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
+        MtrrV6.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize;
+      } else if ((Result.OverlapType == Disjoint) ||
+                 (Result.OverlapType == NotCombinable)) {
+        // MTRR6 is in use, and request does not overlap with MTRR6, check MTRR7
+        CompareRegions (AmdExeAddrMapPtr[i], MtrrV7, &Result, StdHeader);
+        if (Result.OverlapType == EmptySet) {
+          // MTRR7 is empty. Allocate request into MTRR7.
+          MtrrV7.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
+          MtrrV7.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize;
+        } else if ((Result.OverlapType == Disjoint) ||
+                   (Result.OverlapType == NotCombinable)) {
+          // MTRR7 is also in use and request does not overlap - error: 3rd region above 1M
+          AgesaStatus = AGESA_ERROR;
+          PutEventLog (AgesaStatus,
+                         (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_THREE_CACHE_REGIONS_ABOVE_1MB),
+                         i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+          break;
+        } else {
+          // Merge request with MTRR7
+          MtrrV7.ExeCacheStartAddr = Result.MergedStartAddr;
+          MtrrV7.ExeCacheSize = Result.MergedSize;
+          if (CacheInfoPtr->CarExeType == LimitedByL2Size) {
+            RemainingExecutionCacheSize += Result.OverlapAmount;
+          }
+        }
+      } else {
+        // Request overlaps with MTRR6, Merge request with MTRR6
+        MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr;
+        MtrrV6.ExeCacheSize = Result.MergedSize;
+        if (CacheInfoPtr->CarExeType == LimitedByL2Size) {
+          RemainingExecutionCacheSize += Result.OverlapAmount;
+        }
+        CompareRegions (MtrrV6, MtrrV7, &Result, StdHeader);
+        if ((Result.OverlapType != Disjoint) &&
+            (Result.OverlapType != EmptySet) &&
+            (Result.OverlapType != NotCombinable)) {
+          // MTRR6 and MTRR7 now overlap, merge them into MTRR6
+          MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr;
+          MtrrV6.ExeCacheSize = Result.MergedSize;
+          MtrrV7.ExeCacheStartAddr = 0;
+          MtrrV7.ExeCacheSize = 0;
+          if (CacheInfoPtr->CarExeType == LimitedByL2Size) {
+            RemainingExecutionCacheSize += Result.OverlapAmount;
+          }
+        }
+      }
+
+      // Set the VarMTRRs.  Base first, then size/mask; this allows for expanding the region safely.
+      if (MtrrV6.ExeCacheSize != 0) {
+        MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV6.ExeCacheSize - 1)) | 0x0800UL));
+        MsrData &= CacheInfoPtr->VariableMtrrMask;
+        SecondMsrData = (UINT64) ( MtrrV6.ExeCacheStartAddr | (WP_IO & 0xFULL));
+      } else {
+        MsrData = 0;
+        SecondMsrData = 0;
+      }
+      LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE6, &SecondMsrData, StdHeader);
+      LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE6 + 1), &MsrData, StdHeader);
+
+      if (MtrrV7.ExeCacheSize != 0) {
+        MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV7.ExeCacheSize - 1)) | 0x0800UL));
+        MsrData &= CacheInfoPtr->VariableMtrrMask;
+        SecondMsrData = (UINT64) ( MtrrV7.ExeCacheStartAddr | (WP_IO & 0xFULL));
+      } else {
+        MsrData = 0;
+        SecondMsrData = 0;
+      }
+      LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE7, &SecondMsrData, StdHeader);
+      LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE7 + 1), &MsrData, StdHeader);
+    } // endif of MTRR region check
+  } // end of requests For loop
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function calculates available L2 cache space for ROM execution.
+ *
+ * @param[in]   AmdGetExeSizeParams  Pointer to the start of AmdGetExeSizeParamsPtr structure
+ *
+ * @retval      AGESA_SUCCESS      No error
+ * @retval      AGESA_ALERT        No cache available for execution cache.
+ *
+ */
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  )
+{
+  UINT8     WayUsedForCar;
+  UINT8     L2Assoc;
+  UINT32    L2Size;
+  UINT32    L2WaySize;
+  UINT32    CurrentCoreNum;
+  UINT8     L2Ways;
+  UINT8     Ignored;
+  UINT32    DieNumber;
+  UINT32    TotalCores;
+  CPUID_DATA  CpuIdDataStruct;
+  CACHE_INFO  *CacheInfoPtr;
+  AP_MAIL_INFO ApMailboxInfo;
+  AGESA_STATUS IgnoredStatus;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
+  // CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space"
+  ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode);
+  if (CacheInfoPtr->CarExeType == InfiniteExe) {
+    AmdGetExeSizeParams->AvailableExeCacheSize = SIZE_INFINITE_EXE_CACHE;
+    return AGESA_SUCCESS;
+  }
+
+  // EXE cache size is limited by size of the L2, minus previous allocations for stack, heap, etc.
+  // Check for L2 cache size and way size
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader);
+  L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F);
+
+  // get L2Ways from L2 Association to Way translation table
+  L2Ways = L2AssocToL2WayTranslationTable[L2Assoc];
+  ASSERT (L2Ways != 0xFF);
+
+  // get L2Size
+  L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF);
+
+  // get each L2WaySize
+  L2WaySize = L2Size / L2Ways;
+
+  // Determine the size for execution cache
+  if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) {
+    // BSC (Boot Strap Core)
+    WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) +
+                    Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
+                    Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                    Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+  } else {
+    // AP (Application Processor)
+    GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader);
+
+    GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader);
+    DieNumber = (1 << ApMailboxInfo.Fields.ModuleType);
+    GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader);
+    ASSERT ((TotalCores % DieNumber) == 0);
+    if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) {
+      WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) +
+                      Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
+                      Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                      Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+    } else {
+      WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) +
+                      Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                      Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+    }
+  }
+
+  ASSERT (WayUsedForCar < L2Ways);
+
+  if (WayUsedForCar < L2Ways) {
+    AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar);
+    return AGESA_SUCCESS;
+  } else {
+    AmdGetExeSizeParams->AvailableExeCacheSize = 0;
+    return AGESA_ALERT;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function rounds a quotient up if the remainder is not zero.
+ *
+ * @param[in]   Divisor            The divisor
+ * @param[in]   Dividend           The dividend
+ *
+ * @retval      Value              Rounded quotient
+ *
+ */
+UINT8
+STATIC
+Ceiling (
+  IN UINT32 Divisor,
+  IN UINT32 Dividend
+  )
+{
+  if ((Divisor % Dividend) == 0) {
+    return (UINT8) (Divisor / Dividend);
+  } else {
+    return (UINT8) ((Divisor / Dividend) + 1);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function calculates the amount of cache that has already been allocated on the
+ * executing core.
+ *
+ * @param[in]   StdHeader       Handle to config for library and services
+ *
+ * @returns     Allocated size in bytes
+ *
+ */
+UINT32
+STATIC
+CalculateOccupiedExeCache (
+  IN AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64                     OccupExeCacheSize;
+  UINT64                     MsrData;
+  UINT8                      i;
+
+  MsrData = 0;
+  OccupExeCacheSize = 0;
+
+  //
+  //Calculate Variable MTRR base 6~7
+  //
+  for (i = 0; i < 2; i++) {
+    LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader);
+    if (MsrData != 0) {
+      LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader);
+      OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000);
+    }
+  }
+
+  //
+  //Calculate Fixed MTRR base D0000~F8000
+  //
+  for (i = 0; i < 6; i++) {
+    LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader);
+    if (MsrData!= 0) {
+      OccupExeCacheSize = OccupExeCacheSize + 0x8000;
+    }
+  }
+
+  return (UINT32)OccupExeCacheSize;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function compares two memory regions for overlap and returns the combined
+ *  Base,Size  to describe the new combined region.
+ *
+ * There are 13 cases for how two regions may overlap:  key: [] region A, ** region B
+ * 1- [  ] ***      9-  ***  [  ]   disjoint regions
+ * 2- [  ]***       10- ***[  ]     adjacent regions
+ * 3- [ ***]        11- **[**]      common ending
+ * 4- [  *]**       12- *[**  ]     extending
+ * 5- [ ** ]        13- *[*]*       contained
+ * 6- [***  ]                       common start, contained
+ * 7- [***]                         identity
+ * 8- [**]**                        common start, extending
+ * 0- one of the regions is empty (has base=0)
+ *
+ * @param[in]     ARegion       pointer to the base,size pair that describes region A
+ * @param[in]     BRegion       pointer to the base,size pair that describes region B
+ * @param[in,out] CRegion       pointer to the base,size pair that describes region C This struct also has the
+ *                              overlap type and the amount of overlap between the regions.
+ * @param[in]     StdHeader     Handle to config for library and services
+ *
+ * @returns       void, nothing
+ */
+
+VOID
+STATIC
+CompareRegions (
+  IN       EXECUTION_CACHE_REGION  ARegion,
+  IN       EXECUTION_CACHE_REGION  BRegion,
+  IN OUT   MERGED_CACHE_REGION     *CRegion,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  // Use Int64 to handle regions ending at or above the 4G boundary.
+  UINT64        EndOfA;
+  UINT64        EndOfB;
+
+
+  if ((BRegion.ExeCacheStartAddr == 0) ||
+      (ARegion.ExeCacheStartAddr == 0)) {
+    CRegion->MergedStartAddr  =
+    CRegion->MergedSize       =
+    CRegion->OverlapAmount    = 0;
+    CRegion->OverlapType = EmptySet;
+    return;
+  }
+  if (BRegion.ExeCacheStartAddr < ARegion.ExeCacheStartAddr) {
+    //swap regions A & B. this collapses types 9-13 onto 1-5 and reduces the number of tests
+    CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+    CRegion->MergedSize       = ARegion.ExeCacheSize;
+    ARegion                   = BRegion;
+    BRegion.ExeCacheStartAddr = CRegion->MergedStartAddr;
+    BRegion.ExeCacheSize      = CRegion->MergedSize;
+  }
+  CRegion->MergedStartAddr  =
+  CRegion->MergedSize       =
+  CRegion->OverlapType      =
+  CRegion->OverlapAmount    = 0;
+
+  if (ARegion.ExeCacheStartAddr == BRegion.ExeCacheStartAddr) {
+    // Common start, cases 6,7, or 8
+    if (ARegion.ExeCacheSize == BRegion.ExeCacheSize) {
+      // case 7, identity. Need to recover the overlap size
+      CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+      CRegion->MergedSize       = ARegion.ExeCacheSize;
+      CRegion->OverlapAmount    = ARegion.ExeCacheSize;
+      CRegion->OverlapType      = Identity;
+    } else if (ARegion.ExeCacheSize < BRegion.ExeCacheSize) {
+      // case 8, common start extending
+      CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+      CRegion->MergedSize       = BRegion.ExeCacheSize;
+      CRegion->OverlapType      = CommonStartExtending;
+      CRegion->OverlapAmount    = ARegion.ExeCacheSize;
+    } else {
+      // case 6, common start contained
+      CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+      CRegion->MergedSize       = ARegion.ExeCacheSize;
+      CRegion->OverlapType      = CommonStartContained;
+      CRegion->OverlapAmount    = BRegion.ExeCacheSize;
+    }
+  } else {
+    // A_Base is less than B_Base. check for cases 1-5
+    EndOfA = ((UINT64) ARegion.ExeCacheStartAddr) + ((UINT64) ARegion.ExeCacheSize);
+
+    if (EndOfA < ((UINT64) BRegion.ExeCacheStartAddr)) {
+      // case 1, disjoint
+      CRegion->MergedStartAddr  =
+      CRegion->MergedSize       =
+      CRegion->OverlapAmount    = 0;
+      CRegion->OverlapType = Disjoint;
+
+    } else if (EndOfA == ((UINT64) BRegion.ExeCacheStartAddr)) {
+      // case 2, adjacent
+      CRegion->OverlapType = Adjacent;
+      CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+      CRegion->MergedSize       = ARegion.ExeCacheSize + BRegion.ExeCacheSize;
+      CRegion->OverlapAmount    = 0;
+    } else {
+      // EndOfA is > B_Base. check for cases 3,4,5
+      EndOfB = ((UINT64) BRegion.ExeCacheStartAddr) + ((UINT64) BRegion.ExeCacheSize);
+
+      if ( EndOfA < EndOfB) {
+        // case 4, extending
+        CRegion->OverlapType = Extending;
+        CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+        CRegion->MergedSize       = (UINT32) (EndOfB - ((UINT64) ARegion.ExeCacheStartAddr));
+        CRegion->OverlapAmount    = (UINT32) (EndOfA - ((UINT64) BRegion.ExeCacheStartAddr));
+      } else {
+        // case 3, same end; or case 5, contained
+        CRegion->OverlapType = Contained;
+        CRegion->MergedStartAddr  = ARegion.ExeCacheStartAddr;
+        CRegion->MergedSize       = ARegion.ExeCacheSize;
+        CRegion->OverlapAmount    = BRegion.ExeCacheSize;
+      }
+    }
+  } // endif
+  // Once we have combined the regions, they must still obey the MTRR size and boundary rules
+  if ( CRegion->OverlapType != Disjoint ) {
+    if ((!(IsPowerOfTwo (CRegion->MergedSize))) ||
+       ((CRegion->MergedStartAddr % CRegion->MergedSize) != 0) ) {
+      CRegion->OverlapType = NotCombinable;
+    }
+  }
+
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This local function tests the parameter for being an even power of two
+ *
+ * @param[in]   TestNumber    Number to check
+ *
+ * @retval      TRUE - TestNumber is a power of two,
+ * @retval      FALSE - TestNumber is not a power of two
+ *
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN      UINT32                  TestNumber
+  )
+{
+  UINT32      PowerTwo;
+
+  ASSERT (TestNumber >= 0x8000UL);
+  PowerTwo = 0x8000UL;                    // Start at 32K
+  while ( TestNumber > PowerTwo ) {
+    PowerTwo = PowerTwo * 2;
+  }
+  return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h
new file mode 100644
index 0000000000..6e72bee9e0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h
@@ -0,0 +1,165 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_CACHE_INIT_H_
+#define _CPU_CACHE_INIT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define BSP_STACK_SIZE_64K        65536
+#define BSP_STACK_SIZE_32K        32768
+
+#define CORE0_STACK_SIZE          16384
+#define CORE1_STACK_SIZE          4096
+
+#define AMD_MTRR_FIX4K_BASE     0x268
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_VARIABLE_BASE7 0x20E
+
+#define WP_IO 0x0505050505050505ull
+
+#define AGESA_CACHE_SIZE_REDUCED              1
+#define AGESA_CACHE_REGIONS_ACROSS_1MB        2
+#define AGESA_CACHE_REGIONS_ACROSS_4GB        3
+#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY  4
+#define AGESA_CACHE_START_ADDRESS_LESS_D0000  5
+#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB   6
+#define AGESA_DEALLOCATE_CACHE_REGIONS        7
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Cache-As-Ram Executable region allocation modes
+typedef enum {
+  LimitedByL2Size,                            ///< Execution space must be allocated from L2
+  InfiniteExe,                                ///< Family can support unlimited Execution space
+  MaxCarExeMode                               ///< Used as limit or bounds check
+} CAR_EXE_MODE;
+
+/// Cache Information
+typedef struct {
+  IN       UINT32  BspStackSize;              ///< Stack size of BSP
+  IN       UINT32  Core0StackSize;            ///< Stack size of primary cores
+  IN       UINT32  Core1StackSize;            ///< Stack size of all non primary cores
+  IN       UINT32  MemTrainingBufferSize;     ///< Memory training buffer size
+  IN       UINT32  SharedMemSize;             ///< Shared memory size
+  IN       UINT64  VariableMtrrMask;          ///< Mask to apply before variable MTRR writes
+  IN       UINT64  VariableMtrrHeapMask;      ///< Mask to apply before variable MTRR writes for use in heap init.
+  IN       UINT64  HeapBaseMask;              ///< Mask used for the heap MTRR settings
+  IN CAR_EXE_MODE  CarExeType;                ///< Indicates which algorithm to use when allocating EXE space
+} CACHE_INFO;
+
+/// Merged memory region overlap type
+typedef enum {
+  EmptySet,                                   ///< One of the regions is zero length
+  Disjoint,                                   ///< The two regions do not touch
+  Adjacent,                                   ///< one region is next to the other, no gap
+  CommonEnd,                                  ///< regions overlap with a common end point
+  Extending,                                  ///< the 2nd region is extending the size of the 1st
+  Contained,                                  ///< the 2nd region is wholely contained inside the 1st
+  CommonStartContained,                       ///< the 2nd region is contained in the 1st with a common start
+  Identity,                                   ///< the two regions are the same
+  CommonStartExtending,                       ///< the 2nd region has same start as 1st, but is larger size
+  NotCombinable                               ///< the combined regions do not follow the cache block rules
+} OVERLAP_TYPE;
+
+/// Result of merging two memory regions for cache coverage
+typedef struct {
+  IN OUT  UINT32        MergedStartAddr;      ///< Start address of the merged regions
+  IN OUT  UINT32        MergedSize;           ///< Size of the merged regions
+     OUT  UINT32        OverlapAmount;        ///< the size of the overlapping section
+     OUT  OVERLAP_TYPE  OverlapType;          ///< indicates how the two regions overlap
+} MERGED_CACHE_REGION;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+  IN AMD_CONFIG_PARAMS *StdHeader,
+  IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  );
+
+#endif  // _CPU_CACHE_INIT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
new file mode 100644
index 0000000000..62129a70d3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
@@ -0,0 +1,369 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CDIT, ACPI table related API functions.
+ *
+ * Contains code that generates the CDIT table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SLIT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionCdit.h"
+#include "heapManager.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuL3Features.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUCDIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern OPTION_CDIT_CONFIGURATION OptionCditConfiguration;  // global user config record
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuCditHdrStruct =
+{
+  {'C','D','I','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'A','G','E','S','A',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+AcpiCditHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     E X P O R T E D     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiCditStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+  );
+
+AGESA_STATUS
+GetAcpiCditMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+   );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete CDIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[out]      CditPtr          Point to Cdit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiCdit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+  )
+{
+  AGESA_TESTPOINT (Agtp6d , StdHeader);
+  return ((*(OptionCditConfiguration.CditFeature)) (StdHeader, PlatformConfig, CditPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the CDIT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[out]      CditPtr          Point to Cdit Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiCditStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete CDIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[out]      CditPtr          Point to Cdit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiCditMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+   )
+{
+  UINT8 MaxHops;
+  UINT8 DomainNum;
+  UINT8 i;
+  UINT8 j;
+  UINT8 *BufferPtr;
+  UINT8 *SocketTopologyDataPtr;
+  UINT8 *SocketTopologyPtr;
+  UINT32 Socket;
+  BOOLEAN IsProbeFilterEnabled;
+  ACPI_TABLE_HEADER *CpuCditHeaderStructPtr;
+  AGESA_STATUS Flag;
+  ALLOCATE_HEAP_PARAMS AllocStruct;
+  L3_FEATURE_FAMILY_SERVICES *FamilyServices;
+
+  MaxHops = 0;
+  SocketTopologyPtr = NULL;
+  Flag = AGESA_ERROR;
+  IsProbeFilterEnabled = FALSE;
+
+  // find out the pointer to the BufferHandle which contains
+  // Node Topology information
+  AcpiCditHBufferFind (StdHeader, &SocketTopologyPtr);
+  if (SocketTopologyPtr == NULL) {
+    return (Flag);
+  }
+
+  DomainNum = *SocketTopologyPtr;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  CDIT is created\n");
+
+  // create a buffer by calling IBV callout routine
+  AllocStruct.RequestedBufferSize = (DomainNum * DomainNum) + AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + sizeof (ACPI_TABLE_HEADER);
+  AllocStruct.BufferHandle = AMD_ACPI_CDIT_BUFFER_HANDLE;
+  AllocStruct.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) {
+    return (Flag);
+  }
+  *CditPtr = AllocStruct.BufferPtr;
+
+  //CDIT header
+  LibAmdMemCopy (*CditPtr, (VOID *) &CpuCditHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+  CpuCditHeaderStructPtr = (ACPI_TABLE_HEADER *) *CditPtr;
+  CpuCditHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize;
+  BufferPtr = *CditPtr;
+
+  Flag = AGESA_SUCCESS;
+  // CDIT body
+  // Check if Probe Filter is enabled
+  if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) {
+    IsProbeFilterEnabled = TRUE;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if ((FamilyServices == NULL) || (!FamilyServices->IsHtAssistSupported (FamilyServices, PlatformConfig, StdHeader))) {
+          IsProbeFilterEnabled = FALSE;
+          break;
+        }
+      }
+    }
+  }
+
+
+  if (!IsProbeFilterEnabled) {
+    // probe filter is disabled
+    // get MaxHops
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (DomainNum);
+    for (i = 0; i < DomainNum; i++) {
+      for (j = 0; j < DomainNum; j++) {
+        if (*SocketTopologyDataPtr > MaxHops) {
+          MaxHops = *SocketTopologyDataPtr;
+        }
+        SocketTopologyDataPtr++;
+      }
+    }
+
+    // the Max hop entries have a value of 13
+    // and all other entries have 10.
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (DomainNum);
+    for (i = 0; i < DomainNum; i++) {
+      for (j = 0; j < DomainNum; j++) {
+        if (*SocketTopologyDataPtr++ == MaxHops) {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + (i * DomainNum) + j) = 13;
+        } else {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + (i * DomainNum) + j) = 10;
+        }
+      }
+    }
+  } else {
+    // probe filter is enabled
+    // formula : num_hops * 6 + 10
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (DomainNum);
+    for (i = 0; i < DomainNum; i++) {
+      for (j = 0; j < DomainNum; j++) {
+        *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+          AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + (i * DomainNum) + j) =
+          ((*SocketTopologyDataPtr++) * 6) + 10;
+      }
+    }
+  }
+
+  BufferPtr += sizeof (ACPI_TABLE_HEADER);
+  *((UINT32 *) BufferPtr) = (UINT32) DomainNum;
+
+  //Update CDIT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *CditPtr, StdHeader);
+
+  return (Flag);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Find out the pointer to the BufferHandle which contains
+ * Node Topology information
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in] SocketTopologyPtr      Point to the address of Socket Topology
+ *
+ */
+VOID
+STATIC
+AcpiCditHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBuffer;
+
+  LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) {
+    *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr;
+  }
+
+  return;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
new file mode 100644
index 0000000000..04d34a804e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -0,0 +1,389 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Core Leveling Function.
+ *
+ * Contains code to Level the number of core in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "AMD.h"
+#include "Topology.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuEarlyInit.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+CoreLevelingAtEarly (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should core leveling be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               core leveling is supported.
+ * @retval       FALSE              core leveling cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCoreLevelingEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CORE_LEVELING_TYPE  CoreLevelMode;
+
+  CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
+  if (CoreLevelMode != CORE_LEVEL_NONE) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs core leveling for the system.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter.
+ * The possible modes are:
+ *    -0    CORE_LEVEL_LOWEST            Level to lowest common denominator
+ *    -1    CORE_LEVEL_TWO               Level to 2 cores
+ *    -2    CORE_LEVEL_POWER_OF_TWO      Level to 1,2,4 or 8
+ *    -3    CORE_LEVEL_NONE              Do no leveling
+ *    -4    CORE_LEVEL_COMPUTE_UNIT      Level cores to one core per compute unit
+ *
+ * @param[in]  EntryPoint        Timepoint designator.
+ * @param[in]  PlatformConfig    Contains the leveling mode parameter
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+AGESA_STATUS
+CoreLevelingAtEarly (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32    CoreNumPerComputeUnit;
+  UINT32    MinNumOfComputeUnit;
+  UINT32    EnabledComputeUnit;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    NumberOfSockets;
+  UINT32    NumberOfModules;
+  UINT32    MinCoreCountOnNode;
+  UINT32    MaxCoreCountOnNode;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    LeveledCores;
+  UINT32    RequestedCores;
+  UINT32    TotalEnabledCoresOnNode;
+  BOOLEAN   RegUpdated;
+  AP_MAIL_INFO ApMailboxInfo;
+  CORE_LEVELING_TYPE  CoreLevelMode;
+  CPU_CORE_LEVELING_FAMILY_SERVICES  *FamilySpecificServices;
+  WARM_RESET_REQUEST Request;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "CoreLevelingAtEarly\n  CoreLevelMode: %d\n", PlatformConfig->CoreLevelingMode);
+
+  MaxCoreCountOnNode = 0;
+  MinCoreCountOnNode = 0xFFFFFFFF;
+  LeveledCores = 0;
+  CoreNumPerComputeUnit = 1;
+  MinNumOfComputeUnit = 0xFF;
+
+  ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax);
+
+  // Get OEM IO core level mode
+  CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
+
+  // Get socket count
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1;
+
+  // Collect cpu core info
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      for (Module = 0; Module < NumberOfModules; Module++) {
+        if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+          // Get the highest and lowest core count in all nodes
+          TotalEnabledCoresOnNode = HighCore - LowCore + 1;
+          if (TotalEnabledCoresOnNode < MinCoreCountOnNode) {
+            MinCoreCountOnNode = TotalEnabledCoresOnNode;
+          }
+          if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) {
+            MaxCoreCountOnNode = TotalEnabledCoresOnNode;
+          }
+          EnabledComputeUnit = TotalEnabledCoresOnNode;
+          switch (GetComputeUnitMapping (StdHeader)) {
+          case AllCoresMapping:
+            // All cores are in their own compute unit.
+            break;
+          case EvenCoresMapping:
+            // Cores are paired in compute units.
+            CoreNumPerComputeUnit = 2;
+            EnabledComputeUnit = (TotalEnabledCoresOnNode / 2);
+            break;
+          default:
+            ASSERT (FALSE);
+          }
+          // Get minimum of compute unit.  This will either be the minimum number of cores (AllCoresMapping),
+          // or less (EvenCoresMapping).
+          if (EnabledComputeUnit < MinNumOfComputeUnit) {
+            MinNumOfComputeUnit = EnabledComputeUnit;
+          }
+          IDS_HDT_CONSOLE (CPU_TRACE, "  Socket %d Module %d MaxCoreCountOnNode %d MinCoreCountOnNode %d TotalEnabledCoresOnNode %d EnabledComputeUnit %d MinNumOfComputeUnit %d\n", \
+                                      Socket, Module, MaxCoreCountOnNode, MinCoreCountOnNode, TotalEnabledCoresOnNode, EnabledComputeUnit, MinNumOfComputeUnit);
+        }
+      }
+    }
+  }
+
+  // Get LeveledCores
+  switch (CoreLevelMode) {
+  case CORE_LEVEL_LOWEST:
+    if (MinCoreCountOnNode == MaxCoreCountOnNode) {
+      return (AGESA_SUCCESS);
+    }
+    LeveledCores = (MinCoreCountOnNode / CoreNumPerComputeUnit) * CoreNumPerComputeUnit;
+    break;
+  case CORE_LEVEL_TWO:
+    LeveledCores = 2 / NumberOfModules;
+    if (LeveledCores != 0) {
+      LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
+    } else {
+      return (AGESA_WARNING);
+    }
+    if ((LeveledCores * NumberOfModules) != 2) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      2, (LeveledCores * NumberOfModules), 0, 0, StdHeader
+      );
+    }
+    break;
+  case CORE_LEVEL_POWER_OF_TWO:
+    // Level to power of 2 (1, 2, 4, 8...)
+    LeveledCores = 1;
+    while (MinCoreCountOnNode >= (LeveledCores * 2)) {
+      LeveledCores = LeveledCores * 2;
+    }
+    break;
+  case CORE_LEVEL_COMPUTE_UNIT:
+    // Level cores to one core per compute unit, with additional reduction to level
+    // all processors to match the processor with the minimum number of cores.
+    if (CoreNumPerComputeUnit == 1) {
+      // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST.
+      if (MinCoreCountOnNode == MaxCoreCountOnNode) {
+        return (AGESA_SUCCESS);
+      }
+      LeveledCores = MinCoreCountOnNode;
+    } else {
+      // If there are more than one core per compute unit, level to the number of compute units.
+      LeveledCores = MinNumOfComputeUnit;
+    }
+    break;
+  case CORE_LEVEL_ONE:
+    LeveledCores = 1;
+    if (NumberOfModules > 1) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      1, NumberOfModules, 0, 0, StdHeader
+      );
+    }
+    break;
+  case CORE_LEVEL_THREE:
+  case CORE_LEVEL_FOUR:
+  case CORE_LEVEL_FIVE:
+  case CORE_LEVEL_SIX:
+  case CORE_LEVEL_SEVEN:
+  case CORE_LEVEL_EIGHT:
+  case CORE_LEVEL_NINE:
+  case CORE_LEVEL_TEN:
+  case CORE_LEVEL_ELEVEN:
+  case CORE_LEVEL_TWELVE:
+  case CORE_LEVEL_THIRTEEN:
+  case CORE_LEVEL_FOURTEEN:
+  case CORE_LEVEL_FIFTEEN:
+    // MCM processors can not have an odd number of cores. For an odd CORE_LEVEL_N, MCM processors will be
+    // leveled as though CORE_LEVEL_N+1 was chosen.
+    // Processors with compute units disable all cores in an entire compute unit at a time, or on an MCM processor,
+    // two compute units at a time. For example, on an SCM processor with two cores per compute unit, the effective
+    // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and
+    // CORE_LEVEL_EIGHT. The same example for an MCM processor with two cores per compute unit has effective
+    // explicit levels of CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_EIGHT, and CORE_LEVEL_TWELVE.
+    RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3;
+    LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules;
+    LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit;
+    LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
+    if (LeveledCores != 1) {
+      LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit;
+    }
+    if ((LeveledCores * NumberOfModules * CoreNumPerComputeUnit) != RequestedCores) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      RequestedCores, (LeveledCores * NumberOfModules * CoreNumPerComputeUnit), 0, 0, StdHeader
+      );
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+
+  // Set down core register
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+      if (FamilySpecificServices != NULL) {
+        for (Module = 0; Module < NumberOfModules; Module++) {
+          IDS_HDT_CONSOLE (CPU_TRACE, "  SetDownCoreRegister: Socket %d Module %d LeveledCores %d CoreLevelMode %d\n", Socket, Module, LeveledCores, CoreLevelMode);
+          RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader);
+          // If the down core register is updated, trigger a warm reset.
+          if (RegUpdated) {
+            GetWarmResetFlag (StdHeader, &Request);
+            Request.RequestBit = TRUE;
+            Request.StateBits = Request.PostStage - 1;
+            IDS_HDT_CONSOLE (CPU_TRACE, "  Request a warm reset.\n");
+            SetWarmResetFlag (StdHeader, &Request);
+          }
+        }
+      }
+    }
+  }
+
+  return (AGESA_SUCCESS);
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
+{
+  CoreLeveling,
+  (CPU_FEAT_AFTER_PM_INIT),
+  IsCoreLevelingEnabled,
+  CoreLevelingAtEarly
+};
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L      F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c
new file mode 100644
index 0000000000..9fb1c13a7a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c
@@ -0,0 +1,202 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Core performance boost feature support code.
+ *
+ * Contains code that declares the AGESA CPU CPB related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuCpb.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUCPB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should CPB be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               CPB is supported.
+ * @retval       FALSE              CPB cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCpbFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32              Socket;
+  BOOLEAN             IsEnabled;
+  CPB_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+
+  ASSERT (PlatformConfig->CpbMode < MaxCpbMode);
+
+  if (PlatformConfig->CpbMode == CpbModeAuto) {
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if (FamilyServices != NULL) {
+          if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
+            IsEnabled = TRUE;
+            break;
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable core performance boost
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeCpbFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32              Socket;
+  AGESA_STATUS        AgesaStatus;
+  AGESA_STATUS        CalledStatus;
+  CPB_FAMILY_SERVICES *FamilyServices;
+
+  AgesaStatus = AGESA_SUCCESS;
+  CalledStatus = AGESA_SUCCESS;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Boost is enabled\n");
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+      if (FamilyServices != NULL) {
+        if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
+          CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader);
+          if (CalledStatus > AgesaStatus) {
+            AgesaStatus = CalledStatus;
+          }
+        }
+      }
+    }
+  }
+
+  return AgesaStatus;
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb =
+{
+  CoreBoost,
+  (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_S3_LATE_RESTORE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsCpbFeatureEnabled,
+  InitializeCpbFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h
new file mode 100644
index 0000000000..b06bca4c2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Core Performance Boost Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU CPB related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_CPB_H_
+#define _CPU_CPB_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if CPB is supported.
+ *
+ * @param[in]    CpbServices        Core Performance Boost services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               CPB is supported.
+ * @retval       FALSE              CPB is not supported.
+ *
+ */
+typedef BOOLEAN F_CPB_IS_SUPPORTED (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable CPB.
+ *
+ * @param[in]    CpbServices        Core Performance Boost services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_CPB_INIT (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT64                 EntryPoint,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPB_INIT *PF_CPB_INIT;
+
+/**
+ * Provide the interface to the CPB Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPB_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_CPB_IS_SUPPORTED IsCpbSupported;                                   ///< Method: Family specific call to check if CPB is supported.
+  PF_CPB_INIT         EnableCpbOnSocket;                                ///< Method: Family specific call to enable CPB.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_CPB_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
new file mode 100644
index 0000000000..5a9de7c2d1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
@@ -0,0 +1,535 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CRAT, ACPI table related API functions.
+ *
+ * Contains code that Create the APCI CRAT Table after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FEATURE
+ * @e \$Revision: 64574 $   @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ***************************************************************************/
+
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate CRAT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "OptionCrat.h"
+#include "cpuCrat.h"
+#include "mfCrat.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuLateInit.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUCRAT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_CRAT_CONFIGURATION OptionCratConfiguration;  // global user config record
+extern CPU_FAMILY_SUPPORT_TABLE CratFamilyServiceTable;
+extern S_MAKE_CRAT_ENTRY MakeCratEntryTable[];
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiCratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   VOID                  **CratPtr
+  );
+
+AGESA_STATUS
+GetAcpiCratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   VOID                  **CratPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *  All of the DATA should be defined in _CODE segment.
+ *  Use ROMDATA to specify that it belongs to _CODE.
+ *----------------------------------------------------------------------------
+ */
+CONST UINT8 ROMDATA L2L3Associativity[] =
+{
+  0,
+  1,
+  2,
+  0,
+  4,
+  0,
+  8,
+  0,
+  16,
+  0,
+  32,
+  48,
+  64,
+  96,
+  128,
+  0xFF
+};
+
+STATIC CRAT_HEADER  ROMDATA CratHeaderStruct =
+{
+  {'C','R','A','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'A','G','E','S','A',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1,
+  0,
+  0,
+  {0, 0, 0, 0, 0, 0}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Component Resource Affinity Table
+ * i.e. CRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[out]     CratPtr           Point to Crat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+CreateAcpiCrat (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   VOID                  **CratPtr
+  )
+{
+  AGESA_TESTPOINT (Agtp6c , StdHeader);
+  return ((*(OptionCratConfiguration.CratFeature)) (StdHeader, CratPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the CRAT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *    @param[out]     CratPtr        Point to Crat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiCratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   VOID                  **CratPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Component Resource Affinity Table
+ * i.e. CRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[out]     CratPtr           Point to Crat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiCratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   VOID                  **CratPtr
+  )
+{
+  UINT8     i;
+  UINT8     *TableEnd;
+  CRAT_HEADER  *CratHeaderStructPtr;
+  ALLOCATE_HEAP_PARAMS AllocParams;
+
+  // Allocate a buffer
+  AllocParams.RequestedBufferSize = CRAT_MAX_LENGTH;
+  AllocParams.BufferHandle = AMD_CRAT_INFO_BUFFER_HANDLE;
+  AllocParams.Persist = HEAP_SYSTEM_MEM;
+
+  if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
+    return AGESA_ERROR;
+  }
+  *CratPtr = AllocParams.BufferPtr;
+
+
+  CratHeaderStructPtr = (CRAT_HEADER *) *CratPtr;
+  TableEnd = (UINT8 *) *CratPtr;
+
+  // Copy CratHeaderStruct -> data buffer
+  LibAmdMemCopy ((VOID *) CratHeaderStructPtr, (VOID *) &CratHeaderStruct, (UINTN) (sizeof (CRAT_HEADER)), StdHeader);
+
+  TableEnd += sizeof (CRAT_HEADER);
+
+  // Make all CRAT entries.
+  for (i = 0; MakeCratEntryTable[i].MakeCratEntry != NULL; i++) {
+    MakeCratEntryTable[i].MakeCratEntry (CratHeaderStructPtr, &TableEnd, StdHeader);
+
+  }
+
+  // Store size in table (current buffer offset - buffer start offset)
+  CratHeaderStructPtr->Length = (UINT32) (TableEnd - (UINT8 *) CratHeaderStructPtr);
+
+  //Update SSDT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CratHeaderStructPtr, StdHeader);
+  IDS_HDT_CONSOLE (CPU_TRACE, "  CRAT is created\n");
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *                            L O C A L    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add HSA Processing Unit entry.
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+VOID
+MakeHSAProcUnitEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     NodeNum;
+  UINT8     NodeCount;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    RegVal;
+  CRAT_HSA_PROCESSING_UNIT *EntryPtr;
+  AMD_APIC_PARAMS ApicParams;
+  PCI_ADDR  PciAddress;
+
+  // Get Node count
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, 0x60);
+  LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader);
+  NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1);
+
+  NodeNum = 0;
+  ApicParams.StdHeader = *StdHeader;
+  while (NodeNum < NodeCount) {
+    GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader);
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    ApicParams.Socket = (UINT8) Socket;
+    ApicParams.Core = 0;
+    AmdGetApicId (&ApicParams);
+    if (ApicParams.IsPresent) {
+      // Adding one CRAT entry for every node
+      EntryPtr = (CRAT_HSA_PROCESSING_UNIT *) AddOneCratEntry (CRAT_TYPE_HSA_PROC_UNIT, CratHeaderStructPtr, TableEnd, StdHeader);
+
+      EntryPtr->ProximityDomain = NodeNum;
+      EntryPtr->ProcessorIdLow = ApicParams.ApicAddress;
+      EntryPtr->CpuCoreCount = (UINT16) (HighCore - LowCore + 1);
+      EntryPtr->Flags.Enabled = 1;
+      EntryPtr->Flags.CpuPresent = 1;
+    }
+    /// @todo SimdCount SimdWidth IoCount
+    CratHeaderStructPtr->NumDomains++;
+    NodeNum++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add memory entry.
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+VOID
+MakeMemoryEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     EntryNum;
+  UINT8     NumOfMemAffinityInfoEntries;
+  UINT32    Width;
+  AGESA_STATUS  AgesaStatus;
+  CRAT_MEMORY *EntryPtr;
+  LOCATE_HEAP_PTR LocateHeapParams;
+  CRAT_MEMORY_AFFINITY_INFO_HEADER *MemAffinityInfoHeaderPtr;
+  CRAT_MEMORY_AFFINITY_INFO_ENTRY *MemAffinityInfoEntryPtr;
+
+  EntryNum = 0;
+
+  // Get the CRAT memory affinity info from heap
+  LocateHeapParams.BufferHandle = AMD_MEM_CRAT_INFO_BUFFER_HANDLE;
+  AgesaStatus = HeapLocateBuffer (&LocateHeapParams, StdHeader);
+  if (AgesaStatus != AGESA_SUCCESS) {
+    ASSERT (FALSE);
+  } else {
+    MemAffinityInfoHeaderPtr = (CRAT_MEMORY_AFFINITY_INFO_HEADER *) (LocateHeapParams.BufferPtr);
+    MemAffinityInfoHeaderPtr ++;
+    MemAffinityInfoEntryPtr  = (CRAT_MEMORY_AFFINITY_INFO_ENTRY *) MemAffinityInfoHeaderPtr;
+    MemAffinityInfoHeaderPtr --;
+
+    // Get the number of CRAT memory affinity entries
+    NumOfMemAffinityInfoEntries = MemAffinityInfoHeaderPtr->NumOfMemAffinityInfoEntries;
+    Width = MemAffinityInfoHeaderPtr->MemoryWidth;
+
+    // Create CRAT memory affinity entries
+    IDS_HDT_CONSOLE (MAIN_FLOW, "  CRAT memory affinity entries\n");
+    while (EntryNum < NumOfMemAffinityInfoEntries) {
+      // Add one CRAT memory entry
+      EntryPtr = (CRAT_MEMORY *) AddOneCratEntry (CRAT_TYPE_MEMORY, CratHeaderStructPtr, TableEnd, StdHeader);
+      EntryPtr->Flags.Enabled = 1;
+      EntryPtr->ProximityDomain = MemAffinityInfoEntryPtr->Domain;
+      EntryPtr->BaseAddressLow = MemAffinityInfoEntryPtr->BaseAddressLow;
+      EntryPtr->BaseAddressHigh = MemAffinityInfoEntryPtr->BaseAddressHigh;
+      EntryPtr->LengthLow = MemAffinityInfoEntryPtr->LengthLow;
+      EntryPtr->LengthHigh = MemAffinityInfoEntryPtr->LengthHigh;
+      EntryPtr->Width = Width;
+      IDS_HDT_CONSOLE (MAIN_FLOW, "    Entry #%d\n", EntryNum);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Type:              0x%08x\n", EntryPtr->Type);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Length:            0x%08x\n", EntryPtr->Length);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Flags:             %s %s %s\n", (EntryPtr->Flags.Enabled == 1) ? "Enabled" : "",
+                                                                         (EntryPtr->Flags.HotPluggable == 1) ? "EnHotPluggableabled" : "",
+                                                                         (EntryPtr->Flags.NonVolatile == 1) ? "NonVolatile" : ""
+                                                                         );
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Proximity Domain:  0x%08x\n", EntryPtr->ProximityDomain);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Base Address Low:  0x%08x\n", EntryPtr->BaseAddressLow);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Base Address High: 0x%08x\n", EntryPtr->BaseAddressHigh);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Length Low:        0x%08x\n", EntryPtr->LengthLow);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Length High:       0x%08x\n", EntryPtr->LengthHigh);
+      IDS_HDT_CONSOLE (MAIN_FLOW, "      Width:             0x%08x\n", EntryPtr->Width);
+      MemAffinityInfoEntryPtr ++;
+      EntryNum ++;
+    }
+    HeapDeallocateBuffer ((UINT32) AMD_MEM_CRAT_INFO_BUFFER_HANDLE, StdHeader);
+  }
+
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add cache entry.
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+VOID
+MakeCacheEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CRAT_FAMILY_SERVICES  *CratFamilyServices;
+
+  GetFeatureServicesOfSocket (&CratFamilyServiceTable, 0, (CONST VOID **)&CratFamilyServices, StdHeader);
+  CratFamilyServices->generateCratCacheEntry (CratHeaderStructPtr, TableEnd, StdHeader);
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add TLB entry.
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+VOID
+MakeTLBEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CRAT_FAMILY_SERVICES  *CratFamilyServices;
+
+  GetFeatureServicesOfSocket (&CratFamilyServiceTable, 0, (CONST VOID **)&CratFamilyServices, StdHeader);
+  CratFamilyServices->generateCratTLBEntry (CratHeaderStructPtr, TableEnd, StdHeader);
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add CRAT entry.
+ *
+ *    @param[in]      CratEntryType        CRAT entry type
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+UINT8 *
+AddOneCratEntry (
+  IN       CRAT_ENTRY_TYPE CratEntryType,
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *CurrentEntry;
+
+  CurrentEntry = *TableEnd;
+  CratHeaderStructPtr->TotalEntries++;
+  switch (CratEntryType) {
+  case CRAT_TYPE_HSA_PROC_UNIT:
+    *TableEnd += sizeof (CRAT_HSA_PROCESSING_UNIT);
+    ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH);
+    CratHeaderStructPtr->Length += sizeof (CRAT_HSA_PROCESSING_UNIT);
+    ((CRAT_HSA_PROCESSING_UNIT *) CurrentEntry)->Type = (UINT8) CratEntryType;
+    ((CRAT_HSA_PROCESSING_UNIT *) CurrentEntry)->Length = sizeof (CRAT_HSA_PROCESSING_UNIT);
+    break;
+  case CRAT_TYPE_MEMORY:
+    *TableEnd += sizeof (CRAT_MEMORY);
+    ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH);
+    CratHeaderStructPtr->Length += sizeof (CRAT_MEMORY);
+    ((CRAT_MEMORY *) CurrentEntry)->Type = (UINT8) CratEntryType;
+    ((CRAT_MEMORY *) CurrentEntry)->Length = sizeof (CRAT_MEMORY);
+    break;
+  case CRAT_TYPE_CACHE:
+    *TableEnd += sizeof (CRAT_CACHE);
+    ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH);
+    CratHeaderStructPtr->Length += sizeof (CRAT_CACHE);
+    ((CRAT_CACHE *) CurrentEntry)->Type = (UINT8) CratEntryType;
+    ((CRAT_CACHE *) CurrentEntry)->Length = sizeof (CRAT_CACHE);
+    break;
+  case CRAT_TYPE_TLB:
+    *TableEnd += sizeof (CRAT_TLB);
+    ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH);
+    CratHeaderStructPtr->Length += sizeof (CRAT_TLB);
+    ((CRAT_TLB *) CurrentEntry)->Type = (UINT8) CratEntryType;
+    ((CRAT_TLB *) CurrentEntry)->Length = sizeof (CRAT_TLB);
+    break;
+  case CRAT_TYPE_FPU:
+    *TableEnd += sizeof (CRAT_FPU);
+    ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH);
+    CratHeaderStructPtr->Length += sizeof (CRAT_FPU);
+    ((CRAT_FPU *) CurrentEntry)->Type = (UINT8) CratEntryType;
+    ((CRAT_FPU *) CurrentEntry)->Length = sizeof (CRAT_FPU);
+    break;
+  case CRAT_TYPE_IO:
+    *TableEnd += sizeof (CRAT_IO);
+    ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH);
+    CratHeaderStructPtr->Length += sizeof (CRAT_IO);
+    ((CRAT_IO *) CurrentEntry)->Type = (UINT8) CratEntryType;
+    ((CRAT_IO *) CurrentEntry)->Length = sizeof (CRAT_IO);
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+  return CurrentEntry;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.h
new file mode 100644
index 0000000000..a699694121
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.h
@@ -0,0 +1,112 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU CRAT
+ *
+ * Contains code that declares the AGESA CRAT related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63552 $   @e \$Date: 2011-12-26 19:46:05 -0600 (Mon, 26 Dec 2011) $
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_CRAT_H_
+#define _CPU_CRAT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Make CRAT entry
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ */
+typedef VOID F_MAKE_CRAT_ENTRY (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+/// Reference to a Method.
+typedef F_MAKE_CRAT_ENTRY *PF_MAKE_CRAT_ENTRY;
+
+/**
+ * A struct that contains function pointe
+ */
+typedef struct _S_MAKE_CRAT_ENTRY {
+  PF_MAKE_CRAT_ENTRY MakeCratEntry; ///< Function Pointer, which points to the function which makes CRAT entry.
+} S_MAKE_CRAT_ENTRY;
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_CRAT_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
new file mode 100644
index 0000000000..23fd79f1f9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
@@ -0,0 +1,867 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 64351 $   @e \$Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionDmi.h"
+#include "cpuLateInit.h"
+#include "cpuServices.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_DMI_CONFIGURATION    OptionDmiConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+CHAR8 ROMDATA str_ProcManufacturer[] = "Advanced Micro Devices, Inc.";
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+AdjustGranularity (
+  IN UINT32 *CacheSizePtr
+  );
+
+VOID
+STATIC
+IntToString (
+  IN OUT   CHAR8 *String,
+  IN       UINT8 *Integer,
+  IN       UINT8 SizeInByte
+);
+
+AGESA_STATUS
+GetDmiInfoStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  );
+
+AGESA_STATUS
+GetDmiInfoMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  );
+
+AGESA_STATUS
+ReleaseDmiBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+ReleaseDmiBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CreateDmiRecords
+ *
+ *  Description:
+ *     This function creates DMI/SMBios records pertinent to the processor
+ *     SMBIOS type 4, type 7, and type 40.
+ *
+ *  Parameters:
+ *    @param[in, out]  *StdHeader
+ *    @param[in, out]  **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+CreateDmiRecords (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader);
+  return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  GetDmiInfoStub
+ *
+ *  Description:
+ *     This is the default routine for use when the DMI option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *    @param[in, out]    **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+GetDmiInfoStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  GetDmiInfoMain
+ *
+ *  Description:
+ *     This is the common routine for getting Dmi type4 and type7 CPU related information.
+ *
+ *  Parameters:
+ *    @param[in, out]  *StdHeader
+ *    @param[in, out]  **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+GetDmiInfoMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  UINT8  Socket;
+  UINT8  Channel;
+  UINT8  Dimm;
+  UINT16 Index;
+  UINT16 DimmIndex;
+  UINT8 NumberOfDimm;
+  UINT32 MaxCapacity;
+  UINT64 MsrData;
+  UINT64 LocalMsrRegister;
+  UINT8 TypeDetail;
+  BOOLEAN FamilyNotFound;
+  AGESA_STATUS Flag;
+  AGESA_STATUS CalledStatus;
+  AP_EXE_PARAMS ApParams;
+  MEM_DMI_INFO *MemInfo;
+  DMI_T17_MEMORY_TYPE MemType;
+  DMI_INFO *DmiBufferPtr;
+  ALLOCATE_HEAP_PARAMS AllocateHeapParams;
+  LOCATE_HEAP_PTR LocateHeapParams;
+  CPU_LOGICAL_ID LogicalId;
+  PROC_FAMILY_TABLE *ProcData;
+  CPU_GET_MEM_INFO CpuGetMemInfo;
+
+  MsrData = 0;
+  Flag = TRUE;
+  ProcData = NULL;
+  MemInfo = NULL;
+  DmiBufferPtr = *DmiTable;
+  FamilyNotFound = TRUE;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) {
+    ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]);
+    if ((ProcData->ProcessorFamily & LogicalId.Family) != 0) {
+      FamilyNotFound = FALSE;
+      break;
+    }
+  }
+
+  if (FamilyNotFound) {
+    return AGESA_ERROR;
+  }
+
+  if (DmiBufferPtr == NULL) {
+    //
+    // Allocate a buffer by heap function
+    //
+    AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE;
+    AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO);
+    AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
+
+    if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+
+    DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr;
+    *DmiTable = DmiBufferPtr;
+  }
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  DMI is enabled\n");
+
+  // Fill with 0x00
+  LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader);
+
+  //
+  // Get CPU information
+  //
+
+  // Run GetType4Type7Info on all core0s.
+  ApParams.StdHeader = *StdHeader;
+  ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7;
+  ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr;
+  ApParams.RelatedBlockLength = sizeof (DMI_INFO);
+  CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader);
+  if (CalledStatus > Flag) {
+    Flag = CalledStatus;
+  }
+  CalledStatus = GetType4Type7Info (&ApParams);
+  if (CalledStatus > Flag) {
+    Flag = CalledStatus;
+  }
+
+  //------------------------------
+  // T Y P E 16 17 19 20
+  //------------------------------
+
+  LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    if (Flag < AGESA_ERROR) {
+      Flag = AGESA_ERROR;
+    }
+  } else {
+    NumberOfDimm = *((UINT8 *) (LocateHeapParams.BufferPtr));
+    TypeDetail = *((UINT8 *) (LocateHeapParams.BufferPtr) + 1);
+    MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6));
+    MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE));
+    // TYPE 16
+    DmiBufferPtr->T16.Location = 0x03;
+    DmiBufferPtr->T16.Use = 0x03;
+
+    // Gather memory information
+    ProcData->DmiGetMemInfo (&CpuGetMemInfo, StdHeader);
+
+    if (CpuGetMemInfo.EccCapable) {
+      DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16MultiBitEcc;
+    } else {
+      DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16NoneErrCorrection;
+    }
+
+    MaxCapacity = *((UINT32 *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2));
+    // For the total size >= 2TB case, we need leave MaximumCapacity (offset 07h) to 80000000h
+    // and fill the size in bytes into ExtMaxCapacity (offset 0Fh).
+    if (MaxCapacity < 0x200000) {
+      DmiBufferPtr->T16.MaximumCapacity = MaxCapacity << 10;
+      DmiBufferPtr->T16.ExtMaxCapacity = 0;
+    } else {
+      DmiBufferPtr->T16.MaximumCapacity = 0x80000000;
+      DmiBufferPtr->T16.ExtMaxCapacity = (UINT64) MaxCapacity << 20;
+    }
+
+    DmiBufferPtr->T16.NumberOfMemoryDevices = (UINT16) NumberOfDimm;
+
+    // TYPE 17
+    for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) {
+      Socket = (MemInfo + DimmIndex)->Socket;
+      Channel = (MemInfo + DimmIndex)->Channel;
+      Dimm = (MemInfo + DimmIndex)->Dimm;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' ';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0';
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' ';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0';
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType;
+      if ((MemInfo + DimmIndex)->MemorySize != 0) {
+        DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1;
+        if (TypeDetail == 1) {
+          DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Registered = 1;
+        } else if  (TypeDetail == 2) {
+          DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Unbuffered = 1;
+        } else {
+          DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Unknown = 1;
+        }
+      }
+      DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode;
+
+      IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2);
+
+      LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader);
+      DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].ExtSize = (MemInfo + DimmIndex)->ExtSize;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].ConfigSpeed = (MemInfo + DimmIndex)->ConfigSpeed;
+
+      if ((MemInfo + DimmIndex)->MemorySize != 0) {
+        //TYPE 20
+        DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr;
+        DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr;
+        DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = 0xFF;
+        DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF;
+        DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF;
+        DmiBufferPtr->T20[Socket][Channel][Dimm].ExtStartingAddr = (MemInfo + DimmIndex)->ExtStartingAddr;
+        DmiBufferPtr->T20[Socket][Channel][Dimm].ExtEndingAddr = (MemInfo + DimmIndex)->ExtEndingAddr;
+      }
+    }
+
+    // TYPE 19
+    DmiBufferPtr->T19.StartingAddr = 0;
+    DmiBufferPtr->T19.ExtStartingAddr = 0;
+    DmiBufferPtr->T19.ExtEndingAddr = 0;
+
+    // If Ending Address >= 0xFFFFFFFF, update Starting Address (offset 04h) & Ending Address (offset 08h) to 0xFFFFFFFF,
+    // and use the Extended Starting Address (offset 0Fh) & Extended Ending Address (offset 17h) instead.
+    LibAmdMsrRead (TOP_MEM2, &LocalMsrRegister, StdHeader);
+    if (LocalMsrRegister == 0) {
+      LibAmdMsrRead (TOP_MEM, &LocalMsrRegister, StdHeader);
+      DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10);
+    } else {
+      if ((LocalMsrRegister >> 10) >= ((UINT64) 0xFFFFFFFF)) {
+        DmiBufferPtr->T19.StartingAddr = 0xFFFFFFFFUL;
+        DmiBufferPtr->T19.EndingAddr = 0xFFFFFFFFUL;
+        DmiBufferPtr->T19.ExtEndingAddr = LocalMsrRegister;
+      } else {
+        DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10);
+      }
+    }
+
+    DmiBufferPtr->T19.PartitionWidth = 0xFF;
+  }
+  return (Flag);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  GetType4Type7Info
+ *
+ *  Description:
+ *    This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables.
+ *
+ *  Parameters:
+ *    @param[in] ApExeParams   Handle to config for library and services.
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *  Processing:
+ *
+ */
+AGESA_STATUS
+GetType4Type7Info (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT8  ByteIndexInUint64;
+  UINT16 Index;
+  UINT32 SocketNum;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  UINT64 MsrData;
+  DMI_INFO *DmiBufferPtr;
+  AGESA_STATUS IgnoredSts;
+  AGESA_STATUS Flag;
+  BOOLEAN FamilyNotFound;
+  CPUID_DATA CpuId;
+  CPU_TYPE_INFO CpuInfo;
+  PROC_FAMILY_TABLE   *ProcData;
+  CPU_LOGICAL_ID LogicalID;
+
+  Flag = TRUE;
+  DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock;
+  GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);
+
+  ProcData = NULL;
+  FamilyNotFound = TRUE;
+  for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) {
+    ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]);
+    if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) {
+      FamilyNotFound = FALSE;
+      break;
+    }
+  }
+
+  if (FamilyNotFound) {
+    return AGESA_ERROR;
+  }
+
+  ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader);
+
+  // ------------------------------
+  // T Y P E 4
+  // ------------------------------
+
+  IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+
+  // Type 4 Offset 0x05, Processor Type
+  DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR;
+
+  // Type 4 Offset 0x06, Processor Family
+  ProcData->DmiGetT4ProcFamily (&DmiBufferPtr->T4[SocketNum].T4ProcFamily, ProcData, &CpuInfo, &ApExeParams->StdHeader);
+
+  if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) {
+    Flag = AGESA_ERROR;
+  }
+
+  // Type4 Offset 0x08, Processor ID
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader);
+  DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg;
+  DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg;
+
+  // Type4 Offset 0x11, Voltage
+  DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader);
+
+  // Type4 Offset 0x12, External Clock
+  DmiBufferPtr->T4[SocketNum].T4ExternalClock = ProcData->DmiGetExtClock (&ApExeParams->StdHeader);
+
+  // Type4 Offset 0x14, Max Speed
+  DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader);
+
+  // Type4 Offset 0x16, Current Speed
+  DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed;
+
+  // Type4 Offset 0x18, Status
+  DmiBufferPtr->T4[SocketNum].T4Status = SOCKET_POPULATED | CPU_STATUS_ENABLED;
+
+  // Type4 Offset 0x19, Processor Upgrade
+  DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade;
+
+  // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count
+  DmiBufferPtr->T4[SocketNum].T4CoreCount   = CpuInfo.TotalCoreNumber + 1;
+  DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1;
+  DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1;
+
+  // Type4 Offset 0x26, Processor Characteristics
+  DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS;
+
+  // Type4 Offset 0x28, Processor Family 2
+  DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily;
+
+  // Type4 ProcVersion
+  for (Index = 0; Index <= 5; Index++) {
+    LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + Index), &MsrData, &ApExeParams->StdHeader);
+    for (ByteIndexInUint64 = 0; ByteIndexInUint64 <= 7; ByteIndexInUint64++) {
+      DmiBufferPtr->T4[SocketNum].T4ProcVersion[Index * 8 + ByteIndexInUint64] = (UINT8) (MsrData >> (8 * ByteIndexInUint64));
+    }
+  }
+
+  // Type4 Manufacturer
+  ASSERT (PROC_MANU_LENGTH >= sizeof (str_ProcManufacturer));
+  LibAmdMemCopy (DmiBufferPtr->T4[SocketNum].T4ProcManufacturer, str_ProcManufacturer, sizeof (str_ProcManufacturer), &ApExeParams->StdHeader);
+
+  //------------------------------
+  // T Y P E 7
+  //------------------------------
+
+  // Type7 Offset 0x05, Cache Configuration
+  DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1;
+  DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2;
+  DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3;
+
+  // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size
+
+  // Maximum L1 cache size
+  DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.CacheInfo.L1CacheSize);
+
+  // Installed L1 cache size
+  DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize;
+
+  // Maximum L2 cache size
+  DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.CacheInfo.L2CacheSize);
+
+  // Installed L2 cache size
+  DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize;
+
+  // Maximum L3 cache size
+  DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.CacheInfo.L3CacheSize);
+
+  // Installed L3 cache size
+  DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize;
+
+  // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type
+  DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE;
+
+  // Type7 Offset 0x0F, Cache Speed
+  DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1;
+  DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1;
+  DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1;
+
+  // Type7 Offset 0x10, Error Correction Type
+  DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+
+  // Type7 Offset 0x11, System Cache Type
+  DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE;
+
+  // Type7 Offset 0x12, Associativity
+  DmiBufferPtr->T7L1[SocketNum].T7Associativity = CpuInfo.CacheInfo.L1CacheAssoc;
+  DmiBufferPtr->T7L2[SocketNum].T7Associativity = CpuInfo.CacheInfo.L2CacheAssoc;
+  DmiBufferPtr->T7L3[SocketNum].T7Associativity = CpuInfo.CacheInfo.L3CacheAssoc;
+
+  return (Flag);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  DmiGetT4ProcFamilyFromBrandId
+ *
+ *  Description:
+ *     This is the common routine for getting Type 4 processor family information from brand ID
+ *
+ *  Parameters:
+ *    @param[in, out]    *T4ProcFamily           Pointer to type 4 processor family information
+ *    @param[in]         *CpuDmiProcFamilyTable  Pointer to DMI family special service
+ *    @param[in]         *CpuInfo                Pointer to CPU_TYPE_INFO struct
+ *    @param[in, out]    *StdHeader              Standard Head Pointer
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+VOID
+DmiGetT4ProcFamilyFromBrandId (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT16 Index;
+  *T4ProcFamily = P_UPGRADE_UNKNOWN;
+  if (CpuInfo->BrandId.Model != P_ENGINEERING_SAMPLE) {
+    for (Index = 0; Index < CpuDmiProcFamilyTable->LenBrandList; Index++) {
+      if ((CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == CpuInfo->PackageType) &&
+          (CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == CpuInfo->BrandId.Pg) &&
+          (CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == CpuInfo->TotalCoreNumber) &&
+          (CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == CpuInfo->BrandId.String1)) {
+        *T4ProcFamily = CpuDmiProcFamilyTable->DmiBrandList[Index].ValueSetToDmiTable;
+        break;
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  GetNameString
+ *
+ *  Description:
+ *    Get name string from MSR_C001_00[35:30]
+ *
+ *  Parameters:
+ *    @param[in, out]    *String       Pointer to name string
+ *    @param[in, out]    *StdHeader
+ *
+ */
+VOID
+GetNameString (
+  IN OUT   CHAR8 *String,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  i;
+  UINT8  StringIndex;
+  UINT8  MsrIndex;
+  UINT64 MsrData;
+
+  StringIndex = 0;
+  for (MsrIndex = 0; MsrIndex <= 5; MsrIndex++) {
+    LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + MsrIndex), &MsrData, StdHeader);
+    for (i = 0; i < 8; i++) {
+      String[StringIndex] = (CHAR8) (MsrData >> (8 * i));
+      StringIndex++;
+    }
+  }
+  String[StringIndex] = '\0';
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  IsSourceStrContainTargetStr
+ *
+ *  Description:
+ *    check if source string contains target string.
+ *
+ *  Parameters:
+ *    @param[in, out]    *SourceStr      Pointer to source CHAR array
+ *    @param[in, out]    *TargetStr      Pointer to target CHAR array
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval            TRUE             Target string is contained in the source string
+ *    @retval            FALSE            Target string is not contained in the source string
+ */
+BOOLEAN
+IsSourceStrContainTargetStr (
+  IN OUT   CHAR8 *SourceStr,
+  IN OUT   CONST CHAR8 *TargetStr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN IsContained;
+  UINT32  SourceStrIndex;
+  UINT32  TargetStrIndex;
+  CHAR8 TargetChar;
+
+  IsContained = FALSE;
+  if ((TargetStr != NULL) && (SourceStr != NULL)) {
+    for (SourceStrIndex = 0; SourceStr[SourceStrIndex] != '\0'; SourceStrIndex++) {
+      // Compare TrgString with SrcString from frist charactor to the '\0'
+      for (TargetStrIndex = 0; TargetStr[TargetStrIndex] != '\0'; TargetStrIndex++) {
+        if (TargetStr[TargetStrIndex] != SourceStr[SourceStrIndex + TargetStrIndex]) {
+          // if it's not match, try to check the upcase/lowcase
+          TargetChar = 0;
+          if (TargetStr[TargetStrIndex] >= 'a' && TargetStr[TargetStrIndex] <= 'z') {
+            TargetChar = TargetStr[TargetStrIndex] - ('a' - 'A');
+          } else if (TargetStr[TargetStrIndex] >= 'A' && TargetStr[TargetStrIndex] <= 'Z') {
+            TargetChar = TargetStr[TargetStrIndex] + ('a' - 'A');
+          }
+          // compare again
+          if (TargetChar != SourceStr[SourceStrIndex + TargetStrIndex]) {
+            break;
+          }
+        }
+      }
+
+      if ((TargetStr[TargetStrIndex] == '\0') && (TargetStrIndex != 0)) {
+        IsContained = TRUE;
+        break;
+      }
+    }
+  }
+  return IsContained;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  AdjustGranularity
+ *
+ *  Description:
+ *    If cache size is greater than or equal to 32M, then set granularity
+ *    to 64K. otherwise, set granularity to 1K
+ *
+ *  Parameters:
+ *    @param[in]    *CacheSizePtr
+ *
+ *    @retval       CacheSize
+ *
+ *  Processing:
+ *
+ */
+UINT16
+STATIC
+AdjustGranularity (
+  IN UINT32 *CacheSizePtr
+  )
+{
+  UINT16 CacheSize;
+
+  if (*CacheSizePtr >= 0x8000) {
+    CacheSize = (UINT16) (*CacheSizePtr / 64);
+    CacheSize |= 0x8000;
+  } else {
+    CacheSize = (UINT16) *CacheSizePtr;
+  }
+
+  return (CacheSize);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseDmiBufferStub
+ *
+ *  Description:
+ *     This is the default routine for use when the DMI option is NOT requested.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseDmiBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseDmiBuffer
+ *
+ *  Description:
+ *     Deallocate DMI buffer
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseDmiBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader);
+
+  return  AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  IntToString
+ *
+ *  Description:
+ *    Translate UINT array to CHAR array.
+ *
+ *  Parameters:
+ *    @param[in, out]    *String       Pointer to CHAR array
+ *    @param[in]         *Integer      Pointer to UINT array
+ *    @param[in]         SizeInByte    The size of UINT array
+ *
+ *  Processing:
+ *
+ */
+VOID
+STATIC
+IntToString (
+  IN OUT   CHAR8 *String,
+  IN       UINT8 *Integer,
+  IN       UINT8 SizeInByte
+  )
+{
+  UINT8 Index;
+
+  for (Index = 0; Index < SizeInByte; Index++) {
+    *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F;
+    *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F;
+  }
+  for (Index = 0; Index < (SizeInByte * 2); Index++) {
+    if (*(String + Index) >= 0x0A) {
+      *(String + Index) += 0x37;
+    } else {
+      *(String + Index) += 0x30;
+    }
+  }
+  *(String + SizeInByte * 2) = 0x0;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
new file mode 100644
index 0000000000..ffb33ab09b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -0,0 +1,292 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Feature Leveling Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuPostInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SaveFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+WriteFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+GetGlobalCpuFeatureListAddress (
+     OUT   UINT64            **Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  FeatureLeveling
+ *
+ *    CPU feature leveling. Set least common features set of all CPUs
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+FeatureLeveling (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 BscSocket;
+  UINT32 Ignored;
+  UINT32 BscCoreNum;
+  UINT32 Socket;
+  UINT32 Core;
+  UINT32 NumberOfSockets;
+  UINT32 NumberOfCores;
+  BOOLEAN *FirstTime;
+  BOOLEAN *NeedLeveling;
+  AGESA_STATUS IgnoredSts;
+  CPU_FEATURES_LIST *globalCpuFeatureList;
+  AP_TASK  TaskPtr;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);
+  FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));
+  NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
+
+  *FirstTime = TRUE;
+  *NeedLeveling = FALSE;
+
+  LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      if (Socket !=  BscSocket) {
+        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
+      }
+    }
+  }
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+
+  if (*NeedLeveling) {
+    TaskPtr.FuncAddress.PfApTaskI  = WriteFeatures;
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+        for (Core = 0; Core < NumberOfCores; Core++) {
+          if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+            ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+          }
+        }
+      }
+    }
+    ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+  }
+}
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L      F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  SaveFeatures
+ *
+ *    save least common features set of all CPUs
+ *
+ *    @param[in,out]  cpuFeatureListPtr  - Pointer to CPU Feature List.
+ *    @param[in,out]  StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+SaveFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  WriteFeatures
+ *
+ *    Write out least common features set of all CPUs
+ *
+ *    @param[in,out]  cpuFeatureListPtr  - Pointer to CPU Feature List.
+ *    @param[in,out]  StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+WriteFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  GetGlobalCpuFeatureListAddress
+ *
+ *   Determines the address in system DRAM that should be used for CPU feature leveling.
+ *
+ * @param[out] Address           Address to utilize
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *
+ */
+VOID
+STATIC
+GetGlobalCpuFeatureListAddress (
+     OUT   UINT64            **Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 AddressValue;
+
+  AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
+
+  *Address = (UINT64 *)(AddressValue);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.c
new file mode 100644
index 0000000000..1aee1c884f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.c
@@ -0,0 +1,225 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Implement general feature dispatcher.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - External General Services API
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[];
+
+/**
+ * Determines if a specific feature is or will be enabled.
+ *
+ * This code traverses the feature list until a match is
+ * found, then invokes the 'IsEnabled' function of the
+ * feature.
+ *
+ * @param[in]       Feature        Indicates the desired feature.
+ * @param[in]       PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in]       StdHeader      Standard AMD configuration parameters.
+ *
+ * @retval         TRUE      Feature is or will be enabled
+ * @retval         FALSE     Feature is not enabled
+ */
+BOOLEAN
+IsFeatureEnabled (
+  IN       DISPATCHABLE_CPU_FEATURES Feature,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINTN i;
+
+  ASSERT (Feature < MaxCpuFeature);
+
+  for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
+    if (SupportedCpuFeatureList[i]->Feature == Feature) {
+      return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader));
+    }
+  }
+  return FALSE;
+}
+
+/**
+ * Dispatches all features needing to perform some initialization at
+ * this time point.
+ *
+ * This routine searches the feature table for features needing to
+ * run at this time point, and invokes them.
+ *
+ * @param[in]      EntryPoint     Timepoint designator
+ * @param[in]      PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in]      StdHeader      Standard AMD configuration parameters.
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+DispatchCpuFeatures (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN i;
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledStatus;
+  AGESA_STATUS IgnoredStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
+      if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) {
+        IDS_SKIP_HOOK (IDS_CPU_FEAT, (CPU_FEATURE_DESCRIPTOR *) SupportedCpuFeatureList[i], StdHeader) {
+          if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) {
+            CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader);
+            if (CalledStatus > AgesaStatus) {
+              AgesaStatus = CalledStatus;
+            }
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
+
+/**
+ * This routine checks whether any non-coherent links in the system
+ * runs in HT1 mode; used to determine whether certain features
+ * should be disabled when this routine returns TRUE.
+ *
+ * @param[in]      StdHeader  Standard AMD configuration parameters.
+ *
+ * @retval         TRUE       One of the non-coherent links in the
+ *                            system runs in HT1 mode
+ * @retval         FALSE      None of the non-coherent links in the
+ *                            system is running in HT1 mode
+ */
+BOOLEAN
+IsNonCoherentHt1 (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINT32                Socket;
+  UINT32                Module;
+  PCI_ADDR              PciAddress;
+  AGESA_STATUS          AgesaStatus;
+  HT_HOST_FEATS         HtHostFeats;
+  CPU_SPECIFIC_SERVICES *CpuServices;
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&CpuServices, StdHeader);
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+          HtHostFeats.HtHostValue = 0;
+          Link = 0;
+          while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) {
+            // Return TRUE and exit routine once we find a non-coherent link in HT1
+            if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {
+              return TRUE;
+            }
+          }
+        }
+      }
+    }
+  }
+
+  return FALSE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h
new file mode 100644
index 0000000000..4c18809f33
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h
@@ -0,0 +1,297 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Generic CPU feature dispatcher and related services.
+ *
+ * Provides a feature processing engine to handle feature in a
+ * more generic way.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63692 $   @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FEATURES_H_
+#define _CPU_FEATURES_H_
+
+/**
+ * @page cpufeatimpl CPU Generic Feature Implementation Guide
+ *
+ * The CPU generic feature dispatcher provides services which can be used to implement a
+ * wide range of features in a manner that isolates calling code from knowledge about which
+ * families or features are supported in the current build.
+ *
+ * @par Determine if a New Feature is a Suitable Candidate
+ *
+ * A feature must meet the following requirements:
+ * <ul>
+ * <li> Any core in the system must be able to determine if the feature should be enabled or not.
+ *
+ *   <ul>
+ *   <li> MSRs cannot be read in multisocket systems in the 'IsEnabled' function.
+ *
+ *   <li> Cores cannot be launched in the 'IsEnabled' function.
+ *   </ul>
+ * </ul>
+ *
+ * @par Determine the Time Point at which the Feature Should be Enabled
+ *
+ * Factors to consider in making this determination:
+ *
+ * <ul>
+ * <li> Determine if there are any dependencies on other settings that require strict ordering.
+ *
+ * <li> Consider the state of the APs that you will need.
+ *
+ * <li> Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume.
+ * </ul>
+ *
+ * @par Implementing a new feature
+ *
+ * Perform the following steps to implement a new feature:
+ *
+ * <ul>
+ * <li> Create a unique equate for your time point, @b if you cannot use an existing time point.
+ *
+ * <li> Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature.
+ *
+ * <li> Add a new 'C' file to the Features folder for your feature.
+ *
+ *   <ul>
+ *   <li> The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize'
+ *
+ *   <li> The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure.
+ *   </ul>
+ *
+ * <li> Add a new 'H' file to the Features folder for your feature.
+ *
+ *   <ul>
+ *   <li> The 'H' file declares whatever family specific functions required by the feature.
+ *
+ *   <li> The 'H' file declares a structure containing all family specific functions.  For a reference
+ *        example, your feature API should have a set of conventions similar to cpu specific services,
+ *        @ref cpuimplfss.
+ *   </ul>
+ *
+ * <li> Create 'C' files in all applicable family folders.
+ *
+ *   <ul>
+ *   <li> Implement the required family specific functions.
+ *
+ *   <li> Instantiate a family specific services structure.
+ *   </ul>
+ *
+ * <li> Create \<feature name\>Install.h in the include folder.
+ *
+ *   <ul>
+ *   <li> Add logic to determine when your feature should be included in the build.
+ *
+ *   <li> If the feature should be included, define OPTION_\<feature name\> to the address of your
+ *        CPU_FEATURE_DESCRIPTOR instantiation.  If not, define OPTION_\<feature name\> to be blank.
+ *
+ *   <li> Create a family translation table pointing to all applicable instantiations of
+ *        family specific function structures.
+ *   </ul>
+ *
+ * <li> Modify OptionCpuFeaturesInstall.h in the include folder.
+ *
+ *   <ul>
+ *   <li> Include \<feature name\>Install.h.
+ *
+ *   <li> Add OPTION_\<feature name\> to the SupportedCpuFeatureList array.
+ *   </ul>
+ *
+ * <li> If a new time point was created, add a call to DispatchCpuFeatures at the desired location,
+ *      passing your new time point equate.
+ * </ul>
+ *
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FEAT_BEFORE_PM_INIT           (0x0000000000000001ull)
+#define CPU_FEAT_AFTER_PM_INIT            (0x0000000000000002ull)
+#define CPU_FEAT_AFTER_POST_MTRR_SYNC     (0x0000000000000004ull)
+#define CPU_FEAT_INIT_MID_END             (0x0000000000000008ull)
+#define CPU_FEAT_INIT_LATE_END            (0x0000000000000010ull)
+#define CPU_FEAT_S3_LATE_RESTORE_END      (0x0000000000000020ull)
+#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC   (0x0000000000000040ull)
+#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000080ull)
+#define CPU_FEAT_BEFORE_RELINQUISH_AP     (0x0000000000000100ull)
+/**
+ * Enumerated list of supported features.
+ */
+typedef enum {
+  HardwareC1e,               ///< Hardware C1e
+  L3Features,                ///< L3 dependent features
+  MsgBasedC1e,               ///< Message-based C1e
+  SoftwareC1e,               ///< Software C1e
+  CoreLeveling,              ///< Core Leveling
+  C6Cstate,                  ///< C6 C-state
+  IoCstate,                  ///< IO C-state
+  CacheFlushOnHalt,          ///< Cache Flush On Halt
+  PreserveAroundMailbox,     ///< Save-Restore the registers used for AP mailbox, to preserve their normal function.
+  CoreBoost,                 ///< Core Performance Boost (CPB)
+  LowPwrPstate,              ///< 500 MHz Low Power P-state
+  PstateHpcMode,             ///< High performance computing mode
+  CpuApm,                    ///< Application Power Management
+  CpuPsi,                    ///< Power Status Indicator
+  CpuHtc,                    ///< Hardware Thermal Control
+  MaxCpuFeature              ///< Not a valid value, used for verifying input
+} DISPATCHABLE_CPU_FEATURES;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Feature specific call to check if it is supported by the system.
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Feature is supported.
+ * @retval       FALSE              Feature is not supported.
+ *
+ */
+typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  The feature's main entry point for enablement.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE;
+
+
+/**
+ * Generic feature descriptor
+ */
+typedef struct {
+  DISPATCHABLE_CPU_FEATURES Feature;     ///< Enumerated feature ID
+  UINT64                    EntryPoint;  ///< Timepoint designator
+  PF_CPU_FEATURE_IS_ENABLED IsEnabled;   ///< Pointer to the function that checks if the feature is supported
+  PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature
+} CPU_FEATURE_DESCRIPTOR;
+
+/**
+ * Table descriptor for the installed features.
+ */
+typedef struct {
+  UINT8       NumberOfFeats;      ///< Number of valid entries in the table.
+  CPU_FEATURE_DESCRIPTOR *FeatureList;       ///< Pointer to the first element in the array.
+} CPU_FEATURE_TABLE;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+BOOLEAN
+IsFeatureEnabled (
+  IN       DISPATCHABLE_CPU_FEATURES Feature,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+DispatchCpuFeatures (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+IsNonCoherentHt1 (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif // _CPU_FEATURES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c
new file mode 100644
index 0000000000..6ad6cbd134
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c
@@ -0,0 +1,228 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Hardware Thermal Control (HTC) feature support code.
+ *
+ * Contains code that declares the AGESA CPU HTC related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63692 $   @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "cpuFeatures.h"
+#include "cpuHtc.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUHTC_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT32
+STATIC
+EnableHtcOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE           HtcFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION   OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should Hardware Thermal Control (HTC) be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HTC is supported.
+ * @retval       FALSE              HTC cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsHtcFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Socket;
+  BOOLEAN               IsEnabled;
+  HTC_FAMILY_SERVICES   *HtcFamilyServices;
+
+  IsEnabled = TRUE;
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&HtcFamilyServiceTable, Socket, (CONST VOID **)&HtcFamilyServices, StdHeader);
+      if ((HtcFamilyServices == NULL) || (!HtcFamilyServices->IsHtcSupported (HtcFamilyServices, Socket, PlatformConfig, StdHeader))) {
+        IsEnabled = FALSE;
+        break;
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware Thermal Control (HTC)
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeHtcFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK               TaskPtr;
+  AGESA_STATUS          AgesaStatus;
+  AMD_CPU_EARLY_PARAMS  CpuEarlyParams;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    HTC is being initialized\n");
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  TaskPtr.FuncAddress.PfApTaskIOC = EnableHtcOnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS | TASK_HAS_OUTPUT;
+  AgesaStatus = OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    HTC is enabled\n");
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  AP task to enable HTC
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+UINT32
+STATIC
+EnableHtcOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  AGESA_STATUS  CalledStatus;
+  HTC_FAMILY_SERVICES   *HtcFamilyServices;
+
+  CalledStatus = AGESA_UNSUPPORTED;
+  GetFeatureServicesOfCurrentCore (&HtcFamilyServiceTable, (CONST VOID **)&HtcFamilyServices, StdHeader);
+  if (HtcFamilyServices != NULL) {
+    CalledStatus = HtcFamilyServices->EnableHtcOnSocket (HtcFamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader);
+  }
+  return (UINT32) CalledStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc =
+{
+  CpuHtc,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsHtcFeatureEnabled,
+  InitializeHtcFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h
new file mode 100644
index 0000000000..e021f288fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h
@@ -0,0 +1,157 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Hardware Thermal Control (HTC) Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU HTC related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63692 $   @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_HTC_H_
+#define _CPU_HTC_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (HTC_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Hardware Thermal Control (HTC) is supported.
+ *
+ * @param[in]    HtcServices        HTC services.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HTC is supported.
+ * @retval       FALSE              HTC is not supported.
+ *
+ */
+typedef BOOLEAN F_HTC_IS_SUPPORTED (
+  IN       HTC_FAMILY_SERVICES    *HtcServices,
+  IN       UINT32                 Socket,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HTC_IS_SUPPORTED *PF_HTC_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable HTC.
+ *
+ * @param[in]    HtcServices        HTC services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_HTC_INIT (
+  IN       HTC_FAMILY_SERVICES    *HtcServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HTC_INIT *PF_HTC_INIT;
+
+/**
+ * Provide the interface to the HTC Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+/* typedef  */struct _HTC_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_HTC_IS_SUPPORTED IsHtcSupported;                                   ///< Method: Family specific call to check if HTC is supported.
+  PF_HTC_INIT         EnableHtcOnSocket;                                ///< Method: Family specific call to enable HTC.
+} /* HTC_FAMILY_SERVICES */;
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_HTC_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c
new file mode 100644
index 0000000000..e06944fde4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c
@@ -0,0 +1,207 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU HW C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Topology.h"
+#include "cpuFeatures.h"
+#include "cpuHwC1e.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should hardware C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ * @retval       FALSE              HW C1e cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsHwC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32           C1eData;
+  BOOLEAN          IsEnabled;
+  AP_MAILBOXES     ApMailboxes;
+  HW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+  IsEnabled = FALSE;
+  C1eData   = PlatformConfig->C1ePlatformData;
+  if ((PlatformConfig->C1eMode == C1eModeHardware) || (PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) ||
+      (PlatformConfig->C1eMode == C1eModeAuto)) {
+    // If C1eMode is Auto, C1ePlatformData3 specifies the P_LVL3 I/O port of the platform for HW C1e
+    if (PlatformConfig->C1eMode == C1eModeAuto) {
+      C1eData = PlatformConfig->C1ePlatformData3;
+    }
+    ASSERT (C1eData < 0x10000);
+    ASSERT (C1eData != 0);
+    if ((C1eData != 0) && (C1eData < 0xFFFE)) {
+      if (!IsNonCoherentHt1 (StdHeader)) {
+        if (GetNumberOfProcessors (StdHeader) == 1) {
+          GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+          if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
+            GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+            if (FamilyServices != NULL) {
+              IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader);
+            }
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeHwC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_STATUS CalledStatus;
+  AGESA_STATUS AgesaStatus;
+  HW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    HW C1e is enabled\n");
+
+  if (IsWarmReset (StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
+    if (CalledStatus > AgesaStatus) {
+      AgesaStatus = CalledStatus;
+    }
+  }
+  return AgesaStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e =
+{
+  HardwareC1e,
+  CPU_FEAT_AFTER_PM_INIT,
+  IsHwC1eFeatureEnabled,
+  InitializeHwC1eFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h
new file mode 100644
index 0000000000..4888e42cdd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU HW C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_HW_C1E_H_
+#define _CPU_HW_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if hardware C1e is supported.
+ *
+ * @param[in]    HwC1eServices      Hardware C1e services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ * @retval       FALSE              HW C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable hardware C1e.
+ *
+ * @param[in]    HwC1eServices      Hardware C1e services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_HW_C1E_INIT (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HW_C1E_INIT *PF_HW_C1E_INIT;
+
+/**
+ * Provide the interface to the hardware C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _HW_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported;                              ///< Method: Family specific call to check if hardware C1e is supported.
+  PF_HW_C1E_INIT InitializeHwC1e;                                       ///< Method: Family specific call to enable hardware C1e.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_HW_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c
new file mode 100644
index 0000000000..ea546041fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c
@@ -0,0 +1,234 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU IO Cstate function declarations.
+ *
+ * Contains code that declares the AGESA CPU IO Cstate related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFeatures.h"
+#include "cpuIoCstate.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+EnableIoCstateOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE    IoCstateFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should IO Cstate be enabled
+ *  If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               IO Cstate is supported.
+ * @retval       FALSE              IO Cstate cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsIoCstateFeatureSupported (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                    Socket;
+  BOOLEAN                   IsSupported;
+  IO_CSTATE_FAMILY_SERVICES *IoCstateServices;
+
+  IsSupported = FALSE;
+  if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) {
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (CONST VOID **)&IoCstateServices, StdHeader);
+        if (IoCstateServices != NULL) {
+          if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) {
+            IsSupported = TRUE;
+          } else {
+            // Stop checking remaining socket(s) once we find one that does not support IO Cstates
+            IsSupported = FALSE;
+            break;
+          }
+        } else {
+          // Exit the for loop if we found a socket that does not have the IO Cstates feature installed
+          IsSupported = FALSE;
+          break;
+        }
+      }
+    }
+  }
+  return IsSupported;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable IO Cstate feature
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeIoCstateFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    IO C-state is enabled\n");
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  TaskPtr.FuncAddress.PfApTaskIC = EnableIoCstateOnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable IO Cstate on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableIoCstateOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  IO_CSTATE_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeIoCstate (FamilyServices,
+                                     *((UINT64 *) EntryPoint),
+                                     &CpuEarlyParams->PlatformConfig,
+                                     StdHeader);
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate =
+{
+  IoCstate,
+  (CPU_FEAT_AFTER_PM_INIT),
+  IsIoCstateFeatureSupported,
+  InitializeIoCstateFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h
new file mode 100644
index 0000000000..09ad226ab0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h
@@ -0,0 +1,310 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU IO Cstate feature support code.
+ *
+ * Contains code that declares the AGESA CPU IO Cstate related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_IO_CSTATE_H_
+#define _CPU_IO_CSTATE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (IO_CSTATE_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+// Defines for ACPI C-State Objects
+#define   CST_NAME__            '_'
+#define   CST_NAME_C            'C'
+#define   CST_NAME_S            'S'
+#define   CST_NAME_T            'T'
+#define   CST_LENGTH            (CST_BODY_SIZE - 1)
+#define   CST_NUM_OF_ELEMENTS   0x02
+#define   CST_COUNT             0x01
+#define   CST_PKG_LENGTH        (CST_BODY_SIZE - 6) // CST_BODY_SIZE - PkgHeader - Count Buffer
+#define   CST_PKG_ELEMENTS      0x04
+#define   CST_SUBPKG_LENGTH     0x14
+#define   CST_SUBPKG_ELEMENTS   0x0A
+#define   CST_GDR_LENGTH        0x000C
+#define   CST_C1_TYPE           0x01
+#define   CST_C2_TYPE           0x02
+
+#define   CSD_NAME_D            'D'
+#define   CSD_COORD_TYPE_HW_ALL 0xFE
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/* AML code definition */
+
+/// CST Header
+typedef struct _CST_HEADER_STRUCT {
+  UINT8   NameOpcode;      ///< Name Opcode
+  UINT8   CstName_a__;     ///< String "_"
+  UINT8   CstName_a_C;     ///< String "C"
+  UINT8   CstName_a_S;     ///< String "S"
+  UINT8   CstName_a_T;     ///< String "T"
+} CST_HEADER_STRUCT;
+#define CST_HEADER_SIZE 5
+
+/// CST Body
+typedef struct _CST_BODY_STRUCT {
+  UINT8   PkgOpcode;       ///< Package Opcode
+  UINT8   PkgLength;       ///< Package Length
+  UINT8   PkgElements;     ///< Number of Elements
+  UINT8   BytePrefix;      ///< Byte Prefix Opcode
+  UINT8   Count;           ///< Number of Cstate info packages
+  UINT8   PkgOpcode2;      ///< Package Opcode
+  UINT8   PkgLength2;      ///< Package Length
+  UINT8   PkgElements2;    ///< Number of Elements
+  UINT8   BufferOpcode;    ///< Buffer Opcode
+  UINT8   BufferLength;    ///< Buffer Length
+  UINT8   BufferElements;  ///< Number of Elements
+  UINT8   BufferOpcode2;   ///< Buffer Opcode
+  UINT8   GdrOpcode;       ///< Generic Register Descriptor Opcode
+  UINT16  GdrLength;       ///< Descriptor Length
+  UINT8   AddrSpaceId;     ///< Address Space ID
+  UINT8   RegBitWidth;     ///< Register Bit Width
+  UINT8   RegBitOffset;    ///< Register Bit Offset
+  UINT8   AddressSize;     ///< Address Size
+  UINT64  RegisterAddr;    ///< Register Address
+  UINT16  EndTag;          ///< End Tag Descriptor
+  UINT8   BytePrefix2;     ///< Byte Prefix Opcode
+  UINT8   Type;            ///< Type
+  UINT8   WordPrefix;      ///< Word Prefix Opcode
+  UINT16  Latency;         ///< Latency
+  UINT8   DWordPrefix;     ///< Dword Prefix Opcode
+  UINT32  Power;           ///< Power
+} CST_BODY_STRUCT;
+#define CST_BODY_SIZE 39
+
+/// CSD Header
+typedef struct _CSD_HEADER_STRUCT {
+  UINT8   NameOpcode;     ///< Name Opcode
+  UINT8   CsdName_a__;    ///< String "_"
+  UINT8   CsdName_a_C;    ///< String "C"
+  UINT8   CsdName_a_S;    ///< String "S"
+  UINT8   CsdName_a_D;    ///< String "D"
+} CSD_HEADER_STRUCT;
+#define CSD_HEADER_SIZE 5
+
+/// CSD Body
+typedef struct _CSD_BODY_STRUCT {
+  UINT8   PkgOpcode;      ///< Package Opcode
+  UINT8   PkgLength;      ///< Package Length
+  UINT8   PkgElements;    ///< Number of Elements
+  UINT8   PkgOpcode2;     ///< Package Opcode
+  UINT8   PkgLength2;     ///< Package Length
+  UINT8   PkgElements2;   ///< Number of Elements
+  UINT8   BytePrefix;     ///< Byte Prefix Opcode
+  UINT8   NumEntries;     ///< Number of Entries
+  UINT8   BytePrefix2;    ///< Byte Prefix Opcode
+  UINT8   Revision;       ///< Revision
+  UINT8   DWordPrefix;    ///< DWord Prefix Opcode
+  UINT32  Domain;         ///< Dependency Domain Number
+  UINT8   DWordPrefix2;   ///< DWord Prefix Opcode
+  UINT32  CoordType;      ///< Coordination Type
+  UINT8   DWordPrefix3;   ///< Dword Prefix Opcode
+  UINT32  NumProcessors;  ///< Number of Processors in the Domain
+  UINT8   DWordPrefix4;   ///< Dword Prefix Opcode
+  UINT32  Index;          ///< Index of C-State entry for which dependency applies
+} CSD_BODY_STRUCT;
+#define CSD_BODY_SIZE 30
+
+/// input for create _CST
+typedef struct _ACPI_CST_CREATE_INPUT {
+  IO_CSTATE_FAMILY_SERVICES *IoCstateServices;    ///< Family service of IoCstate
+  UINT8                     LocalApicId;    ///< Local Apic for create _CST
+  VOID                      **PstateAcpiBufferPtr;  ///< buffer for fill _CST
+} ACPI_CST_CREATE_INPUT ;
+
+/// input for get _CST
+typedef struct _ACPI_CST_GET_INPUT {
+  IO_CSTATE_FAMILY_SERVICES *IoCstateServices;    ///< Family service of IoCstate
+  PLATFORM_CONFIGURATION    *PlatformConfig;  ///< platform config
+  UINT32                    *CStateAcpiObjSizePtr;  ///< Point to size of _CST
+} ACPI_CST_GET_INPUT ;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if IO Cstate is supported.
+ *
+ * @param[in]    IoCstateServices   IO Cstate services.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               IO Cstate is supported.
+ * @retval       FALSE              IO Cstate is not supported.
+ *
+ */
+typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT32                    Socket,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable IO Cstate.
+ *
+ * @param[in]    IoCstateServices   IO Cstate services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_IO_CSTATE_INIT (
+  IN       IO_CSTATE_FAMILY_SERVICES      *IoCstateServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to return the size of ACPI C-State Objects
+ *
+ * @param[in]    IoCstateServices   IO Cstate services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       Size of ACPI C-State Objects
+ *
+ */
+typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
+  IN       IO_CSTATE_FAMILY_SERVICES   *IoCstateServices,
+  IN       PLATFORM_CONFIGURATION      *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to create ACPI C-State Objects
+ *
+ * @param[in]      IoCstateServices      IO Cstate services.
+ * @param[in]      LocalApicId           Local Apic Id
+ * @param[in, out] PstateAcpiBufferPtr   Pointer to Pstate data buffer
+ * @param[in]      StdHeader             Config Handle for library, services.
+ *
+ */
+typedef VOID F_IO_CSTATE_CREATE_CST (
+  IN       IO_CSTATE_FAMILY_SERVICES   *IoCstateServices,
+  IN       UINT8                       LocalApicId,
+  IN OUT   VOID                        **PstateAcpiBufferPtr,
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check whether CSD object should be created.
+ *
+ * @param[in]      IoCstateServices      IO Cstate services.
+ * @param[in]      StdHeader             Config Handle for library, services.
+ *
+ * @retval         TRUE                  CSD Object should be created.
+ * @retval         FALSE                 CSD Object should not be created.
+ *
+ */
+typedef BOOLEAN F_IO_CSTATE_IS_CSD_GENERATED (
+  IN       IO_CSTATE_FAMILY_SERVICES   *IoCstateServices,
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+/// Reference to a Method
+typedef F_IO_CSTATE_IS_SUPPORTED     *PF_IO_CSTATE_IS_SUPPORTED;
+typedef F_IO_CSTATE_INIT             *PF_IO_CSTATE_INIT;
+typedef F_IO_CSTATE_GET_CST_SIZE     *PF_IO_CSTATE_GET_CST_SIZE;
+typedef F_IO_CSTATE_CREATE_CST       *PF_IO_CSTATE_CREATE_CST;
+typedef F_IO_CSTATE_IS_CSD_GENERATED *PF_IO_CSTATE_IS_CSD_GENERATED;
+
+/**
+ * Provide the interface to the IO Cstate Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _IO_CSTATE_FAMILY_SERVICES {
+  UINT16          Revision;                                  ///< Interface version
+  // Public Methods.
+  PF_IO_CSTATE_IS_SUPPORTED     IsIoCstateSupported;         ///< Method: Family specific call to check if IO Cstate is supported.
+  PF_IO_CSTATE_INIT             InitializeIoCstate;          ///< Method: Family specific call to enable IO Cstate
+  PF_IO_CSTATE_GET_CST_SIZE     GetAcpiCstObj;               ///< Method: Family specific call to return the size of ACPI CST objects.
+  PF_IO_CSTATE_CREATE_CST       CreateAcpiCstObj;            ///< Method: Family specific call to create ACPI CST object
+  PF_IO_CSTATE_IS_CSD_GENERATED IsCsdObjGenerated;           ///< Method: Family specific call to check whether CSD Object should be created.
+};
+
+#endif  // _CPU_IO_CSTATE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c
new file mode 100644
index 0000000000..7f680ae0b9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c
@@ -0,0 +1,376 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU L3 Features Initialization functions.
+ *
+ * Contains code for initializing L3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "cpuL3Features.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should L3 features be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               L3 Features are supported
+ * @retval       FALSE              L3 Features are not supported
+ *
+ */
+BOOLEAN
+STATIC
+IsL3FeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  UINT32           Socket;
+  L3_FEATURE_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->PlatformProfile.UseHtAssist ||
+      PlatformConfig->PlatformProfile.UseAtmMode) {
+    IsEnabled = TRUE;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if ((FamilyServices == NULL) || !FamilyServices->IsL3FeatureSupported (FamilyServices, Socket, StdHeader)) {
+          IsEnabled = FALSE;
+          break;
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable L3 dependent features.
+ *
+ * L3 features initialization requires the following series of steps.
+ *  1. Disable L3 and DRAM scrubbers on all nodes
+ *  2. Wait 40us for outstanding scrub results to complete
+ *  3. Disable all cache activity in the system
+ *  4. Issue WBINVD on all active cores
+ *  5. Initialize Probe Filter, if supported
+ *  6. Initialize ATM Mode, if supported
+ *  7. Enable all cache activity in the system
+ *  8. Restore L3 and DRAM scrubber register values
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeL3Feature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                      CpuCount;
+  UINT32                      Socket;
+  BOOLEAN                     HtAssistEnabled;
+  BOOLEAN                     AtmModeEnabled;
+  AGESA_STATUS                AgesaStatus;
+  AP_MAILBOXES                ApMailboxes;
+  AP_EXE_PARAMS               ApParams;
+  UINT32                      Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE];
+  L3_FEATURE_FAMILY_SERVICES  *FamilyServices[MAX_SOCKETS_SUPPORTED];
+
+  AgesaStatus     = AGESA_SUCCESS;
+  HtAssistEnabled = TRUE;
+  AtmModeEnabled  = TRUE;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Enabling L3 dependent features\n");
+
+  // There are many family service call outs.  Initialize the family service array while
+  // cache is still enabled.
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices[Socket], StdHeader);
+    } else {
+      FamilyServices[Socket] = NULL;
+    }
+  }
+
+  if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) {
+    // Check for optimal settings
+    GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+    CpuCount = GetNumberOfProcessors (StdHeader);
+    if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) ||
+        ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) {
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        // Only check for non-optimal HT Assist setting is if's supported.
+        if ((FamilyServices[Socket] != NULL) &&
+            (FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader))) {
+          if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) {
+            // Non-optimal settings.  Log an event.
+            AgesaStatus = AGESA_WARNING;
+            PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader);
+            break;
+          }
+        }
+      }
+    }
+  } else {
+    // Disable the scrubbers.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
+
+        // If any node in the system does not support Probe Filter, disable it on the system
+        if (!FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) {
+          HtAssistEnabled = FALSE;
+        }
+        // If any node in the system does not support ATM mode, disable it on the system
+        if (!FamilyServices[Socket]->IsAtmModeSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) {
+          AtmModeEnabled = FALSE;
+        }
+      }
+    }
+
+    // Wait for 40us
+    WaitMicroseconds ((UINT32) 40, StdHeader);
+
+    // Run DisableAllCaches on AP cores.
+    ApParams.StdHeader = *StdHeader;
+    ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE;
+    ApParams.RelatedDataBlock = (VOID *) &HtAssistEnabled;
+    ApParams.RelatedBlockLength = sizeof (BOOLEAN);
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+
+    // Run DisableAllCaches on core 0.
+    DisableAllCaches (&ApParams);
+
+    // Family hook before initialization.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Activate Probe Filter & ATM mode.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        if (HtAssistEnabled) {
+          FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader);
+        }
+        if (AtmModeEnabled) {
+          FamilyServices[Socket]->AtmModeInit (FamilyServices[Socket], Socket, StdHeader);
+        }
+      }
+    }
+
+    // Family hook after initialization.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Run EnableAllCaches on core 0.
+    EnableAllCaches (&ApParams);
+
+    // Run EnableAllCaches on every core.
+    ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE;
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+
+    // Restore the scrubbers.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
+      }
+    }
+  }
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Disable all the caches on current core.
+ *
+ * @param[in] ApExeParams   Handle to config for library and services.
+ *
+ * @retval    AGESA_SUCCESS  Always succeeds.
+ *
+ */
+AGESA_STATUS
+DisableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT32   CR0Data;
+  L3_FEATURE_FAMILY_SERVICES  *FamilyServices;
+
+  // Disable cache through CR0.
+  LibAmdReadCpuReg (0, &CR0Data);
+  CR0Data |= (0x60000000);
+  LibAmdWriteCpuReg (0, CR0Data);
+
+  // Execute wbinvd
+  LibAmdWriteBackInvalidateCache ();
+
+  GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader);
+
+  FamilyServices->HookDisableCache (FamilyServices, *(BOOLEAN *) ApExeParams->RelatedDataBlock, &ApExeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Enable all the caches on current core.
+ *
+ * @param[in] ApExeParams    Handle to config for library and services.
+ *
+ * @retval    AGESA_SUCCESS  Always succeeds.
+ *
+ */
+AGESA_STATUS
+EnableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT32   CR0Data;
+  L3_FEATURE_FAMILY_SERVICES  *FamilyServices;
+
+  // Enable cache through CR0.
+  LibAmdReadCpuReg (0, &CR0Data);
+  CR0Data &= ~(0x60000000);
+  LibAmdWriteCpuReg (0, CR0Data);
+
+  GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader);
+
+  FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features =
+{
+  L3Features,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END),
+  IsL3FeatureEnabled,
+  InitializeL3Feature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h
new file mode 100644
index 0000000000..e0290a24a9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h
@@ -0,0 +1,385 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU L3 Features Initialization functions.
+ *
+ * Contains code that declares the AGESA CPU L3 dependent feature related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_L3_FEATURES_H_
+#define _CPU_L3_FEATIRES_H_
+
+#include "Filecode.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define AP_LATE_TASK_DISABLE_CACHE (0x00000000ul | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE)
+#define AP_LATE_TASK_ENABLE_CACHE  (0x00010000ul | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE)
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if L3 Features are supported.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               L3 dependent features are supported
+ * @retval       FALSE              L3 dependent features are not supported
+ *
+ */
+typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific hook before L3 features are initialized.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_L3_FEATURE_BEFORE_INIT (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    HtAssistEnabled     Indicates whether Ht Assist is enabled.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_L3_FEATURE_DISABLE_CACHE (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       BOOLEAN HtAssistEnabled,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef VOID F_L3_FEATURE_ENABLE_CACHE (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to Initialize L3 Features
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to enable.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_L3_FEATURE_INIT (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific hook after L3 Features are initialized.
+ *
+ * @param[in]    L3FeatureServices   L3 Features family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_L3_FEATURE_AFTER_INIT (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to save the L3 scrubber.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to restore the L3 scrubber.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Contains L3 scrubber settings to restore.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if HT Assist is supported.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist is not supported.
+ *
+ */
+typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to Initialize HT Assist
+ *
+ * @param[in]    L3FeatureServices   L3 Features family services.
+ * @param[in]    Socket              Processor socket to enable.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_INIT (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to provide non_optimal HT Assist support
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       TRUE                The system may be running with non-optimal settings.
+ * @return       FALSE               The system may is running optimally.
+ *
+ */
+typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if ATM Mode is supported.
+ *
+ * @param[in]    L3FeatureServices   L3 Features family services.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               ATM Mode is supported.
+ * @retval       FALSE              ATM Mode is not supported.
+ *
+ */
+typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to Initialize ATM mode
+ *
+ * @param[in]    L3FeatureServices   L3 Features family services.
+ * @param[in]    Socket              Processor socket to enable.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_ATM_MODE_INIT (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT;
+
+/**
+ * Provide the interface to the L3 dependent features Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _L3_FEATURE_FAMILY_SERVICES {
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_L3_FEATURE_IS_SUPPORTED IsL3FeatureSupported;      ///< Method: Check if L3 dependent features are supported.
+  PF_L3_FEATURE_GET_L3_SCRUB_CTRL GetL3ScrubCtrl;       ///< Method: Save/disable the L3 scrubber.
+  PF_L3_FEATURE_SET_L3_SCRUB_CTRL SetL3ScrubCtrl;       ///< Method: Restore the L3 scrubber.
+  PF_L3_FEATURE_BEFORE_INIT HookBeforeInit;             ///< Method: Hook before enabling L3 dependent features.
+  PF_L3_FEATURE_AFTER_INIT HookAfterInit;               ///< Method: Hook after enabling L3 dependent features.
+  PF_L3_FEATURE_DISABLE_CACHE HookDisableCache;         ///< Method: Core hook just before disabling cache.
+  PF_L3_FEATURE_ENABLE_CACHE HookEnableCache;           ///< Method: Core hook just after enabling cache.
+  PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported;        ///< Method: Check if HT Assist is supported.
+  PF_HT_ASSIST_INIT HtAssistInit;                       ///< Method: Enable HT Assist.
+  PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig;        ///< Method: Check if HT Assist is running optimally.
+  PF_ATM_MODE_IS_SUPPORTED IsAtmModeSupported;          ///< Method: Check if ATM Mode is supported.
+  PF_ATM_MODE_INIT AtmModeInit;                         ///< Method: Enable ATM Mode.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+DisableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+AGESA_STATUS
+EnableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+#endif  // _CPU_L3_FEATURES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c
new file mode 100644
index 0000000000..c70a448583
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c
@@ -0,0 +1,309 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU create low power P-state for PROCHOT_L throttling support code.
+ *
+ * Contains code that declares the AGESA CPU low power P-state related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63523 $   @e \$Date: 2011-12-25 20:31:15 -0600 (Sun, 25 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFeatures.h"
+#include "cpuLowPwrPstate.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableLowPwrPstateOnSocket (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ProgramHtcPstateLimit (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should Low Power P-state be enabled
+ *  If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Low Power P-state is supported.
+ * @retval       FALSE              Low Power P-state cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsLowPwrPstateFeatureSupported (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32              Socket;
+  BOOLEAN             IsSupported;
+  LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;
+
+  IsSupported = FALSE;
+  if (PlatformConfig->LowPowerPstateForProcHot == LOW_POWER_PSTATE_FOR_PROCHOT_AUTO) {
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if (FamilyServices != NULL) {
+          if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
+            IsSupported = TRUE;
+          } else {
+            IsSupported = FALSE;
+            break;
+          }
+        } else {
+          IsSupported = FALSE;
+          break;
+        }
+      }
+    }
+  }
+  IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader);
+  return IsSupported;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable low power P-state
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeLowPwrPstateFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       BscSocket;
+  UINT32       Ignored;
+  UINT32       BscCoreNum;
+  UINT32       Core;
+  UINT32       Socket;
+  UINT32       NumberOfSockets;
+  UINT32       NumberOfCores;
+  AP_TASK      TaskPtr;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  if (!IsWarmReset (StdHeader)) {
+    IDS_HDT_CONSOLE (CPU_TRACE, "    Low pwr P-state is enabled\n");
+
+    TaskPtr.FuncAddress.PfApTaskI = EnableLowPwrPstateOnSocket;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = PlatformConfig;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+        for (Core = 0; Core < NumberOfCores; Core++) {
+          if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+            ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+          }
+        }
+      }
+    }
+
+    EnableLowPwrPstateOnSocket (PlatformConfig, StdHeader);
+  } else {
+    TaskPtr.FuncAddress.PfApTaskI = ProgramHtcPstateLimit;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = PlatformConfig;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        if (Socket != BscSocket) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader);
+        }
+      }
+    }
+
+    ProgramHtcPstateLimit (PlatformConfig, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  All APs task to enable low power P-state
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+EnableLowPwrPstateOnSocket (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->EnableLowPwrPstate (FamilyServices,
+                                      PlatformConfig,
+                                      StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable low power P-state
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+ProgramHtcPstateLimit (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32   OrMask;
+  UINT32   HtcCtrl;
+  UINT32   CPTC2;
+  PCI_ADDR PciAddress;
+
+  OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+  PciAddress.Address.Function = FUNC_3;
+
+  PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &CPTC2, StdHeader);   // F3xDC[10:8] HwPstateMaxVal
+  OrMask = CPTC2 & 0x700;
+  OrMask = OrMask << 20;
+
+  PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &HtcCtrl, StdHeader); // F3x64[30:28] HtcPstateLimit
+  // F3x64[30:28] HtcPstateLimit = F3xDC[10:8] HwPstateMaxVal
+  HtcCtrl = (HtcCtrl & 0x8FFFFFFF) | OrMask;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &HtcCtrl, StdHeader);
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate =
+{
+  LowPwrPstate,
+  (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsLowPwrPstateFeatureSupported,
+  InitializeLowPwrPstateFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h
new file mode 100644
index 0000000000..77a3dd44ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h
@@ -0,0 +1,156 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU create low power P-state for PROCHOT_L throttling Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU low power P-state related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_LOW_PWR_PSTATE_H_
+#define _CPU_LOW_PWR_PSTATE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Low Power P-state is supported.
+ *
+ * @param[in]    LowPwrPstateService Low Power P-state services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Low Power P-state is supported.
+ * @retval       FALSE              Low Power P-state is not supported.
+ *
+ */
+typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED (
+  IN       LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable Low Power P-state
+ *
+ * @param[in]    LowPwrPstateService Low Power P-state services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_LOW_PWR_PSTATE_INIT (
+  IN       LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_LOW_PWR_PSTATE_INIT *PF_LOW_PWR_PSTATE_INIT;
+
+/**
+ * Provide the interface to the Low Power P-state Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _LOW_PWR_PSTATE_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_LOW_PWR_PSTATE_IS_SUPPORTED IsLowPwrPstateSupported;         ///< Method: Family specific call to check if Low Power P-state is supported.
+  PF_LOW_PWR_PSTATE_INIT         EnableLowPwrPstate;              ///< Method: Family specific call to enable Low Power P-state.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_LOW_PWR_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c
new file mode 100644
index 0000000000..0b7c2725a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -0,0 +1,238 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Message-based C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuMsgBasedC1e.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableMsgC1eOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should message-based C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Message-based C1e is supported.
+ * @retval       FALSE              Message-based C1e cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsMsgBasedC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  UINT32           Socket;
+  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+
+  IsEnabled = FALSE;
+  if ((PlatformConfig->C1eMode == C1eModeMsgBased) || (PlatformConfig->C1eMode == C1eModeAuto)) {
+    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
+    ASSERT (PlatformConfig->C1ePlatformData != 0);
+    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
+      IsEnabled = TRUE;
+      if (IsNonCoherentHt1 (StdHeader)) {
+        IsEnabled = FALSE;
+      } else {
+        for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+          if (IsProcessorPresent (Socket, StdHeader)) {
+            GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+            if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {
+              IsEnabled = FALSE;
+              break;
+            }
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Message-based C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeMsgBasedC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK      TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    MT C1e is enabled\n");
+
+  if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) {
+    CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+    TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable message-based C1e on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableMsgC1eOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeMsgBasedC1e (FamilyServices,
+                                         *((UINT64 *) EntryPoint),
+                                         &CpuEarlyParams->PlatformConfig,
+                                         StdHeader);
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e =
+{
+  MsgBasedC1e,
+  (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsMsgBasedC1eFeatureEnabled,
+  InitializeMsgBasedC1eFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h
new file mode 100644
index 0000000000..40128fad32
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -0,0 +1,154 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Message-based C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_MSG_BASED_C1E_H_
+#define _CPU_MSG_BASED_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if message-based C1e is supported.
+ *
+ * @param[in]    MsgBasedC1eServices Contains the runtime modifiable feature input data.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               Message-based C1e is supported.
+ * @retval       FALSE              Message-based C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable hardware C1e.
+ *
+ * @param[in]    MsgBasedC1eServices Hardware C1e services.
+ * @param[in]    EntryPoint          Timepoint designator.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_MSG_BASED_C1E_INIT (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT;
+
+/**
+ * Provide the interface to the hardware C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _MSG_BASED_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported;                 ///< Method: Family specific call to check if hardware C1e is supported.
+  PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e;                          ///< Method: Family specific call to enable hardware C1e.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_MSG_BASED_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c
new file mode 100644
index 0000000000..24c907e706
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c
@@ -0,0 +1,240 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Power Status Indicator (PSI) feature support code.
+ *
+ * Contains code that declares the AGESA CPU PSI related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "cpuFeatures.h"
+#include "cpuPsi.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUPSI_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT32
+STATIC
+EnablePsiOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE           PsiFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION   OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should Power Status Indicator (PSI) be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSI is supported.
+ * @retval       FALSE              PSI cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsPsiFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Socket;
+  BOOLEAN               IsEnabled;
+  PSI_FAMILY_SERVICES   *PsiFamilyServices;
+  UINT32                VrmType;
+
+  IsEnabled = FALSE;
+
+  for (VrmType = 0; VrmType < MaxVrmType; VrmType++) {
+    if (PlatformConfig->VrmProperties[VrmType].LowPowerThreshold != 0) {
+      IsEnabled = TRUE;
+      break;
+    }
+  }
+
+  if (!IsEnabled) {
+    return FALSE;
+  }
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&PsiFamilyServiceTable, Socket, (CONST VOID **)&PsiFamilyServices, StdHeader);
+      if ((PsiFamilyServices == NULL) || (!PsiFamilyServices->IsPsiSupported (PsiFamilyServices, Socket, PlatformConfig, StdHeader))) {
+        IsEnabled = FALSE;
+        break;
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Power Status Indicator (PSI)
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializePsiFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK               TaskPtr;
+  AGESA_STATUS          AgesaStatus;
+  AMD_CPU_EARLY_PARAMS  CpuEarlyParams;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    PSI mode is being initialized\n");
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  TaskPtr.FuncAddress.PfApTaskIOC = EnablePsiOnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS | TASK_HAS_OUTPUT;
+  AgesaStatus = OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    PSI mode is enabled\n");
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  AP task to enable PSI
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+UINT32
+STATIC
+EnablePsiOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  AGESA_STATUS  CalledStatus;
+  PSI_FAMILY_SERVICES   *PsiFamilyServices;
+
+  CalledStatus = AGESA_UNSUPPORTED;
+  GetFeatureServicesOfCurrentCore (&PsiFamilyServiceTable, (CONST VOID **)&PsiFamilyServices, StdHeader);
+  if (PsiFamilyServices != NULL) {
+    CalledStatus = PsiFamilyServices->EnablePsiOnSocket (PsiFamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader);
+  }
+  return (UINT32) CalledStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi =
+{
+  CpuPsi,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsPsiFeatureEnabled,
+  InitializePsiFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h
new file mode 100644
index 0000000000..ca94466a2c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h
@@ -0,0 +1,157 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Power Status Indicator (PSI) Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU PSI related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_PSI_H_
+#define _CPU_PSI_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (PSI_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Power Status Indicator (PSI) is supported.
+ *
+ * @param[in]    PsiServices        PSI services.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSI is supported.
+ * @retval       FALSE              PSI is not supported.
+ *
+ */
+typedef BOOLEAN F_PSI_IS_SUPPORTED (
+  IN       PSI_FAMILY_SERVICES    *PsiServices,
+  IN       UINT32                 Socket,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSI_IS_SUPPORTED *PF_PSI_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable PSI.
+ *
+ * @param[in]    PsiServices        PSI services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_PSI_INIT (
+  IN       PSI_FAMILY_SERVICES    *PsiServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSI_INIT *PF_PSI_INIT;
+
+/**
+ * Provide the interface to the PSI Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+/* typedef  */struct _PSI_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_PSI_IS_SUPPORTED IsPsiSupported;                                   ///< Method: Family specific call to check if PSI is supported.
+  PF_PSI_INIT         EnablePsiOnSocket;                                ///< Method: Family specific call to enable PSI.
+} /* PSI_FAMILY_SERVICES */;
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_PSI_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateGather.c
new file mode 100644
index 0000000000..f28c853e85
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateGather.c
@@ -0,0 +1,437 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Pstate Data Gather Function.
+ *
+ * Contains code to collect all the Pstate related information from MSRs, and PCI registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuPostInit.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuApicUtilities.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_POST_CONFIGURATION    OptionPstatePostConfiguration;  // global user config record
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PStateGatherStub (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+AGESA_STATUS
+PStateGatherMain (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+PStateGather (
+  IN OUT   VOID *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PStateGatherData
+ *
+ *  Description:
+ *    This function will gather PState information from the MSRs and fill up the
+ *    pStateBuf. This buffer will be used by the PState Leveling, and PState Table
+ *    generation code later.
+ *
+ *  Parameters:
+ *    @param[in]        *PlatformConfig
+ *    @param[in, out]   *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval      AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherData (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   S_CPU_AMD_PSTATE       *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+
+
+  AGESA_STATUS       AgesaStatus;
+
+  AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader);
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Gather data for ACPI Tables if ACPI P-States/C-States object generation is enabled.
+  if ((PlatformConfig->UserOptionPState) || (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) {
+    AgesaStatus = (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr);
+    // Note: Split config struct into PEI/DXE halves. This one is PEI.
+  }
+
+  return AgesaStatus;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGatherStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherStub (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGatherMain
+ *
+ *  Description:
+ *     This is the common routine for BSP gathering the Pstate data.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherMain (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  PopulatedSockets;
+  UINT32                  NumberOfSockets;
+  UINT32                  Socket;
+  AGESA_STATUS            IgnoredSts;
+  PSTATE_LEVELING         *PStateBufferPtr;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+  UINT32                  MaxState;
+  UINT8                   IgnoredByte;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  FamilyServices = NULL;
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  PopulatedSockets = 1;
+  PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);
+
+  PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE);
+
+  MaxState = 0;
+  FamilyServices->GetPstateMaxState (FamilyServices, &MaxState, &IgnoredByte, StdHeader);
+
+  TaskPtr.FuncAddress.PfApTaskI = PStateGather;
+  //
+  // Calculate max buffer size in dwords that need to pass to ap task.
+  //
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES)));
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  //
+  //Get P-States and fill the PStateBufferPtr for BSP
+  //
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+
+  //
+  //Calculate next node buffer address
+  //
+  PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
+  PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
+  PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
+  //
+  //Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
+  //
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        PopulatedSockets++;
+        LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader);
+        TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
+        PStateBufferPtr->SocketNumber = (UINT8) Socket;
+        //
+        //Calculate next node buffer address
+        //
+        PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+        PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
+        PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+      }
+    }
+  }
+  PStateStrucPtr->TotalSocketInSystem = PopulatedSockets;
+
+  return AGESA_SUCCESS;
+}
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGather
+ *
+ *  Description:
+ *     This is the common routine run on each BSC for gathering Pstate data.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateBuffer
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+PStateGather (
+  IN OUT   VOID                *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                 k;
+  UINT32                 IddVal;
+  UINT32                 IddDiv;
+  UINT32                 NodeNum;
+  UINT32                 CoreNum;
+  UINT32                 TempVar_c;
+  UINT32                 TotalEnabledPStates;
+  UINT32                 SwPstate;
+  UINT8                  BoostStates;
+  PCI_ADDR               PciAddress;
+  PSTATE_LEVELING        *PStateBufferPtr;
+  BOOLEAN                PStateEnabled;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+  UINT32                 Socket;
+  AGESA_STATUS           IgnoredSts;
+  CPUID_DATA             CpuId;
+
+  PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
+  TotalEnabledPStates = 0;
+  FamilyServices = NULL;
+  PStateEnabled = FALSE;
+
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  //
+  /// Sockets number:  code looking at PStateBufferPtr->TotalCoresInNode
+  ///        needs to know it is Processor (or socket) core count and NOT a Node Core count.
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+  PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum;
+
+  //
+  // Assume current CoreNum always zero.(BSC)
+  //
+  GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader);
+
+  PStateBufferPtr->CreateAcpiTables = 1;
+
+  //
+  // We need to know the max pstate state in this socket.
+  //
+  FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &BoostStates, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c;
+  PStateBufferPtr->PStateCoreStruct[0].NumberOfBoostedStates = BoostStates;
+
+  for (k = 0; k <= TempVar_c; k++) {
+    // Check if PState is enabled
+    FamilyServices->GetPstateRegisterInfo (        FamilyServices,
+                                                   k,
+                                                   &PStateEnabled,
+                                                   &IddVal,
+                                                   &IddDiv,
+                                                   &SwPstate,
+                                                   StdHeader);
+
+    LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader);
+
+    if (PStateEnabled) {
+      FamilyServices->GetPstateFrequency (
+        FamilyServices,
+        (UINT8) k,
+        &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq),
+        StdHeader);
+
+      FamilyServices->GetPstatePower (
+        FamilyServices,
+        (UINT8) k,
+        &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power),
+        StdHeader);
+
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal;
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv;
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber = SwPstate;
+
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable  = 1;
+      TotalEnabledPStates++;
+    }
+  } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+  // Don't create ACPI Tables if there is one or less than one PState is enabled
+  if (TotalEnabledPStates <= 1) {
+    PStateBufferPtr[0].CreateAcpiTables = 0;
+  }
+
+  //--------------------Check Again--------------------------------
+
+  IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts);
+  // Get the PCI address of internal die 0 as it is the only die programmed.
+  GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+  TempVar_c = 0;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].HtcCapable =
+    (UINT8) ((TempVar_c & 0x00000400) >> 10);    // Bit  10
+
+  TempVar_c = 0;
+  PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit =
+    (UINT8) ((TempVar_c & 0x70000000) >> 28);   // Bits 30:28
+
+  // Get LocalApicId from CPUID Fn0000_0001_EBX
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].LocalApicId = (UINT8) ((CpuId.EBX_Reg & 0xFF000000) >> 24);
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c
new file mode 100644
index 0000000000..90956cee45
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c
@@ -0,0 +1,247 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU create Pstate HPC mode support code.
+ *
+ * Contains code that declares the AGESA CPU Pstate HPC mode related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFeatures.h"
+#include "cpuPstateHpcMode.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnablePstateHpcModeOnAps (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE PstateHpcModeFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should P-state HPC mode be enabled
+ *  If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               P-state HPC mode is supported.
+ * @retval       FALSE              P-state HPC mode cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsPstateHpcModeFeatureSupported (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  UINT32           Socket;
+  PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = TRUE;
+
+  if (PlatformConfig->PStatesInHpcMode) {
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&PstateHpcModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if (FamilyServices == NULL) {
+          IsEnabled = FALSE;
+          break;
+        }
+      }
+    }
+  } else {
+    IsEnabled = FALSE;
+  }
+  return IsEnabled;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable high performance computing (HPC mode)
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializePstateHpcModeFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       BscSocket;
+  UINT32       Ignored;
+  UINT32       BscCoreNum;
+  UINT32       Core;
+  UINT32       Socket;
+  UINT32       NumberOfSockets;
+  UINT32       NumberOfCores;
+  AP_TASK      TaskPtr;
+  AGESA_STATUS IgnoredSts;
+
+  if (!IsWarmReset (StdHeader)) {
+    IDS_HDT_CONSOLE (CPU_TRACE, "    P-state HPC mode is enabled\n");
+
+    IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+    NumberOfSockets = GetPlatformNumberOfSockets ();
+
+    TaskPtr.FuncAddress.PfApTaskI = EnablePstateHpcModeOnAps;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = PlatformConfig;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+        for (Core = 0; Core < NumberOfCores; Core++) {
+          if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+            ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+          }
+        }
+      }
+    }
+
+    EnablePstateHpcModeOnAps (PlatformConfig, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  AP task to enable Pstate HPC mode
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+EnablePstateHpcModeOnAps (
+  IN       VOID *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&PstateHpcModeFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->EnablePstateHpcMode (FamilyServices,
+                                       PlatformConfig,
+                                       StdHeader);
+
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode =
+{
+  PstateHpcMode,
+  (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsPstateHpcModeFeatureSupported,
+  InitializePstateHpcModeFeature
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h
new file mode 100644
index 0000000000..8995398b98
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h
@@ -0,0 +1,127 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Pstate HPC mode Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU Pstate HPC mode related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_PSTATE_HPC_MODE_H_
+#define _CPU_PSTATE_HPC_MODE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_FORWARD_DECLARATION (PSTATE_HPC_MODE_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable P-state HPC mode
+ *
+ * @param[in]    PstateHpcModeService P-state HPC mode services.
+ * @param[in]    PlatformConfig       Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader            Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_PSTATE_HPC_MODE_INIT (
+  IN       PSTATE_HPC_MODE_FAMILY_SERVICES *PstateHpcModeService,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_HPC_MODE_INIT *PF_PSTATE_HPC_MODE_INIT;
+
+/**
+ * Provide the interface to the P-state HPC mode Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _PSTATE_HPC_MODE_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_PSTATE_HPC_MODE_INIT         EnablePstateHpcMode;              ///< Method: Family specific call to enable P-state HPC mode.
+};
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_PSTATE_HPC_MODE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c
new file mode 100644
index 0000000000..76565a61bc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -0,0 +1,1123 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Pstate Leveling Function.
+ *
+ * Contains code to level the Pstates in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuPostInit.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_POST_CONFIGURATION    OptionPstatePostConfiguration;  // global user config record
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PutAllCoreInPState0 (
+  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+StartPstateMsrModify (
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+STATIC
+PutCoreInPState0 (
+  IN       VOID   *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+PStateLevelingStub (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+CorePstateRegModify (
+  IN       VOID               *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PStateLeveling
+ *
+ *  Description:
+ *    This function will populate the PStateBuffer, after doing the PState Leveling
+ *    Note: This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLeveling (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader);
+  return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader));
+  // Note: Split config struct into PEI/DXE halves. This one is PEI.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateLevelingStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLevelingStub (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateLevelingMain
+ *
+ *  Description:
+ *     This is the common routine for creating the ACPI information tables.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32                   i;
+  UINT32                   k;
+  UINT32                   m;
+  UINT32                   TotalIterations;
+  UINT32                   LogicalSocketCount;
+  UINT32                   TempVar_a;
+  UINT32                   TempVar_b;
+  UINT32                   TempVar_c;
+  UINT32                   TempVar_d;
+  UINT32                   TempVar_e;
+  UINT32                   TempVar_f;
+  PCI_ADDR                 PciAddress;
+
+  UINT32                   TempFreqArray[20];
+  UINT32                   TempPowerArray[20];
+  UINT32                   TempIddValueArray[20];
+  UINT32                   TempIddDivArray[20];
+  UINT32                   TempSocketPiArray[20];
+  UINT32                   TempSwP0Array[MAX_SOCKETS_SUPPORTED];
+
+  BOOLEAN                  TempFlag1;
+  BOOLEAN                  TempFlag2;
+  BOOLEAN                  TempFlag3;
+  BOOLEAN                  TempFlag4;
+  BOOLEAN                  AllCoresHaveHtcCapEquToZeroFlag;
+  BOOLEAN                  AllCoreHaveMaxOnePStateFlag;
+  BOOLEAN                  PstateMaxValEquToPstateHtcLimitFlag;
+  BOOLEAN                  AtLeastOneCoreHasPstateHtcLimitEquToOneFlag;
+  BOOLEAN                  PstateMaxValMinusHtcPstateLimitLessThan2Flag;
+  PSTATE_LEVELING          *PStateBufferPtr;
+  PSTATE_LEVELING          *PStateBufferPtrTmp = NULL;
+  UINT32                   MaxPstateInNode;
+  AGESA_STATUS             Status;
+
+  TempFlag1 = FALSE;
+  TempFlag2 = FALSE;
+  TempFlag3 = FALSE;
+  TempFlag4 = FALSE;
+  AllCoresHaveHtcCapEquToZeroFlag = FALSE;
+  AllCoreHaveMaxOnePStateFlag = FALSE;
+  PstateMaxValEquToPstateHtcLimitFlag = FALSE;
+  AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE;
+  PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE;
+  PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
+  Status = AGESA_SUCCESS;
+
+  if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) {
+    PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
+    PStateBufferPtr[0].InitStruct = 1;
+    return AGESA_UNSUPPORTED;
+  }
+
+  LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem;
+  ASSERT (LogicalSocketCount <= MAX_SOCKETS_SUPPORTED);
+
+  // This section of code will execute only for "core 0" i.e. BSP
+  // Read P-States of all the cores.
+  if (PStateBufferPtr[0].InitStruct == 0) {
+    // Determine 'software' P0 indices for each socket
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      TempSwP0Array[i] = (UINT32) (PStateBufferPtrTmp->PStateCoreStruct[0].NumberOfBoostedStates);
+    }
+
+    // Check if core frequency and power are same across all sockets.
+    TempFlag1 = FALSE;
+    for (i = 1; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) {
+        TempFlag1 = TRUE;
+        break;
+      }
+      MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+      for (k = TempSwP0Array[i]; k <= MaxPstateInNode; k++) {
+        if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq !=
+             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) ||
+            (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power !=
+             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) {
+          TempFlag1 = TRUE;
+          break; // Come out of the inner FOR loop
+        }
+      }
+      if (TempFlag1) {
+        break; // Come out of the outer FOR loop
+      }
+    }
+
+    if (!TempFlag1) {
+      // No need to do pStateLeveling, or writing to pState MSR registers
+      // if all CPUs have Identical PStates
+      PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
+      PStateBufferPtr[0].InitStruct = 1;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    } else {
+      PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE;
+    }
+
+    // 1_b) & 1_c)
+    TempFlag1 = FALSE;
+    TempFlag2 = FALSE;
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == TempSwP0Array[i]) {
+        TempFlag1 = TRUE;
+      } else {
+        TempFlag2 = TRUE;
+      }
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) {
+        TempFlag3 = TRUE;
+      } else {
+        TempFlag4 = TRUE;
+      }
+
+      if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
+           PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) {
+        PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
+      }
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue ==
+          PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+        PstateMaxValEquToPstateHtcLimitFlag = TRUE;
+      }
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
+        AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
+      }
+    }
+
+    // Do general setup of flags, that we may use later
+    // Implementation of (1_b)
+    if (TempFlag1 && TempFlag2) {
+      //
+      //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with
+      //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b).
+      //
+      PStateBufferPtr[0].InitStruct = 1;
+      PStateBufferPtr[0].CreateAcpiTables = 0;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    } else if (TempFlag1 && !TempFlag2) {
+      //
+      //all processors have only 1 enabled P-state
+      //
+      AllCoreHaveMaxOnePStateFlag = TRUE;
+      PStateBufferPtr[0].OnlyOneEnabledPState = TRUE;
+    }
+
+    // Processors with F3xE8[HTC_CAPABLE] = 1 can not be
+    // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0.
+    if (TempFlag3 && TempFlag4) {
+      PStateBufferPtr[0].InitStruct = 1;
+      PStateBufferPtr[0].CreateAcpiTables = 0;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    }
+
+    if (TempFlag3) {
+      //
+      //If code run to here means that all processors do not have HTC_CAPABLE.
+      //
+      AllCoresHaveHtcCapEquToZeroFlag = TRUE;
+    }
+
+    //--------------------------------------------------------------------------------
+    // S T E P - 2
+    //--------------------------------------------------------------------------------
+    // Now run the PState Leveling Algorithm which will create mixed CPU P-State
+    // Tables.
+    // Follow the algorithm in the latest BKDG
+    // -------------------------------------------------------------------------------
+    // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the
+    // coherent fabric, and match P0 power for all CPU cores to the highest P0 power
+    // value in the coherent fabric.
+    // 2_a) If all processors have only 1 enabled P-State BIOS must write the
+    //      appropriate CpuFid value resulting from the matched CPU COF to all
+    //      copies of MSRC001_0070[CpuFid], and exit the sequence (No further
+    //      steps are executed)
+    //--------------------------------------------------------------------------------
+    // Identify the lowest P0 Frequency and maximum P0 Power
+    TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].CoreFreq;
+    TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].Power;
+    TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddValue;
+    TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddDiv;
+
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq) {
+        TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq;
+      }
+
+      if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power) {
+        TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power;
+        TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue;
+        TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv;
+      }
+    }
+
+    // Set P0 Frequency and Power for all CPUs
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq = TempVar_d;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power = TempVar_e;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue = TempVar_a;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv = TempVar_b;
+    }
+
+    // 2_a)
+    if (!AllCoreHaveMaxOnePStateFlag) {
+      //--------------------------------------------------------------------------
+      // STEP - 3
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for P-states used by HTC. Skip to step 4
+      // is any processor reports F3xE8[HTC_Capable] = 0;
+      // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for
+      //      processors with F3x64[HtcPstateLimit] = 000b.
+      // 3_b) Identify the lowest CPU COF for all processors in the P-state
+      //      pointed to by [The Hardware Thermal Control (HTC) Register]
+      //      F3x64[HtcPstateLimit]
+      // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control
+      //      (HTC) Register] F3x64[HtcPstateLimit] for all processors to the
+      //      previously identified lowest CPU COF value.
+      // 3_d) Identify the highest power for all processors in the P-state
+      //      pointed to by [The Hardware Thermal Control (HTC) Register]
+      //      F3x64[HtcPstateLimit].
+      // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC)
+      //      Register] F3x64[HtcPstateLimit] to the previously identified
+      //      highest power value.
+      if (!AllCoresHaveHtcCapEquToZeroFlag) {
+        // 3_a)
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) {
+            // To Be Done (Set Htc and Stc PstateLimit values)
+            // for this CPU (using PCI address space)
+            for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) {
+              if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) {
+                // Set F3x64[HtcPstateLimit] = 001b
+                PciAddress.Address.Function = FUNC_3;
+                PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+                // Bits 30:28
+                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
+                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+
+                // Set F3x68[StcPstateLimit] = 001b
+                PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG;
+                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+                // Bits 28:30
+                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
+                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+              }
+            }
+            // Set LocalBuffer
+            PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1;
+            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) {
+              PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
+            }
+
+            if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) {
+              PstateMaxValEquToPstateHtcLimitFlag = TRUE;
+            }
+          }
+
+          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
+            AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
+          }
+        }
+
+        // 3_b) and 3_d)
+        TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit;
+        TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
+        TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
+        TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
+        TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          for (k = 0; k < 1; k++) {
+            TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+            if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
+              TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
+            }
+
+            if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
+              TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
+              TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
+              TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
+            }
+          }
+        }
+
+        // 3_c) and 3_e)
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
+        }
+      } // if(AllCoresHaveHtcCapEquToZeroFlag)
+
+
+      //--------------------------------------------------------------------------
+      // STEP - 4
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for the lowest performance P-state:
+      // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor,
+      //      set PstateEn = 0 for all the P-states greater than
+      //      F3x64[HtcPstateLimit] for all processors.
+      // 4_b) Identify the lowest CPU COF for all processors in the P-state
+      //      pointed to by F3xDC[PstateMaxVal].
+      // 4_c) Modify the CPU COF for all processors in the P-state pointed to by
+      //      F3xDC[PstateMaxVal] to the previously identified lowest CPU COF
+      //      value.
+      // 4_d) Identify the highest power for all processors in the P-state
+      //      pointed to by F3xDC[PstateMaxVal].
+      // 4_e) Modify the power for all processors in the P-state pointed to by
+      //      F3xDC[PstateMaxVal] to the previously identified highest power
+      //      value.
+
+      // 4_a)
+      if (PstateMaxValEquToPstateHtcLimitFlag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1;
+          for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) {
+            PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+          }
+          //--------------------------------------------------------------------------
+          // STEP - 5
+          //--------------------------------------------------------------------------
+          // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance
+          //      P-state with PstateEn set for each processor (Step 4 can disable
+          //      P-states pointed to by F3xDC[PstateMaxVal])
+
+          // Use this value of HtcPstateLimit to program the
+          // F3xDC[pStateMaxValue]
+          TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+          TempVar_e <<= 8;
+          // Bits 10:8
+
+          for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) {
+            if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) {
+              PciAddress.Address.Function = FUNC_3;
+              PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+              LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+              TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e;
+              LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+            }
+          }//End of step 5
+        }
+      }// End of 4_a)
+
+      // 4_b) and 4_d)
+      TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue;
+      TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
+      TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
+      TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
+      TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
+
+      for (i = 0; i < LogicalSocketCount; i++) {
+        CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+        TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+        if (TempVar_d >
+            PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
+          TempVar_d =
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
+        }
+
+        if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
+          TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
+          TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
+          TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
+        }
+      }
+
+      // 4_c) and 4_e)
+      for (i = 0; i < LogicalSocketCount; i++) {
+        CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+        TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
+      }
+
+
+      //--------------------------------------------------------------------------
+      // STEP - 6
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for upper intermediate performance
+      // P-state(s):
+      // Upper intermediate PStates = PStates between (Not including) P0 and
+      // F3x64[HtcPstateLimit]
+      // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0
+      //      for enabled upper intermediate P-states for all processors with
+      //      F3x64[HtcPstateLimit] > 001b and skip the remaining actions for
+      //      this numbered step.
+      // 6_b) Define each of the available upper intermediate P-states; for each
+      //      processor concurrently evaluate the following loop; when any
+      //      processor falls out of the loop (runs out of available upper
+      //      intermediate Pstates) all other processors have their remaining
+      //      upper intermediate P-states invalidated (PstateEn = 0);
+      //      for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--)
+      //         - Identify the lowest CPU COF for P(i).
+      //         - Identify the highest power for P(i).
+      //         - Modify P(i) CPU COF for all processors to the previously
+      //           identified lowest CPU COF value.
+      //         - Modify P(i) power for all processors to the previously
+      //           identified highest power value.
+
+      // 6_a)
+      if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          for (k = TempSwP0Array[i] + 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) {
+            if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) {
+              // Make a function call to clear the
+              // structure values
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+            }
+          }
+        }
+      }
+      // 6_b)
+      else {
+        // Identify Lowest Frequency and Highest Power
+        TotalIterations = 0;
+        TempFlag1 = TRUE;
+
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1;
+        }
+
+        do {
+          //For first socket, try to find a candidate
+          if (TempSocketPiArray[0] != TempSwP0Array[0]) {
+            while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
+              TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
+              if (TempSocketPiArray[0] == TempSwP0Array[0]) {
+                TempFlag1 = FALSE;
+                break;
+              }
+            }
+          } else {
+            TempFlag1 = FALSE;
+          }
+          if (TempFlag1) {
+            TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
+            TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
+            TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
+            TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
+
+            //Try to find next candidate
+            for (i = 1; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempSocketPiArray[i] != TempSwP0Array[i]) {
+                while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
+                  TempSocketPiArray[i]--;
+                  if (TempSocketPiArray[i] == TempSwP0Array[i]) {
+                    TempFlag1 = FALSE;
+                    break;
+                  }
+                }//end while
+              } else {
+                TempFlag1 = FALSE;
+              }
+
+            } //end for LogicalSocketCount
+          }
+
+          if (TempFlag1) {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              //
+              //Compare
+              //
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
+                TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
+              }
+
+              if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
+                TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
+                TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
+                TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
+              }
+            }
+            // Modify (Pi) CPU COF and Power for all the CPUs
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power    = TempPowerArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv   = TempIddDivArray[TotalIterations];
+              TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
+            }
+          } else {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              for (m = TempSocketPiArray[i]; m > TempSwP0Array[i]; m--) {
+                PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
+              }
+            }
+          }
+
+          TotalIterations++;
+        } while (TempFlag1);
+
+      } // else
+
+      //--------------------------------------------------------------------------
+      // STEP - 7
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for lower intermediate performance P - state(s)
+      // Lower Intermediate Pstates = Pstates between (not including)
+      // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal]
+      // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any
+      //      processor, set PstateEn = 0 for enabled lower intermediate P - states
+      //      for all processors with (F3xDC[PstateMaxVal] -
+      //      F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this
+      //      numbered step.
+      // 7_b) Define each of the available lower intermediate P-states; for each
+      //      processor concurrently evaluate the following loop; when any
+      //      processor falls out of the loop (runs out of available lower
+      //      intermediate Pstates) all other processors have their remaining
+      //      lower intermediate P-states invalidated (PstateEn = 0);
+      //      for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--)
+      //         - Identify the lowest CPU COF for P-states between
+      //           (not including) F3x64[HtcPstateLimit] and P(i).
+      //         - Identify the highest power for P-states between
+      //           (not including) F3x64[HtcPstateLimit] and P(i).
+      //         - Modify P(i) CPU COF for all processors to the previously
+      //           identified lowest CPU COF value.
+      //         - Modify P(i) power for all processors to the previously
+      //           identified highest power value.
+
+
+      // 7_a)
+      if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+
+          for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
+              k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+              k--) {
+            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
+                 PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) {
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+            }
+          }
+        }
+      }
+
+      // 7_b)
+      else {
+        // Identify Lowest Frequency and Highest Power
+
+        TotalIterations = 0;
+        TempFlag1 = TRUE;
+
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
+        }
+
+        do {
+          //For first socket, try to find a candidate
+          if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
+            while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
+              TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
+              if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
+                TempFlag1 = FALSE;
+                break;
+              }
+            }
+          } else {
+            TempFlag1 = FALSE;
+          }
+          if (TempFlag1) {
+            TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
+            TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
+            TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
+            TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
+
+            //Try to find next candidate
+            for (i = 1; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+                while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
+                  TempSocketPiArray[i]--;
+                  if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+                    TempFlag1 = FALSE;
+                    break;
+                  }
+                }//end while
+              } else {
+                TempFlag1 = FALSE;
+              }
+            } //end for LogicalSocketCount
+          }
+
+          if (TempFlag1) {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              //
+              //Compare
+              //
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
+                TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
+              }
+              if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
+                TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
+                TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
+                TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
+              }
+            }
+            // Modify (Pi) CPU COF and Power for all the CPUs
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power    = TempPowerArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv   = TempIddDivArray[TotalIterations];
+              TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
+            }
+          } else {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) {
+                PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
+              }
+            }
+          }
+          TotalIterations++;
+        } while (TempFlag1);
+      } // else
+    } // if(!AllCoreHaveMaxOnePStateFlag)
+
+    PStateBufferPtr[0].InitStruct = 1;
+  } // CurrentCore
+
+
+  // Update the pState MSRs
+  // This can be done only by individual core
+  StartPstateMsrModify (PStateStrucPtr, StdHeader);
+
+  //----------------------------------------------------------------------------------
+  // STEP - 8
+  //----------------------------------------------------------------------------------
+  // Place all cores into a valid COF and VID configuration corresponding to an
+  // enabled P-state:
+  // 8_a) Select an enabled P-state != to the P-state pointed to by
+  //      MSRC001_0063[CurPstate] for each core.
+  // 8_b) Transition all cores to the selected P-states by writing the Control value
+  //      from the_PSS object corresponding to the selected P-state to
+  //      MSRC001_0062[PstateCmd].
+  // 8_c) Wait for all cores to report the Status value from the _PSS object
+  //      corresponding to the selected P-state in MSRC001_0063[CurPstate].
+  //
+  PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PutAllCoreInPState0
+ *
+ *  Description:
+ *    This function will put core pstate to p0.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateBufferPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PutAllCoreInPState0 (
+  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCoreNum;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  PutCoreInPState0 (PStateBufferPtr, StdHeader);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CorePstateRegModify
+ *
+ *  Description:
+ *    This function will setting the Pstate MSR to each APs base on Pstate Buffer.
+ *    Note: This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in,out]    *CpuAmdPState
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+CorePstateRegModify (
+  IN       VOID               *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  PSTATE_CPU_FAMILY_SERVICES   *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL)
+  FamilySpecificServices->SetPStateLevelReg  (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will set msr on all cores of all nodes.
+ *
+ * @param[in]     CpuAmdPState  Pointer to S_CPU_AMD_PSTATE.
+ * @param[in]     StdHeader     Header for library and services.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds
+ *
+ */
+AGESA_STATUS
+StartPstateMsrModify (
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCoreNum;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify;
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  CorePstateRegModify (CpuAmdPState, StdHeader);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CpuGetPStateLevelStructure
+ *
+ *  Description:
+ *    Based on the LogicalSocketNumber, this function will return a pointer
+ *      point to the accurate offset of the PSTATE_LEVELING structure.
+ *
+ *  Parameters:
+ *    @param[in,out]          *PStateBufferPtr
+ *    @param[in]              *CpuAmdPState
+ *    @param[in]              LogicalSocketNumber
+ *    @param[in]              *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CpuGetPStateLevelStructure (
+     OUT   PSTATE_LEVELING     **PStateBufferPtr,
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       UINT32              LogicalSocketNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PSTATE_LEVELING         *PStateBufferPtrTmp;
+  UINT32                  i;
+
+  if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc;
+
+  for (i = 1; i <= LogicalSocketNumber; i++) {
+    PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes));
+  }
+
+  *PStateBufferPtr = PStateBufferPtrTmp;
+
+  return AGESA_SUCCESS;
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PutCoreInPState0
+ *
+ *  Description:
+ *    This function will take the CPU core into P0
+ *
+ *  Parameters:
+ *    @param[in]         *PStateBuffer
+ *    @param[in]         *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+PutCoreInPState0 (
+  IN       VOID   *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  PSTATE_LEVELING         *PStateBufferPtr;
+
+  PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
+
+  if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) ||
+     (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) {
+    return;
+  }
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->TransitionPstate  (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.c
new file mode 100644
index 0000000000..4776b13434
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.c
@@ -0,0 +1,917 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD PSTATE, ACPI table related API functions.
+ *
+ * Contains code that generates the _PSS, _PCT, and other ACPI tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#include "cpuPstateTables.h"
+#include "cpuFeatures.h"
+#include "cpuIoCstate.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_LATE_CONFIGURATION    OptionPstateLateConfiguration;  // global user config record
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+extern CPU_FAMILY_SUPPORT_TABLE            IoCstateFamilyServiceTable;
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuSsdtHdrStruct =
+{
+  {'S','S','D','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'P','O','W','E','R','N','O','W'},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT32
+STATIC
+CalAcpiTablesSize (
+  IN       S_CPU_AMD_PSTATE       *AmdPstatePtr,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+GenerateSsdtStub (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+
+UINT32
+CreateAcpiTablesStub (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **SsdtPtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+CreatePStateAcpiTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **SsdtPtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+CreateCStateAcpiTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **SsdtPtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+GenerateSsdt (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CalAcpiTablesSize
+ *
+ *  Description:
+ *    This function will calculate the size of ACPI PState tables
+ *
+ *  Parameters:
+ *    @param[in]     *AmdPstatePtr
+ *    @param[in]     *PlatformConfig
+ *    @param[in]     *StdHeader
+ *
+ *    @retval      UINT32
+ *
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+STATIC
+CalAcpiTablesSize (
+  IN       S_CPU_AMD_PSTATE       *AmdPstatePtr,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                    ScopeSize;
+  UINT32                    CoreCount;
+  UINT32                    SocketCount;
+  UINT32                    MaxCoreNumberInCurrentSocket;
+  UINT32                    MaxSocketNumberInSystem;
+  UINT32                    MaxPstateNumberInCurrentCore;
+  UINT32                    CstateAcpiObjSize;
+  PSTATE_LEVELING           *PStateLevelingBufferStructPtr;
+  IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices;
+
+  ScopeSize = sizeof (ACPI_TABLE_HEADER);
+  CstateAcpiObjSize = 0;
+  IoCstateFamilyServices = NULL;
+
+  PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
+  MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem;
+
+  if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&IoCstateFamilyServices, StdHeader);
+    // If we're supporting multiple families, only proceed when IO Cstate family services are available
+    if (IoCstateFamilyServices != NULL) {
+      CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader);
+    }
+  }
+
+  for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) {
+    MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode;
+    for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) {
+      MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1;
+
+      ScopeSize += (SCOPE_STRUCT_SIZE - 1); // Scope size per core
+      ScopeSize += CstateAcpiObjSize;       // C-State ACPI objects size per core
+
+      // Add P-State ACPI Objects size per core
+      if ((PStateLevelingBufferStructPtr[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) {
+        ScopeSize += (PCT_STRUCT_SIZE +
+                     PSS_HEADER_STRUCT_SIZE +
+                     (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) +
+                     XPSS_HEADER_STRUCT_SIZE +
+                     (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) +
+                     PSD_HEADER_STRUCT_SIZE +
+                     PSD_BODY_STRUCT_SIZE +
+                     PPC_HEADER_BODY_STRUCT_SIZE);
+      }
+    }
+    ScopeSize += MaxCoreNumberInCurrentSocket;
+    PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  }
+  AmdPstatePtr->SizeOfBytes = ScopeSize;
+
+  return ScopeSize;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  GenerateSsdtStub
+ *
+ *  Description:
+ *     This is the default routine for use when both PState and CState option is NOT
+ *     requested. The option install process will create and fill the transfer vector
+ *     with the address of the proper routine (Main or Stub). The link optimizer will
+ *     strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+GenerateSsdtStub (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  GenerateSsdt
+ *
+ *  Description:
+ *    This function will populate the SSDT with ACPI P-States and C-States Objects, whenever
+ *    necessary
+ *    This function should be called only from BSP
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT pointer
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GenerateSsdt (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  UINT32                 i;
+  UINT32                 j;
+  UINT32                 TempVar8_a;
+  UINT32                 CurrSize;
+  UINT32                 TempVar_a;
+  UINT32                 TempVar_b;
+  UINT32                 ScopeSize;
+  UINT32                 CoreCount;
+  UINT32                 SocketCount;
+  UINT32                 MaxCorePerNode;
+  UINT8                  LocalApicId;
+  UINT8                  *IntermediatePtr;
+  AGESA_STATUS           AgesaStatus;
+  LOCATE_HEAP_PTR        LocateHeapParams;
+  ALLOCATE_HEAP_PARAMS   AllocateHeapParams;
+  S_CPU_AMD_PSTATE       *AmdPstatePtr;
+  PSTATE_LEVELING        *PStateLevelingBufferStructPtr;
+  SCOPE                  *ScopeAcpiTablesStructPtr;
+  SCOPE                  *ScopeAcpiTablesStructPtrTemp;
+
+  AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader);
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  // If P-State and C-State ACPI tables do not need to be generated, exit this routine
+  if ((!PlatformConfig->UserOptionPState) && (!IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) {
+    AgesaStatus = AGESA_UNSUPPORTED;
+    return AgesaStatus;
+  }
+
+  // Initialize data variables
+  ScopeSize   = 0;
+  CoreCount   = 0;
+  LocalApicId = 0;
+  CurrSize    = 0;
+
+  // Locate P-State data buffer
+  LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
+  AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    return AGESA_ERROR;
+  }
+  AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader);
+
+  AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr;
+  PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
+
+  // Allocate rough buffer for AcpiTable, if SsdtPtr is NULL
+  if (*SsdtPtr == NULL) {
+    //Do not know the actual size.. pre-calculate it.
+    AllocateHeapParams.RequestedBufferSize = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader);
+    AllocateHeapParams.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE;
+    AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader);
+    if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader);
+    *SsdtPtr = AllocateHeapParams.BufferPtr;
+  }
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  SSDT is created\n");
+
+  // Copy SSDT header into allocated buffer
+  LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+  IntermediatePtr = (UINT8 *) *SsdtPtr;
+  ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)];
+
+  SocketCount = AmdPstatePtr->TotalSocketInSystem;
+
+  // Generate name scope and ACPI objects for every core in the system
+  for (i = 0; i < SocketCount; i++) {
+    MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode;
+    for (j = 0; j < MaxCorePerNode; j++) {
+      CoreCount++;
+      // Set Name Scope for CPU0, 1, 2, ..... n
+      // CPU0 to CPUn will name  as  C000 to Cnnn
+      // -----------------------------------------
+      ScopeAcpiTablesStructPtr->ScopeOpcode      = SCOPE_OPCODE;
+      // This value will be filled at the end of this function
+      // Since at this time, we don't know how many  Pstates we
+      // would have
+      ScopeAcpiTablesStructPtr->ScopeLength      = 0;
+      ScopeAcpiTablesStructPtr->ScopeValue1      = SCOPE_VALUE1;
+      ScopeAcpiTablesStructPtr->ScopeValue2      = SCOPE_VALUE2;
+      ScopeAcpiTablesStructPtr->ScopeNamePt1a__  = SCOPE_NAME__;
+      if (PlatformConfig->ProcessorScopeInSb) {
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_P  = SCOPE_NAME_S;
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_R  = SCOPE_NAME_B;
+      } else {
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_P  = SCOPE_NAME_P;
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_R  = SCOPE_NAME_R;
+      }
+      ScopeAcpiTablesStructPtr->ScopeNamePt1b__  = SCOPE_NAME__;
+      ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z'))
+      ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \
+              ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \
+              (PlatformConfig->ProcessorScopeName1 == '_'))
+
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_C  = PlatformConfig->ProcessorScopeName0;
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_P  = PlatformConfig->ProcessorScopeName1;
+
+      TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F;
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_U  = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
+
+      TempVar8_a = (CoreCount - 1) & 0x0F;
+      if (TempVar8_a < 0xA) {
+        ScopeAcpiTablesStructPtr->ScopeNamePt2a_0  = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
+      } else {
+        ScopeAcpiTablesStructPtr->ScopeNamePt2a_0  = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA);
+      }
+      // Increment and typecast the pointer
+      ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr;
+      ScopeAcpiTablesStructPtrTemp++;
+
+      // Get the Local Apic Id for each core
+      LocalApicId = PStateLevelingBufferStructPtr->PStateCoreStruct[0].LocalApicId + (UINT8) j;
+
+      // Create P-State ACPI Objects
+      CurrSize += ((*(OptionPstateLateConfiguration.PstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader));
+
+      // Create C-State ACPI Objects
+      CurrSize += ((*(OptionPstateLateConfiguration.CstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader));
+
+      // Now update the SCOPE Length field
+      {
+        CurrSize += (SCOPE_STRUCT_SIZE - 1);
+        ScopeSize += CurrSize;
+
+        TempVar_b = ((CurrSize << 4) & 0x0000FF00);
+        TempVar_b |= ((CurrSize & 0x0000000F) | 0x00000040);
+        TempVar_a = TempVar_b;
+        ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a;
+        CurrSize = 0;
+      }
+
+      ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp;
+    }
+    //Calculate next node buffer address
+    PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  }
+  //Update SSDT header Checksum
+  ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER));
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTablesStub
+ *
+ *  Description:
+ *     This is the default routine for use when the P-State or C-State option is NOT
+ *     requested. The option install process will create and fill the transfer vector
+ *     with the address of the proper routine (Main or Stub). The link optimizer will
+ *     strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]     PlatformConfig       Platform operational characteristics; power cap
+ *    @param[in]     PStateLevelingBuffer Buffer that contains P-State Leveling information
+ *    @param[in,out] SsdtPtr              ACPI SSDT table pointer
+ *    @param[in]     LocalApicId          Local Apic Id
+ *    @param[in]     StdHeader            Handle to config for library and services
+ *
+ *    @retval        Size of generated ACPI objects
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+UINT32
+CreateAcpiTablesStub (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **SsdtPtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return  0;
+}
+
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreatePStateAcpiTables
+ *
+ *  Description:
+ *     This is the common routine for creating ACPI P-State objects
+ *
+ *  Parameters:
+ *    @param[in]     PlatformConfig       Platform operational characteristics; power cap
+ *    @param[in]     PStateLevelingBuffer Buffer that contains P-State Leveling information
+ *    @param[in,out] SsdtPtr              ACPI SSDT table pointer
+ *    @param[in]     LocalApicId          Local Apic Id
+ *    @param[in]     StdHeader            Handle to config for library and services
+ *
+ *    @retval          Size of generated ACPI P-States objects
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+UINT32
+CreatePStateAcpiTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **SsdtPtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT8                      PstateCapLevelSupport;
+  UINT8                      PStateMaxValueOnCurrentCore;
+  BOOLEAN                    PstateCapEnable;
+  BOOLEAN                    PstateCapLevelSupportDetermined;
+  BOOLEAN                    IsPsdDependent;
+  UINT32                     k;
+  UINT32                     TempVar_a;
+  UINT32                     TempVar_b;
+  UINT32                     TempVar_c;
+  UINT32                     PstateCapInputMilliWatts;
+  UINT32                     CurrSize;
+  UINT32                     PstateCount;
+  UINT32                     CoreCount1;
+  UINT32                     TransAndBusMastLatency;
+  AGESA_STATUS               IgnoredStatus;
+  PCI_ADDR                   PciAddress;
+  PCT_HEADER_BODY            *pPctAcpiTables;
+  PSS_HEADER                 *pPssHeaderAcpiTables;
+  PSS_BODY                   *pPssBodyAcpiTables;
+  XPSS_HEADER                *pXpssHeaderAcpiTables;
+  XPSS_BODY                  *pXpssBodyAcpiTables;
+  PSD_HEADER                 *pPsdHeaderAcpiTables;
+  PSD_BODY                   *pPsdBodyAcpiTables;
+  PPC_HEADER_BODY            *pPpcAcpiTables;
+  PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
+
+  CurrSize = 0;
+  PstateCount = 0;
+  PstateCapEnable = FALSE;
+  PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP;
+  PstateCapLevelSupportDetermined = TRUE;
+  PstateCapInputMilliWatts = PlatformConfig->PowerCeiling;
+  IsPsdDependent = !(PlatformConfig->ForcePstateIndependent);
+  TransAndBusMastLatency = 0;
+
+  if ((PStateLevelingBuffer[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) {
+    pPctAcpiTables = (PCT_HEADER_BODY *) *SsdtPtr;
+
+    //Check Pstate Capability
+    if (PstateCapInputMilliWatts != 0) {
+      PstateCapEnable = TRUE;
+      PstateCapLevelSupportDetermined = FALSE;
+    }
+
+    PStateMaxValueOnCurrentCore = PStateLevelingBuffer->PStateCoreStruct[0].PStateMaxValue;
+    if (OptionPstateLateConfiguration.CfgPstatePct) {
+      // Set _PCT Table
+      // --------------
+      pPctAcpiTables->NameOpcode              = NAME_OPCODE;
+      pPctAcpiTables->PctName_a__             = PCT_NAME__;
+      pPctAcpiTables->PctName_a_P             = PCT_NAME_P;
+      pPctAcpiTables->PctName_a_C             = PCT_NAME_C;
+      pPctAcpiTables->PctName_a_T             = PCT_NAME_T;
+      pPctAcpiTables->Value1                  = PCT_VALUE1;
+      pPctAcpiTables->Value2                  = PCT_VALUE2;
+      pPctAcpiTables->Value3                  = PCT_VALUE3;
+      pPctAcpiTables->GenericRegDescription1  = GENERIC_REG_DESCRIPTION;
+      pPctAcpiTables->Length1                 = PCT_LENGTH;
+      pPctAcpiTables->AddressSpaceId1         = PCT_ADDRESS_SPACE_ID;
+      pPctAcpiTables->RegisterBitWidth1       = PCT_REGISTER_BIT_WIDTH;
+      pPctAcpiTables->RegisterBitOffset1      = PCT_REGISTER_BIT_OFFSET;
+      pPctAcpiTables->Reserved1               = PCT_RESERVED;
+      pPctAcpiTables->ControlRegAddressLo     = PCT_CONTROL_REG_LO;
+      pPctAcpiTables->ControlRegAddressHi     = PCT_CONTROL_REG_HI;
+      pPctAcpiTables->Value4                  = PCT_VALUE4;
+      pPctAcpiTables->Value5                  = PCT_VALUE5;
+      pPctAcpiTables->GenericRegDescription2  = GENERIC_REG_DESCRIPTION;
+      pPctAcpiTables->Length2                 = PCT_LENGTH;
+      pPctAcpiTables->AddressSpaceId2         = PCT_ADDRESS_SPACE_ID;
+      pPctAcpiTables->RegisterBitWidth2       = PCT_REGISTER_BIT_WIDTH;
+      pPctAcpiTables->RegisterBitOffset2      = PCT_REGISTER_BIT_OFFSET;
+      pPctAcpiTables->Reserved2               = PCT_RESERVED;
+      pPctAcpiTables->StatusRegAddressLo      = PCT_STATUS_REG_LO;
+      pPctAcpiTables->StatusRegAddressHi      = PCT_STATUS_REG_HI;
+      pPctAcpiTables->Value6                  = PCT_VALUE6;
+
+      // Increment and then typecast the pointer
+      pPctAcpiTables++;
+      CurrSize += PCT_STRUCT_SIZE;
+
+      *SsdtPtr = pPctAcpiTables;
+    } // end of OptionPstateLateConfiguration.CfgPstatePct
+
+    pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables;
+    pPssBodyAcpiTables   = (PSS_BODY *)   pPctAcpiTables;
+    if (OptionPstateLateConfiguration.CfgPstatePss) {
+      // Set _PSS Header
+      // Note: Set pssLength and numOfItemsInPss later
+      //---------------------------------------------------
+      pPssHeaderAcpiTables->NameOpcode      = NAME_OPCODE;
+      pPssHeaderAcpiTables->PssName_a__     = PSS_NAME__;
+      pPssHeaderAcpiTables->PssName_a_P     = PSS_NAME_P;
+      pPssHeaderAcpiTables->PssName_a_S     = PSS_NAME_S;
+      pPssHeaderAcpiTables->PssName_b_S     = PSS_NAME_S;
+      pPssHeaderAcpiTables->PkgOpcode       = PACKAGE_OPCODE;
+
+      pPssHeaderAcpiTables++;
+      pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables;
+      // Restore the pPssHeaderAcpiTables
+      pPssHeaderAcpiTables--;
+
+      // Set _PSS Body
+      //---------------
+      PstateCount = 0;
+
+      // Calculate PCI address for socket only
+      GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus);
+      TransAndBusMastLatency = 0;
+      GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (CONST VOID **)&FamilyServices, StdHeader);
+      ASSERT (FamilyServices != NULL)
+      FamilyServices->GetPstateLatency (  FamilyServices,
+                                          PStateLevelingBuffer,
+                                          &PciAddress,
+                                          &TransAndBusMastLatency,
+                                          StdHeader);
+
+      for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+        if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+          pPssBodyAcpiTables->PkgOpcode           = PACKAGE_OPCODE;
+          pPssBodyAcpiTables->PkgLength           = PSS_PKG_LENGTH;
+          pPssBodyAcpiTables->NumOfElements       = PSS_NUM_OF_ELEMENTS;
+          pPssBodyAcpiTables->DwordPrefixOpcode1  = DWORD_PREFIX_OPCODE;
+          pPssBodyAcpiTables->Frequency           =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
+          pPssBodyAcpiTables->DwordPrefixOpcode2  = DWORD_PREFIX_OPCODE;
+          pPssBodyAcpiTables->Power               =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power;
+
+          if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) {
+            PstateCapLevelSupport = (UINT8) PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
+            PstateCapLevelSupportDetermined = TRUE;
+          }
+
+          pPssBodyAcpiTables->DwordPrefixOpcode3  = DWORD_PREFIX_OPCODE;
+          pPssBodyAcpiTables->TransitionLatency   = TransAndBusMastLatency;
+          pPssBodyAcpiTables->DwordPrefixOpcode4  = DWORD_PREFIX_OPCODE;
+          pPssBodyAcpiTables->BusMasterLatency    = TransAndBusMastLatency;
+          pPssBodyAcpiTables->DwordPrefixOpcode5  = DWORD_PREFIX_OPCODE;
+          pPssBodyAcpiTables->Control             =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
+          pPssBodyAcpiTables->DwordPrefixOpcode6  = DWORD_PREFIX_OPCODE;
+          pPssBodyAcpiTables->Status              =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
+
+          pPssBodyAcpiTables++;
+          PstateCount++;
+        }
+      } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+      if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) {
+        PstateCapLevelSupport = PStateMaxValueOnCurrentCore;
+      }
+
+      // Set _PSS Header again
+      // Now Set pssLength and numOfItemsInPss
+      //---------------------------------------
+      TempVar_a = (PstateCount * PSS_BODY_STRUCT_SIZE) + 3;
+      TempVar_b = TempVar_a;
+      TempVar_c = ((TempVar_b << 4) & 0x0000FF00);
+      TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040);
+      TempVar_a = (UINT16) TempVar_c;
+
+      pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a;
+      pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PstateCount;
+      CurrSize += (PSS_HEADER_STRUCT_SIZE + (PstateCount * PSS_BODY_STRUCT_SIZE));
+
+      *SsdtPtr = pPssBodyAcpiTables;
+    } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss
+
+    // Set XPSS Table
+    //---------------
+    // Typecast the pointer
+    pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables;
+    pXpssBodyAcpiTables   = (XPSS_BODY *)   pPssBodyAcpiTables;
+    if (OptionPstateLateConfiguration.CfgPstateXpss) {
+      // Set XPSS Header
+      // Note: Set the pssLength and numOfItemsInPss later
+      //---------------------------------------------------
+      pXpssHeaderAcpiTables->NameOpcode       = NAME_OPCODE;
+      pXpssHeaderAcpiTables->XpssName_a_X     = PSS_NAME_X;
+      pXpssHeaderAcpiTables->XpssName_a_P     = PSS_NAME_P;
+      pXpssHeaderAcpiTables->XpssName_a_S     = PSS_NAME_S;
+      pXpssHeaderAcpiTables->XpssName_b_S     = PSS_NAME_S;
+      pXpssHeaderAcpiTables->PkgOpcode        = PACKAGE_OPCODE;
+
+      // Increment and then typecast the pointer
+      pXpssHeaderAcpiTables++;
+      pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables;
+      // Restore the pXpssHeaderAcpiTables
+      pXpssHeaderAcpiTables--;
+
+      // Set XPSS Body
+      //---------------
+      for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+        if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+          pXpssBodyAcpiTables->PkgOpcode          = PACKAGE_OPCODE;
+          pXpssBodyAcpiTables->PkgLength          = XPSS_PKG_LENGTH;
+          pXpssBodyAcpiTables->NumOfElements      = XPSS_NUM_OF_ELEMENTS;
+          pXpssBodyAcpiTables->XpssValueTbd       = 04;
+          pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE;
+          pXpssBodyAcpiTables->Frequency          =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
+          pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE;
+          pXpssBodyAcpiTables->Power              =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power;
+          pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE;
+          pXpssBodyAcpiTables->TransitionLatency  = TransAndBusMastLatency;
+          pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE;
+          pXpssBodyAcpiTables->BusMasterLatency   = TransAndBusMastLatency;
+          pXpssBodyAcpiTables->ControlBuffer      = XPSS_ACPI_BUFFER;
+          pXpssBodyAcpiTables->ControlLo          =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
+          pXpssBodyAcpiTables->ControlHi          = 0;
+          pXpssBodyAcpiTables->StatusBuffer       = XPSS_ACPI_BUFFER;
+          pXpssBodyAcpiTables->StatusLo           =
+          PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
+          pXpssBodyAcpiTables->StatusHi           = 0;
+          pXpssBodyAcpiTables->ControlMaskBuffer  = XPSS_ACPI_BUFFER;
+          pXpssBodyAcpiTables->ControlMaskLo      = 0;
+          pXpssBodyAcpiTables->ControlMaskHi      = 0;
+          pXpssBodyAcpiTables->StatusMaskBuffer   = XPSS_ACPI_BUFFER;
+          pXpssBodyAcpiTables->StatusMaskLo       = 0;
+          pXpssBodyAcpiTables->StatusMaskHi       = 0;
+
+          pXpssBodyAcpiTables++;
+        }
+      } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+      // Set XPSS Header again
+      // Now set pssLength and numOfItemsInPss
+      //---------------------------------------
+      TempVar_a = (PstateCount * XPSS_BODY_STRUCT_SIZE) + 3;
+      TempVar_b = TempVar_a;
+      TempVar_c = ((TempVar_b << 4) & 0x0000FF00);
+      TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040);
+      TempVar_a = (UINT16) TempVar_c;
+
+      pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a;
+      pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PstateCount;
+      CurrSize += (XPSS_HEADER_STRUCT_SIZE + (PstateCount * XPSS_BODY_STRUCT_SIZE));
+
+      *SsdtPtr = pXpssBodyAcpiTables;
+    } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss
+
+    // Set _PSD Table
+    //---------------
+    // Typecast the pointer
+    pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables;
+    pPsdBodyAcpiTables = (PSD_BODY *)     pXpssBodyAcpiTables;
+    // Get Total Cores Per Node
+    if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) {
+      GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (CONST VOID **)&FamilyServices, StdHeader);
+      ASSERT (FamilyServices != NULL)
+      if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) &&
+          FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) {
+        // Set _PSD Header
+        //----------------
+        pPsdHeaderAcpiTables->NameOpcode    = NAME_OPCODE;
+        pPsdHeaderAcpiTables->PkgOpcode     = PACKAGE_OPCODE;
+        pPsdHeaderAcpiTables->PsdLength     = PSD_HEADER_LENGTH;
+        pPsdHeaderAcpiTables->Value1        = PSD_VALUE1;
+        pPsdHeaderAcpiTables->PsdName_a__   = PSD_NAME__;
+        pPsdHeaderAcpiTables->PsdName_a_P   = PSD_NAME_P;
+        pPsdHeaderAcpiTables->PsdName_a_S   = PSD_NAME_S;
+        pPsdHeaderAcpiTables->PsdName_a_D   = PSD_NAME_D;
+
+        // Typecast the pointer
+        pPsdHeaderAcpiTables++;
+        CurrSize += PSD_HEADER_STRUCT_SIZE;
+        pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables;
+
+        pPsdHeaderAcpiTables--;
+        // Set _PSD Body
+        //--------------
+        pPsdBodyAcpiTables->PkgOpcode           = PACKAGE_OPCODE;
+        pPsdBodyAcpiTables->PkgLength           = PSD_PKG_LENGTH;
+        pPsdBodyAcpiTables->NumOfEntries        = NUM_OF_ENTRIES;
+        pPsdBodyAcpiTables->BytePrefixOpcode1   = BYTE_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->PsdNumOfEntries     = PSD_NUM_OF_ENTRIES;
+        pPsdBodyAcpiTables->BytePrefixOpcode2   = BYTE_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->PsdRevision         = PSD_REVISION;
+        pPsdBodyAcpiTables->DwordPrefixOpcode1  = DWORD_PREFIX_OPCODE;
+
+        IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader);
+
+        if (IsPsdDependent) {
+          pPsdBodyAcpiTables->DependencyDomain    = PSD_DEPENDENCY_DOMAIN;
+          pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_SW_ALL;
+          pPsdBodyAcpiTables->NumOfProcessors     = CoreCount1;
+        } else {
+          switch (GetComputeUnitMapping (StdHeader)) {
+          case AllCoresMapping:
+            // All cores are in their own compute unit.
+            pPsdBodyAcpiTables->DependencyDomain    = LocalApicId;
+            pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_SW_ANY;
+            pPsdBodyAcpiTables->NumOfProcessors     = PSD_NUM_OF_PROCESSORS;
+            break;
+          case EvenCoresMapping:
+            // Cores are paired in compute units.
+            pPsdBodyAcpiTables->DependencyDomain    = (LocalApicId >> 1) & PSD_DOMAIN_COMPUTE_UNIT_MASK;
+            pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_HW_ALL;
+            pPsdBodyAcpiTables->NumOfProcessors     = PSD_CORE_NUM_PER_COMPUTE_UNIT;
+            break;
+          default:
+            ASSERT (FALSE);
+          }
+        }
+        pPsdBodyAcpiTables->DwordPrefixOpcode2  = DWORD_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->DwordPrefixOpcode3  = DWORD_PREFIX_OPCODE;
+
+        pPsdBodyAcpiTables++;
+        *SsdtPtr = pPsdBodyAcpiTables;
+        CurrSize += PSD_BODY_STRUCT_SIZE;
+      }
+    }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd)
+    // Typecast the pointer
+
+    pPpcAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables;
+
+    // Set _PPC Table
+    //---------------
+    if (OptionPstateLateConfiguration.CfgPstatePpc) {
+      // Name (PPCV, value)
+      pPpcAcpiTables->NameOpcode            = NAME_OPCODE;
+      pPpcAcpiTables->PpcName_a_P           = PPC_NAME_P;
+      pPpcAcpiTables->PpcName_b_P           = PPC_NAME_P;
+      pPpcAcpiTables->PpcName_a_C           = PPC_NAME_C;
+      pPpcAcpiTables->PpcName_a_V           = PPC_NAME_V;
+      pPpcAcpiTables->Value1                = PPC_VALUE1;
+      pPpcAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport;
+      // Method (_PPC) { return (PPCV) }
+      pPpcAcpiTables->MethodOpcode          = METHOD_OPCODE;
+      pPpcAcpiTables->PpcLength             = PPC_METHOD_LENGTH;
+      pPpcAcpiTables->PpcName_a__           = PPC_NAME__;
+      pPpcAcpiTables->PpcName_c_P           = PPC_NAME_P;
+      pPpcAcpiTables->PpcName_d_P           = PPC_NAME_P;
+      pPpcAcpiTables->PpcName_b_C           = PPC_NAME_C;
+      pPpcAcpiTables->MethodFlags           = PPC_METHOD_FLAGS;
+      pPpcAcpiTables->ReturnOpcode          = RETURN_OPCODE;
+      pPpcAcpiTables->PpcName_e_P           = PPC_NAME_P;
+      pPpcAcpiTables->PpcName_f_P           = PPC_NAME_P;
+      pPpcAcpiTables->PpcName_c_C           = PPC_NAME_C;
+      pPpcAcpiTables->PpcName_b_V           = PPC_NAME_V;
+
+      CurrSize += PPC_HEADER_BODY_STRUCT_SIZE;
+      // Increment and typecast the pointer
+      pPpcAcpiTables++;
+      *SsdtPtr =  pPpcAcpiTables;
+    }// end of OptionPstateLateConfiguration.CfgPstatePpc
+  }
+  return CurrSize;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreateCStateAcpiTables
+ *
+ *  Description:
+ *     This is the common routine for creating ACPI C-State objects
+ *
+ *  Parameters:
+ *    @param[in]     PlatformConfig       Platform operational characteristics; power cap
+ *    @param[in]     PStateLevelingBuffer Buffer that contains P-State Leveling information
+ *    @param[in,out] SsdtPtr              ACPI SSDT table pointer
+ *    @param[in]     LocalApicId          Local Apic Id
+ *    @param[in]     StdHeader            Handle to config for library and services
+ *
+ *    @retval        Size of ACPI C-States objects generated
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+UINT32
+CreateCStateAcpiTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **SsdtPtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                    ObjSize;
+  IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices;
+
+  ObjSize = 0;
+
+  if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&IoCstateFamilyServices, StdHeader);
+    // If we're supporting multiple families, only proceed when IO Cstate family services are available
+    if (IoCstateFamilyServices != NULL) {
+      IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader);
+      ObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader);
+    }
+  }
+  return ObjSize;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
new file mode 100644
index 0000000000..09120fa5a6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
@@ -0,0 +1,357 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU Pstate Table Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU _PSS related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_PSTATE_TABLES_H_
+#define _CPU_PSTATE_TABLES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (PSTATE_CPU_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// P-state structure for each state
+typedef struct {
+  IN OUT   UINT32               PStateEnable;                ///< Pstate enable
+  IN OUT   UINT32               CoreFreq;                    ///< MHz
+  IN OUT   UINT32               Power;                       ///< milliWatts
+  IN OUT   UINT32               IddValue;                    ///< Current value field
+  IN OUT   UINT32               IddDiv;                      ///< Current divisor field
+  IN OUT   UINT32               SwPstateNumber;              ///< Software P-state number
+} S_PSTATE_VALUES;
+
+/// P-state structure for each core
+typedef struct {
+  IN OUT   UINT8                PStateMaxValue;              ///< Max p-state number in this core
+  IN OUT   UINT8                HtcPstateLimit;              ///< Htc limit
+  IN OUT   UINT8                HtcCapable;                  ///< Htc capable
+  IN OUT   UINT8                LocalApicId;                 ///< Local Apic Id
+  IN OUT   UINT8                NumberOfBoostedStates;       ///< Number of boost P-states
+  IN OUT   S_PSTATE_VALUES      PStateStruct[1];             ///< P state struc
+} S_PSTATE;
+
+/// P-state structure for each node
+typedef struct {
+  IN       UINT8                SetPState0;                  ///< If value = 0x55 (Don't set PState0)
+  IN       UINT8                TotalCoresInNode;            ///< core number per node
+  IN       UINT16               PStateLevelingSizeOfBytes;   ///< Size
+  IN       BOOLEAN              OnlyOneEnabledPState;        ///< Only P0
+  IN       UINT8                InitStruct;                  ///< Init struc
+  IN       BOOLEAN              AllCpusHaveIdenticalPStates; ///< Have Identical p state
+  IN       UINT8                CreateAcpiTables;            ///< Create table flag
+  IN       UINT8                SocketNumber;                ///< Physical socket number of this socket
+  IN       UINT8                Reserved[2];                 ///< Reserved.
+  IN OUT   S_PSTATE             PStateCoreStruct[1];         ///< P state core struc
+} PSTATE_LEVELING;
+
+/// P-state structure for whole system
+typedef struct {
+  IN OUT   UINT32               TotalSocketInSystem;         ///< Total node number in system
+  IN OUT   UINT32               SizeOfBytes;                 ///< Structure size
+  IN OUT   PSTATE_LEVELING      PStateLevelingStruc[1];      ///< P state level structure
+} S_CPU_AMD_PSTATE;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if PSD need to be generated.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD need to be generated
+ * @retval       FALSE              PSD does NOT need to be generated
+ *
+ */
+typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT;
+
+/**
+ *  Family specific call to set core TscFreqSel.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ */
+typedef VOID F_PSTATE_SET_TSC_FREQ_SEL (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL;
+
+/**
+ *  Family specific call to get CPU pstate transition latency for current socket.
+ *
+ *  @param[in]     PstateCpuFamilyServices        Pstate CPU services.
+ *  @param[in]     PStateLevelingBufferStructPtr  Pstate row data buffer pointer.
+ *  @param[in]     PciAddress                     Pci address struct.
+ *  @param[out]    TransitionLatency              Pstate Transition latency result.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_PSTATE_TRANSITION_LATENCY (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_PSTATE_TRANSITION_LATENCY *PF_CPU_PSTATE_TRANSITION_LATENCY;
+
+/**
+ *  Family specific call to get the desired P-state's frequency in megahertz.
+ *
+ *  @param[in]     PstateCpuFamilyServices Pstate CPU services.
+ *  @param[in]     StateNumber             P-state number.
+ *  @param[out]    PowerInMw               P-state frequency in megahertz.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_FREQ (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FreqInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_FREQ *PF_CPU_GET_PSTATE_FREQ;
+
+/**
+ *  Family specific call to set the system wide P-state settings on the current core.
+ *
+ *  @param[in]     PstateCpuFamilyServices Pstate CPU services.
+ *  @param[in]     CpuAmdPState            The current core's P-state data.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_SET_PSTATE_LEVELING_REG (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       S_CPU_AMD_PSTATE   *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_SET_PSTATE_LEVELING_REG *PF_CPU_SET_PSTATE_LEVELING_REG;
+
+/**
+ *  Family specific call to get the desired P-state's rated power in milliwatts.
+ *
+ *  @param[in]     PstateCpuFamilyServices Pstate CPU services.
+ *  @param[in]     StateNumber             P-state number.
+ *  @param[out]    PowerInMw               P-state power in milliwatts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_POWER (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_POWER *PF_CPU_GET_PSTATE_POWER;
+
+/**
+ *  Family specific call to get CPU Pstate Max State.
+ *
+ *  @param[in]     PstateCpuFamilyServices        Pstate CPU services.
+ *  @param[out]    MaxPStateNumber                The max hw pstate value on the current socket.
+ *  @param[out]    NumberOfBoostStates            The number of boosted P-states on the current socket.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_MAX_STATE (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+     OUT   UINT32              *MaxPStateNumber,
+     OUT   UINT8               *NumberOfBoostStates,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_MAX_STATE *PF_CPU_GET_PSTATE_MAX_STATE;
+
+/**
+ *  Family specific call to get CPU pstate register information.
+ *
+ *  @param[in]     PstateCpuFamilyServices        Pstate CPU services.
+ *  @param[in]     PState                         Input hardware Pstate number for query.
+ *  @param[out]    PStateEnabled                  Boolean flag return pstate enable.
+ *  @param[in,out] IddVal                         Pstate current value.
+ *  @param[in,out] IddDiv                         Pstate current divisor.
+ *  @param[out]    SwPstateNumber                 Software P-state number.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_REGISTER_INFO (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+     OUT   UINT32              *SwPstateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_REGISTER_INFO *PF_CPU_GET_PSTATE_REGISTER_INFO;
+
+/**
+ * Provide the interface to the Pstate dependent Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _PSTATE_CPU_FAMILY_SERVICES {
+  UINT16          Revision;                                         ///< Interface version
+  // Public Methods.
+  PF_PSTATE_PSD_IS_NEEDED IsPstatePsdNeeded;                        ///< Method: Family specific call to check if PSD need to be generated.
+  PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent;                  ///< Method: Family specific call to check if PSD is dependent.
+  PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel;                      ///< Method: Family specific call to set core TscFreqSel.
+  PF_CPU_PSTATE_TRANSITION_LATENCY GetPstateLatency;                ///< Method: Family specific call to get pstate transition latency.
+  PF_CPU_GET_PSTATE_FREQ GetPstateFrequency;                        ///< Method: Family specific call to get the desired P-state's frequency in megahertz.
+  PF_CPU_SET_PSTATE_LEVELING_REG SetPStateLevelReg;                 ///< Method: Family specific call to set the system wide P-state settings on the current core.
+  PF_CPU_GET_PSTATE_POWER GetPstatePower;                           ///< Method: Family specific call to get the desired P-state's rated power in milliwatts.
+  PF_CPU_GET_PSTATE_MAX_STATE GetPstateMaxState;                    ///< Method: Family specific call to get pstate max state number.
+  PF_CPU_GET_PSTATE_REGISTER_INFO GetPstateRegisterInfo;            ///< Method: Family specific call to get pstate register information.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PStateGatherData (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   S_CPU_AMD_PSTATE       *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+PStateLeveling (
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CpuGetPStateLevelStructure (
+     OUT   PSTATE_LEVELING     **PStateBufferPtr,
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       UINT32              LogicalSocketNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif  // _CPU_PSTATE_TABLES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c
new file mode 100644
index 0000000000..e26487d981
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c
@@ -0,0 +1,423 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD SLIT, ACPI table related API functions.
+ *
+ * Contains code that generates the SLIT table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SLIT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionSlit.h"
+#include "heapManager.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuL3Features.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration;  // global user config record
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuSlitHdrStruct =
+{
+  {'S','L','I','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'A','G','E','S','A',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+AcpiSlitHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     E X P O R T E D     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiSlitStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+
+AGESA_STATUS
+GetAcpiSlitMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+   );
+
+AGESA_STATUS
+ReleaseSlitBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+ReleaseSlitBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete SLIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiSlit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader);
+  return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the SLIT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiSlitStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete SLIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiSlitMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+   )
+{
+  UINT8 MaxHops;
+  UINT8 SocketNum;
+  UINT8 i;
+  UINT8 j;
+  UINT8 *BufferPtr;
+  UINT8 *SocketTopologyDataPtr;
+  UINT8 *SocketTopologyPtr;
+  UINT32 Socket;
+  BOOLEAN IsProbeFilterEnabled;
+  ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr;
+  AGESA_STATUS Flag;
+  ALLOCATE_HEAP_PARAMS AllocStruct;
+  L3_FEATURE_FAMILY_SERVICES *FamilyServices;
+
+  MaxHops = 0;
+  SocketTopologyPtr = NULL;
+  Flag = AGESA_ERROR;
+  IsProbeFilterEnabled = FALSE;
+
+  // find out the pointer to the BufferHandle which contains
+  // Node Topology information
+  AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr);
+  if (SocketTopologyPtr == NULL) {
+    return (Flag);
+  }
+
+  SocketNum = *SocketTopologyPtr;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  SLIT is created\n");
+
+  // create a buffer by calling IBV callout routine
+  AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER);
+  AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE;
+  AllocStruct.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) {
+    return (Flag);
+  }
+  *SlitPtr = AllocStruct.BufferPtr;
+
+  //SLIT header
+  LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+  CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr;
+  CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize;
+  BufferPtr = *SlitPtr;
+
+  Flag = AGESA_SUCCESS;
+  // SLIT body
+  // Check if Probe Filter is enabled
+  if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) {
+    IsProbeFilterEnabled = TRUE;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+        if ((FamilyServices == NULL) || (!FamilyServices->IsHtAssistSupported (FamilyServices, PlatformConfig, StdHeader))) {
+          IsProbeFilterEnabled = FALSE;
+          break;
+        }
+      }
+    }
+  }
+
+
+  if (!IsProbeFilterEnabled) {
+    // probe filter is disabled
+    // get MaxHops
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        if (*SocketTopologyDataPtr > MaxHops) {
+          MaxHops = *SocketTopologyDataPtr;
+        }
+        SocketTopologyDataPtr++;
+      }
+    }
+
+    // the Max hop entries have a value of 13
+    // and all other entries have 10.
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        if (*SocketTopologyDataPtr++ == MaxHops) {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13;
+        } else {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10;
+        }
+      }
+    }
+  } else {
+    // probe filter is enabled
+    // formula : num_hops * 6 + 10
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+          AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) =
+          ((*SocketTopologyDataPtr++) * 6) + 10;
+      }
+    }
+  }
+
+  BufferPtr += sizeof (ACPI_TABLE_HEADER);
+  *((UINT64 *) BufferPtr) = (UINT64) SocketNum;
+
+  //Update SLIT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader);
+
+  return (Flag);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Find out the pointer to the BufferHandle which contains
+ * Node Topology information
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in] SocketTopologyPtr      Point to the address of Socket Topology
+ *
+ */
+VOID
+STATIC
+AcpiSlitHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBuffer;
+
+  LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) {
+    *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr;
+  }
+
+  return;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseSlitBufferStub
+ *
+ *  Description:
+ *      This is the default routine for use when the SLIT option is NOT requested.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseSlitBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseSlitBuffer
+ *
+ *  Description:
+ *     Deallocate SLIT buffer
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseSlitBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader);
+
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
new file mode 100644
index 0000000000..6d87fbe2fa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
@@ -0,0 +1,643 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD SRAT, ACPI table related API functions.
+ *
+ * Contains code that Create the APCI SRAT Table after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ***************************************************************************/
+
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SRAT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "OptionSrat.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "cpuLateInit.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration;  // global user config record
+
+#define NodeID 0x60
+#define FOURGB 0x010000ul
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiSratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+
+AGESA_STATUS
+GetAcpiSratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *  All of the DATA should be defined in _CODE segment.
+ *  Use ROMDATA to specify that it belongs to _CODE.
+ *----------------------------------------------------------------------------
+ */
+STATIC CPU_SRAT_HEADER  ROMDATA CpuSratHdrStruct =
+{
+  {'S','R','A','T'},
+  0,
+  2,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'A','G','E','S','A',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1,
+  1,
+  {0, 0, 0, 0, 0, 0, 0, 0}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8
+STATIC
+*MakeApicEntry (
+  IN UINT8 ApicId,
+  IN UINT8 Domain,
+  IN UINT8 *BufferLocPtr
+  );
+
+UINT8
+STATIC
+*FillMemoryForCurrentNode (
+  IN      UINT8 *PDomain,
+  IN OUT  UINT8 *PDomainForBase640K,
+  IN      UINT8 Node,
+  IN OUT  UINT8 *BufferLocPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+STATIC
+*MakeMemEntry (
+  IN UINT8  PDomain,
+  IN UINT8  Node,
+  IN UINT32 Base,
+  IN UINT32 Size,
+  IN UINT8  *BufferLocPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Static Resource Affinity Table
+ * i.e. SRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+CreateAcpiSrat (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader);
+  return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the SRAT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiSratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Static Resource Affinity Table
+ * i.e. SRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiSratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  UINT8     *BufferPtr;
+  UINT8     NodeNum;
+  UINT8     NodeCount;
+  UINT8     PDomain;
+  UINT8     PDomainForBase640K;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    CoreNum;
+  UINT32    RegVal;
+  UINT32    tempVar_32;
+  AMD_APIC_PARAMS ApicParams;
+  PCI_ADDR  PciAddress;
+  CPU_SRAT_HEADER  *CpuSratHeaderStructPtr;
+  ALLOCATE_HEAP_PARAMS AllocParams;
+
+  // Get Node count
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID);
+  LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader);
+  NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1);
+
+  // The worst-case buffer size to request is for the SRAT table header, one
+  // entree for special region (base 640k block), two memory
+  // regions per node, and APIC entries for each core in the system.
+  tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY))
+               + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY))
+               + ((UINT32) GetActiveCoresInCurrentModule (StdHeader) * sizeof (CPU_SRAT_APIC_ENTRY))));
+
+  if (*SratPtr == NULL) {
+    //
+    // Allocate a buffer
+    //
+    AllocParams.RequestedBufferSize = tempVar_32;
+    AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE;
+    AllocParams.Persist = HEAP_SYSTEM_MEM;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader);
+    if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader);
+
+    *SratPtr = AllocParams.BufferPtr;
+  }
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  SRAT is created\n");
+
+  CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr;
+  BufferPtr = (UINT8 *) *SratPtr;
+
+  // Copy acpiSRATHeader -> data buffer
+  LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader);
+
+  BufferPtr += sizeof (CPU_SRAT_HEADER);
+
+  // Place all memory and IO affinity entries
+  NodeNum = 0;
+  PDomain = 0;
+  PDomainForBase640K = 0xFF;
+  ApicParams.StdHeader = *StdHeader;
+  while (NodeNum < NodeCount) {
+    GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader);
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader);
+    for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) {
+      ApicParams.Socket = (UINT8) Socket;
+      ApicParams.Core = (UINT8) CoreNum;
+      AmdGetApicId (&ApicParams);
+      if (ApicParams.IsPresent) {
+        BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr);
+      }
+    }
+
+    NodeNum++;
+    PDomain = NodeNum;
+  }
+
+  // Store size in table (current buffer offset - buffer start offset)
+  CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr);
+
+  //Update SSDT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *                            L O C A L    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will build Memory entry for current node.
+ * Note that we only create a memory affinity entry if we find one
+ * that matches the current node.  This makes an easier to read table
+ * though it is not necessary.
+ *
+ *    @param[in]      PDomain            Proximity Domain
+ *    @param[in, out] PDomainForBase640K The PDomain for Base 640K
+ *    @param[in]      Node               The number of Node
+ *    @param[in, out] BufferLocPtr       Point to the address of buffer
+ *    @param[in, out] StdHeader          Standard Head Pointer
+ *
+ *    @retval         UINT8 *(New buffer location ptr)
+ */
+UINT8
+STATIC
+*FillMemoryForCurrentNode (
+  IN      UINT8 *PDomain,
+  IN OUT  UINT8 *PDomainForBase640K,
+  IN      UINT8 Node,
+  IN OUT  UINT8 *BufferLocPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    ValueLimit;
+  UINT32    ValueTOM;
+  BOOLEAN   isModified;
+  UINT8     Domain;
+  UINT32    RegVal;
+  UINT32    DramLeng;
+  UINT32    DramBase;
+  UINT32    DramLimit;
+  UINT32    OffsetRegs;
+  PCI_ADDR  PciAddress;
+  UINT64    MsrValue;
+  UINT32    TopOfMemoryAbove4Gb;
+
+  Domain = *PDomain;
+
+  PciAddress.Address.Segment = 0;
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = LOW_NODE_DEVICEID;
+  PciAddress.Address.Function = FUNC_1;
+
+  for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) {
+    isModified = FALSE;        // FALSE means normal update procedure
+    // Get DRAM Base Address
+    PciAddress.Address.Register = OffsetRegs;
+    LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader);
+    if ((DramBase & 3) != 3) {
+      // 0:1 set if memory range enabled
+      // Not set, so we don't have an enabled range
+      continue;   // Proceed to next Base register
+    }
+
+    // Get DRAM Limit
+    PciAddress.Address.Register = OffsetRegs + 4;
+    LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader);
+    if (DramLimit == 0xFFFFFFFF) {
+      // Node not installed(all FF's)?
+      continue;   // Proceed to next Base register
+    }
+
+    if ((DramLimit & 0xFF) != Node) {
+      // Check if Destination Node ID is current node
+      continue;   // Proceed to next Base register
+    }
+
+    //    We only add an entry now if detected range belongs to current node/PDomain
+    PciAddress.Address.Register = OffsetRegs + 0x104;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
+
+    DramLimit = (((RegVal & 0xFF) << 16) | (DramLimit >> 16));  // Get DRAM Limit addr [47:24]
+    DramLimit++;                     // Add 1 for potential length
+    DramLimit <<= 8;
+
+    // Get DRAM Base Address
+    PciAddress.Address.Register = OffsetRegs + 0x100;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
+    DramBase = ((((RegVal & 0xFF) << 24) | (DramBase >> 8)) & 0xFFFFFF00);   // Get DRAM Base Base value [47:24]
+    DramLeng = DramLimit - DramBase;    // Subtract base from limit to get length
+
+    //    Leave hole for conventional memory (Less than 640K).  It must be on CPU 0.
+    if (DramBase == 0) {
+      if (*PDomainForBase640K == 0xFF) {
+        // It is the first time that the range start at 0.
+        // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K
+        BufferLocPtr = MakeMemEntry (
+                         Domain,
+                         Node,
+                         0,              // Base = 0
+                         0xA0000 >> 16,  // Put it into format used in DRAM regs..
+                         BufferLocPtr
+                         );
+        DramBase += 0x10;       // Add 1MB, so range = 1MB to Top of Region
+        DramLeng -= 0x10;       // Also subtract 1MB from the length
+        *PDomainForBase640K = Domain;        // Save Domain number for memory Less than 640K
+      } else {
+        // If No, there are more than one memory range less than 640K, it should that
+        // node interleaving is enabled. All nodes have the same memory ranges
+        // and all cores in these nodes belong to the same domain.
+        *PDomain = *PDomainForBase640K;
+        return (BufferLocPtr);
+      }
+    }
+    LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader);
+    ValueTOM   = (UINT32) MsrValue >> 16;    // Save it in 39:24 format
+    ValueLimit = DramBase + DramLeng;        // We need to know how large region is
+
+    LibAmdMsrRead (SYS_CFG, &MsrValue, StdHeader);
+    if ((MsrValue & BIT21) != 0) {
+      LibAmdMsrRead (TOP_MEM2, &MsrValue, StdHeader);
+      TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16);    // Save it in 47:16 format
+    } else {
+      TopOfMemoryAbove4Gb = 0xFFFFFFFF;
+    }
+
+    //  SPECIAL CASES:
+    //
+    //  Several conditions require that we process the values of the memory range differently.
+    //  Here are descriptions of the corner cases.
+    //
+    //  1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole).  For this case,
+    //     the range must be truncated to end at TOM.
+    //  *******************************            *******************************
+    //  *                    *        *      ->    *                             *
+    //  *******************************            *******************************
+    //  2                    TOM      4            2                             TOM
+    //
+    //  2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB.  This is handled by changing the
+    //     start base to 4GB.
+    //          ****************                        **********
+    //          *     *        *      ->                *        *
+    //          ****************                        **********
+    //  TOM     3.8   4        6            TOM   3.8   4        6
+    //
+    //  3. Memory range starts below TOM, ends above 4GB.  For this case, the range must be truncated
+    //     to end at TOM.  Note that this scenario creates two ranges, as the second comparison below
+    //     will find that it ends above 4GB since base and limit have been restored after first truncation,
+    //     and a second range will be written based at 4GB ending at original end address.
+    //  *******************************            ****************          **********
+    //  *              *     *        *      ->    *              *          *        *
+    //  *******************************            ****************          **********
+    //  2              TOM   4        6            2              TOM        4        6
+    //
+    //  4. Memory range starts above TOM, ends below or equal to 4GB.  This invalid range should simply
+    //     be ignored.
+    //          *******
+    //          *     *      ->    < NULL >
+    //          *******
+    //  TOM     3.8   4
+    //
+    //  5. Memory range starts below TOM2, and ends beyond TOM2.  This range must be truncated to TOM2.
+    //  ************************         *******************************
+    //  *              *       *   ->    *                             *
+    //  ************************         *******************************
+    //  768          TOM2   1024         768                        TOM2
+    //
+    //  6. Memory range starts above TOM2.  This invalid range should simply be ignored.
+    //          ********************
+    //          *                  *    ->    < NULL >
+    //          ********************
+    //  TOM2    1024            1280
+
+    if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM))
+        || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) {
+      //   TRUNCATE LOW!!! Shrink entry below TOM...
+      //   Base = DramBase, Size = TOM - DramBase
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) {
+      //   TRUNCATE HIGH!!! Shrink entry above 4GB...
+      //   Size = Base + Size - 4GB, Base = 4GB
+      BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) {
+      //   IGNORE!!!  Entry located entirely within memory hole
+      isModified = TRUE;
+    }
+
+    if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) {
+      //   Truncate to TOM2
+      //   Base = DramBase, Size = TOM2 - DramBase
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (TopOfMemoryAbove4Gb - DramBase), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if (DramBase >= TopOfMemoryAbove4Gb) {
+      //   IGNORE!!!  Entry located entirely above TOM2
+      isModified = TRUE;
+    }
+
+    //    If special range(isModified), we are done.
+    //    If not, finally write the memory entry.
+    if (isModified == FALSE) {
+      // Finally write the memory entry.
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr);
+    }
+
+  } // for ( OffsetRegs = DRAMBase0; ... )
+
+  return (BufferLocPtr);
+} // FillMemoryForCurrentNode()
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add APIC entry.
+ *
+ *    @param[in]      ApicId            APIC ID number
+ *    @param[in]      Domain            Domain number
+ *    @param[in]      BufferLocPtr      Point to the address of buffer
+ *
+ *    @retval         UINT8 *(New buffer location ptr)
+ */
+UINT8
+STATIC
+*MakeApicEntry (
+  IN      UINT8 ApicId,
+  IN      UINT8 Domain,
+  IN      UINT8 *BufferLocPtr
+  )
+{
+  CPU_SRAT_APIC_ENTRY *psSratApicEntry;
+  UINT8 ReservedBytes;
+
+  psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr;
+
+  psSratApicEntry->Type = AE_APIC;
+  psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY);
+  psSratApicEntry->Domain = Domain;
+  psSratApicEntry->ApicId = ApicId;
+  psSratApicEntry->Flags = ENABLED;
+  psSratApicEntry->LSApicEid = 0;
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) {
+    psSratApicEntry->Reserved[ReservedBytes] = 0;
+  }
+  return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY));
+} // MakeApicEntry
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will add Memory entry.
+ *
+ *  Parameters:
+ *    @param[in]  PDomain               Proximity Domain
+ *    @param[in]  Node                  The number of Node
+ *    @param[in]  Base                  Memory Base
+ *    @param[in]  Size                  Memory Size
+ *    @param[in]  BufferLocPtr          Point to the address of buffer
+ *
+ *    @retval       UINT8 * (new buffer location ptr)
+ */
+UINT8
+STATIC
+*MakeMemEntry (
+  IN  UINT8   PDomain,
+  IN  UINT8   Node,
+  IN  UINT32  Base,
+  IN  UINT32  Size,
+  IN  UINT8   *BufferLocPtr
+  )
+{
+  CPU_SRAT_MEMORY_ENTRY *psSratMemEntry;
+  UINT8 ReservedBytes;
+
+  psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr;
+
+  psSratMemEntry->Type = AE_MEMORY;                       // [0] = Memory Entry
+  psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40
+  psSratMemEntry->Domain = PDomain;                            // [2] = Proximity Domain
+
+  // [6-7] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) {
+    psSratMemEntry->Reserved1[ReservedBytes] = 0;
+  }
+
+  // [8-11] = Keep 31:0 of address only -> Base Addr Low
+  psSratMemEntry->BaseAddrLow  = Base << 16;
+
+  // [12-15] = Keep 39:32 of address only -> Base Addr High
+  psSratMemEntry->BaseAddrHigh = Base >> 16;
+
+  // [16-19] = Keep 31:0 of address only -> Length Low
+  psSratMemEntry->LengthAddrLow  = Size << 16;
+
+  // [20-23] = Keep 39:32 of address only -> Length High
+  psSratMemEntry->LengthAddrHigh = Size >> 16;
+
+  // [24-27] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) {
+    psSratMemEntry->Reserved2[ReservedBytes] = 0;
+  }
+
+  // [28-31] = Flags
+  psSratMemEntry->Flags = ENABLED;
+
+  // [32-40] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) {
+    psSratMemEntry->Reserved3[ReservedBytes] = 0;
+  }
+  return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
+} // MakeMemEntry()
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c
new file mode 100644
index 0000000000..87cd3b14a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c
@@ -0,0 +1,204 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU SW C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Topology.h"
+#include "cpuFeatures.h"
+#include "cpuSwC1e.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FEATURE_CPUSWC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should software C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               SW C1e is supported.
+ * @retval       FALSE              SW C1e not supported.
+ *
+ */
+BOOLEAN
+STATIC
+IsSwC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN                IsEnabled;
+  BOOLEAN                IsOtherC1eEnabled;
+  AP_MAILBOXES           ApMailboxes;
+  SW_C1E_FAMILY_SERVICES *SwFamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+  IsEnabled = FALSE;
+
+  // Check whether software C1e is enabled only if other C1e methods is/are not supported
+  // or if the platform specifically uses C1eModeSoftwareDeprecated.
+  IsOtherC1eEnabled = (IsFeatureEnabled (HardwareC1e, PlatformConfig, StdHeader) ||
+                       IsFeatureEnabled (MsgBasedC1e, PlatformConfig, StdHeader));
+  if ((PlatformConfig->C1eMode == C1eModeSoftwareDeprecated) ||
+     ((!IsOtherC1eEnabled) && ((PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || (PlatformConfig->C1eMode == C1eModeAuto)))) {
+    ASSERT ((PlatformConfig->C1ePlatformData1 < 0x10000) && (PlatformConfig->C1ePlatformData1 != 0));
+    ASSERT (PlatformConfig->C1ePlatformData2 < 0x100);
+    if ((PlatformConfig->C1ePlatformData1 != 0) && (PlatformConfig->C1ePlatformData1 < 0xFFFE) && (PlatformConfig->C1ePlatformData2 < 0xFF)) {
+      if (!IsNonCoherentHt1 (StdHeader)) {
+        if (GetNumberOfProcessors (StdHeader) == 1) {
+          GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+          if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
+            GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (CONST VOID **)&SwFamilyServices, StdHeader);
+            if (SwFamilyServices != NULL) {
+              IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader);
+            }
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Software C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeSwC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  SW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    SW C1e is enabled\n");
+
+  if (IsWarmReset (StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
+  }
+
+  return AgesaStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e =
+{
+  SoftwareC1e,
+  CPU_FEAT_AFTER_PM_INIT,
+  IsSwC1eFeatureEnabled,
+  InitializeSwC1eFeature
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h
new file mode 100644
index 0000000000..1316f7dddb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h
@@ -0,0 +1,146 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA CPU SW C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_SW_C1E_H_
+#define _CPU_SW_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES);
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if software C1e is supported.
+ *
+ * @param[in]    SwC1eServices      Software C1e services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               SW C1e is supported.
+ * @retval       FALSE              SW C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_SW_C1E_IS_SUPPORTED (
+  IN       SW_C1E_FAMILY_SERVICES *SwC1eServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method
+typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable software C1e.
+ *
+ * @param[in]    SwC1eServices      Software C1e services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_SW_C1E_INIT (
+  IN       SW_C1E_FAMILY_SERVICES *SwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method
+typedef F_SW_C1E_INIT *PF_SW_C1E_INIT;
+
+/**
+ * Provide the interface to the software C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _SW_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_SW_C1E_IS_SUPPORTED IsSwC1eSupported;                              ///< Method: Family specific call to check if software C1e is supported.
+  PF_SW_C1E_INIT InitializeSwC1e;                                       ///< Method: Family specific call to enable software C1e.
+};
+
+#endif  // _CPU_SW_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
new file mode 100644
index 0000000000..c2bb6aa94b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
@@ -0,0 +1,310 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD WHEA Table Creation API, and related functions.
+ *
+ * Contains code that produce the ACPI WHEA related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionWhea.h"
+#include "cpuLateInit.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+CreateHestBank (
+  IN       AMD_HEST_BANK *HestBankPtr,
+  IN       UINT8 BankNum,
+  IN       AMD_WHEA_INIT_DATA *WheaInitDataPtr
+  );
+
+AGESA_STATUS
+GetAcpiWheaStub (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+AGESA_STATUS
+GetAcpiWheaMain (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create the ACPI table of WHEA and return the pointer to the table.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiWhea (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader);
+  return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the WHEA option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiWheaStub (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create the ACPI tale of WHEA and return the pointer to the table.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiWheaMain (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  UINT8  BankNum;
+  UINT8  Entries;
+  UINT16 HestMceTableSize;
+  UINT16 HestCmcTableSize;
+  UINT64 MsrData;
+  AMD_HEST_MCE_TABLE *HestMceTablePtr;
+  AMD_HEST_CMC_TABLE *HestCmcTablePtr;
+  AMD_HEST_BANK *HestBankPtr;
+  AMD_WHEA_INIT_DATA *WheaInitDataPtr;
+  ALLOCATE_HEAP_PARAMS AllocParams;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  FamilySpecificServices = NULL;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  WHEA is created\n");
+
+  // step 1: calculate Hest table size
+  LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
+  BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count);
+  if (BankNum == 0) {
+    return AGESA_ERROR;
+  }
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (CONST VOID **) &WheaInitDataPtr, &Entries, StdHeader);
+
+  ASSERT (WheaInitDataPtr->HestBankNum <= BankNum);
+
+  HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK);
+  HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK);
+
+  HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr;
+  HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr;
+
+  // step 2: allocate a buffer by callback function
+  if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) {
+    AllocParams.RequestedBufferSize = (UINT32) (HestMceTableSize + HestCmcTableSize);
+    AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE;
+    AllocParams.Persist = HEAP_SYSTEM_MEM;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader);
+    if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader);
+
+    HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPtr;
+    HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK)));
+  }
+
+  // step 3: fill in Hest MCE table
+  HestMceTablePtr->TblLength = HestMceTableSize;
+  HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD;
+  HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD;
+  HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD;
+  HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD;
+  HestMceTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum;
+
+  HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1);
+  CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr);
+
+  // step 4: fill in Hest CMC table
+  HestCmcTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum;
+  HestCmcTablePtr->TblLength = HestCmcTableSize;
+
+  HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1);
+  CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr);
+
+  // step 5: fill in the incoming structure
+  *WheaMcePtr = HestMceTablePtr;
+  *WheaCmcPtr = HestCmcTablePtr;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create Bank structure for Hest table
+ *
+ *    @param[in]  HestBankPtr           Pointer to the Hest Back structure
+ *    @param[in]  BankNum               The number of Bank
+ *    @param[in]  WheaInitDataPtr     Pointer to the AMD_WHEA_INIT_DATA structure
+ *
+ */
+VOID
+STATIC
+CreateHestBank (
+  IN       AMD_HEST_BANK *HestBankPtr,
+  IN       UINT8 BankNum,
+  IN       AMD_WHEA_INIT_DATA *WheaInitDataPtr
+  )
+{
+  UINT8 BankIndex;
+  for (BankIndex = 0; BankIndex < BankNum; BankIndex++) {
+    HestBankPtr->BankNum = BankIndex;
+    HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit;
+    HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat;
+    HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn;
+    HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr;
+    HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD;
+    HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD;
+    HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr;
+    HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr;
+    HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr;
+    HestBankPtr++;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
new file mode 100644
index 0000000000..af00f26c8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
@@ -0,0 +1,1259 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * ACPI S3 Support routines
+ *
+ * Contains routines needed for supporting resume from the ACPI S3 sleep state.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_S3_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+SaveDeviceContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+SavePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  );
+
+VOID
+SaveConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  );
+
+VOID
+SaveMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  );
+
+VOID
+SaveConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  );
+
+VOID
+RestorePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  );
+
+VOID
+RestoreConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  );
+
+VOID
+RestoreMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  );
+
+VOID
+RestoreConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves all devices in the given device list.
+ *
+ * This traverses the entire device list twice.  In the first pass, we save
+ * all devices identified as Pre ESR.  In the second pass, we save devices
+ * marked as post ESR.
+ *
+ * @param[in]     DeviceList        Beginning of the device list to save.
+ * @param[in]     Storage           Beginning of the context buffer.
+ * @param[in]     CallPoint         Indicates whether this is AMD_INIT_RESUME or
+ *                                  AMD_S3LATE_RESTORE.
+ * @param[out]    ActualBufferSize  Actual size used in saving the device list.
+ * @param[in]     StdHeader         AMD standard header config param.
+ *
+ */
+VOID
+SaveDeviceListContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       VOID                *Storage,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // Copy device list over
+  LibAmdMemCopy (Storage,
+                 DeviceList,
+                 (UINTN) DeviceList->RelativeOrMaskOffset,
+                 StdHeader);
+  SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves all devices in the given device list.
+ *
+ * This traverses the entire device list twice.  In the first pass, we save
+ * all devices identified as Pre ESR.  In the second pass, we save devices
+ * marked as post ESR.
+ *
+ * @param[in,out] DeviceList        Beginning of the device list to save.
+ * @param[in]     CallPoint         Indicates whether this is AMD_INIT_RESUME or
+ *                                  AMD_S3LATE_RESTORE.
+ * @param[out]    ActualBufferSize  Actual size used in saving the device list.
+ * @param[in]     StdHeader         AMD standard header config param.
+ *
+ */
+VOID
+SaveDeviceContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  UINT64 StartAddress;
+  UINT64 EndAddress;
+  VOID *OrMask;
+
+  StartAddress = (UINT64)DeviceList;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
+
+  // Process Pre ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_PCI:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CPCI:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_MSR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CMSR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  // Process Post ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI:
+      SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_PCI_PRE_ESR:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI:
+      SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CPCI_PRE_ESR:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR:
+      SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_MSR_PRE_ESR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR:
+      SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CMSR_PRE_ESR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+  EndAddress = (UINT64) OrMask;
+  *ActualBufferSize = (UINT32) (EndAddress - StartAddress);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of a PCI device.
+ *
+ * This traverses the provided register list saving PCI registers.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SavePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  AndMask;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  PCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+    PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+    RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+    switch (RegSizeInBytes) {
+    case 1:
+      AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+      AccessWidth = AccessS3SaveWidth8;
+      break;
+    case 2:
+      AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+      AccessWidth = AccessS3SaveWidth16;
+      break;
+    case 3:
+      // In this case, we don't need to save a register. We just need to call a special
+      // function to do certain things in the save and resume sequence.
+      // This should not be used in a non-special case.
+      AndMask = 0;
+      RegSizeInBytes = 0;
+      AccessWidth = 0;
+      break;
+    default:
+      AndMask = RegisterHdr->RegisterList[i].AndMask;
+      RegSizeInBytes = 4;
+      AccessWidth = AccessS3SaveWidth32;
+      break;
+    }
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));
+      LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);
+    }
+    if (AndMask != 0) {
+      // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask
+      **((UINT32 **) OrMask) &= AndMask;
+    }
+    if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) {
+      // Restart from the beginning of the register list
+      i = 0xFFFF;
+    }
+    IntermediatePtr = (UINT8 *) *OrMask;
+    *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of a 'conditional' PCI device.
+ *
+ * This traverses the provided register list saving PCI registers when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SaveConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  AndMask;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+      PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+      RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+      switch (RegSizeInBytes) {
+      case 1:
+        AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+        AccessWidth = AccessS3SaveWidth8;
+        break;
+      case 2:
+        AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+        AccessWidth = AccessS3SaveWidth16;
+        break;
+      case 3:
+        // In this case, we don't need to save a register. We just need to call a special
+        // function to do certain things in the save and resume sequence.
+        // This should not be used in a non-special case.
+        AndMask = 0;
+        RegSizeInBytes = 0;
+        AccessWidth = 0;
+        break;
+      default:
+        AndMask = RegisterHdr->RegisterList[i].AndMask;
+        RegSizeInBytes = 4;
+        AccessWidth = AccessS3SaveWidth32;
+        break;
+      }
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));
+        LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);
+      }
+      if (AndMask != 0) {
+        // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask
+        **((UINT32 **) OrMask) &= AndMask;
+      }
+      if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) {
+        // Restart from the beginning of the register list
+        i = 0xFFFF;
+      }
+      IntermediatePtr = (UINT8 *) *OrMask;
+      *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of an MSR device.
+ *
+ * This traverses the provided register list saving MSRs.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SaveMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  MSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader);
+    }
+    **OrMask &= RegisterHdr->RegisterList[i].AndMask;
+    (*OrMask)++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of a 'conditional' MSR device.
+ *
+ * This traverses the provided register list saving MSRs when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SaveConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  CMSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader);
+      }
+      **OrMask &= RegisterHdr->RegisterList[i].AndMask;
+      (*OrMask)++;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the maximum amount of space required to store all raw register
+ * values for the given device list.
+ *
+ * This traverses the entire device list, and calculates the worst case size
+ * of each device in the device list.
+ *
+ * @param[in]     DeviceList     Beginning of the device list.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        Size in bytes required for storing all registers.
+ */
+UINT32
+GetWorstCaseContextSize (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 WorstCaseSize;
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  REGISTER_BLOCK_HEADERS RegisterHdr;
+
+  WorstCaseSize = DeviceList->RelativeOrMaskOffset;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+
+  // Process Device List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_PCI:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader);
+      } else {
+        S3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.PciRegisters->NumRegisters * 4);
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_CPCI:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader);
+      } else {
+        S3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.CPciRegisters->NumRegisters * 4);
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_MSR:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader);
+      } else {
+        S3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.MsrRegisters->NumRegisters * 8);
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_CMSR:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader);
+      } else {
+        S3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.CMsrRegisters->NumRegisters * 8);
+      Device.CMsrDevice++;
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+  }
+  return (WorstCaseSize);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores all devices marked as 'before exiting self-refresh.'
+ *
+ * This traverses the entire device list, restoring all devices identified
+ * as Pre ESR.
+ *
+ * @param[in,out] OrMaskPtr      Current buffer pointer of raw register values.
+ * @param[in]     Storage        Beginning of the device list.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ */
+VOID
+RestorePreESRContext (
+     OUT   VOID              **OrMaskPtr,
+  IN       VOID              *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  DEVICE_BLOCK_HEADER *DeviceList;
+
+  DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  *OrMaskPtr = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
+
+  // Process Pre ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_PCI:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CPCI:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_MSR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CMSR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores all devices marked as 'after exiting self-refresh.'
+ *
+ * This traverses the entire device list, restoring all devices identified
+ * as Post ESR.
+ *
+ * @param[in]     OrMaskPtr      Current buffer pointer of raw register values.
+ * @param[in]     Storage        Beginning of the device list.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ */
+VOID
+RestorePostESRContext (
+  IN       VOID              *OrMaskPtr,
+  IN       VOID              *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  DEVICE_BLOCK_HEADER *DeviceList;
+
+  DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+
+  // Process Pre ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI:
+      RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_PCI_PRE_ESR:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI:
+      RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CPCI_PRE_ESR:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR:
+      RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_MSR_PRE_ESR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR:
+      RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CMSR_PRE_ESR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of a PCI device.
+ *
+ * This traverses the provided register list restoring PCI registers.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestorePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  AndMask;
+  UINT32  RegValueRead;
+  UINT32  RegValueWrite;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  PCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+    PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+    RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+    switch (RegSizeInBytes) {
+    case 1:
+      AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+      RegValueWrite = **(UINT8 **)OrMask;
+      AccessWidth = AccessS3SaveWidth8;
+      break;
+    case 2:
+      AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+      RegValueWrite = **(UINT16 **)OrMask;
+      AccessWidth = AccessS3SaveWidth16;
+      break;
+    case 3:
+      // In this case, we don't need to restore a register. We just need to call a special
+      // function to do certain things in the save and resume sequence.
+      // This should not be used in a non-special case.
+      AndMask = 0;
+      RegValueWrite = 0;
+      RegSizeInBytes = 0;
+      AccessWidth = 0;
+      break;
+    default:
+      AndMask = RegisterHdr->RegisterList[i].AndMask;
+      RegSizeInBytes = 4;
+      RegValueWrite = **(UINT32 **)OrMask;
+      AccessWidth = AccessS3SaveWidth32;
+      break;
+    }
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));
+      LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);
+      RegValueWrite |= RegValueRead & (~AndMask);
+      LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      if (AndMask != 0) {
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,
+                                             PciAddress,
+                                             &RegValueRead,
+                                             StdHeader);
+        RegValueWrite |= RegValueRead & (~AndMask);
+      }
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,
+                                             PciAddress,
+                                             &RegValueWrite,
+                                             StdHeader);
+    }
+    IntermediatePtr = (UINT8 *) *OrMask;
+    *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
+    if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) {
+      // Restart from the beginning of the register list
+      i = 0xFFFF;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of a 'conditional' PCI device.
+ *
+ * This traverses the provided register list restoring PCI registers when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestoreConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  RegValueRead;
+  UINT32  RegValueWrite;
+  UINT32  AndMask;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+      PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+      RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+      switch (RegSizeInBytes) {
+      case 1:
+        AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+        RegValueWrite = **(UINT8 **)OrMask;
+        AccessWidth = AccessS3SaveWidth8;
+        break;
+      case 2:
+        AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+        RegValueWrite = **(UINT16 **)OrMask;
+        AccessWidth = AccessS3SaveWidth16;
+        break;
+      case 3:
+        // In this case, we don't need to restore a register. We just need to call a special
+        //  function to do certain things in the save and resume sequence.
+        // This should not be used in a non-special case.
+        AndMask = 0;
+        RegValueWrite = 0;
+        RegSizeInBytes = 0;
+        AccessWidth = 0;
+        break;
+      default:
+        AndMask = RegisterHdr->RegisterList[i].AndMask;
+        RegSizeInBytes = 4;
+        RegValueWrite = **(UINT32 **)OrMask;
+        AccessWidth = AccessS3SaveWidth32;
+        break;
+      }
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);
+        RegValueWrite |= RegValueRead & (~AndMask);
+        LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        if (AndMask != 0) {
+          RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,
+                                             PciAddress,
+                                             &RegValueRead,
+                                             StdHeader);
+          RegValueWrite |= RegValueRead & (~AndMask);
+        }
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,
+                                               PciAddress,
+                                               &RegValueWrite,
+                                               StdHeader);
+      }
+      IntermediatePtr = (UINT8 *) *OrMask;
+      *OrMask = &IntermediatePtr[RegSizeInBytes];
+      if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) {
+        // Restart from the beginning of the register list
+        i = 0xFFFF;
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of an MSR device.
+ *
+ * This traverses the provided register list restoring MSRs.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestoreMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  UINT64  RegValueRead;
+  UINT64  RegValueWrite;
+  MSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    RegValueWrite = **OrMask;
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader);
+      RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+      LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address,
+                                                           &RegValueRead,
+                                                           StdHeader);
+      RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address,
+                                                           &RegValueWrite,
+                                                           StdHeader);
+    }
+    (*OrMask)++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of a 'conditional' MSR device.
+ *
+ * This traverses the provided register list restoring MSRs when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestoreConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  UINT64  RegValueRead;
+  UINT64  RegValueWrite;
+  CMSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      RegValueWrite = **OrMask;
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader);
+        RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+        LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address,
+                                                           &RegValueRead,
+                                                           StdHeader);
+        RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address,
+                                                             &RegValueWrite,
+                                                             StdHeader);
+      }
+      (*OrMask)++;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to PCI register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[out]   NonMemoryRelatedDeviceList  List of devices to save and restore
+ *                                           during S3LateRestore.
+ * @param[in]    StdHeader                   AMD standard header config param.
+ *
+ */
+VOID
+GetNonMemoryRelatedDeviceList (
+     OUT   DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  *NonMemoryRelatedDeviceList = NULL;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to PCI register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output PCI register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to 'conditional' PCI register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output 'conditional' PCI register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to MSR register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output MSR register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to 'conditional' MSR register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output 'conditional' MSR register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3_PARAMS structure.
+ *
+ * This routine initializes failsafe values for the AMD_S3_PARAMS structure
+ * to be used by the AMD_INIT_RESUME, AMD_S3_SAVE, and AMD_S3LATE_RESTORE
+ * entry points.
+ *
+ * @param[in,out] S3Params       Required input parameter for the AMD_S3_SAVE,
+ *                               AMD_INIT_RESUME, and AMD_S3_SAVE entry points.
+ *
+ */
+VOID
+AmdS3ParamsInitializer (
+  OUT   AMD_S3_PARAMS *S3Params
+  )
+{
+  S3Params->Signature = 0x52545341;
+  S3Params->Version = 0x0000;
+  S3Params->VolatileStorage = NULL;
+  S3Params->VolatileStorageSize = 0x00000000;
+  S3Params->Flags = 0x00000000;
+  S3Params->NvStorage = NULL;
+  S3Params->NvStorageSize = 0x00000000;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h
new file mode 100644
index 0000000000..09f5f4660c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h
@@ -0,0 +1,421 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  ACPI S3 support definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _S3_H_
+#define _S3_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define RESTART_FROM_BEGINNING_LIST 0xFFFFFFFFul
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* Device related definitions */
+
+/// Header at the beginning of a context save buffer.
+typedef struct {
+  UINT16     Version;                 ///< Version of header
+  UINT16     NumDevices;              ///< Number of devices in the list
+  UINT16     RelativeOrMaskOffset;    ///< Size of device list + header
+} DEVICE_BLOCK_HEADER;
+
+/// S3 device types
+typedef enum {
+  DEV_TYPE_PCI_PRE_ESR,               ///< PCI device before exiting self-refresh
+  DEV_TYPE_PCI,                       ///< PCI device after exiting self-refresh
+  DEV_TYPE_CPCI_PRE_ESR,              ///< 'conditional' PCI device before exiting self-refresh
+  DEV_TYPE_CPCI,                      ///< 'conditional' PCI device after exiting self-refresh
+  DEV_TYPE_MSR_PRE_ESR,               ///< MSR device before exiting self-refresh
+  DEV_TYPE_MSR,                       ///< MSR device after exiting self-refresh
+  DEV_TYPE_CMSR_PRE_ESR,              ///< 'conditional' MSR device before exiting self-refresh
+  DEV_TYPE_CMSR                       ///< 'conditional' MSR device after exiting self-refresh
+} S3_DEVICE_TYPES;
+
+/// S3 restoration call points
+typedef enum {
+  INIT_RESUME,                        ///< AMD_INIT_RESUME
+  S3_LATE_RESTORE                     ///< AMD_S3LATE_RESTORE
+} CALL_POINTS;
+
+/// S3 device common header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< Appropriate S3_DEVICE_TYPES type
+} DEVICE_DESCRIPTOR;
+
+/// S3 PCI device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR
+  UINT8      Node;                    ///< Zero-based node number
+} PCI_DEVICE_DESCRIPTOR;
+
+/// S3 'conditional' PCI device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR
+  UINT8      Node;                    ///< Zero-based node number
+  UINT8      Mask1;                   ///< Conditional mask 1
+  UINT8      Mask2;                   ///< Conditional mask 2
+} CONDITIONAL_PCI_DEVICE_DESCRIPTOR;
+
+/// S3 MSR device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR
+} MSR_DEVICE_DESCRIPTOR;
+
+/// S3 'conditional' MSR device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR
+  UINT8      Mask1;                   ///< Conditional mask 1
+  UINT8      Mask2;                   ///< Conditional mask 2
+} CONDITIONAL_MSR_DEVICE_DESCRIPTOR;
+
+/* Special case related definitions */
+
+/**
+ * PCI special case save handler
+ *
+ * @param[in]     AccessWidth   8, 16, or 32 bit wide access
+ * @param[in]     Address       full PCI address of the register to save
+ * @param[out]    Value         Value read from the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR     Address,
+     OUT   VOID         *Value,
+  IN       VOID         *ConfigPtr
+  );
+
+/**
+ * PCI special case restore handler
+ *
+ * @param[in]     AccessWidth   8, 16, or 32 bit wide access
+ * @param[in]     Address       full PCI address of the register to save
+ * @param[in]     Value         Value to write to the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) (
+  IN       ACCESS_WIDTH       AccessWidth,
+  IN       PCI_ADDR           PciAddress,
+  IN       VOID               *Value,
+  IN       VOID               *StdHeader
+  );
+
+/**
+ * MSR special case save handler
+ *
+ * @param[in]     MsrAddress    Address of model specific register to save
+ * @param[out]    Value         Value read from the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) (
+  IN       UINT32             MsrAddress,
+     OUT   UINT64             *Value,
+  IN       VOID               *StdHeader
+  );
+
+/**
+ * MSR special case restore handler
+ *
+ * @param[in]     MsrAddress    Address of model specific register to restore
+ * @param[in]     Value         Value to write to the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) (
+  IN       UINT32             MsrAddress,
+  IN       UINT64             *Value,
+  IN       VOID               *StdHeader
+  );
+
+/// PCI special case save/restore structure.
+typedef struct {
+  PF_S3_SPECIAL_PCI_SAVE     Save;    ///< Save routine
+  PF_S3_SPECIAL_PCI_RESTORE  Restore; ///< Restore routine
+} PCI_SPECIAL_CASE;
+
+/// MSR special case save/restore structure.
+typedef struct {
+  PF_S3_SPECIAL_MSR_SAVE     Save;    ///< Save routine
+  PF_S3_SPECIAL_MSR_RESTORE  Restore; ///< Restore routine
+} MSR_SPECIAL_CASE;
+
+/* Register related definitions */
+/// S3 register type bit fields
+typedef struct {
+  UINT8      SpecialCaseIndex:4;      ///< Special Case array index
+  UINT8      RegisterSize:3;          ///< For PCI, 1 = byte, 2 = word, else = dword.
+                                      ///< For MSR, don't care
+  UINT8      SpecialCaseFlag:1;       ///< Indicates special case
+} S3_REGISTER_TYPE;
+
+/// S3 PCI register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = register size in bytes,
+                                      ///< Type[2:0] = special case index
+  UINT8             Function;         ///< PCI function of the register
+  UINT16            Offset;           ///< PCI offset of the register
+  UINT32            AndMask;          ///< AND mask to be applied to the value before saving
+} PCI_REG_DESCRIPTOR;
+
+/// S3 'conditional' PCI register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = register size in bytes,
+                                      ///< Type[2:0] = special case index
+  UINT8             Function;         ///< PCI function of the register
+  UINT16            Offset;           ///< PCI offset of the register
+  UINT32            AndMask;          ///< AND mask to be applied to the value before saving
+  UINT8             Mask1;            ///< conditional mask 1
+  UINT8             Mask2;            ///< conditional mask 2
+} CONDITIONAL_PCI_REG_DESCRIPTOR;
+
+/// S3 MSR register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = reserved,
+                                      ///< Type[2:0] = special case index
+  UINT32            Address;          ///< MSR address
+  UINT64            AndMask;          ///< AND mask to be applied to the value before saving
+} MSR_REG_DESCRIPTOR;
+
+/// S3 'conditional' MSR register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = reserved,
+                                      ///< Type[2:0] = special case index
+  UINT32            Address;          ///< MSR address
+  UINT64            AndMask;          ///< AND mask to be applied to the value before saving
+  UINT8             Mask1;            ///< conditional mask 1
+  UINT8             Mask2;            ///< conditional mask 2
+} CONDITIONAL_MSR_REG_DESCRIPTOR;
+
+/// Common header at the beginning of an S3 register list.
+typedef struct {
+  UINT16     Version;                 ///< Version of header
+  UINT16     NumRegisters;            ///< Number of registers in the list
+} REGISTER_BLOCK_HEADER;
+
+/// S3 PCI register list header.
+typedef struct {
+  UINT16                  Version;       ///< Version of header
+  UINT16                  NumRegisters;  ///< Number of registers in the list
+  PCI_REG_DESCRIPTOR      *RegisterList; ///< Pointer to the first register descriptor
+  PCI_SPECIAL_CASE        *SpecialCases; ///< Pointer to array of special case handlers
+} PCI_REGISTER_BLOCK_HEADER;
+
+/// S3 'conditional' PCI register list header.
+typedef struct {
+  UINT16                          Version;       ///< Version of header
+  UINT16                          NumRegisters;  ///< Number of registers in the list
+  CONDITIONAL_PCI_REG_DESCRIPTOR  *RegisterList; ///< Pointer to the first register descriptor
+  PCI_SPECIAL_CASE                *SpecialCases; ///< Pointer to array of special case handlers
+} CPCI_REGISTER_BLOCK_HEADER;
+
+/// S3 MSR register list header.
+typedef struct {
+  UINT16                 Version;       ///< Version of header
+  UINT16                 NumRegisters;  ///< Number of registers in the list
+  MSR_REG_DESCRIPTOR     *RegisterList; ///< Pointer to the first register descriptor
+  MSR_SPECIAL_CASE       *SpecialCases; ///< Pointer to array of special case handlers
+} MSR_REGISTER_BLOCK_HEADER;
+
+/// S3 'conditional' MSR register list header.
+typedef struct {
+  UINT16                          Version;       ///< Version of header
+  UINT16                          NumRegisters;  ///< Number of registers in the list
+  CONDITIONAL_MSR_REG_DESCRIPTOR  *RegisterList; ///< Pointer to the first register descriptor
+  MSR_SPECIAL_CASE                *SpecialCases; ///< Pointer to array of special case handlers
+} CMSR_REGISTER_BLOCK_HEADER;
+
+/// S3 device descriptor pointers for ease of proper pointer advancement.
+typedef union {
+  DEVICE_DESCRIPTOR *CommonDeviceHeader;         ///< Common header
+  PCI_DEVICE_DESCRIPTOR *PciDevice;              ///< PCI header
+  CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header
+  MSR_DEVICE_DESCRIPTOR *MsrDevice;              ///< MSR header
+  CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header
+} DEVICE_DESCRIPTORS;
+
+/// S3 register list header pointers for ease of proper pointer advancement.
+typedef union {
+  DEVICE_DESCRIPTOR          *CommonDeviceHeader; ///< Common header
+  PCI_REGISTER_BLOCK_HEADER  *PciRegisters;       ///< PCI header
+  CPCI_REGISTER_BLOCK_HEADER *CPciRegisters;      ///< 'conditional' PCI header
+  MSR_REGISTER_BLOCK_HEADER  *MsrRegisters;       ///< MSR header
+  CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters;      ///< 'conditional' MSR header
+} REGISTER_BLOCK_HEADERS;
+
+/// S3 Volatile Storage Header
+typedef struct {
+  UINT32  HeapOffset;                             ///< Offset to beginning of heap data
+  UINT32  HeapSize;                               ///< Size of the heap data
+  UINT32  RegisterDataOffset;                     ///< Offset to beginning of raw save data
+  UINT32  RegisterDataSize;                       ///< Size of raw save data
+} S3_VOLATILE_STORAGE_HEADER;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+GetWorstCaseContextSize (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+SaveDeviceListContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       VOID                *Storage,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+RestorePreESRContext (
+     OUT   VOID **OrMaskPtr,
+  IN       VOID *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+RestorePostESRContext (
+  IN       VOID *OrMaskPtr,
+  IN       VOID *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdS3ParamsInitializer (
+     OUT   AMD_S3_PARAMS *S3Params
+  );
+
+VOID
+GetNonMemoryRelatedDeviceList (
+     OUT   DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+S3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+AGESA_STATUS
+S3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+S3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+
+#endif  // _S3_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c
new file mode 100644
index 0000000000..1293159b37
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c
@@ -0,0 +1,919 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Set registers according to a set of register tables
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Table.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "CommonReturns.h"
+#include "cpuL3Features.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_TABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+SetRegistersFromTablesAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * An iterator for all the Family and Model Register Tables.
+ *
+ * RegisterTableHandle should be set to NULL to begin iteration, the first time the method is
+ * invoked.  Register tables can be processed, until this method returns NULL.  RegisterTableHandle
+ * should simply be passed back to the method without modification or use by the caller.
+ * The table selector allows the relevant tables for different cores to be iterated, if the family separates
+ * tables.  For example, MSRs can be in a table processed by all cores and PCI registers in a table processed by
+ * primary cores.
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     Selector                Select whether to iterate over tables for either all cores, primary cores, bsp, ....
+ * @param[in,out] RegisterTableHandle     IN: The handle of the current register table, or NULL if Begin.
+ *                                        OUT: The handle of the next register table, if not End.
+ * @param[out]    NumberOfEntries         The number of entries in the table returned, if not End.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @return        The pointer to the next Register Table, or NULL if End.
+ */
+TABLE_ENTRY_FIELDS
+STATIC
+*GetNextRegisterTable (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       TABLE_CORE_SELECTOR     Selector,
+  IN OUT   REGISTER_TABLE       ***RegisterTableHandle,
+     OUT   UINTN                  *NumberOfEntries,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  REGISTER_TABLE **NextTable;
+  TABLE_ENTRY_FIELDS *Entries;
+
+  ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL));
+  ASSERT (Selector < TableCoreSelectorMax);
+
+  NextTable = *RegisterTableHandle;
+  if (NextTable == NULL) {
+    // Begin
+    NextTable = FamilySpecificServices->RegisterTableList;
+    IDS_OPTION_HOOK (IDS_TRAP_TABLE, &NextTable, StdHeader);
+  } else {
+    NextTable++;
+  }
+  // skip if not selected
+  while ((*NextTable != NULL) && (*NextTable)->Selector != Selector) {
+    NextTable++;
+  }
+  if (*NextTable == NULL) {
+    // End
+    *RegisterTableHandle = NULL;
+    Entries = NULL;
+  } else {
+    // Iterate next table
+    *RegisterTableHandle = NextTable;
+    *NumberOfEntries = (*NextTable)->NumberOfEntries;
+    Entries = (TABLE_ENTRY_FIELDS *) (*NextTable)->Table;
+  }
+  return Entries;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Compare counts to a pair of ranges.
+ *
+ * @param[in]       FirstCount       The actual count to be compared to the first range.
+ * @param[in]       SecondCount      The actual count to be compared to the second range.
+ * @param[in]       Ranges           The ranges which the counts are compared to.
+ *
+ * @retval          TRUE             Either one, or both, of the counts is in the range given.
+ * @retval          FALSE            Neither count is in the range given.
+ */
+BOOLEAN
+IsEitherCountInRange (
+  IN       UINTN                FirstCount,
+  IN       UINTN                SecondCount,
+  IN       COUNT_RANGE_FEATURE  Ranges
+  )
+{
+  // Errors: Entire Range value is zero, Min and Max reversed or not <=, ranges overlap (OK if first range is all),
+  // the real counts are too big.
+  ASSERT ((Ranges.Range0Min <= Ranges.Range0Max) &&
+          (Ranges.Range1Min <= Ranges.Range1Max) &&
+          (Ranges.Range0Max != 0) &&
+          (Ranges.Range1Max != 0) &&
+          ((Ranges.Range0Max == COUNT_RANGE_HIGH) || (Ranges.Range0Max < Ranges.Range1Min)) &&
+          ((FirstCount < COUNT_RANGE_HIGH) && (SecondCount < COUNT_RANGE_HIGH)));
+
+  return (BOOLEAN) (((FirstCount <= Ranges.Range0Max) && (FirstCount >= Ranges.Range0Min)) ||
+                   ((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
+}
+
+/*-------------------------------------------------------------------------------------*/
+/**
+ * Returns the performance profile features list of the currently running processor core.
+ *
+ * @param[out]      Features          The performance profile features supported by this platform
+ * @param[in]       PlatformConfig    Config handle for platform specific information
+ * @param[in]       StdHeader         Header for library and services
+ *
+ */
+VOID
+GetPerformanceFeatures (
+     OUT   PERFORMANCE_PROFILE_FEATS    *Features,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  L3_FEATURE_FAMILY_SERVICES *FeatureFamilyServices;
+
+  Features->PerformanceProfileValue = 0;
+  // Reflect Probe Filter Configuration.
+  Features->PerformanceProfileFeatures.ProbeFilter = 0;
+  if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FeatureFamilyServices, StdHeader);
+    if ((FeatureFamilyServices != NULL) &&
+        (FeatureFamilyServices->IsHtAssistSupported (FeatureFamilyServices, PlatformConfig, StdHeader))) {
+      Features->PerformanceProfileFeatures.ProbeFilter = 1;
+    }
+  }
+
+  // Reflect Display Refresh Requests use 32 bytes Configuration.
+  Features->PerformanceProfileFeatures.RefreshRequest32Byte = 0;
+  if (PlatformConfig->PlatformProfile.Use32ByteRefresh) {
+    Features->PerformanceProfileFeatures.RefreshRequest32Byte = 1;
+  }
+  // Reflect Mct Isoc Read Priority set to variable Configuration.
+  Features->PerformanceProfileFeatures.MctIsocVariable = 0;
+  if (PlatformConfig->PlatformProfile.UseVariableMctIsocPriority) {
+    Features->PerformanceProfileFeatures.MctIsocVariable = 1;
+  }
+  // Indicate if this boot is a warm reset.
+  Features->PerformanceProfileFeatures.IsWarmReset = 0;
+  if (IsWarmReset (StdHeader)) {
+    Features->PerformanceProfileFeatures.IsWarmReset = 1;
+  }
+
+  // Get L3 Cache present as indicated by CPUID
+  Features->PerformanceProfileFeatures.L3Cache = 0;
+  Features->PerformanceProfileFeatures.NoL3Cache = 1;
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuidDataStruct, StdHeader);
+  if (((CpuidDataStruct.EDX_Reg & 0xFFFC0000) >> 18) != 0) {
+    Features->PerformanceProfileFeatures.L3Cache = 1;
+    Features->PerformanceProfileFeatures.NoL3Cache = 0;
+  }
+
+  // Get VRM select high speed from build option.
+  Features->PerformanceProfileFeatures.VrmHighSpeed = 0;
+  if (PlatformConfig->VrmProperties[CoreVrm].HiSpeedEnable) {
+    Features->PerformanceProfileFeatures.VrmHighSpeed = 1;
+  }
+
+  // Get some family, model specific performance type info.
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+
+  // Is the Northbridge P-State feature enabled
+  Features->PerformanceProfileFeatures.NbPstates = 0;
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
+    Features->PerformanceProfileFeatures.NbPstates = 1;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the MSR Register Entry.
+ *
+ * @TableEntryTypeMethod{::MsrRegister}.
+ *
+ * Read - Modify - Write the MSR, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The MSR register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForMsrEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64          MsrData;
+
+  // Even for only single bit fields, use those in the mask.  "Mask nothing" is a bug, even if just by policy.
+  ASSERT (Entry->MsrEntry.Mask != 0);
+
+  LibAmdMsrRead (Entry->MsrEntry.Address, &MsrData, StdHeader);
+  MsrData = MsrData & (~(Entry->MsrEntry.Mask));
+  MsrData = MsrData | Entry->MsrEntry.Data;
+  LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::PciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32          TempVar32_a;
+  UINT32          MySocket;
+  UINT32          MyModule;
+  UINT32          Ignored;
+  PCI_ADDR        MyPciAddress;
+  AGESA_STATUS    IgnoredSts;
+  TABLE_ENTRY_DATA  PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  // Even for only single bit fields, use those in the mask.  "Mask nothing" is a bug, even if just by policy.
+  ASSERT ((Entry->InitialValues[4] == 0) &&
+          (Entry->InitialValues[3] == 0) &&
+          (Entry->PciEntry.Mask != 0));
+
+  LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+  PciEntry.PciEntry = Entry->PciEntry;
+
+  IDS_OPTION_HOOK (IDS_SET_PCI_REGISTER_ENTRY, &PciEntry, StdHeader);
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, MySocket, MyModule, &MyPciAddress, &IgnoredSts);
+  MyPciAddress.Address.Function = PciEntry.PciEntry.Address.Address.Function;
+  MyPciAddress.Address.Register = PciEntry.PciEntry.Address.Address.Register;
+  LibAmdPciRead (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
+  TempVar32_a = TempVar32_a & (~(PciEntry.PciEntry.Mask));
+  TempVar32_a = TempVar32_a | PciEntry.PciEntry.Data;
+  LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Family Specific Workaround Register Entry.
+ *
+ * @TableEntryTypeMethod{::FamSpecificWorkaround}.
+ *
+ * Call the function, passing the data.
+ *
+ * See if you can use the other entries or make an entry that covers the fix.
+ * After all, the purpose of having a table entry is to @b NOT have code which
+ * isn't generic feature code, but is family/model code specific to one case.
+ *
+ * @param[in]     Entry             The Family Specific Workaround register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForFamSpecificWorkaroundEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  ASSERT (Entry->FamSpecificEntry.DoAction != NULL);
+
+  Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Performance Profile PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::ProfileFixup}.
+ *
+ * Check the entry's performance profile features to the platform's and do the
+ * PCI register entry if they match.
+ *
+ * @param[in]     Entry             The Performance Profile register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForPerformanceProfileEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->InitialValues[4] == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                      Entry->FixupEntry.TypeFeats.PerformanceProfileValue)) {
+    LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+    PciEntry.PciEntry = Entry->FixupEntry.PciEntry;
+    SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Core Counts Performance PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::CoreCountsPciRegister}.
+ *
+ * Check the performance profile.
+ * Check the actual core count to the range pair given, and apply if matched.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForCoreCountsPerformanceEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN ActualCoreCount;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue)) {
+    ActualCoreCount = GetActiveCoresInCurrentModule (StdHeader);
+    // Check if the actual core count is in either range.
+    if (IsEitherCountInRange (ActualCoreCount, ActualCoreCount, Entry->CoreCountEntry.CoreCounts.CoreRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->CoreCountEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Processor Counts PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::ProcCountsPciRegister}.
+ *
+ * Check the performance profile.
+ * Check the actual processor count (not node count!) to the range pair given, and apply if matched.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForProcessorCountsEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN ProcessorCount;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue)) {
+    ProcessorCount = GetNumberOfProcessors (StdHeader);
+    // Check if the actual processor count is in either range.
+    if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->ProcCountEntry.ProcessorCounts.ProcessorCountRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Compute Unit Counts PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::CompUnitCountsPciRegister}.
+ *
+ * Check the entry's performance profile features and the compute unit count
+ * to the platform's and do the PCI register entry if they match.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForComputeUnitCountsEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN ComputeUnitCount;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue)) {
+    ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader);
+    // Check if the actual compute unit count is in either range.
+    if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountEntry.ComputeUnitCounts.ComputeUnitRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->CompUnitCountEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Compute Unit Counts MSR Register Entry.
+ *
+ * @TableEntryTypeMethod{::CompUnitCountsMsr}.
+ *
+ * Check the entry's compute unit count to the platform's and do the
+ * MSR entry if they match.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetMsrForComputeUnitCountsEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN ComputeUnitCount;
+  TABLE_ENTRY_DATA          MsrEntry;
+
+  ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader);
+  // Check if the actual compute unit count is in either range.
+  if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountMsrEntry.ComputeUnitCounts.ComputeUnitRanges)) {
+    LibAmdMemFill (&MsrEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+    MsrEntry.MsrEntry = Entry->CompUnitCountMsrEntry.MsrEntry;
+    SetRegisterForMsrEntry (&MsrEntry, PlatformConfig, StdHeader);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ * Returns the platform features list of the currently running processor core.
+ *
+ * @param[out]      Features          The Features supported by this platform
+ * @param[in]       PlatformConfig    Config handle for platform specific information
+ * @param[in]       StdHeader         Header for library and services
+ *
+ */
+VOID
+GetPlatformFeatures (
+     OUT   PLATFORM_FEATS         *Features,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    CapabilityReg;
+  UINT32     Link;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  UINT32     CoreCount;
+
+  // Start with none.
+  Features->PlatformValue = 0;
+
+  switch (PlatformConfig->PlatformProfile.PlatformControlFlowMode) {
+  case Nfcm:
+    Features->PlatformFeatures.PlatformNfcm = 1;
+    break;
+  case UmaDr:
+    Features->PlatformFeatures.PlatformUma = 1;
+    break;
+  case UmaIfcm:
+    Features->PlatformFeatures.PlatformUmaIfcm = 1;
+    break;
+  case Ifcm:
+    Features->PlatformFeatures.PlatformIfcm = 1;
+    break;
+  case Iommu:
+    Features->PlatformFeatures.PlatformIommu = 1;
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  // Check - Single Link?
+  // This is based on the implemented links on the package regardless of their
+  // connection status.  All processors must match the BSP, so we only check it and
+  // not the current node.  We don't care exactly how many links there are, as soon
+  // as we find more than one we are done.
+  Link = 0;
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0);
+  // Until either all capabilities are done or until the desired link is found,
+  // keep looking for HT Host Capabilities.
+  while (Link < 2) {
+    LibAmdPciFindNextCap (&PciAddress, StdHeader);
+    if (PciAddress.AddressValue != ILLEGAL_SBDFO) {
+      LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader);
+      if ((CapabilityReg & 0xE00000FF) == 0x20000008) {
+        Link++;
+      }
+      // A capability other than an HT capability, keep looking.
+    } else {
+      // end of capabilities
+      break;
+    }
+  }
+  if (Link < 2) {
+    Features->PlatformFeatures.PlatformSingleLink = 1;
+  } else {
+    Features->PlatformFeatures.PlatformMultiLink = 1;
+  }
+
+  // Set the legacy core count bits.
+  GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+  switch (CoreCount) {
+  case 1:
+    Features->PlatformFeatures.PlatformSingleCore = 1;
+    break;
+  case 2:
+    Features->PlatformFeatures.PlatformDualCore = 1;
+    break;
+  default:
+    Features->PlatformFeatures.PlatformMultiCore = 1;
+  }
+
+  //
+  // Get some specific platform type info, VC...etc.
+  //
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+  FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader);
+
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks if a register table entry applies to the executing core.
+ *
+ * This function uses a combination of logical ID and platform features to
+ * determine whether or not a register table entry applies to the executing core.
+ *
+ * @param[in]     CoreCpuRevision         The current core's logical ID
+ * @param[in]     EntryCpuRevision        The entry's desired logical IDs
+ * @param[in]     PlatformFeatures        The platform features
+ * @param[in]     EntryFeatures           The entry's desired platform features
+ *
+ * @retval        TRUE           This entry should be applied
+ * @retval        FALSE          This entry does not apply
+ *
+ */
+BOOLEAN
+STATIC
+DoesEntryMatchPlatform (
+  IN       CPU_LOGICAL_ID   CoreCpuRevision,
+  IN       CPU_LOGICAL_ID   EntryCpuRevision,
+  IN       PLATFORM_FEATS   PlatformFeatures,
+  IN       PLATFORM_FEATS   EntryFeatures
+  )
+{
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  if (((CoreCpuRevision.Family & EntryCpuRevision.Family) != 0) &&
+      ((CoreCpuRevision.Revision & EntryCpuRevision.Revision) != 0)) {
+    if (EntryFeatures.PlatformFeatures.AndPlatformFeats == 0) {
+      // Match if ANY entry feats match a platform feat (an OR test)
+      if ((EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue) != 0) {
+        Result = TRUE;
+      }
+    } else {
+      // Match if ALL entry feats match a platform feat (an AND test)
+      if ((EntryFeatures.PlatformValue & ~(AMD_PF_AND)) ==
+          (EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue)) {
+        Result = TRUE;
+      }
+    }
+  }
+
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks register table entry type specific criteria to the platform.
+ *
+ * Entry Data Type implementer methods can use this generically to check their own
+ * specific criteria.  The method collects the actual platform characteristics and
+ * provides them along with the table entry's criteria to this service.
+ *
+ * There are a couple considerations for any implementer method using this service.
+ * The criteria value has to be representable as a UINT32.  The MSB, Bit 31, has to
+ * be used as a AND test request if set in the entry.  (The platform value should never
+ * have that bit set.)
+ *
+ * @param[in]     PlatformTypeSpecificFeatures        The platform features
+ * @param[in]     EntryTypeFeatures                   The entry's desired platform features
+ *
+ * @retval        TRUE                                This entry should be applied
+ * @retval        FALSE                               This entry does not apply
+ *
+ */
+BOOLEAN
+DoesEntryTypeSpecificInfoMatch (
+  IN       UINT32   PlatformTypeSpecificFeatures,
+  IN       UINT32   EntryTypeFeatures
+  )
+{
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  if ((EntryTypeFeatures & BIT31) == 0) {
+    // Match if ANY entry feats match a platform feat (an OR test)
+    if ((EntryTypeFeatures & PlatformTypeSpecificFeatures) != 0) {
+      Result = TRUE;
+    }
+  } else {
+    // Match if ALL entry feats match a platform feat (an AND test)
+    if ((EntryTypeFeatures & ~(BIT31)) == (EntryTypeFeatures & PlatformTypeSpecificFeatures)) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determine this core's Selector matches.
+ *
+ * @param[in]  Selector    Is the current core this selector type?
+ * @param[in]  StdHeader   Config handle for library and services.
+ *
+ * @retval  TRUE           Yes, it is.
+ * @retval  FALSE          No, it is not.
+ */
+BOOLEAN
+STATIC
+IsCoreSelector (
+  IN       TABLE_CORE_SELECTOR       Selector,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  BOOLEAN Result;
+  AGESA_STATUS  CalledStatus;
+
+  Result = TRUE;
+  ASSERT (Selector < TableCoreSelectorMax);
+
+  if ((Selector == PrimaryCores) && !IsCurrentCorePrimary (StdHeader)) {
+    Result = FALSE;
+  }
+  if ((Selector == CorePairPrimary) && !IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    Result = FALSE;
+  }
+  if ((Selector == BscCore) && (!IsBsp (StdHeader, &CalledStatus))) {
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the registers for this core based on entries in a list of Register Tables.
+ *
+ * Determine the platform features and this core's logical id.  Get the specific table
+ * entry type implementations for the logical model, which may be either generic (the ones
+ * in this file) or specific.
+ *
+ * Scan the tables starting the with ones for all cores and progressively narrowing the selection
+ * based on this core's role (ex. primary core).  For a selected table, check for each entry
+ * matching the current core and platform, and call the implementer method to perform the
+ * register set operation if it matches.
+ *
+ * @param[in]  PlatformConfig    Config handle for platform specific information
+ * @param[in]  StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegistersFromTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPU_LOGICAL_ID         CpuLogicalId;
+  PLATFORM_FEATS         PlatformFeatures;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  TABLE_ENTRY_FIELDS    *Entries;
+  TABLE_CORE_SELECTOR    Selector;
+  TABLE_ENTRY_TYPE       EntryType;
+  REGISTER_TABLE       **TableHandle;
+  UINTN                  NumberOfEntries;
+  UINTN                  CurrentEntryCount;
+  TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer;
+  PF_DO_TABLE_ENTRY       DoTableEntry[TableEntryTypeMax];
+
+  // Did you really mean to increase the size of ALL table entries??!!
+  // While it is not necessarily a bug to increase the size of table entries:
+  //   - Is this warning a surprise?  Please fix it.
+  //   - If expected, is this really a feature which is worth the increase?  Then let other entries also use the space.
+  ASSERT (sizeof (TABLE_ENTRY_DATA) == (MAX_ENTRY_TYPE_ITEMS32 * sizeof (UINT32)));
+
+  PlatformFeatures.PlatformValue = 0;
+  GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+  GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuLogicalId, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+
+  // Build a non-sparse table of implementer methods, so we don't have to keep searching.
+  // It is a bug to not include a descriptor for a type that is in the table (but the
+  // descriptor can point to a non-assert stub).
+  // Also, it is not a bug to have no register table implementations, but it is a bug to have none and call this routine.
+  for (EntryType = MsrRegister; EntryType < TableEntryTypeMax; EntryType++) {
+    DoTableEntry[EntryType] = (PF_DO_TABLE_ENTRY)CommonAssert;
+  }
+  TypeImplementer = FamilySpecificServices->TableEntryTypeDescriptors;
+  ASSERT (TypeImplementer != NULL);
+  while (TypeImplementer->EntryType < TableEntryTypeMax) {
+    DoTableEntry[TypeImplementer->EntryType] = TypeImplementer->DoTableEntry;
+    TypeImplementer++;
+  }
+
+  for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) {
+    if (IsCoreSelector (Selector, StdHeader)) {
+      // If the current core is the selected type of core, work the table list for tables for that type of core.
+      TableHandle = NULL;
+      Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader);
+      while (Entries != NULL) {
+        for (CurrentEntryCount = 0; CurrentEntryCount < NumberOfEntries; CurrentEntryCount++, Entries++) {
+          if (DoesEntryMatchPlatform (CpuLogicalId, Entries->CpuRevision, PlatformFeatures, Entries->Features)) {
+            // The entry matches this config, Do It!
+            // Find the implementer for this entry type and pass the entry data to it.
+            ASSERT (Entries->EntryType < TableEntryTypeMax);
+            DoTableEntry[Entries->EntryType] (&Entries->Entry, PlatformConfig, StdHeader);
+          }
+        }
+        Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader);
+      }
+    } else {
+      // Once a selector does not match the current core, quit looking.
+      break;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the registers for this core based on entries in a list of Register Tables.
+ *
+ * This function acts as a wrapper for calling the SetRegistersFromTables
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+SetRegistersFromTablesAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader);
+  SetRegistersFromTables (&EarlyParams->PlatformConfig, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
new file mode 100644
index 0000000000..42a4ae6ed4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
@@ -0,0 +1,1321 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains code to initialize the CPU MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_TABLE_H_
+#define _CPU_TABLE_H_
+
+#define MAX_ENTRY_TYPE_ITEMS32 6        // The maximum number of initializer items for UINT32 entry data types.
+
+/**
+ * @page regtableimpl Register Table Implementation Guide
+ *
+ * This register table implementation is modular and extensible, so that support code as
+ * well as table data can be family specific or built out if not needed, and new types
+ * of table entries can be added with low overhead.  Because many aspects are now generic,
+ * there can be common implementations for CPU revision and platform feature matching and for
+ * finding and iterating tables.
+ *
+ * @par Adding a new table entry type.
+ *
+ * To add a new table entry type follow these steps.
+ * <ul>
+ * <li>  Add a member to the enum TABLE_ENTRY_TYPE which is a descriptive name of the entry's purpose
+ *       or distinct characteristics.
+ *
+ * <li>  Create an entry data struct with the customized data needed.  For example, custom register designations,
+ *       data and mask sizes, or feature comparisons.  Name your struct by adding "_" and upper-casing the enum name
+ *       and adding "_TYPE_ENTRY_DATA" at the end.
+ *
+ * <li>  Add the entry data type as a member of the TABLE_ENTRY_DATA union.  Be aware of the size of your
+ *       entry data struct; all table entries in all tables will share any size increase you introduce!
+ *
+ * <li>  If your data entry contains any member types except for UINT32, you can't use the generic first union member
+ *       for the initializers that make up the actual tables (it's just UINT32's). The generic MSR entry is
+ *       an example. Follow the steps below:
+ *
+ *       <ul>
+ *       <li>  Make a union which has your entry data type as the first member.  Use TABLE_ENTRY_DATA as the
+ *             second member.  Name this with your register followed by "_DATA_INITIALIZER".
+ *
+ *       <li>  Make a copy of TABLE_ENTRY_FIELDS, and rename it your register "_TYPE_ENTRY_INITIALIZER".  Rename
+ *             the TABLE_ENTRY_DATA member of that struct to have the type you created in the previous step.
+ *             This type can be used to declare an array of entries and make a register table in some family specific
+ *             file.
+ *       </ul>
+ *
+ * <li>  Add the descriptor that will link table entries of your data type to an implementation for it.
+ *       <ul>
+ *       <li>  Find the options file which instantiates the CPU_SPECIFIC_SERVICES for each logical model that will
+ *             support the new entry type.
+ *
+ *       <li> From there find the instantiation of its TABLE_ENTRY_TYPE_DESCRIPTOR.  Add a descriptor to the
+ *            to the list for your new type.  Provide the name of a function which will implement the
+ *            entry data.  The function name should reflect that it implements the action for the entry type.
+ *            The function must be an instance of F_DO_TABLE_ENTRY.
+ *       </ul>
+ *
+ * <li>  Implement the function for your entry type data.  (If parts of it are family specific add methods to
+ *       CPU_SPECIFIC_SERVICES for that and implement them for each family or model required.)  @n
+ *       The definition of the function must conform to F_DO_TABLE_ENTRY.
+ *       In the function preamble, include a cross reference to the entry enum:
+ *       @code
+ *       *
+ *       * @TableEntryTypeMethod{::MyRegister}
+ *       *
+ *       @endcode
+ *
+ * </ul>
+ *
+ * @par  Adding a new Register Table
+ *
+ * To add a new register table for a logical CPU model follow the steps below.
+ *
+ * <ul>
+ * <li>  Find the options file which instantiates the CPU_SPECIFIC_SERVICES for the logical model that
+ *       should include the table.
+ *
+ * <li>  From there find the instantiation of its REGISTER_TABLE list. Add the name of the new register table.
+ * </ul>
+ *
+ */
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Define the supported table entries.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * These are the available types of table entries.
+ *
+ * Each type corresponds to:
+ * - a semantics for the type specific data, for example semantics for a Register value,
+ * Data value, and Mask value.
+ * - optionally, including a method for type specific matching criteria
+ * - a method for writing the desired update to the hardware.
+ *
+ * All types share in common a method to match CPU Family and Model and a method to match
+ * platform feature set.
+ *
+ */
+typedef enum {
+  MsrRegister,                 ///< Processor MSR registers.
+  PciRegister,                 ///< Processor Config Space registers.
+  FamSpecificWorkaround,       ///< Processor Family Specific Workarounds which are @b not practical using the other types.
+  HtPhyRegister,               ///< Processor HT Phy registers.
+  HtPhyRangeRegister,          ///< Processor HT Phy range of contiguous registers (ex. 40h:48h).
+  DeemphasisRegister,          ///< Processor Deemphasis register (HT Phy special case).
+  HtPhyFreqRegister,           ///< Processor Frequency dependent HT Phy settings.
+  ProfileFixup,                ///< Processor Performance Profile fixups to PCI Config Registers.
+  HtHostPciRegister,           ///< Processor Ht Host capability registers (PCI Config).
+  HtHostPerfPciRegister,       ///< Processor Ht Host capability registers which depend on performance features.
+  HtTokenPciRegister,          ///< Processor Ht Link Token count registers.
+  CoreCountsPciRegister,       ///< Processor PCI Config Registers which depend on core counts.
+  ProcCountsPciRegister,       ///< Processor PCI Config Registers which depend on processor counts.
+  CompUnitCountsPciRegister,   ///< Processor PCI Config Registers which depend on compute unit counts.
+  TokenPciRegister,            ///< Processor northbridge Token Count register which may be dependent on connectivity.
+  HtFeatPciRegister,           ///< Processor HT Link feature dependant PCI Config Registers.
+  HtPhyProfileRegister,        ///< Processor HT Phy registers which depend on performance features.
+  HtLinkPciRegister,           ///< Processor HT Link registers (one per link) not part of HT Host capability.
+  CompUnitCountsMsr,           ///< Processor MSRs which depend on compute unit counts.
+  TableEntryTypeMax            ///< Not a valid entry type, use for limit checking.
+} TABLE_ENTRY_TYPE;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Useful types and defines: Selectors, Platform Features, and type specific features.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * Select tables for the current core.
+ *
+ * This allows more efficient register table processing, by allowing cores to skip
+ * redundantly setting PCI registers, for example.  This feature is not intended to
+ * be relied on for function:  it is valid to have a single register table with all settings
+ * processed by every core; it's just slower.
+ *
+ */
+typedef enum {
+  AllCores,                   ///< Select only tables which apply to all cores.
+  CorePairPrimary,            ///< Select tables which apply to the primary core of a compute unit (SharedC, SharedNc).
+  PrimaryCores,               ///< Select tables which apply to primary cores.
+  BscCore,                    ///< Select tables which apply to the boot core.
+  TableCoreSelectorMax        ///< Not a valid selector, use for limit checking.
+} TABLE_CORE_SELECTOR;
+
+// Initializer bit pattern values for platform features.
+// Keep in synch with the PLATFORM_FEATURES struct!
+
+// The 5 control flow modes.
+#define AMD_PF_NFCM           BIT0
+#define AMD_PF_UMA            BIT1    // UMA_DR
+#define AMD_PF_UMA_IFCM       BIT2
+#define AMD_PF_IFCM           BIT3
+#define AMD_PF_IOMMU          BIT4
+// Degree of HT connectivity possible.
+#define AMD_PF_SINGLE_LINK    BIT5
+#define AMD_PF_MULTI_LINK     BIT6
+// For some legacy MSRs, define a couple core count bits.  Do not continue adding
+// core counts to the platform feats, if you need more than this design a table entry type.
+// Here, provide exactly 1, exactly 2, or anything else.
+#define AMD_PF_SINGLE_CORE    BIT7
+#define AMD_PF_DUAL_CORE      BIT8
+#define AMD_PF_MULTI_CORE     BIT9
+
+// Not a platform type, but treat all others as AND
+#define AMD_PF_AND            BIT31
+
+#define AMD_PF_ALL    (AMD_PF_NFCM          | \
+                       AMD_PF_UMA           | \
+                       AMD_PF_UMA_IFCM      | \
+                       AMD_PF_IFCM          | \
+                       AMD_PF_IOMMU         | \
+                       AMD_PF_SINGLE_LINK   | \
+                       AMD_PF_MULTI_LINK    | \
+                       AMD_PF_SINGLE_CORE   | \
+                       AMD_PF_DUAL_CORE     | \
+                       AMD_PF_MULTI_CORE)
+// Do not include AMD_PF_AND in AMD_PF_ALL !
+
+/**
+ * The current platform features.
+ *
+ * Keep this in sync with defines above that are used in the initializers!
+ *
+ * The comments with the bit number are useful for the computing the reserved member size, but
+ * do not write code that assumes you know what bit number one of these members is.
+ *
+ * These platform features are standard for all logical families and models.
+ */
+typedef struct {
+  UINT32          PlatformNfcm:1;             ///< BIT_0 Normal Flow Control Mode.
+  UINT32          PlatformUma:1;              ///< BIT_1 UMA (Display Refresh) Flow Control.
+  UINT32          PlatformUmaIfcm:1;          ///< BIT_2 UMA using Isochronous Flow Control.
+  UINT32          PlatformIfcm:1;             ///< BIT_3 Isochronous Flow Control Mode (not UMA).
+  UINT32          PlatformIommu:1;            ///< BIT_4 IOMMU (a special case Isochronous mode).
+  UINT32          PlatformSingleLink:1;       ///< BIT_5 The processor is in a package which implements only a single HT Link.
+  UINT32          PlatformMultiLink:1;        ///< BIT_6 The processor is in a package which implements more than one HT Link.
+  UINT32          PlatformSingleCore:1;       ///< BIT_7 Single Core processor, for legacy entries.
+  UINT32          PlatformDualCore:1;         ///< BIT_8 Dual Core processor, for legacy entries.
+  UINT32          PlatformMultiCore:1;        ///< BIT_9 More than dual Core processor, for legacy entries.
+  UINT32          :(30 - 9);                  ///< The possibilities are (not quite) endless.
+  UINT32          AndPlatformFeats:1;         ///< BIT_31
+} PLATFORM_FEATURES;
+
+/**
+ * Platform Features
+ */
+typedef union {
+  UINT32            PlatformValue;            ///< Describe Platform Features in UINT32.
+  ///< This one goes first, because then initializers use it automatically for the union.
+  PLATFORM_FEATURES PlatformFeatures;         ///< Describe Platform Features in structure
+} PLATFORM_FEATS;
+
+// Sublink Types are defined so they can match each attribute against either
+// sublink zero or one.  The table entry must contain the correct matching
+// values based on the register. This is available in the BKDG, for each register
+// which sublink it controls.  If the register is independent of sublink, OR values
+// together or use HT_LINKTYPE_ALL to match if either sublink matches (ex. E0 - E5).
+// Sublink 0 types, bits 0 thru 14
+#define HTPHY_LINKTYPE_SL0_HT3          BIT0
+#define HTPHY_LINKTYPE_SL0_HT1          BIT1
+#define HTPHY_LINKTYPE_SL0_COHERENT     BIT2
+#define HTPHY_LINKTYPE_SL0_NONCOHERENT  BIT3
+#define HTPHY_LINKTYPE_SL0_LINK0        BIT4
+#define HTPHY_LINKTYPE_SL0_LINK1        BIT5
+#define HTPHY_LINKTYPE_SL0_LINK2        BIT6
+#define HTPHY_LINKTYPE_SL0_LINK3        BIT7
+#define HTPHY_LINKTYPE_SL0_INTERNAL     BIT8
+#define HTPHY_LINKTYPE_SL0_EXTERNAL     BIT9
+#define HTPHY_LINKTYPE_SL0_AND          BIT15
+
+// SubLink 1 types, bits 16 thru 30
+#define HTPHY_LINKTYPE_SL1_HT3          BIT16
+#define HTPHY_LINKTYPE_SL1_HT1          BIT17
+#define HTPHY_LINKTYPE_SL1_COHERENT     BIT18
+#define HTPHY_LINKTYPE_SL1_NONCOHERENT  BIT19
+#define HTPHY_LINKTYPE_SL1_LINK4        BIT20
+#define HTPHY_LINKTYPE_SL1_LINK5        BIT21
+#define HTPHY_LINKTYPE_SL1_LINK6        BIT22
+#define HTPHY_LINKTYPE_SL1_LINK7        BIT23
+#define HTPHY_LINKTYPE_SL1_INTERNAL     BIT24
+#define HTPHY_LINKTYPE_SL1_EXTERNAL     BIT25
+#define HTPHY_LINKTYPE_SL1_AND          BIT31
+
+#define HTPHY_LINKTYPE_SL0_ALL          (HTPHY_LINKTYPE_SL0_HT3         | \
+                                         HTPHY_LINKTYPE_SL0_HT1         | \
+                                         HTPHY_LINKTYPE_SL0_COHERENT    | \
+                                         HTPHY_LINKTYPE_SL0_NONCOHERENT | \
+                                         HTPHY_LINKTYPE_SL0_LINK0       | \
+                                         HTPHY_LINKTYPE_SL0_LINK1       | \
+                                         HTPHY_LINKTYPE_SL0_LINK2       | \
+                                         HTPHY_LINKTYPE_SL0_LINK3       | \
+                                         HTPHY_LINKTYPE_SL0_INTERNAL    | \
+                                         HTPHY_LINKTYPE_SL0_EXTERNAL)
+#define HTPHY_LINKTYPE_SL1_ALL          (HTPHY_LINKTYPE_SL1_HT3         | \
+                                         HTPHY_LINKTYPE_SL1_HT1         | \
+                                         HTPHY_LINKTYPE_SL1_COHERENT    | \
+                                         HTPHY_LINKTYPE_SL1_NONCOHERENT | \
+                                         HTPHY_LINKTYPE_SL1_LINK4       | \
+                                         HTPHY_LINKTYPE_SL1_LINK5       | \
+                                         HTPHY_LINKTYPE_SL1_LINK6       | \
+                                         HTPHY_LINKTYPE_SL1_LINK7       | \
+                                         HTPHY_LINKTYPE_SL1_INTERNAL    | \
+                                         HTPHY_LINKTYPE_SL1_EXTERNAL)
+#define HTPHY_LINKTYPE_ALL              (HTPHY_LINKTYPE_SL0_ALL | HTPHY_LINKTYPE_SL1_ALL)
+
+#define HTPHY_REGISTER_MAX              0x0000FFFFul
+/**
+ * HT PHY Link Features
+ */
+typedef struct {
+  UINT32 HtPhySL0Ht3:1;                       ///< Ht Phy Sub-link 0 Ht3
+  UINT32 HtPhySL0Ht1:1;                       ///< Ht Phy Sub-link 0 Ht1
+  UINT32 HtPhySL0Coh:1;                       ///< Ht Phy Sub-link 0 Coherent
+  UINT32 HtPhySL0NonCoh:1;                    ///< Ht Phy Sub-link 0 NonCoherent
+  UINT32 HtPhySL0Link0:1;                     ///< Ht Phy Sub-link 0 specifically for node link 0.
+  UINT32 HtPhySL0Link1:1;                     ///< Ht Phy Sub-link 0 specifically for node link 1.
+  UINT32 HtPhySL0Link2:1;                     ///< Ht Phy Sub-link 0 specifically for node link 2.
+  UINT32 HtPhySL0Link3:1;                     ///< Ht Phy Sub-link 0 specifically for node link 3.
+  UINT32 HtPhySL0Internal:1;                  ///< Ht Phy Sub-link 0 is internal link.  Intended for IDS support.
+  UINT32 HtPhySL0External:1;                  ///< Ht Phy Sub-link 0 is external link.  Intended for IDS support.
+  UINT32 :(14 - 9);                           ///< Ht Phy Sub-link 0 Pad
+  UINT32 HtPhySL0And:1;                       ///< Ht Phy feature match should match all selected features, for sub-link 0.
+  UINT32 HtPhySL1Ht3:1;                       ///< Ht Phy Sub-link 1 Ht3
+  UINT32 HtPhySL1Ht1:1;                       ///< Ht Phy Sub-link 1 Ht1
+  UINT32 HtPhySL1Coh:1;                       ///< Ht Phy Sub-link 1 Coherent
+  UINT32 HtPhySL1NonCoh:1;                    ///< Ht Phy Sub-link 1 NonCoherent
+  UINT32 HtPhySL1Link4:1;                     ///< Ht Phy Sub-link 1 specifically for node link 4.
+  UINT32 HtPhySL1Link5:1;                     ///< Ht Phy Sub-link 1 specifically for node link 5.
+  UINT32 HtPhySL1Link6:1;                     ///< Ht Phy Sub-link 1 specifically for node link 6.
+  UINT32 HtPhySL1Link7:1;                     ///< Ht Phy Sub-link 1 specifically for node link 7.
+  UINT32 HtPhySL1Internal:1;                  ///< Ht Phy Sub-link 1 is internal link.  Intended for IDS support.
+  UINT32 HtPhySL1External:1;                  ///< Ht Phy Sub-link 1 is external link.  Intended for IDS support.
+  UINT32 :(30 - 25);                          ///< Ht Phy Sub-link 1 Pad
+  UINT32 HtPhySL1And:1;                       ///< Ht Phy feature match should match all selected features, for sub-link 1.
+} HT_PHY_LINK_FEATURES;
+
+/**
+ * Ht Phy Link Features
+ */
+typedef union {
+  UINT32                  HtPhyLinkValue;     ///< Describe HY Phy Features in UINT32.
+  ///< This one goes first, because then initializers use it automatically for the union.
+  HT_PHY_LINK_FEATURES    HtPhyLinkFeatures;  ///< Describe HT Phy Features in structure.
+} HT_PHY_LINK_FEATS;
+
+// DB Level for initializing Deemphasis
+// This must be in sync with DEEMPHASIS_FEATURES and PLATFORM_DEEMPHASIS_LEVEL (agesa.h)
+#define DEEMPHASIS_LEVEL_NONE   BIT0
+#define DEEMPHASIS_LEVEL__3     BIT1
+#define DEEMPHASIS_LEVEL__6     BIT2
+#define DEEMPHASIS_LEVEL__8     BIT3
+#define DEEMPHASIS_LEVEL__11    BIT4
+#define DEEMPHASIS_LEVEL__11_8  BIT5
+#define DCV_LEVEL_NONE          BIT16
+#define DCV_LEVEL__2            BIT17
+#define DCV_LEVEL__3            BIT18
+#define DCV_LEVEL__5            BIT19
+#define DCV_LEVEL__6            BIT20
+#define DCV_LEVEL__7            BIT21
+#define DCV_LEVEL__8            BIT22
+#define DCV_LEVEL__9            BIT23
+#define DCV_LEVEL__11           BIT24
+// Note that an "AND" feature doesn't make any sense, levels are mutually exclusive.
+
+// An error check value.
+#define DEEMPHASIS_LEVELS_ALL    (DEEMPHASIS_LEVEL_NONE    | \
+                                  DEEMPHASIS_LEVEL__3      | \
+                                  DEEMPHASIS_LEVEL__6      | \
+                                  DEEMPHASIS_LEVEL__8      | \
+                                  DEEMPHASIS_LEVEL__11     | \
+                                  DEEMPHASIS_LEVEL__11_8)
+
+#define DCV_LEVELS_ALL           (DCV_LEVEL_NONE           | \
+                                  DCV_LEVEL__2             | \
+                                  DCV_LEVEL__3             | \
+                                  DCV_LEVEL__5             | \
+                                  DCV_LEVEL__6             | \
+                                  DCV_LEVEL__7             | \
+                                  DCV_LEVEL__8             | \
+                                  DCV_LEVEL__9             | \
+                                  DCV_LEVEL__11)
+
+#define VALID_DEEMPHASIS_LEVELS  (DEEMPHASIS_LEVELS_ALL | DCV_LEVELS_ALL)
+
+/**
+ * Deemphasis Ht Phy Link Deemphasis.
+ *
+ * This must be in sync with defines above and ::PLATFORM_DEEMPHASIS_LEVEL (agesa.h)
+ */
+typedef struct {
+  UINT32          DeemphasisLevelNone:1;         ///< The deemphasis level None.
+  UINT32          DeemphasisLevelMinus3:1;       ///< The deemphasis level minus 3 db.
+  UINT32          DeemphasisLevelMinus6:1;       ///< The deemphasis level minus 6 db.
+  UINT32          DeemphasisLevelMinus8:1;       ///< The deemphasis level minus 8 db.
+  UINT32          DeemphasisLevelMinus11:1;      ///< The deemphasis level minus 11 db.
+  UINT32          DeemphasisLevelMinus11w8:1;    ///< The deemphasis level minus 11 db, minus 8 precursor.
+  UINT32          :(15 - 5);                     ///< reserved.
+  UINT32          DcvLevelNone:1;                ///< The level for DCV None.
+  UINT32          DcvLevelMinus2:1;              ///< The level for DCV minus 2 db.
+  UINT32          DcvLevelMinus3:1;              ///< The level for DCV minus 3 db.
+  UINT32          DcvLevelMinus5:1;              ///< The level for DCV minus 5 db.
+  UINT32          DcvLevelMinus6:1;              ///< The level for DCV minus 6 db.
+  UINT32          DcvLevelMinus7:1;              ///< The level for DCV minus 7 db.
+  UINT32          DcvLevelMinus8:1;              ///< The level for DCV minus 8 db.
+  UINT32          DcvLevelMinus9:1;              ///< The level for DCV minus 9 db.
+  UINT32          DcvLevelMinus11:1;             ///< The level for DCV minus 11 db.
+  UINT32          :(15 - 8);                     ///< reserved.
+} DEEMPHASIS_FEATURES;
+
+/**
+ * Deemphasis Ht Phy Link Features.
+ */
+typedef union {
+  UINT32                  DeemphasisValues;      ///< Initialize HT Deemphasis in UINT32.
+  DEEMPHASIS_FEATURES     DeemphasisLevels;      ///< HT Deemphasis levels.
+} DEEMPHASIS_FEATS;
+
+// Initializer bit patterns for PERFORMANCE_PROFILE_FEATS.
+#define PERFORMANCE_REFRESH_REQUEST_32B       BIT0
+#define PERFORMANCE_PROBEFILTER               BIT1
+#define PERFORMANCE_L3_CACHE                  BIT2
+#define PERFORMANCE_NO_L3_CACHE               BIT3
+#define PERFORMANCE_MCT_ISOC_VARIABLE         BIT4
+#define PERFORMANCE_IS_WARM_RESET             BIT5
+#define PERFORMANCE_VRM_HIGH_SPEED_ENABLE     BIT6
+#define PERFORMANCE_NB_PSTATES_ENABLE         BIT7
+#define PERFORMANCE_AND                       BIT31
+
+#define PERFORMANCE_PROFILE_ALL   (PERFORMANCE_REFRESH_REQUEST_32B | \
+                                   PERFORMANCE_PROBEFILTER         | \
+                                   PERFORMANCE_L3_CACHE            | \
+                                   PERFORMANCE_NO_L3_CACHE         | \
+                                   PERFORMANCE_MCT_ISOC_VARIABLE   | \
+                                   PERFORMANCE_IS_WARM_RESET       | \
+                                   PERFORMANCE_VRM_HIGH_SPEED_ENABLE | \
+                                   PERFORMANCE_NB_PSTATES_ENABLE)
+
+/**
+ * Performance Profile specific Type Features.
+ *
+ * Register settings for the different control flow modes can have additional dependencies
+ */
+typedef struct {
+  UINT32       RefreshRequest32Byte:1;         ///< BIT_0.   Display Refresh Requests use 32 bytes (32BE).
+  UINT32       ProbeFilter:1;                  ///< BIT_1    Probe Filter will be enabled.
+  UINT32       L3Cache:1;                      ///< BIT_2    L3 Cache is present.
+  UINT32       NoL3Cache:1;                    ///< BIT_3    L3 Cache is NOT present.
+  UINT32       MctIsocVariable:1;              ///< BIT_4    Mct Isoc Read Priority set to variable.
+  UINT32       IsWarmReset:1;                  ///< BIT_5    This boot is on a warm reset, cold reset pass is already completed.
+  UINT32       VrmHighSpeed:1;                 ///< BIT_6    Select high speed VRM.
+  UINT32       NbPstates:1;                    ///< BIT_7    Northbridge PStates are enabled
+  UINT32       :(30 - 7);                      ///< available for future expansion.
+  UINT32       AndPerformanceFeats:1;          ///< BIT_31.  AND other selected features.
+} PERFORMANCE_PROFILE_FEATURES;
+
+/**
+ * Performance Profile features.
+ */
+typedef union {
+  UINT32                        PerformanceProfileValue;     ///< Initializer value.
+  PERFORMANCE_PROFILE_FEATURES  PerformanceProfileFeatures;  ///< The performance profile features.
+} PERFORMANCE_PROFILE_FEATS;
+
+/**
+ * Package Type Features
+ *
+ */
+typedef struct {
+  UINT32        PkgType0:1;                 ///< Package Type 0
+  UINT32        PkgType1:1;                 ///< Package Type 1
+  UINT32        PkgType2:1;                 ///< Package Type 2
+  UINT32        PkgType3:1;                 ///< Package Type 3
+  UINT32        PkgType4:1;                 ///< Package Type 4
+  UINT32        PkgType5:1;                 ///< Package Type 5
+  UINT32        PkgType6:1;                 ///< Package Type 6
+  UINT32        PkgType7:1;                 ///< Package Type 7
+  UINT32        PkgType8:1;                 ///< Package Type 8
+  UINT32        PkgType9:1;                 ///< Package Type 9
+  UINT32        PkgType10:1;                ///< Package Type 10
+  UINT32        PkgType11:1;                ///< Package Type 11
+  UINT32        PkgType12:1;                ///< Package Type 12
+  UINT32        PkgType13:1;                ///< Package Type 13
+  UINT32        PkgType14:1;                ///< Package Type 14
+  UINT32        PkgType15:1;                ///< Package Type 15
+  UINT32        Reserved:15;                ///< Package Type Reserved
+  UINT32        ReservedAndFeats:1;         ///< BIT_31.  AND other selected features. Always zero here.
+} PACKAGE_TYPE_FEATURES;
+
+// Initializer Values for Package Type
+#define PACKAGE_TYPE_ALL              0XFFFF       ///< Package Type apply all packages
+
+// Initializer Values for Ht Host Pci Config Registers
+#define HT_HOST_FEAT_COHERENT          BIT0
+#define HT_HOST_FEAT_NONCOHERENT       BIT1
+#define HT_HOST_FEAT_GANGED            BIT2
+#define HT_HOST_FEAT_UNGANGED          BIT3
+#define HT_HOST_FEAT_HT3               BIT4
+#define HT_HOST_FEAT_HT1               BIT5
+#define HT_HOST_AND                    BIT31
+
+#define HT_HOST_FEATURES_ALL    (HT_HOST_FEAT_COHERENT    | \
+                                 HT_HOST_FEAT_NONCOHERENT | \
+                                 HT_HOST_FEAT_GANGED      | \
+                                 HT_HOST_FEAT_UNGANGED    | \
+                                 HT_HOST_FEAT_HT3         | \
+                                 HT_HOST_FEAT_HT1)
+
+/**
+ * HT Host PCI register features.
+ *
+ * Links which are not connected do not match any of these features.
+ */
+typedef struct {
+  UINT32       Coherent:1;                 ///< BIT_0 Apply to links with a coherent connection.
+  UINT32       NonCoherent:1;              ///< BIT_1 Apply to links with a non-coherent connection.
+  UINT32       Ganged:1;                   ///< BIT_2 Apply to links with a ganged connection.
+  UINT32       UnGanged:1;                 ///< BIT_3 Apply to links with a unganged connection.
+  UINT32       Ht3:1;                      ///< BIT_4 Apply to links with HT3 frequency (> 1000 MHz)
+  UINT32       Ht1:1;                      ///< BIT_5 Apply to links with HT1 frequency (< 1200 MHz)
+  UINT32       :(30 - 5);                  ///< Future expansion.
+  UINT32       AndHtHostFeats:1;           ///< BIT_31.  AND other selected features.
+} HT_HOST_FEATURES;
+
+/**
+ * HT Host features for table data.
+ */
+typedef union {
+  UINT32                 HtHostValue;                ///< Initializer value.
+  HT_HOST_FEATURES       HtHostFeatures;             ///< The HT Host Features.
+} HT_HOST_FEATS;
+
+// Core Range Initializer values.
+#define COUNT_RANGE_LOW            0ul
+#define COUNT_RANGE_HIGH           0xFFul
+
+// A count range matching none is often useful as the second range, matching will then be
+// based on the first range.  A count range all is provided as a first range for default settings.
+#define COUNT_RANGE_NONE           ((((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) << 16)
+#define COUNT_RANGE_ALL            (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_LOW))
+#define IGNORE_FREQ_0              (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH))
+#define IGNORE_PROCESSOR_0         (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH))
+
+#define CORE_RANGE_0(min, max)            ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define CORE_RANGE_1(min, max)            (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define PROCESSOR_RANGE_0(min, max)       ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define PROCESSOR_RANGE_1(min, max)       (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define DEGREE_RANGE_0(min, max)          ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define DEGREE_RANGE_1(min, max)          (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define FREQ_RANGE_0(min, max)            ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define FREQ_RANGE_1(min, max)            (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define COMPUTE_UNIT_RANGE_0(min, max)    ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define COMPUTE_UNIT_RANGE_1(min, max)    (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+
+/**
+ * Count Range Feature, two count ranges for core counts, processor counts, or node counts.
+ */
+typedef struct {
+  UINT32       Range0Min:8;           ///< The minimum of the first count range.
+  UINT32       Range0Max:8;           ///< The maximum of the first count range.
+  UINT32       Range1Min:8;           ///< The minimum of the second count range.
+  UINT32       Range1Max:8;           ///< The maximum of the second count range.
+} COUNT_RANGE_FEATURE;
+
+/**
+ * Core Count Ranges for table data.
+ *
+ * Provide a pair of core count ranges. If the actual core count is included in either range (OR),
+ * the feature should be considered a match.
+ */
+typedef union {
+  UINT32       CoreRangeValue;          ///< Initializer value.
+  COUNT_RANGE_FEATURE CoreRanges;       ///< The Core Counts.
+} CORE_COUNT_RANGES;
+
+/**
+ * Processor count ranges for table data.
+ *
+ * Provide a pair of processor count ranges.  If the actual counts are included in either range (OR),
+ * the feature should be considered a match.
+ */
+typedef union {
+  UINT32       ProcessorCountRangeValue;             ///< Initializer value.
+  COUNT_RANGE_FEATURE ProcessorCountRanges;          ///< The Processor and Node Counts.
+} PROCESSOR_COUNTS;
+
+/**
+ * Compute unit count ranges for table data.
+ *
+ * Provide a pair of compute unit count ranges. If the actual counts are included in either ranges (OR),
+ * the feature should be considered a match.
+ */
+typedef union {
+  UINT32    ComputeUnitRangeValue;                ///< Initializer value.
+  COUNT_RANGE_FEATURE ComputeUnitRanges;          ///< The Processor and Node Counts.
+} COMPUTE_UNIT_COUNTS;
+
+/**
+ * Connectivity count ranges for table data.
+ *
+ * Provide a processor count range and a system degree range.  The degree of a system is
+ * the maximum degree of any node.  The degree of a node is the number of nodes to which
+ * it is directly connected (not considering width or redundant links). If both the actual
+ * counts are included in each range (AND), the feature should be considered a match.
+ */
+typedef union {
+  UINT32       ConnectivityCountRangeValue;             ///< Initializer value.
+  COUNT_RANGE_FEATURE ConnectivityCountRanges;          ///< The Processor and Degree Counts.
+} CONNECTIVITY_COUNT;
+
+/**
+ * HT Frequency Count Range.
+ *
+ * Provide a pair of Frequency count ranges, with the frequency encoded as an HT Frequency value
+ * (such as would be programmed into the HT Host Link Frequency register).  By converting a NB freq,
+ * the same count can be applied for it.  If the actual value is included in either range
+ */
+typedef union {
+  UINT32       HtFreqCountRangeValue;                  ///< Initializer value.
+  COUNT_RANGE_FEATURE HtFreqCountRanges;               ///< The HT Freq counts.
+} HT_FREQ_COUNTS;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * The specific data for each table entry.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ *  Make an extra type so we can use compilers that don't support designated initializers.
+ *
+ *  All the entry type unions are no more than 5 UINT32's in size.  For entry types which are a struct of UINT32's,
+ *  this type can be used so that initializers can be declared TABLE_ENTRY_FIELDS, instead of a special non-union type.
+ *  A non-union type then has to be cast back to TABLE_ENTRY_FIELDS in order to process the table, and you can't mix
+ *  entry types with non-union initializers in the same table with any other type.
+ *
+ *  If the entry type contains anything but UINT32's, then it must have a non-union initializer type for creating the
+ *  actual tables.  For example, MSR entry has UINT64 and workaround entry has a function pointer.
+ */
+typedef UINT32 GENERIC_TYPE_ENTRY_INITIALIZER[MAX_ENTRY_TYPE_ITEMS32];
+
+/**
+ * Table Entry Data for MSR Registers.
+ *
+ * Apply data to register after mask, for MSRs.
+ */
+typedef struct {
+  UINT32  Address;                    ///< MSR address
+  UINT64  Data;                       ///< Data to set in the MSR
+  UINT64  Mask;                       ///< Mask to be applied to the MSR. Set every bit of all updated fields.
+} MSR_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for PCI Registers.
+ *
+ * Apply data to register after mask, for PCI Config registers.
+ */
+typedef struct {
+  PCI_ADDR  Address;                  ///< Address should contain Function, Offset only.  It will apply to all CPUs
+  UINT32    Data;                     ///< Data to be written into PCI device
+  UINT32    Mask;                     ///< Mask to be used before data write. Set every bit of all updated fields.
+} PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Registers.
+ *
+ * Apply data to register after mask, for HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  HT_PHY_LINK_FEATS TypeFeats;        ///< HT Phy Link Features
+  UINT32            Address;          ///< Address of Ht Phy Register
+  UINT32            Data;             ///< Data to be written into PCI device
+  UINT32            Mask;             ///< Mask to be used before data write.  Set every bit of all updated fields.
+} HT_PHY_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Register Ranges.
+ *
+ * Apply data to register after mask, for a range of HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  HT_PHY_LINK_FEATS TypeFeats;        ///< HT Phy Link Features
+  UINT32            LowAddress;       ///< Low address of Ht Phy Register range.
+  UINT32            HighAddress;      ///< High address of register range.
+  UINT32            Data;             ///< Data to be written into PCI device.
+  UINT32            Mask;             ///< Mask to be used before data write.  Set every bit of all updated fields.
+} HT_PHY_RANGE_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Deemphasis Registers.
+ *
+ * Apply data to register after mask, for HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  DEEMPHASIS_FEATS        Levels;       ///< The DCV and Deemphasis levels to match
+  HT_PHY_TYPE_ENTRY_DATA  HtPhyEntry;   ///< The HT Phy Entry to set the deemphasis values
+} DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Date for HT Phy Frequency Count Register updates.
+ *
+ * Compare the NB freq to a range, the HT freq to a range, the link features.
+ * Apply data to register after mask, if all three matched.
+ */
+typedef struct {
+  HT_FREQ_COUNTS       HtFreqCounts;      ///< Specify the HT Frequency range.
+  HT_FREQ_COUNTS       NbFreqCounts;      ///< Specify the NB Frequency range.
+  HT_PHY_TYPE_ENTRY_DATA HtPhyEntry;      ///< The HT Phy register update to perform.
+} HT_PHY_FREQ_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for Profile Fixup Registers.
+ *
+ * If TypeFeats matches current config, apply data to register after mask for PCI Config registers.
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
+  PCI_TYPE_ENTRY_DATA PciEntry;        ///< The PCI Register entry data.
+} PROFILE_FIXUP_TYPE_ENTRY_DATA;
+
+/**
+ * A variation of PCI register for the HT Host registers.
+ *
+ * A setting to the HT Host buffer counts needs to be made to all the registers for
+ * all the links.  There are also link specific criteria to check.
+ */
+typedef struct {
+  HT_HOST_FEATS     TypeFeats;        ///< Link Features.
+  PCI_ADDR          Address;          ///< Address of PCI Register to Fixed Up.
+  UINT32            Data;             ///< Data to be written into PCI device
+  UINT32            Mask;             ///< Mask to be used before data write.  Set every bit of all updated fields.
+} HT_HOST_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * A variation of PCI register for the HT Host performance registers.
+ *
+ * A setting to the HT Host buffer counts needs to be made to all the registers for
+ * all the links.  There are also link specific criteria to check.
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS   PerformanceFeats;    ///< Performance Profile features.
+  HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry;         ///< Link Features.
+} HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * A variation of HT Host PCI register for the Link Token registers.
+ *
+ * Use Link Features, Performance Fixup features, and processor counts to match entries.
+ * Link Features are iterated through the connected links.  All the matching Link Token count
+ * registers are updated.
+ */
+typedef struct {
+  CONNECTIVITY_COUNT          ConnectivityCount;   ///< Specify Processor count and Degree count range.
+  PERFORMANCE_PROFILE_FEATS   PerformanceFeats;    ///< Performance Profile features.
+  HT_HOST_FEATS               LinkFeats;           ///< Link Features.
+  PCI_ADDR                    Address;             ///< Address of PCI Register to Fixed Up.
+  UINT32                      Data;                ///< Data to be written into PCI device
+  UINT32                      Mask;                ///< Mask to be used before data write. Set every bit of all updated fields.
+} HT_TOKEN_PCI_REGISTER;
+
+/**
+ * Core Count dependent PCI registers.
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
+  CORE_COUNT_RANGES CoreCounts;        ///< Specify up to two core count ranges to match.
+  PCI_TYPE_ENTRY_DATA PciEntry;        ///< The PCI Register entry data.
+} CORE_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Processor Count dependent PCI registers.
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
+  PROCESSOR_COUNTS  ProcessorCounts;   ///< Specify a processor count range.
+  PCI_TYPE_ENTRY_DATA PciEntry;        ///< The PCI Register entry data.
+} PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Compute Unit Count dependent PCI registers.
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats;         ///< Profile Fixup Features.
+  COMPUTE_UNIT_COUNTS       ComputeUnitCounts; ///< Specify a compute unit count range.
+  PCI_TYPE_ENTRY_DATA       PciEntry;          ///< The PCI Register entry data.
+} COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Compute Unit Count dependent MSR registers.
+ *
+ */
+typedef struct {
+  COMPUTE_UNIT_COUNTS       ComputeUnitCounts; ///< Specify a compute unit count range.
+  MSR_TYPE_ENTRY_DATA       MsrEntry;          ///< The MSR Register entry data.
+} COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA;
+
+/**
+ * System connectivity dependent PCI registers.
+ *
+ * The topology specific recommended settings are based on the different connectivity of nodes
+ * in each configuration:  the more connections, the fewer resources each connection gets.
+ * The connectivity criteria translate as:
+ * - 2 Socket, half populated  ==   Degree 1
+ * - 4 Socket, half populated   ==  Degree 2
+ * - 2 Socket, fully populated  ==  Degree 3
+ * - 4 Socket, fully populated  ==  Degree > 3.  (4 or 5 if 3P, 6 if 4P)
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats;     ///< Profile Fixup Features.
+  CONNECTIVITY_COUNT  ConnectivityCount;   ///< Specify a system degree range.
+  PCI_TYPE_ENTRY_DATA PciEntry;            ///< The PCI Register entry data.
+} CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * A Family Specific Workaround method.
+ *
+ * \@TableTypeFamSpecificInstances.
+ *
+ * When called, the entry's CPU Logical ID and Platform Features matched the current config.
+ * The method must implement any specific criteria checking for the workaround.
+ *
+ * See if you can use the other entries or make an entry specifically for the fix.
+ * After all, the purpose of having a table entry is to @b NOT have code which
+ * isn't generic feature code, but is family/model specific.
+ *
+ * @param[in]     Data       The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]     StdHeader  Config params for library, services.
+ */
+typedef VOID F_FAM_SPECIFIC_WORKAROUND (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/// Reference to a method.
+typedef F_FAM_SPECIFIC_WORKAROUND *PF_FAM_SPECIFIC_WORKAROUND;
+
+/**
+ * Table Entry Data for Family Specific Workarounds.
+ *
+ * See if you can use the other entries or make an entry specifically for the fix.
+ * After all, the purpose of having a table entry is to @b NOT have code which
+ * isn't generic feature code, but is family/model specific.
+ *
+ * Call DoAction passing Data.
+ */
+typedef struct {
+  PF_FAM_SPECIFIC_WORKAROUND  DoAction;     ///< A function implementing the workaround.
+  UINT32                Data;               ///< This data is passed to DoAction().
+} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA;
+
+/**
+ * Package Type Features
+ *
+ * FamilyPackageType are various among CPU families.
+ *
+ */
+typedef union {
+  UINT32                      PackageTypeValue;    ///< Package Type
+  PACKAGE_TYPE_FEATURES       FamilyPackageType;   ///< Package Type of CPU family
+} PACKAGE_TYPE_FEATS;
+
+/**
+ * HT Features dependent Global PCI registers.
+ *
+ */
+typedef struct {
+  HT_HOST_FEATS               LinkFeats;           ///< Link Features.
+  PACKAGE_TYPE_FEATS          PackageType;         ///< Package Type
+  PCI_TYPE_ENTRY_DATA         PciEntry;            ///< The PCI Register entry data.
+} HT_FEATURES_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Registers which depend on performance profile features.
+ *
+ * Match performance profile features and link features.
+ * Apply data to register after mask, for HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS  TypeFeats;            ///< Profile Fixup Features.
+  HT_PHY_TYPE_ENTRY_DATA     HtPhyEntry;           ///< The HT Phy Entry to set the deemphasis values
+} PROFILE_HT_PHY_TYPE_ENTRY_DATA;
+
+/**
+ * HT Link PCI registers that are not in the HT Host capability.
+ *
+ * Some HT Link registers have an instance per link, but are just sequential.  Specify the base register
+ * in the table register address (link 0 sublink 0).
+ */
+typedef struct {
+  HT_HOST_FEATS               LinkFeats;           ///< Link Features.
+  PCI_TYPE_ENTRY_DATA         PciEntry;            ///< The PCI Register entry data.
+} HT_LINK_PCI_TYPE_ENTRY_DATA;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * A complete register table and table entries.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * All the available entry data types.
+ */
+typedef union {
+  GENERIC_TYPE_ENTRY_INITIALIZER          InitialValues;         ///< Not a valid entry type; as the first union item,
+                                                                 ///< it can be used with initializers.
+  MSR_TYPE_ENTRY_DATA                     MsrEntry;              ///< Msr entry.
+  PCI_TYPE_ENTRY_DATA                     PciEntry;              ///< PCI entry.
+  FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificEntry;      ///< Family Specific Workaround entry.
+  HT_PHY_TYPE_ENTRY_DATA                  HtPhyEntry;            ///< HT Phy entry.
+  HT_PHY_RANGE_TYPE_ENTRY_DATA            HtPhyRangeEntry;       ///< A range of Ht Phy Registers
+  DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA       DeemphasisEntry;       ///< A HT Deemphasis level's settings.
+  HT_PHY_FREQ_TYPE_ENTRY_DATA             HtPhyFreqEntry;        ///< A frequency dependent Ht Phy Register setting.
+  PROFILE_FIXUP_TYPE_ENTRY_DATA           FixupEntry;            ///< Profile Fixup entry.
+  HT_HOST_PCI_TYPE_ENTRY_DATA             HtHostEntry;           ///< HT Host PCI entry.
+  HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA HtHostPerfEntry;       ///< HT Host Performance PCI entry
+  HT_TOKEN_PCI_REGISTER                   HtTokenEntry;          ///< HT Link Token Count entry.
+  CORE_COUNTS_PCI_TYPE_ENTRY_DATA         CoreCountEntry;        ///< Core count dependent settings.
+  PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA    ProcCountEntry;        ///< Processor count entry.
+  COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA CompUnitCountEntry;    ///< Compute unit count dependent entry.
+  CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA TokenPciEntry;         ///< System connectivity dependent Token register.
+  HT_FEATURES_PCI_TYPE_ENTRY_DATA         HtFeatPciEntry;        ///< HT Features PCI entry.
+  PROFILE_HT_PHY_TYPE_ENTRY_DATA          HtPhyProfileEntry;     ///< Performance dependent HT Phy register.
+  HT_LINK_PCI_TYPE_ENTRY_DATA             HtLinkPciEntry;        ///< Per Link, non HT Host, PCI registers.
+  COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA CompUnitCountMsrEntry; ///< Compute unit count dependent MSR entry.
+} TABLE_ENTRY_DATA;
+
+/**
+ * Register Table Entry common fields.
+ *
+ * All the various types of register table entries are subclasses of this object.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       EntryType;                  ///< The type of table entry this is.
+  CPU_LOGICAL_ID         CpuRevision;                ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS         Features;                   ///< Common Platform Features match criteria.
+  TABLE_ENTRY_DATA       Entry;                      ///< The type dependent entry data (ex. register, data, mask).
+} TABLE_ENTRY_FIELDS;
+
+/**
+ * An entire register table.
+ */
+typedef struct {
+  TABLE_CORE_SELECTOR  Selector;                     ///< For efficiency, these cores should process this table
+  UINTN                NumberOfEntries;              ///< The number of entries in the table.
+  CONST TABLE_ENTRY_FIELDS  *Table;                  ///< The table entries.
+} REGISTER_TABLE;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Describe implementers for table entries.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * Implement the semantics of a Table Entry Type.
+ *
+ * @TableEntryTypeInstances.
+ *
+ * @param[in]       CurrentEntry        The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ */
+typedef VOID F_DO_TABLE_ENTRY (
+  IN       TABLE_ENTRY_DATA       *CurrentEntry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a method
+typedef F_DO_TABLE_ENTRY *PF_DO_TABLE_ENTRY;
+
+/**
+ * Describe the attributes of a Table Entry Type.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       EntryType;                  ///< The type of table entry this describes.
+  PF_DO_TABLE_ENTRY      DoTableEntry;               ///< Provide all semantics associated with TABLE_ENTRY_DATA
+} TABLE_ENTRY_TYPE_DESCRIPTOR;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Non-union initializers for entry data which is not just UINT32.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * A union of data types, that can be initialized with MSR data.
+ *
+ * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
+ */
+typedef union {
+  MSR_TYPE_ENTRY_DATA    MsrInitializer;            ///< The data in the table initializer is assigned to this member.
+  TABLE_ENTRY_DATA       Reserved;                  ///< Make sure the size is the same as the real union.
+} MSR_DATA_INITIALIZER;
+
+/**
+ * A type suitable for an initializer for MSR Table entries.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       Type;                       ///< The type of table entry this is.
+  CPU_LOGICAL_ID         CpuRevision;                ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS         Features;                   ///< Common Platform Features match criteria.
+  MSR_DATA_INITIALIZER    EntryData;                 ///< The special union which accepts msr data initializer.
+} MSR_TYPE_ENTRY_INITIALIZER;
+
+/**
+ * A union of data types, that can be initialized with MSR CU data.
+ *
+ * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
+ */
+typedef union {
+  COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA  MsrInitializer;  ///< The data in the table initializer is assigned to this member.
+  TABLE_ENTRY_DATA       Reserved;                          ///< Make sure the size is the same as the real union.
+} MSR_CU_DATA_INITIALIZER;
+
+/**
+ * A type suitable for an initializer for MSR CU count Table entries.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE           Type;                   ///< The type of table entry this is.
+  CPU_LOGICAL_ID             CpuRevision;            ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS             Features;               ///< Common Platform Features match criteria.
+  MSR_CU_DATA_INITIALIZER    EntryData;              ///< The special union which accepts msr data initializer.
+} MSR_CU_TYPE_ENTRY_INITIALIZER;
+
+/**
+ * A union of data types, that can be initialized with Family Specific Workaround data.
+ *
+ * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
+ */
+typedef union {
+  FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA    FamSpecificInitializer; ///< The data in the table initializer is assigned to this member.
+  TABLE_ENTRY_DATA       Reserved;                                   ///< Make sure the size is the same as the real union.
+} FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER;
+
+/**
+ * A type suitable for an initializer for Family Specific Workaround Table entries.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       Type;                             ///< The type of table entry this is.
+  CPU_LOGICAL_ID         CpuRevision;                      ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS         Features;                         ///< Common Platform Features match criteria.
+  FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER    EntryData;   ///< Special union accepts family specific workaround data initializer.
+} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * Set the registers for this core based on entries in a list of Register Tables.
+ */
+VOID SetRegistersFromTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Find the features of the running platform.
+ */
+VOID
+GetPlatformFeatures (
+     OUT   PLATFORM_FEATS    *Features,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Checks register table entry type specific criteria to the platform.
+ */
+BOOLEAN
+DoesEntryTypeSpecificInfoMatch (
+  IN       UINT32   PlatformTypeSpecificFeatures,
+  IN       UINT32   EntryTypeFeatures
+  );
+
+/**
+ * Perform the MSR Register Entry.
+ */
+VOID
+SetRegisterForMsrEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the PCI Register Entry.
+ */
+VOID
+SetRegisterForPciEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Performance Profile PCI Register Entry.
+ */
+VOID
+SetRegisterForPerformanceProfileEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the HT Host PCI Register Entry.
+ */
+VOID
+SetRegisterForHtHostEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the HT Host Performance PCI Register Entry.
+ */
+VOID
+SetRegisterForHtHostPerfEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Set the HT Link Token Count registers.
+ */
+VOID
+SetRegisterForHtLinkTokenEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the Core Counts Performance PCI Register Entry.
+ */
+VOID
+SetRegisterForCoreCountsPerformanceEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Processor Counts PCI Register Entry.
+ */
+VOID
+SetRegisterForProcessorCountsEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Compute Unit Counts PCI Register Entry.
+ */
+VOID
+SetRegisterForComputeUnitCountsEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the Compute Unit Counts MSR Register Entry.
+ */
+VOID
+SetMsrForComputeUnitCountsEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the Family Specific Workaround Register Entry.
+ */
+VOID
+SetRegisterForFamSpecificWorkaroundEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Program HT Phy PCI registers.
+ */
+VOID
+SetRegisterForHtPhyEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Program a range of HT Phy PCI registers.
+ */
+VOID
+SetRegisterForHtPhyRangeEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Program Deemphasis registers, for the platform specified levels.
+ */
+VOID
+SetRegisterForDeemphasisEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Program HT Phy PCI registers which have complex frequency dependencies.
+ */
+VOID
+SetRegisterForHtPhyFreqEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the Processor Token Counts PCI Register Entry.
+ */
+VOID
+SetRegisterForTokenPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the HT Link Feature PCI Register Entry.
+ */
+VOID
+SetRegisterForHtFeaturePciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the HT Phy Performance Profile Register Entry.
+ */
+VOID
+SetRegisterForHtPhyProfileEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the HT Link PCI Register Entry.
+ */
+VOID
+SetRegisterForHtLinkPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Compare counts to a pair of ranges.
+ */
+BOOLEAN
+IsEitherCountInRange (
+  IN       UINTN                FirstCount,
+  IN       UINTN                SecondCount,
+  IN       COUNT_RANGE_FEATURE  Ranges
+  );
+
+/**
+ * Returns the performance profile features list of the currently running processor core.
+ */
+VOID
+GetPerformanceFeatures (
+     OUT   PERFORMANCE_PROFILE_FEATS    *Features,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+#endif  // _CPU_TABLE_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
new file mode 100644
index 0000000000..f2dc00bd9a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
@@ -0,0 +1,954 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Set registers according to a set of register tables
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Table.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "CommonReturns.h"
+#include "cpuL3Features.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_TABLEHT_FILECODE
+
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program HT Phy PCI registers using BKDG values.
+ *
+ * @TableEntryTypeMethod{::HtPhyRegister}.
+ *
+ *
+ * @param[in]       Entry               The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForHtPhyEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->InitialValues[4] == 0) &&
+          ((Entry->HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0) &&
+          (Entry->HtPhyEntry.Address < HTPHY_REGISTER_MAX));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (FamilySpecificServices->NextLinkHasHtPhyFeats (
+           FamilySpecificServices,
+           &CapabilitySet,
+           &Link,
+           &Entry->HtPhyEntry.TypeFeats,
+           &MatchedSublink1,
+           &Freq0,
+           &Freq1,
+           StdHeader)) {
+    FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyEntry, CapabilitySet, Link, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program a range of HT Phy PCI registers using BKDG values.
+ *
+ * @TableEntryTypeMethod{::HtPhyRangeRegister}.
+ *
+ *
+ * @param[in]       Entry               The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForHtPhyRangeEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  HT_PHY_TYPE_ENTRY_DATA CurrentHtPhyRegister;
+  BOOLEAN                MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtPhyRangeEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->HtPhyRangeEntry.LowAddress <= Entry->HtPhyRangeEntry.HighAddress) &&
+          (Entry->HtPhyRangeEntry.HighAddress < HTPHY_REGISTER_MAX) &&
+          (Entry->HtPhyRangeEntry.HighAddress != 0));
+
+  CurrentHtPhyRegister.Mask = Entry->HtPhyRangeEntry.Mask;
+  CurrentHtPhyRegister.Data = Entry->HtPhyRangeEntry.Data;
+  CurrentHtPhyRegister.TypeFeats = Entry->HtPhyRangeEntry.TypeFeats;
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (FamilySpecificServices->NextLinkHasHtPhyFeats (
+           FamilySpecificServices,
+           &CapabilitySet,
+           &Link,
+           &Entry->HtPhyRangeEntry.TypeFeats,
+           &MatchedSublink1,
+           &Freq0,
+           &Freq1,
+           StdHeader)) {
+    for (CurrentHtPhyRegister.Address = Entry->HtPhyRangeEntry.LowAddress;
+         CurrentHtPhyRegister.Address <= Entry->HtPhyRangeEntry.HighAddress;
+         CurrentHtPhyRegister.Address++) {
+      FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &CurrentHtPhyRegister, CapabilitySet, Link, StdHeader);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is PackageLink an Internal Link?
+ *
+ * This is a test for the logical link match codes in the user interface, not a test for
+ * the actual northbridge links.
+ *
+ * @param[in]    PackageLink   The link
+ *
+ * @retval       TRUE          This is an internal link
+ * @retval       FALSE         This is not an internal link
+ */
+BOOLEAN
+STATIC
+IsDeemphasisLinkInternal (
+  IN       UINT32  PackageLink
+  )
+{
+  return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Package Link number, for the current node and real link number.
+ *
+ * Based on the link to package link mapping from BKDG, look up package link for
+ * the input link on the internal node number corresponding to the current core's node.
+ * For single module processors, the northbridge link and package link are the same.
+ *
+ * @param[in]   Link                      the link on the current node.
+ * @param[in]   FamilySpecificServices    CPU specific support interface.
+ * @param[in]   StdHeader                 Config params for library, services.
+ *
+ * @return      the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
+ *
+ */
+UINT32
+STATIC
+LookupPackageLink (
+  IN       UINT32                 Link,
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32 PackageLinkMapItem;
+  UINT32 PackageLink;
+  AP_MAIL_INFO ApMailbox;
+
+  PackageLink = HT_LIST_TERMINAL;
+
+  GetApMailbox (&ApMailbox.Info, StdHeader);
+
+  if (ApMailbox.Fields.ModuleType != 0) {
+    ASSERT (FamilySpecificServices->PackageLinkMap != NULL);
+    // Use table to find this module's package link
+    PackageLinkMapItem = 0;
+    while ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
+      if (((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Module == ApMailbox.Fields.Module) &&
+          ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
+        PackageLink = (*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].PackageLink;
+        break;
+      }
+      PackageLinkMapItem++;
+    }
+  } else {
+    PackageLink = Link;
+  }
+  return PackageLink;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the platform's specified deemphasis levels for the current link.
+ *
+ * Search the platform's list for a match to the current link and also matching frequency.
+ * If a match is found, use the specified deemphasis levels.
+ *
+ * @param[in]       Socket                    The current Socket.
+ * @param[in]       Link                      The link on that socket.
+ * @param[in]       Frequency                 The frequency the link is set to.
+ * @param[in]       PlatformConfig            Config handle for platform specific information
+ * @param[in]       FamilySpecificServices    CPU specific support interface.
+ * @param[in]       StdHeader                 Config params for library, services.
+ *
+ * @return          The Deemphasis values for the link.
+ */
+UINT32
+STATIC
+GetLinkDeemphasis (
+  IN       UINT32                  Socket,
+  IN       UINT32                  Link,
+  IN       HT_FREQUENCIES          Frequency,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 Result;
+  CPU_HT_DEEMPHASIS_LEVEL *Match;
+  UINT32 PackageLink;
+
+  PackageLink = LookupPackageLink (Link, FamilySpecificServices, StdHeader);
+  // All External and Internal links have deemphasis level none as the default.
+  // However, it is expected that the platform BIOS will provide deemphasis levels for the external links.
+  Result = ((DCV_LEVEL_NONE) | (DEEMPHASIS_LEVEL_NONE));
+
+  if (PlatformConfig->PlatformDeemphasisList != NULL) {
+    Match = PlatformConfig->PlatformDeemphasisList;
+    while (Match->Socket != HT_LIST_TERMINAL) {
+      if (((Match->Socket == Socket) || (Match->Socket == HT_LIST_MATCH_ANY)) &&
+          ((Match->Link == PackageLink) ||
+           ((Match->Link == HT_LIST_MATCH_ANY) && (!IsDeemphasisLinkInternal (PackageLink))) ||
+           ((Match->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsDeemphasisLinkInternal (PackageLink)))) &&
+          ((Match->LoFreq <= Frequency) && (Match->HighFreq >= Frequency))) {
+        // Found a match, get the deemphasis value.
+        ASSERT ((MaxPlatformDeemphasisLevel > Match->DcvDeemphasis) | (MaxPlatformDeemphasisLevel > Match->ReceiverDeemphasis));
+        Result = ((1 << Match->DcvDeemphasis) | (1 << Match->ReceiverDeemphasis));
+        break;
+      } else {
+        Match++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program Deemphasis registers using BKDG values, for the platform specified levels.
+ *
+ * @TableEntryTypeMethod{::DeemphasisRegister}.
+ *
+ *
+ * @param[in]    Entry            The type specific entry data to be implemented (that is written).
+ * @param[in]    PlatformConfig   Config handle for platform specific information
+ * @param[in]    StdHeader        Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForDeemphasisEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->DeemphasisEntry.Levels.DeemphasisValues & ~(VALID_DEEMPHASIS_LEVELS)) == 0) &&
+          ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->DeemphasisEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (FamilySpecificServices->NextLinkHasHtPhyFeats (
+           FamilySpecificServices,
+           &CapabilitySet,
+           &Link,
+           &Entry->DeemphasisEntry.HtPhyEntry.TypeFeats,
+           &MatchedSublink1,
+           &Freq0,
+           &Freq1,
+           StdHeader)) {
+    if (DoesEntryTypeSpecificInfoMatch (
+          GetLinkDeemphasis (
+            MySocket,
+            (MatchedSublink1 ? (Link + 4) : Link),
+            (MatchedSublink1 ? Freq1 : Freq0),
+            PlatformConfig,
+            FamilySpecificServices,
+            StdHeader),
+          Entry->DeemphasisEntry.Levels.DeemphasisValues)) {
+      FamilySpecificServices->SetHtPhyRegister (
+        FamilySpecificServices,
+        &Entry->DeemphasisEntry.HtPhyEntry,
+        CapabilitySet,
+        Link,
+        StdHeader
+        );
+      IDS_HDT_CONSOLE (HT_TRACE, "Socket %d Module %d Sub-link %1d :\n  ----> running on HT3, %s Level is %s\n",
+        MySocket, MyModule,
+        ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & HTPHY_LINKTYPE_SL0_ALL) != 0) ? Link : (Link + 4),
+        ((Entry->DeemphasisEntry.Levels.DeemphasisValues & DCV_LEVELS_ALL) != 0) ? "DCV" : "Deemphasis",
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL_NONE) ? " 0 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__3) ? " - 3 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__8) ? " - 8 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11) ? " - 11 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11_8) ? " - 11 dB postcursor with - 8 dB precursor" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL_NONE) ? " 0 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__2) ? " - 2 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__3) ? " - 3 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__5) ? " - 5 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__6) ? " - 6 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__7) ? " - 7 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__8) ? " - 8 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__9) ? " - 9 dB" :
+        (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__11) ? " - 11 dB" : "Undefined");
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program HT Phy PCI registers which have complex frequency dependencies.
+ *
+ * @TableEntryTypeMethod{::HtPhyFreqRegister}.
+ *
+ * After matching a link for HT Features, check if the HT frequency matches the given range.
+ * If it does, get the northbridge frequency limits for implemented NB P-states and check if
+ * each matches the given range - range 0 and range 1 for each NB frequency, respectively.
+ * If all matches, apply the entry.
+ *
+ * @param[in]       Entry               The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForHtPhyFreqEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+  BOOLEAN               Temp1;
+  BOOLEAN               Temp2;
+  UINT32                NbFreq0;
+  UINT32                NbFreq1;
+  UINT32                NbDivisor0;
+  UINT32                NbDivisor1;
+
+  // Errors:  extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->HtPhyFreqEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (FamilySpecificServices->NextLinkHasHtPhyFeats (
+           FamilySpecificServices,
+           &CapabilitySet,
+           &Link,
+           &Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats,
+           &MatchedSublink1,
+           &Freq0,
+           &Freq1,
+           StdHeader)) {
+    // Check the HT Frequency for match to the range.
+    if (IsEitherCountInRange (
+          (MatchedSublink1 ? Freq1 : Freq0),
+          (MatchedSublink1 ? Freq1 : Freq0),
+          Entry->HtPhyFreqEntry.HtFreqCounts.HtFreqCountRanges)) {
+      // Get the NB Frequency, convert to 100's of MHz, then convert to equivalent HT encoding.  This supports
+      // NB frequencies from 800 MHz to 2600 MHz, which is currently greater than any processor supports.
+      OptionMultiSocketConfiguration.GetSystemNbPstateSettings (
+        (UINT32) 0,
+        PlatformConfig,
+        &NbFreq0,
+        &NbDivisor0,
+        &Temp1,
+        &Temp2,
+        StdHeader);
+
+      if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings (
+            (UINT32) 1,
+            PlatformConfig,
+            &NbFreq1,
+            &NbDivisor1,
+            &Temp1,
+            &Temp2,
+            StdHeader)) {
+        ASSERT (NbDivisor1 != 0);
+        NbFreq1 = (NbFreq1 / NbDivisor1);
+        NbFreq1 = (NbFreq1 / 100);
+        NbFreq1 = (NbFreq1 / 2) + 1;
+      } else {
+        NbFreq1 = 0;
+      }
+
+      ASSERT (NbDivisor0 != 0);
+      NbFreq0 = (NbFreq0 / NbDivisor0);
+      NbFreq0 = (NbFreq0 / 100);
+      NbFreq0 = (NbFreq0 / 2) + 1;
+      if (IsEitherCountInRange (NbFreq0, NbFreq1, Entry->HtPhyFreqEntry.NbFreqCounts.HtFreqCountRanges)) {
+        FamilySpecificServices->SetHtPhyRegister (
+          FamilySpecificServices,
+          &Entry->HtPhyFreqEntry.HtPhyEntry,
+          CapabilitySet,
+          Link,
+          StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Phy Performance Profile Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtPhyProfileRegister}.
+ *
+ * @param[in]     Entry             The HT Phy register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtPhyProfileEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  TABLE_ENTRY_DATA          HtPhyEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->InitialValues[5] == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (
+        PlatformProfile.PerformanceProfileValue,
+        Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue)) {
+    LibAmdMemFill (&HtPhyEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+    HtPhyEntry.HtPhyEntry = Entry->HtPhyProfileEntry.HtPhyEntry;
+    SetRegisterForHtPhyEntry (&HtPhyEntry, PlatformConfig, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Host PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtHostPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * For all HT links, check the link's feature set for a match to the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtHostEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  PCI_ADDR              PciAddress;
+  HT_HOST_FEATS         HtHostFeats;
+  UINT32                RegisterData;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->InitialValues[4] == 0) &&
+          ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
+          (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX));
+
+  HtHostFeats.HtHostValue = 0;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
+    if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) {
+      // Do the HT Host PCI register update.
+      PciAddress = CapabilitySet;
+      PciAddress.Address.Register += Entry->HtHostEntry.Address.Address.Register;
+      LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+      RegisterData = RegisterData & (~(Entry->HtHostEntry.Mask));
+      RegisterData = RegisterData | Entry->HtHostEntry.Data;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Host Performance PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtHostPerfPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * For all HT links, check the link's feature set for a match to the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtHostPerfEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  TABLE_ENTRY_DATA HtHostPciTypeEntryData;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->InitialValues[5] == 0) &&
+          ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
+          (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX));
+
+  // Check for any performance profile features.
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                      Entry->HtHostPerfEntry.PerformanceFeats.PerformanceProfileValue)) {
+    // Perform HT Host entry process.
+    LibAmdMemFill (&HtHostPciTypeEntryData, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+    HtHostPciTypeEntryData.HtHostEntry = Entry->HtHostPerfEntry.HtHostEntry;
+    SetRegisterForHtHostEntry (&HtHostPciTypeEntryData, PlatformConfig, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the HT Link Token Count registers.
+ *
+ * @TableEntryTypeMethod{::HtTokenPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Check the performance profile features.
+ * For all HT links, check the link's feature set for a match to the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The Link Token register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtLinkTokenEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN                 ProcessorCount;
+  UINTN                     SystemDegree;
+  UINT32                RegisterData;
+  PCI_ADDR              PciAddress;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
+          ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->HtTokenEntry.Mask != 0));
+
+  HtHostFeats.HtHostValue = 0;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  // Check if the actual processor count and SystemDegree are in either range.
+  ProcessorCount = GetNumberOfProcessors (StdHeader);
+  SystemDegree = GetSystemDegree (StdHeader);
+  if (IsEitherCountInRange (ProcessorCount, SystemDegree, Entry->HtTokenEntry.ConnectivityCount.ConnectivityCountRanges)) {
+    // Check for any performance profile features.
+    GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+    if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                        Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) {
+      // Check the link features.
+      Link = 0;
+      while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
+        if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) {
+          // Do the HT Host PCI register update. Token register are four registers, sublink 0 and 1 share fields.
+          // If sublink 0 is unconnected, we should let sublink 1 match.  If the links are ganged, of course only sublink 0 matches.
+          // If the links are unganged and both connected, the BKDG settings are for both coherent.
+          PciAddress = CapabilitySet;
+          PciAddress.Address.Register = Entry->HtTokenEntry.Address.Address.Register +
+            ((Link > 3) ? (((UINT32)Link - 4) * 4) : ((UINT32)Link * 4));
+          PciAddress.Address.Function = Entry->HtTokenEntry.Address.Address.Function;
+          LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+          RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask));
+          RegisterData = RegisterData | Entry->HtTokenEntry.Data;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Processor Token Counts PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::TokenPciRegister}.
+ *
+ * The table criteria then translate as:
+ * - 2 Socket, half populated  ==   Degree 1
+ * - 4 Socket, half populated   ==  Degree 2
+ * - 2 Socket, fully populated  ==  Degree 3
+ * - 4 Socket, fully populated  ==  Degree > 3.  (4 or 5 if 3P, 6 if 4P)
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForTokenPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN                     SystemDegree;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue)) {
+    SystemDegree = GetSystemDegree (StdHeader);
+    // Check if the system degree is in the range.
+    if (IsEitherCountInRange (SystemDegree, SystemDegree, Entry->TokenPciEntry.ConnectivityCount.ConnectivityCountRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->TokenPciEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Link Feature PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtFeatPciRegister}.
+ *
+ * Set a single field (that is, the register field is not in HT Host capability or a
+ * set of per link registers) in PCI config, based on HT link features and package type.
+ * This code is used for two cases: single link processors and multilink processors.
+ * For single link cases, the link will be tested for a match to the HT Features for the link.
+ * For multilink processors, the entry will match if @b any link is found which matches.
+ * For example, a setting can be applied based on coherent HT3 by matching coherent AND HT3.
+ *
+ * Make the core's PCI address.  Check the package type (currently more important to the single link case),
+ * and if matching, iterate through all links checking for an HT feature match until found or exhausted.
+ * If a match was found, pass the PCI entry data to the implementer for writing for the current core.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtFeaturePciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  UINT32                ProcessorPackageType;
+  BOOLEAN               IsMatch;
+  TABLE_ENTRY_DATA      PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->HtFeatPciEntry.PciEntry.Mask != 0) &&
+          ((Entry->HtFeatPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0));
+
+  HtHostFeats.HtHostValue = 0;
+  LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+  PciEntry.PciEntry = Entry->HtFeatPciEntry.PciEntry;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0);
+
+  ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->HtFeatPciEntry.PackageType.PackageTypeValue)) {
+    IsMatch = FALSE;
+    while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
+      if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtFeatPciEntry.LinkFeats.HtHostValue)) {
+        IsMatch = TRUE;
+        break;
+      }
+    }
+    if (IsMatch) {
+      // Do the PCI register update.
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Link PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtLinkPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Registers are processed for match per link, assuming sequential PCI address per link.
+ * Read - Modify - Write each matching link's PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtLinkPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  TABLE_ENTRY_DATA      PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->HtLinkPciEntry.PciEntry.Mask != 0) &&
+          ((Entry->HtLinkPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0));
+
+  HtHostFeats.HtHostValue = 0;
+  LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+  PciEntry.PciEntry = Entry->HtLinkPciEntry.PciEntry;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  Link = 0;
+  while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
+    if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtLinkPciEntry.LinkFeats.HtHostValue)) {
+      // Do the update to the link's non-Host PCI register, based on the entry address.
+      PciEntry.PciEntry.Address = Entry->HtLinkPciEntry.PciEntry.Address;
+      PciEntry.PciEntry.Address.Address.Register = PciEntry.PciEntry.Address.Address.Register + ((UINT32)Link * 4);
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm
new file mode 100644
index 0000000000..a41683f66c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm
@@ -0,0 +1,388 @@
+;/**
+; * @file
+; *
+; * Agesa pre-memory miscellaneous support, including ap halt loop.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU
+; * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+; */
+;*****************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*****************************************************************************
+
+    .XLIST
+    INCLUDE agesa.inc
+    INCLUDE cpcarmac.inc
+    .LIST
+
+    .586P
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   A B S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .MODEL flat
+    .CODE
+;======================================================================
+; ExecuteFinalHltInstruction:  Disables the stack and performs
+;                              a hlt instruction on an AP.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       eax, ebx, ecx, edx, esp
+;
+;======================================================================
+PUBLIC ExecuteFinalHltInstruction
+ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
+
+  mov esi,  StandardHeader        ; The code must reference all parameters to avoid a build warning
+  mov esi,  HaltFlags
+  mov edi,  ApMtrrSettingList
+  ; Do these special steps in case if the core is part of a compute unit
+  ; Note: The following bits are family specific flags, that gets set during build time,
+  ;          and indicates things like "family cache control methodology", etc.
+  ; esi bit0 = 0  -> not a Primary core
+  ; esi bit0 = 1  -> Primary core
+  ; esi bit1 = 0  -> Cache disable
+  ; esi bit1 = 1  -> Cache enable
+  .if (esi & 2h)
+    ; Set CombineCr0Cd bit
+    mov ecx,  CU_CFG3
+    _RDMSR
+    bts edx,  (COMBINE_CR0_CD - 32)
+    _WRMSR
+    ; Clear the CR0.CD bit
+    mov eax,  CR0                 ; Make sure cache is enabled for all APs
+    btr eax,  CR0_CD
+    btr eax,  CR0_NW
+    mov CR0,  eax                 ; Write back to CR0
+  .else
+    mov eax,  CR0                 ; Make sure cache is disabled for all APs
+    bts eax,  CR0_CD              ; Disable cache
+    bts eax,  CR0_NW
+    mov CR0,  eax                 ; Write back to CR0
+  .endif
+
+  .if (esi & 1h)
+    ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
+    mov esi,  edi                 ; Get ApMtrrSettingList
+
+    ; Configure the MTRRs on the AP so
+    ; when it runs remote code it will execute
+    ; out of RAM instead of ROM.
+
+    ; Disable MTRRs and turn on modification enable bit
+    mov ecx,  MTRR_SYS_CFG
+    _RDMSR
+    btr eax,  MTRR_VAR_DRAM_EN     ; Disable
+    bts eax,  MTRR_FIX_DRAM_MOD_EN  ;  Enable
+    btr eax,  MTRR_FIX_DRAM_EN     ; Disable
+    bts eax,  SYS_UC_LOCK_EN
+    _WRMSR
+
+    ; Setup default values for Fixed-Sized MTRRs
+    ; Set 7FFFh-00000h as WB
+    mov ecx,  AMD_AP_MTRR_FIX64k_00000
+    mov eax,  1E1E1E1Eh
+    mov edx,  eax
+    _WRMSR
+
+    ; Set 9FFFFh-80000h also as WB
+    mov ecx,  AMD_AP_MTRR_FIX16k_80000
+    _WRMSR
+
+    ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
+    mov ecx,  AMD_AP_MTRR_FIX16k_A0000
+    xor eax,  eax
+    xor edx,  edx
+    _WRMSR
+
+    ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
+    xor eax,  eax
+    xor edx,  edx
+    mov ecx,  AMD_AP_MTRR_FIX4k_C0000
+
+CDLoop:
+    _WRMSR
+    inc ecx
+    cmp ecx,  AMD_AP_MTRR_FIX4k_D8000
+    jbe CDLoop
+
+    ; Set FFFFFh-E0000h as Uncacheable Memory
+    mov eax,  18181818h
+    mov edx,  eax
+
+    mov ecx,  AMD_AP_MTRR_FIX4k_E0000
+
+EFLoop:
+    _WRMSR
+    inc ecx
+    cmp ecx,  AMD_AP_MTRR_FIX4k_F8000
+    jbe EFLoop
+
+    ; If IBV provided settings for Fixed-Sized MTRRs,
+    ; overwrite the default settings.
+    .if ((esi != 0) && (esi != 0FFFFFFFFh))
+      mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
+      ; While we are not at the end of the list
+      .while (ecx != CPU_LIST_TERMINAL)
+        ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
+        .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
+               (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
+          mov eax,  dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
+          mov edx,  dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
+          _WRMSR
+        .endif
+        add esi,  sizeof (AP_MTRR_SETTINGS)
+        mov ecx,  (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
+      .endw
+    .endif
+
+    ; Enable fixed-range and variable-range MTRRs
+    mov ecx,  AMD_MTRR_DEFTYPE
+    _RDMSR
+    bts eax, MTRR_DEF_TYPE_EN      ; MtrrDefTypeEn
+    bts eax, MTRR_DEF_TYPE_FIX_EN  ; MtrrDefTypeFixEn
+    _WRMSR
+
+    ; Enable Top-of-Memory setting
+    ; Enable use of RdMem/WrMem bits attributes
+    mov ecx,  MTRR_SYS_CFG
+    _RDMSR
+    bts eax,  MTRR_VAR_DRAM_EN     ; Enable
+    btr eax,  MTRR_FIX_DRAM_MOD_EN ; Disable
+    bts eax,  MTRR_FIX_DRAM_EN     ;  Enable
+    _WRMSR
+
+    mov esi, (1 SHL FLAG_IS_PRIMARY)
+  .else                                 ; end if primary core
+    xor esi, esi
+  .endif
+  ; Make sure not to touch any Shared MSR from this point on
+
+  AMD_DISABLE_STACK_FAMILY_HOOK
+
+  bt esi, FLAG_IS_PRIMARY
+  .if (carry?)
+    ; restore variable MTRR6 and MTRR7 to default states
+    mov ecx,  AMD_MTRR_VARIABLE_MASK7    ; clear MTRRPhysBase6 MTRRPhysMask6
+    xor eax,  eax                        ;  and MTRRPhysBase7 MTRRPhysMask7
+    xor edx,  edx
+    .while (cx >= AMD_MTRR_VARIABLE_BASE6)
+      _WRMSR
+      dec cx
+    .endw
+  .endif
+
+@@:
+  cli
+  hlt
+  jmp @B  ;ExecuteHltInstruction
+  ret
+ExecuteFinalHltInstruction ENDP
+
+;======================================================================
+; ExecuteHltInstruction:  Performs a hlt instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       eax, ebx, ecx, edx, esp
+;
+;======================================================================
+PUBLIC  ExecuteHltInstruction
+ExecuteHltInstruction PROC NEAR C
+  cli
+  hlt
+  ret
+ExecuteHltInstruction ENDP
+
+;======================================================================
+; NmiHandler:  Simply performs an IRET.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC  NmiHandler
+NmiHandler PROC NEAR C
+  iretd
+NmiHandler ENDP
+
+;======================================================================
+; GetCsSelector:  Returns the current protected mode CS selector.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC  GetCsSelector
+GetCsSelector PROC NEAR C, CsSelector:PTR
+  push ax
+  push ebx
+
+  call FarCallGetCs
+  mov  ebx, CsSelector
+  mov  [ebx], ax
+  pop  ebx
+  pop  ax
+  ret
+GetCsSelector ENDP
+
+;======================================================================
+; FarCallGetCs:
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+;======================================================================
+FarCallGetCs PROC FAR PRIVATE
+
+  mov  ax, ss:[esp + 4]
+  retf
+
+FarCallGetCs ENDP
+
+;======================================================================
+; SetIdtr:
+;
+;   In:
+;       @param[in]   IdtPtr Points to IDT table
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+;======================================================================
+PUBLIC  SetIdtr
+SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
+  mov   ebx, IdtPtr
+  lidt  fword ptr ss:[ebx]
+  ret
+SetIdtr ENDP
+
+;======================================================================
+; GetIdtr:
+;
+;   In:
+;       @param[in]   IdtPtr Points to IDT table
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+;======================================================================
+PUBLIC  GetIdtr
+GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
+  mov   ebx, IdtPtr
+  sidt  fword ptr ss:[ebx]
+  ret
+GetIdtr ENDP
+
+;======================================================================
+; ExecuteWbinvdInstruction:  Performs a wbinvd instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC  ExecuteWbinvdInstruction
+ExecuteWbinvdInstruction PROC NEAR C
+  wbinvd                        ; Write back the cache tag RAMs
+  ret
+ExecuteWbinvdInstruction ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.c
new file mode 100644
index 0000000000..bc80453a90
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.c
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 35978 $   @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// typedef unsigned int   uintptr_t;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+ExecuteFinalHltInstruction (
+	IN       UINT32 SharedCore,
+	IN       AP_MTRR_SETTINGS  *ApMtrrSettingsList,
+	IN       AMD_CONFIG_PARAMS *StdHeader
+	);
+
+VOID
+NmiHandler (
+	IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+	);
+
+VOID
+ExecuteHltInstruction (
+	IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+	);
+
+VOID
+ExecuteWbinvdInstruction (
+	IN       AMD_CONFIG_PARAMS *StdHeader
+	);
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/// Structure needed to load the IDTR using the lidt instruction
+
+VOID
+SetIdtr (
+	IN     IDT_BASE_LIMIT *IdtInfo,
+	IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+	)
+{
+	__lidt (IdtInfo);
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+GetCsSelector (
+	IN     UINT16 *Selector,
+	IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+	)
+{
+	static const UINT8 opcode [] = {0x8C, 0xC8, 0xC3}; // mov eax, cs; ret
+	*Selector = ((UINT16 (*)(void)) (size_t) opcode) ();
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+NmiHandler (
+	IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+	)
+{
+	static const UINT8 opcode [] = {0xCF};  // iret
+	((void (*)(void)) (size_t) opcode) ();
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+ExecuteHltInstruction (
+	IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+	)
+{
+	_disable ();
+	__halt ();
+}
+
+//---------------------------------------------------------------------------
+
+VOID
+ExecuteWbinvdInstruction (
+	IN       AMD_CONFIG_PARAMS *StdHeader
+	)
+{
+	__wbinvd ();
+}
+
+//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm
new file mode 100644
index 0000000000..7270b8f992
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm
@@ -0,0 +1,200 @@
+;/**
+; * @file
+; *
+; * Agesa pre-memory miscellaneous support, including ap halt loop.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU
+; * @e \$Revision: 10071 $   @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
+; */
+;*****************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*****************************************************************************
+
+ text  SEGMENT
+
+
+;======================================================================
+; ExecuteFinalHltInstruction:  Performs a hlt instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       eax, ebx, ecx, edx, esp
+;
+;======================================================================
+ExecuteFinalHltInstruction PROC PUBLIC
+@@:
+    cli
+    hlt
+    jmp @B ;ExecuteHltInstruction
+ExecuteFinalHltInstruction ENDP
+
+;======================================================================
+; ExecuteHltInstruction:  Performs a hlt instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       eax, ebx, ecx, edx, esp
+;
+;======================================================================
+ExecuteHltInstruction PROC PUBLIC
+    cli
+    hlt
+    ret
+ExecuteHltInstruction ENDP
+
+;======================================================================
+; NmiHandler:  Simply performs an IRET.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+NmiHandler PROC PUBLIC
+    iretq
+NmiHandler ENDP
+
+;======================================================================
+; GetCsSelector:  Returns the current protected mode CS selector.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+GetCsSelector PROC PUBLIC
+    ; This stub function is here to avoid compilation errors.
+    ; At this time, there is no need to provide a 64 bit function.
+    ret
+GetCsSelector ENDP
+
+;======================================================================
+; SetIdtr:
+;
+;   In:
+;       @param[in]   IdtPtr Points to IDT table
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+;======================================================================
+SetIdtr PROC PUBLIC
+    ; This stub function is here to avoid compilation errors.
+    ; At this time, there is no need to provide a 64 bit function.
+    ret
+SetIdtr ENDP
+
+;======================================================================
+; GetIdtr:
+;
+;   In:
+;       @param[in]   IdtPtr Points to IDT table
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+;======================================================================
+GetIdtr PROC PUBLIC
+    ; This stub function is here to avoid compilation errors.
+    ; At this time, there is no need to provide a 64 bit function.
+    ret
+GetIdtr ENDP
+
+;======================================================================
+; ExecuteWbinvdInstruction:  Performs a wbinvd instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+ExecuteWbinvdInstruction PROC PUBLIC
+    wbinvd                        ; Write back the cache tag RAMs
+    ret
+ExecuteWbinvdInstruction ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
new file mode 100644
index 0000000000..4ab535a3fe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+.include "src/vendorcode/amd/agesa/f15tn/gcccar.inc"
+
+.code32
+.align 4
+.globl ExecuteFinalHltInstruction
+    .type   ExecuteFinalHltInstruction, @function
+/* ExecuteFinalHltInstruction (
+  IN       UINT32 HaltFlags,
+  IN       AP_MTRR_SETTINGS  *ApMtrrSettingsList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+*/
+
+/* This function disables CAR. We don't care about the stack on this CPU */
+ExecuteFinalHltInstruction:
+  movl 4(%esp),  %esi               /* HaltFlags*/
+  movl 8(%esp),  %edi               /* ApMtrrSettingList */
+//1:	jmp 1b  //good
+/*  Do these special steps in case if the core is part of a compute unit
+ *  Note: The following bits are family specific flags, that gets set during build time,
+ *           and indicates things like "family cache control methodology", etc.
+ *  esi bit0 = 0  -> not a Primary core
+ *  esi bit0 = 1  -> Primary core
+ *  esi bit1 = 0  -> Cache disable
+ *  esi bit1 = 1  -> Cache enable
+ */
+
+  bt $1, %esi                     /* .if (esi & 2h) */
+  jz  0f
+    /* Set CombineCr0Cd bit */
+    movl $CU_CFG3,  %ecx
+    rdmsr
+    bts $(COMBINE_CR0_CD - 32),  %edx
+    wrmsr
+    /* Clear the CR0.CD bit */
+    movl %cr0,  %eax                /* Make sure cache is enabled for all APs */
+    btr $CR0_CD,  %eax
+    btr $CR0_NW,  %eax
+    mov %eax,  %cr0                 /*  Write back to CR0 */
+    jmp 1f                          /* .else */
+0:
+    movl %cr0,  %eax                /* Make sure cache is disabled for all APs */
+    bts $CR0_CD,  %eax              /* Disable cache */
+    bts $CR0_NW,  %eax
+    movl %eax,  %cr0                /* Write back to CR0 */
+1:                                  /* .endif */
+
+//	jmp 1b
+  bt $0,  %esi                     /* .if (esi & 1h) */
+  jz  2f
+    /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */
+    movl %edi,  %esi                /* Get ApMtrrSettingList */
+
+    /* Configure the MTRRs on the AP so
+     * when it runs remote code it will execute
+     * out of RAM instead of ROM.
+     */
+
+    /* Disable MTRRs and turn on modification enable bit */
+    movl $MTRR_SYS_CFG, %ecx
+    rdmsr
+    /* TODO: why comment this? */
+    //btr $MTRR_VAR_DRAM_EN,  %eax      /* Disable */
+    bts $MTRR_FIX_DRAM_MOD_EN,  %eax  /* Enable */
+    btr $MTRR_FIX_DRAM_EN,  %eax      /* Disable */
+    //bts $SYS_UC_LOCK_EN,  %eax
+    wrmsr
+
+    /* Setup default values for Fixed-Sized MTRRs */
+    /* Set 7FFFh-00000h as WB */
+    movl $AMD_AP_MTRR_FIX64k_00000,  %ecx
+    movl $0x1E1E1E1E,  %eax
+    movl %eax,  %edx
+    wrmsr
+
+    /* Set 9FFFFh-80000h also as WB */
+    movl $AMD_AP_MTRR_FIX16k_80000,  %ecx
+    wrmsr
+
+    /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */
+    movl $AMD_AP_MTRR_FIX16k_A0000,  %ecx
+    xorl %eax,  %eax
+    xorl %edx,  %edx
+    wrmsr
+
+    /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */
+    xorl %eax,  %eax
+    xorl %edx,  %edx
+    movl $AMD_AP_MTRR_FIX4k_C0000,  %ecx
+
+CDLoop:
+    wrmsr
+    inc %ecx
+    cmp $AMD_AP_MTRR_FIX4k_D8000,  %ecx
+    jbe CDLoop
+
+    /* Set FFFFFh-E0000h as Uncacheable Memory */
+    movl $0x18181818,  %eax
+    movl %eax,  %edx
+
+    mov $AMD_AP_MTRR_FIX4k_E0000, %ecx
+
+EFLoop:
+    wrmsr
+    inc %ecx
+    cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx
+    jbe EFLoop
+
+    /* If IBV provided settings for Fixed-Sized MTRRs,
+     * overwrite the default settings. */
+    cmp $0,  %esi           /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */
+    jz 4f
+    cmp $0xFFFFFFFF,  %esi
+    jz 4f
+      5:
+      mov (%esi),  %ecx         /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */
+      /* While we are not at the end of the list */
+      cmp $CPU_LIST_TERMINAL,  %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/
+      je 4f
+        /* TODO - coreboot isn't checking for valid data.
+         * Ensure that the MSR address is valid for Fixed-Sized MTRRs */
+        /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
+               (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \
+               (ecx == AMD_AP_MTRR_FIX16k_A0000))
+         */
+          mov 4(%esi),  %eax                /* MsrData */
+          mov 8(%esi),  %edx                /* MsrData */
+          wrmsr
+        /* .endif */
+        add $12,  %esi                   /* sizeof (AP_MTRR_SETTINGS) */
+        jmp 5b                               /* .endw */
+    4: /* .endif */
+
+    /* Enable fixed-range and variable-range MTRRs */
+    mov $AMD_MTRR_DEFTYPE,  %ecx
+    rdmsr
+    bts $MTRR_DEF_TYPE_EN,  %eax      /* MtrrDefTypeEn */
+    bts $MTRR_DEF_TYPE_FIX_EN,  %eax  /* MtrrDefTypeFixEn */
+    wrmsr
+
+    /* Enable Top-of-Memory setting */
+    /* Enable use of RdMem/WrMem bits attributes */
+    mov $MTRR_SYS_CFG,  %ecx
+    rdmsr
+    /* TODO: */
+    //bts $MTRR_VAR_DRAM_EN,  %eax       /* Enable */
+    btr $MTRR_FIX_DRAM_MOD_EN,  %eax   /* Disable */
+    bts $MTRR_FIX_DRAM_EN,  %eax       /* Enable */
+    wrmsr
+
+    bts $FLAG_IS_PRIMARY,  %esi
+    jmp 3f /* .else                            ; end if primary core */
+  2:
+    xor %esi,  %esi
+  3: /* .endif*/
+
+//8:	jmp 8b //bad
+  /* Make sure not to touch any Shared MSR from this point on */
+
+    AMD_DISABLE_STACK_FAMILY_HOOK
+
+    /* restore variable MTTR6 and MTTR7 to default states */
+    bt $FLAG_IS_PRIMARY, %esi                     /* .if (esi & 1h) */
+    jz  6f
+      movl $AMD_MTRR_VARIABLE_MASK7,  %ecx  /* clear MTRRPhysBase6 MTRRPhysMask6 */
+      xor %eax,  %eax                         /* and MTRRPhysBase7 MTRRPhysMask7 */
+      xor %edx,  %edx
+      cmp $AMD_MTRR_VARIABLE_BASE6,  %ecx                      /* .while (cl < 010h) */
+      jl 6f
+      wrmsr
+      dec %ecx
+    6:                                  /* .endw */
+
+  xor  %eax,  %eax
+
+7:
+  cli
+  hlt
+  jmp 7b  /* ExecuteHltInstruction */
+
+    .size   ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c
new file mode 100644
index 0000000000..a24dd11789
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c
@@ -0,0 +1,1469 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU APIC related utility functions.
+ *
+ * Contains code that provides mechanism to invoke and control APIC communication.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUAPICUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* ApFlags bits */
+#define AP_TASK_HAS_INPUT    0x00000001ul
+#define AP_TASK_HAS_OUTPUT   0x00000002ul
+#define AP_RETURN_PARAMS     0x00000004ul
+#define AP_END_AT_HLT        0x00000008ul
+#define AP_PASS_EARLY_PARAMS 0x00000010ul
+
+#define XFER_ELEMENT_SIZE    sizeof (UINT32)
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef VOID F_CPU_AMD_NMI_HANDLER (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+ApUtilSetupIdtForHlt (
+  IN       IDT_DESCRIPTOR *NmiIdtDescPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+STATIC
+ApUtilRemoteRead (
+  IN       UINT32 TargetApicId,
+  IN       UINT8  RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilLocalWrite (
+  IN       UINT32 RegAddr,
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+STATIC
+ApUtilLocalRead (
+  IN       UINT32 RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilGetLocalApicBase (
+     OUT   UINT64 *ApicBase,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+STATIC
+ApUtilCalculateUniqueId (
+  IN      UINT8 Socket,
+  IN      UINT8 Core,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilFireDirectedNmi (
+  IN      UINT32 TargetApicId,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilReceivePointer (
+  IN       UINT32 TargetApicId,
+     OUT   VOID  **ReturnPointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilTransmitPointer (
+  IN       UINT32 TargetApicId,
+  IN       VOID  **Pointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+PerformFinalHalt (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LocalApicInitialization (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+LocalApicInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern
+VOID
+ExecuteHltInstruction (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern
+VOID
+NmiHandler (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern
+VOID
+ExecuteFinalHltInstruction (
+  IN       UINT32 SharedCore,
+  IN       AP_MTRR_SETTINGS  *ApMtrrSettingsList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Local APIC.
+ *
+ * This function determines and programs the appropriate APIC ID value
+ * for the executing core.  This code must be run after HT initialization
+ * is complete.
+ *
+ *  @param[in]     CpuEarlyParamsPtr  Service parameters.
+ *  @param[in]     StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+LocalApicInitialization (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT32    CurrentCore;
+  UINT32    CurrentNodeNum;
+  UINT32    CoreIdBits;
+  UINT32    Mnc;
+  UINT32    ProcessorCount;
+  UINT32    ProcessorApicIndex;
+  UINT32    IoApicNum;
+  UINT32    StartLocalApicId;
+  UINT64    LocalApicBase;
+  UINT32    TempVar_a;
+  UINT64    MsrData;
+  UINT64    Address;
+  CPUID_DATA  CpuidData;
+
+  // Local variables default values
+  IoApicNum = CpuEarlyParamsPtr->PlatformConfig.NumberOfIoApics;
+
+  GetCurrentCore (&CurrentCore, StdHeader);
+  GetCurrentNodeNum (&CurrentNodeNum, StdHeader);
+
+  // Get Mnc
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader);
+  CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12;
+  Mnc = 1 << (CoreIdBits & 0x000F);
+
+  // Get ProcessorCount in the system
+  ProcessorCount = GetNumberOfProcessors (StdHeader);
+
+  // Get the APIC Index of this processor.
+  ProcessorApicIndex = GetProcessorApicIndex (CurrentNodeNum, StdHeader);
+
+  TempVar_a = (Mnc * ProcessorCount) + IoApicNum;
+  ASSERT (TempVar_a < 255);
+
+  // Apply apic enumeration rules
+  // For systems with >= 16 APICs, put the IO-APICs at 0..n and
+  // put the local-APICs at m..z
+  // For systems with < 16 APICs, put the Local-APICs at 0..n and
+  // put the IO-APICs at (n + 1)..z
+  // This is needed because many IO-APIC devices only have 4 bits
+  // for their APIC id and therefore must reside at 0..15
+  StartLocalApicId = 0;
+  if (TempVar_a >= 16) {
+    if (IoApicNum >= 1) {
+      StartLocalApicId = (IoApicNum - 1) / Mnc;
+      StartLocalApicId = (StartLocalApicId + 1) * Mnc;
+    }
+  }
+
+  // Set local apic id
+  TempVar_a = (ProcessorApicIndex * Mnc) + CurrentCore + StartLocalApicId;
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Node %d core %d APIC ID = 0x%x\n", CurrentNodeNum, CurrentCore, TempVar_a);
+  TempVar_a = TempVar_a << APIC20_ApicId;
+
+  // Enable local apic id
+  LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader);
+  MsrData |= APIC_ENABLE_BIT;
+  LibAmdMsrWrite (MSR_APIC_BAR, &MsrData, StdHeader);
+
+  // Get local apic base Address
+  ApUtilGetLocalApicBase (&LocalApicBase, StdHeader);
+
+  Address = LocalApicBase + APIC_ID_REG;
+  LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Local APIC at the AmdInitEarly entry point.
+ *
+ * This function acts as a wrapper for calling the LocalApicInitialization
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+LocalApicInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuLocalApicInit, StdHeader);
+  LocalApicInitialization (EarlyParams, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for all APs in the system.
+ *
+ * This routine puts the AP cores in an infinite loop in which the cores
+ * will poll their masters, waiting to be told to perform a task.  At early,
+ * all socket-relative core zeros will receive their tasks from the BSC.
+ * All others will receive their tasks from the core zero of their local
+ * processor.  At the end of AmdInitEarly, all cores will switch to receiving
+ * their tasks from the BSC.
+ *
+ * @param[in]     StdHeader       Handle to config for library and services.
+ * @param[in]     CpuEarlyParams  AMD_CPU_EARLY_PARAMS pointer.
+ *
+ */
+VOID
+ApEntry (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  UINT8   RemoteCmd;
+  UINT8   SourceSocket;
+  UINT8   CommandStart;
+  UINT32  ApFlags;
+  UINT32  FuncType;
+  UINT32  ReturnCode;
+  UINT32  CurrentSocket;
+  UINT32  CurrentCore;
+  UINT32  *InputDataPtr;
+  UINT32  BscSocket;
+  UINT32  Ignored;
+  UINT32  TargetApicId;
+  AP_FUNCTION_PTR FuncAddress;
+  IDT_DESCRIPTOR IdtDesc[32];
+  AP_DATA_TRANSFER DataTransferInfo;
+  AGESA_STATUS IgnoredSts;
+
+  ASSERT (!IsBsp (StdHeader, &IgnoredSts));
+
+  // Initialize local variables
+  ReturnCode = 0;
+  DataTransferInfo.DataTransferFlags = 0;
+  InputDataPtr = NULL;
+
+  // Determine the executing core's socket and core numbers
+  IdentifyCore (StdHeader, &CurrentSocket, &Ignored, &CurrentCore, &IgnoredSts);
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Socket %d core %d begin AP tasking engine\n", CurrentSocket, CurrentCore);
+
+  // Determine the BSC's socket number
+  GetSocketModuleOfNode ((UINT32) 0x00000000, &BscSocket, &Ignored, StdHeader);
+
+  // Setup Interrupt Descriptor Table for sleep mode
+  ApUtilSetupIdtForHlt (&IdtDesc[2], StdHeader);
+
+  // Indicate to the BSC that we have reached the tasking engine
+  ApUtilWriteControlByte (CORE_IDLE, StdHeader);
+
+  if (CurrentCore == 0) {
+    // Core 0s receive their tasks from the BSC
+    SourceSocket = (UINT8) BscSocket;
+  } else {
+    // All non-zero cores receive their tasks from the core 0 of their socket
+    SourceSocket = (UINT8) CurrentSocket;
+  }
+
+  GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader);
+
+  // Determine the unique value that the master will write when it has a task
+  // for this core to perform.
+  CommandStart = ApUtilCalculateUniqueId (
+                   (UINT8)CurrentSocket,
+                   (UINT8)CurrentCore,
+                   StdHeader
+                   );
+  for (;;) {
+    RemoteCmd = ApUtilReadRemoteControlByte (TargetApicId, StdHeader);
+    if (RemoteCmd == CommandStart) {
+      ApFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader);
+
+      ApUtilReceivePointer (TargetApicId, (VOID **) &FuncAddress, StdHeader);
+
+      FuncType = ApFlags & (UINT32) (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS);
+      if ((ApFlags & AP_TASK_HAS_INPUT) != 0) {
+        DataTransferInfo.DataSizeInDwords = 0;
+        DataTransferInfo.DataPtr = NULL;
+        DataTransferInfo.DataTransferFlags = 0;
+        if (ApUtilReceiveBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader) == AGESA_ERROR) {
+          // There is not enough space to put the input data on the heap.  Undefined behavior is about
+          // to result.
+          IDS_ERROR_TRAP;
+        }
+        InputDataPtr = (UINT32 *) DataTransferInfo.DataPtr;
+      }
+      ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+      switch (FuncType) {
+      case 0:
+        FuncAddress.PfApTask (StdHeader);
+        break;
+      case AP_TASK_HAS_INPUT:
+        FuncAddress.PfApTaskI (InputDataPtr, StdHeader);
+        break;
+      case AP_PASS_EARLY_PARAMS:
+        FuncAddress.PfApTaskC (StdHeader, CpuEarlyParams);
+        break;
+      case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS):
+        FuncAddress.PfApTaskIC (InputDataPtr, StdHeader, CpuEarlyParams);
+        break;
+      case AP_TASK_HAS_OUTPUT:
+        ReturnCode = FuncAddress.PfApTaskO (StdHeader);
+        break;
+      case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT):
+        ReturnCode = FuncAddress.PfApTaskIO (InputDataPtr, StdHeader);
+        break;
+      case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+        ReturnCode = FuncAddress.PfApTaskOC (StdHeader, CpuEarlyParams);
+        break;
+      case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+        ReturnCode = FuncAddress.PfApTaskIOC (InputDataPtr, StdHeader, CpuEarlyParams);
+        break;
+      default:
+        ReturnCode = 0;
+        break;
+      }
+      if (((ApFlags & AP_RETURN_PARAMS) != 0)) {
+        ApUtilTransmitBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader);
+      }
+      if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) {
+        ApUtilWriteDataDword (ReturnCode, StdHeader);
+      }
+      if ((ApFlags & AP_END_AT_HLT) != 0) {
+        RemoteCmd = CORE_IDLE_HLT;
+      } else {
+        ApUtilWriteControlByte (CORE_IDLE, StdHeader);
+      }
+    }
+    if (RemoteCmd == CORE_IDLE_HLT) {
+      SourceSocket = (UINT8) BscSocket;
+      GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader);
+      ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader);
+      ExecuteHltInstruction (StdHeader);
+      ApUtilWriteControlByte (CORE_IDLE, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads the 'control byte' on the designated remote core.
+ *
+ * This function will read the current contents of the control byte
+ * on the designated core using the APIC remote read inter-
+ * processor interrupt sequence.
+ *
+ * @param[in]      TargetApicId  Local APIC ID of the desired core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ * @return         The current value of the remote cores control byte
+ *
+ */
+UINT8
+ApUtilReadRemoteControlByte (
+  IN       UINT32 TargetApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  ControlByte;
+  UINT32 ApicRegister;
+
+  ApicRegister = ApUtilRemoteRead (TargetApicId, APIC_CTRL_DWORD, StdHeader);
+  ControlByte = (UINT8) ((ApicRegister & APIC_CTRL_MASK) >> APIC_CTRL_SHIFT);
+  return (ControlByte);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Writes the 'control byte' on the executing core.
+ *
+ * This function writes data to a local APIC offset used in inter-
+ * processor communication.
+ *
+ * @param[in]       Value
+ * @param[in]       StdHeader
+ *
+ */
+VOID
+ApUtilWriteControlByte (
+  IN       UINT8 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ApicRegister;
+
+  ApicRegister = ApUtilLocalRead (APIC_CTRL_REG, StdHeader);
+  ApicRegister = ((ApicRegister & ~APIC_CTRL_MASK) | (UINT32) (Value << APIC_CTRL_SHIFT));
+  ApUtilLocalWrite (APIC_CTRL_REG, ApicRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads the 'data dword' on the designated remote core.
+ *
+ * This function will read the current contents of the data dword
+ * on the designated core using the APIC remote read inter-
+ * processor interrupt sequence.
+ *
+ * @param[in]      TargetApicId  Local APIC ID of the desired core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ * @return         The current value of the remote core's data dword
+ *
+ */
+UINT32
+ApUtilReadRemoteDataDword (
+  IN       UINT32 TargetApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return (ApUtilRemoteRead (TargetApicId, APIC_DATA_DWORD, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Writes the 'data dword' on the executing core.
+ *
+ * This function writes data to a local APIC offset used in inter-
+ * processor communication.
+ *
+ * @param[in]      Value        Value to write
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+ApUtilWriteDataDword (
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ApUtilLocalWrite (APIC_DATA_REG, Value, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the given task on the specified local core.
+ *
+ * This function is used to invoke an AP to run a specified AGESA
+ * procedure.  It can only be called by cores that have subordinate
+ * APs -- the BSC at POST, or any socket-relative core 0s at Early.
+ *
+ * @param[in]      Socket       Socket number of the target core
+ * @param[in]      Core         Core number of the target core
+ * @param[in]      TaskPtr      Function descriptor
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @return         Return value of the task that the AP core ran,
+ *                 or zero if the task was VOID.
+ *
+ */
+UINT32
+ApUtilRunCodeOnSocketCore (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  CoreId;
+  UINT8  CurrentStatus;
+  UINT8  WaitStatus[3];
+  UINT32 ApFlags;
+  UINT32 ReturnCode;
+  UINT32 TargetApicId;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  ApFlags = 0;
+  ReturnCode = 0;
+
+  CoreId = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
+
+  GetLocalApicIdForCore (Socket, Core, &TargetApicId, StdHeader);
+
+  if (TaskPtr->DataTransfer.DataSizeInDwords != 0) {
+    ApFlags |= AP_TASK_HAS_INPUT;
+    if (((TaskPtr->ExeFlags & RETURN_PARAMS) != 0) &&
+        ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) {
+      ApFlags |= AP_RETURN_PARAMS;
+    }
+  }
+
+  if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) {
+    ApFlags |= AP_TASK_HAS_OUTPUT;
+  }
+
+  if ((TaskPtr->ExeFlags & END_AT_HLT) != 0) {
+    ApFlags |= AP_END_AT_HLT;
+  }
+
+  if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) {
+    ApFlags |= AP_PASS_EARLY_PARAMS;
+  }
+
+  WaitStatus[0] = CORE_IDLE;
+  WaitStatus[1] = CORE_IDLE_HLT;
+  WaitStatus[2] = CORE_UNAVAILABLE;
+  WaitForStatus.Status = WaitStatus;
+  WaitForStatus.NumberOfElements = 3;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+  CurrentStatus = ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+
+  if (CurrentStatus != CORE_UNAVAILABLE) {
+    ApUtilWriteDataDword (ApFlags, StdHeader);
+    ApUtilWriteControlByte (CoreId, StdHeader);
+
+    if (CurrentStatus == CORE_IDLE_HLT) {
+      ApUtilFireDirectedNmi (TargetApicId, StdHeader);
+    }
+
+    ApUtilTransmitPointer (TargetApicId, (VOID **) &TaskPtr->FuncAddress, StdHeader);
+
+    if ((ApFlags & AP_TASK_HAS_INPUT) != 0) {
+      ApUtilTransmitBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader);
+    }
+
+    if ((TaskPtr->ExeFlags & WAIT_FOR_CORE) != 0) {
+      if (((ApFlags & AP_TASK_HAS_INPUT) != 0) &&
+          ((ApFlags & AP_RETURN_PARAMS) != 0) &&
+          ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) {
+        if (ApUtilReceiveBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader) == AGESA_ERROR) {
+          // There is not enough space to put the return data.  This should never occur.  If it
+          // does, this would point to strange heap corruption.
+          IDS_ERROR_TRAP;
+        }
+      }
+
+      ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+      if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) {
+        ReturnCode = ApUtilReadRemoteDataDword (TargetApicId, StdHeader);
+      }
+    }
+  } else {
+    ReturnCode = 0;
+  }
+  return (ReturnCode);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Waits for a remote core's control byte value to either be equal or
+ * not equal to any number of specified values.
+ *
+ * This function will loop doing remote read IPIs until the remote core's
+ * control byte becomes one of the values in the input array if the input
+ * flags are set for equality.  Otherwise, the loop will continue until
+ * the control byte value is not equal to one of the elements in the
+ * array.  The caller can also specify an iteration count for timeout
+ * purposes.
+ *
+ * @param[in]      TargetApicId   Local APIC ID of the desired core
+ * @param[in]      WaitParamsPtr  Wait parameter structure
+ * @param[in]      StdHeader      Configuration parameteres pointer
+ *
+ * @return         The current value of the remote core's control byte
+ *
+ */
+UINT8
+ApUtilWaitForCoreStatus (
+  IN       UINT32 TargetApicId,
+  IN       AP_WAIT_FOR_STATUS *WaitParamsPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BOOLEAN  IsEqual;
+  UINT8 CoreStatus;
+  UINT8 i;
+  UINT8 j;
+
+  CoreStatus = 0;
+  for (i = 0; (WaitParamsPtr->RetryCount == WAIT_INFINITELY) ||
+              (i < WaitParamsPtr->RetryCount); ++i) {
+    CoreStatus = ApUtilReadRemoteControlByte (TargetApicId, StdHeader);
+    // Determine whether or not the current remote status is equal
+    // to an element in the array.
+    IsEqual = FALSE;
+    for (j = 0; !IsEqual && j < WaitParamsPtr->NumberOfElements; ++j) {
+      if (CoreStatus == WaitParamsPtr->Status[j]) {
+        IsEqual = TRUE;
+      }
+    }
+    if ((((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) != 0) && IsEqual) ||
+        (((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) == 0) && !IsEqual)) {
+      break;
+    }
+  }
+  return (CoreStatus);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the AP task on the executing core.
+ *
+ * @param[in]      TaskPtr      Function descriptor
+ * @param[in]      StdHeader    Configuration parameters pointer
+ * @param[in]      ConfigParams Entry point CPU parameters pointer
+ *
+ * @return         Return value of the task, or zero if the task
+ *                 was VOID.
+ *
+ */
+UINT32
+ApUtilTaskOnExecutingCore (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  )
+{
+  UINT32   InvocationOptions;
+  UINT32   ReturnCode;
+
+  ReturnCode = 0;
+  InvocationOptions = 0;
+
+  if (TaskPtr->DataTransfer.DataSizeInDwords != 0) {
+    InvocationOptions |= AP_TASK_HAS_INPUT;
+  }
+  if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) {
+    InvocationOptions |= AP_TASK_HAS_OUTPUT;
+  }
+  if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) {
+    InvocationOptions |= AP_PASS_EARLY_PARAMS;
+  }
+
+  switch (InvocationOptions) {
+  case 0:
+    TaskPtr->FuncAddress.PfApTask (StdHeader);
+    break;
+  case AP_TASK_HAS_INPUT:
+    TaskPtr->FuncAddress.PfApTaskI (TaskPtr->DataTransfer.DataPtr, StdHeader);
+    break;
+  case AP_PASS_EARLY_PARAMS:
+    TaskPtr->FuncAddress.PfApTaskC (StdHeader, ConfigParams);
+    break;
+  case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS):
+    TaskPtr->FuncAddress.PfApTaskIC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams);
+    break;
+  case AP_TASK_HAS_OUTPUT:
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskO (StdHeader);
+    break;
+  case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT):
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskIO (TaskPtr->DataTransfer.DataPtr, StdHeader);
+    break;
+  case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskOC (StdHeader, ConfigParams);
+    break;
+  case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskIOC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams);
+    break;
+  default:
+    ReturnCode = 0;
+    break;
+  }
+  return (ReturnCode);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
+ *
+ * This function prepares the executing AP core for recovering from a hlt
+ * instruction by initializing its IDTR.
+ *
+ * @param[in]        NmiIdtDescPtr Pointer to a writable IDT entry to
+ *                                 be used for NMIs
+ * @param[in]        StdHeader     Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilSetupIdtForHlt (
+  IN       IDT_DESCRIPTOR *NmiIdtDescPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   DescSize;
+  UINT64  HandlerOffset;
+  UINT64  EferRegister;
+  IDT_BASE_LIMIT IdtInfo;
+
+  LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader);
+  if ((EferRegister & 0x100) != 0) {
+    DescSize = 16;
+  } else {
+    DescSize = 8;
+  }
+
+  HandlerOffset = (UINT64) (UINTN) NmiHandler;
+  NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF;
+  NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16);
+  GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);
+  NmiIdtDescPtr->Flags = IDT_DESC_PRESENT | IDT_DESC_TYPE_INT32;
+  NmiIdtDescPtr->Rsvd = 0;
+  NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32);
+  NmiIdtDescPtr->Rsvd64 = 0;
+  IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1);
+  IdtInfo.Base = (UINT64) (UINTN) NmiIdtDescPtr - (DescSize * 2);
+  IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader);
+  SetIdtr (&IdtInfo , StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate the APIC ID for a given core.
+ *
+ * Get the current node's apic id and deconstruct it to the base id of local apic id space.
+ * Then construct the target's apic id using that base.
+ * @b Assumes: The target Socket and Core exist!
+ * Other Notes:
+ *  - Must run after HT initialization is complete.
+ *  - Code sync: This calculation MUST match the assignment
+ *    calculation done above in LocalApicInitializationAtEarly function.
+ *  - Assumes family homogeneous population of all sockets.
+ *
+ *  @param[in]      TargetSocket   The socket in which the Core's Processor is installed.
+ *  @param[in]      TargetCore     The Core on that Processor
+ *  @param[out]     LocalApicId    Its APIC Id
+ *  @param[in]      StdHeader      Handle to header for library and services.
+ *
+ */
+VOID
+GetLocalApicIdForCore (
+  IN       UINT32            TargetSocket,
+  IN       UINT32            TargetCore,
+     OUT   UINT32            *LocalApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  CoreIdBits;
+  UINT32  CurrentNode;
+  UINT32  CurrentCore;
+  UINT32  TargetNode;
+  UINT32  MaxCoresInProcessor;
+  UINT32  TotalCores;
+  UINT32  CurrentLocalApicId;
+  UINT64  LocalApicBase;
+  UINT32  TempVar_a;
+  UINT64  Address;
+  UINT32  ProcessorApicIndex;
+  BOOLEAN ReturnResult;
+  CPUID_DATA  CpuidData;
+
+  TargetNode = 0;
+
+  // Get local apic base Address
+  ApUtilGetLocalApicBase (&LocalApicBase, StdHeader);
+  Address = LocalApicBase + APIC_ID_REG;
+
+  LibAmdMemRead (AccessWidth32, Address, &TempVar_a, StdHeader);
+
+  // ApicId [7:0]
+  CurrentLocalApicId = (TempVar_a >> APIC20_ApicId) & 0x000000FF;
+
+  GetCurrentNodeAndCore (&CurrentNode, &CurrentCore, StdHeader);
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader);
+  CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12;
+  MaxCoresInProcessor = (1 << CoreIdBits);
+
+  // Get the APIC Index of this processor.
+  ProcessorApicIndex = GetProcessorApicIndex (CurrentNode, StdHeader);
+
+  TotalCores = (MaxCoresInProcessor * ProcessorApicIndex) + CurrentCore;
+  CurrentLocalApicId -= TotalCores;
+
+  // Use the Node Id of TargetSocket, Module 0.  No socket transitions are missed or added,
+  // even if the TargetCore is not on Module 0 in that processor and that's all that matters now.
+  ReturnResult = GetNodeId (TargetSocket, 0, (UINT8 *)&TargetNode, StdHeader);
+  ASSERT (ReturnResult);
+
+  // Get the APIC Index of this processor.
+  ProcessorApicIndex = GetProcessorApicIndex (TargetNode, StdHeader);
+
+  CurrentLocalApicId += ((MaxCoresInProcessor * ProcessorApicIndex) + TargetCore);
+  *LocalApicId = CurrentLocalApicId;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely passes a buffer to the designated remote core.
+ *
+ * This function uses a sequence of remote reads to transmit a data
+ * buffer, one UINT32 at a time.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[in]      BufferInfo   Information about the buffer to pass, and
+ *                              how to pass it
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+ApUtilTransmitBuffer (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN       AP_DATA_TRANSFER  *BufferInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  TargetCore;
+  UINT8  MyUniqueId;
+  UINT8  CurrentStatus;
+  UINT32 *CurrentPtr;
+  UINT32 i;
+  UINT32 MyCore;
+  UINT32 MySocket;
+  UINT32 Ignored;
+  UINT32 TargetApicId;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+  AGESA_STATUS IgnoredSts;
+
+  GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader);
+
+  if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
+    ApUtilWriteDataDword ((UINT32) 0x00000000, StdHeader);
+  } else {
+    ApUtilWriteDataDword ((UINT32) BufferInfo->DataSizeInDwords, StdHeader);
+  }
+  TargetCore = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
+
+  ApUtilWriteControlByte (TargetCore, StdHeader);
+
+  IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &IgnoredSts);
+
+  MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader);
+
+  WaitForStatus.Status = &MyUniqueId;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+
+  ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+  ApUtilWriteDataDword (BufferInfo->DataTransferFlags, StdHeader);
+
+  ApUtilWriteControlByte (CORE_DATA_FLAGS_READY, StdHeader);
+  WaitForStatus.WaitForStatusFlags = 0;
+  ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+  if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
+    ApUtilTransmitPointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader);
+  } else {
+    ApUtilWriteControlByte (CORE_STS_DATA_READY_1, StdHeader);
+    CurrentStatus = CORE_STS_DATA_READY_0;
+    WaitForStatus.Status = &CurrentStatus;
+    WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+    ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+    WaitForStatus.WaitForStatusFlags = 0;
+    CurrentPtr = (UINT32 *) BufferInfo->DataPtr;
+    for (i = 0; i < BufferInfo->DataSizeInDwords; ++i) {
+      ApUtilWriteDataDword (*CurrentPtr++, StdHeader);
+      ApUtilWriteControlByte (CurrentStatus, StdHeader);
+      ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+      CurrentStatus ^= 0x01;
+    }
+  }
+  ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely receives a buffer from the designated remote core.
+ *
+ * This function uses a sequence of remote reads to receive a data
+ * buffer, one UINT32 at a time.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[in]      BufferInfo   Information about where to place the buffer
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @retval         AGESA_SUCCESS Transaction was successful
+ * @retval         AGESA_ALERT   The non-NULL desired location to place
+ *                               the buffer was not used as the buffer
+ *                               resides in a shared memory space.  The
+ *                               input data pointer has changed.
+ * @retval         AGESA_ERROR   There is not enough room to receive the
+ *                               buffer.
+ *
+ */
+AGESA_STATUS
+ApUtilReceiveBuffer (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN OUT   AP_DATA_TRANSFER  *BufferInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    MyUniqueId;
+  UINT8    SourceUniqueId;
+  UINT8    CurrentStatus;
+  UINT32   i;
+  UINT32   MySocket;
+  UINT32   MyCore;
+  UINT32   Ignored;
+  UINT32   *CurrentPtr;
+  UINT32   TransactionSize;
+  UINT32   TargetApicId;
+  AGESA_STATUS ReturnStatus;
+  ALLOCATE_HEAP_PARAMS HeapMalloc;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  ReturnStatus = AGESA_SUCCESS;
+  IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &ReturnStatus);
+
+  MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader);
+
+  GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader);
+
+  WaitForStatus.Status = &MyUniqueId;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+
+  ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+  TransactionSize = ApUtilReadRemoteDataDword (TargetApicId, StdHeader);
+
+  if (BufferInfo->DataPtr == NULL && TransactionSize != 0) {
+    HeapMalloc.BufferHandle = AMD_CPU_AP_TASKING_HANDLE;
+    HeapMalloc.Persist = HEAP_LOCAL_CACHE;
+    // Deallocate the general purpose heap structure, if it exists.  Ignore
+    // the status in case it does not exist.
+    HeapDeallocateBuffer (HeapMalloc.BufferHandle, StdHeader);
+    HeapMalloc.RequestedBufferSize = (TransactionSize * XFER_ELEMENT_SIZE);
+    if (HeapAllocateBuffer (&HeapMalloc, StdHeader) == AGESA_SUCCESS) {
+      BufferInfo->DataPtr = (UINT32 *) HeapMalloc.BufferPtr;
+      BufferInfo->DataSizeInDwords = (UINT16) (HeapMalloc.RequestedBufferSize / XFER_ELEMENT_SIZE);
+    } else {
+      BufferInfo->DataSizeInDwords = 0;
+    }
+  }
+
+  if (TransactionSize <= BufferInfo->DataSizeInDwords) {
+    SourceUniqueId = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
+    ApUtilWriteControlByte (SourceUniqueId, StdHeader);
+    CurrentStatus = CORE_DATA_FLAGS_READY;
+    WaitForStatus.Status = &CurrentStatus;
+    ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+    BufferInfo->DataTransferFlags =  ApUtilReadRemoteDataDword (TargetApicId, StdHeader);
+    ApUtilWriteControlByte (CORE_DATA_FLAGS_ACKNOWLEDGE, StdHeader);
+    if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
+      if (BufferInfo->DataPtr != NULL) {
+        ReturnStatus = AGESA_ALERT;
+      }
+      ApUtilReceivePointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader);
+    } else {
+      CurrentStatus = CORE_STS_DATA_READY_1;
+      ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+      CurrentStatus = CORE_STS_DATA_READY_0;
+      ApUtilWriteControlByte (CurrentStatus, StdHeader);
+      CurrentPtr = BufferInfo->DataPtr;
+      for (i = 0; i < TransactionSize; ++i) {
+        ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+        *CurrentPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader);
+        CurrentStatus ^= 0x01;
+        ApUtilWriteControlByte (CurrentStatus, StdHeader);
+      }
+    }
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+  } else {
+    BufferInfo->DataSizeInDwords = (UINT16) TransactionSize;
+    ReturnStatus = AGESA_ERROR;
+  }
+  return (ReturnStatus);
+}
+
+
+VOID
+RelinquishControlOfAllAPs (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32        BscSocket;
+  UINT32        Ignored;
+  UINT32        BscCoreNum;
+  UINT32        Core;
+  UINT32        Socket;
+  UINT32        NumberOfSockets;
+  AP_TASK       TaskPtr;
+  AGESA_STATUS  IgnoredSts;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  TaskPtr.FuncAddress.PfApTask = PerformFinalHalt;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) {
+      while (Core-- > 0) {
+        if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The last AGESA code that an AP performs
+ *
+ * This function, run only by APs, breaks down their cache subsystem, sets up
+ * for memory to be present upon wake (from IBV Init/Startup IPIs), and halts.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+PerformFinalHalt (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PrimaryCore;
+  UINT32 HaltFlags;
+  UINT32 CacheEnDis;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+  // CacheEnDis is a family specific flag, that lets the code to decide whether to
+  // keep the cache control bits set or cleared.
+  CacheEnDis = FamilyServices->InitCacheDisabled;
+
+  // Determine if the current core has the primary core role.  The first core to execute
+  // in each compute unit has the primary role.
+  PrimaryCore = (UINT32) IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader);
+
+  // Aggregate the flags for the halt service.
+  HaltFlags = PrimaryCore | (CacheEnDis << 1);
+
+  ApUtilWriteControlByte (CORE_UNAVAILABLE, StdHeader);
+  ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads the APIC register on the designated remote core.
+ *
+ * This function uses the remote read inter-processor interrupt protocol
+ * to read an APIC register from the remote core
+ *
+ * @param[in]        TargetApicId  Local APIC ID of the desired core
+ * @param[in]        RegAddr       APIC register to read
+ * @param[in]        StdHeader     Configuration parameters pointer
+ *
+ * @return           The current value of the remote core's desired APIC register
+ *
+ */
+UINT32
+STATIC
+ApUtilRemoteRead (
+  IN       UINT32            TargetApicId,
+  IN       UINT8             RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ApicRegister;
+  UINT64 ApicBase;
+  UINT64 ApicAddr;
+
+  ApUtilGetLocalApicBase (&ApicBase, StdHeader);
+  TargetApicId <<= LOCAL_APIC_ID;
+
+  do {
+    ApicAddr = ApicBase + APIC_CMD_HI_REG;
+    LibAmdMemWrite (AccessWidth32, ApicAddr, &TargetApicId, StdHeader);
+    ApicAddr = ApicBase + APIC_CMD_LO_REG;
+    ApicRegister = CMD_REG_TO_READ | (UINT32) RegAddr;
+    LibAmdMemWrite (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+    do {
+      LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+    } while ((ApicRegister & CMD_REG_DELIVERY_STATUS) != 0);
+    while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) == CMD_REG_REMOTE_DELIVERY_PENDING) {
+      LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+    }
+  } while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) != CMD_REG_REMOTE_DELIVERY_DONE);
+  ApicAddr = ApicBase + APIC_REMOTE_READ_REG;
+  LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+  return (ApicRegister);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Writes an APIC register on the executing core.
+ *
+ * This function gets the base address of the executing core's local APIC,
+ * and writes a UINT32 value to a specified offset.
+ *
+ * @param[in]      RegAddr      APIC register to write to
+ * @param[in]      Value        Data to be written to the desired APIC register
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilLocalWrite (
+  IN       UINT32 RegAddr,
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 ApicAddr;
+
+  ApUtilGetLocalApicBase (&ApicAddr, StdHeader);
+  ApicAddr += RegAddr;
+
+  LibAmdMemWrite (AccessWidth32, ApicAddr, &Value, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads an APIC register on the executing core.
+ *
+ * This function gets the base address of the executing core's local APIC,
+ * and reads a UINT32 value from a specified offset.
+ *
+ * @param[in]      RegAddr      APIC register to read from
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @return         The current value of the local APIC register
+ *
+ */
+UINT32
+STATIC
+ApUtilLocalRead (
+  IN       UINT32  RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ApicRegister;
+  UINT64 ApicAddr;
+
+  ApUtilGetLocalApicBase (&ApicAddr, StdHeader);
+  ApicAddr += RegAddr;
+  LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+
+  return (ApicRegister);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the 64-bit base address of the executing core's local APIC.
+ *
+ * This function reads the APICBASE MSR and isolates the programmed address.
+ *
+ * @param[out]     ApicBase     Base address
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilGetLocalApicBase (
+     OUT   UINT64 *ApicBase,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdMsrRead (MSR_APIC_BAR, ApicBase, StdHeader);
+  *ApicBase &= LAPIC_BASE_ADDR_MASK;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the unique ID of the input Socket/Core.
+ *
+ * This routine converts a socket-core combination to to a number
+ * that will be used to directly address a particular core.  This
+ * unique value must be less than 128 because we only have a byte
+ * to use for status.  APIC IDs are not guaranteed to be below
+ * 128.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @return         The unique ID of the desired core
+ *
+ */
+UINT8
+STATIC
+ApUtilCalculateUniqueId (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 UniqueId;
+
+  UniqueId = ((Core << 3) | Socket);
+  ASSERT ((UniqueId & 0x80) == 0);
+  return (UniqueId);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Wakes up a core from the halted state.
+ *
+ * This function sends a directed NMI inter-processor interrupt to
+ * the input Socket/Core.
+ *
+ * @param[in]      TargetApicId    Local APIC ID of the desired core
+ * @param[in]      StdHeader       Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilFireDirectedNmi (
+  IN       UINT32 TargetApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  TargetApicId <<= LOCAL_APIC_ID;
+
+  ApUtilLocalWrite ((UINT32) APIC_CMD_HI_REG, TargetApicId, StdHeader);
+  ApUtilLocalWrite ((UINT32) APIC_CMD_LO_REG, (UINT32) CMD_REG_TO_NMI, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely receives a pointer from the designated remote core.
+ *
+ * This function uses a sequence of remote reads to receive a pointer,
+ * one UINT32 at a time.
+ *
+ * @param[in]      TargetApicId  Local APIC ID of the desired core
+ * @param[out]     ReturnPointer Pointer passed from remote core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilReceivePointer (
+  IN       UINT32 TargetApicId,
+     OUT   VOID  **ReturnPointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   i;
+  UINT8   WaitStatus;
+  UINT32  *AddressScratchPtr;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  WaitStatus = CORE_STS_DATA_READY_0;
+  WaitForStatus.Status = &WaitStatus;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  AddressScratchPtr = (UINT32 *) ReturnPointer;
+  for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); ++i) {
+    ApUtilWriteControlByte (CORE_NEEDS_PTR, StdHeader);
+    WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+    ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+    *AddressScratchPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader);
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+    WaitForStatus.WaitForStatusFlags = 0;
+    ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely transmits a pointer to the designated remote core.
+ *
+ * This function uses a sequence of remote reads to transmit a pointer,
+ * one UINT32 at a time.
+ *
+ * @param[in]      TargetApicId  Local APIC ID of the desired core
+ * @param[out]     Pointer       Pointer passed from remote core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilTransmitPointer (
+  IN       UINT32 TargetApicId,
+  IN       VOID  **Pointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   i;
+  UINT8   WaitStatus;
+  UINT32  *AddressScratchPtr;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  WaitStatus = CORE_NEEDS_PTR;
+  WaitForStatus.Status = &WaitStatus;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+
+  AddressScratchPtr = (UINT32 *) Pointer;
+
+  for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); i++) {
+    WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+    ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+    ApUtilWriteDataDword (*AddressScratchPtr++, StdHeader);
+    ApUtilWriteControlByte (CORE_STS_DATA_READY_0, StdHeader);
+    WaitForStatus.WaitForStatusFlags = 0;
+    ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h
new file mode 100644
index 0000000000..3c8e4dee4c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h
@@ -0,0 +1,330 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU APIC related utility functions and structures
+ *
+ * Contains code that provides mechanism to invoke and control APIC communication.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_APIC_UTILITIES_H_
+#define _CPU_APIC_UTILITIES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define APIC_CTRL_DWORD 0xF
+#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
+#define APIC_CTRL_MASK 0xFF
+#define APIC_CTRL_SHIFT 0
+
+#define APIC_DATA_DWORD 0x38
+#define APIC_DATA_REG (APIC_DATA_DWORD << 4)
+
+#define APIC_REMOTE_READ_REG 0xC0
+#define APIC_CMD_LO_REG 0x300
+#define APIC_CMD_HI_REG 0x310
+
+// APIC_CMD_LO_REG bits
+#define CMD_REG_DELIVERY_STATUS 0x1000
+#define CMD_REG_TO_READ 0x300
+#define CMD_REG_REMOTE_RD_STS_MSK 0x30000ul
+#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000ul
+#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000ul
+#define CMD_REG_TO_NMI 0x400
+
+// ExeFlags bits
+#define WAIT_FOR_CORE     0x00000001ul
+#define TASK_HAS_OUTPUT   0x00000002ul
+#define RETURN_PARAMS     0x00000004ul
+#define END_AT_HLT        0x00000008ul
+#define PASS_EARLY_PARAMS 0x00000010ul
+
+// Control Byte Values
+// bit 7 indicates the type of message
+// 1 - control message
+// 0 - launch + APIC ID = message to go
+//
+#define CORE_UNAVAILABLE            0xFF
+#define CORE_IDLE                   0xFE
+#define CORE_IDLE_HLT               0xFD
+#define CORE_ACTIVE                 0xFC
+#define CORE_NEEDS_PTR              0xFB
+#define CORE_NEEDS_DATA_SIZE        0xFA
+#define CORE_STS_DATA_READY_1       0xF9
+#define CORE_STS_DATA_READY_0       0xF8
+#define CORE_DATA_FLAGS_READY       0xF7
+#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
+#define CORE_DATA_PTR_READY         0xF5
+
+// Macro used to determine the number of dwords to transmit to the AP as input
+#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
+
+// IDT table
+#define IDT_DESC_PRESENT     0x80
+
+#define IDT_DESC_TYPE_LDT    0x02
+#define IDT_DESC_TYPE_CALL16 0x04
+#define IDT_DESC_TYPE_TASK   0x05
+#define IDT_DESC_TYPE_INT16  0x06
+#define IDT_DESC_TYPE_TRAP16 0x07
+#define IDT_DESC_TYPE_CALL32 0x0C
+#define IDT_DESC_TYPE_INT32  0x0E
+#define IDT_DESC_TYPE_TRAP32 0x0F
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+
+/// Function pointer union representing the eight different
+/// types of functions that an AP can be asked to perform.
+typedef union {
+  PF_AP_TASK     PfApTask;      ///< AMD_CONFIG_PARAMS *  input with no output
+  PF_AP_TASK_I   PfApTaskI;     ///< VOID * + AMD_CONFIG_PARAMS *  input with no output
+  PF_AP_TASK_C   PfApTaskC;     ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS *  input with no output
+  PF_AP_TASK_IC  PfApTaskIC;    ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS *  input with no output
+  PF_AP_TASK_O   PfApTaskO;     ///< AMD_CONFIG_PARAMS * input with UINT32 output
+  PF_AP_TASK_IO  PfApTaskIO;    ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
+  PF_AP_TASK_OC  PfApTaskOC;    ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
+  PF_AP_TASK_IOC PfApTaskIOC;   ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS *  input with UINT32 output
+} AP_FUNCTION_PTR;
+
+/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
+/// containing information about the data transfer from one core
+/// to another.
+typedef struct {
+  IN OUT   UINT16 DataSizeInDwords;   ///< Size of the data to be transferred rounded up to the nearest dword
+  IN OUT   VOID   *DataPtr;           ///< Pointer to the data
+  IN       UINT32 DataTransferFlags;  ///< Flags dictating certain aspects of the data transfer
+} AP_DATA_TRANSFER;
+
+/// Input structure for ApUtilRunCodeOnSocketCore.
+typedef struct _AP_TASK {
+  AP_FUNCTION_PTR  FuncAddress;   ///< Pointer to the function that the AP will run
+  AP_DATA_TRANSFER DataTransfer;  ///< Data transfer struct for optionally passing data that the AP should use as input to the function
+  UINT32           ExeFlags;      ///< Flags dictating certain aspects of the AP tasking sequence
+} AP_TASK;
+
+/// Input structure for ApUtilWaitForCoreStatus.
+typedef struct {
+  IN       UINT8  *Status;            ///< Pointer to the 1st element of an array of values to wait for
+  IN       UINT8  NumberOfElements;   ///< Number of elements in the array
+  IN       UINT32 RetryCount;         ///< Number of remote read cycles to complete before quitting
+  IN       UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
+} AP_WAIT_FOR_STATUS;
+
+/// Interrupt Descriptor Table entry
+typedef struct {
+  UINT16 OffsetLo;     ///< Lower 16 bits of the interrupt handler routine's offset
+  UINT16 Selector;     ///< Interrupt handler routine's selector
+  UINT8  Rsvd;         ///< Reserved
+  UINT8  Flags;        ///< Interrupt flags
+  UINT16 OffsetHi;     ///< Upper 16 bits of the interrupt handler routine's offset
+  UINT32 Offset64;     ///< High order 32 bits of the handler's offset needed when in 64 bit mode
+  UINT32 Rsvd64;       ///< Reserved
+} IDT_DESCRIPTOR;
+
+/// Structure needed to load the IDTR using the lidt instruction
+typedef struct {
+  UINT16 Limit;        ///< Interrupt Descriptor Table size
+  UINT64 Base;         ///< Interrupt Descriptor Table base address
+} IDT_BASE_LIMIT;
+
+#define WAIT_STATUS_EQUALITY 0x00000001ul
+#define WAIT_INFINITELY 0
+
+// Data Transfer Flags
+#define DATA_IN_MEMORY 0x00000001ul
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+//                   These are   P U B L I C   functions, used by AGESA
+UINT8
+ApUtilReadRemoteControlByte (
+  IN       UINT32 TargetApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApUtilWriteControlByte (
+  IN       UINT8 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+ApUtilReadRemoteDataDword (
+  IN       UINT32 TargetApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApUtilWriteDataDword (
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+ApUtilRunCodeOnSocketCore (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+ApUtilWaitForCoreStatus (
+  IN       UINT32 TargetApicId,
+  IN       AP_WAIT_FOR_STATUS *WaitParamsPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApEntry (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+UINT32
+ApUtilTaskOnExecutingCore (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID    *ConfigParams
+  );
+
+VOID
+ApUtilTransmitBuffer (
+  IN     UINT8   Socket,
+  IN     UINT8   Core,
+  IN     AP_DATA_TRANSFER *BufferInfo,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+ApUtilReceiveBuffer (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN OUT   AP_DATA_TRANSFER  *BufferInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetLocalApicIdForCore (
+  IN       UINT32 TargetSocket,
+  IN       UINT32 TargetCore,
+     OUT   UINT32 *LocalApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApUtilRunCodeOnAllLocalCoresAtEarly (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+VOID
+RelinquishControlOfAllAPs (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GetCsSelector (
+  IN       UINT16 *Selector,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetIdtr (
+  IN       IDT_BASE_LIMIT *IdtInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetIdtr (
+  IN       IDT_BASE_LIMIT *IdtInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  /* _CPU_APIC_UTILITIES_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c
new file mode 100644
index 0000000000..5249f9c0ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c
@@ -0,0 +1,198 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU BIST Status Check Implementation.
+ *
+ * Implement CPU BIST Status checking
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_CPU_CPUBIST_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+UINT32
+STATIC
+GetBistResults (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+ /*----------------------------------------------------------------------------------------
+  *                          E X P O R T E D    F U N C T I O N S
+  *----------------------------------------------------------------------------------------
+ */
+
+ /*---------------------------------------------------------------------------------------*/
+ /**
+  *
+  * This function checks the status of BIST and places the error status in the event log
+  * if there are any errors
+  *
+  * @param[in]      StdHeader              Header for library and services
+  *
+  * @retval         AGESA_SUCCESS          No BIST errors have been logged.
+  * @retval         AGESA_ALERT            BIST errors have been detected and added to the
+  *                                        event log.
+  */
+AGESA_STATUS
+CheckBistStatus (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                Socket;
+  UINT32                Core;
+  UINT32                BscSocket;
+  UINT32                BscCoreNum;
+  UINT32                NumberOfSockets;
+  UINT32                NumberOfCores;
+  UINT32                Ignored;
+  UINT32                ReturnCode;
+  AGESA_STATUS          IgnoredSts;
+  AGESA_STATUS          AgesaStatus;
+  AP_TASK               TaskPtr;
+
+  // Make sure that Standard Header is valid
+  ASSERT (StdHeader != NULL);
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Get the BscSocket, BscCoreNum and NumberOfSockets in the system
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  // Setup TaskPtr struct to execute routine on APs
+  TaskPtr.FuncAddress.PfApTaskO = GetBistResults;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+          ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+        } else {
+          ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader);
+        }
+
+        // If BIST value is non-zero, add to BSP's event log
+        if (ReturnCode != 0) {
+          IDS_HDT_CONSOLE (CPU_TRACE, "  BIST failure: socket %d core %d, status = 0x%x\n", Socket, Core, ReturnCode);
+          AgesaStatus = AGESA_ALERT;
+          PutEventLog (AGESA_ALERT,
+                       CPU_EVENT_BIST_ERROR,
+                       ReturnCode, Socket, Core, 0, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L          F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+*/
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Reads the lower 32 bits of the BIST register
+ *
+ * @param[in]      StdHeader              Header for library and services
+ *
+ * @retval         Value of the BIST register
+*/
+UINT32
+STATIC
+GetBistResults (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64   BistResults;
+
+  // Read MSRC001_0060 BIST Results Register
+  LibAmdMsrRead (MSR_BIST, &BistResults, StdHeader);
+
+  return (UINT32) (BistResults & 0xFFFFFFFF);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c
new file mode 100644
index 0000000000..e296e3cebf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c
@@ -0,0 +1,339 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuEarlyInit.h"
+#include "cpuRegisters.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_CPU_CPUBRANDID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST CHAR8 ROMDATA strEngSample[] = "AMD Engineering Sample";
+CONST CHAR8 ROMDATA strTtkSample[] = "AMD Thermal Test Kit";
+CONST CHAR8 ROMDATA strUnknown[] = "AMD Processor Model Unknown";
+
+CONST AMD_CPU_BRAND ROMDATA EngSample_Str = {0, 0, 0, SOCKET_IGNORE, strEngSample, sizeof (strEngSample)};
+CONST AMD_CPU_BRAND ROMDATA TtkSample_Str = {0, 1, 0, SOCKET_IGNORE, strTtkSample, sizeof (strTtkSample)};
+CONST AMD_CPU_BRAND ROMDATA Dflt_Str1 = {0, 0, 0, SOCKET_IGNORE, strUnknown, sizeof (strUnknown)};
+CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, DR_NO_STRING};
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program BrandID registers (CPUIDNameStringPtr[0-5])
+ *
+ * This function determines the appropriate brand string for the executing
+ * core, and programs the namestring MSRs.
+ *
+ * @param[in,out] StdHeader   Config handle for library and services.
+ *
+ */
+VOID
+SetBrandIdRegisters (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   SocketIndex;
+  UINT8   SuffixStatus;
+  UINT8   TableElements;
+  UINT8   TableEntryCount;
+  UINT8   TableEntryIndex;
+  CHAR8   TempChar;
+  CHAR8   *NameStringPtr;
+  CHAR8   *SuffixStringPtr;
+  CHAR8   *BrandStringPtr;
+  CHAR8   *TempNameCharPtr;
+  UINT32  MsrIndex;
+  UINT32  Quotient;
+  UINT32  Remainder;
+  UINT64  *MsrNameStringPtrPtr;
+  CPUID_DATA    CpuId;
+  CPU_LOGICAL_ID CpuLogicalId;
+  CPU_BRAND_TABLE *SocketTableEntry;
+  CPU_BRAND_TABLE **SocketTableEntry1;
+  AMD_CPU_BRAND *SocketTablePtr;
+  AMD_CPU_BRAND_DATA Data;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  SuffixStatus = 0;
+  FamilySpecificServices = NULL;
+  SocketTablePtr = NULL;
+  SocketTableEntry = NULL;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  // Step1: Allocate 48 bytes from Heap space
+  AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH;
+  AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    // Clear NameBuffer
+    BrandStringPtr = (CHAR8 *) AllocHeapParams.BufferPtr;
+    LibAmdMemFill (BrandStringPtr, 0, CPU_BRAND_ID_LENGTH, StdHeader);
+  } else {
+    PutEventLog (
+      AGESA_ERROR,
+      CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE,
+      0, 0, 0, 0, StdHeader
+      );
+    return;
+  }
+
+  // Step2: Get brandid from model number and model string
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+
+  // Step3: Figure out Socket/Page/Model/String1/String2/Core Number
+  Data.String2 = (UINT8) (CpuId.EBX_Reg & 0x0f);
+  Data.Model   = (UINT8) ((CpuId.EBX_Reg >> 4) & 0x7f);
+  Data.String1 = (UINT8) ((CpuId.EBX_Reg >> 11) & 0x0f);
+  Data.Page    = (UINT8) ((CpuId.EBX_Reg >> 15) & 0x01);
+  Data.Socket  = (UINT8) ((CpuId.EBX_Reg >> 28) & 0x0f);
+  Data.Cores = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader);
+
+  // Step4: If NN = 0, we have an engineering sample, no suffix; then jump to Step6
+  if (Data.Model == 0) {
+    if (Data.Page == 0) {
+      SocketTablePtr = (AMD_CPU_BRAND *)&EngSample_Str;
+    } else {
+      SocketTablePtr = (AMD_CPU_BRAND *)&TtkSample_Str;
+    }
+  } else {
+
+    // Model is not equal to zero, so decrement it
+    // For family 10 if PkgType[3:0] is greater than or equal to 2h and families >= 12h
+    GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+    if ((((CpuLogicalId.Family & AMD_FAMILY_10) != 0) && (Data.Socket >= DR_SOCKET_S1G3)) ||
+        ((CpuLogicalId.Family & AMD_FAMILY_GE_12) != 0)) {
+      Data.Model--;
+    }
+
+    // Step5: Search for String1 (there can be only 1)
+    FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (CONST VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
+    SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
+    for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
+         && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
+      if (*SocketTableEntry1 == NULL) {
+        break;
+      }
+      SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table;
+      TableElements = (*SocketTableEntry1)->NumberOfEntries;
+      for (SocketIndex = 0; (SocketIndex < TableElements)
+           && SuffixStatus == 0; SocketIndex++) {
+        if ((SocketTablePtr->Page == Data.Page) &&
+            (SocketTablePtr->Index == Data.String1) &&
+            (SocketTablePtr->Socket == Data.Socket) &&
+            (SocketTablePtr->Cores == Data.Cores)) {
+          SuffixStatus = 1;
+        } else {
+          SocketTablePtr++;
+        }
+      }
+    }
+    if (SuffixStatus == 0) {
+      SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str1;  // We did not find one, make 'Unknown'
+    }
+  }
+
+  // Step6: Copy String into NameBuffer
+  // We now have data structure pointing to correct type in (*SocketTablePtr)
+  LibAmdMemCopy  (BrandStringPtr,
+                  (CHAR8 *)SocketTablePtr->Stringstart,
+                  SocketTablePtr->Stringlength,
+                  StdHeader);
+
+  // Step7: Get suffix, determine addition to BRANDSPEED
+  if (SuffixStatus != 0) {
+    // Turn our value into a decimal string
+    // We have a value like 37d which we need to turn into '3' '7'
+    // Divide by 10, store remainder as an ASCII char on stack, repeat until Quotient is 0
+    NameStringPtr = BrandStringPtr + SocketTablePtr->Stringlength - 1;
+    TempNameCharPtr = NameStringPtr;
+    Quotient = Data.Model;
+    do {
+      Remainder = Quotient % 10;
+      Quotient = Quotient / 10;
+      *TempNameCharPtr++ = (CHAR8) (Remainder + '0');   // Put suffix into our NameBuffer
+    } while (Quotient != 0);
+    if (Data.Model < 10) {
+      *TempNameCharPtr++ = '0';
+    }
+
+    // Step8: Reverse the string sequence and copy into NameBuffer
+    SuffixStringPtr = TempNameCharPtr--;
+    while (NameStringPtr < TempNameCharPtr) {
+      TempChar = *NameStringPtr;
+      *NameStringPtr = *TempNameCharPtr;
+      *TempNameCharPtr = TempChar;
+      NameStringPtr++;
+      TempNameCharPtr--;
+    }
+
+    // Step9: Search for String2
+    SuffixStatus = 0;
+    FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (CONST VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
+    SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
+    for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
+         && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
+      if (*SocketTableEntry1 == NULL) {
+        break;
+      }
+      SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table;
+      TableElements = (*SocketTableEntry1)->NumberOfEntries;
+      for (SocketIndex = 0; (SocketIndex < TableElements)
+           && SuffixStatus == 0; SocketIndex++) {
+        if ((SocketTablePtr->Page == Data.Page) &&
+            (SocketTablePtr->Index == Data.String2) &&
+            (SocketTablePtr->Socket == Data.Socket) &&
+            (SocketTablePtr->Cores == Data.Cores)) {
+          SuffixStatus = 1;
+        } else {
+          SocketTablePtr++;
+        }
+      }
+    }
+    if (SuffixStatus == 0) {
+      SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str2;
+    }
+
+    // Step10: Copy String2 into our NameBuffer
+    if (SocketTablePtr->Stringlength != 0) {
+      LibAmdMemCopy (SuffixStringPtr,
+                      (CHAR8 *)SocketTablePtr->Stringstart,
+                      SocketTablePtr->Stringlength,
+                      StdHeader);
+    }
+  }
+
+  // Step11: Put values into name MSRs,  Always write the full 48 bytes
+  MsrNameStringPtrPtr = (UINT64 *) BrandStringPtr;
+  for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
+    LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
+    MsrNameStringPtrPtr++;
+  }
+  HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program BrandID registers (CPUIDNameStringPtr[0-5])
+ *
+ * This function acts as a wrapper for calling the SetBrandIdRegisters
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuSetBrandID, StdHeader);
+  SetBrandIdRegisters (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c
new file mode 100644
index 0000000000..6078ca046e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c
@@ -0,0 +1,436 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "Table.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "Topology.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUEARLYINIT_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetPerformEarlyFlag (
+  IN OUT   UINT32   *PerformEarlyFlag,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+McaInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by AmdCpuEarly to initialize the input
+ * structure for the Cpu Init @ Early routine.
+ *
+ * @param[in]       StdHeader         Opaque handle to standard config header
+ * @param[in]       PlatformConfig    Config handle for platform specific information
+ * @param[in,out]   CpuEarlyParamsPtr Service Interface structure to initialize.
+ *
+ * @retval          AGESA_SUCCESS     Always Succeeds
+ */
+VOID
+AmdCpuEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr
+  )
+{
+  ASSERT (CpuEarlyParamsPtr != NULL);
+
+  CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
+  CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the early entry point
+ *
+ * This function performs a large list of initialization items.  These items
+ * include:
+ *
+ *    -1      local APIC initialization
+ *    -2      MSR table initialization
+ *    -3      PCI table initialization
+ *    -4      HT Phy PCI table initialization
+ *    -5      microcode patch loading
+ *    -6      namestring determination/programming
+ *    -7      AP initialization
+ *    -8      power management initialization
+ *    -9      core leveling
+ *
+ * This routine must be run by all cores in the system.  Please note that
+ * all APs that enter will never exit.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  PlatformConfig    Config handle for platform specific information
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+AmdCpuEarly (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  )
+{
+  UINT8         WaitStatus;
+  UINT8         i;
+  UINT8         StartCore;
+  UINT8         EndCore;
+  UINT32        NodeNum;
+  UINT32        PrimaryCore;
+  UINT32        SocketNum;
+  UINT32        ModuleNum;
+  UINT32        HighCore;
+  UINT32        ApHeapIndex;
+  UINT32        CurrentPerformEarlyFlag;
+  UINT32        TargetApicId;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+  AGESA_STATUS  Status;
+  AGESA_STATUS  CalledStatus;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+  S_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore;
+
+  Status = AGESA_SUCCESS;
+  CalledStatus = AGESA_SUCCESS;
+
+  AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams);
+
+  IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader);
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  EarlyTableOnCore = NULL;
+  FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (CONST S_PERFORM_EARLY_INIT_ON_CORE **)&EarlyTableOnCore, &CpuEarlyParams, StdHeader);
+  if (EarlyTableOnCore != NULL) {
+    GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader);
+    for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) {
+      if ((EarlyTableOnCore[i].PerformEarlyInitFlag & CurrentPerformEarlyFlag) != 0) {
+        IDS_HDT_CONSOLE (CPU_TRACE, "  Perform core init step %d\n", i);
+        EarlyTableOnCore[i].PerformEarlyInitOnCore (FamilySpecificServices, &CpuEarlyParams, StdHeader);
+      }
+    }
+  }
+
+  // B S P    C O D E    T O    I N I T I A L I Z E    A Ps
+  // -------------------------------------------------------
+  // -------------------------------------------------------
+  // IMPORTANT: Here we determine if we are BSP or AP
+  if (IsBsp (StdHeader, &CalledStatus)) {
+
+    // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization.
+    // Use '0' as a dummy heap index value.
+    GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader);
+    GetCpuServicesOfSocket (SocketNum, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader);
+    FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader);
+
+    // Clear BSP's Status Byte
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+
+    NodeNum = 0;
+    ApHeapIndex = 1;
+    while (NodeNum < MAX_NODES &&
+          GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) {
+      GetCpuServicesOfSocket (SocketNum, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+      GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader);
+      if (NodeNum == 0) {
+        StartCore = (UINT8) PrimaryCore + 1;
+      } else {
+        StartCore = (UINT8) PrimaryCore;
+      }
+
+      EndCore = (UINT8) HighCore;
+      for (i = StartCore; i <= EndCore; i++) {
+        FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader);
+        IDS_HDT_CONSOLE (CPU_TRACE, "  Launch socket %d core %d\n", SocketNum, i);
+        if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, i, PrimaryCore, StdHeader)) {
+          IDS_HDT_CONSOLE (CPU_TRACE, "  Waiting for socket %d core %d\n", SocketNum, i);
+          GetLocalApicIdForCore (SocketNum, i, &TargetApicId, StdHeader);
+          WaitStatus = CORE_IDLE;
+          WaitForStatus.Status = &WaitStatus;
+          WaitForStatus.NumberOfElements = 1;
+          WaitForStatus.RetryCount = WAIT_INFINITELY;
+          WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+          ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader);
+          ApHeapIndex++;
+        }
+      }
+      NodeNum++;
+    }
+
+    // B S P    P h a s e - 1   E N D
+
+    IDS_OPTION_HOOK (IDS_BEFORE_PM_INIT, &CpuEarlyParams, StdHeader);
+
+    AGESA_TESTPOINT (TpProcCpuBeforePMFeatureInit, StdHeader);
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features before early power mgmt init\n");
+    CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_PM_INIT, PlatformConfig, StdHeader);
+    if (CalledStatus > Status) {
+      Status = CalledStatus;
+    }
+
+    AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader);
+    CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader);
+    if (CalledStatus > Status) {
+      Status = CalledStatus;
+    }
+
+    AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader);
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features after early power mgmt init\n");
+    CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader);
+
+    IDS_OPTION_HOOK (IDS_BEFORE_AP_EARLY_HALT, &CpuEarlyParams, StdHeader);
+
+    // Sleep all APs
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Halting all APs\n");
+    ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader);
+  } else {
+    ApEntry (StdHeader, &CpuEarlyParams);
+  }
+
+  if (CalledStatus > Status) {
+    Status = CalledStatus;
+  }
+
+  return (Status);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize Machine Check Architecture registers
+ *
+ * This function initializes the MCA MSRs.  On cold reset, these registers
+ * have an invalid data that must be cleared on all cores.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+McaInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16      TempVar16_a;
+  UINT32      MsrAddress;
+  UINT64      MsrData;
+  CPUID_DATA  CpuIdDataStruct;
+
+  if (!(IsWarmReset (StdHeader))) {
+    // Run CPUID to verify that the processor supports MCE and MCA
+    // i.e. edx[7], and edx[14]
+    // CPUID_MODEL = 1
+    LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader);
+    if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) {
+      // Check to see if the MCG_CTL_P bit is set
+      // MCG = Global Machine Check Exception Reporting Control Register
+      LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
+      if ((MsrData & MCG_CTL_P) != 0) {
+        TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2);
+        TempVar16_a += MSR_MC0_CTL;
+
+        // Initialize the data
+        MsrData = 0;
+        for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) {
+          LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize Machine Check Architecture registers
+ *
+ * This function acts as a wrapper for calling the McaInitialization
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+McaInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  McaInitialization (StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the given task on all cores (including self) on the socket of the executing
+ * core 0.
+ *
+ * This function is used to invoke all APs on the socket of the executing core 0 to
+ * run a specified AGESA procedure.
+ *
+ * @param[in]  TaskPtr      Function descriptor
+ * @param[in]  StdHeader    Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+ApUtilRunCodeOnAllLocalCoresAtEarly (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  UINT32 Core;
+  UINT32 Socket;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  UINT32 ActiveCores;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+  GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
+
+  for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+    ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader);
+  }
+  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get current condition, such as warm/cold reset, to determine if related function
+ * need to be performed at early stage
+ *
+ *  @param[in, out]   PerformEarlyFlag      Perform early flag.
+ *  @param[in]        StdHeader             Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+GetPerformEarlyFlag (
+  IN OUT   UINT32   *PerformEarlyFlag,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  *PerformEarlyFlag = 0;
+  if (IsWarmReset (StdHeader)) {
+    *PerformEarlyFlag |= PERFORM_EARLY_WARM_RESET;
+  } else {
+    *PerformEarlyFlag |= PERFORM_EARLY_COLD_BOOT;
+  }
+  return;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h
new file mode 100644
index 0000000000..f101ab13fa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h
@@ -0,0 +1,331 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_EARLY_INIT_H_
+#define _CPU_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+#define CPU_BRAND_ID_LENGTH     48            // Total number of characters supported
+#define LOW_NODE_DEVICEID       24
+#define NB_CAPABILITIES         0xE8          //Function 3 Registers
+//----------------------------------------------------------------------------
+//                         CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/* All lengths are in bytes */
+#define MICROCODE_TRIADE_SIZE           28
+#define MICROCODE_HEADER_LENGTH         64
+
+/**
+ * @page ucodeflag Microcode Patches Signature Guide
+ *
+ * We mark patches in the ROM with a signature so that they can be easily found
+ *
+ *   @anchor Microcode Patch Signature
+ *   @li @e  Microcode Patch Signature @n
+ *         Microcode patches are marked by adding a signature before patches in the ROM image to
+ *         help identify where they are located.
+ *         There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
+ *         The other is '$UCODE4K', it indicates there's a following patch with 4K size.
+ *         If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
+ *
+ *
+ */
+/// Microcode patch flag for replacement
+typedef struct {
+  IN       UINT8   MicrocodePatchesFlag[8];  ///< a flag followed by microcode
+} MICROCODE_PATCHES_FLAG;
+
+#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
+#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
+#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
+
+/* Offsets in UCODE PATCH Header */
+/* Note: Header is 64 bytes      */
+#define DATE_CODE_OFFSET                0   // 4 bytes
+#define PATCH_ID                        4   // 4 bytes
+#define MICROCODE_PATH_DATA_ID          8   // 2 bytes
+#define MICROCODE_PATCH_DATA_LENGTH     10  // 1 byte
+#define MICROCODE_PATCH_DATA_CHECKSUM   12  // 4 bytes
+#define CHIPSET_1_DEVICE_ID             16  // 4 bytes
+#define CHIPSET_2_DEVICE_ID             20  // 4 bytes
+#define PROCESSOR_REV_ID                24  // 2 bytes
+#define CHIPSET_1_REV_ID                26  // 1 byte
+#define CHIPSET_2_REV_ID                27  // 1 byte
+
+#define MICROCODE_PATCH_2K_SIZE    2048
+#define MICROCODE_PATCH_4K_SIZE    4096
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// A structure representing BrandId[15:0] from
+/// CPUID Fn8000_0001_EBX
+typedef struct {
+  UINT8           String1:4;   ///< An index to a string value used to create the name string
+  UINT8           String2:4;   ///< An index to a string value used to create the name string
+  UINT8           Page:1;      ///< An index to the appropriate page for the String1, String2, and Model values
+  UINT8           Model:7;     ///< A field used to create the model number in the name string
+  UINT8           Socket:4;    ///< Specifies the package type
+  UINT8           Cores:4;     ///< Identifies how many physical cores are present
+} AMD_CPU_BRAND_DATA;
+
+/// A structure containing string1 and string2 values
+/// as well as information pertaining to their usage
+typedef struct {
+  IN       UINT8  Cores;              ///< Appropriate number of physical cores
+  IN       UINT8  Page;               ///< This string's page number
+  IN       UINT8  Index;              ///< String index
+  IN       UINT8  Socket;             ///< Package type information
+  IN       CONST CHAR8 *Stringstart;  ///< The literal string
+  IN       UINT8  Stringlength;       ///< Number of characters in the string
+} AMD_CPU_BRAND;
+
+/// An entire CPU brand table.
+typedef struct {
+  UINT8 NumberOfEntries;        ///< The number of entries in the table.
+  CONST AMD_CPU_BRAND  *Table;  ///< The table entries.
+} CPU_BRAND_TABLE;
+
+//----------------------------------------------------------------------------
+//                         CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Microcode patch field definitions
+typedef struct {
+  UINT32   DateCode;                   ///< Date of patch creation
+  UINT32   PatchID;                    ///< Patch level
+  UINT16   MicrocodePatchDataID;       ///< Internal use only
+  UINT8    MicrocodePatchDataLength;   ///< Internal use only
+  UINT8    InitializationFlag;         ///< Internal use only
+  UINT32   MicrocodePatchDataChecksum; ///< Doubleword sum of data block
+  UINT32   Chipset1DeviceID;           ///< Device ID of 1st HT device to match
+  UINT32   Chipset2DeviceID;           ///< Device ID of 2nd HT device to match
+  UINT16   ProcessorRevisionID;        ///< Equivalent ID
+  UINT8    Chipset1RevisionID;         ///< Revision level of 1st HT device to match
+  UINT8    Chipset2RevisionID;         ///< Revision level of 2nd HT device to match
+  UINT8    BiosApiRevision;            ///< BIOS INT 15 API revision required
+  UINT8    Reserved1[3];               ///< Reserved
+  UINT32   MatchRegister0;             ///< Internal use only
+  UINT32   MatchRegister1;             ///< Internal use only
+  UINT32   MatchRegister2;             ///< Internal use only
+  UINT32   MatchRegister3;             ///< Internal use only
+  UINT32   MatchRegister4;             ///< Internal use only
+  UINT32   MatchRegister5;             ///< Internal use only
+  UINT32   MatchRegister6;             ///< Internal use only
+  UINT32   MatchRegister7;             ///< Internal use only
+  UINT8    PatchDataBlock[896];        ///< Raw patch data
+  UINT8    Reserved2[896];             ///< Reserved
+  UINT8    X86CodePresent;             ///< Boolean to determine if executable code exists
+  UINT8    X86CodeEntry[191];          ///< Code to execute if X86CodePresent != 0
+} MICROCODE_PATCH;
+
+/// Two kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+  IN       UINT8   MicrocodePatches[MICROCODE_PATCH_2K_SIZE];  ///< 2k UINT8 elements
+} MICROCODE_PATCHES;
+
+/// Four kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+  IN       UINT8   MicrocodePatches[MICROCODE_PATCH_4K_SIZE];  ///< 4k UINT8 elements
+} MICROCODE_PATCHES_4K;
+
+/**
+ *  Set down core register
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices  The current Family Specific Services.
+ * @param[in]      Socket        Socket ID.
+ * @param[in]      Module        Module ID in socket.
+ * @param[in]      LeveledCores  Number of core.
+ * @param[in]      CoreLevelMode Core level mode.
+ * @param[in]      StdHeader     Header for library and services.
+ *
+ * @retval         TRUE          Down Core register is updated.
+ * @retval         FALSE         Down Core register is not updated.
+ */
+typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES  *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
+
+/**
+ * Provide the interface to the Core Leveling Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CORE_LEVELING_FAMILY_SERVICES {             // See Forward Declaration above
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister;    ///< Method: Set down core register.
+};
+
+//----------------------------------------------------------------------------
+//                         CPU PERFORM EARLY INIT ON CORE
+//
+//----------------------------------------------------------------------------
+/// Flag definition.
+#define PERFORM_EARLY_WARM_RESET    0x1        // bit 0 --- the related function needs to be run if it's warm reset
+#define PERFORM_EARLY_COLD_BOOT     0x2        // bit 1 --- the related function needs to be run if it's cold boot
+
+#define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFFul // the related function always needs to be run
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+//                   These are   P U B L I C   functions, used by IBVs
+AGESA_STATUS
+AmdCpuEarly (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  );
+
+//                   These are   P U B L I C   functions, used by AGESA
+VOID
+SetBrandIdRegisters (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+PmInitializationAtEarly (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+BOOLEAN
+LoadMicrocodePatch (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetPatchEquivalentId (
+  IN OUT   UINT16             *ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+BOOLEAN
+ValidateMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN       UINT16             ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+GetMicrocodeVersion (
+     OUT   UINT32             *pMicrocodeVersion,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+AmdCpuEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr
+  );
+
+VOID
+McaInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_EARLY_INIT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEnvInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEnvInit.h
new file mode 100644
index 0000000000..0cd1d9d6a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEnvInit.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Env Init API functions Prototypes.
+ *
+ * Contains code for doing any Env CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_ENV_INIT_H_
+#define _CPU_ENV_INIT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+// HobTransfer
+AGESA_STATUS
+CopyHeapToMainRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif // _CPU_ENV_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c
new file mode 100644
index 0000000000..be8f8b719b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c
@@ -0,0 +1,423 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Event (Error) Log APIs, and related functions.
+ *
+ * Contains code that records and returns the events and errors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUEVENTLOG_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define TOTAL_EVENT_LOG_BUFFERS  16
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * A wrapper for each Event Log entry.
+ */
+typedef struct {
+  UINT16      Count;         ///< Entry number
+  AGESA_EVENT AgesaEvent;    ///< The entry itself.
+} AGESA_EVENT_STRUCT;
+
+/**
+ * The Event Log.
+ */
+typedef struct {
+  UINT16        ReadWriteFlag;   ///< Read Write flag.
+  UINT16        Count;           ///< The total number of active entries.
+  UINT16        ReadRecordPtr;   ///< The next entry to read.
+  UINT16        WriteRecordPtr;  ///< The next entry to write.
+  AGESA_EVENT_STRUCT AgesaEventStruct[TOTAL_EVENT_LOG_BUFFERS];   ///< The entries.
+} AGESA_STRUCT_BUFFER;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetEventLogHeapPointer (
+     OUT  AGESA_STRUCT_BUFFER **EventLog,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * External AGESA interface to read an Event from the Event Log.
+ *
+ * This is the implementation of the external AGESA interface entry, as a thin wrapper
+ * around the internal log services.
+ *
+ * @param[in]  Event           The event class, id, and any associated data.
+ *
+ * @retval     AGESA_SUCCESS   Always Succeeds.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+  )
+{
+  AGESA_EVENT  LogEvent;
+  AGESA_STATUS Status;
+
+  AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader);
+
+  ASSERT (Event != NULL);
+  Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader);
+  Status = GetEventLog (&LogEvent, &Event->StdHeader);
+
+  Event->EventClass = LogEvent.EventClass;
+  Event->EventInfo = LogEvent.EventInfo;
+  Event->DataParam1 = LogEvent.DataParam1;
+  Event->DataParam2 = LogEvent.DataParam2;
+  Event->DataParam3 = LogEvent.DataParam3;
+  Event->DataParam4 = LogEvent.DataParam4;
+
+  AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader);
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function prepares the Event Log for use.
+ *
+ * Allocate the memory for an event log on the heap.  Set the read pointer, write pointer,
+ * and count to reflect the log is empty.
+ *
+ * @param[in]  StdHeader      Our configuration, for passing to services.
+ *
+ * @retval      AGESA_SUCCESS     The event log is initialized.
+ * @retval      AGESA_ERROR       Allocate Heap Buffer returned an error.
+ *
+ */
+AGESA_STATUS
+EventLogInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS  AllocateHeapParams;
+  AGESA_STRUCT_BUFFER   *AgesaEventAlloc;
+  AGESA_STATUS          Status;
+
+  AllocateHeapParams.BufferHandle = EVENT_LOG_BUFFER_HANDLE;
+  AllocateHeapParams.RequestedBufferSize = sizeof (AGESA_STRUCT_BUFFER);
+  AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader);
+  AgesaEventAlloc = (AGESA_STRUCT_BUFFER *) AllocateHeapParams.BufferPtr;
+  AgesaEventAlloc->Count = 0;
+  AgesaEventAlloc->ReadRecordPtr = 0;
+  AgesaEventAlloc->WriteRecordPtr = 0;
+  AgesaEventAlloc->ReadWriteFlag = 1;
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function logs AGESA events into the event log.
+ *
+ * It will put the information in a circular buffer consisting of 16 such log
+ * entries. If the buffer gets full, then the next event log entry will be written
+ * over the oldest event log entry.
+ *
+ * @param[in]   EventClass   The severity of the event, its associated AGESA_STATUS.
+ * @param[in]   EventInfo    Uniquely identifies the event.
+ * @param[in]   DataParam1   Event specific additional data
+ * @param[in]   DataParam2   Event specific additional data
+ * @param[in]   DataParam3   Event specific additional data
+ * @param[in]   DataParam4   Event specific additional data
+ * @param[in]   StdHeader    Header for library and services
+ *
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 Index;
+  AGESA_STRUCT_BUFFER *AgesaEventAlloc;
+
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\n * %s Event: %08x Data: %x, %x, %x, %x\n\n",
+                    (EventClass == AGESA_FATAL)       ? "FATAL"       :
+                    (EventClass == AGESA_CRITICAL)    ? "CRITICAL"    :
+                    (EventClass == AGESA_ERROR)       ? "ERROR"       :
+                    (EventClass == AGESA_WARNING)     ? "WARNING"     :
+                    (EventClass == AGESA_ALERT)       ? "ALERT"       :
+                    (EventClass == AGESA_BOUNDS_CHK)  ? "BOUNDS_CHK"  :
+                    (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" :
+                    "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4);
+
+  AgesaEventAlloc = NULL;
+  GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
+  ASSERT (AgesaEventAlloc != NULL);
+  Index = AgesaEventAlloc->WriteRecordPtr;
+
+  // Add the new event log data into a circular buffer
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass = EventClass;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo  = EventInfo;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1 = DataParam1;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2 = DataParam2;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3 = DataParam3;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4 = DataParam4;
+
+  if ((AgesaEventAlloc->WriteRecordPtr == AgesaEventAlloc->ReadRecordPtr) &&
+             (AgesaEventAlloc->ReadWriteFlag == 0)) {
+    AgesaEventAlloc->WriteRecordPtr += 1;
+    AgesaEventAlloc->ReadRecordPtr += 1;
+    if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) {
+      AgesaEventAlloc->WriteRecordPtr = 0;
+      AgesaEventAlloc->ReadRecordPtr  = 0;
+    }
+  } else {
+    AgesaEventAlloc->WriteRecordPtr += 1;
+    if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) {
+      AgesaEventAlloc->WriteRecordPtr = 0;
+    }
+    AgesaEventAlloc->ReadWriteFlag = 0;
+  }
+  AgesaEventAlloc->Count = AgesaEventAlloc->Count + 1;
+
+  if (AgesaEventAlloc->Count <= TOTAL_EVENT_LOG_BUFFERS) {
+    AgesaEventAlloc->AgesaEventStruct[Index].Count = Index;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function gets event logs from the circular buffer.
+ *
+ * It will read the oldest entry from the circular buffer and place that information to the structure
+ * pointed to by the parameter. The read pointers will be incremented to remove the entry from buffer
+ * so that a subsequent call will return the next entry from the buffer. If the buffer is empty the
+ * returned log event will have EventInfo zero, which is not a valid event id.
+ *
+ * @param[out]  EventRecord    The next log event.
+ * @param[in]   StdHeader    Header for library and services
+ *
+ * @retval      AGESA_SUCCESS     Always succeeds.
+ *
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 Index;
+  AGESA_STRUCT_BUFFER *AgesaEventAlloc;
+
+  AgesaEventAlloc = NULL;
+
+  GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
+  ASSERT (AgesaEventAlloc != NULL);
+
+  if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) &&
+      (AgesaEventAlloc->ReadWriteFlag == 1)) {
+    // EventInfo == zero, means no more data.
+    LibAmdMemFill (EventRecord, 0, sizeof (AGESA_EVENT), StdHeader);
+  } else {
+    Index = AgesaEventAlloc->ReadRecordPtr;
+    EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass;
+    EventRecord->EventInfo  = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo;
+    EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1;
+    EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2;
+    EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3;
+    EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4;
+    if (AgesaEventAlloc->ReadRecordPtr == (TOTAL_EVENT_LOG_BUFFERS - 1)) {
+      AgesaEventAlloc->ReadRecordPtr = 0;
+    } else {
+      AgesaEventAlloc->ReadRecordPtr = AgesaEventAlloc->ReadRecordPtr + 1;
+    }
+    if (AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) {
+      AgesaEventAlloc->ReadWriteFlag = 1;
+    }
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function gets event logs from the circular buffer without flushing the entry.
+ *
+ * It will read the desired entry from the circular buffer and place that information to the structure
+ * pointed to by the parameter. The read pointers will not be incremented to remove the entry from the
+ * buffer. If the buffer is empty, or the desired entry does not exist, FALSE will be returned.
+ *
+ * @param[out]  EventRecord  The next log event.
+ * @param[in]   Index        Zero-based unread entry index
+ * @param[in]   StdHeader    Header for library and services
+ *
+ * @retval      TRUE         Entry exists
+ * @retval      FALSE        Entry does not exist
+ *
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 ActualIndex;
+  UINT16 UnreadEntries;
+  AGESA_STRUCT_BUFFER *AgesaEventAlloc;
+
+  AgesaEventAlloc = NULL;
+
+  GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
+  ASSERT (AgesaEventAlloc != NULL);
+
+  if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) &&
+      (AgesaEventAlloc->ReadWriteFlag == 1)) {
+    // EventInfo == zero, means no more data.
+    return FALSE;
+  }
+  if (AgesaEventAlloc->ReadRecordPtr < AgesaEventAlloc->WriteRecordPtr) {
+    UnreadEntries = AgesaEventAlloc->WriteRecordPtr - AgesaEventAlloc->ReadRecordPtr;
+  } else {
+    UnreadEntries = TOTAL_EVENT_LOG_BUFFERS - (AgesaEventAlloc->ReadRecordPtr - AgesaEventAlloc->WriteRecordPtr);
+  }
+  if (Index >= UnreadEntries) {
+    return FALSE;
+  }
+  ActualIndex = Index + AgesaEventAlloc->ReadRecordPtr;
+  if (ActualIndex >= TOTAL_EVENT_LOG_BUFFERS) {
+    ActualIndex -= TOTAL_EVENT_LOG_BUFFERS;
+  }
+
+  EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventClass;
+  EventRecord->EventInfo  = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventInfo;
+  EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam1;
+  EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam2;
+  EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam3;
+  EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam4;
+
+  return TRUE;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function gets the Event Log pointer.
+ *
+ * It will locate the Event Log on the heap using the heap locate service.  If the Event
+ * Log is not located, NULL is returned.
+ *
+ * @param[out]  EventLog  Pointer to the Event Log, or NULL.
+ * @param[in]   StdHeader Our Configuration, for passing to services.
+ *
+ */
+VOID
+STATIC
+GetEventLogHeapPointer (
+     OUT   AGESA_STRUCT_BUFFER **EventLog,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateHeapStruct;
+
+  LocateHeapStruct.BufferHandle = EVENT_LOG_BUFFER_HANDLE;
+  LocateHeapStruct.BufferPtr = NULL;
+  if ((HeapLocateBuffer (&LocateHeapStruct, StdHeader)) == AGESA_SUCCESS) {
+    *EventLog = (AGESA_STRUCT_BUFFER *)LocateHeapStruct.BufferPtr;
+  } else {
+    *EventLog = NULL;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c
new file mode 100644
index 0000000000..c3659cb28a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c
@@ -0,0 +1,510 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Family Translation functions.
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "CommonReturns.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUFAMILYTRANSLATION_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuNullServices =
+{
+  0,
+  (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess,
+  (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+  (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_NB_FREQ) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
+  (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_NB_IDD_MAX) CommonReturnFalse,
+  (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse,
+  (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8,
+  (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess,
+  (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+  (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnZero32,
+  (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+  (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess,
+  (PF_CPU_SAVE_FEATURES) CommonReturnAgesaSuccess,
+  (PF_CPU_WRITE_FEATURES) CommonReturnAgesaSuccess,
+  (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+  (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+  (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+  (PF_SET_HT_PHY_REGISTER) CommonVoid,
+  (PF_GET_NEXT_HT_LINK_FEATURES) CommonVoid,
+  NULL,
+  NULL,
+  NULL,
+  NULL,
+  InitCacheDisabled,
+  (PF_GET_EARLY_INIT_TABLE) CommonVoid
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetCpuServices (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT64            *MatchData,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
+extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Returns the logical ID of the desired processor. This will be obtained by
+ *  reading the CPUID and converting it into a "logical ID" which is not package
+ *  dependent.
+ *
+ *  @param[in]      Socket             Socket
+ *  @param[out]     LogicalId          The Processor's Logical ID
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetLogicalIdOfSocket (
+  IN       UINT32 Socket,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32      RawCpuid;
+  PCI_ADDR    PciAddress;
+  AGESA_STATUS AssumedSuccess;
+
+  RawCpuid = 0;
+
+  if (GetPciAddress (StdHeader, (UINT8)Socket, 0, &PciAddress, &AssumedSuccess)) {
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = CPUID_FMR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RawCpuid, StdHeader);
+    GetLogicalIdFromCpuid (RawCpuid, LogicalId, StdHeader);
+  } else {
+    LogicalId->Family = 0;
+    LogicalId->Revision = 0;
+    // Logical ID was not found.
+    IDS_ERROR_TRAP;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Returns the logical ID of the executing core. This will be obtained by reading
+ *  the CPUID and converting it into a "logical ID" which is not package dependent.
+ *
+ *  @param[out]     LogicalId          The Processor's Logical ID
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetLogicalIdOfCurrentCore (
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader);
+  GetLogicalIdFromCpuid (CpuidDataStruct.EAX_Reg, LogicalId, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Returns the logical ID of a processor with the given CPUID value. This
+ *  will be obtained by converting it into a "logical ID" which is not package
+ *  dependent.
+ *
+ *  @param[in]      RawCpuid           The unprocessed CPUID value to be translated
+ *  @param[out]     LogicalId          The Processor's Logical ID
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services
+ *
+ */
+VOID
+GetLogicalIdFromCpuid (
+  IN       UINT32 RawCpuid,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8       i;
+  UINT8       k;
+  UINT8       NumberOfFamiliesSupported;
+  UINT8       NumberOfLogicalSubFamilies;
+  UINT8       LogicalIdEntries;
+  UINT32      j;
+  UINT32      RawFamily;
+  UINT32      CpuModelAndExtendedModel;
+  UINT64      LogicalFamily;
+  BOOLEAN     IdNotFound;
+  BOOLEAN     FamilyNotFound;
+  CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdPtr;
+  CPU_LOGICAL_ID_XLAT *CpuLogicalIdAndRevPtr;
+  CONST CPU_LOGICAL_ID_FAMILY_XLAT *ImageSupportedId;
+
+  IdNotFound = TRUE;
+  FamilyNotFound = TRUE;
+  CpuLogicalIdAndRevPtr = NULL;
+  ImageSupportedId = CpuSupportedFamilyIdTable.FamilyIdTable;
+  NumberOfFamiliesSupported = CpuSupportedFamilyIdTable.Elements;
+
+  RawFamily = ((RawCpuid & 0xF00) >> 8) + ((RawCpuid & 0xFF00000) >> 20);
+  RawCpuid &= (UINT32) CPU_FMS_MASK;
+  CpuModelAndExtendedModel = (UINT16) ((RawCpuid >> 8) | RawCpuid);
+
+  LogicalId->Family = 0;
+  LogicalId->Revision = 0;
+
+  for (i = 0; i < NumberOfFamiliesSupported && FamilyNotFound; i++) {
+    if (ImageSupportedId[i].Family == RawFamily) {
+      FamilyNotFound = FALSE;
+      LogicalId->Family = ImageSupportedId[i].UnknownRevision.Family;
+      LogicalId->Revision = ImageSupportedId[i].UnknownRevision.Revision;
+
+      NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements;
+      SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable;
+      for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) {
+        SubFamilyIdPtr[j] ((CONST CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader);
+        ASSERT (CpuLogicalIdAndRevPtr != NULL);
+        for (k = 0; k < LogicalIdEntries; k++) {
+          if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) {
+            IdNotFound = FALSE;
+            LogicalId->Family = LogicalFamily;
+            LogicalId->Revision = CpuLogicalIdAndRevPtr[k].LogicalId;
+            break;
+          }
+        }
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ *
+ *  @param[in]      Socket             The Processor in this Socket.
+ *  @param[out]     FunctionTable      The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetCpuServicesOfSocket (
+  IN       UINT32 Socket,
+     OUT   CONST CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable,
+                              Socket,
+                              (CONST VOID **) FunctionTable,
+                              StdHeader);
+  if (*FunctionTable == NULL) {
+    *FunctionTable = &cpuNullServices;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[in]      Socket             The Processor in this Socket.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetFeatureServicesOfSocket (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT32            Socket,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID CpuFamilyRevision;
+
+  GetLogicalIdOfSocket (Socket, &CpuFamilyRevision, StdHeader);
+  GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the executing core's family specific services structure.
+ *
+ *  @param[out]     FunctionTable      The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetCpuServicesOfCurrentCore (
+     OUT   CONST CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable,
+                                   (CONST VOID **) FunctionTable,
+                                   StdHeader);
+  if (*FunctionTable == NULL) {
+    *FunctionTable = &cpuNullServices;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetFeatureServicesOfCurrentCore (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID CpuFamilyRevision;
+
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ *
+ *  @param[in]      LogicalId          The Processor's logical ID.
+ *  @param[out]     FunctionTable      The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetCpuServicesFromLogicalId (
+  IN       CPU_LOGICAL_ID *LogicalId,
+     OUT   CONST CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable,
+                                   LogicalId,
+                                   (CONST VOID **) FunctionTable,
+                                   StdHeader);
+  if (*FunctionTable == NULL) {
+    *FunctionTable = &cpuNullServices;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[in]      LogicalId          The Processor's logical ID.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetFeatureServicesFromLogicalId (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       CPU_LOGICAL_ID    *LogicalId,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetCpuServices (FamilyTable, &LogicalId->Family, CpuServices, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Finds a family match in the given table, and returns the pointer to the
+ *  appropriate table.  If no match is found in the table, NULL will be returned.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[in]      MatchData          Family data that must match.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+STATIC
+GetCpuServices (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT64            *MatchData,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN IsFamily;
+  UINT8   i;
+  UINT8   NumberOfFamiliesSupported;
+  CONST CPU_SPECIFIC_SERVICES_XLAT *ImageSupportedFamiliesPtr;
+
+  ImageSupportedFamiliesPtr = FamilyTable->FamilyTable;
+  NumberOfFamiliesSupported = FamilyTable->Elements;
+  IsFamily = FALSE;
+  for (i = 0; i < NumberOfFamiliesSupported; i++) {
+    if ((ImageSupportedFamiliesPtr[i].Family & *MatchData) != 0) {
+      IsFamily = TRUE;
+      break;
+    }
+  }
+  if (IsFamily) {
+    *CpuServices = ImageSupportedFamiliesPtr[i].TablePtr;
+  } else {
+    *CpuServices = NULL;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Used to stub out various family specific tables of information.
+ *
+ *  @param[in]      FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]      Empty                   NULL, to indicate no data.
+ *  @param[out]     NumberOfElements        Zero, to indicate no data.
+ *  @param[in]      StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetEmptyArray (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   CONST VOID **Empty,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 0;
+  *Empty = NULL;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
new file mode 100644
index 0000000000..9abcfe48d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
@@ -0,0 +1,1034 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Family Translation functions.
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FAMILY_TRANSLATION_H_
+#define _CPU_FAMILY_TRANSLATION_H_
+
+/**
+ * @page cpuimplfss CPU Family Specific Services Implementation Guide
+ *
+ * CPU Family Specific Services provides access to supported family service functions and data,
+ * in a manner that isolates calling code from knowledge about particular families or which
+ * families are supported in the current build.
+ *
+ * @par Adding a Method to Family Specific Services
+ *
+ * To add a new method to Family Specific Services, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (*PF_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (*PF_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> [Optionally make the type F_<name> and provide a separate:
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME> </tt> @n
+ *     and provide a single line "///" doxygen comment brief description on the PF_ type.]
+ *   </ul>
+ *
+ * <li> The first parameter to @b all Family Specific Service Methods is @b required to be a reference to
+ *   their Family Service struct.
+ *   @n <tt> IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices </tt> @n
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef.  Begin the
+ *   detailed description by provide a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @CpuServiceInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the CPU_SPECIFIC_SERVICES struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing a Family Specific Instance of the method.
+ *
+ * To implement an instance of a method for a specific family follow these steps.
+ *
+ * - In appropriate files in the family specific directory, implement the method with the return type
+ *   and parameters matching the method typedef.
+ *
+ * - Name the function FnnMethodName(), where nn is the family number.
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @CpuServiceMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other family specific services as part of the method implementation, the function
+ *   @b must use FamilySpecificServices->OtherMethod().  Do not directly call other family specific
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple families.
+ *
+ * - Do @b not call Family translation services from a family specific instance.  Use the parameter.
+ *
+ * - Add the instance to the family specific CPU_SPECIFIC_SERVICES instance.
+ *
+ * - If a family does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking Family Specific Services.
+ *
+ * The following example shows how to invoke a family specific method.
+ * @n @code
+ *        CPU_SPECIFIC_SERVICES *FamilyServices;
+ *
+ *        GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ *        ASSERT (FamilyServices != NULL);
+ *        FamilyServices->MethodName (FamilyServices, StdHeader);
+ * @endcode
+ *
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+#include "cpuPostInit.h"
+#include "cpuEnvInit.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "Table.h"
+#include "Ids.h"
+#include "Topology.h"
+
+//  Forward declaration needed for multi-structure mutual references.
+AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES);
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/**
+ *  Disable the desired P-state.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             Hardware P-state number.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_DISABLE_PSTATE (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE;
+
+/**
+ *  Transition the current core to the desired P-state.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             Software P-state number.
+ *  @param[in]     WaitForChange           Wait/don't wait for P-state change to complete.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       BOOLEAN WaitForChange,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE;
+
+/**
+ *  Get the desired P-state's maximum current required in milliamps.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             The desired hardware P-state number.
+ *  @param[out]    ProcIddMax              The P-state's maximum current.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    The P-state is enabled, and ProcIddMax is valid.
+ *  @retval        FALSE                   The P-state is disabled.
+ *
+ */
+typedef BOOLEAN F_CPU_GET_IDD_MAX (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX;
+
+
+/**
+ *  Returns the rate at which the current core's timestamp counter increments in megahertz.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    FreqInMHz               The rate at which the TSC increments in megahertz.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_TSC_RATE (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32 *FreqInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE;
+
+/**
+ *  Returns the processor north bridge's clock rate in megahertz.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    FreqInMHz               The desired node's frequency in megahertz.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        AGESA_SUCCESS           FreqInMHz is valid.
+ */
+typedef AGESA_STATUS F_CPU_GET_NB_FREQ (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32 *FreqInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ;
+
+/**
+ *  Returns the node's minimum and maximum northbridge frequency.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[out]    MinFreqInMHz            The minimum north bridge frequency.
+ *  @param[out]    MaxFreqInMHz            The maximum north bridge frequency.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        AGESA_STATUS            Northbridge frequency is valid
+ */
+typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *MinFreqInMHz,
+     OUT   UINT32 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_MIN_MAX_NB_FREQ *PF_CPU_GET_MIN_MAX_NB_FREQ;
+
+/**
+ *  Returns the processor north bridge's P-state settings.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[in]     NbPstate                The NB P-state number to check.
+ *  @param[out]    FreqNumeratorInMHz      The desired node's frequency numerator in megahertz.
+ *  @param[out]    FreqDivisor             The desired node's frequency divisor.
+ *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    NbPstate is valid
+ *  @retval        FALSE                   NbPstate is disabled or invalid
+ */
+typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR *PciAddress,
+  IN       UINT32 NbPstate,
+     OUT   UINT32 *FreqNumeratorInMHz,
+     OUT   UINT32 *FreqDivisor,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_NB_PSTATE_INFO *PF_CPU_GET_NB_PSTATE_INFO;
+
+/**
+ *  Returns whether or not the NB frequency initialization sequence is required
+ *  to be performed by the BIOS.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PciAddress              The northbridge to query by pci base address.
+ *  @param[out]    NbVidUpdateAll          Do all NbVids need to be updated as well.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED;
+
+/**
+ *  Get the desired NB P-state's maximum current required in milliamps.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             The desired hardware P-state number.
+ *  @param[out]    NbIddMax                The NB P-state's maximum current.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    The NB P-state is enabled, and NbIddMax is valid.
+ *  @retval        FALSE                   The NB P-state is disabled.
+ *
+ */
+typedef BOOLEAN F_CPU_GET_NB_IDD_MAX (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *NbIddMax,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_NB_IDD_MAX *PF_CPU_GET_NB_IDD_MAX;
+
+/**
+ *  Launches the desired core from the reset vector.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     SocketNumber            The desired core's socket number.
+ *  @param[in]     ModuleNumber            The desired core's die number.
+ *  @param[in]     CoreNumber              The desired core's die relative core number.
+ *  @param[in]     PrimaryCoreNumber       SocketNumber / ModuleNumber's primary core number.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    The core was launched successfully.
+ *  @retval        FALSE                   The core was previously launched, or has a problem.
+ */
+typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32 SocketNumber,
+  IN       UINT32 ModuleNumber,
+  IN       UINT32 CoreNumber,
+  IN       UINT32 PrimaryCoreNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH;
+
+/**
+ *  Returns the appropriate number of physical processor cores
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        One-based number of physical cores on current processor
+ */
+typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_NUMBER_OF_PHYSICAL_CORES *PF_CPU_NUMBER_OF_PHYSICAL_CORES;
+
+/**
+ *  Returns a family specific table of information pointer and size.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    FamilySpecificArray     Pointer to the appropriate list for the core.
+ *  @param[out]    NumberOfElements        Number of valid entries FamilySpecificArray.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   CONST VOID **FamilySpecificArray,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY;
+
+/**
+ *  Returns a model specific list of logical IDs.
+ *
+ *  @param[out]    LogicalIdXlat           Installed logical ID table.
+ *  @param[out]    NumberOfElements        Number of entries in the Logical ID translate table.
+ *  @param[out]    LogicalFamily           Base logical family bit mask.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_CPU_GET_SUBFAMILY_ID_ARRAY (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **LogicalIdXlat,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a method.
+typedef F_CPU_GET_SUBFAMILY_ID_ARRAY *PF_CPU_GET_SUBFAMILY_ID_ARRAY;
+
+/**
+ *  Use the Mailbox Register to get the Ap Mailbox info for the current core.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    ApMailboxInfo           The AP Mailbox info
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE *PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE;
+
+/**
+ *  Set the AP core number in the AP's Mailbox.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     Socket                  The AP's socket
+ *  @param[in]     Module                  The AP's module
+ *  @param[in]     ApCoreNumber            The AP's unique core number
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_SET_AP_CORE_NUMBER) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32                 Socket,
+  IN       UINT32                 Module,
+  IN       UINT32                 ApCoreNumber,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_SET_AP_CORE_NUMBER *PF_CPU_SET_AP_CORE_NUMBER;
+
+/**
+ *  Get the AP core number from hardware.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_GET_AP_CORE_NUMBER *PF_CPU_GET_AP_CORE_NUMBER;
+
+/**
+ *  Move the AP's core number from the mailbox to hardware.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+typedef VOID (F_CPU_TRANSFER_AP_CORE_NUMBER) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_TRANSFER_AP_CORE_NUMBER *PF_CPU_TRANSFER_AP_CORE_NUMBER;
+
+/**
+ * Core ID position in the initial APIC ID, reflected as a number zero or one.
+ */
+typedef enum {
+  CoreIdPositionZero, ///< Zero, the Core Id bits are the Most Significant bits.
+  CoreIdPositionOne,  ///< One, the Core Id bits are the Least Significant bits.
+  CoreIdPositionMax   ///< Limit check.
+} CORE_ID_POSITION;
+
+/**
+ * Return a number zero or one, based on the Core ID position in the initial APIC Id.
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @retval        CoreIdPositionZero      Core Id is not low
+ * @retval        CoreIdPositionOne       Core Id is low
+ */
+typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID;
+
+/**
+ *  Get least common features set of all CPUs and save them to CPU_FEATURES_LIST
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in,out] cpuFeatureListPtr       The CPU Features List
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_SAVE_FEATURES) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST      *cpuFeatureListPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_SAVE_FEATURES *PF_CPU_SAVE_FEATURES;
+
+/**
+ *  Get least common features from CPU_FEATURES_LIST and write them to CPU
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in,out] cpuFeatureListPtr       The CPU Features List
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_WRITE_FEATURES) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST      *cpuFeatureListPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_WRITE_FEATURES *PF_CPU_WRITE_FEATURES;
+
+/**
+ *  Set Warm Reset Flag
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices  The current Family Specific Services.
+ * @param[in]      StdHeader     Header for library and services.
+ * @param[in]      Request       Value to set the flags to.
+ *
+ */
+typedef VOID (F_CPU_SET_WARM_RESET_FLAG) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+/// Reference to a method
+typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG;
+
+/**
+ *  Get Warm Reset Flag
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices  The current Family Specific Services.
+ * @param[in]      StdHeader     Header for library and services.
+ * @param[out]     BiosRstDet    Indicate warm reset status.
+ *
+ */
+typedef VOID (F_CPU_GET_WARM_RESET_FLAG) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  );
+
+/// Reference to a method
+typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG;
+
+
+/**
+ *  Get CPU Specific Platform Type Info.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[in,out] FeaturesUnion                  The Features supported by this platform.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PLATFORM_FEATS         *FeaturesUnion,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO;
+
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      PlatformConfig                 Platform profile/build option config structure.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+typedef BOOLEAN F_IS_NB_PSTATE_ENABLED (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED;
+
+/**
+ * Gets the next link with features matching the HT phy register table entry type features.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]     FamilySpecificServices   The current Family Specific Services.
+ * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0;
+ *                                         Each call returns the HT Host Capability function and offset;
+ *                                         Caller may use it to access registers, but must @b not modify it;
+ *                                         Each new call passes the previous value as input.
+ * @param[in,out] Link             Initially zero, each call returns the link number; caller passes it back unmodified each call.
+ * @param[in]     HtPhyLinkType    Link type field from a register table entry to compare against
+ * @param[out]    MatchedSublink1  TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
+ * @param[out]    Frequency0       The frequency of sublink0 (200 MHz if not connected).
+ * @param[out]    Frequency1       The frequency of sublink1 (200 MHz if not connected).
+ * @param[in]     StdHeader        Standard Head Pointer
+ *
+ * @retval        TRUE             Link matches
+ * @retval        FALSE            No more links
+ *
+ */
+typedef BOOLEAN F_NEXT_LINK_HAS_HTFPY_FEATS (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PCI_ADDR           *HtHostCapability,
+  IN OUT   UINT32             *Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+     OUT   BOOLEAN            *MatchedSublink1,
+     OUT   HT_FREQUENCIES     *Frequency0,
+     OUT   HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+/// Reference to a Method.
+typedef F_NEXT_LINK_HAS_HTFPY_FEATS *PF_NEXT_LINK_HAS_HTFPY_FEATS;
+
+/**
+ * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]  FamilySpecificServices    The current Family Specific Services.
+ * @param[in]  HtPhyEntry                HT Phy register table entry to apply
+ * @param[in]  CapabilitySet             The link's HT Host base address.
+ * @param[in]  Link                      Zero based, node, link number (not package link), always a sublink0 link.
+ * @param[in]  StdHeader                 Config handle for library and services
+ *
+ */
+typedef VOID F_SET_HT_PHY_REGISTER (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                CapabilitySet,
+  IN       UINT32                  Link,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_SET_HT_PHY_REGISTER *PF_SET_HT_PHY_REGISTER;
+
+/**
+ * Performs an early initialization function on the executing core.
+ *
+ * @param[in]  FamilyServices            The current Family Specific Services.
+ * @param[in]  EarlyParams               CPU module early paramters.
+ * @param[in]  StdHeader                 Config handle for library and services
+ *
+ */
+typedef VOID F_PERFORM_EARLY_INIT_ON_CORE (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_PERFORM_EARLY_INIT_ON_CORE *PF_PERFORM_EARLY_INIT_ON_CORE;
+
+/**
+ * A struct that contains function pointer and function flag
+ *
+ * the flag indicates if the function need to be run.
+ */
+typedef struct _S_PERFORM_EARLY_INIT_ON_CORE {
+  PF_PERFORM_EARLY_INIT_ON_CORE PerformEarlyInitOnCore; ///< Function Pointer, which points to the function need to be run at early stage
+  UINT32 PerformEarlyInitFlag; ///< Function Flag, which indicates if the function need to be run.
+} S_PERFORM_EARLY_INIT_ON_CORE;
+
+/**
+ * Returns the initialization steps that the executing core should
+ * perform at AmdInitEarly.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]  FamilyServices            The current Family Specific Services.
+ * @param[out] Table                     Table of appropriate init steps for the executing core.
+ * @param[in]  EarlyParams               CPU module early paramters.
+ * @param[in]  StdHeader                 Config handle for library and services
+ *
+ */
+typedef VOID F_GET_EARLY_INIT_TABLE (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_EARLY_INIT_TABLE *PF_GET_EARLY_INIT_TABLE;
+
+/**
+ * Provide the features of the next HT link.
+ *
+ *  @CpuServiceInstances
+ *
+ * This method is different than the HT Phy Features method, because for the phy registers
+ * sublink 1 matches and should be programmed if the link is ganged but for PCI config
+ * registers sublink 1 is reserved if the link is ganged.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[in,out] Link                      The link number, for accessing non-capability set registers.
+ *                                          Zero on initial call, and passed back unmodified on each subsequent call.
+ * @param[in,out] LinkBase                  IN: initially the node's PCI config base address, passed back on each call.
+ *                                          OUT: the base HT Host capability PCI address for the link.
+ * @param[out]    HtHostFeats               The link's features.
+ * @param[in]     StdHeader                 Standard Head Pointer
+ *
+ * @retval        TRUE                      Valid link and features found.
+ * @retval        FALSE                     No more links.
+ */
+typedef BOOLEAN F_GET_NEXT_HT_LINK_FEATURES (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   UINTN                  *Link,
+  IN OUT   PCI_ADDR               *LinkBase,
+     OUT   HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_NEXT_HT_LINK_FEATURES *PF_GET_NEXT_HT_LINK_FEATURES;
+
+/// Cache Enable / Disable policy before giving control back to OS.
+typedef enum {
+  InitCacheDisabled,            ///<Disable cache CR0.CD bit
+  InitCacheEnabled              ///<Enable cache CR0.CD bit
+} FAMILY_CACHE_INIT_POLICY;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the interface to all cpu Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ * See CPU Family Specific Services Implementation Guide for adding new services.
+ */
+struct _CPU_SPECIFIC_SERVICES {                                         // See the Forwaqrd Declaration above
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_CPU_DISABLE_PSTATE DisablePstate;                                  ///< Method: Disable the desired P-state.
+  PF_CPU_TRANSITION_PSTATE TransitionPstate;                            ///< Method: Transition the current core to the desired P-state.
+  PF_CPU_GET_IDD_MAX GetProcIddMax;                                     ///< Method: Gets P-state maximum current required
+  PF_CPU_GET_TSC_RATE GetTscRate;                                       ///< Method: Returns the rate at which the current core's timestamp counter increments in megahertz.
+  PF_CPU_GET_NB_FREQ GetCurrentNbFrequency;                             ///< Method: Returns the processor north bridge's clock rate in megahertz.
+  PF_CPU_GET_MIN_MAX_NB_FREQ GetMinMaxNbFrequency;                      ///< Method: Returns the node's minimum and maximum northbridge frequency.
+  PF_CPU_GET_NB_PSTATE_INFO GetNbPstateInfo;                            ///< Method: Returns information about the processor north bridge's P-states.
+  PF_CPU_IS_NBCOF_INIT_NEEDED IsNbCofInitNeeded;                        ///< Method: Returns whether or not the NB frequency initialization sequence is required to be performed by the BIOS.
+  PF_CPU_GET_NB_IDD_MAX GetNbIddMax;                                    ///< Method: Gets NB P-state maximum current required
+  PF_CPU_AP_INITIAL_LAUNCH LaunchApCore;                                ///< Method: Launches the desired core from the reset vector.
+  PF_CPU_NUMBER_OF_PHYSICAL_CORES GetNumberOfPhysicalCores;             ///< Method: Get the number of physical cores of current processor.
+  PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE GetApMailboxFromHardware;     ///< Method: Get the AP's topology info from the hardware mailbox.
+  PF_CPU_SET_AP_CORE_NUMBER SetApCoreNumber;                            ///< Method: Set the AP's core number to the hardware mailbox.
+  PF_CPU_GET_AP_CORE_NUMBER GetApCoreNumber;                            ///< Method: Get the AP's core number from hardware.
+  PF_CPU_TRANSFER_AP_CORE_NUMBER TransferApCoreNumber;                  ///< Method: Move the AP's core number from the mailbox to hardware.
+  PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID CoreIdPositionInInitialApicId; ///< Method: Which bits in initial APIC Id are the Core Id.
+  PF_CPU_SAVE_FEATURES SaveFeatures;                                    ///< Method: Get least common features set of all CPUs and save them to CPU_FEATURES_LIST
+  PF_CPU_WRITE_FEATURES WriteFeatures;                                  ///< Method: Get least common features from CPU_FEATURES_LIST and write them to CPU
+  PF_CPU_SET_WARM_RESET_FLAG SetWarmResetFlag;                          ///< Method: Set Warm Reset Flag
+  PF_CPU_GET_WARM_RESET_FLAG GetWarmResetFlag;                          ///< Method: Get Warm Reset Flag
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString1;                     ///< Method: Get a Brand String table
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString2;                     ///< Method: Get a Brand String table
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicroCodePatchesStruct;           ///< Method: Get microcode patches
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicrocodeEquivalenceTable;        ///< Method: Get CPU equivalence for loading microcode patches.
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetCacheInfo;                        ///< Method: Get setup for cache use and initialization.
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetSysPmTableStruct;                 ///< Method: Get Power Management settings.
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetWheaInitData;                     ///< Method: Get Whea Initial Data.
+  PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO GetPlatformTypeSpecificInfo;   ///< Method: Get Specific platform Type features.
+  PF_IS_NB_PSTATE_ENABLED IsNbPstateEnabled;                            ///< Method: Get whether Northbridge PStates feature is enabled.
+  PF_NEXT_LINK_HAS_HTFPY_FEATS NextLinkHasHtPhyFeats;                   ///< Method: Iterate over HT Links matching features, for HT PHY entries.
+  PF_SET_HT_PHY_REGISTER SetHtPhyRegister;                              ///< Method: Set an Ht Phy register based on table entry.
+  PF_GET_NEXT_HT_LINK_FEATURES GetNextHtLinkFeatures;                   ///< Method: Iterate over HT links, returning link features.
+  REGISTER_TABLE **RegisterTableList;                                   ///< Public Data: The available register tables.
+  TABLE_ENTRY_TYPE_DESCRIPTOR *TableEntryTypeDescriptors;               ///< Public Data: implemented register table entry types.
+  PACKAGE_HTLINK_MAP PackageLinkMap;                                    ///< Public Data: translate northbridge HT links to package level links, or NULL.
+  CORE_PAIR_MAP *CorePairMap;                                           ///< Public Data: translate compute unit core pairing, or NULL.
+  FAMILY_CACHE_INIT_POLICY InitCacheDisabled;                           ///< public Data: Family related information.
+  PF_GET_EARLY_INIT_TABLE GetEarlyInitOnCoreTable;                      ///< Method: Get the initialization steps needed at AmdInitEarly.
+};
+
+/**
+ * A Family Id and an interface to it's implementations of Family Specific Services.
+ *
+ * Note that this is a logical family id, which may specify family, model (or even stepping).
+ */
+typedef struct {
+  UINT64          Family;                         ///< The Family to which this interface belongs.
+  CONST VOID      *TablePtr;                      ///< The interface to its Family Specific Services.
+} CPU_SPECIFIC_SERVICES_XLAT;
+
+/**
+ * A collection of Family specific interfaces to Family Specific services.
+ */
+typedef struct {
+  UINT8  Elements;                                       ///< The number of tables to search.
+  CONST    CPU_SPECIFIC_SERVICES_XLAT *FamilyTable;      ///< The family interfaces.
+} CPU_FAMILY_SUPPORT_TABLE;
+
+/**
+ * Implement the translation of a logical CPU id to an id that can be used to get Family specific services.
+ */
+typedef struct {
+  UINT32 Family;                                              ///< Provide translation for this family
+  CPU_LOGICAL_ID UnknownRevision;                             ///< In this family, unrecognized models (or steppings) are treated as though they were this model and stepping.
+  CONST    PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdTable;   ///< Method: Get family specific model (and stepping) resolution.
+  UINT8  Elements;                                            ///< The number of family specific model tables pointed to by SubFamilyIdTable
+} CPU_LOGICAL_ID_FAMILY_XLAT;
+
+/**
+ * A collection of all available family id translations.
+ */
+typedef struct {
+  UINT8  Elements;                                            ///< The number of family translation items to search.
+  CONST    CPU_LOGICAL_ID_FAMILY_XLAT *FamilyIdTable;         ///< The family translation items.
+} CPU_FAMILY_ID_XLAT_TABLE;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a logical identifier for the specified processor, based on CPUID, but independent of CPUID formatting.
+ */
+VOID
+GetLogicalIdOfSocket (
+  IN       UINT32 Socket,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get a logical identifier for the executing core, based on CPUID, but independent of CPUID formatting.
+ */
+VOID
+GetLogicalIdOfCurrentCore (
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get a logical identifier for the specified CPUID value.
+ */
+VOID
+GetLogicalIdFromCpuid (
+  IN       UINT32 RawCpuid,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ */
+VOID
+GetCpuServicesOfSocket (
+  IN       UINT32 Socket,
+     OUT   CONST CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ */
+VOID
+GetFeatureServicesOfSocket (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT32            Socket,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the executing core's family specific services structure.
+ */
+VOID
+GetCpuServicesOfCurrentCore (
+     OUT   CONST CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the executing core's family specific services structure.
+ */
+VOID
+GetFeatureServicesOfCurrentCore (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ */
+VOID
+GetCpuServicesFromLogicalId (
+  IN       CPU_LOGICAL_ID *LogicalId,
+     OUT   CONST CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ */
+VOID
+GetFeatureServicesFromLogicalId (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       CPU_LOGICAL_ID    *LogicalId,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Used by logical families which don't need a certain register setting table or other data array.
+ */
+VOID
+GetEmptyArray (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   CONST VOID **Empty,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_FAMILY_TRANSLATION_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c
new file mode 100644
index 0000000000..378a89a77b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c
@@ -0,0 +1,1263 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Implement External, AGESA Common, and CPU component General Services.
+ *
+ * Contains implementation of the interfaces: General Services API in AGESA.h,
+ * GeneralServices.h, and cpuServices.h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Options.h"
+#include "Topology.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUGENERALSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTIONS_CONFIG_TOPOLOGY TopologyConfiguration;
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - External General Services API
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * Invoke corresponding Cpu Service for external user.
+ *
+ * @param[in,out]    AmdParamApic    Our interface struct
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT   AMD_APIC_PARAMS *AmdParamApic
+  )
+{
+  AGESA_STATUS AgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdGetApicIdEntry, &AmdParamApic->StdHeader);
+  AmdParamApic->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamApic->StdHeader);
+
+  AmdParamApic->IsPresent = GetApicId (
+    &AmdParamApic->StdHeader,
+    AmdParamApic->Socket,
+    AmdParamApic->Core,
+    &AmdParamApic->ApicAddress,
+    &AgesaStatus
+    );
+
+  AGESA_TESTPOINT (TpIfAmdGetApicIdExit, &AmdParamApic->StdHeader);
+  return AgesaStatus;
+}
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * Invoke corresponding Cpu Service for external user.
+ *
+ * @param[in,out]    AmdParamGetPci    Our interface struct
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+  )
+{
+  AGESA_STATUS AgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdGetPciAddressEntry, &AmdParamGetPci->StdHeader);
+  AmdParamGetPci->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamGetPci->StdHeader);
+
+  AmdParamGetPci->IsPresent = GetPciAddress (
+    &AmdParamGetPci->StdHeader,
+    AmdParamGetPci->Socket,
+    AmdParamGetPci->Module,
+    &AmdParamGetPci->PciAddress,
+    &AgesaStatus
+    );
+
+  AGESA_TESTPOINT (TpIfAmdGetPciAddressExit, &AmdParamGetPci->StdHeader);
+  return AgesaStatus;
+}
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * Invoke corresponding Cpu Service for external user.
+ *
+ * @param[in,out]    AmdParamIdentify    Our interface struct
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT   AMD_IDENTIFY_PARAMS *AmdParamIdentify
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Core;
+
+  AGESA_TESTPOINT (TpIfAmdIdentifyCoreEntry, &AmdParamIdentify->StdHeader);
+  AmdParamIdentify->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamIdentify->StdHeader);
+
+  IdentifyCore (
+    &AmdParamIdentify->StdHeader,
+    &Socket,
+    &Module,
+    &Core,
+    &AgesaStatus
+    );
+  AmdParamIdentify->Socket = (UINT8)Socket;
+  AmdParamIdentify->Module = (UINT8)Module;
+  AmdParamIdentify->Core = (UINT8)Core;
+
+  AGESA_TESTPOINT (TpIfAmdIdentifyCoreExit, &AmdParamIdentify->StdHeader);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - AGESA common General Services
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * Code sync: This calculation MUST match the assignment
+ *    calculation done in LocalApicInitializationAtEarly function.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The socket in which the Core's Processor is installed.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+*/
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  BOOLEAN ReturnValue;
+  UINT32  CoreCount;
+  UINT32  ApicID;
+
+  ReturnValue = FALSE;
+  if (GetActiveCoresInGivenSocket (Socket, &CoreCount, StdHeader)) {
+    if (Core < CoreCount) {
+      ReturnValue = TRUE;
+      GetLocalApicIdForCore (Socket, Core, &ApicID, StdHeader);
+      *ApicAddress = (UINT8) ApicID;
+    }
+  }
+
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  return ReturnValue;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  UINT8        Node;
+  BOOLEAN      Result;
+
+  ASSERT (Socket < MAX_SOCKETS);
+  ASSERT (Module < MAX_DIES);
+
+  Result = TRUE;
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  if (GetNodeId (Socket, Module, &Node, StdHeader)) {
+    // socket is populated
+    PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    PciAddress->Address.Device = PciAddress->Address.Device + Node;
+  } else {
+    // socket is not populated
+    PciAddress->AddressValue = ILLEGAL_SBDFO;
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  AP_MAIL_INFO ApMailboxInfo;
+  UINT32 CurrentCore;
+
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS);
+  ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES);
+  *Socket = (UINT8)ApMailboxInfo.Fields.Socket;
+  *Module = (UINT8)ApMailboxInfo.Fields.Module;
+
+  // Get Core Id
+  GetCurrentCore (&CurrentCore, StdHeader);
+  *Core = (UINT8)CurrentCore;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - cpu component General Services
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the current Platform's number of Sockets, regardless of how many are populated.
+ *
+ * The Options component can provide how many sockets are available in system.
+ * This can be used to avoid testing presence of Processors in Sockets which don't exist.
+ * The result can be one socket to the maximum possible sockets of any supported processor family.
+ * You cannot assume that all sockets contain a processor or that the sockets have processors
+ * installed in any particular order.  Do not convert this number to a number of nodes.
+ *
+ * @return   The number of available sockets for the platform.
+ *
+ */
+UINT32
+GetPlatformNumberOfSockets ( VOID )
+{
+  return TopologyConfiguration.PlatformNumberOfSockets;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the number of Modules to check presence in each Processor.
+ *
+ * The Options component can provide how many modules need to be check for presence in each
+ * processor, regardless whether all, or any, processor have that many modules present on this boot.
+ * The result can be one module to the maximum possible modules of any supported processor family.
+ * You cannot assume that Modules are in any particular order, especially with respect to node id.
+ *
+ * @return   The maximum number of modules in each processor.
+ *
+ */
+UINT32
+GetPlatformNumberOfModules ( VOID )
+{
+  return TopologyConfiguration.PlatformNumberOfModules;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is a processor present in Socket?
+ *
+ * Check to see if any possible module of the processor is present.  This provides
+ * support for a few cases where a PCI address isn't needed, but code still needs to
+ * iterate by Socket.
+ *
+ * @param[in]   Socket  The socket which is being tested
+ * @param[in]   StdHeader    Header for library and services.
+ *
+ * @retval      TRUE    The socket has a processor installed
+ * @retval      FALSE   The socket is empty (or the processor is dead).
+ *
+ */
+BOOLEAN
+IsProcessorPresent (
+  IN       UINT32             Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+  UINT32 Module;
+  AGESA_STATUS Status;
+
+  ASSERT (Socket < MAX_SOCKETS);
+  Result = FALSE;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
+      Result = TRUE;
+      break;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the number of installed processors (not Nodes! and not Sockets!)
+ *
+ * Iterate over the Socket, Module to Node Map, counting the number of present nodes.
+ * Do not use this as a Node Count!  Do not use this as the number of Sockets!  (This
+ * is for APIC ID utilities.)
+ *
+ * @param[in]   StdHeader    Header for library and services.
+ *
+ * @return      the number of processors installed
+ *
+ */
+UINT32
+GetNumberOfProcessors (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  UINT32 Result;
+  UINT32 Socket;
+  UINT32 Module;
+  AGESA_STATUS Status;
+
+  Result = 0;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+      if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
+        Result++;
+        break;
+      }
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * For a specific Node, get its Socket and Module ids.
+ *
+ * If asking for the current running Node, read the mailbox socket, module. Specific Node,
+ * locate the Node to Socket/Module Map in heap, and return the ids, if present.
+ *
+ * @param[in]    Node         What Socket and Module is this Node?
+ * @param[out]   Socket       The Socket containing that Node.
+ * @param[out]   Module       The Processor Module of that Node.
+ * @param[in]    StdHeader    Header for library and services.
+ *
+ * @retval TRUE Node is present, Socket, Module are valid.
+ * @retval FALSE Node is not present, why do you ask?
+ */
+BOOLEAN
+GetSocketModuleOfNode (
+  IN       UINT32    Node,
+     OUT   UINT32    *Socket,
+     OUT   UINT32    *Module,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  NODE_TO_SOCKET_DIE_MAP  pNodeMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+  AGESA_STATUS Status;
+
+  Result = FALSE;
+
+  ASSERT (Node < MAX_NODES);
+
+  //  Get Map from heap
+  SocketDieHeapDataBlock.BufferHandle = NODE_ID_MAP_HANDLE;
+  Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pNodeMap = (NODE_TO_SOCKET_DIE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pNodeMap != NULL) && (Status == AGESA_SUCCESS));
+  *Socket = (*pNodeMap)[Node].Socket;
+  *Module = (*pNodeMap)[Node].Die;
+  if ((*pNodeMap)[Node].Socket != 0xFF) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the current core's Processor APIC Index.
+ *
+ * The Processor APIC Index is the position of the current processor in the APIC id
+ * assignment.  Processors are ordered in node id order.  This is not the same, however,
+ * as the node id of the current socket and module or the current socket id.
+ *
+ * @param[in]    Node      The current desired core's node id (usually the current core).
+ * @param[in]    StdHeader Header for library and services.
+ *
+ * @return  Processor APIC Index
+ *
+ */
+UINT32
+GetProcessorApicIndex (
+  IN       UINT32            Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProcessorApicIndex;
+  UINT32 PreviousSocket;
+  UINT32 CurrentSocket;
+  UINT32 Ignored;
+  UINT32 i;
+
+  ASSERT (Node < MAX_NODES);
+
+  // Calculate total APIC devices up to Current Node, Core.
+  ProcessorApicIndex = 0;
+  PreviousSocket = 0xFF;
+  for (i = 0; i < (Node + 1); i++) {
+    GetSocketModuleOfNode (i, &CurrentSocket, &Ignored, StdHeader);
+    if (CurrentSocket != PreviousSocket) {
+      ProcessorApicIndex++;
+      PreviousSocket = CurrentSocket;
+    }
+  }
+  // Convert to Index (zero based) from count (one based).
+  ProcessorApicIndex--;
+  return ProcessorApicIndex;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns current node number
+ *
+ *  @param[out]      Node       This Core's Node id
+ *  @param[in]        StdHeader  Header for library and services.
+ *
+ */
+VOID
+GetCurrentNodeNum (
+     OUT   UINT32 *Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_MAIL_INFO ApMailboxInfo;
+
+  // Get the Node Id from the Mailbox.
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
+  *Node = ApMailboxInfo.Fields.Node;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns Total number of active cores in the current socket
+ *
+ * @param[out]     CoreCount    The cores in this processor.
+ * @param[in]      StdHeader    Header for library and services.
+ *
+ */
+VOID
+GetActiveCoresInCurrentSocket (
+     OUT   UINT32 *CoreCount,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+  UINT32 TotalCoresCount;
+
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader);
+  TotalCoresCount = (CpuidDataStruct.ECX_Reg & 0x000000FF) + 1;
+  *CoreCount = TotalCoresCount;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provides the Total number of active cores in the current core's node.
+ *
+ * @param[in]      StdHeader   Header for library and services.
+ *
+ * @return         The current node core count
+ */
+UINTN
+GetActiveCoresInCurrentModule (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Core;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 ProcessorCoreCount;
+  AGESA_STATUS AgesaStatus;
+
+  ProcessorCoreCount = 0;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
+  if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+    ProcessorCoreCount = ((HighCore - LowCore) + 1);
+  }
+  return ProcessorCoreCount;
+}
+
+/**
+ * Provide the number of compute units on current module.
+ *
+ *
+ * @param[in]   StdHeader    Header for library and services.
+ *
+ * @return      The current compute unit counts.
+ *
+ */
+UINTN
+GetNumberOfCompUnitsInCurrentModule (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                 Socket;
+  UINT32                 Module;
+  UINT32                 CurrentCore;
+  UINT32                 ComputeUnitCount;
+  UINT32                 Enabled;
+  AGESA_STATUS           IgnoredSts;
+  LOCATE_HEAP_PTR        SocketDieHeapDataBlock;
+  SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
+
+  ComputeUnitCount = 0;
+
+  ASSERT ((GetComputeUnitMapping (StdHeader) == AllCoresMapping) ||
+          (GetComputeUnitMapping (StdHeader) == EvenCoresMapping));
+
+  IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
+  //  Get data block from heap
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+  IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS));
+  // Current Core's socket, module must be present.
+  ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF);
+  // Process compute unit info
+  Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits;
+
+  while (Enabled > 0) {
+    if ((Enabled & 0x1) != 0) {
+      ComputeUnitCount++;
+    }
+    Enabled >>= 1;
+  }
+
+  return ComputeUnitCount;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provides the Total number of active cores in the given socket.
+ *
+ * @param[in]      Socket      Get a core count for the processor in this socket.
+ * @param[out]     CoreCount   Its core count
+ * @param[in]      StdHeader   Header for library and services.
+ *
+ * @retval     TRUE    A processor is present in the Socket and the CoreCount is valid.
+ * @retval     FALSE   The Socket does not have a Processor
+ */
+BOOLEAN
+GetActiveCoresInGivenSocket (
+  IN       UINT32             Socket,
+     OUT   UINT32             *CoreCount,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32 Module;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 ProcessorCoreCount;
+  BOOLEAN Result;
+
+  Result = FALSE;
+  ProcessorCoreCount = 0;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+      ProcessorCoreCount = ProcessorCoreCount + ((HighCore - LowCore) + 1);
+      Result = TRUE;
+    } else {
+      break;
+    }
+  }
+  *CoreCount = ProcessorCoreCount;
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provides the range of Cores in a Processor which are in a Module.
+ *
+ * Cores are named uniquely in a processor, 0 to TotalCores.  Any module in the processor has
+ * a set of those cores, named from LowCore to HighCore.
+ *
+ * @param[in]      Socket      Get a core range for the processor in this socket.
+ * @param[in]      Module      Get a core range for this Module in the processor.
+ * @param[out]     LowCore     The lowest Processor Core in the Module.
+ * @param[out]     HighCore    The highest Processor Core in the Module.
+ * @param[in]      StdHeader   Header for library and services.
+ *
+ * @retval     TRUE    A processor is present in the Socket and the Core Range is valid.
+ * @retval     FALSE   The Socket does not have a Processor
+ */
+BOOLEAN
+GetGivenModuleCoreRange (
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   UINT32            *LowCore,
+     OUT   UINT32            *HighCore,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+  AGESA_STATUS Status;
+
+  ASSERT (Socket < MAX_SOCKETS);
+  ASSERT (Module < MAX_DIES);
+  Result = FALSE;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
+  *LowCore = (*pSocketDieMap)[Socket][Module].LowCore;
+  *HighCore = (*pSocketDieMap)[Socket][Module].HighCore;
+  if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the current running core number.
+ *
+ * @param[out]     Core       The core id.
+ * @param[in]      StdHeader  Header for library and services.
+ *
+ */
+VOID
+GetCurrentCore (
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+  UINT32      LocalApicId;
+  UINT32      ApicIdCoreIdSize;
+  CORE_ID_POSITION      InitApicIdCpuIdLo;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  //  Read CPUID ebx[31:24] to get initial APICID
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader);
+  LocalApicId = (CpuidDataStruct.EBX_Reg & 0xFF000000) >> 24;
+
+  // Find the core ID size.
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader);
+  ApicIdCoreIdSize = (CpuidDataStruct.ECX_Reg & 0x0000F000) >> 12;
+
+  InitApicIdCpuIdLo = FamilyServices->CoreIdPositionInInitialApicId (FamilyServices, StdHeader);
+  ASSERT (InitApicIdCpuIdLo < CoreIdPositionMax);
+
+  // Now extract the core ID from the Apic ID by right justifying the id and masking off non-core Id bits.
+  *Core = ((LocalApicId >> ((1 - (UINT32)InitApicIdCpuIdLo) * (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))) &
+             (MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns current node, and core number.
+ *
+ * @param[out]     Node         The node id of the current core's node.
+ * @param[out]     Core         The core id if the current core.
+ * @param[in]      StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+GetCurrentNodeAndCore (
+     OUT   UINT32 *Node,
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  // Get Node Id
+  GetCurrentNodeNum (Node, StdHeader);
+
+  // Get Core Id
+  GetCurrentCore (Core, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Is the current core a primary core of it's node?
+ *
+ *  @param[in]  StdHeader   Config handle for library and services.
+ *
+ *  @retval        TRUE  Is Primary Core
+ *  @retval        FALSE Is not Primary Core
+ *
+ */
+BOOLEAN
+IsCurrentCorePrimary (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN Result;
+  UINT32 Core;
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 PrimaryCore;
+  UINT32 IgnoredCore;
+  AGESA_STATUS IgnoredSts;
+
+  Result = FALSE;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetGivenModuleCoreRange (Socket, Module, &PrimaryCore, &IgnoredCore, StdHeader);
+  if (Core == PrimaryCore) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns node id based on SocketId and ModuleId.
+ *
+ * @param[in]  SocketId       The socket to look up
+ * @param[in]  ModuleId       The module in that socket
+ * @param[out] NodeId         Provide the corresponding Node Id.
+ * @param[in]  StdHeader   Handle of Header for calling lib functions and services.
+ *
+ * @retval     TRUE       The socket is populated
+ * @retval     FALSE      The socket is not populated
+ *
+ */
+BOOLEAN
+GetNodeId (
+  IN       UINT32  SocketId,
+  IN       UINT32  ModuleId,
+     OUT   UINT8   *NodeId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+  AGESA_STATUS Status;
+
+  Result = FALSE;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
+  *NodeId = (*pSocketDieMap)[SocketId][ModuleId].Node;
+  if ((*pSocketDieMap)[SocketId][ModuleId].Node != 0xFF) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the cached AP Mailbox Info if available, or read the info from the hardware.
+ *
+ * Locate the known AP Mailbox Info Cache buffer in this core's local heap.  If it
+ * doesn't exist, read the hardware to get the info.
+ * This routine gets the main AP mailbox, not the system degree.
+ *
+ * @param[out]    ApMailboxInfo  Provide the info in this AP core's mailbox
+ * @param[in]     StdHeader      Config handle for library and services.
+ *
+ */
+VOID
+GetApMailbox (
+     OUT   UINT32               *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AGESA_STATUS     Ignored;
+  LOCATE_HEAP_PTR  LocalApMailboxCache;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+  AP_MAILBOXES     ApMailboxes;
+  BOOLEAN IamBsp;
+
+  IamBsp = IsBsp (StdHeader, &Ignored);
+  LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  if (((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || IamBsp) &&
+      (HeapLocateBuffer (&LocalApMailboxCache, StdHeader) == AGESA_SUCCESS)) {
+    // If during HEAP_LOCAL_CACHE stage, we always try to get ApMailbox from heap
+    // If we're not in HEAP_LOCAL_CACHE stage, only BSP can get ApMailbox from heap
+    *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info;
+  } else if (!IamBsp) {
+    // If this is an AP, the hardware register should be good.
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
+    *ApMailboxInfo = ApMailboxes.ApMailInfo.Info;
+  } else {
+    // This is the BSC.  The hardware mailbox has not been set up yet.
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Cache the Ap Mailbox info in our local heap for later use.
+ *
+ * This enables us to use the info even after the mailbox register is initialized
+ * with operational values.  Get all the AP mailboxes and keep them in one buffer.
+ *
+ * @param[in]     StdHeader   Config handle for library and services.
+ *
+ */
+VOID
+CacheApMailbox (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AP_MAILBOXES ApMailboxes;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  // Get mailbox from hardware.
+  FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
+
+  // Allocate heap for the info
+  AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES);
+  AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = ApMailboxes;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Compute the degree of the system.
+ *
+ * The degree of a system is the maximum degree of any node.  The degree of a node is the
+ * number of nodes to which it is directly connected (not considering width or redundant
+ * links).
+ *
+ * @param[in]     StdHeader            Config handle for library and services.
+ *
+ */
+UINTN
+GetSystemDegree (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_MAILBOXES *ApMailboxes;
+  LOCATE_HEAP_PTR  LocalApMailboxCache;
+  AGESA_STATUS Status;
+
+  //  Get data block from heap
+  LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  Status = HeapLocateBuffer (&LocalApMailboxCache, StdHeader);
+  // non-Success handled by ASSERT not NULL below.
+  ApMailboxes = (AP_MAILBOXES *)LocalApMailboxCache.BufferPtr;
+  ASSERT ((ApMailboxes != NULL) && (Status == AGESA_SUCCESS));
+  return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Spins until the number of microseconds specified have
+ *  expired regardless of CPU operational frequency.
+ *
+ *  @param[in]   Microseconds  Wait time in microseconds
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+WaitMicroseconds (
+  IN       UINT32 Microseconds,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 TscRateInMhz;
+  UINT64 NumberOfTicks;
+  UINT64 InitialTsc;
+  UINT64 CurrentTsc;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  LibAmdMsrRead (TSC, &InitialTsc, StdHeader);
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
+  NumberOfTicks = Microseconds * TscRateInMhz;
+  do {
+    LibAmdMsrRead (TSC, &CurrentTsc, StdHeader);
+  } while ((CurrentTsc - InitialTsc) < NumberOfTicks);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ *
+ *  @param[in,out]   StdHeader        Header for library and services
+ *  @param[out]      AgesaStatus      Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  UINT64 MsrData;
+
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  //  Read APIC_BASE register (0x1B), bit[8] returns 1 for BSP
+  LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader);
+  if ((MsrData & BIT8) != 0 ) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the compute unit mapping algorithm.
+ *
+ * Look up the compute unit values for the current core's socket/module and find the matching
+ * core pair map item.  This will tell us how to determine the core's status.
+ *
+ * @param[in]   StdHeader        Header for library and services
+ *
+ * @retval      AllCoresMapping  Each core is in a compute unit of its own.
+ * @retval      EvenCoresMapping Even/Odd pairs of cores are in each compute unit.
+ */
+COMPUTE_UNIT_MAPPING
+GetComputeUnitMapping (
+  IN      AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT32  CurrentCore;
+  UINT32  Module;
+  UINT32  Socket;
+  UINT8   Enabled;
+  UINT8   DualCore;
+  AGESA_STATUS  IgnoredSts;
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+  CORE_PAIR_MAP *CorePairMap;
+  COMPUTE_UNIT_MAPPING Result;
+
+  // Invalid mapping, unless we find one.
+  Result = MaxComputeUnitMapping;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  //  Get data block from heap
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+  IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS));
+  // Current Core's socket, module must be present.
+  ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF);
+
+  // Process compute unit info
+  Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits;
+  DualCore = (*pSocketDieMap)[Socket][Module].DualCoreComputeUnits;
+  CorePairMap = FamilyServices->CorePairMap;
+  if ((Enabled != 0) && (CorePairMap != NULL)) {
+    while (CorePairMap->Enabled != 0xFF) {
+      if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) {
+        break;
+      }
+      CorePairMap++;
+    }
+    // The assert is for finding a processor configured in a way the core pair map doesn't support.
+    ASSERT (CorePairMap->Enabled != 0xFF);
+    Result = CorePairMap->Mapping;
+  } else {
+    // Families that don't have compute units act as though each core is in its own compute unit
+    // and all cores are primary
+    Result = AllCoresMapping;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is current core the primary core of its compute unit?
+ *
+ * Get the mapping algorithm and the current core number.  Selecting First/Last ordering for
+ * primary @b ASSUMES cores are launched in ascending core number order.
+ *
+ * @param[in]   Selector         Select whether first or last core has the primary core role.
+ * @param[in]   StdHeader        Header for library and services
+ *
+ * @retval       TRUE             This is the primary core of a compute unit.
+ * @retval       FALSE            This is the second shared core of a compute unit.
+ *
+ */
+BOOLEAN
+IsCorePairPrimary (
+  IN       COMPUTE_UNIT_PRIMARY_SELECTOR Selector,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  BOOLEAN Result;
+  UINT32  CurrentCore;
+  UINT32  Module;
+  UINT32  Socket;
+  AGESA_STATUS  IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
+
+  Result = FALSE;
+  switch (GetComputeUnitMapping (StdHeader)) {
+  case AllCoresMapping:
+    // All cores are primaries
+    Result = TRUE;
+    break;
+  case EvenCoresMapping:
+    // Even core numbers are first to execute, odd cores are last to execute
+    if (Selector == FirstCoreIsComputeUnitPrimary) {
+      Result = (BOOLEAN) ((CurrentCore & 1) == 0);
+    } else {
+      Result = (BOOLEAN) ((CurrentCore & 1) != 0);
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Are the two specified cores shared in a compute unit?
+ *
+ * Look up the compute unit values for the current core's socket/module and find the matching
+ * core pair map item.  This will tell us how to determine the core's status.
+ *
+ * @param[in]   Socket           The processor in this socket is to be checked
+ * @param[in]   Module           The processor in this module is to be checked
+ * @param[in]   CoreA            One of the two cores to check
+ * @param[in]   CoreB            The other core to be checked
+ * @param[in]   StdHeader        Header for library and services
+ *
+ * @retval       TRUE            The cores are in the same compute unit.
+ * @retval       FALSE           The cores are not in the same compute unit, or the processor does
+ *                               not have compute units.
+ *
+ */
+BOOLEAN
+AreCoresPaired (
+  IN       UINT32  Socket,
+  IN       UINT32  Module,
+  IN       UINT32  CoreA,
+  IN       UINT32  CoreB,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN Result;
+
+  Result = FALSE;
+  switch (GetComputeUnitMapping (StdHeader)) {
+  case AllCoresMapping:
+    // No cores are sharing a compute unit
+    Result = FALSE;
+    break;
+  case EvenCoresMapping:
+    // Even core numbers are paired with odd core numbers, n with n + 1
+    if ((CoreA & 1) == 0) {
+      Result = (BOOLEAN) (CoreA == (CoreB - 1));
+    } else {
+      Result = (BOOLEAN) (CoreA == (CoreB + 1));
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ *
+ * @param[in]      StdHeader               Pointer to structure containing the function call
+ *                                         whose parameter structure is to be created, the
+ *                                         allocation method, and a pointer to the newly
+ *                                         created structure.
+ *
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8        EncodedSize;
+  UINT64       LocalMsrRegister;
+
+  // Make sure that Standard header is valid
+  ASSERT (StdHeader != NULL);
+
+  if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) {
+    EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize);
+    LocalMsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2));
+    LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c
new file mode 100644
index 0000000000..c832be43f9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c
@@ -0,0 +1,151 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize the 'common' way of running early initialization.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUINITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetCommonEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
+
+CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
+{
+  {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {NULL, 0}
+};
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
+ * processor that uses the standard initialization steps should take.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetCommonEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  *Table = CommonEarlyInitOnCoreTable;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c
new file mode 100644
index 0000000000..a9a5631ef8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c
@@ -0,0 +1,420 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Late Init API
+ *
+ * Contains code for doing any late CPU initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_CPULATEINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+DisableCf8ExtCfg (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the late entry point
+ *
+ * This function should be the last function run by the AGESA
+ * CPU module and prepares the processor for the operating system
+ * bootstrap load process.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  PlatformConfig    Contains the runtime modifiable feature input data.
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+AmdCpuLate (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  )
+{
+  AP_EXE_PARAMS ApParams;
+
+  if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode != HARDWARE_PREFETCHER_AUTO) ||
+      (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode != SOFTWARE_PREFETCHES_AUTO)) {
+    ApParams.StdHeader = *StdHeader;
+    ApParams.FunctionNumber = AP_LATE_TASK_CPU_LATE_INIT;
+    ApParams.RelatedDataBlock = (VOID *) PlatformConfig;
+    ApParams.RelatedBlockLength = sizeof (PLATFORM_CONFIGURATION);
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+    CpuLateInitApTask (&ApParams);
+  }
+  DisableCf8ExtCfg (StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CpuLateInitApTask
+ *
+ *  Description:
+ *    This is the last function run on all APs
+ *
+ *  Parameters:
+ *    @param[in] ApExeParams   Handle to config for library and services.
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *  Processing:
+ *
+ */
+AGESA_STATUS
+CpuLateInitApTask (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT64   LocalMsrRegister;
+  PLATFORM_CONFIGURATION *PlatformConfig;
+  BOOLEAN  CuCfg3Exist;
+
+  PlatformConfig = (PLATFORM_CONFIGURATION *) ApExeParams->RelatedDataBlock;
+  // The processor that has compute unit has CU_CFG3 MSR
+  switch (GetComputeUnitMapping (&(ApExeParams->StdHeader))) {
+  case AllCoresMapping:
+    CuCfg3Exist = FALSE;
+    break;
+  case EvenCoresMapping:
+    CuCfg3Exist = TRUE;
+    break;
+  default:
+    CuCfg3Exist = FALSE;
+  }
+
+  // DISABLE_HARDWARE_PREFETCH
+  if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HARDWARE_PREFETCH) {
+    // DC_CFG (MSR_C001_1022)
+    //  [13] = 1
+    //  [15] = 1
+    LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader));
+    LocalMsrRegister |= (BIT13 | BIT15);
+    LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader));
+    // CU_CFG3 (MSR_C001_102B)
+    //  [3]  = 1
+    //  [16] = 1
+    //  [17] = 1
+    //  [18] = 1
+    if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) {
+      LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader));
+      LocalMsrRegister |= (BIT3 | BIT16 | BIT17 | BIT18);
+      LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader));
+    }
+  }
+
+  // DISABLE_L1_PREFETCHER
+  if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER) ||
+             (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) {
+    // CU_CFG3 (MSR_C001_102B)
+    //  [3] = 1
+    if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) {
+      LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader));
+      LocalMsrRegister |= BIT3;
+      LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader));
+    }
+
+  }
+
+  // DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES
+  if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES ) ||
+             (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) {
+    // DC_CFG (MSR_C001_1022)
+    //  [15] = 1
+    LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader));
+    LocalMsrRegister |= BIT15;
+    LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader));
+
+  }
+
+  // DISABLE_SOFTWARE_PREFETCHES
+  if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode == DISABLE_SOFTWARE_PREFETCHES) {
+    // MSR_DE_CFG (MSR_C001_1029)
+    //  [7:2] = 0x3F
+    if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader))) {
+      LibAmdMsrRead (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader));
+      LocalMsrRegister |= 0xFC;
+      LibAmdMsrWrite (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader));
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Clear EnableCf8ExtCfg on all socket
+ *
+ * Clear F3x8C bit 14 EnableCf8ExtCfg
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *
+ */
+VOID
+DisableCf8ExtCfg (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  PCI_ADDR PciAddress;
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 PciData;
+  UINT32 LegacyPciAccess;
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+        PciAddress.Address.Function = FUNC_3;
+        PciAddress.Address.Register = NB_CFG_HIGH_REG;
+        LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
+        // read from PCI register
+        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+        LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader);
+        // Disable Cf8ExtCfg
+        PciData &= 0xFFFFBFFF;
+        // write to PCI register
+        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+        LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader);
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate an ACPI style checksum
+ *
+ * Computes the checksum and stores the value to the checksum
+ * field of the passed in ACPI table's header.
+ *
+ * @param[in]  Table             ACPI table to checksum
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+ChecksumAcpiTable (
+  IN OUT   ACPI_TABLE_HEADER *Table,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  *BuffTempPtr;
+  UINT8  Checksum;
+  UINT32 BufferOffset;
+
+  Table->Checksum = 0;
+  Checksum = 0;
+  BuffTempPtr = (UINT8 *) Table;
+  for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) {
+    Checksum = Checksum - *(BuffTempPtr + BufferOffset);
+  }
+
+  Table->Checksum = Checksum;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Run code on every AP in the system.
+ *
+ * @param[in] ApParams       AP task pointer.
+ * @param[in] StdHeader      Handle to config for library and services
+ *
+ * @return    The most severe AGESA_STATUS returned by an AP.
+ *
+ */
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  UINT8                   Socket;
+  UINT8                   Core;
+  UINT8                   ApicId;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCoreNum;
+  AGESA_STATUS            CalledStatus;
+  AGESA_STATUS            IgnoredStatus;
+  AGESA_STATUS            AgesaStatus;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredStatus));
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+          GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);
+          AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);
+          CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
+          AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader);
+          if (CalledStatus > AgesaStatus) {
+            AgesaStatus = CalledStatus;
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Run code on core 0 of every socket in the system.
+ *
+ * @param[in] ApParams       AP task pointer.
+ * @param[in] StdHeader      Handle to config for library and services
+ *
+ * @return    The most severe AGESA_STATUS returned by an AP.
+ *
+ */
+AGESA_STATUS
+RunLateApTaskOnAllCore0s (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                  NumberOfSockets;
+  UINT8                   Socket;
+  UINT8                   ApicId;
+  UINT32                  BscSocket;
+  UINT32                  IgnoredModule;
+  UINT32                  IgnoredCore;
+  AGESA_STATUS            CalledStatus;
+  AGESA_STATUS            IgnoredStatus;
+  AGESA_STATUS            AgesaStatus;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredStatus));
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      if (Socket != BscSocket) {
+        GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus);
+        AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader);
+        CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
+        AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader);
+        if (CalledStatus > AgesaStatus) {
+          AgesaStatus = CalledStatus;
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
new file mode 100644
index 0000000000..59d396d0df
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
@@ -0,0 +1,1160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Late Init API functions Prototypes.
+ *
+ * Contains code for doing any late CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 64351 $   @e \$Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_LATE_INIT_H_
+#define _CPU_LATE_INIT_H_
+
+#include "Filecode.h"
+
+//  Forward declaration needed for multi-structure mutual references.
+AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+CpuLateInitApTask (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+#define AP_LATE_TASK_CPU_LATE_INIT (PROC_CPU_CPULATEINIT_FILECODE)
+#define CPU_LATE_INIT_AP_TASK {AP_LATE_TASK_CPU_LATE_INIT, (IMAGE_ENTRY) CpuLateInitApTask},
+
+//----------------------------------------------------------------------------
+//                         DMI DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
+// SMBIOS constant definition
+#define CENTRAL_PROCESSOR       0x03
+#define EXTERNAL_CLOCK_DFLT     200
+#define EXTERNAL_CLOCK_100MHZ   100
+#define P_FAMILY_UNKNOWN        0x02
+#define P_ENGINEERING_SAMPLE    0x00
+#define P_CHARACTERISTICS       0x4
+#define CACHE_CFG_L1            0x180
+#define CACHE_CFG_L2            0x181
+#define CACHE_CFG_L3            0x182
+#define SRAM_TYPE               0x10
+#define ERR_CORRECT_TYPE        0x06
+#define CACHE_TYPE              0x05
+#define DMI_ASSOCIATIVE_OTHER   0x01
+#define DMI_ASSOCIATIVE_UNKNOWN 0x02
+#define DMI_ASSOCIATIVE_DIRECT_MAPPED   0x03
+#define DMI_ASSOCIATIVE_2_WAY   0x04
+#define DMI_ASSOCIATIVE_4_WAY   0x05
+#define DMI_ASSOCIATIVE_FULLY   0x06
+#define DMI_ASSOCIATIVE_8_WAY   0x07
+#define DMI_ASSOCIATIVE_16_WAY  0x08
+#define DMI_ASSOCIATIVE_12_WAY  0x09
+#define DMI_ASSOCIATIVE_24_WAY  0x0A
+#define DMI_ASSOCIATIVE_32_WAY  0x0B
+#define DMI_ASSOCIATIVE_48_WAY  0x0C
+#define DMI_ASSOCIATIVE_64_WAY  0x0D
+#define DMI_ASSOCIATIVE_20_WAY  0x0E
+#define SOCKET_POPULATED        0x40
+#define CPU_STATUS_UNKNOWN      0x00
+#define CPU_STATUS_ENABLED      0x01
+
+// Processor Upgrade Definition
+#define P_UPGRADE_UNKNOWN       0x02
+#define P_UPGRADE_NONE          0x06
+#define P_UPGRADE_S1GX          0x16
+#define P_UPGRADE_AM2           0x17
+#define P_UPGRADE_F1207         0x18
+#define P_UPGRADE_G34           0x1A
+#define P_UPGRADE_AM3           0x1B
+#define P_UPGRADE_C32           0x1C
+#define P_UPGRADE_FS1           0x27
+#define P_UPGRADE_FM1           0x29
+#define P_UPGRADE_FM2           0x2A
+
+//----------------------------------------------------------------------------
+//                         SRAT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define NorthbridgeCapabilities 0xE8
+#define DRAMBase0 0x40
+#define MMIOBase0 0x80
+#define TOP_MEM 0xC001001Aul
+#define LOW_NODE_DEVICEID 24
+#define LOW_APICID 0
+
+
+// Miscellaneous AMD related values
+#define MAX_NUMBER_NODES  8
+
+// Flags
+#define ENABLED         1   // Bit 0
+#define DISABLED        0   // Bit 0
+#define HOTPLUGGABLE    2   // Bit 1
+
+// Affinity Entry Structures
+#define AE_APIC     0
+#define AE_MEMORY   1
+
+
+// Memory Types
+#define TYPE_MEMORY   1
+#define TYPE_RESERVED 2
+#define TYPE_ACPI     3
+#define TYPE_NVS      4
+
+//----------------------------------------------------------------------------
+//                         SLIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define PROBE_FILTER_CTRL_REG             0x1D4
+#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH   8
+
+//----------------------------------------------------------------------------
+//                         CDIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH   4 // Num domains is a 4-bytes unsigned integer
+
+
+//----------------------------------------------------------------------------
+//                         P-STATE DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+//-------------------------------------
+//          ERROR Codes
+//-------------------------------------
+#define     NO_ERROR                    0x0
+#define     USER_DISABLE_ERROR          0x01            // User disabled SSDT generation
+#define     CORES_MISSMATCH_PSS_ERROR   0x02            // No PSS match
+#define     PNOW_SUPPORT_ERROR          0x04            // One of the Cores do not support PNOW!
+#define     PWR_FREQ_MATCH_ERROR        0x08            // FREQ and PWR mismatch
+#define     NO_PSS_SIZE_ERROR           0x10            // Error in PSS Size
+#define     INVALID_PSTATE_ERROR        0x20            // Invalid Max or only 1 P-State available
+#define     NO_PSS_ENTRY                0x0FFFFul
+#define     INVALID_FREQ                0x0FFFFFFFFul
+
+//-------------------------
+// Default definitions
+// AMD BKDG default values
+//-------------------------
+#define DEFAULT_ISOCH_RELIEF_TIME       IRT_80uS
+#define DEFAULT_RAMP_VOLTAGE_OFFSET     RVO_50mV
+#define DEFAULT_MAX_VOLTAGE_STEP        MVS_25mV
+#define DEFAULT_PERF_PRESENT_CAP        0           // default for Desktop
+#define DEFAULT_VOLTAGE_STABLE_TIME     (100 / 20)  // 100uS
+#define DEFAULT_PLL_LOCK_TIME           2           // 2uS
+#define DEFAULT_TRANSITION_LATENCY      100         // 100uS
+#define DEFAULT_BUS_MASTER_LATENCY      9           // 9uS
+#define DEFAULT_CPU_SCOPE_NUMBER        "0UPC"
+
+// Defines for Common ACPI
+// -----------------------------
+#define     SCOPE_OPCODE            0x10
+#define     NAME_OPCODE             0x08
+#define     METHOD_OPCODE           0x14
+#define     PACKAGE_OPCODE          0x12
+#define     BUFFER_OPCODE           0x11
+#define     BYTE_PREFIX_OPCODE      0x0A
+#define     WORD_PREFIX_OPCODE      0x0B
+#define     DWORD_PREFIX_OPCODE     0x0C
+#define     RETURN_OPCODE           0xA4
+#define     ACPI_BUFFER             0x080A0B11ul
+
+// Generic Register Descriptor (GDR) Fields
+#define     GDR_ASI_SYSTEM_IO       0x01    // Address Space ID
+#define     GDR_ASZ_BYTE_ACCESS     0x01    // Address Size
+
+// Defines for ACPI Scope Table
+// ----------------------------
+#define     SCOPE_LENGTH    (SCOPE_STRUCT_SIZE + \
+                            PCT_STRUCT_SIZE + \
+                            PSS_HEADER_STRUCT_SIZE + \
+                            PSS_BODY_STRUCT_SIZE + \
+                            PPC_HEADER_BODY_STRUCT_SIZE)
+#define     SCOPE_VALUE1    0x5C
+#define     SCOPE_VALUE2    0x2E
+#define     SCOPE_NAME__    '_'
+#define     SCOPE_NAME_P    'P'
+#define     SCOPE_NAME_R    'R'
+#define     SCOPE_NAME_S    'S'
+#define     SCOPE_NAME_B    'B'
+#define     SCOPE_NAME_C    'C'
+#define     SCOPE_NAME_U    'U'
+#define     SCOPE_NAME_0    '0'
+#define     SCOPE_NAME_1    '1'
+#define     SCOPE_NAME_2    '2'
+#define     SCOPE_NAME_3    '3'
+#define     SCOPE_NAME_A    'A'
+
+#ifdef OEM_SCOPE_NAME
+  #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
+    #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
+  #endif
+  #define     SCOPE_NAME_VALUE    OEM_SCOPE_NAME
+#else
+  #define     SCOPE_NAME_VALUE    SCOPE_NAME_C
+#endif  // OEM_SCOPE_NAME
+
+#ifdef OEM_SCOPE_NAME1
+  #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
+         ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
+         (OEM_SCOPE_NAME1 == '_')))
+    #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
+  #endif
+  #define     SCOPE_NAME_VALUE1   OEM_SCOPE_NAME1
+#else
+  #define     SCOPE_NAME_VALUE1   SCOPE_NAME_0
+#endif  // OEM_SCOPE_NAME
+
+// Defines for PCT Control and Status Table
+// ----------------------------------------
+#define     PCT_NAME__                  '_'
+#define     PCT_NAME_P                  'P'
+#define     PCT_NAME_C                  'C'
+#define     PCT_NAME_T                  'T'
+#define     PCT_VALUE1                  0x11022C12ul
+#define     PCT_VALUE2                  0x0A14
+#define     PCT_VALUE3                  0x11
+#define     GENERIC_REG_DESCRIPTION     0x82
+#define     PCT_LENGTH                  0x0C
+#define     PCT_ADDRESS_SPACE_ID        0x7F
+#define     PCT_REGISTER_BIT_WIDTH      0x40
+#define     PCT_REGISTER_BIT_OFFSET     0x00
+#define     PCT_RESERVED                0x00
+#define     PCT_CONTROL_REG_LO          0xC0010062ul
+#define     PCT_CONTROL_REG_HI          0x00
+#define     PCT_VALUE4                  0x14110079ul
+#define     PCT_VALUE5                  0x110A
+#define     PCT_STATUS_REG_LO           0x00
+#define     PCT_STATUS_REG_HI           0x00
+#define     PCT_VALUE6                  0x0079
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define     PSS_NAME__          '_'
+#define     PSS_NAME_X          'X'
+#define     PSS_NAME_P          'P'
+#define     PSS_NAME_S          'S'
+#define     PSS_LENGTH          (sizeof pssBodyStruct + 3)
+#define     NUM_OF_ITEMS_IN_PSS 0x00
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define     PSS_PKG_LENGTH              0x20  // PSS_BODY_STRUCT_SIZE - 1
+#define     PSS_NUM_OF_ELEMENTS         0x06
+#define     PSS_FREQUENCY               0x00
+#define     PSS_POWER                   0x00
+#define     PSS_TRANSITION_LATENCY      DEFAULT_TRANSITION_LATENCY
+#define     PSS_BUS_MASTER_LATENCY      DEFAULT_BUS_MASTER_LATENCY
+#define     PSS_CONTROL                 ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
+                                         (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
+                                         (DEFAULT_EXT_TYPE << 27) + \
+                                         (DEFAULT_PLL_LOCK_TIME << 20) + \
+                                         (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
+                                         (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
+                                         (PSS_VID << 6) + PSS_FID)
+#define     PSS_STATUS                  (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
+
+// Defines for XPSS Header Table
+// ----------------------------
+#define     XPSS_PKG_LENGTH             0x47  // XPSS_BODY_STRUCT_SIZE - 1
+#define     XPSS_NUM_OF_ELEMENTS        0x08
+#define     XPSS_ACPI_BUFFER            0x080A0B11ul
+
+
+// Defines for PPC Header Table
+// ----------------------------
+#define     PPC_NAME__  '_'
+#define     PPC_NAME_P  'P'
+#define     PPC_NAME_C  'C'
+#define     PPC_NAME_V  'V'
+#define     PPC_METHOD_FLAGS  0x00;
+#define     PPC_VALUE1  0x0A;
+
+// Defines for PSD Header Table
+// ----------------------------
+#define     PSD_NAME__          '_'
+#define     PSD_NAME_P          'P'
+#define     PSD_NAME_S          'S'
+#define     PSD_NAME_D          'D'
+#define     PSD_HEADER_LENGTH   (PSD_BODY_STRUCT_SIZE + 2)
+#define     PSD_VALUE1          0x01
+
+
+// Defines for PSD Header Table
+// ----------------------------
+#define     PSD_PKG_LENGTH          (PSD_BODY_STRUCT_SIZE - 1)
+#define     NUM_OF_ENTRIES          0x05
+#define     PSD_NUM_OF_ENTRIES      0x05
+#define     PSD_REVISION            0x00
+#define     PSD_DEPENDENCY_DOMAIN   0x00
+#define     PSD_COORDINATION_TYPE_HW_ALL   0xFE
+#define     PSD_COORDINATION_TYPE_SW_ANY   0xFD
+#define     PSD_COORDINATION_TYPE_SW_ALL   0xFC
+#define     PSD_NUM_OF_PROCESSORS   0x01
+#define     PSD_CORE_NUM_PER_COMPUTE_UNIT    0x02
+#define     PSD_DOMAIN_COMPUTE_UNIT_MASK   0x7F
+
+
+#define     CUSTOM_PSTATE_FLAG      0x55
+#define     PSTATE_FLAG_1           0x55
+#define     TARGET_PSTATE_FLAG      0xAA
+#define     PSTATE_FLAG_2           0xAA
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+//--------------------------------------------
+//              AML code definition
+//                   (Scope)
+//---------------------------------------------
+/// SCOPE
+typedef struct _SCOPE {
+  UINT8   ScopeOpcode;                  ///< Opcode
+  UINT16  ScopeLength;                  ///< Scope Length
+  UINT8   ScopeValue1;                  ///< Value1
+  UINT8   ScopeValue2;                  ///< Value2
+  UINT8   ScopeNamePt1a__;              ///< Name Pointer
+  UINT8   ScopeNamePt1a_P;              ///< Name Pointer
+  UINT8   ScopeNamePt1a_R;              ///< Name Pointer
+  UINT8   ScopeNamePt1b__;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_C;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_P;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_U;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_0;              ///< Name Pointer
+} SCOPE;
+#define     SCOPE_STRUCT_SIZE   13      // 13 Bytes
+
+//--------------------------------------------
+//              AML code definition
+//             (PCT Header and Body)
+//---------------------------------------------
+
+///Performance Control Header
+typedef struct _PCT_HEADER_BODY {
+  UINT8   NameOpcode;                   ///< Opcode
+  UINT8   PctName_a__;                  ///< String "_"
+  UINT8   PctName_a_P;                  ///< String "P"
+  UINT8   PctName_a_C;                  ///< String "C"
+  UINT8   PctName_a_T;                  ///< String "T"
+  UINT32  Value1;                       ///< Value1
+  UINT16  Value2;                       ///< Value2
+  UINT8   Value3;                       ///< Value3
+  UINT8   GenericRegDescription1;       ///< Generic Reg Description
+  UINT16  Length1;                      ///< Length1
+  UINT8   AddressSpaceId1;              ///< PCT Address Space ID
+  UINT8   RegisterBitWidth1;            ///< PCT Register Bit Width
+  UINT8   RegisterBitOffset1;           ///< PCT Register Bit Offset
+  UINT8   Reserved1;                    ///< Reserved
+  UINT32  ControlRegAddressLo;          ///< Control Register Address Low
+  UINT32  ControlRegAddressHi;          ///< Control Register Address High
+  UINT32  Value4;                       ///< Value4
+  UINT16  Value5;                       ///< Value 5
+  UINT8   GenericRegDescription2;       ///< Generic Reg Description
+  UINT16  Length2;                      ///< Length2
+  UINT8   AddressSpaceId2;              ///< PCT Address Space ID
+  UINT8   RegisterBitWidth2;            ///< PCT Register Bit Width
+  UINT8   RegisterBitOffset2;           ///< PCT Register Bit Offset
+  UINT8   Reserved2;                    ///< Reserved
+  UINT32  StatusRegAddressLo;           ///< Control Register Address Low
+  UINT32  StatusRegAddressHi;           ///< Control Register Address High
+  UINT16  Value6;                       ///< Values
+} PCT_HEADER_BODY;
+#define     PCT_STRUCT_SIZE     50      // 50 Bytes
+
+
+//--------------------------------------------
+//              AML code definition
+//                 (PSS Header)
+//--------------------------------------------
+///Performance Supported States Header
+typedef struct  _PSS_HEADER {
+  UINT8   NameOpcode;                   ///< Opcode
+  UINT8   PssName_a__;                  ///< String "_"
+  UINT8   PssName_a_P;                  ///< String "P"
+  UINT8   PssName_a_S;                  ///< String "S"
+  UINT8   PssName_b_S;                  ///< String "S"
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT16  PssLength;                    ///< PSS Length
+  UINT8   NumOfItemsInPss;              ///< Number of Items in PSS
+} PSS_HEADER;
+#define     PSS_HEADER_STRUCT_SIZE  9   // 9 Bytes
+
+
+//--------------------------------------------
+//              AML code definition
+//                 (PSS Body)
+//--------------------------------------------
+///Performance Supported States Body
+typedef struct _PSS_BODY {
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT8   PkgLength;                    ///< Package Length
+  UINT8   NumOfElements;                ///< Number of Elements
+  UINT8   DwordPrefixOpcode1;           ///< Prefix Opcode1
+  UINT32  Frequency;                    ///< Frequency
+  UINT8   DwordPrefixOpcode2;           ///< Prefix Opcode2
+  UINT32  Power;                        ///< Power
+  UINT8   DwordPrefixOpcode3;           ///< Prefix Opcode3
+  UINT32  TransitionLatency;            ///< Transition Latency
+  UINT8   DwordPrefixOpcode4;           ///< Prefix Opcode4
+  UINT32  BusMasterLatency;             ///< Bus Master Latency
+  UINT8   DwordPrefixOpcode5;           ///< Prefix Opcode5
+  UINT32  Control;                      ///< Control
+  UINT8   DwordPrefixOpcode6;           ///< Prefix Opcode6
+  UINT32  Status;                       ///< Status
+} PSS_BODY;
+#define     PSS_BODY_STRUCT_SIZE    33  // 33 Bytes
+
+
+/*--------------------------------------------
+ *              AML code definition
+ *                 (XPSS Header)
+ *--------------------------------------------
+ */
+/// Extended PSS Header
+typedef struct  _XPSS_HEADER {
+  UINT8   NameOpcode;                   ///< 08h
+  UINT8   XpssName_a_X;                 ///< String "X"
+  UINT8   XpssName_a_P;                 ///< String "P"
+  UINT8   XpssName_a_S;                 ///< String "S"
+  UINT8   XpssName_b_S;                 ///< String "S"
+  UINT8   PkgOpcode;                    ///< 12h
+  UINT16  XpssLength;                   ///< XPSS Length
+  UINT8   NumOfItemsInXpss;             ///< Number of Items in XPSS
+} XPSS_HEADER;
+#define     XPSS_HEADER_STRUCT_SIZE  9  // 9 Bytes
+
+/*--------------------------------------------
+ *              AML code definition
+ *                 (XPSS Body)
+ *--------------------------------------------
+ */
+/// Extended PSS Body
+typedef struct  _XPSS_BODY {
+  UINT8   PkgOpcode;                    ///< 12h
+  UINT8   PkgLength;                    ///< Package Length
+  UINT8   XpssValueTbd;                 ///< XPSS Value
+  UINT8   NumOfElements;                ///< Number of Elements
+  UINT8   DwordPrefixOpcode1;           ///< Prefix Opcode1
+  UINT32  Frequency;                    ///< Frequency
+  UINT8   DwordPrefixOpcode2;           ///< Prefix Opcode2
+  UINT32  Power;                        ///< Power
+  UINT8   DwordPrefixOpcode3;           ///< Prefix Opcode3
+  UINT32  TransitionLatency;            ///< Transition Latency
+  UINT8   DwordPrefixOpcode4;           ///< Prefix Opcode4
+  UINT32  BusMasterLatency;             ///< Bus Master Latency
+  UINT32  ControlBuffer;                ///< Control Buffer
+  UINT32  ControlLo;                    ///< Control Low
+  UINT32  ControlHi;                    ///< Control High
+  UINT32  StatusBuffer;                 ///< Status Buffer
+  UINT32  StatusLo;                     ///< Status Low
+  UINT32  StatusHi;                     ///< Status High
+  UINT32  ControlMaskBuffer;            ///< Control Mask Buffer
+  UINT32  ControlMaskLo;                ///< Control Mask Low
+  UINT32  ControlMaskHi;                ///< Control Mask High
+  UINT32  StatusMaskBuffer;             ///< Status Mask Buffer
+  UINT32  StatusMaskLo;                 ///< Status Mask Low
+  UINT32  StatusMaskHi;                 ///< Status Mask High
+} XPSS_BODY;
+#define     XPSS_BODY_STRUCT_SIZE    72 // 72 Bytes
+
+/*--------------------------------------------
+ *              AML code definition
+ *             (PPC Header and Body)
+ *--------------------------------------------
+ */
+/// Performance Present Capabilities Header
+typedef struct _PPC_HEADER_BODY {
+  UINT8   NameOpcode;                   ///< Name Opcode
+  UINT8   PpcName_a_P;                  ///< String "P"
+  UINT8   PpcName_b_P;                  ///< String "P"
+  UINT8   PpcName_a_C;                  ///< String "C"
+  UINT8   PpcName_a_V;                  ///< String "V"
+  UINT8   Value1;                       ///< Value
+  UINT8   DefaultPerfPresentCap;        ///< Default Perf Present Cap
+  UINT8   MethodOpcode;                 ///< Method Opcode
+  UINT8   PpcLength;                    ///< Method Length
+  UINT8   PpcName_a__;                  ///< String "_"
+  UINT8   PpcName_c_P;                  ///< String "P"
+  UINT8   PpcName_d_P;                  ///< String "P"
+  UINT8   PpcName_b_C;                  ///< String "C"
+  UINT8   MethodFlags;                  ///< Method Flags
+  UINT8   ReturnOpcode;                 ///< Return Opcoce
+  UINT8   PpcName_e_P;                  ///< String "P"
+  UINT8   PpcName_f_P;                  ///< String "P"
+  UINT8   PpcName_c_C;                  ///< String "C"
+  UINT8   PpcName_b_V;                  ///< String "V"
+
+} PPC_HEADER_BODY;
+#define     PPC_HEADER_BODY_STRUCT_SIZE     19 // 19 Bytes
+#define     PPC_METHOD_LENGTH               11 // 11 Bytes
+
+
+/*--------------------------------------------
+ *              AML code definition
+ *                (PSD Header)
+ *--------------------------------------------
+ */
+/// P-State Dependency Header
+typedef struct  _PSD_HEADER {
+  UINT8   NameOpcode;                   ///< Name Opcode
+  UINT8   PsdName_a__;                  ///< String "_"
+  UINT8   PsdName_a_P;                  ///< String "P"
+  UINT8   PsdName_a_S;                  ///< String "S"
+  UINT8   PsdName_a_D;                  ///< String "D"
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT8   PsdLength;                    ///< PSD Length
+  UINT8   Value1;                       ///< Value
+} PSD_HEADER;
+#define     PSD_HEADER_STRUCT_SIZE  8   // 8 Bytes
+
+/*--------------------------------------------
+ *              AML code definition
+ *                 (PSD Body)
+ *--------------------------------------------
+ */
+/// P-State Dependency Body
+typedef struct _PSD_BODY {
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT8   PkgLength;                    ///< Package Length
+  UINT8   NumOfEntries;                 ///< Number of Entries
+  UINT8   BytePrefixOpcode1;            ///< Prefix Opcode1 in Byte
+  UINT8   PsdNumOfEntries;              ///< PSD Number of Entries
+  UINT8   BytePrefixOpcode2;            ///< Prefix Opcode2 in Byte
+  UINT8   PsdRevision;                  ///< PSD Revision
+  UINT8   DwordPrefixOpcode1;           ///< Prefix Opcode1 in DWord
+  UINT32  DependencyDomain;             ///< Dependency Domain
+  UINT8   DwordPrefixOpcode2;           ///< Prefix Opcode2 in DWord
+  UINT32  CoordinationType;             ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
+  UINT8   DwordPrefixOpcode3;           ///< Prefix Opcode3 in DWord
+  UINT32  NumOfProcessors;              ///< Number of Processors
+} PSD_BODY;
+#define     PSD_BODY_STRUCT_SIZE    22  // 22 Bytes
+
+//----------------------------------------------------------------------------
+//                         WHEA TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// HEST MCE TABLE
+typedef struct _AMD_HEST_MCE_TABLE {
+  UINT16 TblLength;               ///< Length, in bytes, of entire AMD_HEST_MCE structure.
+  UINT32 GlobCapInitDataLSD;      ///< Holds the value that the OS will program into
+  UINT32 GlobCapInitDataMSD;      ///< the machine check global capability register(MCG_CAP).
+  UINT32 GlobCtrlInitDataLSD;     ///< Holds the value that the OS will program into
+  UINT32 GlobCtrlInitDataMSD;     ///< the machine check global control register(MCG_CTL).
+  UINT8 NumHWBanks;               ///< The number of hardware error reporting banks.
+  UINT8 Rsvd[7];                  ///< reserve 7 bytes as spec's required
+} AMD_HEST_MCE_TABLE;
+
+/// HEST CMC TABLE
+typedef struct _AMD_HEST_CMC_TABLE {
+  UINT16 TblLength;               ///< Length, in bytes, of entire AMD_HEST_CMC structure.
+  UINT8 NumHWBanks;               ///< The number of hardware error reporting banks.
+  UINT8 Rsvd[3];                  ///< reserve 3 bytes as spec's required
+} AMD_HEST_CMC_TABLE;
+
+/// HEST BANK
+typedef struct _AMD_HEST_BANK {
+  UINT8 BankNum;                  ///< Zero-based index identifies the machine check error bank.
+  UINT8 ClrStatusOnInit;          ///< Indicates if the status information in this machine check bank
+                                  ///< is to be cleared during system initialization.
+  UINT8 StatusDataFormat;         ///< Indicates the format of the data in the status register
+  UINT8 ConfWriteEn;              ///< This field indicates whether configuration parameters may be
+                                  ///< modified by the OS. If the bit for the associated parameter is
+                                  ///< set, the parameter is writable by the OS.
+  UINT32 CtrlRegMSRAddr;          ///< Address of the hardware bank's control MSR. Ignored if zero.
+
+  UINT32 CtrlInitDataLSD;         ///< This is the value the OS will program into the machine check
+  UINT32 CtrlInitDataMSD;         ///< bank's control register
+  UINT32 StatRegMSRAddr;          ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
+  UINT32 AddrRegMSRAddr;          ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
+  UINT32 MiscRegMSRAddr;          ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
+} AMD_HEST_BANK;
+
+/// Initial data of AMD_HEST_BANK
+typedef struct _AMD_HEST_BANK_INIT_DATA {
+  UINT32 CtrlInitDataLSD;         ///< Initial data of CtrlInitDataLSD
+  UINT32 CtrlInitDataMSD;         ///< Initial data of CtrlInitDataMSD
+  UINT32 CtrlRegMSRAddr;          ///< Initial data of CtrlRegMSRAddr
+  UINT32 StatRegMSRAddr;          ///< Initial data of StatRegMSRAddr
+  UINT32 AddrRegMSRAddr;          ///< Initial data of AddrRegMSRAddr
+  UINT32 MiscRegMSRAddr;          ///< Initial data of MiscRegMSRAddr
+} AMD_HEST_BANK_INIT_DATA;
+
+/// MSR179 Global Machine Check Capabilities data struct
+typedef struct _MSR_MCG_CAP_STRUCT {
+  UINT64 Count:8;                 ///< Indicates the number of
+                                  ///< error-reporting banks visible to each core
+  UINT64 McgCtlP:1;               ///< 1=The machine check control registers
+  UINT64 Rsvd:55;                 ///< reserved
+} MSR_MCG_CAP_STRUCT;
+
+/// Initial data of WHEA
+typedef struct _AMD_WHEA_INIT_DATA {
+  UINT32 GlobCapInitDataLSD;      ///< Holds the value that the OS will program into the machine
+  UINT32 GlobCapInitDataMSD;      ///< Check global capability register
+  UINT32 GlobCtrlInitDataLSD;     ///< Holds the value that the OS will grogram into the machine
+  UINT32 GlobCtrlInitDataMSD;     ///< Check global control register
+  UINT8  ClrStatusOnInit;         ///< Indicates if the status information in this machine check
+                                  ///< bank is to be cleared during system initialization
+  UINT8  StatusDataFormat;        ///< Indicates the format of the data in the status register
+  UINT8  ConfWriteEn;             ///< This field indicates whether configuration parameters may be
+                                  ///< modified by the OS. If the bit for the associated parameter is
+                                  ///< set, the parameter is writable by the OS.
+  UINT8  HestBankNum;             ///< Number of HEST Bank
+  AMD_HEST_BANK_INIT_DATA *HestBankInitData;  ///< Pointer to Initial data of HEST Bank
+} AMD_WHEA_INIT_DATA;
+
+//----------------------------------------------------------------------------
+//                         DMI TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// DMI brand information
+typedef struct {
+  UINT16 String1:4;                 ///< String1
+  UINT16 String2:4;                 ///< String2
+  UINT16 Model:7;                   ///< Model
+  UINT16 Pg:1;                      ///< Page
+} BRAND_ID;
+
+/// DMI cache information
+typedef struct {
+  UINT32 L1CacheSize;               ///< L1 cache size
+  UINT8  L1CacheAssoc;              ///< L1 cache associativity
+  UINT32 L2CacheSize;               ///< L2 cache size
+  UINT8  L2CacheAssoc;              ///< L2 cache associativity
+  UINT32 L3CacheSize;               ///< L3 cache size
+  UINT8  L3CacheAssoc;              ///< L3 cache associativity
+} CPU_CACHE_INFO;
+
+/// DMI processor information
+typedef struct {
+  UINT8  ExtendedFamily;            ///< Extended Family
+  UINT8  ExtendedModel;             ///< Extended Model
+  UINT8  BaseFamily;                ///< Base Family
+  UINT8  BaseModel;                 ///< Base Model
+  UINT8  Stepping;                  ///< Stepping
+  UINT8  PackageType;               ///< PackageType
+  BRAND_ID BrandId;                 ///< BrandId which contains information about String1, String2, Model and Page
+  UINT8  TotalCoreNumber;           ///< Number of total cores
+  UINT8  EnabledCoreNumber;         ///< Number of enabled cores
+  UINT8  ProcUpgrade;               ///< ProcUpdrade
+  CPU_CACHE_INFO CacheInfo;         ///< CPU cache info
+} CPU_TYPE_INFO;
+
+/// A structure containing processor name string and
+/// the value that should be provide to DMI type 4 processor family
+typedef struct {
+  IN       CONST CHAR8 *Stringstart;  ///< The literal string
+  IN       UINT8  T4ProcFamilySetting; ///< The value set to DMI type 4 processor family
+} CPU_T4_PROC_FAMILY;
+
+/// DMI ECC information
+typedef struct {
+  BOOLEAN EccCapable;               ///< ECC Capable
+} CPU_GET_MEM_INFO;
+
+/*  Transfer vectors for DMI family specific routines   */
+typedef VOID  OPTION_DMI_GET_CPU_INFO (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef VOID  OPTION_DMI_GET_PROC_FAMILY (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef UINT8 OPTION_DMI_GET_VOLTAGE (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef UINT16  OPTION_DMI_GET_MAX_SPEED (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef UINT16  OPTION_DMI_GET_EXT_CLOCK (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef VOID  OPTION_DMI_GET_MEM_INFO (
+  IN OUT   CPU_GET_MEM_INFO  *CpuGetMemInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Brand table entry format
+typedef struct {
+  UINT8 PackageType;                ///< Package type
+  UINT8 PgOfBrandId;                ///< Page
+  UINT8 NumberOfCores;              ///< Number of cores
+  UINT8 String1ofBrandId;           ///< String1
+  UINT8 ValueSetToDmiTable;         ///< The value which will should be set to DMI table
+} DMI_BRAND_ENTRY;
+
+/// Family specific data table structure
+struct _PROC_FAMILY_TABLE {
+  UINT64                    ProcessorFamily;  ///< processor
+  OPTION_DMI_GET_CPU_INFO   *DmiGetCpuInfo;   ///< transfer vectors
+  OPTION_DMI_GET_PROC_FAMILY  *DmiGetT4ProcFamily;  ///< Get DMI type 4 processor family information
+  OPTION_DMI_GET_VOLTAGE    *DmiGetVoltage;   ///< vector for reading voltage
+  OPTION_DMI_GET_MAX_SPEED  *DmiGetMaxSpeed;  ///< vector for reading speed
+  OPTION_DMI_GET_EXT_CLOCK  *DmiGetExtClock;  ///< vector for reading external clock speed
+  OPTION_DMI_GET_MEM_INFO   *DmiGetMemInfo;   ///< Get memory information
+  UINT8                     LenBrandList;     ///< size of brand table
+  CONST DMI_BRAND_ENTRY     *DmiBrandList;    ///< translate brand info to DMI identifier
+};
+
+//----------------------------------------------------------------------------
+//                         SLIT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct {
+  UINT8   Sign[4];                      ///< Signature
+  UINT32  TableLength;                  ///< Table Length
+  UINT8   Revision;                     ///< Revision
+  UINT8   Checksum;                     ///< Checksum
+  UINT8   OemId[6];                     ///< OEM ID
+  UINT8   OemTableId[8];                ///< OEM Tabled ID
+  UINT32  OemRev;                       ///< OEM Revision
+  UINT8   CreatorId[4];                 ///< Creator ID
+  UINT32  CreatorRev;                   ///< Creator Revision
+} ACPI_TABLE_HEADER;
+
+//----------------------------------------------------------------------------
+//                         SRAT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct _CPU_SRAT_HEADER {
+  UINT8   Sign[4];                      ///< Signature
+  UINT32  TableLength;                  ///< Table Length
+  UINT8   Revision;                     ///< Revision
+  UINT8   Checksum;                     ///< Checksum
+  UINT8   OemId[6];                     ///< OEM ID
+  UINT8   OemTableId[8];                ///< OEM Tabled ID
+  UINT32  OemRev;                       ///< OEM Revision
+  UINT8   CreatorId[4];                 ///< Creator ID
+  UINT32  CreatorRev;                   ///< Creator Revision
+  UINT32  TableRev;                     ///< Table Revision
+  UINT8   Reserved[8];                  ///< Reserved
+} CPU_SRAT_HEADER;
+
+
+/// Format for SRAT APIC Affinity Entry
+typedef struct _CPU_SRAT_APIC_ENTRY {
+  UINT8   Type;                         ///< Type
+  UINT8   Length;                       ///< Length
+  UINT8   Domain;                       ///< Domain
+  UINT8   ApicId;                       ///< Apic ID
+  UINT32  Flags;                        ///< Flags
+  UINT8   LSApicEid;                    ///< Local SAPIC EID
+  UINT8   Reserved[7];                  ///< Reserved
+} CPU_SRAT_APIC_ENTRY;
+
+
+/// Format for SRAT Memory Affinity Entry
+typedef struct _CPU_SRAT_MEMORY_ENTRY {
+  UINT8   Type;                         ///< 0: Memory affinity = 1
+  UINT8   Length;                       ///< 1: Length = 40 bytes
+  UINT32  Domain;                       ///< 2: Proximity domain
+  UINT8   Reserved1[2];                 ///< 6: Reserved
+  UINT32  BaseAddrLow;                  ///< 8:  Low 32bits address base
+  UINT32  BaseAddrHigh;                 ///< 12: High 32bits address base
+  UINT32  LengthAddrLow;                ///< 16: Low 32bits address limit
+  UINT32  LengthAddrHigh;               ///< 20: High 32bits address limit
+  UINT8   Reserved2[4];                 ///< 24: Memory Type
+  UINT32  Flags;                        ///< 28: Flags
+  UINT8   Reserved3[8];                 ///< 32: Reserved
+} CPU_SRAT_MEMORY_ENTRY;
+
+//----------------------------------------------------------------------------
+//                         CRAT TYPEDEFS, STRUCTURES, ENUMS
+//                         Component Resource Affinity Table
+//----------------------------------------------------------------------------
+/// Format for CRAT Header
+typedef struct {
+  UINT8   Sign[4];                      ///< CRAT, Signature for the Component Resource Affinity Table.
+  UINT32  Length;                       ///< Length, in bytes, of the entire CRAT
+  UINT8   Revision;                     ///< 0
+  UINT8   Checksum;                     ///< Entire table must sum to zero.
+  UINT8   OemId[6];                     ///< OEM ID
+  UINT8   OemTableId[8];                ///< OEM Tabled ID
+  UINT32  OemRev;                       ///< OEM Revision
+  UINT8   CreatorId[4];                 ///< Creator ID
+  UINT32  CreatorRev;                   ///< Creator Revision
+  UINT32  TotalEntries;                 ///< total number[n] of entries in the CRAT
+  UINT16  NumDomains;                   ///< Number of HSA proximity domains
+  UINT8   Reserved[6];                  ///< Reserved
+} CRAT_HEADER;
+
+/// Flags field of the CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+  UINT32 Enabled:1;                  ///< Enabled
+  UINT32 HotPluggable:1;             ///< Hot Pluggable
+  UINT32 CpuPresent:1;               ///< Cpu Present
+  UINT32 GpuPresent:1;               ///< Gpu Present
+  UINT32 IommuPresent:1;             ///< IOMMU Present
+  UINT32 :27;                        ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT_FLAG;
+
+/// CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+  UINT8  Type;                       ///< 0 - CRAT HSA Processing Unit Structure
+  UINT8  Length;                     ///< 40
+  UINT16 Reserved;                   ///< Reserved
+  CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure
+  UINT32 ProximityDomain;            ///< Integer that represents the proximity domain to which the node belongs to
+  UINT32 ProcessorIdLow;             ///< Low value  of the logical processor included in this HSA proximity domain
+  UINT16 CpuCoreCount;               ///< Indicates overall count of x86(-64) -compatible execution units (CPU cores) are present in this (APU-) node (identifiable by SW).
+  UINT16 SimdCount;                  ///< Indicates overall count of GPU SIMDs present  in this node (identifiable by SW).
+  UINT16 SimdWidth;                  ///< "Width" of a single SIMD unit. SIMDCount*SIMDWidth determines the total number of non-x86 execution units.
+  UINT16 IoCount;                    ///< Number of discoverable IO Interfaces connecting this node to other components.
+  UINT8  Reserved1[16];              ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT;
+
+/// Flags field of the CRAT Memory Affinity Structure
+typedef struct {
+  UINT32 Enabled:1;                  ///< Enabled
+  UINT32 HotPluggable:1;             ///< Hot Pluggable
+  UINT32 NonVolatile:1;              ///< If set, the memory region represents Non-Volatile memory
+  UINT32 :29;                        ///< Reserved
+} CRAT_MEMORY_FLAG;
+
+/// CRAT Memory Affinity Structure
+typedef struct {
+  UINT8  Type;                       ///< 1 - CRAT Memory Affinity Structure
+  UINT8  Length;                     ///< 40
+  UINT16 Reserved;                   ///< Reserved
+  CRAT_MEMORY_FLAG Flags;            ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged
+  UINT32 ProximityDomain;            ///< Integer that represents the proximity domain to which the node belongs to
+  UINT32 BaseAddressLow;             ///< Low 32Bits of the Base Address of the memory range
+  UINT32 BaseAddressHigh;            ///< High 32Bits of the Base Address of the memory range
+  UINT32 LengthLow;                  ///< Low 32Bits of the length of the memory range
+  UINT32 LengthHigh;                 ///< High 32Bits of the length of the memory range
+  UINT32 Width;                      ///< Memory width - Specifies the number of parallel bits of the memory interface
+  UINT8  Reserved1[8];               ///< Reserved
+} CRAT_MEMORY;
+
+/// Flags field of the CRAT Cache Affinity structure
+typedef struct {
+  UINT32 Enabled:1;                  ///< Enabled
+  UINT32 DataCache:1;                ///< 1 if cache includes data
+  UINT32 InstructionCache:1;         ///< 1 if cache includes instructions
+  UINT32 CpuCache:1;                 ///< 1 if cache is part of CPU functionality
+  UINT32 SimdCache:1;                ///< 1 if cache is part of SIMD functionality
+  UINT32 :27;                        ///< Reserved
+} CRAT_CACHE_FLAG;
+
+/// CRAT Cache Affinity Structure
+typedef struct {
+  UINT8  Type;                       ///< 2 - CRAT Cache Affinity Structure
+  UINT8  Length;                     ///< 64
+  UINT16 Reserved;                   ///< Reserved
+  CRAT_CACHE_FLAG Flags;             ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled
+  UINT32 ProcessorIdLow;             ///< Low value of a logical processor which includes this component
+  UINT8  SiblingMap[32];             ///< Bitmask of  Processor Id sharing this component. 1 bit per logical processor
+  UINT32 CacheSize;                  ///< Cache size in KB
+  UINT8  CacheLevel;                 ///< Integer representing level: 1, 2, 3, 4, etc.
+  UINT8  LinesPerTag;                ///< Cache Lines per tag
+  UINT16 CacheLineSize;              ///< Cache line size in bytes
+  UINT8  Associativity;              ///< Cache associativity
+                                     ///< The associativity fields are encoded as follows:
+                                     ///< 00h: Reserved.
+                                     ///< 01h: Direct mapped.
+                                     ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+                                     ///< FFh: Fully associative
+  UINT8  CacheProperties;            ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded.
+                                     ///< 0: Cache is strictly exclusive to lower level caches.
+                                     ///< 1:  Cache is mostly exclusive to lower level caches.
+                                     ///< 2: Cache is strictly inclusive to lower level caches.
+                                     ///< 3: Cache is mostly inclusive to lower level caches.
+                                     ///< 4: Cache is a "constant cache" (= explicit update)
+                                     ///< 5: Cache is a "specialty cache" (e.g. Texture cache)
+                                     ///< 6-7: Reserved
+                                     ///< CacheProperties bits [7:3] are reserved
+  UINT16 CacheLatency;               ///< Cost of time to access cache described in nanoseconds.
+  UINT8  Reserved1[8];               ///< Reserved
+} CRAT_CACHE;
+
+/// Flags field of the CRAT TLB Affinity structure
+typedef struct {
+  UINT32 Enabled:1;                  ///< Enabled
+  UINT32 DataTLB:1;                  ///< 1 if TLB includes translation information for data.
+  UINT32 InstructionTLB:1;           ///< 1 if TLB includes translation information for instructions.
+  UINT32 CpuTLB:1;                   ///< 1 if TLB is part of CPU functionality
+  UINT32 SimdTLB:1;                  ///< 1 if TLB is part of SIMD functionality
+  UINT32 :27;                        ///< Reserved
+} CRAT_TLB_FLAG;
+
+/// CRAT TLB Affinity Structure
+typedef struct {
+  UINT8  Type;                       ///< 3 - CRAT TLB  Affinity Structure
+  UINT8  Length;                     ///< 64
+  UINT16 Reserved;                   ///< Reserved
+  CRAT_TLB_FLAG Flags;               ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined
+  UINT32 ProcessorIdLow;             ///< Low value of a logical processor which includes this component.
+  UINT8  SiblingMap[32];             ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+  UINT32 TLBLevel;                   ///< Integer representing level: 1, 2, 3, 4, etc.
+  UINT8  DataTLBAssociativity2MB;    ///< Data TLB associativity for 2MB pages
+                                     ///< The associativity fields are encoded as follows:
+                                     ///< 00h: Reserved.
+                                     ///< 01h: Direct mapped.
+                                     ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+                                     ///< FFh: Fully associative.
+  UINT8  DataTLBSize2MB;             ///< Data TLB number of entries for 2MB.
+  UINT8  InstructionTLBAssoc2MB;     ///< Instruction TLB associativity for 2MB pages
+                                     ///< The associativity fields are encoded as follows:
+                                     ///< 00h: Reserved.
+                                     ///< 01h: Direct mapped.
+                                     ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+                                     ///< FFh: Fully associative.
+  UINT8  InstructionTLBSize2MB;      ///< Instruction TLB number of entries for 2MB pages.
+  UINT8  DTLB4KAssoc;                ///< Data TLB Associativity for 4KB pages
+  UINT8  DTLB4KSize;                 ///< Data TLB number of entries for 4KB pages
+  UINT8  ITLB4KAssoc;                ///< Instruction TLB Associativity for 4KB pages
+  UINT8  ITLB4KSize;                 ///< Instruction TLB number of entries for 4KB pages
+  UINT8  DTLB1GAssoc;                ///< Data TLB Associativity for 1GB pages
+  UINT8  DTLB1GSize;                 ///< Data TLB number of entries for 1GB pages
+  UINT8  ITLB1GAssoc;                ///< Instruction TLB Associativity for 1GB pages
+  UINT8  ITLB1GSize;                 ///< Instruction TLB number of entries for 1GB pages
+  UINT8  Reserved1[4];               ///< Reserved
+} CRAT_TLB;
+
+/// Flags field of the CRAT FPU Affinity structure
+typedef struct {
+  UINT32 Enabled:1;                  ///< Enabled
+  UINT32 :31;                        ///< Reserved
+} CRAT_FPU_FLAG;
+
+/// CRAT FPU Affinity Structure
+typedef struct {
+  UINT8  Type;                       ///< 4 - CRAT FPU Affinity Structure
+  UINT8  Length;                     ///< 64
+  UINT16 Reserved;                   ///< Reserved
+  CRAT_FPU_FLAG Flags;               ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined
+  UINT32 ProcessorIdLow;             ///< Low value of a logical processor which includes this component.
+  UINT8  SiblingMap[32];             ///< Bitmask of  Processor Id sharing this component. 1 bit per logical processor
+  UINT32 FPUSize;                    ///< Product specific
+  UINT8  Reserved1[16];              ///< Reserved
+} CRAT_FPU;
+
+/// Flags field of the CRAT IO Affinity structure
+typedef struct {
+  UINT32 Enabled:1;                  ///< Enabled
+  UINT32 Coherency:1;                ///< If set, IO interface supports coherent transactions (natively or through protocol extensions)
+  UINT32 :30;                        ///< Reserved
+} CRAT_IO_FLAG;
+
+/// CRAT IO Affinity Structure
+typedef struct {
+  UINT8  Type;                       ///< 5 - CRAT IO Affinity Structure
+  UINT8  Length;                     ///< 64
+  UINT16 Reserved;                   ///< Reserved
+  CRAT_IO_FLAG Flags;                ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined.
+  UINT32 ProximityDomainFrom;        ///< Integer that represents the proximity domain to which the IO Interface belongs to
+  UINT32 ProximityDomainTo;          ///< Integer that represents the other proximity domain to which the IO Interface belongs to
+  UINT8  IoType;                     ///< IO Interface type. Values defined are
+                                     ///< 0: Undefined
+                                     ///< 1: Hypertransport
+                                     ///< 2: PCI Express
+                                     ///< 3: Other (e.g. internal)
+                                     ///< 4-255: Reserved
+  UINT8  VersionMajor;               ///< Major version of the Bus interface
+  UINT16 VersionMinor;               ///< Minor version of the Bus interface ((optional)
+  UINT32 MinimumLatency;             ///< Cost of time to transfer, described in nanoseconds.
+  UINT32 MaximumLatency;             ///< Cost of time to transfer, described in nanoseconds.
+  UINT32 MinimumBandwidth;           ///< Minimum interface Bandwidth in MB/s
+  UINT32 MaximumBandwidth;           ///< Maximum interface Bandwidth in MB/s
+  UINT32 RecommendedTransferSize;    ///< Recommended transfer size to reach maximum interface bandwidth in Bytes
+  UINT8  Reserved1[24];              ///< Reserved
+} CRAT_IO;
+
+#define CRAT_MAX_LENGTH    0x400ul   ///< Reserve 1K for CRAT
+/// CRAT entry type
+typedef enum {
+  CRAT_TYPE_HSA_PROC_UNIT = 0,       ///< 0 - CRAT HSA Processing Unit Structure
+  CRAT_TYPE_MEMORY,                  ///< 1 - CRAT Memory Affinity Structure
+  CRAT_TYPE_CACHE,                   ///< 2 - CRAT Cache Affinity Structure
+  CRAT_TYPE_TLB,                     ///< 3 - CRAT TLB  Affinity Structure
+  CRAT_TYPE_FPU,                     ///< 4 - CRAT FPU Affinity Structure
+  CRAT_TYPE_IO,                      ///< 5 - CRAT IO Affinity Structure
+} CRAT_ENTRY_TYPE;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdCpuLate (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  );
+
+AGESA_STATUS
+CreateAcpiWhea (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+AGESA_STATUS
+CreateDmiRecords (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   DMI_INFO             **DmiTable
+  );
+
+AGESA_STATUS
+GetType4Type7Info (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+VOID
+DmiGetT4ProcFamilyFromBrandId (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+GetNameString (
+  IN OUT   CHAR8 *String,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+IsSourceStrContainTargetStr (
+  IN OUT   CHAR8 *SourceStr,
+  IN OUT   CONST CHAR8 *TargetStr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CreateAcpiCrat (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   VOID                  **CratPtr
+  );
+
+AGESA_STATUS
+CreateAcpiCdit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+  );
+
+AGESA_STATUS
+CreateAcpiSrat (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **SratPtr
+  );
+
+AGESA_STATUS
+CreateAcpiSlit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+
+VOID
+ChecksumAcpiTable (
+  IN OUT   ACPI_TABLE_HEADER *Table,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+RunLateApTaskOnAllCore0s (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
new file mode 100644
index 0000000000..1ccc7e7221
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
@@ -0,0 +1,456 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Microcode Patch Related Functions
+ *
+ * Contains code to program a microcode into the CPU
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *---------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuEarlyInit.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUMICROCODEPATCH_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef union {
+  UINT64           RawData;
+  PATCH_LOADER_MSR BitFields;
+} PATCH_LOADER;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+LoadMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+LoadMicrocodePatchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  Update microcode patch in current processor.
+ *
+ *  Then reads the patch id, and compare it to the expected, in the Microprocessor
+ *  patch block.
+ *
+ *  @param[in] StdHeader   - Config handle for library and services.
+ *
+ *  @retval    TRUE   - Patch Loaded Successfully.
+ *  @retval    FALSE  - Patch Did Not Get Loaded.
+ *
+ */
+BOOLEAN
+LoadMicrocodePatch (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    PatchNumber;
+  UINT8    TotalPatches;
+  UINT16   ProcessorEquivalentId;
+  BOOLEAN  Status;
+  MICROCODE_PATCH **MicrocodePatchPtr;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  MICROCODE_PATCH *ForceLoadMicrocodePatchPtr;
+  Status = FALSE;
+
+  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    // Get the patch pointer
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (CONST VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader);
+    ForceLoadMicrocodePatchPtr = NULL;
+    IDS_SKIP_HOOK (IDS_UCODE, &ForceLoadMicrocodePatchPtr, StdHeader) {
+      if (ForceLoadMicrocodePatchPtr == NULL) {
+        // Get the processor microcode path equivalent ID
+        if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) {
+          // parse the patch table to see if we have one for the current cpu
+          for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) {
+            if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) {
+              if (LoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) {
+                Status = TRUE;
+              } else {
+                PutEventLog (AGESA_ERROR,
+                             CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED,
+                             0, 0, 0, 0, StdHeader);
+              }
+              break; // Once we find a microcode patch that matches the processor, exit the for loop
+            }
+          }
+        }
+      } else {
+        if (LoadMicrocode (ForceLoadMicrocodePatchPtr, StdHeader)) {
+          Status = TRUE;
+        } else {
+          PutEventLog (AGESA_ERROR,
+                       CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED,
+                       0, 0, 0, 0, StdHeader);
+        }
+      }
+    }
+  }
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  LoadMicrocode
+ *
+ *    Update microcode patch in current processor, then reads the
+ *    patch id, and compare it to the expected, in the Microprocessor
+ *    patch block.
+ *
+ *    @param[in]       MicrocodePatchPtr  - Pointer to Microcode Patch.
+ *    @param[in,out]   StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          TRUE  - Patch Loaded Successfully.
+ *    @retval          FALSE - Patch Did Not Get Loaded.
+ *
+ */
+BOOLEAN
+STATIC
+LoadMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32       MicrocodeVersion;
+  PATCH_LOADER PatchLoaderMsr;
+
+  // Load microcode patch into CPU
+  PatchLoaderMsr.RawData = (UINT64) (UINTN) MicrocodePatchPtr;
+  PatchLoaderMsr.BitFields.SBZ = 0;
+  LibAmdMsrWrite (0xC0010020ul , &PatchLoaderMsr.RawData, StdHeader);
+
+  // Do ucode patch Authentication
+  // Read microcode version back from CPU, determine if
+  // it is the same patch level as contained in the source
+  // microprocessor patch block passed in
+  GetMicrocodeVersion (&MicrocodeVersion, StdHeader);
+  if (MicrocodeVersion == MicrocodePatchPtr->PatchID) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  GetPatchEquivalentId
+ *
+ *    Return the equivalent ID for microcode patching
+ *
+ *    @param[in,out]   ProcessorEquivalentId   - Pointer to Processor Equivalent ID table.
+ *    @param[in,out]   StdHeader               - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          TRUE  - ID Found.
+ *    @retval          FALSE - ID Not Found.
+ *
+ */
+BOOLEAN
+GetPatchEquivalentId (
+  IN OUT   UINT16             *ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8        i;
+  UINT8        EquivalencyEntries;
+  UINT16       ProcessorRevisionId;
+  UINT16       *MicrocodeEquivalenceTable;
+  CPUID_DATA   CpuIdData;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  //
+  // compute the processor revision ID
+  //
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuIdData, StdHeader);
+  // high byte contains extended model and extended family
+  ProcessorRevisionId  = (UINT16) ((CpuIdData.EAX_Reg & (CPU_EMODEL | CPU_EFAMILY)) >> 8);
+  // low byte contains model and family
+  ProcessorRevisionId |= (CpuIdData.EAX_Reg & (CPU_STEPPING | CPU_MODEL));
+
+  //
+  // find the equivalent ID for microcode purpose using the equivalence table
+  //
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices,
+                                                        (CONST VOID **) &MicrocodeEquivalenceTable,
+                                                        &EquivalencyEntries,
+                                                        StdHeader);
+
+  // parse the equivalence table
+  for (i = 0; i < (EquivalencyEntries * 2); i += 2) {
+    // check for equivalence
+    if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) {
+      *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1];
+      return (TRUE);
+    }
+  }
+  // end of table reach, this processor is not supported
+  *ProcessorEquivalentId = 0x0000;
+  return (FALSE);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  ValidateMicrocode
+ *
+ *    Determine if the microcode patch block, currently pointed to
+ *    is valid, and is appropriate for the current processor
+
+ *    @param[in]       MicrocodePatchPtr      - Pointer to Microcode Patch.
+ *    @param[in]       ProcessorEquivalentId  - Pointer to Processor Equivalent ID table.
+ *    @param[in,out]   StdHeader              - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          TRUE  - Patch Found.
+ *    @retval          FALSE - Patch Not Found.
+ *
+ */
+BOOLEAN
+ValidateMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN       UINT16             ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BOOLEAN   Chipset1Matched;
+  BOOLEAN   Chipset2Matched;
+  PCI_ADDR  PciAddress;
+  UINT32    PciDeviceVidDid;
+  UINT8     PciDeviceRevision;
+  UINT8     DevCount;
+  UINT8     FunCount;
+  UINT32    Chipset1DeviceID;
+  UINT32    Chipset2DeviceID;
+  UINT8     MulitFunction;
+
+  Chipset1Matched = FALSE;
+  Chipset2Matched = FALSE;
+  PciDeviceVidDid = 0;
+  PciDeviceRevision = 0;
+  Chipset1DeviceID = MicrocodePatchPtr->Chipset1DeviceID;
+  Chipset2DeviceID = MicrocodePatchPtr->Chipset2DeviceID;
+  MulitFunction = 0;
+
+  //
+  // parse the supplied microcode to see if it is compatible with the processor
+  //
+  if (MicrocodePatchPtr->ProcessorRevisionID !=  ProcessorEquivalentId) {
+    return (FALSE);
+  }
+
+  if (Chipset1DeviceID == 0) {
+    Chipset1Matched = TRUE;
+  }
+  if (Chipset2DeviceID == 0) {
+    Chipset2Matched = TRUE;
+  }
+
+  if ((!Chipset1Matched) || (!Chipset2Matched)) {
+    //
+    // Scan all PCI devices in Bus 0, try to find out matched case.
+    //
+    for (DevCount = 0; DevCount < 32; DevCount++) {
+      for (FunCount = 0; FunCount < 8; FunCount++) {
+        PciAddress.AddressValue = MAKE_SBDFO (0, 0, DevCount, FunCount, 0);
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciDeviceVidDid, StdHeader);
+        if (PciDeviceVidDid == 0xFFFFFFFF) {
+          if (FunCount == 0) {
+            break;
+          } else {
+            continue;
+          }
+        }
+        PciAddress.Address.Register = 0x8;
+        LibAmdPciRead (AccessWidth8, PciAddress, &PciDeviceRevision, StdHeader);
+        if ((!Chipset1Matched) && (PciDeviceVidDid == Chipset1DeviceID)) {
+          if (PciDeviceRevision == MicrocodePatchPtr->Chipset1RevisionID) {
+            Chipset1Matched = TRUE;
+          }
+        }
+        if ((!Chipset2Matched) && (PciDeviceVidDid == Chipset2DeviceID)) {
+          if (PciDeviceRevision == MicrocodePatchPtr->Chipset2RevisionID) {
+            Chipset2Matched = TRUE;
+          }
+        }
+        if (Chipset1Matched && Chipset2Matched) {
+          break;
+        }
+        //
+        // Check multi-function. If it doesen't exist, we don't have to loop functions to 7.
+        //
+        if (FunCount == 0) {
+          MulitFunction = 0;
+          PciAddress.Address.Register = 0xE;
+          LibAmdPciRead (AccessWidth8, PciAddress, &MulitFunction, StdHeader);
+          if ((MulitFunction & 0x80) == 0) {
+            break;
+          }
+        }
+      } // end FunCount for loop.
+
+      if (Chipset1Matched && Chipset2Matched) {
+        break;
+      }
+    }  // end DevCount for loop.
+  }
+
+  return (Chipset1Matched && Chipset2Matched);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  GetMicrocodeVersion
+ *
+ *    Return the version of the currently loaded microcode patch, if any.
+ *    Read from the patch level MSR, return the value in eax. If no patch
+ *    has been loaded, 0 will be returned.
+ *
+ *    @param[out]      pMicrocodeVersion  - Pointer to Microcode Version.
+ *    @param[in,out]   StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+GetMicrocodeVersion (
+     OUT   UINT32             *pMicrocodeVersion,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT64  MsrData;
+
+  MsrData = 0;
+  LibAmdMsrRead (0x0000008Bul , &MsrData, StdHeader);
+
+  *pMicrocodeVersion = (UINT32) MsrData;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Update microcode patch in current processor.
+ *
+ * This function acts as a wrapper for calling the LoadMicrocodePatch
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+LoadMicrocodePatchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
+  LoadMicrocodePatch (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPage.h
new file mode 100644
index 0000000000..27e25c52af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPage.h
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for CPU Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/**
+ * @page cpumain CPU Component Documentation
+ *
+ * Additional documentation for the CPU component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage cpuimplfss "CPU Family Specific Services Implementation Guide"
+ *   - @subpage regtableimpl  "Register Table Implementation Guide"
+ *   - @subpage cpufeatimpl  "CPU Generic Feature Implementation Guide"
+ *   - @subpage ucodeflag "Microcode Patches Signature Guide"
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
new file mode 100644
index 0000000000..5eda346c6a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
@@ -0,0 +1,519 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU POST API, and related functions.
+ *
+ * Contains code that initialized the CPU after memory init.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ****************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * Description: cpuPostInit.c - Cpu POST Initialization Functions.
+ *
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Options.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "GeneralServices.h"
+#include "cpuPostInit.h"
+#include "cpuPstateTables.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_CPU_CPUPOSTINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SyncVariableMTRR (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+extern
+VOID
+ExecuteWbinvdInstruction (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+PstateCreateHeapInfo (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the POST entry point
+ *
+ * This function performs a large list of initialization items.  These items
+ * include:
+ *
+ *    -1      AP MTRR sync
+ *    -2      feature leveling
+ *    -3      P-state data gather
+ *    -4      P-state leveling
+ *    -5      AP cache breakdown & release
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  PlatformConfig    Config handle for platform specific information
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+AmdCpuPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+  //
+  // Sync variable MTRR
+  //
+  AGESA_TESTPOINT (TpProcCpuApMtrrSync, StdHeader);
+  SyncVariableMTRR (StdHeader);
+
+  AGESA_TESTPOINT (TpProcCpuPostFeatureInit, StdHeader);
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features after AP MTRR sync\n");
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_POST_MTRR_SYNC, PlatformConfig, StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+  //
+  // Feature Leveling
+  //
+  AGESA_TESTPOINT (TpProcCpuFeatureLeveling, StdHeader);
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Perform feature leveling\n");
+  FeatureLeveling (StdHeader);
+  //
+  // P-state Gathered and set heap info
+  //
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Create P-state info in the heap\n");
+  PstateCreateHeapInfo (PlatformConfig, StdHeader);
+
+  // Set TscFreqSel at the rate specified by the core P0 after core frequency leveling.
+  SetCoresTscFreqSel (StdHeader);
+
+  // Dispatch CPU features before relinquishing control of APs
+  AGESA_TESTPOINT (TpProcCpuBeforeRelinquishAPsFeatureInit, StdHeader);
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features before Relinquishing control of APs\n");
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_RELINQUISH_AP, PlatformConfig, StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  // Relinquish control of all APs to IBV.
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Relinquish control of APs\n");
+  RelinquishControlOfAllAPs (StdHeader);
+
+  return (AgesaStatus);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the address in system DRAM that should be used for p-state data
+ * gather and leveling.
+ *
+ * @param[out] Ptr               Address to utilize
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+GetPstateGatherDataAddressAtPost (
+     OUT   UINT64            **Ptr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 AddressValue;
+
+  AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
+
+  *Ptr = (UINT64 *)(AddressValue);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * AP task to sync memory subsystem MSRs with the BSC
+ *
+ * This function processes a list of MSRs and the BSC's current values for those
+ * MSRs.  This will allow the APs to see system RAM.
+ *
+ * @param[in]  MtrrTable         Memory related MSR table
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+SyncAllApMtrrToBsc (
+  IN       VOID *MtrrTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   i;
+
+  for (i = 0; ((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress != 0; i++) {
+    LibAmdMsrWrite (((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress,
+                    &((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterValue,
+                    StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Creates p-state information on the heap
+ *
+ * This function gathers p-state information from all processors in the system,
+ * determines a level set of p-states, and places that information into the
+ * heap.  This heap data will be used by GenerateSsdt to generate the
+ * final _PSS and XPSS objects.
+ *
+ * @param[in]  PlatformConfig    Pointer to runtime configuration options
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS     No error
+ * @retval     AGESA_ERROR       CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE
+ */
+AGESA_STATUS
+PstateCreateHeapInfo (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS            AgesaStatus;
+  S_CPU_AMD_PSTATE        *PStateBufferPtr;
+  ALLOCATE_HEAP_PARAMS    AllocHeapParams;
+  UINT8                   *PStateBufferPtrInHeap;
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  //
+  //Get proper address for gather data pool address
+  //Zero P-state gather data pool
+  //
+  GetPstateGatherDataAddressAtPost ((UINT64 **)&PStateBufferPtr, StdHeader);
+  LibAmdMemFill (PStateBufferPtr, 0, sizeof (S_CPU_AMD_PSTATE), StdHeader);
+
+  //
+  //Get all the CPUs P-States and fill the PStateBufferPtr for each core
+  //
+  AgesaStatus = PStateGatherData (PlatformConfig, PStateBufferPtr, StdHeader);
+  if (AgesaStatus != AGESA_SUCCESS) {
+    return AgesaStatus;
+  }
+
+  //
+  //Do Pstate Leveling for each core if needed.
+  //
+  AgesaStatus = PStateLeveling (PStateBufferPtr, StdHeader);
+
+  //
+  //Create Heap and store p-state data for ACPI table in CpuLate
+  //
+  AllocHeapParams.RequestedBufferSize = PStateBufferPtr->SizeOfBytes;
+  AllocHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    //
+    // Zero Buffer
+    //
+    PStateBufferPtrInHeap = (UINT8 *) AllocHeapParams.BufferPtr;
+    LibAmdMemFill (PStateBufferPtrInHeap, 0, PStateBufferPtr->SizeOfBytes, StdHeader);
+    LibAmdMemCopy  (PStateBufferPtrInHeap, PStateBufferPtr, PStateBufferPtr->SizeOfBytes, StdHeader);
+
+  } else {
+    PutEventLog (AGESA_ERROR,
+                   CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE,
+                 0, 0, 0, 0, StdHeader);
+  }
+
+  return AgesaStatus;
+}
+
+VOID
+SyncApMsrsToBsc (
+  IN OUT   BSC_AP_MSR_SYNC    *ApMsrSync,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT16                  i;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCoreNum;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  //
+  //Sync all MTRR settings with BSP
+  //
+  for (i = 0; ApMsrSync[i].RegisterAddress != 0; i++) {
+    LibAmdMsrRead (ApMsrSync[i].RegisterAddress, &ApMsrSync[i].RegisterValue, StdHeader);
+  }
+
+  TaskPtr.FuncAddress.PfApTaskI = SyncAllApMtrrToBsc;
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((((sizeof (BSC_AP_MSR_SYNC)) * i) + 4) >> 2);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = ApMsrSync;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * SyncVariableMTRR
+ *
+ * Sync variable MTRR
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+SyncVariableMTRR (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BSC_AP_MSR_SYNC ApMsrSync[20];
+
+  ApMsrSync[0].RegisterAddress = SYS_CFG;
+  ApMsrSync[1].RegisterAddress = TOP_MEM;
+  ApMsrSync[2].RegisterAddress = TOP_MEM2;
+  ApMsrSync[3].RegisterAddress = 0x200;
+  ApMsrSync[4].RegisterAddress = 0x201;
+  ApMsrSync[5].RegisterAddress = 0x202;
+  ApMsrSync[6].RegisterAddress = 0x203;
+  ApMsrSync[7].RegisterAddress = 0x204;
+  ApMsrSync[8].RegisterAddress = 0x205;
+  ApMsrSync[9].RegisterAddress = 0x206;
+  ApMsrSync[10].RegisterAddress = 0x207;
+  ApMsrSync[11].RegisterAddress = 0x208;
+  ApMsrSync[12].RegisterAddress = 0x209;
+  ApMsrSync[13].RegisterAddress = 0x20A;
+  ApMsrSync[14].RegisterAddress = 0x20B;
+  ApMsrSync[15].RegisterAddress = 0xC0010016;
+  ApMsrSync[16].RegisterAddress = 0xC0010017;
+  ApMsrSync[17].RegisterAddress = 0xC0010018;
+  ApMsrSync[18].RegisterAddress = 0xC0010019;
+  ApMsrSync[19].RegisterAddress = 0;
+  SyncApMsrsToBsc (ApMsrSync, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The function suppose to do any thing need to be done at the end of AmdInitPost.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+FinalizeAtPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  //
+  // Execute wbinvd to ensure heap data in cache write back to memory.
+  //
+  ExecuteWbinvdInstruction (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set TSC Frequency Selection.
+ *
+ * This function set TSC Frequency Selection.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+SetTscFreqSel (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
+
+  FamilyServices = NULL;
+
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  if (FamilyServices != NULL) {
+    FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader);
+  }
+
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set TSC Frequency Selection to all cores.
+ *
+ * This function set TscFreqSel to all cores in the system.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+SetCoresTscFreqSel (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCoreNum;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  SetTscFreqSel (StdHeader);
+
+  TaskPtr.FuncAddress.PfApTask = SetTscFreqSel;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.DataTransfer.DataPtr = NULL;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h
new file mode 100644
index 0000000000..91bc28a25a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h
@@ -0,0 +1,265 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POST_INIT_H_
+#define _CPU_POST_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (CPU_CFOH_FAMILY_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define P_STATE_DATA_GATHER_TEMP_ADDR     0x200000ul ///< Fixed the row data at 2M memory address.
+#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000ul ///< Fixed the row data at 2M memory address.
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// CPU FEATURE LIST
+typedef struct {
+  UINT8  ABM:1;             ///< byte 0 bit 0
+  UINT8  AES:1;             ///< byte 0 bit 1
+  UINT8  AltMovCr8:1;       ///< byte 0 bit 2
+  UINT8  APIC:1;            ///< byte 0 bit 3
+  UINT8  AVX:1;             ///< byte 0 bit 4
+  UINT8  CLFSH:1;           ///< byte 0 bit 5
+  UINT8  CMOV:1;            ///< byte 0 bit 6
+  UINT8  CmpLegacy:1;       ///< byte 0 bit 7
+  UINT8  CMPXCHG8B:1;       ///< byte 1 bit 0
+  UINT8  CMPXCHG16B:1;      ///< byte 1 bit 1
+  UINT8  F16C :1;           ///< byte 1 bit 2
+  UINT8  DE:1;              ///< byte 1 bit 3
+  UINT8  ExtApicSpace:1;    ///< byte 1 bit 4
+  UINT8  FFXSR:1;           ///< byte 1 bit 5
+  UINT8  FMA:1;             ///< byte 1 bit 6
+  UINT8  FMA4:1;            ///< byte 1 bit 7
+  UINT8  FPU:1;             ///< byte 2 bit 0
+  UINT8  FXSR:1;            ///< byte 2 bit 1
+  UINT8  HTT:1;             ///< byte 2 bit 2
+  UINT8  IBS:1;             ///< byte 2 bit 3
+  UINT8  LahfSahf:1;        ///< byte 2 bit 4
+  UINT8  LM:1;              ///< byte 2 bit 5
+  UINT8  LWP:1;             ///< byte 2 bit 6
+  UINT8  MCA:1;             ///< byte 2 bit 7
+  UINT8  MCE:1;             ///< byte 3 bit 0
+  UINT8  MisAlignSse:1;     ///< byte 3 bit 1
+  UINT8  MMX:1;             ///< byte 3 bit 2
+  UINT8  MmxExt:1;          ///< byte 3 bit 3
+  UINT8  Monitor:1;         ///< byte 3 bit 4
+  UINT8  MSR:1;             ///< byte 3 bit 5
+  UINT8  MTRR:1;            ///< byte 3 bit 6
+  UINT8  NodeId:1;          ///< byte 3 bit 7
+  UINT8  NX:1;              ///< byte 4 bit 0
+  UINT8  OSVW:1;            ///< byte 4 bit 1
+  UINT8  OSXSAVE:1;         ///< byte 4 bit 2
+  UINT8  PAE:1;             ///< byte 4 bit 3
+  UINT8  Page1GB:1;         ///< byte 4 bit 4
+  UINT8  PAT:1;             ///< byte 4 bit 5
+  UINT8  PCLMULQDQ:1;       ///< byte 4 bit 6
+  UINT8  PGE:1;             ///< byte 4 bit 7
+  UINT8  POPCNT:1;          ///< byte 5 bit 0
+  UINT8  PSE:1;             ///< byte 5 bit 1
+  UINT8  PSE36:1;           ///< byte 5 bit 2
+  UINT8  RDTSCP:1;          ///< byte 5 bit 3
+  UINT8  SKINIT:1;          ///< byte 5 bit 4
+  UINT8  SSE:1;             ///< byte 5 bit 5
+  UINT8  SSE2:1;            ///< byte 5 bit 6
+  UINT8  SSE3:1;            ///< byte 5 bit 7
+  UINT8  SSE4A:1;           ///< byte 6 bit 0
+  UINT8  SSE41:1;           ///< byte 6 bit 1
+  UINT8  SSE42:1;           ///< byte 6 bit 2
+  UINT8  SSE5:1;            ///< byte 6 bit 3
+  UINT8  SSSE3:1;           ///< byte 6 bit 4
+  UINT8  SVM:1;             ///< byte 6 bit 5
+  UINT8  SysCallSysRet:1;   ///< byte 6 bit 6
+  UINT8  SysEnterSysExit:1; ///< byte 6 bit 7
+  UINT8  bit56 :1;            ///< byte 7 bit 0
+  UINT8  TCE:1;             ///< byte 7 bit 1
+  UINT8  ThreeDNow:1;       ///< byte 7 bit 2
+  UINT8  ThreeDNowExt:1;    ///< byte 7 bit 3
+  UINT8  ThreeDNowPrefetch:1; ///< byte 7 bit 4
+  UINT8  TimeStampCounter:1;  ///< byte 7 bit 5
+  UINT8  VME:1;             ///< byte 7 bit 6
+  UINT8  WDT:1;             ///< byte 7 bit 7
+  UINT8  X2APIC:1;          ///< byte 8 bit 0
+  UINT8  XOP:1;             ///< byte 8 bit 1
+  UINT8  XSAVE:1;           ///< byte 8 bit 2
+  UINT8  Reserve:5;         ///< Reserved
+} CPU_FEATURES_LIST;
+
+//----------------------------------------------------------------------------
+//                         POST INIT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// BSC to AP MSR sync up
+typedef struct {
+  UINT32 RegisterAddress;   ///< MSR Address
+  UINT64 RegisterValue;     ///< BSC's MSR Value
+} BSC_AP_MSR_SYNC;
+
+/**
+ *  Set Cache Flush On Halt Register.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]          FamilySpecificServices   The current Family Specific Services.
+ * @param[in]          EntryPoint               Timepoint designator.
+ * @param[in]          PlatformConfig           Contains the runtime modifiable feature input data.
+ * @param[in]          StdHeader                Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_SET_CFOH_REG) (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+ /// Reference to a Method.
+typedef F_CPU_SET_CFOH_REG *PF_CPU_SET_CFOH_REG;
+
+/**
+ * Provide the interface to the Cache Flush On Halt Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CFOH_FAMILY_SERVICES {                     // See forward reference above
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_CPU_SET_CFOH_REG SetCacheFlushOnHaltRegister;    ///< Method: Set Cache Flush On Halt register.
+};
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+//                   These are   P U B L I C   functions, used by IBVs
+AGESA_STATUS
+AmdCpuPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  );
+
+//                   These are   P U B L I C   functions, used by AGESA
+
+VOID
+FeatureLeveling (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CopyHeapToTempRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SyncApMsrsToBsc (
+  IN OUT   BSC_AP_MSR_SYNC    *ApMsrSync,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+FinalizeAtPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetCoresTscFreqSel (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GetPstateGatherDataAddressAtPost (
+     OUT   UINT64            **Ptr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SyncAllApMtrrToBsc (
+  IN       VOID *MtrrTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _CPU_POST_INIT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c
new file mode 100644
index 0000000000..52e8e1e363
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c
@@ -0,0 +1,302 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Power Management functions.
+ *
+ * Contains code for doing early power management
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMultiSocket.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PerformThisPmStep (
+  IN       VOID *Step,
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+VOID
+STATIC
+GoToMemInitPstateCore0 (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+VOID
+STATIC
+GoToMemInitPstateCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the "BIOS Requirements for P-State Initialization and Transitions."
+ *
+ * This is the generic arbiter code to be executed by the BSC.  The system power
+ * management init tables will be traversed.  This must be run by the system BSC
+ * only.
+ *
+ * @param[in]  CpuEarlyParams    Required input parameters for early CPU initialization
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return     Most severe AGESA_STATUS level that any system processor encountered
+ *
+ */
+AGESA_STATUS
+PmInitializationAtEarly (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8              i;
+  UINT8              NumberOfSystemWideSteps;
+  AP_TASK            TaskPtr;
+  AGESA_STATUS       ReturnCode;
+  WARM_RESET_REQUEST Request;
+
+  // Determine the number of steps to perform
+  OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader);
+
+  // Traverse the PM init table
+  TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep;
+  TaskPtr.DataTransfer.DataSizeInDwords = 1;
+  TaskPtr.DataTransfer.DataPtr = &i;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  for (i = 0; i < NumberOfSystemWideSteps; ++i) {
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Perform PM init step %d\n", i);
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
+  }
+
+  // GoToMemInitPstateCore0 only if there is no pending warm reset.
+  GetWarmResetFlag (StdHeader, &Request);
+  if (Request.RequestBit == FALSE) {
+    TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0;
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Transition all cores to POST P-state\n");
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
+  }
+
+  // Retrieve/Process any errors
+  ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader);
+
+  return (ReturnCode);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs the next step in the executing core 0's family specific power
+ * management table.
+ *
+ * This function determines if the input step is valid, and invokes the power
+ * management step if appropriate.  This must be run by processor core 0s only.
+ *
+ * @param[in]  Step              Zero based step number
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+STATIC
+PerformThisPmStep (
+  IN       VOID *Step,
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  UINT8           MyNumberOfSteps;
+  UINT32          ExeResetFlags;
+  SYS_PM_TBL_STEP *FamilyTablePtr;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN         ThisIsWarmReset;
+  BOOLEAN         NoResetLimit;
+  BOOLEAN         NotConflictResetLimit;
+  BOOLEAN         WarmResetOnly;
+  BOOLEAN         ColdResetOnly;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &FamilyTablePtr, &MyNumberOfSteps, StdHeader);
+
+  if (*(UINT8 *)Step < MyNumberOfSteps) {
+    if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) {
+      ExeResetFlags = FamilyTablePtr[*(UINT8 *)Step].ExeFlags & (PM_EXEFLAGS_COLD_ONLY | PM_EXEFLAGS_WARM_ONLY);
+      ThisIsWarmReset = IsWarmReset (StdHeader);
+      NoResetLimit = (ExeResetFlags == 0) ? TRUE : FALSE;
+      NotConflictResetLimit = (BOOLEAN) (ExeResetFlags != (PM_EXEFLAGS_COLD_ONLY | PM_EXEFLAGS_WARM_ONLY));
+      WarmResetOnly = (BOOLEAN) ((ExeResetFlags & PM_EXEFLAGS_WARM_ONLY) == PM_EXEFLAGS_WARM_ONLY);
+      ColdResetOnly = (BOOLEAN) ((ExeResetFlags & PM_EXEFLAGS_COLD_ONLY) == PM_EXEFLAGS_COLD_ONLY);
+
+      IDS_HDT_CONSOLE (CPU_TRACE, "  \tIsWarmReset = %d.\n", ThisIsWarmReset);
+      IDS_HDT_CONSOLE (CPU_TRACE, "  \tNoResetLimit = %d\n", NoResetLimit);
+      IDS_HDT_CONSOLE (CPU_TRACE, "  \tNotConflictResetLimit = %d\n", NotConflictResetLimit);
+      IDS_HDT_CONSOLE (CPU_TRACE, "  \tWarmResetOnly = %d\n", WarmResetOnly);
+      IDS_HDT_CONSOLE (CPU_TRACE, "  \tColdResetOnly = %d\n", ColdResetOnly);
+
+      ASSERT (NotConflictResetLimit);
+
+      if (NoResetLimit ||
+          (NotConflictResetLimit &&
+           ((WarmResetOnly && ThisIsWarmReset) || (ColdResetOnly && !ThisIsWarmReset)))) {
+        FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader);
+      } else {
+        IDS_HDT_CONSOLE (CPU_TRACE, "  \t\tThis PM init step was skipped!\n");
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Transitions the executing processor to the desired P-state.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is
+ * run by all processor core 0s.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+STATIC
+GoToMemInitPstateCore0 (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  AP_TASK      TaskPtr;
+
+  TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Transitions the executing core to the desired P-state.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is
+ * run by all system cores.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+STATIC
+GoToMemInitPstateCore (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c
new file mode 100644
index 0000000000..fb3d08e5e0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -0,0 +1,613 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Power Management Multisocket Functions.
+ *
+ * Contains code for doing power management for multisocket CPUs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuPowerMgmtMultiSocket.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetNextEvent (
+  IN OUT   VOID  *EventLogEntryPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
+ *
+ * This function loops through all possible socket locations, starting core 0 of
+ * each populated socket to perform the passed in AP_TASK.  After starting all
+ * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by
+ * the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ * @return     The most severe error code from AP_TASK
+ *
+ */
+AGESA_STATUS
+RunCodeOnAllSystemCore0sMulti (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  )
+{
+  UINT32 BscSocket;
+  UINT32 BscModule;
+  UINT32 BscCoreNum;
+  UINT8  Socket;
+  UINT32 NumberOfSockets;
+  AGESA_STATUS DummyStatus;
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledStatus;
+
+
+  ASSERT (IsBsp (StdHeader, &DummyStatus));
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);
+  AgesaStatus = AGESA_SUCCESS;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        CalledStatus = ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader);
+        if (CalledStatus > AgesaStatus) {
+          AgesaStatus = CalledStatus;
+        }
+      }
+    }
+  }
+  CalledStatus = ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  return AgesaStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket BSC call to determine the maximum number of steps that any single
+ * processor needs to execute.
+ *
+ * This function loops through all possible socket locations, gathering the number
+ * of power management steps each populated socket requires, and returns the
+ * highest number.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+GetNumberOfSystemPmStepsPtrMulti (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  NumberOfSteps;
+  UINT32 NumberOfSockets;
+  UINT32 Socket;
+  SYS_PM_TBL_STEP *Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  *NumSystemSteps = 0;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+      FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, &NumberOfSteps, StdHeader);
+      if (NumberOfSteps > *NumSystemSteps) {
+        *NumSystemSteps = NumberOfSteps;
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket call to determine the frequency that the northbridges must run.
+ *
+ * This function loops through all possible socket locations, comparing the
+ * maximum NB frequencies to determine the slowest.  This function also
+ * determines if all coherent NB frequencies are equivalent.
+ *
+ * @param[in]  NbPstate                    NB P-state number to check (0 = fastest)
+ * @param[in]  PlatformConfig              Platform profile/build option config structure.
+ * @param[out] SystemNbCofNumerator        NB frequency numerator for the system in MHz
+ * @param[out] SystemNbCofDenominator      NB frequency denominator for the system
+ * @param[out] SystemNbCofsMatch           Whether or not all NB frequencies are equivalent
+ * @param[out] NbPstateIsEnabledOnAllCPUs  Whether or not NbPstate is valid on all CPUs
+ * @param[in]  StdHeader                   Config handle for library and services
+ *
+ * @retval     TRUE                        At least one processor has NbPstate enabled.
+ * @retval     FALSE                       NbPstate is disabled on all CPUs
+ *
+ */
+BOOLEAN
+GetSystemNbCofMulti (
+  IN       UINT32 NbPstate,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32 *SystemNbCofNumerator,
+     OUT   UINT32 *SystemNbCofDenominator,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32   Socket;
+  UINT8    Module;
+  UINT32   CurrentNbCof;
+  UINT32   CurrentDivisor;
+  UINT32   CurrentFreq;
+  UINT32   LowFrequency;
+  UINT32   Ignored32;
+  BOOLEAN  FirstCofNotFound;
+  BOOLEAN  NbPstateDisabled;
+  BOOLEAN  IsNbPstateEnabledOnAny;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  // Find the slowest NB COF in the system & whether or not all are equivalent
+  LowFrequency = 0xFFFFFFFF;
+  *SystemNbCofsMatch = TRUE;
+  *NbPstateIsEnabledOnAllCPUs = FALSE;
+  IsNbPstateEnabledOnAny = FALSE;
+  FirstCofNotFound = TRUE;
+  NbPstateDisabled = FALSE;
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) {
+          break;
+        }
+      }
+      if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
+                                                   PlatformConfig,
+                                                   &PciAddress,
+                                                   NbPstate,
+                                                   &CurrentNbCof,
+                                                   &CurrentDivisor,
+                                                   &Ignored32,
+                                                   StdHeader)) {
+        ASSERT (CurrentDivisor != 0);
+        CurrentFreq = (CurrentNbCof / CurrentDivisor);
+        if (FirstCofNotFound) {
+          *SystemNbCofNumerator = CurrentNbCof;
+          *SystemNbCofDenominator = CurrentDivisor;
+          LowFrequency = CurrentFreq;
+          IsNbPstateEnabledOnAny = TRUE;
+          if (!NbPstateDisabled) {
+            *NbPstateIsEnabledOnAllCPUs = TRUE;
+          }
+          FirstCofNotFound = FALSE;
+        } else {
+          if (CurrentFreq != LowFrequency) {
+            *SystemNbCofsMatch = FALSE;
+            if (CurrentFreq < LowFrequency) {
+              LowFrequency = CurrentFreq;
+              *SystemNbCofNumerator = CurrentNbCof;
+              *SystemNbCofDenominator = CurrentDivisor;
+            }
+          }
+        }
+      } else {
+        NbPstateDisabled = TRUE;
+        *NbPstateIsEnabledOnAllCPUs = FALSE;
+      }
+    }
+  }
+  return IsNbPstateEnabledOnAny;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket call to determine if the BIOS is responsible for updating the
+ * northbridge operating frequency and voltage.
+ *
+ * This function loops through all possible socket locations, checking whether
+ * any populated sockets require NB COF VID programming.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     TRUE    BIOS needs to set up NB frequency and voltage
+ * @retval     FALSE   BIOS does not need to set up NB frequency and voltage
+ *
+ */
+BOOLEAN
+GetSystemNbCofVidUpdateMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    Module;
+  UINT32   Socket;
+  UINT32   NumberOfSockets;
+  BOOLEAN  IgnoredBool;
+  BOOLEAN  AtLeast1RequiresUpdate;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  AtLeast1RequiresUpdate = FALSE;
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) {
+          break;
+        }
+      }
+      if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) {
+        AtLeast1RequiresUpdate = TRUE;
+        break;
+      }
+    }
+  }
+  return AtLeast1RequiresUpdate;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket call to determine the most severe AGESA_STATUS return value after
+ * processing the power management initialization tables.
+ *
+ * This function loops through all possible socket locations, collecting any
+ * power management initialization errors that may have occurred.  These errors
+ * are transferred from the core 0s of the socket in which the errors occurred
+ * to the BSC's heap.  The BSC's heap is then searched for the most severe error
+ * that occurred, and returns it.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return     The most severe error code from power management init
+ *
+ */
+AGESA_STATUS
+GetEarlyPmErrorsMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 i;
+  UINT32 BscSocket;
+  UINT32 BscModule;
+  UINT32 BscCoreNum;
+  UINT32 Socket;
+  UINT32 NumberOfSockets;
+  AP_TASK      TaskPtr;
+  AGESA_EVENT  EventLogEntry;
+  AGESA_STATUS ReturnCode;
+  AGESA_STATUS DummyStatus;
+
+  ASSERT (IsBsp (StdHeader, &ReturnCode));
+
+  ReturnCode = AGESA_SUCCESS;
+  EventLogEntry.EventClass = AGESA_SUCCESS;
+  EventLogEntry.EventInfo = 0;
+  EventLogEntry.DataParam1 = 0;
+  EventLogEntry.DataParam2 = 0;
+  EventLogEntry.DataParam3 = 0;
+  EventLogEntry.DataParam4 = 0;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);
+
+  TaskPtr.FuncAddress.PfApTaskI = GetNextEvent;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT);
+  TaskPtr.DataTransfer.DataPtr = &EventLogEntry;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS;
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        do {
+          ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader);
+          if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
+            PutEventLog (
+              EventLogEntry.EventClass,
+              EventLogEntry.EventInfo,
+              EventLogEntry.DataParam1,
+              EventLogEntry.DataParam2,
+              EventLogEntry.DataParam3,
+              EventLogEntry.DataParam4,
+              StdHeader
+              );
+          }
+        } while (EventLogEntry.EventInfo != 0);
+      }
+    }
+  }
+
+  for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
+    if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
+      if (EventLogEntry.EventClass > ReturnCode) {
+        ReturnCode = EventLogEntry.EventClass;
+      }
+    }
+  }
+  return (ReturnCode);
+}
+
+/**
+ * Multisocket call to loop through all possible socket locations and Nb Pstates,
+ * comparing the NB frequencies to determine the slowest system and P0 frequency
+ *
+ * @param[in]  PlatformConfig      Platform profile/build option config structure.
+ * @param[out] MinSysNbFreq        NB frequency numerator for the system in MHz
+ * @param[out] MinP0NbFreq         NB frequency numerator for P0 in MHz
+ * @param[in]  StdHeader           Config handle for library and services
+ */
+VOID
+GetMinNbCofMulti (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32                 *MinSysNbFreq,
+     OUT   UINT32                 *MinP0NbFreq,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Socket;
+  UINT32                Module;
+  UINT32                CurrMinFreq;
+  UINT32                CurrMaxFreq;
+  PCI_ADDR              PciAddress;
+  AGESA_STATUS          Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  AGESA_STATUS AgesaStatus;
+
+  *MinSysNbFreq = 0xFFFFFFFF;
+  *MinP0NbFreq  = 0xFFFFFFFF;
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) {
+          break;
+        }
+      }
+
+
+      AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices,
+                                                      PlatformConfig,
+                                                      &PciAddress,
+                                                      &CurrMinFreq,
+                                                      &CurrMaxFreq,
+                                                      StdHeader);
+      ASSERT (AgesaStatus == AGESA_SUCCESS);
+      ASSERT ((CurrMinFreq != 0) && (CurrMaxFreq != 0));
+      // Determine the slowest NB Pmin frequency
+      if (CurrMinFreq < *MinSysNbFreq) {
+        *MinSysNbFreq = CurrMinFreq;
+      }
+
+      // Determine the slowest NB P0 frequency
+      if (CurrMaxFreq < *MinP0NbFreq) {
+        *MinP0NbFreq = CurrMaxFreq;
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get PCI Config Space Address for the current running core.
+ *
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[in]    StdHeader    Header for library and services.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetCurrPciAddrMulti (
+     OUT   PCI_ADDR               *PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT8        Node;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Core;
+  BOOLEAN      Result;
+  AGESA_STATUS IgnoredSts;
+
+  Result = TRUE;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+
+  ASSERT (Socket < MAX_SOCKETS);
+  ASSERT (Module < MAX_DIES);
+
+  if (GetNodeId (Socket, Module, &Node, StdHeader)) {
+    // Socket is populated
+    PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    PciAddress->Address.Device = PciAddress->Address.Device + Node;
+  } else {
+    // Socket is not populated
+    PciAddress->AddressValue = ILLEGAL_SBDFO;
+    Result = FALSE;
+  }
+
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Writes to all nodes on the executing core's socket.
+ *
+ *  @param[in]     PciAddress    The Function and Register to update
+ *  @param[in]     Mask          The bitwise AND mask to apply to the current register value
+ *  @param[in]     Data          The bitwise OR mask to apply to the current register value
+ *  @param[in]     StdHeader     Header for library and services.
+ *
+ */
+VOID
+ModifyCurrSocketPciMulti (
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 Mask,
+  IN       UINT32                 Data,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Core;
+  UINT32 LocalPciRegister;
+  AGESA_STATUS AgesaStatus;
+  PCI_ADDR Reg;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
+
+  for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
+      Reg.Address.Function = PciAddress->Address.Function;
+      Reg.Address.Register = PciAddress->Address.Register;
+      LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
+      LocalPciRegister &= Mask;
+      LocalPciRegister |= Data;
+      LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * AP task to return the next event log entry to the BSC.
+ *
+ * This function calls to the event log manager to retrieve the next error out
+ * of the heap.
+ *
+ * @param[out] EventLogEntryPtr  The AP's next event log entry
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+GetNextEvent (
+  IN OUT   VOID  *EventLogEntryPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.h
new file mode 100644
index 0000000000..3298b6b1b1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.h
@@ -0,0 +1,153 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Power Management Multisocket Functions.
+ *
+ * Contains code for doing power management for multisocket CPUs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POWER_MGMT_MULTI_SOCKET_H_
+#define _CPU_POWER_MGMT_MULTI_SOCKET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+RunCodeOnAllSystemCore0sMulti (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+VOID
+GetNumberOfSystemPmStepsPtrMulti (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetSystemNbCofMulti (
+  IN       UINT32 NbPstate,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32 *SystemNbCofNumerator,
+     OUT   UINT32 *SystemNbCofDenominator,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetSystemNbCofVidUpdateMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetMinNbCofMulti (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32                 *MinSysNbFreq,
+     OUT   UINT32                 *MinP0NbFreq,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+GetCurrPciAddrMulti (
+     OUT   PCI_ADDR               *PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+ModifyCurrSocketPciMulti (
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 Mask,
+  IN       UINT32                 Data,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+GetEarlyPmErrorsMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _CPU_POWER_MGMT_MULTI_SOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c
new file mode 100644
index 0000000000..1ed05a6fba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -0,0 +1,359 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Power Management Single Socket Functions.
+ *
+ * Contains code for doing power management for single socket CPU
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuPowerMgmtSingleSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
+ *
+ * This function will simply invoke the task on the executing core.  This must be
+ * run by the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ * @return     The severe error code from AP_TASK
+ *
+ */
+AGESA_STATUS
+RunCodeOnAllSystemCore0sSingle (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  )
+{
+  AGESA_STATUS  CalledStatus;
+
+  CalledStatus = ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
+  return CalledStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket BSC call to determine the maximum number of steps that any single
+ * processor needs to execute.
+ *
+ * This function simply returns the number of steps that the BSC needs.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+GetNumberOfSystemPmStepsPtrSingle (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  SYS_PM_TBL_STEP *Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, NumSystemSteps, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket call to determine the frequency that the northbridges must run.
+ *
+ * This function simply returns the executing core's NB frequency, and that all
+ * NB frequencies are equivalent.
+ *
+ * @param[in]  NbPstate                    NB P-state number to check (0 = fastest)
+ * @param[in]  PlatformConfig              Platform profile/build option config structure.
+ * @param[out] SystemNbCofNumerator        NB frequency numerator for the system in MHz
+ * @param[out] SystemNbCofDenominator      NB frequency denominator for the system
+ * @param[out] SystemNbCofsMatch           Whether or not all NB frequencies are equivalent
+ * @param[out] NbPstateIsEnabledOnAllCPUs  Whether or not NbPstate is valid on all CPUs
+ * @param[in]  StdHeader                   Config handle for library and services
+ *
+ * @retval     TRUE                        At least one processor has NbPstate enabled.
+ * @retval     FALSE                       NbPstate is disabled on all CPUs
+ *
+ */
+BOOLEAN
+GetSystemNbCofSingle (
+  IN       UINT32 NbPstate,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32 *SystemNbCofNumerator,
+     OUT   UINT32 *SystemNbCofDenominator,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Ignored;
+  PCI_ADDR PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+  *SystemNbCofsMatch = TRUE;
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
+                                                                         PlatformConfig,
+                                                                         &PciAddress,
+                                                                         NbPstate,
+                                                                         SystemNbCofNumerator,
+                                                                         SystemNbCofDenominator,
+                                                                         &Ignored,
+                                                                         StdHeader);
+  return *NbPstateIsEnabledOnAllCPUs;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket call to determine if the BIOS is responsible for updating the
+ * northbridge operating frequency and voltage.
+ *
+ * This function simply returns whether or not the executing core needs NB COF
+ * VID programming.
+ *
+ * @param[in]  StdHeader              Config handle for library and services
+ *
+ * @retval     TRUE    BIOS needs to set up NB frequency and voltage
+ * @retval     FALSE   BIOS does not need to set up NB frequency and voltage
+ *
+ */
+BOOLEAN
+GetSystemNbCofVidUpdateSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN   Ignored;
+  PCI_ADDR PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket call to determine the most severe AGESA_STATUS return value after
+ * processing the power management initialization tables.
+ *
+ * This function searches the event log for the most severe error and returns
+ * the status code.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return     The most severe error code from power management init
+ *
+ */
+AGESA_STATUS
+GetEarlyPmErrorsSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16       i;
+  AGESA_EVENT  EventLogEntry;
+  AGESA_STATUS ReturnCode;
+
+  ASSERT (IsBsp (StdHeader, &ReturnCode));
+
+  ReturnCode = AGESA_SUCCESS;
+  for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
+    if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
+      if (EventLogEntry.EventClass > ReturnCode) {
+        ReturnCode = EventLogEntry.EventClass;
+      }
+    }
+  }
+
+  return (ReturnCode);
+}
+
+/**
+ * Single socket call to loop through all Nb Pstates, comparing the NB frequencies
+ * to determine the slowest in the system. This routine also returns the NB P0 frequency.
+ *
+ * @param[in]  PlatformConfig      Platform profile/build option config structure.
+ * @param[out] MinSysNbFreq        NB frequency numerator for the system in MHz
+ * @param[out] MinP0NbFreq         NB frequency numerator for P0 in MHz
+ * @param[in]  StdHeader           Config handle for library and services
+ */
+VOID
+GetMinNbCofSingle (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32                 *MinSysNbFreq,
+     OUT   UINT32                 *MinP0NbFreq,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR              PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  AGESA_STATUS AgesaStatus;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices,
+                                             PlatformConfig,
+                                             &PciAddress,
+                                             MinSysNbFreq,
+                                             MinP0NbFreq,
+                                             StdHeader);
+  ASSERT (AgesaStatus == AGESA_SUCCESS);
+  ASSERT ((MinSysNbFreq != 0) && (MinP0NbFreq != 0));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get PCI Config Space Address for the current running core.
+ *
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[in]    StdHeader    Header for library and services.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetCurrPciAddrSingle (
+     OUT   PCI_ADDR               *PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Writes to all nodes on the executing core's socket.
+ *
+ *  @param[in]     PciAddress    The Function and Register to update
+ *  @param[in]     Mask          The bitwise AND mask to apply to the current register value
+ *  @param[in]     Data          The bitwise OR mask to apply to the current register value
+ *  @param[in]     StdHeader     Header for library and services.
+ *
+ */
+VOID
+ModifyCurrSocketPciSingle (
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 Mask,
+  IN       UINT32                 Data,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 LocalPciRegister;
+  PCI_ADDR Reg;
+
+  Reg.AddressValue     = MAKE_SBDFO (0, 0, 24, 0, 0);
+  Reg.Address.Function = PciAddress->Address.Function;
+  Reg.Address.Register = PciAddress->Address.Register;
+  LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
+  LocalPciRegister &= Mask;
+  LocalPciRegister |= Data;
+  LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.h
new file mode 100644
index 0000000000..3572d0763c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.h
@@ -0,0 +1,154 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Power Management Single Socket Functions.
+ *
+ * Contains code for doing power management for single socket CPU
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POWER_MGMT_SINGLE_SOCKET_H_
+#define _CPU_POWER_MGMT_SINGLE_SOCKET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+RunCodeOnAllSystemCore0sSingle (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+VOID
+GetNumberOfSystemPmStepsPtrSingle (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetSystemNbCofSingle (
+  IN       UINT32 NbPstate,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32 *SystemNbCofNumerator,
+     OUT   UINT32 *SystemNbCofDenominator,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetSystemNbCofVidUpdateSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetMinNbCofSingle (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32                 *MinSysNbFreq,
+     OUT   UINT32                 *MinP0NbFreq,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+GetCurrPciAddrSingle (
+     OUT   PCI_ADDR               *PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+ModifyCurrSocketPciSingle (
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 Mask,
+  IN       UINT32                 Data,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+GetEarlyPmErrorsSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_POWER_MGMT_SINGLE_SOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h
new file mode 100644
index 0000000000..be5f341ba7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power Management Table declarations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POWER_MGMT_SYSTEM_TABLES_H_
+#define _CPU_POWER_MGMT_SYSTEM_TABLES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define PM_EXEFLAGS_WARM_ONLY    0x00000001ul   /* Skip step if set && cold reset */
+#define PM_EXEFLAGS_COLD_ONLY    0x00000002ul   /* Skip step if set && warm reset */
+#define PM_EXEFLAGS_NOT_ON_S3    0x00000004ul   /* Skip step if S3 resume */
+#define PM_EXEFLAGS_SYSTEM_TASK  0x00000008ul   /* Future use */
+#define PM_EXEFLAGS_SERIAL_EXE   0x00000010ul   /* BSC will wait for remote core 0 to complete the step*/
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+typedef VOID F_PM_STEP_FUNCTION (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PM_STEP_FUNCTION *PF_PM_STEP_FUNCTION;
+
+
+/// A structure representing a step in a power management
+/// initialization process to be invoked at AmdInitEarly
+typedef struct {
+  UINT32  ExeFlags;                                   ///< Execution flags
+  PF_PM_STEP_FUNCTION FuncPtr;                        ///< Function pointer
+} SYS_PM_TBL_STEP;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
new file mode 100644
index 0000000000..173044c3a1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
@@ -0,0 +1,441 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 64348 $   @e \$Date: 2012-01-19 03:43:52 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_REGISTERS_H_
+#define _CPU_REGISTERS_H_
+
+#include "cpuFamRegisters.h"
+/*
+ *--------------------------------------------------------------
+ *
+ *                      M O D U L E S    U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      D E F I N I T I O N S  /  M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+#define BIT0        0x0000000000000001ull
+#define BIT1        0x0000000000000002ull
+#define BIT2        0x0000000000000004ull
+#define BIT3        0x0000000000000008ull
+#define BIT4        0x0000000000000010ull
+#define BIT5        0x0000000000000020ull
+#define BIT6        0x0000000000000040ull
+#define BIT7        0x0000000000000080ull
+#define BIT8        0x0000000000000100ull
+#define BIT9        0x0000000000000200ull
+#define BIT10       0x0000000000000400ull
+#define BIT11       0x0000000000000800ull
+#define BIT12       0x0000000000001000ull
+#define BIT13       0x0000000000002000ull
+#define BIT14       0x0000000000004000ull
+#define BIT15       0x0000000000008000ull
+#define BIT16       0x0000000000010000ull
+#define BIT17       0x0000000000020000ull
+#define BIT18       0x0000000000040000ull
+#define BIT19       0x0000000000080000ull
+#define BIT20       0x0000000000100000ull
+#define BIT21       0x0000000000200000ull
+#define BIT22       0x0000000000400000ull
+#define BIT23       0x0000000000800000ull
+#define BIT24       0x0000000001000000ull
+#define BIT25       0x0000000002000000ull
+#define BIT26       0x0000000004000000ull
+#define BIT27       0x0000000008000000ull
+#define BIT28       0x0000000010000000ull
+#define BIT29       0x0000000020000000ull
+#define BIT30       0x0000000040000000ull
+#define BIT31       0x0000000080000000ull
+#define BIT32       0x0000000100000000ull
+#define BIT33       0x0000000200000000ull
+#define BIT34       0x0000000400000000ull
+#define BIT35       0x0000000800000000ull
+#define BIT36       0x0000001000000000ull
+#define BIT37       0x0000002000000000ull
+#define BIT38       0x0000004000000000ull
+#define BIT39       0x0000008000000000ull
+#define BIT40       0x0000010000000000ull
+#define BIT41       0x0000020000000000ull
+#define BIT42       0x0000040000000000ull
+#define BIT43       0x0000080000000000ull
+#define BIT44       0x0000100000000000ull
+#define BIT45       0x0000200000000000ull
+#define BIT46       0x0000400000000000ull
+#define BIT47       0x0000800000000000ull
+#define BIT48       0x0001000000000000ull
+#define BIT49       0x0002000000000000ull
+#define BIT50       0x0004000000000000ull
+#define BIT51       0x0008000000000000ull
+#define BIT52       0x0010000000000000ull
+#define BIT53       0x0020000000000000ull
+#define BIT54       0x0040000000000000ull
+#define BIT55       0x0080000000000000ull
+#define BIT56       0x0100000000000000ull
+#define BIT57       0x0200000000000000ull
+#define BIT58       0x0400000000000000ull
+#define BIT59       0x0800000000000000ull
+#define BIT60       0x1000000000000000ull
+#define BIT61       0x2000000000000000ull
+#define BIT62       0x4000000000000000ull
+#define BIT63       0x8000000000000000ull
+
+/// CPUID related registers
+#define AMD_CPUID_FMF               0x80000001ul  // Family Model Features information
+#define AMD_CPUID_APICID_LPC_BID    0x00000001ul  // Local APIC ID, Logical Processor Count, Brand ID
+#define AMD_CPUID_L2L3Cache_L2TLB   0x80000006ul
+#define CPUID_ASSOCIATIVITY_DISABLED 0x00
+#define CPUID_ASSOCIATIVITY_1_WAY   0x01
+#define CPUID_ASSOCIATIVITY_2_WAY   0x02
+#define CPUID_ASSOCIATIVITY_4_WAY   0x04
+#define CPUID_ASSOCIATIVITY_8_WAY   0x06
+#define CPUID_ASSOCIATIVITY_16_WAY  0x08
+#define CPUID_ASSOCIATIVITY_32_WAY  0x0A
+#define CPUID_ASSOCIATIVITY_48_WAY  0x0B
+#define CPUID_ASSOCIATIVITY_64_WAY  0x0C
+#define CPUID_ASSOCIATIVITY_96_WAY  0x0D
+#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
+#define CPUID_ASSOCIATIVITY_FULLY   0x0F
+#define AMD_CPUID_TLB_L1Cache       0x80000005ul
+#define AMD_CPUID_APM               0x80000007ul
+#define LOCAL_APIC_ID               24
+#define LOGICAL_PROCESSOR_COUNT     16
+#define AMD_CPUID_ASIZE_PCCOUNT     0x80000008ul  // Address Size, Physical Core Count
+
+/// CPU Logical ID Transfer
+typedef struct {
+  UINT32         RawId;                         ///< RawID
+  UINT64         LogicalId;                     ///< LogicalID
+} CPU_LOGICAL_ID_XLAT;
+
+/// Logical CPU ID Table
+typedef struct {
+  IN       UINT32  Elements;                    ///< Number of Elements
+  IN       CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
+} LOGICAL_ID_TABLE;
+
+// MSRs
+// ------------------------
+#define MCG_CTL_P                   0x00000100ul              // bit 8  for MCG_CTL_P under MSRR
+#define MSR_MCG_CAP                 0x00000179ul
+#define MSR_MC0_CTL                 0x00000400ul
+#define MSR_MC0_STATUS              0x00000401ul
+#define MSR_MC5_STATUS              0x00000415ul
+#define MSR_MC6_STATUS              0x00000419ul
+
+#define MSR_APIC_BAR                0x0000001Bul
+
+#define CPUID_LONG_MODE_ADDR        0x80000008ul
+#define AMD_CPUID_FMF               0x80000001ul
+
+#define MSR_EXTENDED_FEATURE_EN     0xC0000080ul
+#define MSR_MC_MISC_LINK_THRESHOLD  0xC0000408ul
+#define MSR_MC_MISC_L3_THRESHOLD    0xC0000409ul
+
+/// Patch Loader Register
+typedef struct {
+  UINT64 PatchBase:32;                ///< Linear address of patch header address block
+  UINT64 SBZ:32;                      ///< Should be zero
+} PATCH_LOADER_MSR;
+
+#define MSR_SYS_CFG                 0xC0010010ul    // SYSCFG - F15 Shared
+#define MSR_TOM2                    0xC001001Dul    // TOP_MEM2 - F15 Shared
+#define MSR_MC0_CTL_MASK            0xC0010044ul    // MC0 Control Mask
+#define MSR_MC1_CTL_MASK            0xC0010045ul    // MC1 Control Mask
+#define MSR_MC2_CTL_MASK            0xC0010046ul    // MC2 Control Mask
+#define MSR_MC4_CTL_MASK            0xC0010048ul    // MC4 Control Mask
+
+#define MSR_CPUID_FEATS             0xC0011004ul    // CPUID Features
+#define MSR_CPUID_EXT_FEATS         0xC0011005ul    // CPUID Extended Features
+#define MSR_HWCR                    0xC0010015ul
+#define MSR_NB_CFG                  0xC001001Ful    // NB Config
+#define ENABLE_CF8_EXT_CFG          0x00004000ul    // [46]
+#define INIT_APIC_CPUID_LO          0x00400000ul    // [54]
+#define MSR_LS_CFG                  0xC0011020ul
+#define MSR_IC_CFG                  0xC0011021ul    // ICache Config - F15 Shared
+#define MSR_DC_CFG                  0xC0011022ul
+#define MSR_ME_CFG                  0xC0011029ul
+#define MSR_CU_CFG                  0xC0011023ul    // F15 Shared
+#define MSR_DE_CFG                  0xC0011029ul    // F15 Shared
+#define MSR_CU_CFG2                 0xC001102Aul    // F15 Shared
+#define MSR_CU_CFG3                 0xC001102Bul    // F15 Shared
+#define MSR_LS_CFG2                 0xC001102Dul
+#define MSR_IBS_OP_DATA3            0xC0011037ul
+
+
+#define MSR_CPUID_NAME_STRING0      0xC0010030ul    // First CPUID namestring register
+#define MSR_CPUID_NAME_STRING1      0xC0010031ul
+#define MSR_CPUID_NAME_STRING2      0XC0010032ul
+#define MSR_CPUID_NAME_STRING3      0xC0010033ul
+#define MSR_CPUID_NAME_STRING4      0xC0010034ul
+#define MSR_CPUID_NAME_STRING5      0xC0010035ul    // Last CPUID namestring register
+#define MSR_MMIO_Cfg_Base           0xC0010058ul    // MMIO Configuration Base Address Register
+#define MSR_BIST                    0xC0010060ul    // BIST Results register
+#define MSR_OSVW_ID_Length          0xC0010140ul
+#define MSR_OSVW_Status             0xC0010141ul
+#define MSR_NB_PERF_CTL0            0xC0010240ul
+#define MSR_NB_PERF_CTR0            0xC0010241ul
+#define MSR_NB_PERF_CTL1            0xC0010242ul
+#define MSR_NB_PERF_CTR1            0xC0010243ul
+#define MSR_NB_PERF_CTL2            0xC0010244ul
+#define MSR_NB_PERF_CTR2            0xC0010245ul
+#define MSR_NB_PERF_CTL3            0xC0010246ul
+#define MSR_NB_PERF_CTR3            0xC0010247ul
+#define MSR_PERF_CONTROL3           0xC0010003ul    // Perfromance control register number 3
+#define MSR_PERF_COUNTER3           0xC0010007ul    // Performance counter register number 3
+#define PERF_RESERVE_BIT_MASK       0x030FFFDFFFFFull  // Mask of the Performance control Reserve bits
+#define PERF_CAR_CORRUPTION_EVENT   0x040040F0E2ul    // Configure the controller to capture the
+                                                    // CAR Corruption
+// FUNC_0 registers
+// ----------------
+#define HT_LINK_FREQ_OFFSET         8           // Link HT Frequency from capability base
+#define HT_LINK_CONTROL_REG_OFFSET  4
+#define HT_LINK_TYPE_REG_OFFSET     0x18
+#define HT_LINK_EXTENDED_FREQ       0x1C
+#define HT_LINK_HOST_CAP_MAX        0x20        // HT Host Capability offsets are less than its size.
+#define HT_CAPABILITIES_POINTER     0x34
+#define NODE_ID                     0x60
+#define HT_INIT_CTRL                0x6C
+#define HT_INIT_CTRL_REQ_DIS        0x02        // [1] = ReqDis
+#define HT_INIT_COLD_RST_DET        BIT4
+#define HT_INIT_BIOS_RST_DET_0      BIT5
+#define HT_INIT_BIOS_RST_DET_1      BIT9
+#define HT_INIT_BIOS_RST_DET_2      BIT10
+#define HT_INIT_BIOS_RST_DET        BIT9 | BIT10
+#define HT_TRANS_CTRL               0x68
+#define HT_TRANS_CTRL_CPU1_EN       0x00000020ul  // [5] = CPU1 Enable
+#define HT_LINK_CONTROL_0           0x84
+#define HT_LINK_FREQ_0              0x88        // Link HT Frequency
+#define EXTENDED_NODE_ID            0x160
+#define ECS_HT_TRANS_CTRL           0x168
+#define ECS_HT_TRANS_CTRL_CPU2_EN   0x00000001ul  // [0] = CPU2 Enable
+#define ECS_HT_TRANS_CTRL_CPU3_EN   0x00000002ul  // [1] = CPU3 Enable
+#define ECS_HT_TRANS_CTRL_CPU4_EN   0x00000004ul  // [2] = CPU4 Enable
+#define ECS_HT_TRANS_CTRL_CPU5_EN   0x00000008ul  // [3] = CPU5 Enable
+
+#define CORE_CTRL                   0x1DC
+#define CORE_CTRL_CORE1_EN          0x00000002ul
+#define CORE_CTRL_CORE2_EN          0x00000004ul
+#define CORE_CTRL_CORE3_EN          0x00000008ul
+#define CORE_CTRL_CORE4_EN          0x00000010ul
+#define CORE_CTRL_CORE5_EN          0x00000020ul
+#define CORE_CTRL_CORE6_EN          0x00000040ul
+#define CORE_CTRL_CORE7_EN          0x00000080ul
+#define CORE_CTRL_CORE8_EN          0x00000100ul
+#define CORE_CTRL_CORE9_EN          0x00000200ul
+
+// FUNC_3 registers
+// ----------------
+#define HARDWARE_THERMAL_CTRL_REG       0x64
+#define SOFTWARE_THERMAL_CTRL_REG       0x68
+
+#define ACPI_PSC_0_REG                  0x80    // ACPI Power State Control Registers
+#define ACPI_PSC_4_REG                  0x84
+
+#define NB_CFG_HIGH_REG                 0x8C
+#define POWER_CTRL_MISCELLANEOUS_REG    0xA0
+#define CLOCK_POWER_TIMING_CTRL2_REG    0xDC
+#define NORTH_BRIDGE_CAPABILITIES_REG   0xE8
+#define MULTI_NODE_CPU                  29
+#define CPUID_FMR                       0xFC    // Family / Model registers
+#define DOWNCORE_CTRL                   0x190   // Downcore Control Register
+
+#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
+#define REG_HT4_PHY_OFFSET_BASE_4X180    0x180
+#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
+
+#define HTPHY_OFFSET_MASK         0xE00001FFul
+#define HTPHY_WRITE_CMD           0x40000000ul
+#define HTPHY_IS_COMPLETE_MASK    0x80000000ul
+#define HTPHY_DIRECT_MAP          0x20000000ul
+#define HTPHY_DIRECT_OFFSET_MASK  0x6000FFFFul
+
+// FUNC_5 registers
+// ----------------
+#define COMPUTE_UNIT_STATUS       0x80
+#define NORTH_BRIDGE_CAPABILITIES_2_REG  0x84
+
+
+// Misc. defines.
+#define PCI_DEV_BASE    24
+
+#define CPU_STEPPING    0x0000000Ful
+#define CPU_MODEL       0x000000F0ul
+#define CPU_EMODEL      0x000F0000ul
+#define CPU_EFAMILY     0x00F00000ul
+#define CPU_FMS_MASK    CPU_EFAMILY | CPU_EMODEL | CPU_MODEL | CPU_STEPPING
+
+#define HTPHY_SELECT        2
+#define PCI_SELECT          1
+#define MSR_SELECT          0
+
+#define LOGICAL_ID      1
+#define F_SCHEME        0
+#define DR_SCHEME       1
+#define GR_SCHEME       2
+
+#define DR_NO_STRING        0
+#define DR_SOCKET_C32       5
+#define DR_SOCKET_ASB2      4
+#define DR_SOCKET_G34       3
+#define DR_SOCKET_S1G3      2
+#define DR_SOCKET_S1G4      2
+#define DR_SOCKET_AM3       1
+#define DR_SOCKET_1207      0
+#define LN_SOCKET_FM1       2
+#define LN_SOCKET_FS1       1
+#define LN_SOCKET_FP1       0
+#define ON_SOCKET_FT1       0
+#define KR_SOCKET_FT2       0
+#define OR_SOCKET_AM3       1
+#define OR_SOCKET_G34       3
+#define OR_SOCKET_C32       5
+#define TN_SOCKET_FP2       0
+#define TN_SOCKET_FS1       1
+#define TN_SOCKET_FM2       2
+#define KV_SOCKET_FS2       1
+#define KV_SOCKET_FM3       2
+#define KB_SOCKET_FT2       0
+#define SOCKET_IGNORE       0xF
+
+#define LAPIC_BASE_ADDR_MASK    0x0000FFFFFFFFF000ull
+#define APIC_EXT_BRDCST_MASK    0x000E0000ul
+#define APIC_ENABLE_BIT         0x00000800ul
+#define LOCAL_APIC_ADDR         0xFEE00000ul
+#define INT_CMD_REG_LO          0x300
+#define INT_CMD_REG_HI          0x310
+#define REMOTE_MSG_REG          0x380
+#define REMOTE_READ_REG         0xC0
+#define APIC_ID_REG             0x20
+#define APIC20_ApicId           24
+#define CMD_REG_TO_READ_DATA    0x338
+
+#define MAX_CORE_ID_SIZE 8
+#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
+
+/*-------------------------
+ * Default definitions
+ *-------------------------
+ */
+#define DOWNCORE_MASK_SINGLE    0xFFFFFFFEul
+#define DOWNCORE_MASK_DUAL      0xFFFFFFFCul
+#define DOWNCORE_MASK_TRI       0xFFFFFFF8ul
+#define DOWNCORE_MASK_FOUR      0xFFFFFFF0ul
+#define DOWNCORE_MASK_FIVE      0xFFFFFFE0ul
+#define DOWNCORE_MASK_SIX       0xFFFFFFC0ul
+#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT  0xFFFFFFFAul
+#define DOWNCORE_MASK_TRI_COMPUTE_UNIT   0xFFFFFFEAul
+#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT  0xFFFFFFAAul
+
+#define DELIVERY_STATUS             BIT13
+#define REMOTE_READ_STAT_MASK       0x00030000ul
+#define REMOTE_DELIVERY_PENDING     0x00010000ul
+#define REMOTE_DELIVERY_DONE        0x00020000ul
+
+/*
+ * --------------------------------------------------------------------------------------
+ *
+ *             D E F I N E S    /   T Y P E D E F S   /  S T R U C T U R E S
+ *
+ * --------------------------------------------------------------------------------------
+ */
+
+/// CpuEarly param type
+typedef struct {
+  IN       UINT8                  MemInitPState;        ///< Pstate value during memory initial
+  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< Runtime configurable user options
+} AMD_CPU_EARLY_PARAMS;
+
+/// Enum - Will be used to access each structure
+///        related to each CPU family
+typedef enum {
+  REVF,                                       ///< NPT, RevF
+  REVG,                                       ///< NPT, RevG
+  DEERHOUND,                                  ///< Family 10h, Deerhound
+  GRIFFIN                                     ///< Family 11h, Griffin
+} CPU_FAMILY;
+
+/// CPUID
+typedef enum {
+  REG_EAX,                                    ///< EAX
+  REG_EBX,                                    ///< EBX
+  REG_ECX,                                    ///< ECX
+  REG_EDX                                     ///< EDX
+} CPUID_REG;
+
+#endif      // _CPU_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuServices.h
new file mode 100644
index 0000000000..bbc0e324eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuServices.h
@@ -0,0 +1,360 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Services
+ *
+ * Related to the General Services API's, but for the CPU component.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_SERVICES_H_
+#define _CPU_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+ /// WARM RESET STATE_BITS
+#define WR_STATE_COLD  00
+#define WR_STATE_RESET 01
+#define WR_STATE_EARLY 02
+#define WR_STATE_POST  03
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * The role of primary core for each compute unit can be relative to the cores' launch order.
+ *
+ * One core of a compute unit is always given the role as primary.  In different feature algorithms
+ * the core performing the primary core role can be designated relative to compute order.  In most cases,
+ * the primary core is the first core of a compute unit to execute.  However, in some cases the primary core
+ * role is associated with the last core to execute.
+ *
+ * If the launch order is strictly ascending, then first core is the lowest number and last core is highest.
+ * But if the launch order is not ascending, the first and last core follow the launch order, not the numbering order.
+ *
+ * Note that for compute units with only one core (AllCoresMapping), that core is primary for both orderings.
+ * (This includes processors without hardware compute units.)
+ *
+ */
+typedef enum {
+  FirstCoreIsComputeUnitPrimary,                   ///< the primary core role associates with the first core.
+  LastCoreIsComputeUnitPrimary,                    ///< the primary core role associates with the last core.
+  MaxComputeUnitPrimarySelector,                   ///< limit check.
+} COMPUTE_UNIT_PRIMARY_SELECTOR;
+
+/**
+ * The supported Core to Compute unit mappings.
+ */
+typedef enum {
+  AllCoresMapping,                            ///< All Cores are primary cores
+  EvenCoresMapping,                           ///< Compute units are even/odd core pairs.
+  BitMapMapping,                              ///< Currently not supported by any family, arbitrary core
+                                              ///< to compute unit mapping.
+  MaxComputeUnitMapping                       ///< Not a mapping, use for limit check.
+} COMPUTE_UNIT_MAPPING;
+
+/**
+ * Core Pair Map entry.
+ * Provide for interpreting the core pairing for the processor's compute units.
+ *
+ * HT_LIST_TERMINAL as an Enabled value means the end of a list of map structs.
+ * Zero as an Enabled value implies Compute Units are not supported by the processor
+ * and the mapping is assumed to be AllCoresMapping.
+ *
+ */
+typedef struct {
+  UINT8 Enabled;                              ///< The value of the Enabled Compute Units
+  UINT8 DualCore;                             ///< The value of the Dual Core Compute Units
+  COMPUTE_UNIT_MAPPING Mapping;               ///< When the processor module matches these values, use this mapping method.
+} CORE_PAIR_MAP;
+
+//----------------------------------------------------------------------------
+//                         CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// SYSTEM INFO
+typedef struct _SYSTEM_INFO {
+  UINT32            TotalNumberOfSockets;               ///< Total Number of Sockets
+  UINT32            TotalNumberOfCores;                 ///< Total Number Of Cores
+  UINT32            CurrentSocketNum;                   ///< Current Socket Number
+  UINT32            CurrentCoreNum;                     ///< Current Core Number
+  UINT32            CurrentCoreApicId;                  ///< Current Core Apic ID
+  UINT32            CurrentLogicalCpuId;                ///< Current Logical CPU ID
+} SYSTEM_INFO;
+
+/// WARM_RESET_REQUEST
+typedef struct _WARM_RESET_REQUEST {
+  UINT8             RequestBit:1;                       ///< Request Bit
+  UINT8             StateBits:2;                        ///< State Bits
+  UINT8             PostStage:2;                        ///< Post Stage
+  UINT8             Reserved:(8 - 5);                   ///< Reserved
+} WARM_RESET_REQUEST;
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GetCurrentNodeNum (
+     OUT   UINT32 *Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get the current Platform's number of Sockets, regardless of how many are populated.
+ *
+ */
+UINT32
+GetPlatformNumberOfSockets ( VOID );
+
+/**
+ * Get the number of Modules to check presence in each Processor.
+ *
+ */
+UINT32
+GetPlatformNumberOfModules ( VOID );
+
+BOOLEAN
+IsProcessorPresent (
+  IN       UINT32            Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * For a specific Node, get its Socket and Module ids.
+ *
+ */
+BOOLEAN
+GetSocketModuleOfNode (
+  IN       UINT32    Node,
+     OUT   UINT32    *Socket,
+     OUT   UINT32    *Module,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get the current core's Processor APIC Index.
+ */
+UINT32
+GetProcessorApicIndex (
+  IN       UINT32            Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Provide the number of installed processors (not Nodes! and not Sockets!)
+ */
+UINT32
+GetNumberOfProcessors (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetActiveCoresInCurrentSocket (
+     OUT   UINT32 *CoreCount,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetActiveCoresInGivenSocket (
+  IN       UINT32             Socket,
+     OUT   UINT32             *CoreCount,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINTN
+GetActiveCoresInCurrentModule (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINTN
+GetNumberOfCompUnitsInCurrentModule (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetGivenModuleCoreRange (
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   UINT32            *LowCore,
+     OUT   UINT32            *HighCore,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetCurrentCore (
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetCurrentNodeAndCore (
+     OUT   UINT32 *Node,
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+IsCurrentCorePrimary (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetApMailbox (
+     OUT   UINT32               *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+CacheApMailbox (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+UINTN
+GetSystemDegree (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+GetNodeId (
+  IN       UINT32  SocketId,
+  IN       UINT32  ModuleId,
+     OUT   UINT8   *NodeId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+WaitMicroseconds (
+  IN       UINT32 Microseconds,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get the compute unit mapping algorithm.
+ */
+COMPUTE_UNIT_MAPPING
+GetComputeUnitMapping (
+  IN      AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+/**
+ * Does the current core have the role of primary core for the compute unit?
+ */
+BOOLEAN
+IsCorePairPrimary (
+  IN       COMPUTE_UNIT_PRIMARY_SELECTOR Selector,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+/**
+ * Are the two specified cores shared in a compute unit?
+ */
+BOOLEAN
+AreCoresPaired (
+  IN       UINT32  Socket,
+  IN       UINT32  Module,
+  IN       UINT32  CoreA,
+  IN       UINT32  CoreB,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+VOID
+GetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  );
+
+BOOLEAN
+IsWarmReset (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CheckBistStatus (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetWarmResetAtEarly (
+  IN      UINT32            Data,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+);
+
+#endif  // _CPU_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
new file mode 100644
index 0000000000..a7af298a32
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
@@ -0,0 +1,261 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Warm Reset Implementation.
+ *
+ * Implement Warm Reset Interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_CPUWARMRESET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will set the CPU register warm reset bits.
+ *
+ *    Note: This function will be called by UEFI BIOS's
+ *    The UEFI wrapper code should register this function, to be called back later point
+ *    in time, before the wrapper code does warm reset.
+ *
+ *    @param[in] StdHeader Config handle for library and services
+ *    @param[in] Request   Indicate warm reset status
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+SetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will get the CPU register warm reset bits.
+ *
+ *    Note: This function will be called by UEFI BIOS's
+ *    The UEFI wrapper code should register this function, to be called back later point
+ *    in time, before the wrapper code does warm reset.
+ *
+ *    @param[in] StdHeader Config handle for library and services
+ *    @param[out] Request   Indicate warm reset status
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+GetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
+
+  switch (StdHeader->Func) {
+  case AMD_INIT_RESET:
+    Request->PostStage = (UINT8) WR_STATE_RESET;
+    break;
+  case AMD_INIT_EARLY:
+    Request->PostStage = (UINT8) WR_STATE_EARLY;
+    break;
+  case AMD_INIT_POST:
+    // Fall through to default case
+  default:
+    Request->PostStage = (UINT8) WR_STATE_POST;
+    break;
+  }
+}
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S - (AGESA ONLY)
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is this boot a warm reset?
+ *
+ * This function reads the CPU register warm reset bit that is preserved after a warm reset.
+ * Which in fact gets set before issuing warm reset.  We just use the BSP's register always.
+ *
+ * @param[in]       StdHeader       Config handle for library and services
+ *
+ * @retval      TRUE            Warm Reset
+ * @retval      FALSE           Not Warm Reset
+ *
+ */
+BOOLEAN
+IsWarmReset (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 PostStage;
+  WARM_RESET_REQUEST Request;
+  BOOLEAN  WarmReset;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  FamilySpecificServices = NULL;
+
+  switch (StdHeader->Func) {
+  case AMD_INIT_RESET:
+    PostStage = WR_STATE_RESET;
+    break;
+  case AMD_INIT_EARLY:
+    PostStage = WR_STATE_EARLY;
+    break;
+  case AMD_INIT_POST:
+  default:
+    PostStage = WR_STATE_POST;
+    break;
+  }
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
+
+  if (Request.StateBits >= PostStage) {
+    WarmReset = TRUE;
+  } else {
+    WarmReset = FALSE;
+  }
+
+  return WarmReset;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will set the CPU register warm reset bits at AmdInitEarly if it is
+ *    currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
+ *    and the StateBits to (current poststage - 1)
+ *
+ *    @param[in] Data      The table data value (unused in this routine)
+ *    @param[in] StdHeader Config handle for library and services
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+SetWarmResetAtEarly (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  WARM_RESET_REQUEST Request;
+
+  if (!IsWarmReset (StdHeader)) {
+    GetWarmResetFlag (StdHeader, &Request);
+
+    Request.RequestBit = TRUE;
+    Request.StateBits = (Request.PostStage - 1);
+
+    SetWarmResetFlag (StdHeader, &Request);
+  }
+}
+
+/*----------------------------------------------------------------------------------------
+ *                            L O C A L    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
new file mode 100644
index 0000000000..a59a45efdf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -0,0 +1,911 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_HEAPMANAGER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT64
+STATIC
+HeapGetCurrentBase (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+DeleteFreeSpaceNode (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            OffsetOfDeletedNode
+  );
+
+VOID
+STATIC
+InsertFreeSpaceNode (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            OffsetOfInsertNode
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  This function initializes the heap for each CPU core.
+ *
+ *  Check for already initialized.  If not, determine offset of local heap in CAS and
+ *  setup initial heap markers and bookkeeping status.  Initialize a couple heap items
+ *  all cores need, for convenience.  Currently these are caching the AP mailbox info and
+ *  an initial event log.
+ *
+ *  @param[in]  StdHeader          Handle of Header for calling lib functions and services.
+ *
+ *  @retval     AGESA_SUCCESS      This core's heap is initialized
+ *  @retval     AGESA_FATAL        This core's heap cannot be initialized due to any reasons below:
+ *                                 - current processor family cannot be identified.
+ *
+ */
+AGESA_STATUS
+HeapManagerInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // First Time Initialization
+  // Note: First 16 bytes of buffer is reserved for Heap Manager use
+  UINT16                HeapAlreadyInitSizeDword;
+  UINT32                HeapAlreadyRead;
+  UINT8                 L2LineSize;
+  UINT8                 *HeapBufferPtr;
+  UINT8                 *HeapInitPtr;
+  UINT32                *HeapDataPtr;
+  UINT64                MsrData;
+  UINT64                MsrMask;
+  UINT8                 Ignored;
+  CPUID_DATA            CpuId;
+  BUFFER_NODE           *FreeSpaceNode;
+  CACHE_INFO            *CacheInfoPtr;
+  AGESA_STATUS          IgnoredSts;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+
+  // Check whether this is a known processor family.
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Family == 0) && (CpuFamilyRevision.Revision == 0)) {
+    IDS_ERROR_TRAP;
+    return AGESA_FATAL;
+  }
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
+  HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+
+  // Check whether the heap manager is already initialized
+  LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
+  if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) {
+    LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
+    if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) {
+      if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) {
+        // This is not a bug, there are multiple premem basic entry points,
+        // and each will call heap init to make sure create struct will succeed.
+        // If that is later deemed a problem, there needs to be a reasonable test
+        // for the calling code to make to determine if it needs to init heap or not.
+        // In the mean time, add this to the event log
+        PutEventLog (AGESA_SUCCESS,
+                    CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED,
+                    0, 0, 0, 0, StdHeader);
+        return AGESA_SUCCESS;
+      }
+    }
+  }
+
+  // Set variable MTRR base and mask
+  MsrData = ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask);
+  MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
+
+  MsrData |= 0x06;
+  LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
+  LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrMask, StdHeader);
+
+  // Set top of memory to a temp value
+  MsrData = (UINT64) (AMD_TEMP_TOM);
+  LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
+
+  // Enable variable MTTRs
+  LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
+  MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
+  LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
+
+  // Initialize Heap Space
+  // BIOS may store to a line only after it has been allocated by a load
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader);
+  L2LineSize = (UINT8) (CpuId.ECX_Reg);
+  HeapInitPtr = HeapBufferPtr ;
+  for (HeapAlreadyRead = 0; HeapAlreadyRead < AMD_HEAP_SIZE_PER_CORE;
+      (HeapAlreadyRead = HeapAlreadyRead + L2LineSize)) {
+    Ignored = *HeapInitPtr;
+    HeapInitPtr += L2LineSize;
+  }
+
+  HeapDataPtr = (UINT32 *) HeapBufferPtr;
+  for (HeapAlreadyInitSizeDword = 0; HeapAlreadyInitSizeDword < AMD_HEAP_SIZE_DWORD_PER_CORE; HeapAlreadyInitSizeDword++) {
+    *HeapDataPtr = 0;
+    HeapDataPtr++;
+  }
+
+  // Note: We are reserving the first 16 bytes for Heap Manager use
+  // UsedSize indicates the size of heap spaced is used for HEAP_MANAGER, BUFFER_NODE,
+  //   Pad for 16-byte alignment, buffer data, and IDS SENTINEL.
+  // FirstActiveBufferOffset is initalized as invalid heap offset, AMD_HEAP_INVALID_HEAP_OFFSET.
+  // FirstFreeSpaceOffset is initalized as the byte right after HEAP_MANAGER header.
+  // Then we set Signature of HEAP_MANAGER header as valid, HEAP_SIGNATURE_VALID.
+  ((HEAP_MANAGER*) HeapBufferPtr)->UsedSize = sizeof (HEAP_MANAGER);
+  ((HEAP_MANAGER*) HeapBufferPtr)->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
+  ((HEAP_MANAGER*) HeapBufferPtr)->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
+  ((HEAP_MANAGER*) HeapBufferPtr)->Signature = HEAP_SIGNATURE_VALID;
+  // Create free space link
+  FreeSpaceNode = (BUFFER_NODE *) (HeapBufferPtr + sizeof (HEAP_MANAGER));
+  FreeSpaceNode->BufferSize = AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE);
+  FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+
+  StdHeader->HeapStatus = HEAP_LOCAL_CACHE;
+  if (!IsBsp (StdHeader, &IgnoredSts)) {
+    // The BSP's hardware mailbox has not been initialized, so only APs
+    // can do this at this point.
+    CacheApMailbox (StdHeader);
+  }
+  EventLogInitialization (StdHeader);
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap
+ *
+ * This function will allocate new buffer either by using internal 'AGESA' heapmanager
+ * or by using externa (IBV) heapmanager. This function will also determine if whether or not
+ * there is enough space for the new structure. If so, it will zero out the buffer,
+ * and return a pointer to the region.
+ *
+ * @param[in,out]  AllocateHeapParams structure pointer containing the size of the
+ *                                   desired new region, its handle, and the
+ *                                   return pointer.
+ * @param[in,out]  StdHeader         Config handle for library and services.
+ *
+ * @retval         AGESA_SUCCESS     No error
+ * @retval         AGESA_BOUNDS_CHK  Handle already exists, or not enough
+ *                                   free space
+ * @retval         AGESA_UNSUPPORTED Do not support this kind of heap allocation
+ * @retval         AGESA_ERROR       Heap is invaild
+ *
+ */
+AGESA_STATUS
+HeapAllocateBuffer (
+  IN OUT   ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *BaseAddress;
+  UINT8  AlignTo16Byte;
+  UINT8  CalloutFcnData;
+  UINT32 RemainSize;
+  UINT32 OffsetOfSplitNode;
+  UINT32 OffsetOfNode;
+  HEAP_MANAGER *HeapManager;
+  BUFFER_NODE *FreeSpaceNode;
+  BUFFER_NODE *SplitFreeSpaceNode;
+  BUFFER_NODE *CurrentBufferNode;
+  BUFFER_NODE *NewBufferNode;
+  AGESA_BUFFER_PARAMS  AgesaBuffer;
+
+  ASSERT (StdHeader != NULL);
+  if (AllocateHeapParams->Persist == HEAP_RUNTIME_SYSTEM_MEM) {
+    ASSERT (StdHeader->HeapStatus == HEAP_SYSTEM_MEM);
+    if (StdHeader->HeapStatus != HEAP_SYSTEM_MEM) {
+      return AGESA_UNSUPPORTED;
+    }
+  }
+
+  // At this stage we will decide to either use external (IBV) heap manger
+  // or internal (AGESA) heap manager.
+
+  // If (HeapStatus == HEAP_SYSTEM_MEM), then use the call function to call
+  // external heap manager
+  if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
+    AgesaBuffer.StdHeader = *StdHeader;
+    AgesaBuffer.BufferHandle = AllocateHeapParams->BufferHandle;
+    AgesaBuffer.BufferLength = AllocateHeapParams->RequestedBufferSize;
+
+    if (AllocateHeapParams->Persist == HEAP_RUNTIME_SYSTEM_MEM) {
+      CalloutFcnData = HEAP_CALLOUT_RUNTIME;
+    } else {
+      CalloutFcnData = HEAP_CALLOUT_BOOTTIME;
+    }
+    AGESA_TESTPOINT (TpIfBeforeAllocateHeapBuffer, StdHeader);
+    if (AgesaAllocateBuffer (CalloutFcnData, &AgesaBuffer) != AGESA_SUCCESS) {
+      AllocateHeapParams->BufferPtr = NULL;
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpIfAfterAllocateHeapBuffer, StdHeader);
+
+    AllocateHeapParams->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer);
+    return AGESA_SUCCESS;
+  }
+
+  // If (StdHeader->HeapStatus != HEAP_SYSTEM_MEM), then allocated buffer
+  // using following AGESA Heap Manager code.
+
+  // Buffer pointer is NULL unless we return a buffer.
+  AlignTo16Byte = 0;
+  AllocateHeapParams->BufferPtr = NULL;
+  AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL;
+
+  // Get base address
+  BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr;
+  HeapManager = (HEAP_MANAGER *) BaseAddress;
+
+  // Check Heap database is valid
+  if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
+    // The base address in StdHeader is incorrect, get base address by itself
+    BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+    HeapManager = (HEAP_MANAGER *) BaseAddress;
+    if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
+      // Heap is not available, ASSERT here
+      ASSERT (FALSE);
+      return AGESA_ERROR;
+    }
+    StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+  }
+
+  // Allocate
+  CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + sizeof (HEAP_MANAGER));
+  // If there already has been a heap with the incoming BufferHandle, we return AGESA_BOUNDS_CHK.
+  if (HeapManager->FirstActiveBufferOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
+    CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + HeapManager->FirstActiveBufferOffset);
+    while (CurrentBufferNode->OffsetOfNextNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
+      if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) {
+      PutEventLog (AGESA_BOUNDS_CHK,
+                   CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED,
+                   AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader);
+        return AGESA_BOUNDS_CHK;
+      } else {
+        CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + CurrentBufferNode->OffsetOfNextNode);
+      }
+    }
+    if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) {
+      PutEventLog (AGESA_BOUNDS_CHK,
+                   CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED,
+                   AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader);
+      return AGESA_BOUNDS_CHK;
+    }
+  }
+
+  // Find the buffer size that first matches the requested buffer size (i.e. the first free buffer of greater size).
+  OffsetOfNode = HeapManager->FirstFreeSpaceOffset;
+  FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode);
+  while (OffsetOfNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
+    AlignTo16Byte = (UINT8) ((0x10 - (((UINTN) (VOID *) FreeSpaceNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
+    AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize + AlignTo16Byte);
+    if (FreeSpaceNode->BufferSize >= AllocateHeapParams->RequestedBufferSize) {
+      break;
+    }
+    AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize - AlignTo16Byte);
+    OffsetOfNode = FreeSpaceNode->OffsetOfNextNode;
+    FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode);
+  }
+  if (OffsetOfNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+    // We don't find any free space buffer that matches the requested buffer size.
+    PutEventLog (AGESA_BOUNDS_CHK,
+                 CPU_ERROR_HEAP_IS_FULL,
+                 AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader);
+    return AGESA_BOUNDS_CHK;
+  } else {
+    // We find one matched free space buffer.
+    DeleteFreeSpaceNode (StdHeader, OffsetOfNode);
+    NewBufferNode = FreeSpaceNode;
+    // Add new buffer node to the buffer chain
+    if (HeapManager->FirstActiveBufferOffset == AMD_HEAP_INVALID_HEAP_OFFSET) {
+      HeapManager->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
+    } else {
+      CurrentBufferNode->OffsetOfNextNode = OffsetOfNode;
+    }
+    // New buffer size
+    RemainSize = FreeSpaceNode->BufferSize - AllocateHeapParams->RequestedBufferSize;
+    if (RemainSize > sizeof (BUFFER_NODE)) {
+      NewBufferNode->BufferSize = AllocateHeapParams->RequestedBufferSize;
+      OffsetOfSplitNode = OffsetOfNode + sizeof (BUFFER_NODE) + NewBufferNode->BufferSize;
+      SplitFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfSplitNode);
+      SplitFreeSpaceNode->BufferSize = RemainSize - sizeof (BUFFER_NODE);
+      InsertFreeSpaceNode (StdHeader, OffsetOfSplitNode);
+    } else {
+      // Remain size is less than BUFFER_NODE, we use whole size instead of requested size.
+      NewBufferNode->BufferSize = FreeSpaceNode->BufferSize;
+    }
+  }
+
+  // Initialize BUFFER_NODE structure of NewBufferNode
+  NewBufferNode->BufferHandle = AllocateHeapParams->BufferHandle;
+  if ((AllocateHeapParams->Persist == HEAP_TEMP_MEM) || (AllocateHeapParams->Persist == HEAP_SYSTEM_MEM)) {
+    NewBufferNode->Persist = AllocateHeapParams->Persist;
+  } else {
+    NewBufferNode->Persist = HEAP_LOCAL_CACHE;
+  }
+  NewBufferNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+  NewBufferNode->PadSize = AlignTo16Byte;
+
+  // Clear to 0x00
+  LibAmdMemFill ((VOID *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE)), 0x00, NewBufferNode->BufferSize, StdHeader);
+
+  // Debug feature
+  SET_SENTINEL_BEFORE (NewBufferNode, AlignTo16Byte);
+  SET_SENTINEL_AFTER (NewBufferNode);
+
+  // Update global variables
+  HeapManager->UsedSize += NewBufferNode->BufferSize + sizeof (BUFFER_NODE);
+
+  // Now fill in the incoming structure
+  AllocateHeapParams->BufferPtr = (UINT8 *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte);
+  AllocateHeapParams->RequestedBufferSize -= (NUM_OF_SENTINEL * SIZE_OF_SENTINEL + AlignTo16Byte);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Deallocates a previously allocated buffer in the heap
+ *
+ * This function will deallocate buffer either by using internal 'AGESA' heapmanager
+ * or by using externa (IBV) heapmanager.
+ *
+ * @param[in]      BufferHandle      Handle of the buffer to free.
+ * @param[in]      StdHeader         Config handle for library and services.
+ *
+ * @retval         AGESA_SUCCESS     No error
+ * @retval         AGESA_BOUNDS_CHK  Handle does not exist on the heap
+ *
+ */
+AGESA_STATUS
+HeapDeallocateBuffer (
+  IN       UINT32 BufferHandle,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *BaseAddress;
+  UINT32 NodeSize;
+  UINT32 OffsetOfFreeSpaceNode;
+  UINT32 OffsetOfPreviousNode;
+  UINT32 OffsetOfCurrentNode;
+  BOOLEAN HeapLocateFlag;
+  HEAP_MANAGER *HeapManager;
+  BUFFER_NODE *CurrentNode;
+  BUFFER_NODE *PreviousNode;
+  BUFFER_NODE *FreeSpaceNode;
+  AGESA_BUFFER_PARAMS  AgesaBuffer;
+
+  ASSERT (StdHeader != NULL);
+
+  HeapLocateFlag = TRUE;
+  BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr;
+  HeapManager = (HEAP_MANAGER *) BaseAddress;
+
+  // Check Heap database is valid
+  if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
+    // The base address in StdHeader is incorrect, get base address by itself
+    BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+    HeapManager = (HEAP_MANAGER *) BaseAddress;
+    if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
+      // Heap is not available, ASSERT here
+      ASSERT (FALSE);
+      return AGESA_ERROR;
+    }
+    StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+  }
+
+  OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+  OffsetOfCurrentNode =  HeapManager->FirstActiveBufferOffset;
+  CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+
+  // Locate heap
+  if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
+    if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+      HeapLocateFlag = FALSE;
+    } else {
+      while (CurrentNode->BufferHandle != BufferHandle) {
+        if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+          HeapLocateFlag = FALSE;
+          break;
+        } else {
+          OffsetOfPreviousNode = OffsetOfCurrentNode;
+          OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode;
+          CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+        }
+      }
+    }
+  } else {
+    HeapLocateFlag = FALSE;
+  }
+
+  if (HeapLocateFlag == TRUE) {
+    // CurrentNode points to the buffer which wanted to be deallocated.
+    // Remove deallocated heap from active buffer chain.
+    if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+      HeapManager->FirstActiveBufferOffset = CurrentNode->OffsetOfNextNode;
+    } else {
+      PreviousNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode);
+      PreviousNode->OffsetOfNextNode = CurrentNode->OffsetOfNextNode;
+    }
+    // Now, CurrentNode become a free space node.
+    HeapManager->UsedSize -= CurrentNode->BufferSize + sizeof (BUFFER_NODE);
+    // Loop free space chain to see if any free space node is just before/after CurrentNode, then merge them.
+    OffsetOfFreeSpaceNode = HeapManager->FirstFreeSpaceOffset;
+    FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode);
+    while (OffsetOfFreeSpaceNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
+      if ((OffsetOfFreeSpaceNode + sizeof (BUFFER_NODE) + FreeSpaceNode->BufferSize) == OffsetOfCurrentNode) {
+        DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode);
+        NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE);
+        OffsetOfCurrentNode = OffsetOfFreeSpaceNode;
+        CurrentNode = FreeSpaceNode;
+        CurrentNode->BufferSize = NodeSize;
+      } else if (OffsetOfFreeSpaceNode == (OffsetOfCurrentNode + sizeof (BUFFER_NODE) + CurrentNode->BufferSize)) {
+        DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode);
+        NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE);
+        CurrentNode->BufferSize = NodeSize;
+      }
+      OffsetOfFreeSpaceNode = FreeSpaceNode->OffsetOfNextNode;
+      FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode);
+    }
+    InsertFreeSpaceNode (StdHeader, OffsetOfCurrentNode);
+    return AGESA_SUCCESS;
+  } else {
+    // If HeapStatus == HEAP_SYSTEM_MEM, try callout function
+    if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
+      AgesaBuffer.StdHeader = *StdHeader;
+      AgesaBuffer.BufferHandle = BufferHandle;
+
+      AGESA_TESTPOINT (TpIfBeforeDeallocateHeapBuffer, StdHeader);
+      if (AgesaDeallocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+        return AGESA_ERROR;
+      }
+      AGESA_TESTPOINT (TpIfAfterDeallocateHeapBuffer, StdHeader);
+
+      return AGESA_SUCCESS;
+    }
+    // If we are still unable to locate the buffer handle, return AGESA_BOUNDS_CHK
+    if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
+      PutEventLog (AGESA_BOUNDS_CHK,
+                 CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT,
+                 BufferHandle, 0, 0, 0, StdHeader);
+    } else {
+      ASSERT (FALSE);
+    }
+    return AGESA_BOUNDS_CHK;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locates a previously allocated buffer on the heap.
+ *
+ * This function searches the heap for a buffer with the desired handle, and
+ * returns a pointer to the buffer.
+ *
+ * @param[in,out]  LocateHeap     Structure containing the buffer's handle,
+ *                                   and the return pointer.
+ * @param[in]      StdHeader         Config handle for library and services.
+ *
+ * @retval         AGESA_SUCCESS     No error
+ * @retval         AGESA_BOUNDS_CHK  Handle does not exist on the heap
+ *
+ */
+AGESA_STATUS
+HeapLocateBuffer (
+  IN OUT   LOCATE_HEAP_PTR *LocateHeap,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *BaseAddress;
+  UINT8  AlignTo16Byte;
+  UINT32 OffsetOfCurrentNode;
+  BOOLEAN HeapLocateFlag;
+  HEAP_MANAGER *HeapManager;
+  BUFFER_NODE *CurrentNode;
+  AGESA_BUFFER_PARAMS  AgesaBuffer;
+
+  ASSERT (StdHeader != NULL);
+
+  HeapLocateFlag = TRUE;
+  BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr;
+  HeapManager = (HEAP_MANAGER *) BaseAddress;
+
+  // Check Heap database is valid
+  if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
+    // The base address in StdHeader is incorrect, get base address by itself
+    BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+    HeapManager = (HEAP_MANAGER *) BaseAddress;
+    if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
+      // Heap is not available, ASSERT here
+      ASSERT (FALSE);
+      return AGESA_ERROR;
+    }
+    StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+  }
+  OffsetOfCurrentNode =  HeapManager->FirstActiveBufferOffset;
+  CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+
+  // Find buffer using internal heap manager
+  // Locate the heap using handle = LocateHeap-> BufferHandle
+  // If HeapStatus != HEAP_SYSTEM_ MEM
+  if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
+    if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+      HeapLocateFlag = FALSE;
+    } else {
+      while (CurrentNode->BufferHandle != LocateHeap->BufferHandle) {
+        if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+          HeapLocateFlag = FALSE;
+          break;
+        } else {
+          OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode;
+          CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+        }
+      }
+    }
+  } else {
+    HeapLocateFlag = FALSE;
+  }
+
+  if (HeapLocateFlag) {
+    AlignTo16Byte = CurrentNode->PadSize;
+    LocateHeap->BufferPtr = (UINT8 *) ((UINT8 *) CurrentNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte);
+    LocateHeap->BufferSize = CurrentNode->BufferSize - NUM_OF_SENTINEL * SIZE_OF_SENTINEL - AlignTo16Byte;
+    return AGESA_SUCCESS;
+  } else {
+    // If HeapStatus == HEAP_SYSTEM_MEM, try callout function
+    if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
+      AgesaBuffer.StdHeader = *StdHeader;
+      AgesaBuffer.BufferHandle = LocateHeap->BufferHandle;
+
+      AGESA_TESTPOINT (TpIfBeforeLocateHeapBuffer, StdHeader);
+      if (AgesaLocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+        LocateHeap->BufferPtr = NULL;
+        return AGESA_ERROR;
+      }
+      LocateHeap->BufferSize = AgesaBuffer.BufferLength;
+      AGESA_TESTPOINT (TpIfAfterLocateHeapBuffer, StdHeader);
+
+      LocateHeap->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer);
+      return AGESA_SUCCESS;
+    }
+
+    // If we are still unable to deallocate the buffer handle, return AGESA_BOUNDS_CHK
+    LocateHeap->BufferPtr = NULL;
+    LocateHeap->BufferSize = 0;
+    if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
+      PutEventLog (AGESA_BOUNDS_CHK,
+                   CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT,
+                   LocateHeap->BufferHandle, 0, 0, 0, StdHeader);
+    } else {
+      ASSERT (FALSE);
+    }
+    return AGESA_BOUNDS_CHK;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the heap base address
+ *
+ * This function will try to locate heap from cache, temp memory, main memory.
+ * The heap signature will be checked for validity on each possible location.
+ * Firstly, try if heap base is in cache by calling the function HeapGetCurrentBase.
+ * Secondly, try if heap base is temp memory by UserOptoions.CfgHeapDramAddress.
+ * Thirdly, try if heap base is in main memory by doing a buffer locate with buffer handle
+ * AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
+ * If no valid heap signature is found in each possible location above, a NULL pointer is returned.
+ *
+ * @param[in]      StdHeader      Config handle for library and services.
+ *
+ * @return         Heap base address of the executing core's heap.
+ *
+ */
+UINT64
+HeapGetBaseAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 BaseAddress;
+  HEAP_MANAGER *HeapManager;
+  AGESA_BUFFER_PARAMS AgesaBuffer;
+
+  // Firstly, we try to see if heap is in cache
+  BaseAddress = HeapGetCurrentBase (StdHeader);
+  HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress;
+
+  if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) &&
+      (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) &&
+      (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) {
+    // Secondly, we try to see if heap is in temp memory
+    BaseAddress = UserOptions.CfgHeapDramAddress;
+    HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress;
+    if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
+      // Thirdly, we try to see if heap in main memory
+      // by locating with external buffer manager (IBV)
+      AgesaBuffer.StdHeader = *StdHeader;
+      AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
+      if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) {
+        BaseAddress = (UINT64) (UINTN) AgesaBuffer.BufferPointer;
+        HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress;
+        if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
+          // No valid heap signature ever found, return a NULL pointer
+          BaseAddress = (UINT64) (UINTN) NULL;
+        }
+      } else {
+        // No heap buffer is allocated by external manager (IBV), return a NULL pointer
+        BaseAddress = (UINT64) (UINTN) NULL;
+      }
+    }
+  }
+
+  return BaseAddress;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DeleteFreeSpaceNode
+ *
+ *  Description:
+ *    Delete a free space node from free space chain
+ *
+ *  Parameters:
+ * @param[in]      StdHeader             Config handle for library and services.
+ * @param[in]      OffsetOfDeletedNode   Offset of deleted node.
+ *
+ *  Processing:
+ *
+ */
+VOID
+STATIC
+DeleteFreeSpaceNode (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            OffsetOfDeletedNode
+  )
+{
+  UINT8 *BaseAddress;
+  UINT32 OffsetOfPreviousNode;
+  UINT32 OffsetOfCurrentNode;
+  HEAP_MANAGER *HeapManager;
+  BUFFER_NODE *CurrentFreeSpaceNode;
+  BUFFER_NODE *PreviousFreeSpaceNode;
+
+
+  BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr;
+  HeapManager = (HEAP_MANAGER *) BaseAddress;
+
+  OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+  OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset;
+  //
+  // After AmdInitEnv, there is no free space provided for HeapAllocateBuffer.
+  // Hence if the FirstFreeSpaceOffset is AMD_HEAP_INVALID_HEAP_OFFSET, then
+  // no need to do more on delete node.
+  //
+  if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
+    CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+    while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && (OffsetOfCurrentNode != OffsetOfDeletedNode)) {
+      OffsetOfPreviousNode = OffsetOfCurrentNode;
+      OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode;
+      CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+    }
+    if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
+      if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+        HeapManager->FirstFreeSpaceOffset = CurrentFreeSpaceNode->OffsetOfNextNode;
+      } else {
+        PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode);
+        PreviousFreeSpaceNode->OffsetOfNextNode = CurrentFreeSpaceNode->OffsetOfNextNode;
+      }
+    }
+  }
+  return;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  InsertFreeSpaceNode
+ *
+ *  Description:
+ *    Insert a free space node to free space chain, size order
+ *
+ *  Parameters:
+ * @param[in]      StdHeader             Config handle for library and services.
+ * @param[in]      OffsetOfInsertNode    Offset of inserted node.
+ *
+ *  Processing:
+ *
+ */
+VOID
+STATIC
+InsertFreeSpaceNode (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            OffsetOfInsertNode
+  )
+{
+  UINT8 *BaseAddress;
+  UINT32 OffsetOfPreviousNode;
+  UINT32 OffsetOfCurrentNode;
+  HEAP_MANAGER *HeapManager;
+  BUFFER_NODE *CurrentFreeSpaceNode;
+  BUFFER_NODE *PreviousFreeSpaceNode;
+  BUFFER_NODE *InsertedFreeSpaceNode;
+
+  BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr;
+  HeapManager = (HEAP_MANAGER *) BaseAddress;
+
+  OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+  OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset;
+  CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+  InsertedFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode);
+  while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) &&
+         (CurrentFreeSpaceNode->BufferSize < InsertedFreeSpaceNode->BufferSize)) {
+    OffsetOfPreviousNode = OffsetOfCurrentNode;
+    OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode;
+    CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
+  }
+  InsertedFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode;
+  if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
+    HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode;
+  } else {
+    PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode);
+    PreviousFreeSpaceNode->OffsetOfNextNode = OffsetOfInsertNode;
+  }
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the base address of the executing core's heap.
+ *
+ * This function uses the executing core's socket/core numbers to determine
+ * where it's heap should be located.
+ *
+ * @param[in]      StdHeader      Config handle for library and services.
+ *
+ * @return         A pointer to the executing core's heap.
+ *
+ */
+UINT64
+STATIC
+HeapGetCurrentBase (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32      SystemCoreNumber;
+  UINT64      ReturnPtr;
+  AGESA_STATUS          IgnoredStatus;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    ReturnPtr = AMD_HEAP_START_ADDRESS;
+  } else {
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+
+    SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader);
+    ASSERT (SystemCoreNumber != 0);
+    ASSERT (SystemCoreNumber < 64);
+    ReturnPtr = ((SystemCoreNumber * AMD_HEAP_SIZE_PER_CORE) + AMD_HEAP_START_ADDRESS);
+  }
+  ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
+  return ReturnPtr;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h
new file mode 100644
index 0000000000..9bbb6524e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h
@@ -0,0 +1,274 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 64574 $   @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _HEAP_MANAGER_H_
+#define _HEAP_MANAGER_H_
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define AMD_MTRR_VARIABLE_BASE0 0x200
+#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
+#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
+
+#define AMD_HEAP_START_ADDRESS  0x400000ul
+#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
+#define AMD_HEAP_SIZE_PER_CORE  0x010000ul
+#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
+#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
+#define AMD_HEAP_SIZE_DWORD_PER_CORE  (AMD_HEAP_SIZE_PER_CORE / 4)
+
+#define AMD_TEMP_TOM            0x20000000ul  // Set TOM to 512 MB (temporary value)
+#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul    // bit 20
+
+#define AMD_HEAP_RAM_ADDRESS    0xB0000ul
+
+#define HEAP_SIGNATURE_VALID    0x50414548ul // Signature: 'HEAP'
+#define HEAP_SIGNATURE_INVALID  0x00000000ul // Signature cleared
+
+///Heap Manager Life cycle
+#define HEAP_DO_NOT_EXIST_YET        1
+#define HEAP_LOCAL_CACHE             2
+#define HEAP_TEMP_MEM                3
+#define HEAP_SYSTEM_MEM              4
+#define HEAP_DO_NOT_EXIST_ANYMORE    5
+#define HEAP_S3_RESUME               6
+#define HEAP_RUNTIME_SYSTEM_MEM      7
+
+///Heap callout
+#define HEAP_CALLOUT_BOOTTIME        0
+#define HEAP_CALLOUT_RUNTIME         1
+
+#define AMD_MTRR_FIX64k_00000    0x250
+#define AMD_MTRR_FIX16k_80000    0x258
+#define AMD_MTRR_FIX16k_A0000    0x259
+#define AMD_MTRR_FIX4k_C0000     0x268
+#define AMD_MTRR_FIX4k_C8000     0x269
+#define AMD_MTRR_FIX4k_D0000     0x26A
+#define AMD_MTRR_FIX4k_D8000     0x26B
+#define AMD_MTRR_FIX4k_E0000     0x26C
+#define AMD_MTRR_FIX4k_E8000     0x26D
+#define AMD_MTRR_FIX4k_F0000     0x26E
+#define AMD_MTRR_FIX4k_F8000     0x26F
+
+#define AMD_MTRR_FIX64K_WB_DRAM  0x1E
+#define AMD_MTRR_FIX64K_WT_DRAM  0x1C
+#define AMD_MTRR_FIX64K_UC_DRAM  0x18
+#define AMD_MTRR_FIX16K_WB_DRAM  0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX16K_WT_DRAM  0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX16K_UC_DRAM  0x1818181818181818ull
+#define AMD_MTRR_FIX4K_WB_DRAM   0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX4K_WT_DRAM   0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX4K_UC_DRAM   0x1818181818181818ull
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Allocate Heap Parameters
+typedef struct _ALLOCATE_HEAP_PARAMS {
+  UINT32  RequestedBufferSize;                    ///< Size of buffer.
+  UINT32  BufferHandle;                           ///< An unique ID of buffer.
+  UINT8   Persist;                                ///< A flag. If marked, to be stored and passed to AmdInitLate.
+  UINT8   *BufferPtr;                             ///< Pointer to buffer.
+} ALLOCATE_HEAP_PARAMS;
+
+/// Locate Heap Parameters
+typedef struct _LOCATE_HEAP_PTR {
+  UINT32  BufferHandle;                           ///< An unique ID of buffer.
+  UINT32 BufferSize;                              ///< Data buffer size.
+  UINT8   *BufferPtr;                             ///< Pointer to buffer.
+} LOCATE_HEAP_PTR;
+
+/// Heap Node Header
+typedef struct _BUFFER_NODE {
+  UINT32        BufferHandle;                     ///< An unique ID of buffer.
+  UINT32        BufferSize;                       ///< Size of buffer.
+  UINT8         Persist;                          ///< A flag. If marked, to be stored and passed to AmdInitLate.
+  UINT8         PadSize;                          ///< Size of pad.
+  UINT32        OffsetOfNextNode;                 ///< Offset of next node (relative to the base).
+} BUFFER_NODE;
+
+/// Heap Manager
+typedef struct _HEAP_MANAGER {
+  UINT32 Signature;                               ///< a signature to indicate if the heap is valid.
+  UINT32 UsedSize;                                ///< Used size of heap.
+  UINT32 FirstActiveBufferOffset;                 ///< Offset of the first active buffer.
+  UINT32 FirstFreeSpaceOffset;                    ///< Offset of the first free space.
+} HEAP_MANAGER;
+
+/// AGESA Buffer Handles (These are reserved)
+typedef enum {
+  AMD_INIT_RESET_HANDLE = 0x000A000,              ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
+  AMD_INIT_EARLY_HANDLE,                          ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
+  AMD_INIT_POST_HANDLE,                           ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
+  AMD_INIT_ENV_HANDLE,                            ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
+  AMD_INIT_MID_HANDLE,                            ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
+  AMD_INIT_LATE_HANDLE,                           ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
+  AMD_INIT_RESUME_HANDLE,                         ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
+  AMD_LATE_RUN_AP_TASK_HANDLE,                    ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
+  AMD_S3_SAVE_HANDLE,                             ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
+  AMD_S3_LATE_RESTORE_HANDLE,                     ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
+  AMD_S3_SCRIPT_SAVE_TABLE_HANDLE,                ///< Assign 0x000A00A buffer handle to be used for S3 save table
+  AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE,               ///< Assign 0x000A00B buffer handle to be used for S3 save table
+  AMD_CPU_AP_TASKING_HANDLE,                      ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
+  AMD_REC_MEM_SOCKET_HANDLE,                      ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
+  AMD_MEM_AUTO_HANDLE,                            ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
+  AMD_MEM_SPD_HANDLE,                             ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
+  AMD_MEM_DATA_HANDLE,                            ///< Assign 0x000A010 buffer handle to MemData
+  AMD_MEM_TRAIN_BUFFER_HANDLE,                    ///< Assign 0x000A011 buffer handle to allocate buffer for training
+  AMD_MEM_S3_DATA_HANDLE,                         ///< Assign 0x000A012 buffer handle to special case register for S3
+  AMD_MEM_S3_NB_HANDLE,                           ///< Assign 0x000A013 buffer handle to NB block for S3
+  AMD_MEM_S3_MR0_DATA_HANDLE,                     ///< Assign 0x000A014 buffer handle to MR0 data block for S3
+  AMD_UMA_INFO_HANDLE,                            ///< Assign 0x000A015 buffer handle to be used for Uma information
+  AMD_DMI_MEM_DEV_INFO_HANDLE,                    ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
+  HT_STATE_DATA_HANDLE,                           ///< Assign 0x000A017 buffer handle to HT State Data
+  PRESERVE_MAIL_BOX_HANDLE,                       ///< Assign 0x000A018 buffer handle for Preserve Mailbox Feature.
+  EVENT_LOG_BUFFER_HANDLE,                        ///< Assign 0x000A019 buffer handle to Event Log
+  IDS_CONTROL_HANDLE,                             ///< Assign 0x000A01A buffer handle to AmdIds routine.
+  IDS_HT_DATA_HANDLE,                             ///< Assign 0x000A01B buffer handle to Ht IDS control
+  IDS_HDT_OUT_BUFFER_HANDLE,                      ///< Assign 0x000A01C buffer handle to be used for HDTOUT support.
+  IDS_CHECK_POINT_PERF_HANDLE,                    ///< Assign 0x000A01D buffer handle to Performance analysis
+  AMD_PCIE_COMPLEX_DATA_HANDLE,                   ///< Assign 0x000A01E buffer handle to be used for PCIe support
+  AMD_MEM_SYS_DATA_HANDLE,                        ///< Assign 0x000A01F buffer handle to be used for memory data structure
+  AMD_GNB_SMU_CONFIG_HANDLE,                      ///< Assign 0x000A020 buffer handle to be used for GNB SMU configuration
+  AMD_PP_FUSE_TABLE_HANDLE,                       ///< Assign 0x000A021 buffer handle to be used for TT fuse table
+  AMD_GFX_PLATFORM_CONFIG_HANDLE,                 ///< Assign 0x000A022 buffer handle to be used for Gfx platform configuration
+  AMD_GNB_TEMP_DATA_HANDLE,                       ///< Assign 0x000A024 buffer handle for GNB general purpose data block
+  AMD_MEM_2D_RDQS_HANDLE,                         ///< Assign 0x000A025 buffer handle for 2D training
+  AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE,               ///< Assign 0x000A026 buffer handle to be used for GNB IOMMU scratch memory
+  AMD_MEM_S3_SAVE_HANDLE,                         ///< Assign 0x000A027 buffer handle for memory data saved right after memory init
+  AMD_MEM_2D_RDQS_RIM_HANDLE,                     ///< Assign 0x000A028 buffer handle for 2D training Eye RIM Search
+  AMD_CPU_NB_PSTATE_FIXUP_HANDLE,                 ///< Assign 0x000A029 buffer handle for an NB P-state workaround
+  AMD_MEM_CRAT_INFO_BUFFER_HANDLE,                ///< Assign 0x000A02B buffer handle for CRAT Memory affinity component structure
+  AMD_MEM_MISC_HANDLES_START = 0x1000000,         ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
+  AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF,           ///< miscellaneous memory init tasks' buffers.
+  AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000,     ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
+  SOCKET_DIE_MAP_HANDLE = 0x534F4B54,             ///< 'sokt'
+  NODE_ID_MAP_HANDLE = 0x4E4F4445,                ///< 'node'
+  HOP_COUNT_TABLE_HANDLE = 0x484F5053,            ///< 'hops'
+  LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258,    ///< 'ambx'
+  AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852,   ///< 'FCHR' Buffer handle for FCH private data block at InitReset
+  AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845,         ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
+  IDS_TRAP_TABLE_HANDLE = 0x49524547,             ///< 'IREG' Handle for IDS register table
+  IDS_SAVE_IDTR_HANDLE = 0x49445452,              ///< 'IDTR'
+  IDS_BSC_IDT_HANDLE = 0x42534349,                ///< 'BSCI' BSC Idt table
+  IDS_NV_TO_CMOS_HANDLE = 0x534D4349,             ///< 'ICMS' Handle for IDS CMOS save
+  IDS_GRA_HANDLE = 0x41524749,                    ///< 'IGRA' Handle for IDS GRA save
+  IDS_EXTEND_HANDLE = 0x54584549                  ///< 'IEXT' Handle for IDS extend module
+} AGESA_BUFFER_HANDLE;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+HeapManagerInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+HeapAllocateBuffer (
+  IN OUT   ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+  IN       UINT32 BufferHandle,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+HeapLocateBuffer (
+  IN OUT   LOCATE_HEAP_PTR *LocateHeap,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT64
+HeapGetBaseAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+EventLogInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif // _HEAP_MANAGER_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
new file mode 100644
index 0000000000..768f2cd62b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
@@ -0,0 +1,143 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD MMIO Map Manager APIs, and related functions.
+ *
+ * Contains code that manage MMIO base/limit registers
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63522 $   @e \$Date: 2011-12-25 20:25:03 -0600 (Sun, 25 Dec 2011) $
+ *
+ */
+/*******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "mmioMapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_MMIOMAPMANAGER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE MmioMapFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  MMIO map manager
+ *
+ * @param[in]    AmdAddMmioParams   Pointer to a data structure containing the parameter information.
+ *
+ * @retval       AGESA_STATUS       AGESA_ERROR       - The requested range could not be added because there are not
+ *                                                      enough mapping resources.
+ *                                  AGESA_UNSUPPORTED - not support on currect processor
+ *                                  AGESA_BOUNDS_CHK  - One or more input parameters are invalid. For example, the
+ *                                                      TargetAddress does not correspond to any device in the system.
+ *                                  AGESA_SUCCESS     - Adding MMIO map succeeds
+ *
+ */
+AGESA_STATUS
+AmdAddMmioMapping (
+  IN       AMD_ADD_MMIO_PARAMS AmdAddMmioParams
+  )
+{
+  MMIO_MAP_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&MmioMapFamilyServiceTable, (CONST VOID **)&FamilyServices, &(AmdAddMmioParams.StdHeader));
+  if (FamilyServices != NULL) {
+    return (FamilyServices->addingMmioMap (FamilyServices, AmdAddMmioParams));
+  } else {
+    return AGESA_UNSUPPORTED;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
new file mode 100644
index 0000000000..d4cb6e5bb4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
@@ -0,0 +1,169 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD MMIO Map Manager APIs, and related functions.
+ *
+ * Contains code that manage MMIO base/limit registers
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 63522 $   @e \$Date: 2011-12-25 20:25:03 -0600 (Sun, 25 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _MMIO_MAP_MANAGER_H_
+#define _MMIO_MAP_MANAGER_H_
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (MMIO_MAP_FAMILY_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// MMIO attribute
+typedef struct _AMD_MMIO_ATTRIBUTE {
+  UINT8   MmioReadableRange:1;  ///< Indicator whether the range is readable
+  UINT8   MmioWritableRange:1;  ///< Indicator whether the range is writable
+  UINT8   MmioPostedRange:1;    ///< Indicator whether the range is posted
+  UINT8   MmioSecuredRange:1;   ///< Indicator whether the range is locked
+  UINT8   :4;                   ///< Reserved
+} AMD_MMIO_ATTRIBUTE;
+
+/// MMIO destination
+typedef struct _AMD_MMIO_DST {
+  UINT32   DstNode:3;           ///< Destination node ID bits
+  UINT32   DstLink:2;           ///< Destination link ID
+  UINT32   DstSubLink:1;        ///< Destination sublink
+} AMD_MMIO_DST;
+
+/// MMIO range
+typedef struct _MMIO_RANGE {
+  UINT64  Base;                 ///< Base
+  UINT64  Limit;                ///< Limit
+  AMD_MMIO_ATTRIBUTE Attribute; ///< Attribute
+  AMD_MMIO_DST Destination;     ///< Destination
+  UINT8   RangeNum;             ///< Range No.
+  BOOLEAN Modified;             ///< if this MMIO base/limit registers need to be updated
+} MMIO_RANGE;
+
+/// AMD_ADD_MMIO_PARAMS
+typedef struct _AMD_ADD_MMIO_PARAMS {
+  AMD_CONFIG_PARAMS StdHeader;  ///< Config Handle for library, services.
+  UINT64 BaseAddress;           ///< This is the starting address of the requested MMIO range.
+  UINT64 Length;                ///< This is the length of the range to allocate, in bytes.
+  PCI_ADDR TargetAddress;       ///< This is the PCIe address of the device for which this range is allocated, and it
+                                ///< provides the bus, device, and function of the target device.
+  AMD_MMIO_ATTRIBUTE Attributes;///< This indicates the attributes of the requested range.
+} AMD_ADD_MMIO_PARAMS;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to MMIO map manager.
+ *
+ * @param[in]    MmioMapServices    MMIO map manager services.
+ * @param[in]    AmdAddMmioParams   Pointer to a data structure containing the parameter information.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_MMIO_MAP_ADDING_MAP (
+  IN       MMIO_MAP_FAMILY_SERVICES *MmioMapServices,
+  IN       AMD_ADD_MMIO_PARAMS      AmdAddMmioParams
+  );
+
+/// Reference to a Method.
+typedef F_MMIO_MAP_ADDING_MAP *PF_MMIO_MAP_ADDING_MAP;
+
+/**
+ * Provide the interface to the MMIO map manager Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _MMIO_MAP_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_MMIO_MAP_ADDING_MAP  addingMmioMap;                                ///< Method: Family specific call to adding MMIO map.
+};
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdAddMmioMapping (
+  IN       AMD_ADD_MMIO_PARAMS AmdAddMmioParams
+  );
+
+#endif // _MMIO_MAP_MANAGER_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdFch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdFch.h
new file mode 100644
index 0000000000..5e4a66f1a3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdFch.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD FCH Component
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _AMD_FCH_H_
+#define _AMD_FCH_H_
+
+typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr);
+typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg);
+
+
+/// FCH API build options
+typedef struct {
+  FCH_INIT        *InitReset;                   ///< InitReset
+  FCH_INIT        *InitResetConstructor;        ///< InitResetConstructor
+  FCH_INIT        *InitEnv;                     ///< InitEnv
+  FCH_INIT        *InitEnvConstructor;          ///< InitEnvConstructor
+  FCH_INIT        *InitMid;                     ///< InitMid
+  FCH_INIT        *InitMidConstructor;          ///< InitMidConstructor
+  FCH_INIT        *InitLate;                    ///< InitLate
+  FCH_INIT        *InitLateConstructor;         ///< InitLateConstructor
+} BLDOPT_FCH_FUNCTION;
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c
new file mode 100644
index 0000000000..a56cc1bbef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c
@@ -0,0 +1,346 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "AdvancedApi.h"
+#include "cpuServices.h"
+#include "CommonInits.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+EXECUTION_CACHE_REGION InitExeCacheMap[] =
+{
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdEarlyPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+AllocateExecutionCacheInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitEarly stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdEarlyPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by the wrapper to initialize the input
+ * structure for the AllocateExecutionCache.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   AmdExeAddrMapPtr  Our Service interface struct
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AllocateExecutionCacheInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  UINT8 i;
+  ASSERT (AmdExeAddrMapPtr != NULL);
+
+  for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr;
+    AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Initializer routine that will be invoked by the wrapper to initialize the input
+ *  structure for the AmdInitEarly.
+ *
+ *  @param[in]      StdHeader       AMD standard header config param.
+ *  @param[in,out]  EarlyParams     The service interface struct to initialize.
+ *
+ *  @retval         AGESA_SUCCESS   Always succeeds.
+ */
+AGESA_STATUS
+AmdInitEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (EarlyParams != NULL);
+
+  EarlyParams->StdHeader = *StdHeader;
+
+  // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED.
+  //
+
+  AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
+
+  AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig);
+
+  AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform initialization services required at the Early Init POST time point.
+ *
+ * Execution Cache, HyperTransport, and AP Init advanced services are performed.
+ *
+ * @param[in]     EarlyParams  The interface struct for all early services
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.
+ *
+ */
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  )
+{
+  AGESA_STATUS  CalledAgesaStatus;
+  AGESA_STATUS  EarlyInitStatus;
+  WARM_RESET_REQUEST Request;
+  UINT8 PrevRequestBit;
+  UINT8 PrevStateBits;
+
+  IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader);
+
+  AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);
+
+  EarlyInitStatus = AGESA_SUCCESS;
+
+  // Setup ROM execution cache
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n");
+  CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n");
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    {
+      extern CHAR8 *BldOptDebugOutput[];
+
+      UINT8 i;
+      for (i = 0; BldOptDebugOutput[i] != NULL; i++) {
+        IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]);
+      }
+    }
+  )
+
+  //
+  // WARNING: AGESA's own IDT is at heap which would be moved from one place to another
+  //          so we MUST restore IDT every time before moving heap.
+  //
+  IDS_EXCEPTION_TRAP (IDS_IDT_REPLACE_IDTR_FOR_BSC, NULL, &EarlyParams->StdHeader);
+  ASSERT (EarlyParams != NULL);
+  PrevRequestBit = FALSE;
+  PrevStateBits = WR_STATE_COLD;
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: Start %x \n\n", PrevStateBits);
+  // If a previously requested warm reset cannot be triggered in the
+  // current stage, store the previous state of request and reset the
+  // request struct to the current post stage
+  GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    if (Request.StateBits >= Request.PostStage) {
+      PrevRequestBit = Request.RequestBit;
+      PrevStateBits = Request.StateBits;
+      Request.RequestBit = FALSE;
+      Request.StateBits = Request.PostStage - 1;
+      SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+    }
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader);
+
+  // Full Hypertransport Initialization
+  // IMPORTANT: All AP cores call Ht Init.  HT Init handles full init for the BSC, and map init for APs.
+  IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n");
+  CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n");
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader);
+  CalledAgesaStatus = GnbInitAtEarlier (EarlyParams);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // AP launch
+  IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n");
+  CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n");
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // Warm Reset, should be at the end of AmdInitEarly
+  GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+  // If a warm reset is requested in the current post stage, trigger the
+  // warm reset and ignore the previous request
+  if (Request.RequestBit == TRUE) {
+    if (Request.StateBits < Request.PostStage) {
+      AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader);
+    }
+  } else {
+    // Otherwise, if there's a previous request, restore it
+    // so that the subsequent post stage can trigger the warm reset
+    if (PrevRequestBit == TRUE) {
+      Request.RequestBit = PrevRequestBit;
+      Request.StateBits = PrevStateBits;
+      SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+    }
+  }
+
+  IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader);
+  CalledAgesaStatus = GnbInitAtEarly (EarlyParams);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n");
+
+  // Flush out all debug contents in case warm reset is triggered after this point
+  IDS_HDT_CONSOLE_FLUSH_BUFFER (&EarlyParams->StdHeader);
+  IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader);
+
+  return  EarlyInitStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
new file mode 100644
index 0000000000..b1d3c1bf16
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
@@ -0,0 +1,213 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuEnvInit.h"
+#include "heapManager.h"
+#include "GnbInterface.h"
+#include "CommonInits.h"
+#include "AmdFch.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#include "CreateStruct.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_AMDINITENV_FILECODE
+
+extern BLDOPT_FCH_FUNCTION  BldoptFchFunction;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitEnv
+ *
+ *  @param[in,out]  EnvParamsPtr   Newly created interface parameters for AmdInitEnv
+ *
+ *  @retval         AGESA_SUCCESS  Always succeeds
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitEnvInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_ENV_PARAMS    *EnvParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (EnvParamsPtr != NULL);
+
+  EnvParamsPtr->StdHeader = *StdHeader;
+
+  CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader);
+  BldoptFchFunction.InitEnvConstructor (EnvParamsPtr);
+  GnbInitDataStructAtEnvDef (&EnvParamsPtr->GnbEnvConfiguration, EnvParamsPtr);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_ENV function.
+ *
+ * This entry point is responsible for copying the heap contents from the
+ * temp RAM area to main memory.
+ *
+ * @param[in,out] EnvParams         Required input parameters for the AMD_INIT_ENV
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD env calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS  *EnvParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitEnvStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
+
+  ASSERT (EnvParams != NULL);
+  AmdInitEnvStatus = AGESA_SUCCESS;
+
+
+  //Copy Temp Ram heap content to Main Ram
+  AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+  EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+  EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);
+  // Any heap allocate/deallocat/locate buffer should be used after heap is rebuild from here.
+  // After persist heaps are tansfer and rebuild, HeapLocateBuffer can start to be used in IDS hook.
+
+  //Heap have been relocated, so Debug Print need be init again to get new address
+  IDS_PERF_TIMESTAMP (&EnvParams->StdHeader);
+  IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n");
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n");
+  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));
+  IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
+
+  AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+
+  IDS_PERF_TIMESTAMP (&EnvParams->StdHeader);
+  AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);
+  AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;
+
+  IDS_PERF_TIMESTAMP (&EnvParams->StdHeader);
+  AgesaStatus = GnbInitAtEnv (EnvParams);
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n");
+  IDS_PERF_TIMESTAMP (&EnvParams->StdHeader);
+  IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
+  return  AmdInitEnvStatus;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
new file mode 100644
index 0000000000..9dd2d0d8cc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
@@ -0,0 +1,331 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionDmi.h"
+#include "OptionSlit.h"
+#include "cpuLateInit.h"
+#include "cpuFeatures.h"
+#include "CommonInits.h"
+#include "GnbInterface.h"
+#include "OptionPstate.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_DMI_CONFIGURATION    OptionDmiConfiguration;  // global user config record
+extern OPTION_SLIT_CONFIGURATION   OptionSlitConfiguration; // global user config record
+extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdLatePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitLate stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdLatePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitLateInitializer
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitLate
+ *
+ *  @param[in, out]    IN OUT   AMD_LATE_PARAMS *LateParamsPtr
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitLateInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_LATE_PARAMS   *LateParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (LateParamsPtr != NULL);
+
+  LateParamsPtr->StdHeader = *StdHeader;
+
+  AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader);
+
+  LateParamsPtr->AcpiSlit = NULL;
+
+  LateParamsPtr->AcpiSrat = NULL;
+
+  LateParamsPtr->AcpiWheaMce = NULL;
+  LateParamsPtr->AcpiWheaCmc = NULL;
+
+  LateParamsPtr->AcpiPState = NULL;
+
+  LateParamsPtr->DmiTable = NULL;
+
+  LateParamsPtr->AcpiAlib = NULL;
+
+  LateParamsPtr->IvrsExclusionRangeList = UserOptions.CfgIvrsExclusionRangeList;
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitLateDestructor
+ *
+ *  Destruct routine that provide a chance if something need to be done
+ *  before the end of AmdInitLate.
+ *
+ *  @param[in]    StdHeader       The standard header.
+ *  @param[in]    LateParamsPtr   AMD init late param.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitLateDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_LATE_PARAMS   *LateParamsPtr
+  )
+{
+
+  ASSERT (LateParamsPtr != NULL);
+
+  (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader);
+  (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_LATE function.
+ *
+ * This entry point is responsible for creating any desired ACPI tables, providing
+ * information for DMI, and to prepare the processors for the operating system
+ * bootstrap load process.
+ *
+ * @param[in,out] LateParams     Required input parameters for the AMD_INIT_LATE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD late calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS *LateParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitLateStatus;
+
+  IDS_PERF_TIMESTAMP (&LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n");
+  AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader);
+
+  ASSERT (LateParams != NULL);
+  AmdInitLateStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader);
+
+  IDS_PERF_TIMESTAMP (&LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n");
+  // _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables
+  if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) {
+    AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState));
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+
+
+  // SRAT Table Generation
+  if (LateParams->PlatformConfig.UserOptionSrat) {
+    AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // SLIT Table Generation
+  if (LateParams->PlatformConfig.UserOptionSlit) {
+    AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // WHEA Table Generation
+  if (LateParams->PlatformConfig.UserOptionWhea) {
+    AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // DMI Table Generation
+  if (LateParams->PlatformConfig.UserOptionDmi) {
+    AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+  IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n");
+
+  // Cpu Features
+  IDS_PERF_TIMESTAMP (&LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n");
+  AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n");
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  // It is the last function run by the AGESA CPU module and prepares the processor
+  // for the operating system bootstrap load process.
+  IDS_PERF_TIMESTAMP (&LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n");
+  AgesaStatus = AmdCpuLate (&LateParams->StdHeader, &LateParams->PlatformConfig);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n");
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  IDS_PERF_TIMESTAMP (&LateParams->StdHeader);
+  AgesaStatus = GnbInitAtLate (LateParams);
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n");
+  AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader);
+//End Debug Print Service
+  IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader);
+  IDS_PERF_TIMESTAMP (&LateParams->StdHeader);
+  IDS_PERF_ANALYSE (&LateParams->StdHeader);
+
+  return  AmdInitLateStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
new file mode 100644
index 0000000000..f4b0b45ae6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
@@ -0,0 +1,201 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "CommonInits.h"
+#include "GnbInterface.h"
+#include "AmdFch.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_AMDINITMID_FILECODE
+
+extern BLDOPT_FCH_FUNCTION  BldoptFchFunction;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitMid
+ *
+ *  @param[in,out]  MidParamsPtr   Newly created interface parameters for AmdInitMid
+ *
+ *  @retval         AGESA_SUCCESS  Always succeeds
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitMidInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_MID_PARAMS    *MidParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (MidParamsPtr != NULL);
+
+  MidParamsPtr->StdHeader = *StdHeader;
+  CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader);
+  BldoptFchFunction.InitMidConstructor (MidParamsPtr);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_MID function.
+ *
+ * This entry point is responsible for performing any necessary functions needed
+ * after PCI bus enumeration and just before control is passed to the video option ROM.
+ *
+ * @param[in,out] MidParams      Required input parameters for the AMD_INIT_MID
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD mid calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS *MidParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  CalledStatus;
+
+  IDS_PERF_TIMESTAMP (&MidParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n");
+  AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  ASSERT (MidParams != NULL);
+  IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);
+
+  IDS_PERF_TIMESTAMP (&MidParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n");
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n");
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  IDS_PERF_TIMESTAMP (&MidParams->StdHeader);
+  CalledStatus = BldoptFchFunction.InitMid (MidParams);
+  AgesaStatus = (CalledStatus > AgesaStatus) ? CalledStatus : AgesaStatus;
+
+  IDS_PERF_TIMESTAMP (&MidParams->StdHeader);
+  CalledStatus = GnbInitAtMid (MidParams);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);
+
+  AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n");
+  IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);
+  IDS_PERF_TIMESTAMP (&MidParams->StdHeader);
+
+  return AgesaStatus;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
new file mode 100644
index 0000000000..1dd6719584
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
@@ -0,0 +1,373 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63692 $   @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuPostInit.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CommonInits.h"
+#include "cpuServices.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#include "CreateStruct.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdPostPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitPost stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdPostPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitPostInitializer
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitPost
+ *
+ *  @param[in, out]    IN OUT   AMD_POST_PARAMS *PostParamsPtr
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitPostInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_POST_PARAMS   *PostParamsPtr
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PostParamsPtr != NULL);
+
+  PostParamsPtr->StdHeader = *StdHeader;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+  AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader);
+
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
+    PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig);
+    PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader;
+    AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader);
+    AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig);
+    GnbInitDataStructAtPostDef (&PostParamsPtr->GnbPostConfig, PostParamsPtr);
+  }
+  return AgesaStatus;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitPostDestructor
+ *
+ *  Destruct routine that provide a chance if something need to be done
+ *  before the end of AmdInitPost.
+ *
+ *  @param[in]    StdHeader       The standard header.
+ *  @param[in]    PostParamsPtr   AMD init post param.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitPostDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_POST_PARAMS   *PostParamsPtr
+  )
+{
+
+  ASSERT (PostParamsPtr != NULL);
+
+  PostParamsPtr->StdHeader = *StdHeader;
+  PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader;
+
+  //
+  // AmdMemAuto completed. Here, release heap space which is used for memory init.
+  //
+  MemAmdFinalize (PostParamsPtr->MemConfig.MemData);
+  HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+
+  //
+  // AmdCpuPost completed.
+  //
+  if (PostParamsPtr->MemConfig.SysLimit != 0) {
+    // WBINVD can only be executed when memory is available
+    FinalizeAtPost (StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_POST function.
+ *
+ * This entry point is responsible for initializing all system memory,
+ * gathering important data out of the pre-memory cache storage into a
+ * temporary holding buffer in main memory. After that APs will be
+ * shutdown in preparation for the host environment to take control.
+ * Note: pre-memory stack will be disabled also.
+ *
+ * @param[in,out] PostParams     Required input parameters for the AMD_INIT_POST
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD POST calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS *PostParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitPostStatus;
+  WARM_RESET_REQUEST Request;
+  UINT8 PrevRequestBit;
+  UINT8 PrevStateBits;
+
+  IDS_PERF_TIMESTAMP (&PostParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n");
+
+  ASSERT (PostParams != NULL);
+  AmdInitPostStatus = AGESA_SUCCESS;
+  PrevRequestBit = FALSE;
+  PrevStateBits = WR_STATE_COLD;
+
+  IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
+
+  // If a previously requested warm reset cannot be triggered in the
+  // current stage, store the previous state of request and reset the
+  // request struct to the current post stage
+  GetWarmResetFlag (&PostParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    if (Request.StateBits >= Request.PostStage) {
+      PrevRequestBit = Request.RequestBit;
+      PrevStateBits = Request.StateBits;
+      Request.RequestBit = FALSE;
+      Request.StateBits = Request.PostStage - 1;
+      SetWarmResetFlag (&PostParams->StdHeader, &Request);
+    }
+  }
+
+  IDS_PERF_TIMESTAMP (&PostParams->StdHeader);
+  AgesaStatus = GnbInitAtPost (PostParams);
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  IDS_PERF_TIMESTAMP (&PostParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n");
+  AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n");
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  // Check BIST status
+  AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  //
+  // P-State data gathered, then, Relinquish APs
+  //
+  IDS_PERF_TIMESTAMP (&PostParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n");
+  AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n");
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  if (AgesaStatus != AGESA_FATAL) {
+
+    // Warm Reset
+    GetWarmResetFlag (&PostParams->StdHeader, &Request);
+    // If a warm reset is requested in the current post stage, trigger the
+    // warm reset and ignore the previous request
+    if (Request.RequestBit == TRUE) {
+      if (Request.StateBits < Request.PostStage) {
+        AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
+      }
+    } else {
+      // Otherwise, if there's a previous request, restore it
+      // so that the subsequent post stage can trigger the warm reset
+      if (PrevRequestBit == TRUE) {
+        Request.RequestBit = PrevRequestBit;
+        Request.StateBits = PrevStateBits;
+        SetWarmResetFlag (&PostParams->StdHeader, &Request);
+      }
+    }
+
+    IDS_PERF_TIMESTAMP (&PostParams->StdHeader);
+    AgesaStatus = GnbInitAtPostAfterDram (PostParams);
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+
+    IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
+
+    AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
+    IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n");
+    IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n");
+
+    //For Heap will be relocate to new address in next stage, flush out  debug print buffer if needed
+    IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader);
+
+    // WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here
+    IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader);
+    IDS_PERF_TIMESTAMP (&PostParams->StdHeader);
+
+    // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
+    AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+    PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
+
+  // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside
+  // of AGESA to be recognized by IsWarmReset()
+  GetWarmResetFlag (&PostParams->StdHeader, &Request);
+  Request.StateBits = Request.PostStage;
+  SetWarmResetFlag (&PostParams->StdHeader, &Request);
+
+  return  AmdInitPostStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c
new file mode 100644
index 0000000000..12b2d76ad5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c
@@ -0,0 +1,195 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "mm.h"
+#include "GnbInterface.h"
+#include "cpuRecovery.h"
+#include "cpuCacheInit.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_COMMON_AMDINITRECOVERY_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform initialization services required at the Early Init POST time point.
+ *
+ * Execution Cache, HyperTransport, C1e, and AP Init advanced services are performed.
+ *
+ * @param[in, out]     RecoveryParams  The interface struct for Recovery services
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.
+ *
+ */
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS      *RecoveryParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  CalledAgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitRecoveryEntry, &RecoveryParams->StdHeader);
+
+  ASSERT (RecoveryParams != NULL);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&RecoveryParams->StdHeader, &RecoveryParams->CacheRegion[0]);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdHtInitRecovery (&RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdCpuRecovery ((AMD_CPU_RECOVERY_PARAMS *) &RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdMemRecovery (RecoveryParams->MemConfig.MemData);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdGnbRecovery (&RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdInitRecoveryExit, &RecoveryParams->StdHeader);
+  return  AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Initialize defaults and options for Amd Init Reset.
+ *
+ * @param[in]  StdHeader              AMD standard header config param.
+ * @param[in]  AmdRecoveryParamsPtr   The Reset Init interface to initialize.
+ *
+ * @retval     AGESA_SUCCESS    Always Succeeds.
+ */
+AGESA_STATUS
+AmdInitRecoveryInitializer (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN OUT   AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (AmdRecoveryParamsPtr != NULL);
+
+  AmdRecoveryParamsPtr->StdHeader = *StdHeader;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+  AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &AmdRecoveryParamsPtr->StdHeader) == AGESA_SUCCESS) {
+    AmdRecoveryParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
+    AmdRecoveryParamsPtr->MemConfig.MemData->ParameterListPtr = &(AmdRecoveryParamsPtr->MemConfig);
+    LibAmdMemCopy ((VOID *) AmdRecoveryParamsPtr->MemConfig.MemData,
+                   (VOID *) AmdRecoveryParamsPtr,
+                   (UINTN) sizeof (AmdRecoveryParamsPtr->StdHeader),
+                   &AmdRecoveryParamsPtr->StdHeader
+                  );
+    AmdMemInitDataStructDefRecovery (AmdRecoveryParamsPtr->MemConfig.MemData);
+    return AGESA_SUCCESS;
+  } else {
+    return AGESA_ERROR;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
new file mode 100644
index 0000000000..a15855f829
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
@@ -0,0 +1,283 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuServices.h"
+#include "AdvancedApi.h"
+#include "GeneralServices.h"
+#include "OptionsHt.h"
+#include "AmdFch.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE
+
+extern BLDOPT_FCH_FUNCTION  BldoptFchFunction;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST OPTION_HT_INIT_RESET HtOptionInitReset;
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitResetExecutionCacheAllocateInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by the wrapper to initialize the input
+ * structure for the AllocateExecutionCache.
+ *
+ *  Parameters:
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   AmdExeAddrMapPtr  Our Service interface struct
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdInitResetExecutionCacheAllocateInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  ASSERT (AmdExeAddrMapPtr != NULL);
+
+  LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_RESET function.
+ *
+ * This entry point is responsible for establishing the HT links to the program
+ * ROM and for performing basic processor initialization.
+ *
+ * @param[in,out] ResetParams    Required input parameters for the AMD_INIT_RESET
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD reset calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS *ResetParams
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledAgesaStatus;
+  WARM_RESET_REQUEST Request;
+  UINT8 PrevRequestBit;
+  UINT8 PrevStateBits;
+
+  IDS_PERF_TIMESTAMP (&ResetParams->StdHeader);
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  //IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader);
+
+  // Init Debug Print function
+  IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader);
+
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
+
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString);
+
+  AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
+  ASSERT (ResetParams != NULL);
+
+  PrevRequestBit = FALSE;
+  PrevStateBits = WR_STATE_COLD;
+
+  IDS_PERF_TIMESTAMP (&ResetParams->StdHeader);
+  if (IsBsp (&ResetParams->StdHeader, &AgesaStatus)) {
+    CalledAgesaStatus = BldoptFchFunction.InitReset (ResetParams);
+    AgesaStatus = (CalledAgesaStatus > AgesaStatus) ? CalledAgesaStatus : AgesaStatus;
+  }
+
+  // If a previously requested warm reset cannot be triggered in the
+  // current stage, store the previous state of request and reset the
+  // request struct to the current post stage
+  GetWarmResetFlag (&ResetParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    if (Request.StateBits >= Request.PostStage) {
+      PrevRequestBit = Request.RequestBit;
+      PrevStateBits = Request.StateBits;
+      Request.RequestBit = FALSE;
+      Request.StateBits = Request.PostStage - 1;
+      SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+    }
+  }
+
+  // Initialize the PCI MMIO access mechanism
+  InitializePciMmio (&ResetParams->StdHeader);
+
+  IDS_PERF_TIMESTAMP (&ResetParams->StdHeader);
+  // Initialize Hyper Transport Registers
+  if (HtOptionInitReset.HtInitReset != NULL) {
+    IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n");
+    CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig);
+    IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n");
+    if (CalledAgesaStatus > AgesaStatus) {
+      AgesaStatus = CalledAgesaStatus;
+    }
+  }
+
+  // Warm Reset, should be at the end of AmdInitReset
+  GetWarmResetFlag (&ResetParams->StdHeader, &Request);
+  // If a warm reset is requested in the current post stage, trigger the
+  // warm reset and ignore the previous request
+  if (Request.RequestBit == TRUE) {
+    if (Request.StateBits < Request.PostStage) {
+      AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader);
+    }
+  } else {
+    // Otherwise, if there's a previous request, restore it
+    // so that the subsequent post stage can trigger the warm reset
+    if (PrevRequestBit == TRUE) {
+      Request.RequestBit = PrevRequestBit;
+      Request.StateBits = PrevStateBits;
+      SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+    }
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n");
+
+  AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader);
+
+  IDS_PERF_TIMESTAMP (&ResetParams->StdHeader);
+
+  return  AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize defaults and options for Amd Init Reset.
+ *
+ * @param[in]  StdHeader        Header
+ * @param[in]  AmdResetParams   The Reset Init interface to initialize.
+ *
+ * @retval     AGESA_SUCCESS    Always Succeeds.
+ */
+AGESA_STATUS
+AmdInitResetConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_RESET_PARAMS     *AmdResetParams
+  )
+{
+  ASSERT (AmdResetParams != NULL);
+
+  AmdResetParams->StdHeader = *StdHeader;
+
+  AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]);
+  // Initialize Hyper Transport input structure
+  if (HtOptionInitReset.HtResetConstructor != NULL) {
+    HtOptionInitReset.HtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig);
+  }
+  BldoptFchFunction.InitResetConstructor (AmdResetParams);
+
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c
new file mode 100644
index 0000000000..a86fb2a979
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c
@@ -0,0 +1,272 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "Filecode.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuPostInit.h"
+#include "CommonInits.h"
+#include "cpuFeatures.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_RESUME function.
+ *
+ * This entry point is responsible for performing silicon device and memory
+ * re-initialization for the resume boot path.
+ *
+ * @param[in]     ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD resume calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  VOID   *OrMaskPtr;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS AmdInitResumeStatus;
+  BSC_AP_MSR_SYNC ApMsrSync[4];
+
+  IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume Start\n");
+
+  AmdInitResumeStatus = AGESA_SUCCESS;
+
+  ASSERT (ResumeParams != NULL);
+
+  if (ResumeParams->S3DataBlock.NvStorage != NULL) {
+
+    MemS3ResumeInitNB (&ResumeParams->StdHeader);
+
+    // Restore registers before exiting self refresh
+    RestorePreESRContext (&OrMaskPtr,
+                          ResumeParams->S3DataBlock.NvStorage,
+                          INIT_RESUME,
+                          &ResumeParams->StdHeader);
+    // Exit self refresh
+    ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader);
+    IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader);
+    if (ReturnStatus > AmdInitResumeStatus) {
+      AmdInitResumeStatus = ReturnStatus;
+    }
+    if (ReturnStatus == AGESA_SUCCESS) {
+
+      // Restore registers after exiting self refresh
+      RestorePostESRContext (OrMaskPtr,
+                             ResumeParams->S3DataBlock.NvStorage,
+                             INIT_RESUME,
+                             &ResumeParams->StdHeader);
+
+      ApMsrSync[0].RegisterAddress = SYS_CFG;
+      ApMsrSync[1].RegisterAddress = TOP_MEM;
+      ApMsrSync[2].RegisterAddress = TOP_MEM2;
+      ApMsrSync[3].RegisterAddress = 0;
+      SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader);
+      IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader);
+
+      IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features after S3 AP MTRR sync\n");
+      ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
+      IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader);
+      if (ReturnStatus > AmdInitResumeStatus) {
+        AmdInitResumeStatus = ReturnStatus;
+      }
+    }
+  }
+
+  // Set TscFreqSel at the rate specified by the core P0
+  SetCoresTscFreqSel (&ResumeParams->StdHeader);
+
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume End\n");
+  // HDT out of All Aps
+  IDS_HDT_CONSOLE_FLUSH_BUFFER (&ResumeParams->StdHeader);
+  // Relinquish control of all APs to IBV
+  RelinquishControlOfAllAPs (&ResumeParams->StdHeader);
+
+  // Restore IDT
+  IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &ResumeParams->StdHeader);
+  IDS_OPTION_HOOK (IDS_AFTER_S3_RESUME, NULL, &ResumeParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader);
+  IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader);
+  IDS_PERF_ANALYSE (&ResumeParams->StdHeader);
+
+  return (AmdInitResumeStatus);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_INIT_RESUME function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_INIT_RESUME entry point.
+ *
+ * @param[in]     StdHeader       The standard header.
+ * @param[in,out] ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdInitResumeInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (ResumeParams != NULL);
+
+  ResumeParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&ResumeParams->S3DataBlock);
+  CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Destructor for the AMD_INIT_RESUME function.
+ *
+ * This routine is responsible for deallocation of heap space allocated during
+ * AMD_INIT_RESUME entry point.
+ *
+ * @param[in]    StdHeader       The standard header.
+ * @param[in,out] ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+AmdInitResumeDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS RetVal;
+
+  ASSERT (ResumeParams != NULL);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  // Deallocate heap space allocated during memory S3 resume
+  RetVal = MemS3Deallocate (&ResumeParams->StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  return ReturnStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
new file mode 100644
index 0000000000..b9cf7a97aa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "Options.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST DISPATCH_TABLE ApDispatchTable[];
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Application Processor perform a function as directed by the BSC.
+ *
+ * This is needed for an AP task that must run after AGESA has relinquished control
+ * of the APs to the IBV.
+ *
+ * @param[in]     AmdApExeParams  The interface struct for any required routine.
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.  Note
+ *                that this will be the return value passed back to the BSC as the
+ *                return value for the call out.
+ *
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  )
+{
+  AGESA_STATUS        CalledAgesaStatus;
+  AGESA_STATUS        ApLateTaskStatus;
+  DISPATCH_TABLE      *Entry;
+
+  AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader);
+
+  ASSERT (AmdApExeParams != NULL);
+  ApLateTaskStatus = AGESA_SUCCESS;
+  CalledAgesaStatus = AGESA_UNSUPPORTED;
+
+  // Dispatch, if valid
+  Entry = (DISPATCH_TABLE *) ApDispatchTable;
+  while (Entry->FunctionId != 0) {
+    if (AmdApExeParams->FunctionNumber == Entry->FunctionId) {
+      CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams);
+      break;
+    }
+    Entry++;
+  }
+
+  if (CalledAgesaStatus > ApLateTaskStatus) {
+    ApLateTaskStatus = CalledAgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader);
+  return  ApLateTaskStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_LATE_RUN_AP_TASK function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3_SAVE entry point.
+ *
+ * @param[in]     StdHeader      The standard header.
+ * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdLateRunApTaskInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AP_EXE_PARAMS     *AmdApExeParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (AmdApExeParams != NULL);
+
+  AmdApExeParams->StdHeader = *StdHeader;
+  AmdApExeParams->FunctionNumber = 0;
+  AmdApExeParams->RelatedDataBlock = NULL;
+  AmdApExeParams->RelatedBlockLength = 0;
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
new file mode 100644
index 0000000000..6b2dfd80eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
@@ -0,0 +1,244 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "S3.h"
+#include "cpuFeatures.h"
+#include "S3SaveState.h"
+#include "CommonInits.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdS3LateRestorePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_S3LATE_RESTORE function.
+ *
+ * This entry point is responsible for restoring saved registers and preparing the
+ * silicon components for OS restart.
+ *
+ * @param[in,out] S3LateParams   Required input parameters for the AMD_S3LATE_RESTORE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD S3 late restore calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  )
+{
+  UINT8  *BufferPointer;
+  VOID   *OrMaskPtr;
+  VOID   *LateContextPtr;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS CalledStatus;
+
+  AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  ASSERT (S3LateParams != NULL);
+
+  BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
+  S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+  ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
+
+  IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n");
+
+  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
+  IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));
+
+  if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {
+    LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];
+    // Restore registers before exiting self refresh
+    RestorePreESRContext (&OrMaskPtr,
+                          LateContextPtr,
+                          S3_LATE_RESTORE,
+                          &S3LateParams->StdHeader);
+    // Restore registers after exiting self refresh
+    RestorePostESRContext (OrMaskPtr,
+                           LateContextPtr,
+                           S3_LATE_RESTORE,
+                           &S3LateParams->StdHeader);
+  }
+
+  // Dispatch any features needing to run at this time point
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features at S3 late restore end\n");
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,
+                                      &S3LateParams->PlatformConfig,
+                                      &S3LateParams->StdHeader);
+  if (CalledStatus > ReturnStatus) {
+    ReturnStatus = CalledStatus;
+  }
+
+  CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);
+  if (CalledStatus > ReturnStatus) {
+    ReturnStatus = CalledStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n");
+  IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader);
+  return  ReturnStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3LATE_RESTORE function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3LATE_RESTORE entry point.
+ *
+ * @param[in]     StdHeader         AMD standard header config param.
+ * @param[in,out] S3LateParams      Required input parameters for the
+ *                                  AMD_S3LATE_RESTORE entry point.
+ *
+ * @retval        AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestoreInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (S3LateParams != NULL);
+
+  S3LateParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&S3LateParams->S3DataBlock);
+
+  AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdS3LateRestore stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval          AGESA_SUCCESS    Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestorePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c
new file mode 100644
index 0000000000..78f9d4782e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c
@@ -0,0 +1,444 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "CommonInits.h"
+#include "AmdFch.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE
+
+extern BLDOPT_FCH_FUNCTION  BldoptFchFunction;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST UINT32 ROMDATA S3LateHeapTable[] =
+{
+  EVENT_LOG_BUFFER_HANDLE,
+  SOCKET_DIE_MAP_HANDLE,
+  NODE_ID_MAP_HANDLE,
+  LOCAL_AP_MAIL_BOX_CACHE_HANDLE,
+  IDS_CONTROL_HANDLE,
+  AMD_S3_SCRIPT_SAVE_TABLE_HANDLE,
+  AMD_PCIE_COMPLEX_DATA_HANDLE
+};
+
+#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT))
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdS3SavePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_S3_SAVE function.
+ *
+ * This entry point is responsible for saving silicon component registers to the
+ * SMM save area in preparation of entering system suspend-to-RAM mode.
+ *
+ * @param[in,out] AmdS3SaveParams   Required input parameters for the AMD_S3_SAVE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD S3 save calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS *AmdS3SaveParams
+  )
+{
+  UINTN  i;
+  UINT32 EarlyBufferSize;
+  UINT32 LateBufferSize;
+  UINT32 LateContextSize;
+  UINT32 HeapSize;
+  UINT8  *BufferPointer;
+  UINT8  HeapStatus;
+  ALLOCATE_HEAP_PARAMS HeapParams;
+  LOCATE_HEAP_PTR LocateHeap;
+  BUFFER_NODE *FreeSpaceNode;
+  ALLOCATE_HEAP_PARAMS AllocParams;
+  DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList;
+  DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS AgesaStatus;
+  VOID   *HeapPtrs[S3LATE_TABLE_SIZE];
+  UINT32 HeapSizes[S3LATE_TABLE_SIZE];
+  UINT32 HeapBuffersPresent;
+  HEAP_MANAGER *HeapPtr;
+  VOID *MemDataPointer;
+
+  AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader);
+
+  ASSERT (AmdS3SaveParams != NULL);
+
+  HeapBuffersPresent = 0;
+  EarlyBufferSize = 0;
+  LateBufferSize = 0;
+  LateContextSize = 0;
+  HeapSize = 0;
+  NonMemoryRelatedDeviceList = NULL;
+  MemoryRelatedDeviceList = NULL;
+  ReturnStatus = AGESA_SUCCESS;
+  MemDataPointer = NULL;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) {
+    AgesaStatus = GnbInitAtS3Save (AmdS3SaveParams);
+    if (AgesaStatus > ReturnStatus) {
+      ReturnStatus = AgesaStatus;
+    }
+
+    LocateHeap.BufferHandle = AMD_MEM_S3_SAVE_HANDLE;
+    if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
+      // Memory data has been saved and stored in the heap.
+      // Just copy data from heap.
+      // First 4 bytes in the heap store the size of the saved memory data.
+      EarlyBufferSize = *(UINT32 *) LocateHeap.BufferPtr;
+      MemDataPointer = LocateHeap.BufferPtr + 4;
+    } else {
+      // Get memory device list
+      MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
+      if (MemoryRelatedDeviceList != NULL) {
+        // Determine size needed
+        EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader);
+      }
+    }
+
+    if (UserOptions.CfgS3LateRestore) {
+      for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
+        LocateHeap.BufferHandle = S3LateHeapTable[i];
+        if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
+          HeapBuffersPresent++;
+          HeapSize += LocateHeap.BufferSize;
+          HeapPtrs[i] = LocateHeap.BufferPtr;
+          HeapSizes[i] = LocateHeap.BufferSize;
+        } else {
+          HeapPtrs[i] = NULL;
+          HeapSizes[i] = 0;
+        }
+      }
+
+      // Determine heap data size requirements
+      if (HeapBuffersPresent != 0) {
+        HeapSize += ((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * ((sizeof (BUFFER_NODE)) + (NUM_OF_SENTINEL * SIZE_OF_SENTINEL) + 0xF))); // reserve 0xF per buffer node for 16 byte alignment
+      }
+
+      // Get non memory device list
+      GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
+
+      if (NonMemoryRelatedDeviceList != NULL) {
+        // Determine size needed
+        LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader);
+      }
+      LateBufferSize = HeapSize + LateContextSize;
+      if (LateBufferSize != 0) {
+        LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER);
+      }
+    }
+
+    if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) {
+      //
+      // Allocate a buffer
+      //
+      AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize;
+      AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE;
+      AllocParams.Persist = 0;
+      AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
+      if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) {
+        if (AGESA_ERROR > ReturnStatus) {
+          ReturnStatus = AGESA_ERROR;
+        }
+      }
+      AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
+
+      if (EarlyBufferSize != 0) {
+        AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPtr;
+        if (MemDataPointer != NULL) {
+          LibAmdMemCopy (AmdS3SaveParams->S3DataBlock.NvStorage,
+                    MemDataPointer,
+                    EarlyBufferSize,
+                    &AmdS3SaveParams->StdHeader);
+        } else {
+          SaveDeviceListContext (MemoryRelatedDeviceList,
+                           AmdS3SaveParams->S3DataBlock.NvStorage,
+                           INIT_RESUME,
+                           &EarlyBufferSize,
+                           &AmdS3SaveParams->StdHeader);
+        }
+        AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize;
+      }
+
+      if (LateBufferSize != 0) {
+        BufferPointer = AllocParams.BufferPtr;
+        AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]);
+
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize;
+
+        if (HeapSize != 0) {
+          // Transfer heap contents
+          ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER);
+          HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)];
+          HeapPtr->UsedSize = sizeof (HEAP_MANAGER);
+          HeapPtr->Signature = HEAP_SIGNATURE_VALID;
+          HeapPtr->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
+          HeapPtr->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
+          FreeSpaceNode = (BUFFER_NODE *) ((UINT8 *) HeapPtr + sizeof (HEAP_MANAGER));
+          FreeSpaceNode->BufferSize = HeapSize - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE);
+          FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+
+          HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
+          AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+          AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) (UINTN) HeapPtr;
+
+          for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
+            if (HeapPtrs[i] != NULL) {
+              HeapParams.RequestedBufferSize = HeapSizes[i]; // S3LateHeapTable[i].BufferLength;
+              HeapParams.BufferHandle = S3LateHeapTable[i];
+              HeapParams.Persist = HEAP_S3_RESUME;
+              if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
+                LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader);
+              }
+            }
+          }
+
+          AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus;
+        }
+
+
+        if (LateContextSize != 0) {
+
+          ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
+
+          SaveDeviceListContext (NonMemoryRelatedDeviceList,
+                                &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]),
+                                S3_LATE_RESTORE,
+                                &LateContextSize,
+                                &AmdS3SaveParams->StdHeader);
+        }
+
+        AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
+      }
+    }
+  }
+
+  AgesaStatus = BldoptFchFunction.InitLate (AmdS3SaveParams);
+  if (AgesaStatus > ReturnStatus) {
+    ReturnStatus = AgesaStatus;
+  }
+  IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader);
+  return  ReturnStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3_SAVE function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3_SAVE entry point.
+ *
+ * @param[in]    StdHeader       The standard header.
+ * @param[in,out] S3SaveParams   Required input parameters for the AMD_S3_SAVE
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3SaveInitializer (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (S3SaveParams != NULL);
+
+  S3SaveParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock);
+
+  AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader);
+  BldoptFchFunction.InitLateConstructor (S3SaveParams);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Destructor for the AMD_S3_SAVE function.
+ *
+ * This routine is responsible for deallocation of heap space allocated during
+ * AMD_S3_SAVE entry point.
+ *
+ * @param[in]     StdHeader       The standard header.
+ * @param[in,out] S3SaveParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+AmdS3SaveDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  )
+{
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS RetVal;
+  LOCATE_HEAP_PTR LocateHeap;
+
+  ASSERT (S3SaveParams != NULL);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  // Deallocate heap space allocated during memory S3 save
+  LocateHeap.BufferHandle = AMD_MEM_S3_SAVE_HANDLE;
+  if (HeapLocateBuffer (&LocateHeap, StdHeader) == AGESA_SUCCESS) {
+    RetVal = HeapDeallocateBuffer (AMD_MEM_S3_SAVE_HANDLE, StdHeader);
+  } else {
+    RetVal = MemS3Deallocate (&S3SaveParams->StdHeader);
+  }
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  return ReturnStatus;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdS3Save stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval          AGESA_SUCCESS    Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3SavePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
new file mode 100644
index 0000000000..10dba85517
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
@@ -0,0 +1,167 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common initialization routines.
+ *
+ * Contains common initialization routines across AGESA entries of phases.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CommonInits.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_COMMONINITS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+
+/**
+ * Common routine to initialize PLATFORM_CONFIGURATION.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+CommonPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINTN i;
+
+  PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile;
+  PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList;
+  PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode;
+  PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode;
+  PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData;
+  PlatformConfig->C1ePlatformData1 = UserOptions.CfgPlatformC1eOpData1;
+  PlatformConfig->C1ePlatformData2 = UserOptions.CfgPlatformC1eOpData2;
+  PlatformConfig->C1ePlatformData3 = UserOptions.CfgPlatformC1eOpData3;
+  PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode;
+  PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData;
+  PlatformConfig->CStateIoBaseAddress = UserOptions.CfgPlatformCStateIoBaseAddress;
+  PlatformConfig->CpbMode = UserOptions.CfgPlatformCpbMode;
+  PlatformConfig->UserOptionDmi = UserOptions.OptionDmi;
+  PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates;
+  PlatformConfig->UserOptionCrat = UserOptions.OptionCrat;
+  PlatformConfig->UserOptionCdit = UserOptions.OptionCdit;
+  PlatformConfig->UserOptionSrat = UserOptions.OptionSrat;
+  PlatformConfig->UserOptionSlit = UserOptions.OptionSlit;
+  PlatformConfig->UserOptionWhea = UserOptions.OptionWhea;
+  PlatformConfig->LowPowerPstateForProcHot = UserOptions.CfgLowPowerPstateForProcHot;
+  PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue;
+  PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent;
+  PlatformConfig->PStatesInHpcMode = UserOptions.OptionPStatesInHpcMode;
+  PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics;
+  for (i = 0; i < MaxVrmType; i++) {
+    PlatformConfig->VrmProperties[i] = UserOptions.CfgPlatVrmCfg[i];
+  }
+  PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb;
+  PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0;
+  PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1;
+  PlatformConfig->GnbHdAudio = UserOptions.CfgGnbHdAudio;
+  PlatformConfig->AbmSupport = UserOptions.CfgAbmSupport;
+  PlatformConfig->DynamicRefreshRate = UserOptions.CfgDynamicRefreshRate;
+  PlatformConfig->LcdBackLightControl = UserOptions.CfgLcdBackLightControl;
+  if ((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) ||
+      (StdHeader->HeapStatus == HEAP_TEMP_MEM) ||
+      (StdHeader->HeapStatus == HEAP_SYSTEM_MEM)) {
+    IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h
new file mode 100644
index 0000000000..0a237d53cb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common initialization routines.
+ *
+ * Contains common initialization routines across AGESA entries of phases.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _COMMON_INITS_H_
+#define _COMMON_INITS_H_
+
+/**
+ * Common routine to initialize PLATFORM_CONFIGURATION.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+CommonPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+#endif // _COMMON_INITS_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonPage.h
new file mode 100644
index 0000000000..bcf787fff1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonPage.h
@@ -0,0 +1,143 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for Processor Common Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/**
+ * @page commonmain Processor Common Component Documentation
+ *
+ * Additional documentation for the Common component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS"
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+/**
+ * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS
+ * @par
+ * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code.
+ * <ul>
+ *
+ * <li>
+ * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named
+ * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a
+ * typedef of a function prototype) in AGESA code. Examples:
+ * @n @code
+ * VOID
+ *   LibAmdPciFindNextCap (
+ *     IN OUT   PCI_ADDR *Address,
+ *     IN       AMD_CONFIG_PARAMS *StdHeader
+ *     )
+ *
+ * typedef VOID F_DO_TABLE_ENTRY (
+ *   IN       TABLE_ENTRY_DATA       *CurrentEntry,
+ *   IN       PLATFORM_CONFIGURATION *PlatformConfig,
+ *   IN       AMD_CONFIG_PARAMS      *StdHeader
+ *   );
+ *
+ * @endcode
+ *
+ * <li>
+ * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples:
+ * @n @code
+   /// Example of struct member naming.
+ * typedef struct {
+ *   IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard Header
+ *   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+ * } AMD_CPU_RECOVERY_PARAMS;
+ *
+ * @endcode
+ *
+ * <li>
+ * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should
+ * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example:
+ * @n @code
+ * AMD_CONFIG_PARAMS *NewStdHeader;
+ * [...]
+ * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+ * @endcode
+ *
+ * <li>
+ * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not
+ * checked.  Freedom is allowed in order to conform to these guidelines in a practical, readable
+ * way.  This includes typecast arguments.  Examples:
+ * @n @code
+ * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event);
+ *
+ * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader);
+ * @endcode
+ *
+ * </ul>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
new file mode 100644
index 0000000000..973cfded21
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
@@ -0,0 +1,239 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Filecode.h"
+#include "CommonReturns.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+CommonFchInitStub (
+  IN       VOID       *DataPtr
+  );
+
+VOID
+FchTaskDummy (
+  IN       VOID       *DataPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return TRUE.
+*
+* @retval TRUE  Default case, no special action
+*/
+BOOLEAN
+CommonReturnTrue ( VOID )
+{
+  return TRUE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return False.
+*
+* @retval FALSE  Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse ( VOID )
+{
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 ( VOID )
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 ( VOID )
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 ( VOID )
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL ( VOID )
+{
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess ( VOID )
+{
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid ( VOID )
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert ( VOID )
+{
+  ASSERT (FALSE);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonFchInitStub (
+  IN       VOID       *DataPtr
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+
+VOID
+FchTaskDummy (
+  IN       VOID       *DataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c
new file mode 100644
index 0000000000..005dc2d529
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c
@@ -0,0 +1,340 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Input Structure Creation
+ *
+ * Contains AGESA input structure creation support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[];
+extern CONST UINTN InitializerCount;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocate and initialize Config headers and Service Interface structures.
+ *
+ * This function will be called for each AGESA public APIs.
+ * This function will do the following:
+ * -# Locate the AGESA API structure parameters initializer function information.
+ * -# Find the size of the structure that gets passed to each public APIs as
+ *    the entry parameter. Allocate heap space using the size for PreMemHeap, callout for
+ *    memory allocation for PostMemDram, and just set the config and service interface
+ *    pointers for ByHost.
+ * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams.
+ *    For ByHost, we're using the caller's existing config params.
+ * -# Call the initializer function, and pass a reference to the Config params and to
+ *    the Service Interface struct.  On return the constructor will have filled the
+ *    remaining structure with default values.
+ * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS
+ *    area (i.e. Fill *newStructPtr with the pointer to the newly created structure)
+ * -# Set the appropriate AGESA function number in the StdHeader member of the input
+ *    parameter structure.
+ *
+ * @param[in,out]  InterfaceParams         Pointer to structure containing the function call
+ *                                         whose parameter structure is to be created, the
+ *                                         allocation method, and a pointer to the newly
+ *                                         created structure.
+ *
+ * @retval         AGESA_SUCCESS           The interface struct is allocated and initialized.
+ * @retval         AGESA_UNSUPPORTED       The Service is not supported.
+ *
+ */
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  )
+{
+  UINTN                     ServiceIndex;
+  ALLOCATE_HEAP_PARAMS      AllocHeapParams;
+  AMD_CONFIG_PARAMS         *NewlyCreatedConfig;
+  VOID                      *NewlyCreatedServiceInterface;
+  AGESA_STATUS              AgesaStatus;
+  AGESA_STATUS              TempStatus;
+  AGESA_STATUS              IgnoredSts;
+  CPU_SPECIFIC_SERVICES     *FamilySpecificServices;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  ASSERT (InterfaceParams != NULL);
+
+  switch (InterfaceParams->AgesaFunctionName) {
+  case AMD_INIT_RESET:
+    if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) {
+      // APs must transfer their system core number from the mailbox to
+      // a local register while it is still valid.
+      GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &InterfaceParams->StdHeader);
+      FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader);
+    }
+    InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET;
+    break;
+  case AMD_INIT_EARLY:
+  case AMD_INIT_RECOVERY:
+  case AMD_INIT_RESUME:
+  case AMD_INIT_POST:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  case AMD_INIT_ENV:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+    break;
+  case AMD_INIT_LATE:
+  case AMD_INIT_MID:
+  case AMD_S3_SAVE:
+  case AMD_LATE_RUN_AP_TASK:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_S3LATE_RESTORE:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+    break;
+  default:
+    ASSERT (FALSE);
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  }
+
+  InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader);
+
+  if (InterfaceParams->AgesaFunctionName == AMD_INIT_RESET) {
+    AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader);
+  }
+
+  // Step 1
+  for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) {
+    if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
+      break;
+    }
+  }
+  if (ServiceIndex >= InitializerCount) {
+    // A call was made to AGESA with an invalid function number.  This wrapper error may be due to the build target
+    // not containing the desired entry point.
+    return AGESA_UNSUPPORTED;
+  }
+
+  // Step 2
+  LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader);
+
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    // Allocate one buffer to contain the config params and the service struct.
+    // The service struct begins immediately after the config params.
+    AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS);
+    AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader));
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+    NewlyCreatedConfig++;
+    NewlyCreatedServiceInterface =  NewlyCreatedConfig;
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+  } else {
+    // The caller (example, agesa basic interface implementation) already has a buffer to use.
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams;
+    NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr;
+    ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize);
+  }
+  ASSERT (NewlyCreatedConfig != NULL);
+  ASSERT (NewlyCreatedServiceInterface != NULL);
+
+  // Step 3
+  if (InterfaceParams->AllocationMethod != ByHost) {
+    *NewlyCreatedConfig = InterfaceParams->StdHeader;
+  }
+
+  // Step 4
+  TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface);
+  AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+
+  // Step 5
+  if (InterfaceParams->AllocationMethod != ByHost) {
+    InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface;
+    InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize;
+  }
+
+  // Step 6
+  ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName;
+  return AgesaStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Clears storage space from allocation for a parameter block of an
+ *  AGESA software call entry.
+ *
+ *  @param[in,out]  InterfaceParams         Pointer to structure containing the function call
+ *                                          whose parameter structure is to be deallocated.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  )
+{
+  UINT8 i;
+  UINT8 *BufferPtr;
+  VOID  *ServicePtr;
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  TempStatus;
+  LOCATE_HEAP_PTR LocHeap;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  switch (InterfaceParams->AgesaFunctionName) {
+  case AMD_INIT_RESET:
+  case AMD_INIT_EARLY:
+  case AMD_INIT_RECOVERY:
+  case AMD_INIT_RESUME:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  case AMD_INIT_POST:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+    break;
+  case AMD_INIT_ENV:
+  case AMD_INIT_LATE:
+  case AMD_INIT_MID:
+  case AMD_S3_SAVE:
+  case AMD_LATE_RUN_AP_TASK:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_S3LATE_RESTORE:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+    break;
+  default:
+    ASSERT (FALSE);
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  }
+
+  InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader);
+
+// Step 1
+  for (i = 0; i < InitializerCount; i++) {
+    if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
+      break;
+    }
+  }
+  if (i >= InitializerCount) {
+    return AGESA_BOUNDS_CHK;
+  }
+
+  // Step 2
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle;
+    if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) {
+      BufferPtr = (UINT8 *) LocHeap.BufferPtr;
+      ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)];
+      TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr);
+      AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+    }
+  }
+
+  // Step 3
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader));
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+  } else {
+    // Unless we define service specific destructors, nothing to do for ByHost.
+    return AGESA_SUCCESS;
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h
new file mode 100644
index 0000000000..ca1947df1a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h
@@ -0,0 +1,222 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD AGESA Input Structure Creation
+ *
+ * Contains AGESA input creation structures.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+#ifndef _CREATE_STRUCT_H_
+#define _CREATE_STRUCT_H_
+
+/**
+ * A constructor method.
+ *
+ * Sets inputs to valid, basic level, defaults for the specific service instance.
+ * Constructors should avoid using the header, since these routines should not
+ * do operations which may fail or require status back to the user.  The constructor
+ * should always SUCCEED.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   ServiceInterface  Service Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+typedef AGESA_STATUS
+F_AGESA_FUNCTION (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       VOID                 *ServiceInterface
+  );
+
+/// Reference to a Method.
+typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION;
+
+/**
+ * A Destructor method.
+ *
+ * Sets inputs to valid, basic level, defaults for the specific service instance.
+ * The constructor should always SUCCEED.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header.
+ * @param[in]   ServiceInterface  Service Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+typedef AGESA_STATUS
+F_AGESA_DESTRUCTOR (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       VOID                 *ServiceInterface
+  );
+
+/// Reference to a Method.
+typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR;
+
+/**
+ * Provide the information needed to invoke each service constructor.
+ */
+typedef struct {
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< Identifies the service
+  IN       UINT16              CreateStructSize;   ///< The service's input struct size.
+                                                   ///  Do NOT include a config params header!
+     OUT   PF_AGESA_FUNCTION   AgesaFunction;      ///< The constructor function
+     OUT   PF_AGESA_DESTRUCTOR AgesaDestructor;    ///< The destructor function.
+  IN       AGESA_BUFFER_HANDLE BufferHandle;       ///< The buffer handle id for the service.
+} FUNCTION_PARAMS_INFO;
+
+/**
+ * All available services have their constructor info here.
+ */
+AGESA_STATUS
+AmdInitResetConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_RESET_PARAMS     *AmdResetParams
+  );
+
+AGESA_STATUS
+AmdInitRecoveryInitializer (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN OUT   AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  );
+
+AGESA_STATUS
+AmdInitPostInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_POST_PARAMS *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitPostDestructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_POST_PARAMS      *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitEnvInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_ENV_PARAMS *EnvParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitMidInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_MID_PARAMS *MidParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitLateInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_LATE_PARAMS *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitLateDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_LATE_PARAMS   *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitResumeInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  );
+
+AGESA_STATUS
+AmdInitResumeDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  );
+
+AGESA_STATUS
+AmdS3SaveInitializer (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  );
+
+AGESA_STATUS
+AmdS3SaveDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  );
+
+AGESA_STATUS
+AmdS3LateRestoreInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  );
+
+AGESA_STATUS
+AmdLateRunApTaskInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AP_EXE_PARAMS     *AmdApExeParams
+  );
+#endif // _CREATE_STRUCT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
new file mode 100644
index 0000000000..f57d73080e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
@@ -0,0 +1,468 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * S3 save/restore script
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern S3_SCRIPT_CONFIGURATION    OptionS3ScriptConfiguration;
+extern S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable[];
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+AGESA_STATUS
+STATIC
+S3RestoreStateFromTable (
+  IN      S3_SAVE_TABLE_HEADER  *S3SaveTablePtr,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestore (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return OptionS3ScriptConfiguration.Restore (StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestoreStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestoreState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  S3_SAVE_TABLE_HEADER  *S3SaveTablePtr;
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    IDS_ERROR_TRAP;
+    return  AGESA_FATAL;
+  }
+  S3SaveTablePtr->Locked = TRUE;
+  Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] S3SaveTablePtr     Pointer to S3 Save Table
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+STATIC
+S3RestoreStateFromTable (
+  IN      S3_SAVE_TABLE_HEADER  *S3SaveTablePtr,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  VOID                  *S3SaveTableRecordPtr;
+  PCI_ADDR              PciAddress;
+  UINTN                 Index;
+  S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER);
+  IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+  while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) {
+    switch  (*(UINT16 *) S3SaveTableRecordPtr) {
+    case  SAVE_STATE_IO_WRITE_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+      LibAmdIoWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_IO_READ_WRITE_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+      LibAmdIoRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_WRITE_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+     LibAmdMemWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_READ_WRITE_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+      LibAmdMemRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+      LibAmdPciWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+      LibAmdPciRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_STALL_OPCODE:
+      break;
+    case  SAVE_STATE_INFORMATION_OPCODE:
+      IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: Info: [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER));
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                             sizeof (S3_INFO_OP_HEADER) +
+                             ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length;
+      break;
+    case  SAVE_STATE_DISPATCH_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Function Id: 0x%02x, Context: ",  S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)),
+          ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length,
+          AccessWidth8);
+        IDS_HDT_CONSOLE (S3_TRACE, "\n");
+        );
+      Index = 0;
+      while (S3DispatchFunctionTable[Index].FunctionId != 0) {
+        if (S3DispatchFunctionTable[Index].FunctionId == ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId) {
+          (S3DispatchFunctionTable[Index].Function) (
+            StdHeader,
+            ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length,
+            (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER))
+            );
+          break;
+        }
+        Index++;
+      }
+      ASSERT (S3DispatchFunctionTable[Index].FunctionId != 0);
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                             sizeof (S3_DISPATCH_OP_HEADER) +
+                             ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length;
+      break;
+
+    case  SAVE_STATE_IO_POLL_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%04x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+          1,
+          ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+          1,
+          ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        )
+      LibAmdIoPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_POLL_OPCODE:
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+          1,
+          ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+          1,
+          ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        )
+      LibAmdMemPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      S3_SCRIPT_DEBUG_CODE (
+        IDS_HDT_CONSOLE (S3_TRACE, "  S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address);
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+          1,
+          ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+        S3SaveDebugPrintHexArray (
+          StdHeader,
+          (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+          1,
+          ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
+          );
+        )
+      LibAmdPciPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    default:
+      IDS_HDT_CONSOLE (S3_TRACE, " ERROR!!! Invalid S3 restore opcode\n");
+      ASSERT (FALSE);
+      return AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
new file mode 100644
index 0000000000..e147875d3f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
@@ -0,0 +1,678 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * S3 save/restore script
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+S3SaveStateExtendTableLenth (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInit (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return OptionS3ScriptConfiguration.Init (StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInitStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInitState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status == AGESA_SUCCESS) {
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH;
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER);
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->Locked = FALSE;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in]     StdHeader          Pointer to standard header
+ * @param[in,out] S3SaveTable        S3 save table header
+ */
+AGESA_STATUS
+S3SaveStateExtendTableLenth (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+  VOID                  *TempBuffer;
+  UINT16                NewTableLength;
+  UINT16                CurrentTableLength;
+  //Allocate temporary buffer
+  NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT;
+  AllocHeapParams.RequestedBufferSize = NewTableLength;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  //Save current table length
+  CurrentTableLength = (*S3SaveTable)->TableLength;
+  //Update table length
+  (*S3SaveTable)->TableLength = NewTableLength;
+  //Copy S3 save toable to temporary location
+  LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader);
+  //Save pointer to temp buffer
+  TempBuffer = AllocHeapParams.BufferPtr;
+  // Free original S3 save buffer
+  HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader);
+
+  AllocHeapParams.RequestedBufferSize = NewTableLength;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader);
+  *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr;
+  HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in]  StdHeader          Pointer to standard header
+ * @param[out] S3SaveTable        S3 save table header
+ */
+AGESA_STATUS
+S3ScriptGetS3SaveTable (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  )
+{
+  AGESA_STATUS          Status;
+  LOCATE_HEAP_PTR       LocHeapParams;
+  LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    *S3SaveTable = NULL;
+    return Status;
+  }
+  *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 write opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Count              Number of register writes
+ * @param[in] Buffer             Pointer to write buffer
+ */
+AGESA_STATUS
+S3SaveStateSaveWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      UINT32              Count,
+  IN      VOID                *Buffer
+  )
+{
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_WRITE_OP_HEADER      *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  if (S3SaveTablePtr->Locked) {
+    return  AGESA_UNSUPPORTED;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  S3_SCRIPT_DEBUG_CODE (
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
+    S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width);
+    IDS_HDT_CONSOLE (S3_TRACE, "\n");
+    );
+  SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Count = Count;
+  SaveOffsetPtr->Address = Address;
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER),
+    Buffer,
+    WidthLength * Count,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 write opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Data               Pointer to data
+ * @param[in] DataMask           Pointer data mask
+ */
+AGESA_STATUS
+S3SaveStateSaveReadWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_READ_WRITE_OP_HEADER *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  if (S3SaveTablePtr->Locked) {
+    return  AGESA_UNSUPPORTED;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  S3_SCRIPT_DEBUG_CODE (
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
+    S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
+    IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+    S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
+    IDS_HDT_CONSOLE (S3_TRACE, "\n");
+    );
+  SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Address = Address;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+    Data,
+    WidthLength,
+    StdHeader
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength,
+    DataMask,
+    WidthLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 poll opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Data               Pointer to data
+ * @param[in] DataMask           Pointer data mask
+ * @param[in] Delay              Time delay for poll
+ */
+AGESA_STATUS
+S3SaveStateSavePollOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask,
+  IN      UINT64              Delay
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_POLL_OP_HEADER       *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  if (S3SaveTablePtr->Locked) {
+    return  AGESA_UNSUPPORTED;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  S3_SCRIPT_DEBUG_CODE (
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
+    S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
+    IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
+    S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
+    IDS_HDT_CONSOLE (S3_TRACE, "\n");
+    );
+  SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Delay = Delay;
+  SaveOffsetPtr->Address = Address;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER),
+    Data,
+    WidthLength,
+    StdHeader
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength,
+    DataMask,
+    WidthLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 info opcode
+ *
+ *
+ *
+ * @param[in] StdHeader               Pointer to standard header
+ * @param[in] OpCode                  Operation opcode
+ * @param[in] InformationLength       Info length
+ * @param[in] Information             Pointer to information
+ */
+AGESA_STATUS
+S3SaveStateSaveInfoOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT32              InformationLength,
+  IN      VOID                *Information
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_INFO_OP_HEADER       *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  if (S3SaveTablePtr->Locked) {
+    return  AGESA_UNSUPPORTED;
+  }
+  OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Length = InformationLength;
+  S3_SCRIPT_DEBUG_CODE (
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: Info: %s \n", Information);
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
+    Information,
+    InformationLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 dispatch opcode
+ *
+ *
+ *
+ * @param[in] StdHeader               Pointer to standard header
+ * @param[in] OpCode                  Operation opcode
+ * @param[in] FunctionId              Function ID
+ * @param[in] ContextLength           Context length
+ * @param[in] Context                 Pointer to Context
+ */
+AGESA_STATUS
+S3SaveStateSaveDispatchOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT16              FunctionId,
+  IN      UINT16              ContextLength,
+  IN      VOID                *Context
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_DISPATCH_OP_HEADER   *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  if (S3SaveTablePtr->Locked) {
+    return  AGESA_UNSUPPORTED;
+  }
+  OpCodeLength = sizeof (S3_DISPATCH_OP_HEADER) + ContextLength;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  S3_SCRIPT_DEBUG_CODE (
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Function Id: 0x%02x, Context: ",  S3SaveDebugOpcodeString (StdHeader, OpCode), FunctionId);
+    S3SaveDebugPrintHexArray (StdHeader, Context, ContextLength, AccessWidth8);
+    IDS_HDT_CONSOLE (S3_TRACE, "\n");
+    );
+  SaveOffsetPtr = (S3_DISPATCH_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Length = ContextLength;
+  SaveOffsetPtr->FunctionId = FunctionId;
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_DISPATCH_OP_HEADER),
+    Context,
+    ContextLength,
+    StdHeader
+    );
+
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 debug support
+ *
+ *
+ *
+ * @param[in] StdHeader               Pointer to standard header
+ * @param[in] Op                      Opcode
+ */
+CHAR8*
+S3SaveDebugOpcodeString (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              Op
+  )
+{
+  switch (Op) {
+  case SAVE_STATE_IO_WRITE_OPCODE:
+    return (CHAR8 *)"IO WR";
+  case SAVE_STATE_IO_READ_WRITE_OPCODE:
+    return (CHAR8 *)"IO RD/WR";
+  case SAVE_STATE_IO_POLL_OPCODE:
+    return (CHAR8 *)"IO POLL";
+  case SAVE_STATE_MEM_WRITE_OPCODE:
+    return (CHAR8 *)"MEM WR";
+  case SAVE_STATE_MEM_READ_WRITE_OPCODE:
+    return (CHAR8 *)"MEM RD/WR";
+  case SAVE_STATE_MEM_POLL_OPCODE:
+    return (CHAR8 *)"MEM POLL";
+  case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
+    return (CHAR8 *)"PCI WR";
+  case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
+    return (CHAR8 *)"PCI RD/WR";
+  case SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
+    return (CHAR8 *)"PCI POLL";
+  case SAVE_STATE_STALL_OPCODE:
+    return (CHAR8 *)"STALL";
+  case SAVE_STATE_DISPATCH_OPCODE:
+    return (CHAR8 *)"DISPATCH";
+  default:
+    IDS_ERROR_TRAP;
+  }
+  return (CHAR8 *)"!!! Unrecognize opcode !!!";
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 debug support
+ *
+ *
+ *
+ * @param[in] StdHeader               Pointer to standard header
+ * @param[in] Array                   Array
+ * @param[in] Count                   Count of element in array
+ * @param[in] Width                   Array Element width
+ */
+VOID
+S3SaveDebugPrintHexArray (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      VOID                *Array,
+  IN      UINT32              Count,
+  IN      ACCESS_WIDTH        Width
+  )
+{
+  UINTN  Index;
+
+  for (Index = 0; Index < Count; Index++) {
+    switch (Width) {
+    case AccessWidth8:
+    case AccessS3SaveWidth8:
+      IDS_HDT_CONSOLE (S3_TRACE, "0x%02x", *((UINT8*)Array + Index));
+      break;
+    case AccessWidth16:
+    case AccessS3SaveWidth16:
+      IDS_HDT_CONSOLE (S3_TRACE, "0x%04x", *((UINT16*)Array + Index));
+      break;
+    case AccessWidth32:
+    case AccessS3SaveWidth32:
+      IDS_HDT_CONSOLE (S3_TRACE, "0x%08x", *((UINT32*)Array + Index));
+      break;
+    case AccessWidth64:
+    case AccessS3SaveWidth64:
+      //IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0]));
+      break;
+    default:
+      IDS_ERROR_TRAP;
+    }
+    if (Index < (Count - 1)) {
+      IDS_HDT_CONSOLE (S3_TRACE, ", ");
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h
new file mode 100644
index 0000000000..7eb76dd9f9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h
@@ -0,0 +1,389 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _S3SAVESTATE_H_
+#define _S3SAVESTATE_H_
+
+#pragma pack (push, 1)
+
+#ifndef S3_SCRIPT_DEBUG_CODE
+  #define S3_SCRIPT_DEBUG_CODE(Code) Code
+#endif
+
+/// Dispatch function ID repository
+typedef enum {
+  NbSmuIndirectWriteS3Script_ID = 1,           ///< GNB SMU service request function ID.
+  NbSmuServiceRequestS3Script_ID,              ///< GNB PCIe late restore function ID.
+  PcieLateRestoreS3Script_ID,                  ///< GNB SMU indirect write.
+  GnbSmuServiceRequestV4S3Script_ID,           ///< SMU service request
+  GnbLibStallS3Script_ID,                      ///< Stall request
+  PcieLateRestoreTNS3Script_ID,                ///< GNB PCIe late restore TN
+  PcieLateRestoreKMS3Script_ID,                ///< GNB PCIe late restore KM
+  PcieLateRestoreTHS3Script_ID,                ///< GNB PCIe late restore KM
+  GfxRequestSclkTNS3Script_ID                  ///< SCLk setting
+} S3_DISPATCH_FUNCTION_ID;
+
+#define SAVE_STATE_IO_WRITE_OPCODE              0x00
+#define SAVE_STATE_IO_READ_WRITE_OPCODE         0x01
+#define SAVE_STATE_MEM_WRITE_OPCODE             0x02
+#define SAVE_STATE_MEM_READ_WRITE_OPCODE        0x03
+#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE      0x04
+#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05
+#define SAVE_STATE_STALL_OPCODE                 0x07
+#define SAVE_STATE_INFORMATION_OPCODE           0x0A
+#define SAVE_STATE_IO_POLL_OPCODE               0x0D
+#define SAVE_STATE_MEM_POLL_OPCODE              0x0E
+#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE       0x0F
+#define SAVE_STATE_DISPATCH_OPCODE              0x20
+#define SAVE_STATE_BREAKPOINT_OPCODE            0x21
+
+
+#define S3_TABLE_LENGTH             8 * 1024
+#define S3_TABLE_LENGTH_INCREMENT   1 * 1024
+
+/// S3 Save Table
+typedef struct {
+  UINT16                      TableLength;        ///< Table Length
+  UINT32                      SaveOffset;         ///< Save Location
+  BOOLEAN                     Locked;             ///< Locked
+} S3_SAVE_TABLE_HEADER;
+
+/// S3 write operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register address
+  UINT32                      Count;              ///< Write count
+} S3_WRITE_OP_HEADER;
+
+/// S3 Read and Write Operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register Address
+} S3_READ_WRITE_OP_HEADER;
+
+/// S3 Poll operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register address
+  UINT64                      Delay;              ///< Time delay
+} S3_POLL_OP_HEADER;
+
+/// Information operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  UINT32                      Length;             ///< Length of info
+} S3_INFO_OP_HEADER;
+
+/// Dispatch operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  UINT16                      FunctionId;         ///< Function ID
+  UINT16                      Length;             ///< Length in bytes of the context
+} S3_DISPATCH_OP_HEADER;
+
+
+typedef VOID S3_DISPATCH_FUNCTION (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      UINT16                ContextLength,
+  IN      VOID                  *Context
+  );
+
+/// Dispatch function table entry
+typedef struct {
+  UINT16                        FunctionId;         ///<Function ID
+  S3_DISPATCH_FUNCTION          *Function;          ///<Function pointer
+} S3_DISPATCH_FUNCTION_ENTRY;
+
+typedef AGESA_STATUS (*S3_SCRIPT_INIT) (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+typedef AGESA_STATUS (*S3_SCRIPT_RESTORE) (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/// S3 Script Configuration
+typedef struct {
+  S3_SCRIPT_INIT              Init;               ///< Script initialization
+  S3_SCRIPT_RESTORE           Restore;            ///< Script restore
+} S3_SCRIPT_CONFIGURATION;
+
+AGESA_STATUS
+S3ScriptInit (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInitState (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInitStateStub (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestore (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestoreState (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestoreStateStub (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptGetS3SaveTable (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  OUT     S3_SAVE_TABLE_HEADER  **S3SaveTable
+  );
+
+VOID
+S3SaveDebugPrintHexArray (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      VOID                  *Array,
+  IN      UINT32                Count,
+  IN      ACCESS_WIDTH          Width
+  );
+
+CHAR8*
+S3SaveDebugOpcodeString (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      UINT16                Op
+  );
+
+AGESA_STATUS
+S3SaveStateSaveWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      UINT32              Count,
+  IN      VOID                *Buffer
+  );
+
+AGESA_STATUS
+S3SaveStateSaveReadWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask
+  );
+
+AGESA_STATUS
+S3SaveStateSavePollOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask,
+  IN      UINT64              Delay
+  );
+
+AGESA_STATUS
+S3SaveStateSaveInfoOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT32              InformationLength,
+  IN      VOID                *Information
+  );
+
+AGESA_STATUS
+S3SaveStateSaveDispatchOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT16              FunctionId,
+  IN      UINT16              ContextLength,
+  IN      VOID                *Context
+  );
+
+//PCI write
+#define S3_SAVE_PCI_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_WRITE_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    1,  \
+    DataPtr  \
+    )
+
+//PCI read modify write
+#define S3_SAVE_PCI_RMW (StdHeader, Address, Width, DataPtr, DataMaskPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    DataPtr,  \
+    DataMask  \
+    )
+
+//PCI read modify write
+#define S3_SAVE_PCI_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
+  S3SaveStateSavePollOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_POLL_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    DataPtr,  \
+    DataMask,  \
+    Delay  \
+    )
+
+//Memory/MMIO write
+#define S3_SAVE_MEM_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    1,  \
+    DataPtr  \
+    )
+
+//Memory/MMIO read modify write
+#define S3_SAVE_MEM_RMW(StdHeader, Address, Width, DataPtr, DataMaskPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    DataPtr,  \
+    DataMask  \
+    )
+
+//Memory/MMIO read modify write
+#define S3_SAVE_MEM_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
+  S3SaveStateSavePollOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_POLL_OPCODE,  \
+    Width,  \
+    Address, \
+    DataPtr,  \
+    DataMask,  \
+    Delay \
+    )
+
+// I/O write
+#define S3_SAVE_IO_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_IO_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    1,  \
+    DataPtr  \
+    )
+
+// Save information
+#define S3_SAVE_INFORMATION(StdHeader, InformationLength, Information) \
+  S3SaveStateSaveInfoOp (  \
+    StdHeader,  \
+    SAVE_STATE_INFORMATION_OPCODE,  \
+    InformationLength,  \
+    Information \
+    )
+
+// Save information string S3_SAVE_INFORMATION_STRING (StdHeader, "Message")
+#define S3_SAVE_INFORMATION_STRING(StdHeader, Information) \
+  S3SaveStateSaveInfoOp (  \
+    StdHeader,  \
+    SAVE_STATE_INFORMATION_OPCODE,  \
+    sizeof (Information),  \
+    Information \
+    )
+
+// Save dispatch function
+#define S3_SAVE_DISPATCH(StdHeader, FunctionId, ContextLength, Context) \
+  S3SaveStateSaveDispatchOp (  \
+    StdHeader,  \
+    SAVE_STATE_DISPATCH_OPCODE,  \
+    FunctionId, \
+    ContextLength,  \
+    Context \
+    )
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c
new file mode 100644
index 0000000000..cf5bfc6576
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c
@@ -0,0 +1,108 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH HD Audio Controller
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE (0xB002)
+//
+// Declaration of local functions
+//
+
+/**
+ *
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+Fchdef178  (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Azalia.AzaliaEnable == hdaconf1  ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, BIT0);
+    RwPci ((((0x14<<3)+2)  << 16) + FCH_AZ_REG4C, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader);
+
+    if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) {
+      RwPci ((((0x14<<3)+2)  << 16) + FCH_AZ_REG44, AccessWidth32, (UINT32)~BIT8, BIT8, StdHeader);
+      RwPci ((((0x14<<3)+2)  << 16) + FCH_AZ_REG60, AccessWidth32, (UINT32)~BIT16, BIT16, StdHeader);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
new file mode 100644
index 0000000000..37acfc65f8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH HD Audio Controller
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE (0xB004)
+
+/**
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+Fchdef180  (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
new file mode 100644
index 0000000000..65c5e5928a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH HD Audio Controller
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE (0xB003)
+//
+// Declaration of local functions
+//
+
+
+
+
+
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
new file mode 100644
index 0000000000..d10857e8a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH HD Audio Controller
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE (0xB001)
+
+/**
+ *
+ *
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+Fchdef174  (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c
new file mode 100644
index 0000000000..bd94fae296
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c
@@ -0,0 +1,270 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH ACPI lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_ACPILIB_FILECODE
+//
+//
+// Routine Description:
+//
+//  Locate ACPI table
+//
+// Arguments:
+//
+//  Signature - table signature
+//
+//Returns:
+//
+//  pointer to ACPI table
+//
+//
+VOID*
+AcpiLocateTable (
+  IN  UINT32     Signature
+  )
+{
+  UINT32              Index;
+  UINT32              *RsdPtr;
+  UINT32              *Rsdt;
+  UINTN               TableOffset;
+  DESCRIPTION_HEADER  *CurrentTable;
+
+  RsdPtr = (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_LOW;
+  Rsdt = NULL;
+  do {
+      if ( *RsdPtr == Int32FromChar('R','S','D',' ') && *(RsdPtr + 1) == Int32FromChar('P','T','R',' ') ) { /* ' DSR' & ' RTP' */
+      Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress;
+      break;
+    }
+    RsdPtr += 4;
+  } while ( RsdPtr <= (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_HIGH );
+
+  if ( Rsdt != NULL && AcpiGetTableCheckSum (Rsdt) == 0 ) {
+    for ( Index = 0; Index < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; Index++ ) {
+      TableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + Index * 4);
+      CurrentTable = (DESCRIPTION_HEADER*)TableOffset;
+      if ( CurrentTable->Signature == Signature ) {
+        return CurrentTable;
+      }
+    }
+  }
+  return NULL;
+}
+
+//
+//
+//  Routine Description:
+//
+//  Update table CheckSum
+//
+//  Arguments:
+//
+//  TablePtr - table pointer
+//
+//  Returns:
+//
+//  none
+//
+//
+VOID
+AcpiSetTableCheckSum (
+  IN  VOID     *TablePtr
+  )
+{
+  UINT8   CheckSum;
+
+  CheckSum = 0;
+  ((DESCRIPTION_HEADER*)TablePtr)->CheckSum = 0;
+  CheckSum = AcpiGetTableCheckSum (TablePtr);
+  ((DESCRIPTION_HEADER*)TablePtr)->CheckSum = (UINT8) (FCHOEM_ACPI_BYTE_CHECHSUM - CheckSum);
+}
+
+//
+//
+//  Routine Description:
+//
+//  Get table CheckSum - Get ACPI table checksum
+//
+//  Arguments:
+//
+//  TablePtr - table pointer
+//
+//  Returns:
+//
+//  none
+//
+//
+UINT8
+AcpiGetTableCheckSum (
+  IN  VOID     *TablePtr
+  )
+{
+  return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
+}
+
+
+//
+//
+//  Routine Description:
+//
+//  GetByteSum - Get BYTE checksum value
+//
+//  Arguments:
+//
+//  DataPtr - table pointer
+//  Length  - table length
+//
+//  Returns:
+//
+//  CheckSum - CheckSum value
+//
+//
+UINT8
+GetByteSum (
+  IN  VOID       *DataPtr,
+  IN  UINT32     Length
+  )
+{
+  UINT32   Index;
+  UINT8    CheckSum;
+
+  CheckSum = 0;
+  for ( Index = 0; Index < Length; Index++ ) {
+    CheckSum = CheckSum + (*((UINT8*)DataPtr + Index));
+  }
+  return CheckSum;
+}
+
+//
+//
+//  Routine Description:
+//
+//  GetFchAcpiMmioBase - Get FCH HwAcpi MMIO Base Address
+//
+//  Arguments:
+//
+//  AcpiMmioBase - HwAcpi MMIO Base Address
+//  StdHeader    - Amd Stand Header
+//
+//  Returns:
+//
+//  AcpiMmioBase - HwAcpi MMIO Base Address
+//
+//
+VOID
+GetFchAcpiMmioBase (
+     OUT   UINT32                *AcpiMmioBase,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    AcpiMmioBaseAddressDword;
+
+  ReadPmio (FCH_PMIOA_REG24 + 2, AccessWidth16, &AcpiMmioBaseAddressDword, StdHeader);
+  *AcpiMmioBase = AcpiMmioBaseAddressDword << 16;
+}
+
+//
+//
+//  Routine Description:
+//
+//  GetFchAcpiPmBase - Get FCH HwAcpi PM Base Address
+//
+//  Arguments:
+//
+//  AcpiPmBase   - HwAcpi PM Base Address
+//  StdHeader    - Amd Stand Header
+//
+//  Returns:
+//
+//  AcpiPmBase   - HwAcpi PM Base Address
+//
+//
+VOID
+GetFchAcpiPmBase (
+     OUT   UINT16                *AcpiPmBase,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  ReadPmio (FCH_PMIOA_REG60, AccessWidth16, AcpiPmBase, StdHeader);
+}
+
+
+UINT8
+ReadFchSleepType (
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT16     Value16;
+
+  ReadPmio (FCH_PMIOA_REG62, AccessWidth16, &Value16, StdHeader);
+  LibAmdIoRead (AccessWidth16, Value16, &Value16, StdHeader);
+  return (UINT8) ((Value16 >> 10) & 7);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.h
new file mode 100644
index 0000000000..44461899cb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.h
@@ -0,0 +1,114 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH ACPI lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+///
+/// RSDP - ACPI 2.0 table RSDP
+///
+typedef struct _RSDP_HEADER {
+  UINT64               Signature;                      ///< RSDP signature "RSD PTR"
+  UINT8                CheckSum;                       ///< checksum of the first 20 bytes
+  UINT8                OEMID[6];                       ///< OEM ID
+  UINT8                Revision;                       ///< 0 for APCI 1.0, 2 for ACPI 2.0
+  UINT32               RsdtAddress;                    ///< physical address of RSDT
+  UINT32               Length;                         ///< total length of RSDP (including extended part)
+  UINT64               XsdtAddress;                    ///< physical address of XSDT
+  UINT8                ExtendedCheckSum;               ///< chechsum of whole table
+  UINT8                Reserved[3];                    ///< Reserved
+} RSDP_HEADER;
+
+///
+/// DESCRIPTION_HEADER - ACPI common table header
+///
+typedef struct _DESCRIPTION_HEADER {
+  UINT32               Signature;                      ///< ACPI signature (4 ASCII characters)
+  UINT32               Length;                         ///< Length of table, in bytes, including header
+  UINT8                Revision;                       ///< ACPI Specification minor version #
+  UINT8                CheckSum;                       ///< To make sum of entire table == 0
+  UINT8                OemId[6];                       ///< OEM identification
+  UINT8                OemTableId[8];                  ///< OEM table identification
+  UINT32               OemRevision;                    ///< OEM revision number
+  UINT32               CreatorId;                      ///< ASL compiler vendor ID
+  UINT32               CreatorRevision;                ///< ASL compiler revision number
+} DESCRIPTION_HEADER;
+
+///
+/// _AcpiRegWrite - ACPI MMIO register R/W structure
+///
+typedef struct _ACPI_REG_WRITE {
+  UINT8        MmioBase;               /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
+  UINT8        MmioReg;                /// MmioReg      : Register index
+  UINT8        DataAndMask;            /// DataANDMask  : AND Register Data
+  UINT8        DataOrMask;             /// DataOrMask   : Or Register Data
+} ACPI_REG_WRITE;
+
+VOID*     AcpiLocateTable (IN UINT32 Signature);
+VOID      AcpiSetTableCheckSum (IN VOID *TablePtr);
+UINT8     AcpiGetTableCheckSum (IN VOID *TablePtr);
+UINT8     GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h
new file mode 100644
index 0000000000..c614936bd7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH BIOS Ram usage
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#ifndef _FCH_BIOS_RAM_USAGE_H_
+#define _FCH_BIOS_RAM_USAGE_H_
+
+#define RESTORE_MEMORY_CONTROLLER_START       0
+#define XHCI_REGISTER_BAR00                   0xD0
+#define XHCI_REGISTER_BAR01                   0xD1
+#define XHCI_REGISTER_BAR02                   0xD2
+#define XHCI_REGISTER_BAR03                   0xD3
+#define XHCI_REGISTER_04H                     0xD4
+#define XHCI_REGISTER_0CH                     0xD5
+#define XHCI_REGISTER_3CH                     0xD6
+#define XHCI1_REGISTER_BAR00                  0xE0
+#define XHCI1_REGISTER_BAR01                  0xE1
+#define XHCI1_REGISTER_BAR02                  0xE2
+#define XHCI1_REGISTER_BAR03                  0xE3
+#define XHCI1_REGISTER_04H                    0xE4
+#define XHCI1_REGISTER_0CH                    0xE5
+#define XHCI1_REGISTER_3CH                    0xE6
+#define RTC_WORKAROUND_DATA_START             0xF0
+#define BOOT_TIME_FLAG_SEC                    0xF8
+#define BOOT_TIME_FLAG_INT19                  0xFC
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c
new file mode 100644
index 0000000000..732e71337a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH common
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "heapManager.h"
+#define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h
new file mode 100644
index 0000000000..34805bb6d5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h
@@ -0,0 +1,1187 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Function Support Definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
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+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
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+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#ifndef _FCH_COMMON_CFG_H_
+#define _FCH_COMMON_CFG_H_
+
+#pragma pack (push, 1)
+
+//-----------------------------------------------------------------------------
+//                     FCH DEFINITIONS AND MACROS
+//-----------------------------------------------------------------------------
+
+//
+// FCH Component Data Structure Definitions
+//
+
+/// PCI_ADDRESS - PCI access structure
+#define PCI_ADDRESS(bus, dev, func, reg) \
+                   (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+///
+///  - Byte Register R/W structure
+///
+typedef struct _REG8_MASK {
+  UINT8                 RegIndex;                       /// RegIndex - Reserved
+  UINT8                 AndMask;                        /// AndMask - Reserved
+  UINT8                 OrMask;                         /// OrMask - Reserved
+} REG8_MASK;
+
+
+///
+/// PCIE Reset Block
+///
+typedef enum {
+  NbBlock,                                              ///< Reset for NB PCIE
+  FchBlock                                              ///< Reset for FCH GPP
+} RESET_BLOCK;
+
+///
+/// PCIE Reset Operation
+///
+typedef enum {
+  DeassertReset,                                        ///< DeassertRese - Deassert reset
+  AssertReset                                           ///< AssertReset - Assert reset
+} RESET_OP;
+
+
+///
+/// SD structure
+///
+typedef struct {
+  SD_MODE               SdConfig;                       ///< SD Mode configuration
+                                                        ///   @li <b>00</b> - Disabled
+                                                        ///   @li <b>00</b> - AMDA,  set 24,18,16,  default
+                                                        ///   @li <b>01</b> - DMA clear 24, 16, set 18
+                                                        ///   @li <b>10</b> - PIO clear 24,18,16
+                                                        ///
+  UINT8                 SdSpeed;                        ///< SD Speed
+                                                        ///   @li <b>0</b> - Low speed clear 17
+                                                        ///   @li <b>1</b> - High speed, set 17, default
+                                                        ///
+  UINT8                 SdBitWidth;                     ///< SD Bit Width
+                                                        ///   @li <b>0</b> - 32BIT clear 23
+                                                        ///   @li <b>1</b> - 64BIT, set 23,default
+                                                        ///
+  UINT32                SdSsid;                         ///< SD Subsystem ID
+  SD_CLOCK_CONTROL      SdClockControl;                 ///< SD Clock Control
+  BOOLEAN               SdClcokMultiplier;              ///< SD Clock Multiplier enable/disable
+  UINT8                 SdReTuningMode;                 ///< SD Re-tuning modes select
+                                                        ///    @li <b>0</b> - mode 1
+                                                        ///    @li <b>1</b> - mode 2
+                                                        ///    @li <b>2</b> - mode 3
+  UINT8                 SdHostControllerVersion;        ///< SD controller Version
+                                                        ///    @li <b>1</b> - SD 2.0
+                                                        ///    @li <b>2</b> - SD 3.0
+} FCH_SD;
+
+///
+/// CODEC_ENTRY - Fch HD Audio OEM Codec structure
+///
+typedef struct _CODEC_ENTRY {
+  UINT8                 Nid;                            /// Nid - Reserved
+  UINT32                Byte40;                         /// Byte40 - Reserved
+} CODEC_ENTRY;
+
+///
+/// CODEC_TBL_LIST - Fch HD Audio Codec table list
+///
+typedef struct _CODEC_TBL_LIST {
+  UINT32                CodecId;                        /// CodecID - Codec ID
+  CODEC_ENTRY*          CodecTablePtr;                  /// CodecTablePtr - Codec table pointer
+} CODEC_TBL_LIST;
+
+///
+/// AZALIA_PIN - HID Azalia or GPIO define structure.
+///
+typedef struct _AZALIA_PIN {
+  UINT8                 AzaliaSdin0;                    ///< AzaliaSdin0
+                                                        ///   @par
+                                                        ///   @li <b>00</b> - GPIO PIN
+                                                        ///   @li <b>10</b> - As a Azalia SDIN pin
+
+  UINT8                 AzaliaSdin1;                    ///< AzaliaSdin1
+                                                        ///   @par
+                                                        /// SDIN1 is define at BIT2 & BIT3
+                                                        ///   @li <b>00</b> - GPIO PIN
+                                                        ///   @li <b>10</b> - As a Azalia SDIN pin
+
+  UINT8                 AzaliaSdin2;                    ///< AzaliaSdin2
+                                                        ///   @par
+                                                        /// SDIN2 is define at BIT4 & BIT5
+                                                        ///   @li <b>00</b> - GPIO PIN
+                                                        ///   @li <b>10</b> - As a Azalia SDIN pin
+
+  UINT8                 AzaliaSdin3;                    ///< AzaliaSdin3
+                                                        ///   @par
+                                                        /// SDIN3 is define at BIT6 & BIT7
+                                                        ///   @li <b>00</b> - GPIO PIN
+                                                        ///   @li <b>10</b> - As a Azalia SDIN pin
+} AZALIA_PIN;
+
+///
+/// Azalia structure
+///
+typedef struct {
+  HDA_CONFIG            AzaliaEnable;                   ///< AzaliaEnable       - Azalia function configuration
+  BOOLEAN               AzaliaMsiEnable;                ///< AzaliaMsiEnable    - Azalia MSI capability
+  UINT32                AzaliaSsid;                     ///< AzaliaSsid         - Azalia Subsystem ID
+  UINT8                 AzaliaPinCfg;                   ///< AzaliaPinCfg       - Azalia Controller SDIN pin Configuration
+                                                        ///  @par
+                                                        ///  @li <b>0</b>       - disable
+                                                        ///  @li <b>1</b>       - enable
+
+  UINT8                 AzaliaFrontPanel;               ///< AzaliaFrontPanel   - Azalia Controller Front Panel Configuration
+                                                        ///   @par
+                                                        /// Support Front Panel configuration
+                                                        ///   @li <b>0</b>      - Auto
+                                                        ///   @li <b>1</b>      - disable
+                                                        ///   @li <b>2</b>      - enable
+
+  UINT8                 FrontPanelDetected;             ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
+                                                        ///  @par
+                                                        /// Force Front Panel configuration
+                                                        ///  @li <b>0</b>       - Not Detected
+                                                        ///  @li <b>1</b>       - Detected
+
+  UINT8                 AzaliaSnoop;                    ///< AzaliaSnoop        - Azalia Controller Snoop feature Configuration
+                                                        ///   @par
+                                                        /// Azalia Controller Snoop feature Configuration
+                                                        ///   @li <b>0</b>      - disable
+                                                        ///   @li <b>1</b>      - enable
+
+  UINT8                 AzaliaDummy;                    /// AzaliaDummy         - Reserved */
+
+  AZALIA_PIN            AzaliaConfig;                   /// AzaliaConfig        - Azaliz Pin Configuration
+
+///
+/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer
+///
+  CODEC_TBL_LIST        *AzaliaOemCodecTablePtr;        /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer
+
+///
+/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
+///
+  VOID                  *AzaliaOemFpCodecTablePtr;      /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer
+} FCH_AZALIA;
+
+///
+/// SPI structure
+///
+typedef struct {
+  BOOLEAN               LpcMsiEnable;                   ///< LPC MSI capability
+  UINT32                LpcSsid;                        ///< LPC Subsystem ID
+  UINT32                RomBaseAddress;                 ///< SpiRomBaseAddress
+                                                        ///   @par
+                                                        ///   SPI ROM BASE Address
+                                                        ///
+  UINT8                 SpiSpeed;                       ///< SpiSpeed - Spi Frequency
+                                                        ///  @par
+                                                        ///  SPI Speed [1.0] - the clock speed for non-fast read command
+                                                        ///   @li <b>00</b> - 66Mhz
+                                                        ///   @li <b>01</b> - 33Mhz
+                                                        ///   @li <b>10</b> - 22Mhz
+                                                        ///   @li <b>11</b> - 16.5Mhz
+                                                        ///
+  UINT8                 SpiFastSpeed;                   ///< FastSpeed  - Spi Fast Speed feature
+                                                        /// @par
+                                                        ///  TBD
+                                                        ///
+  UINT8                 WriteSpeed;                     ///< WriteSpeed - Spi Write Speed
+                                                        /// @par
+                                                        ///  TBD
+                                                        ///
+  UINT8                 SpiMode;                        ///< SpiMode    - Spi Mode Setting
+                                                        /// @par
+                                                        ///  @li <b>101</b> - Qual-io 1-4-4
+                                                        ///  @li <b>100</b> - Dual-io 1-2-2
+                                                        ///  @li <b>011</b> - Qual-io 1-1-4
+                                                        ///  @li <b>010</b> - Dual-io 1-1-2
+                                                        ///  @li <b>111</b> - FastRead
+                                                        ///  @li <b>110</b> - Normal
+                                                        ///
+  UINT8                 AutoMode;                       ///< AutoMode   - Spi Auto Mode
+                                                        /// @par
+                                                        ///  SPI Auto Mode
+                                                        ///  @li <b>0</b> - Disabled
+                                                        ///  @li <b>1</b> - Enabled
+                                                        ///
+  UINT8                 SpiBurstWrite;                  ///< SpiBurstWrite - Spi Burst Write Mode
+                                                        /// @par
+                                                        ///  SPI Burst Write
+                                                        ///  @li <b>0</b> - Disabled
+                                                        ///  @li <b>1</b> - Enabled
+} FCH_SPI;
+
+
+///
+/// IDE structure
+///
+typedef struct {
+  BOOLEAN               IdeEnable;                      ///< IDE function switch
+  BOOLEAN               IdeMsiEnable;                   ///< IDE MSI capability
+  UINT32                IdeSsid;                        ///< IDE controller Subsystem ID
+} FCH_IDE;
+
+///
+/// IR Structure
+///
+typedef struct {
+  IR_CONFIG             IrConfig;                       ///< IrConfig
+  UINT8                 IrPinControl;                   ///< IrPinControl
+} FCH_IR;
+
+
+///
+/// PCI Bridge Structure
+///
+typedef struct {
+  BOOLEAN               PcibMsiEnable;                  ///< PCI-PCI Bridge MSI capability
+  UINT32                PcibSsid;                       ///< PCI-PCI Bridge Subsystem ID
+  UINT8                 PciClks;                        ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+  UINT16                PcibClkStopOverride;            ///< PCIB_CLK_Stop Override
+  BOOLEAN               PcibClockRun;                   ///< Enable the auto clkrun functionality
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+} FCH_PCIB;
+
+
+///
+/// - SATA Phy setting structure
+///
+typedef struct _SATA_PHY_SETTING {
+  UINT16                PhyCoreControlWord;             /// PhyCoreControlWord - Reserved
+  UINT32                PhyFineTuneDword;               /// PhyFineTuneDword - Reserved
+} SATA_PHY_SETTING;
+
+///
+/// SATA main setting structure
+///
+typedef struct _SATA_ST {
+  UINT8                 SataModeReg;                    ///< SataModeReg - Sata Controller Mode
+  BOOLEAN               SataEnable;                     ///< SataEnable - Sata Controller Function
+                                                        ///   @par
+                                                        /// Sata Controller
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+  UINT8                 Sata6AhciCap;                   ///< Sata6AhciCap - Reserved */
+  BOOLEAN               SataSetMaxGen2;                 ///< SataSetMaxGen2 - Set Sata Max Gen2 mode
+                                                        ///   @par
+                                                        /// Sata Controller Set to Max Gen2 mode
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+  BOOLEAN               IdeEnable;                      ///< IdeEnable - Ide Controller Mode
+                                                        ///  @par
+                                                        /// Sata IDE Controller set to Combined Mode
+                                                        ///  @li <b>0</b> - disable
+                                                        ///  @li <b>1</b> - enable
+                                                        ///
+  UINT8                 SataClkMode;                    /// SataClkMode - Reserved
+} SATA_ST;
+
+///
+/// SATA_PORT_ST - SATA PORT structure
+///
+typedef struct _SATA_PORT_ST {
+  UINT8                 SataPortReg;                    ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7
+                                                        ///  @li <b>0</b> - disable
+                                                        ///  @li <b>1</b> - enable
+                                                        ///
+  BOOLEAN               Port0;                          ///< PORT0 - 0:disable, 1:enable
+  BOOLEAN               Port1;                          ///< PORT1 - 0:disable, 1:enable
+  BOOLEAN               Port2;                          ///< PORT2 - 0:disable, 1:enable
+  BOOLEAN               Port3;                          ///< PORT3 - 0:disable, 1:enable
+  BOOLEAN               Port4;                          ///< PORT4 - 0:disable, 1:enable
+  BOOLEAN               Port5;                          ///< PORT5 - 0:disable, 1:enable
+  BOOLEAN               Port6;                          ///< PORT6 - 0:disable, 1:enable
+  BOOLEAN               Port7;                          ///< PORT7 - 0:disable, 1:enable
+} SATA_PORT_ST;
+
+///
+///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode
+///
+typedef struct _SATA_PORT_MD {
+  UINT16                SataPortMode;                   ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7
+  UINT8                 Port0;                          ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
+  UINT8                 Port1;                          ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
+  UINT8                 Port2;                          ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
+  UINT8                 Port3;                          ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
+  UINT8                 Port4;                          ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
+  UINT8                 Port5;                          ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
+  UINT8                 Port6;                          ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
+  UINT8                 Port7;                          ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
+} SATA_PORT_MD;
+///
+/// SATA structure
+///
+typedef struct {
+  BOOLEAN               SataMsiEnable;                  ///< SATA MSI capability
+  UINT32                SataIdeSsid;                    ///< SATA IDE mode SSID
+  UINT32                SataRaidSsid;                   ///< SATA RAID mode SSID
+  UINT32                SataRaid5Ssid;                  ///< SATA RAID 5 mode SSID
+  UINT32                SataAhciSsid;                   ///< SATA AHCI mode SSID
+
+  SATA_ST               SataMode;                       /// SataMode - Reserved
+  SATA_CLASS            SataClass;                      ///< SataClass - SATA Controller mode [2:0]
+  UINT8                 SataIdeMode;                    ///< SataIdeMode - Sata IDE Controller mode
+                                                        ///  @par
+                                                        ///   @li <b>0</b> - Legacy IDE mode
+                                                        ///   @li <b>1</b> - Native IDE mode
+                                                        ///
+  UINT8                 SataDisUnusedIdePChannel;       ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+                                                        ///  @par
+                                                        ///   @li <b>0</b> - Channel Enable
+                                                        ///   @li <b>1</b> - Channel Disable
+                                                        ///
+  UINT8                 SataDisUnusedIdeSChannel;       ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel
+                                                        ///   @par
+                                                        ///    @li <b>0</b> - Channel Enable
+                                                        ///    @li <b>1</b> - Channel Disable
+                                                        ///
+  UINT8                 IdeDisUnusedIdePChannel;        ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+                                                        ///   @par
+                                                        ///    @li <b>0</b> - Channel Enable
+                                                        ///    @li <b>1</b> - Channel Disable
+                                                        ///
+  UINT8                 IdeDisUnusedIdeSChannel;        ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel
+                                                        ///   @par
+                                                        ///    @li <b>0</b> - Channel Enable
+                                                        ///    @li <b>1</b> - Channel Disable
+                                                        ///
+  UINT8                 SataOptionReserved;             /// SataOptionReserved - Reserved
+
+  SATA_PORT_ST          SataEspPort;                    ///<  SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
+
+  SATA_PORT_ST          SataPortPower;                  ///<  SataPortPower - Port Power configuration
+
+  SATA_PORT_MD          SataPortMd;                     ///<  SataPortMd - Port Mode
+
+  UINT8                 SataAggrLinkPmCap;              /// SataAggrLinkPmCap - 0:OFF   1:ON
+  UINT8                 SataPortMultCap;                /// SataPortMultCap - 0:OFF   1:ON
+  UINT8                 SataClkAutoOff;                 /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled
+  UINT8                 SataPscCap;                     /// SataPscCap 1:Enable PSC, 0:Disable PSC capability
+  UINT8                 BiosOsHandOff;                  /// BiosOsHandOff - Reserved
+  UINT8                 SataFisBasedSwitching;          /// SataFisBasedSwitching - Reserved
+  UINT8                 SataCccSupport;                 /// SataCccSupport - Reserved
+  UINT8                 SataSscCap;                     /// SataSscCap - 1:Enable, 0:Disable SSC capability
+  UINT8                 SataMsiCapability;              /// SataMsiCapability 0:Hidden 1:Visible
+  UINT8                 SataForceRaid;                  /// SataForceRaid   0:No function 1:Force RAID
+  UINT8                 SataInternal100Spread;          /// SataInternal100Spread - Reserved
+  UINT8                 SataDebugDummy;                 /// SataDebugDummy - Reserved
+  UINT8                 SataTargetSupport8Device;       /// SataTargetSupport8Device - Reserved
+  UINT8                 SataDisableGenericMode;         /// SataDisableGenericMode - Reserved
+  BOOLEAN               SataAhciEnclosureManagement;    /// SataAhciEnclosureManagement - Reserved
+  UINT8                 SataSgpio0;                     /// SataSgpio0 - Reserved
+  UINT8                 SataSgpio1;                     /// SataSgpio1 - Reserved
+  UINT8                 SataPhyPllShutDown;             /// SataPhyPllShutDown - Reserved
+  BOOLEAN               SataHotRemovalEnh;              /// SataHotRemovalEnh - Reserved
+
+  SATA_PORT_ST          SataHotRemovalEnhPort;          ///<  SataHotRemovalEnhPort - Hot Remove
+
+  BOOLEAN               SataOobDetectionEnh;            /// SataOobDetectionEnh - TRUE
+  BOOLEAN               SataPowerSavingEnh;             /// SataPowerSavingEnh - TRUE
+  UINT8                 SataMemoryPowerSaving;          /// SataMemoryPowerSaving - 0-3 Default [3]
+  UINT32                TempMmio;                       /// TempMmio - Reserved
+} FCH_SATA;
+
+
+//
+// IMC Message Register Software Interface
+//
+#define CPU_MISC_BUS_DEV_FUN          ((0x18 << 3) + 3)
+
+#define MSG_SYS_TO_IMC                0x80
+#define Fun_80                        0x80
+#define Fun_81                        0x81
+#define Fun_82                        0x82
+#define Fun_83                        0x83
+#define Fun_84                        0x84
+#define Fun_85                        0x85
+#define Fun_86                        0x86
+#define Fun_87                        0x87
+#define Fun_88                        0x88
+#define Fun_89                        0x89
+#define Fun_90                        0x90
+#define MSG_IMC_TO_SYS                0x81
+#define MSG_REG0                      0x82
+#define MSG_REG1                      0x83
+#define MSG_REG2                      0x84
+#define MSG_REG3                      0x85
+#define MSG_REG4                      0x86
+#define MSG_REG5                      0x87
+#define MSG_REG6                      0x88
+#define MSG_REG7                      0x89
+#define MSG_REG8                      0x8A
+#define MSG_REG9                      0x8B
+#define MSG_REGA                      0x8C
+#define MSG_REGB                      0x8D
+#define MSG_REGC                      0x8E
+#define MSG_REGD                      0x8F
+
+#define DISABLED                      0
+#define ENABLED                       1
+
+
+
+///
+/// EC structure
+///
+typedef struct _FCH_EC {
+  UINT8                 MsgFun81Zone0MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun81Zone0MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun81Zone0MsgReg2;           ///<Thermal zone control byte 1
+  UINT8                 MsgFun81Zone0MsgReg3;           ///<Thermal zone control byte 2
+  UINT8                 MsgFun81Zone0MsgReg4;           ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+  UINT8                 MsgFun81Zone0MsgReg5;           ///<Hysteresis information
+  UINT8                 MsgFun81Zone0MsgReg6;           ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+  UINT8                 MsgFun81Zone0MsgReg7;           ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
+  UINT8                 MsgFun81Zone0MsgReg8;           ///<Fan PWM stepping rate in unit of PWM level percentage
+  UINT8                 MsgFun81Zone0MsgReg9;           ///<Fan PWM ramping rate in 5ms unit
+//
+// EC LDN9 function 81 zone 1
+//
+  UINT8                 MsgFun81Zone1MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun81Zone1MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun81Zone1MsgReg2;           ///<Thermal zone control byte 1
+  UINT8                 MsgFun81Zone1MsgReg3;           ///<Thermal zone control byte 2
+  UINT8                 MsgFun81Zone1MsgReg4;           ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+  UINT8                 MsgFun81Zone1MsgReg5;           ///<Hysteresis information
+  UINT8                 MsgFun81Zone1MsgReg6;           ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+  UINT8                 MsgFun81Zone1MsgReg7;           ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
+  UINT8                 MsgFun81Zone1MsgReg8;           ///<Fan PWM stepping rate in unit of PWM level percentage
+  UINT8                 MsgFun81Zone1MsgReg9;           ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 2
+//
+  UINT8                 MsgFun81Zone2MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun81Zone2MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun81Zone2MsgReg2;           ///<Thermal zone control byte 1
+  UINT8                 MsgFun81Zone2MsgReg3;           ///<Thermal zone control byte 2
+  UINT8                 MsgFun81Zone2MsgReg4;           ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+  UINT8                 MsgFun81Zone2MsgReg5;           ///<Hysteresis information
+  UINT8                 MsgFun81Zone2MsgReg6;           ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+  UINT8                 MsgFun81Zone2MsgReg7;           ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
+  UINT8                 MsgFun81Zone2MsgReg8;           ///<Fan PWM stepping rate in unit of PWM level percentage
+  UINT8                 MsgFun81Zone2MsgReg9;           ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 3
+//
+  UINT8                 MsgFun81Zone3MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun81Zone3MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun81Zone3MsgReg2;           ///<Thermal zone control byte 1
+  UINT8                 MsgFun81Zone3MsgReg3;           ///<Thermal zone control byte 2
+  UINT8                 MsgFun81Zone3MsgReg4;           ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+  UINT8                 MsgFun81Zone3MsgReg5;           ///<Hysteresis information
+  UINT8                 MsgFun81Zone3MsgReg6;           ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+  UINT8                 MsgFun81Zone3MsgReg7;           ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
+  UINT8                 MsgFun81Zone3MsgReg8;           ///<Fan PWM stepping rate in unit of PWM level percentage
+  UINT8                 MsgFun81Zone3MsgReg9;           ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 83 zone 0
+//
+  UINT8                 MsgFun83Zone0MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun83Zone0MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun83Zone0MsgReg2;           ///<_AC0
+  UINT8                 MsgFun83Zone0MsgReg3;           ///<_AC1
+  UINT8                 MsgFun83Zone0MsgReg4;           ///<_AC2
+  UINT8                 MsgFun83Zone0MsgReg5;           ///<_AC3
+  UINT8                 MsgFun83Zone0MsgReg6;           ///<_AC4
+  UINT8                 MsgFun83Zone0MsgReg7;           ///<_AC5
+  UINT8                 MsgFun83Zone0MsgReg8;           ///<_AC6
+  UINT8                 MsgFun83Zone0MsgReg9;           ///<_AC7
+  UINT8                 MsgFun83Zone0MsgRegA;           ///<_CRT
+  UINT8                 MsgFun83Zone0MsgRegB;           ///<_PSV
+//
+//EC LDN9 function 83 zone 1
+//
+  UINT8                 MsgFun83Zone1MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun83Zone1MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun83Zone1MsgReg2;           ///<_AC0
+  UINT8                 MsgFun83Zone1MsgReg3;           ///<_AC1
+  UINT8                 MsgFun83Zone1MsgReg4;           ///<_AC2
+  UINT8                 MsgFun83Zone1MsgReg5;           ///<_AC3
+  UINT8                 MsgFun83Zone1MsgReg6;           ///<_AC4
+  UINT8                 MsgFun83Zone1MsgReg7;           ///<_AC5
+  UINT8                 MsgFun83Zone1MsgReg8;           ///<_AC6
+  UINT8                 MsgFun83Zone1MsgReg9;           ///<_AC7
+  UINT8                 MsgFun83Zone1MsgRegA;           ///<_CRT
+  UINT8                 MsgFun83Zone1MsgRegB;           ///<_PSV
+//
+//EC LDN9 function 83 zone 2
+//
+  UINT8                 MsgFun83Zone2MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun83Zone2MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun83Zone2MsgReg2;           ///<_AC0
+  UINT8                 MsgFun83Zone2MsgReg3;           ///<_AC1
+  UINT8                 MsgFun83Zone2MsgReg4;           ///<_AC2
+  UINT8                 MsgFun83Zone2MsgReg5;           ///<_AC3
+  UINT8                 MsgFun83Zone2MsgReg6;           ///<_AC4
+  UINT8                 MsgFun83Zone2MsgReg7;           ///<_AC5
+  UINT8                 MsgFun83Zone2MsgReg8;           ///<_AC6
+  UINT8                 MsgFun83Zone2MsgReg9;           ///<_AC7
+  UINT8                 MsgFun83Zone2MsgRegA;           ///<_CRT
+  UINT8                 MsgFun83Zone2MsgRegB;           ///<_PSV
+//
+//EC LDN9 function 83 zone 3
+//
+  UINT8                 MsgFun83Zone3MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun83Zone3MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun83Zone3MsgReg2;           ///<_AC0
+  UINT8                 MsgFun83Zone3MsgReg3;           ///<_AC1
+  UINT8                 MsgFun83Zone3MsgReg4;           ///<_AC2
+  UINT8                 MsgFun83Zone3MsgReg5;           ///<_AC3
+  UINT8                 MsgFun83Zone3MsgReg6;           ///<_AC4
+  UINT8                 MsgFun83Zone3MsgReg7;           ///<_AC5
+  UINT8                 MsgFun83Zone3MsgReg8;           ///<_AC6
+  UINT8                 MsgFun83Zone3MsgReg9;           ///<_AC7
+  UINT8                 MsgFun83Zone3MsgRegA;           ///<_CRT
+  UINT8                 MsgFun83Zone3MsgRegB;           ///<_PSV
+//
+//EC LDN9 function 85 zone 0
+//
+  UINT8                 MsgFun85Zone0MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun85Zone0MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun85Zone0MsgReg2;           ///<AL0 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg3;           ///<AL1 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg4;           ///<AL2 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg5;           ///<AL3 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg6;           ///<AL4 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg7;           ///<AL5 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg8;           ///<AL6 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone0MsgReg9;           ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 1
+//
+  UINT8                 MsgFun85Zone1MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun85Zone1MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun85Zone1MsgReg2;           ///<AL0 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg3;           ///<AL1 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg4;           ///<AL2 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg5;           ///<AL3 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg6;           ///<AL4 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg7;           ///<AL5 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg8;           ///<AL6 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone1MsgReg9;           ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 2
+//
+  UINT8                 MsgFun85Zone2MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun85Zone2MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun85Zone2MsgReg2;           ///<AL0 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg3;           ///<AL1 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg4;           ///<AL2 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg5;           ///<AL3 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg6;           ///<AL4 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg7;           ///<AL5 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg8;           ///<AL6 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone2MsgReg9;           ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 3
+//
+  UINT8                 MsgFun85Zone3MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun85Zone3MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun85Zone3MsgReg2;           ///<AL0 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg3;           ///<AL1 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg4;           ///<AL2 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg5;           ///<AL3 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg6;           ///<AL4 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg7;           ///<AL5 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg8;           ///<AL6 PWM level in percentage (0 - 100%)
+  UINT8                 MsgFun85Zone3MsgReg9;           ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 89 TEMPIN channel 0
+//
+  UINT8                 MsgFun89Zone0MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun89Zone0MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun89Zone0MsgReg2;           ///<At DWORD bit 0-7
+  UINT8                 MsgFun89Zone0MsgReg3;           ///<At DWORD bit 15-8
+  UINT8                 MsgFun89Zone0MsgReg4;           ///<At DWORD bit 23-16
+  UINT8                 MsgFun89Zone0MsgReg5;           ///<At DWORD bit 31-24
+  UINT8                 MsgFun89Zone0MsgReg6;           ///<Ct DWORD bit 0-7
+  UINT8                 MsgFun89Zone0MsgReg7;           ///<Ct DWORD bit 15-8
+  UINT8                 MsgFun89Zone0MsgReg8;           ///<Ct DWORD bit 23-16
+  UINT8                 MsgFun89Zone0MsgReg9;           ///<Ct DWORD bit 31-24
+  UINT8                 MsgFun89Zone0MsgRegA;           ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 1
+//
+  UINT8                 MsgFun89Zone1MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun89Zone1MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun89Zone1MsgReg2;           ///<At DWORD bit 0-7
+  UINT8                 MsgFun89Zone1MsgReg3;           ///<At DWORD bit 15-8
+  UINT8                 MsgFun89Zone1MsgReg4;           ///<At DWORD bit 23-16
+  UINT8                 MsgFun89Zone1MsgReg5;           ///<At DWORD bit 31-24
+  UINT8                 MsgFun89Zone1MsgReg6;           ///<Ct DWORD bit 0-7
+  UINT8                 MsgFun89Zone1MsgReg7;           ///<Ct DWORD bit 15-8
+  UINT8                 MsgFun89Zone1MsgReg8;           ///<Ct DWORD bit 23-16
+  UINT8                 MsgFun89Zone1MsgReg9;           ///<Ct DWORD bit 31-24
+  UINT8                 MsgFun89Zone1MsgRegA;           ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 2
+//
+  UINT8                 MsgFun89Zone2MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun89Zone2MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun89Zone2MsgReg2;           ///<At DWORD bit 0-7
+  UINT8                 MsgFun89Zone2MsgReg3;           ///<At DWORD bit 15-8
+  UINT8                 MsgFun89Zone2MsgReg4;           ///<At DWORD bit 23-16
+  UINT8                 MsgFun89Zone2MsgReg5;           ///<At DWORD bit 31-24
+  UINT8                 MsgFun89Zone2MsgReg6;           ///<Ct DWORD bit 0-7
+  UINT8                 MsgFun89Zone2MsgReg7;           ///<Ct DWORD bit 15-8
+  UINT8                 MsgFun89Zone2MsgReg8;           ///<Ct DWORD bit 23-16
+  UINT8                 MsgFun89Zone2MsgReg9;           ///<Ct DWORD bit 31-24
+  UINT8                 MsgFun89Zone2MsgRegA;           ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 3
+//
+  UINT8                 MsgFun89Zone3MsgReg0;           ///<Thermal zone
+  UINT8                 MsgFun89Zone3MsgReg1;           ///<Thermal zone
+  UINT8                 MsgFun89Zone3MsgReg2;           ///<At DWORD bit 0-7
+  UINT8                 MsgFun89Zone3MsgReg3;           ///<At DWORD bit 15-8
+  UINT8                 MsgFun89Zone3MsgReg4;           ///<At DWORD bit 23-16
+  UINT8                 MsgFun89Zone3MsgReg5;           ///<At DWORD bit 31-24
+  UINT8                 MsgFun89Zone3MsgReg6;           ///<Ct DWORD bit 0-7
+  UINT8                 MsgFun89Zone3MsgReg7;           ///<Ct DWORD bit 15-8
+  UINT8                 MsgFun89Zone3MsgReg8;           ///<Ct DWORD bit 23-16
+  UINT8                 MsgFun89Zone3MsgReg9;           ///<Ct DWORD bit 31-24
+  UINT8                 MsgFun89Zone3MsgRegA;           ///<Mode bit 0-7
+//
+// FLAG for Fun83/85/89 support
+//
+  UINT16                IMCFUNSupportBitMap;            ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
+} FCH_EC;
+
+///
+/// IMC structure
+///
+typedef struct _FCH_IMC {
+  UINT8                 ImcEnable;                      ///< ImcEnable - IMC Enable
+  UINT8                 ImcEnabled;                     ///< ImcEnabled - IMC Enable
+  UINT8                 ImcSureBootTimer;               ///< ImcSureBootTimer - IMc SureBootTimer function
+  FCH_EC                EcStruct;                       ///< EC structure
+  UINT8                 ImcEnableOverWrite;             ///< OverWrite IMC with the EC structure
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+} FCH_IMC;
+
+
+///
+/// Hpet structure
+///
+typedef struct {
+  BOOLEAN               HpetEnable;                     ///< HPET function switch
+
+  BOOLEAN               HpetMsiDis;                     ///< HpetMsiDis - South Bridge HPET MSI Configuration
+                                                        ///   @par
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT32                HpetBase;                       ///< HpetBase
+                                                        ///   @par
+                                                        ///  HPET Base address
+} FCH_HPET;
+
+
+///
+/// GCPU related parameters
+///
+typedef struct {
+  UINT8                 AcDcMsg;                        ///< Send a message to CPU to indicate the power mode (AC vs battery)
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT8                 TimerTickTrack;                 ///< Send a message to CPU to indicate the latest periodic timer interval
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT8                 ClockInterruptTag;              ///< Mark the periodic timer interrupt
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT8                 OhciTrafficHanding;             ///< Cause CPU to break out from C state when USB OHCI has pending traffic
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT8                 EhciTrafficHanding;             ///< Cause CPU to break out from C state when USB EHCI has pending traffic
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT8                 GcpuMsgCMultiCore;              ///< Track of CPU C state by monitoring each core's C state message
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+
+  UINT8                 GcpuMsgCStage;                  ///< Enable the FCH C state coordination logic
+                                                        ///   @li <b>1</b> - disable
+                                                        ///   @li <b>0</b> - enable
+} FCH_GCPU;
+
+
+///
+/// Timer
+///
+typedef struct {
+  BOOLEAN               Enable;                         ///< Whether to register timer SMI in POST
+  BOOLEAN               StartNow;                       ///< Whether to start the SMI immediately during registration
+  UINT16                CycleDuration;                  ///< [14:0] - Actual cycle duration = CycleDuration + 1
+} TIMER_SMI;
+
+
+///
+/// MISC structure
+///
+typedef struct {
+  BOOLEAN               NativePcieSupport;              /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled
+  BOOLEAN               S3Resume;                       /// S3Resume - Flag of ACPI S3 Resume.
+  BOOLEAN               RebootRequired;                 /// RebootRequired - Flag of Reboot system is required.
+  UINT8                 FchVariant;                     /// FchVariant - FCH Variant value.
+  UINT8                 Cg2Pll;                         ///< CG2 PLL - 0:disable, 1:enable
+  TIMER_SMI             LongTimer;                      ///< Long Timer SMI
+  TIMER_SMI             ShortTimer;                     ///< Short Timer SMI
+} FCH_MISC;
+
+
+///
+/// SMBus structure
+///
+typedef struct {
+  UINT32                SmbusSsid;                      ///< SMBUS controller Subsystem ID
+} FCH_SMBUS;
+
+
+///
+/// Acpi structure
+///
+typedef struct {
+  UINT16                Smbus0BaseAddress;              ///< Smbus0BaseAddress
+                                                        ///   @par
+                                                        ///  Smbus BASE Address
+                                                        ///
+  UINT16                Smbus1BaseAddress;              ///< Smbus1BaseAddress
+                                                        ///   @par
+                                                        ///  Smbus1 (ASF) BASE Address
+                                                        ///
+  UINT16                SioPmeBaseAddress;              ///< SioPmeBaseAddress
+                                                        ///   @par
+                                                        ///  SIO PME BASE Address
+                                                        ///
+  UINT32                WatchDogTimerBase;              ///< WatchDogTimerBase
+                                                        ///   @par
+                                                        ///  Watch Dog Timer Address
+                                                        ///
+  UINT16                AcpiPm1EvtBlkAddr;              ///< AcpiPm1EvtBlkAddr
+                                                        ///   @par
+                                                        ///  ACPI PM1 event block Address
+                                                        ///
+  UINT16                AcpiPm1CntBlkAddr;              ///< AcpiPm1CntBlkAddr
+                                                        ///   @par
+                                                        ///  ACPI PM1 Control block Address
+                                                        ///
+  UINT16                AcpiPmTmrBlkAddr;               ///< AcpiPmTmrBlkAddr
+                                                        ///   @par
+                                                        ///  ACPI PM timer block Address
+                                                        ///
+  UINT16                CpuControlBlkAddr;              ///< CpuControlBlkAddr
+                                                        ///   @par
+                                                        ///  ACPI CPU control block Address
+                                                        ///
+  UINT16                AcpiGpe0BlkAddr;                ///< AcpiGpe0BlkAddr
+                                                        ///   @par
+                                                        ///  ACPI GPE0 block Address
+                                                        ///
+  UINT16                SmiCmdPortAddr;                 ///< SmiCmdPortAddr
+                                                        ///   @par
+                                                        ///  SMI command port Address
+                                                        ///
+  UINT16                AcpiPmaCntBlkAddr;              ///< AcpiPmaCntBlkAddr
+                                                        ///   @par
+                                                        ///  ACPI PMA Control block Address
+                                                        ///
+  BOOLEAN               AnyHt200MhzLink;                ///< AnyHt200MhzLink
+                                                        ///   @par
+                                                        ///  HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable)
+                                                        ///
+  BOOLEAN               SpreadSpectrum;                 ///< SpreadSpectrum
+                                                        ///  @par
+                                                        ///  Spread Spectrum function
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+  POWER_FAIL            PwrFailShadow;                  ///< PwrFailShadow = PM_Reg: 5Bh [3:0]
+                                                        ///  @par
+                                                        ///   @li  <b>00</b> - Always off
+                                                        ///   @li  <b>01</b> - Always on
+                                                        ///   @li  <b>11</b> - Use previous
+                                                        ///
+  UINT8                 StressResetMode;                ///< StressResetMode 01-10
+                                                        ///   @li  <b>00</b> - Disabed
+                                                        ///   @li  <b>01</b> - Io Write 0x64 with 0xfe
+                                                        ///   @li  <b>10</b> - Io Write 0xcf9 with 0x06
+                                                        ///   @li  <b>11</b> - Io Write 0xcf9 with 0x0e
+                                                        ///
+  BOOLEAN               MtC1eEnable;                    /// MtC1eEnable - Enable MtC1e
+  VOID*                 OemProgrammingTablePtr;         /// Pointer of ACPI OEM table
+} FCH_ACPI;
+
+
+///
+/// HWM temp parameter structure
+///
+typedef struct _FCH_HWM_TEMP_PAR {
+  UINT16                At;                             ///< At
+  UINT16                Ct;                             ///< Ct
+  UINT8                 Mode;                           ///< Mode BIT0:HiRatio BIT1:HiCurrent
+} FCH_HWM_TEMP_PAR;
+
+///
+/// HWM Current structure
+///
+typedef struct _FCH_HWM_CUR {
+  UINT16                FanSpeed[5];                    ///< FanSpeed    - fan Speed
+  UINT16                Temperature[5];                 ///< Temperature - temperature
+  UINT16                Voltage[8];                     ///< Voltage     - voltage
+} FCH_HWM_CUR;
+
+///
+/// HWM fan control structure
+///
+typedef struct _FCH_HWM_FAN_CTR {
+  UINT8                 InputControlReg00;              /// Fan Input Control register, PM2 offset [0:4]0
+  UINT8                 ControlReg01;                   /// Fan control register, PM2 offset [0:4]1
+  UINT8                 FreqReg02;                      /// Fan frequency register, PM2 offset [0:4]2
+  UINT8                 LowDutyReg03;                   /// Low Duty register, PM2 offset [0:4]3
+  UINT8                 MedDutyReg04;                   /// Med Duty register, PM2 offset [0:4]4
+  UINT8                 MultiplierReg05;                /// Multiplier register, PM2 offset [0:4]5
+  UINT16                LowTempReg06;                   /// Low Temp register, PM2 offset [0:4]6
+  UINT16                MedTempReg08;                   /// Med Temp register, PM2 offset [0:4]8
+  UINT16                HighTempReg0A;                  /// High Temp register, PM2 offset [0:4]A
+  UINT8                 LinearRangeReg0C;               /// Linear Range register, PM2 offset [0:4]C
+  UINT8                 LinearHoldCountReg0D;           /// Linear Hold Count register, PM2 offset [0:4]D
+} FCH_HWM_FAN_CTR;
+
+///
+/// Hwm structure
+///
+typedef struct _FCH_HWM {
+  UINT8                 HwMonitorEnable;                ///< HwMonitorEnable
+  UINT32                HwmControl;                     ///< hwmControl
+                                                        ///   @par
+                                                        ///  HWM control configuration
+                                                        ///   @li <b>0</b> - HWM is Enabled
+                                                        ///   @li <b>1</b> - IMC is Enabled
+                                                        ///
+  UINT8                 FanSampleFreqDiv;               ///< Sampling rate of Fan Speed
+                                                        ///   @li <b>00</b> - Base(22.5KHz)
+                                                        ///   @li <b>01</b> - Base(22.5KHz)/2
+                                                        ///   @li <b>10</b> - Base(22.5KHz)/4
+                                                        ///   @li <b>11</b> - Base(22.5KHz)/8
+                                                        ///
+  UINT8                 HwmFchtsiAutoPoll;              ///< TSI Auto Polling
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+  UINT8                 HwmFchtsiAutoPollStarted;       ///< HwmSbtsiAutoPollStarted
+  UINT8                 FanLinearEnhanceEn;             ///< FanLinearEnhanceEn
+  UINT8                 FanLinearHoldFix;               ///< FanLinearHoldFix
+  UINT8                 FanLinearRangeOutLimit;         ///< FanLinearRangeOutLimit
+  UINT16                HwmCalibrationFactor;           /// Calibration Factor
+  FCH_HWM_CUR           HwmCurrent;                     /// HWM Current structure
+  FCH_HWM_CUR           HwmCurrentRaw;                  /// HWM Current Raw structure
+  FCH_HWM_TEMP_PAR      HwmTempPar[5];                  /// HWM Temp parameter structure
+  FCH_HWM_FAN_CTR       HwmFanControl[5];               /// HWM Fan Control structure
+  FCH_HWM_FAN_CTR       HwmFanControlCooked[5];               /// HWM Fan Control structure
+} FCH_HWM;
+
+
+///
+/// Gec structure
+///
+typedef struct {
+  BOOLEAN               GecEnable;                      ///< GecEnable - GEC function switch
+  UINT8                 GecPhyStatus;                   /// GEC PHY Status
+  UINT8                 GecPowerPolicy;                 /// GEC Power Policy
+                                                        ///   @li <b>00</b> - GEC is powered down in S3 and S5
+                                                        ///   @li <b>01</b> - GEC is powered down only in S5
+                                                        ///   @li <b>10</b> - GEC is powered down only in S3
+                                                        ///   @li <b>11</b> - GEC is never powered down
+                                                        ///
+  UINT8                 GecDebugBus;                    /// GEC Debug Bus
+                                                        ///   @li <b>0</b> - disable
+                                                        ///   @li <b>1</b> - enable
+                                                        ///
+  UINT32                GecShadowRomBase;               ///< GecShadowRomBase
+                                                        ///   @par
+                                                        ///  GEC (NIC) SHADOWROM BASE Address
+                                                        ///
+  VOID                  *PtrDynamicGecRomAddress;       /// Pointer of Dynamic GEC ROM Address
+} FCH_GEC;
+
+
+///
+/// _ABTblEntry - AB link register table R/W structure
+///
+typedef struct _AB_TBL_ENTRY {
+  UINT8                 RegType;                        /// RegType  : AB Register Type (ABCFG, AXCFG and so on)
+  UINT32                RegIndex;                       /// RegIndex : AB Register Index
+  UINT32                RegMask;                        /// RegMask  : AB Register Mask
+  UINT32                RegData;                        /// RegData  : AB Register Data
+} AB_TBL_ENTRY;
+
+///
+/// AB structure
+///
+typedef struct {
+  BOOLEAN               AbMsiEnable;                    ///< ABlink MSI capability
+  UINT8                 ALinkClkGateOff;                /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR
+  UINT8                 BLinkClkGateOff;                /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR
+  UINT8                 AbClockGating;                  /// AB Clock Gating - 0:disable, 1:enable *KR
+  UINT8                 GppClockGating;                 /// GPP Clock Gating - 0:disable, 1:enable
+  UINT8                 UmiL1TimerOverride;             /// UMI L1 inactivity timer overwrite value
+  UINT8                 UmiLinkWidth;                   /// UMI Link Width
+  UINT8                 UmiDynamicSpeedChange;          /// UMI Dynamic Speed Change - 0:disable, 1:enable
+  UINT8                 PcieRefClockOverClocking;       /// PCIe Ref Clock OverClocking value
+  UINT8                 UmiGppTxDriverStrength;         /// UMI GPP TX Driver Strength
+  BOOLEAN               NbSbGen2;                       /// UMI link Gen2 - 0:Gen1, 1:Gen2
+  UINT8                 PcieOrderRule;                  /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted
+  UINT8                 SlowSpeedAbLinkClock;           /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR
+  UINT8                 ResetCpuOnSyncFlood;            /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR
+  BOOLEAN               AbDmaMemoryWrtie3264B;          /// AB DMA Memory Write 32/64 BYTE Support *KR only
+  BOOLEAN               AbMemoryPowerSaving;            /// AB Memory Power Saving *KR only
+  BOOLEAN               SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only
+  BOOLEAN               SbgMemoryPowerSaving;           /// SBG Memory Power Saving *KR only
+} FCH_AB;
+
+
+/**
+ * PCIE_CAP_ID - PCIe Cap ID
+ *
+ */
+#define  PCIE_CAP_ID    0x10
+
+///
+/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure
+///
+typedef struct {
+  BOOLEAN               PortPresent;                    ///< Port connection
+                                                        ///  @par
+                                                        ///  @li <b>0</b> - Port doesn't have slot. No need to train the link
+                                                        ///  @li <b>1</b> - Port connection defined and needs to be trained
+                                                        ///
+  BOOLEAN               PortDetected;                   ///< Link training status
+                                                        ///  @par
+                                                        ///  @li <b>0</b> - EP not detected
+                                                        ///  @li <b>1</b> - EP detected
+                                                        ///
+  BOOLEAN               PortIsGen2;                     ///< Port link speed configuration
+                                                        ///  @par
+                                                        ///  @li <b>00</b> - Auto
+                                                        ///  @li <b>01</b> - Forced GEN1
+                                                        ///  @li <b>10</b> - Forced GEN2
+                                                        ///  @li <b>11</b> - Reserved
+                                                        ///
+  BOOLEAN               PortHotPlug;                    ///< Support hot plug?
+                                                        ///  @par
+                                                        ///  @li <b>0</b> - No support
+                                                        ///  @li <b>1</b> - support
+                                                        ///
+  UINT8                 PortMisc;                       ///  PortMisc - Reserved
+} FCH_GPP_PORT_CONFIG;
+
+///
+/// GPP structure
+///
+typedef struct {
+  FCH_GPP_PORT_CONFIG   PortCfg[4];                     /// GPP port configuration structure
+  GPP_LINKMODE          GppLinkConfig;                  ///< GppLinkConfig - PCIE_GPP_Enable[3:0]
+                                                        ///  @li  <b>0000</b> - Port ABCD -> 4:0:0:0
+                                                        ///  @li  <b>0010</b> - Port ABCD -> 2:2:0:0
+                                                        ///  @li  <b>0011</b> - Port ABCD -> 2:1:1:0
+                                                        ///  @li  <b>0100</b> - Port ABCD -> 1:1:1:1
+                                                        ///
+  BOOLEAN               GppFunctionEnable;              ///< GPP Function - 0:disable, 1:enable
+  BOOLEAN               GppToggleReset;                 ///< Toggle GPP core reset
+  UINT8                 GppHotPlugGeventNum;            ///< Hotplug GEVENT # - valid value 0-31
+  UINT8                 GppFoundGfxDev;                 ///< Gpp Found Gfx Device
+                                                        ///  @li   <b>0</b> - Not found
+                                                        ///  @li   <b>1</b> - Found
+                                                        ///
+  BOOLEAN               GppGen2;                        ///< GPP Gen2 - 0:disable, 1:enable
+  UINT8                 GppGen2Strap;                   ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this
+  BOOLEAN               GppMemWrImprove;                ///< GPP Memory Write Improve - 0:disable, 1:enable
+  BOOLEAN               GppUnhidePorts;                 ///< GPP Unhide Ports - 0:disable, 1:enable
+  UINT8                 GppPortAspm;                    ///< GppPortAspm - ASPM state for all GPP ports
+                                                        ///  @li   <b>01</b> - Disabled
+                                                        ///  @li   <b>01</b> - L0s
+                                                        ///  @li   <b>10</b> - L1
+                                                        ///  @li   <b>11</b> - L0s + L1
+                                                        ///
+  BOOLEAN               GppLaneReversal;                ///< GPP Lane Reversal - 0:disable, 1:enable
+  BOOLEAN               GppPhyPllPowerDown;             ///< GPP PHY PLL Power Down - 0:disable, 1:enable
+  BOOLEAN               GppDynamicPowerSaving;          ///< GPP Dynamic Power Saving - 0:disable, 1:enable
+  BOOLEAN               PcieAer;                        ///< PcieAer - Advanced Error Report: 0/1-disable/enable
+  BOOLEAN               PcieRas;                        ///< PCIe RAS - 0:disable, 1:enable
+  BOOLEAN               PcieCompliance;                 ///< PCIe Compliance - 0:disable, 1:enable
+  BOOLEAN               PcieSoftwareDownGrade;          ///< PCIe Software Down Grade
+  BOOLEAN               UmiPhyPllPowerDown;             ///< UMI PHY PLL Power Down - 0:disable, 1:enable
+  BOOLEAN               SerialDebugBusEnable;           ///< Serial Debug Bus Enable
+  UINT8                 GppHardwareDownGrade;           ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D
+  UINT8                 GppL1ImmediateAck;              ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable
+  BOOLEAN               NewGppAlgorithm;                ///< NewGppAlgorithm - New GPP procedure
+  UINT8                 HotPlugPortsStatus;             ///< HotPlugPortsStatus - Save Hot-Plug Ports Status
+  UINT8                 FailPortsStatus;                ///< FailPortsStatus - Save Failure Ports Status
+  UINT8                 GppPortMinPollingTime;          ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training
+} FCH_GPP;
+
+
+///
+/// FCH USB sturcture
+///
+typedef struct {
+  BOOLEAN               Ohci1Enable;                    ///< OHCI1 controller enable
+  BOOLEAN               Ohci2Enable;                    ///< OHCI2 controller enable
+  BOOLEAN               Ohci3Enable;                    ///< OHCI3 controller enable
+  BOOLEAN               Ohci4Enable;                    ///< OHCI4 controller enable
+  BOOLEAN               Ehci1Enable;                    ///< EHCI1 controller enable
+  BOOLEAN               Ehci2Enable;                    ///< EHCI2 controller enable
+  BOOLEAN               Ehci3Enable;                    ///< EHCI3 controller enable
+  BOOLEAN               Xhci0Enable;                    ///< XHCI0 controller enable
+  BOOLEAN               Xhci1Enable;                    ///< XHCI1 controller enable
+  BOOLEAN               UsbMsiEnable;                   ///< USB MSI capability
+  UINT32                OhciSsid;                       ///< OHCI SSID
+  UINT32                Ohci4Ssid;                      ///< OHCI 4 SSID
+  UINT32                EhciSsid;                       ///< EHCI SSID
+  UINT32                XhciSsid;                       ///< XHCI SSID
+  BOOLEAN               UsbPhyPowerDown;                ///< USB PHY Power Down - 0:disable, 1:enable
+  UINT32                UserDefineXhciRomAddr;          ///< XHCI ROM address define by platform BIOS
+} FCH_USB;
+
+
+/// Private: FCH_DATA_BLOCK_RESET
+typedef struct _FCH_RESET_DATA_BLOCK {
+  AMD_CONFIG_PARAMS     *StdHeader;                     ///< Header structure
+  FCH_RESET_INTERFACE   FchReset;                       ///< Reset interface
+
+  UINT8                 FastSpeed;                      ///< SPI Fast Speed - 0:disable, 1:enable
+  UINT8                 WriteSpeed;                     ///< SPI Write Speed
+  UINT8                 Mode;                           ///< SPI Mode
+                                                        ///  @li   <b>101</b> - Qual-io 1-4-4
+                                                        ///  @li   <b>100</b> - Dual-io 1-2-2
+                                                        ///  @li   <b>011</b> - Qual-io 1-1-4
+                                                        ///  @li   <b>010</b> - Dual-io 1-1-2
+                                                        ///  @li   <b>111</b> - FastRead
+                                                        ///  @li   <b>110</b> - Normal
+                                                        ///
+  UINT8                 AutoMode;                       ///< SPI Auto Mode - 0:disable, 1:enable
+  UINT8                 BurstWrite;                     ///< SPI Burst Write - 0:disable, 1:enable
+  BOOLEAN               Sata6AhciCap;                   ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable
+  UINT8                 Cg2Pll;                         ///< CG2 PLL - 0:disable, 1:enable
+  BOOLEAN               EcKbd;                          ///< EC KBD - 0:disable, 1:enable
+  BOOLEAN               LegacyFree;                     ///< Legacy Free - 0:disable, 1:enable
+  BOOLEAN               SataSetMaxGen2;                 ///< SATA enable maximum GEN2
+  UINT8                 SataClkMode;                    ///< SATA reference clock selector and divider
+  UINT8                 SataModeReg;                    ///< Output: SATAConfig PMIO:0xDA
+  BOOLEAN               SataInternal100Spread;          ///< SATA internal 100MHz spread ON/OFF
+  UINT8                 SpiSpeed;                       ///< SPI NormSpeed: 00-66MHz, 01-33MHz, 10-22MHz, 11-16.5MHz
+  BOOLEAN               EcChannel0;                     ///< Enable EC channel 0
+  FCH_GPP               Gpp;                            ///< GPP subsystem
+  VOID*                 OemResetProgrammingTablePtr;    /// Pointer of ACPI OEM table
+} FCH_RESET_DATA_BLOCK;
+
+
+/// Private: FCH_DATA_BLOCK
+typedef struct _FCH_DATA_BLOCK {
+  AMD_CONFIG_PARAMS     *StdHeader;                     ///< Header structure
+
+  FCH_ACPI              HwAcpi;                         ///< ACPI structure
+  FCH_AB                Ab;                             ///< AB structure
+  FCH_GPP               Gpp;                            ///< GPP structure
+  FCH_USB               Usb;                            ///< USB structure
+  FCH_SATA              Sata;                           ///< SATA structure
+  FCH_SMBUS             Smbus;                          ///< SMBus structure
+  FCH_IDE               Ide;                            ///< IDE structure
+  FCH_AZALIA            Azalia;                         ///< Azalia structure
+  FCH_SPI               Spi;                            ///< SPI structure
+  FCH_PCIB              Pcib;                           ///< PCIB structure
+  FCH_GEC               Gec;                            ///< GEC structure
+  FCH_SD                Sd;                             ///< SD structure
+  FCH_HWM               Hwm;                            ///< Hardware Moniter structure
+  FCH_IR                Ir;                             ///< IR structure
+  FCH_HPET              Hpet;                           ///< HPET structure
+  FCH_GCPU              Gcpu;                           ///< GCPU structure
+  FCH_IMC               Imc;                            ///< IMC structure
+  FCH_MISC              Misc;                           ///< MISC structure
+} FCH_DATA_BLOCK;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
new file mode 100644
index 0000000000..777e9cefe8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH common SMM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * FchSmmAcpiOn - Config Fch during ACPI_ON
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSmmAcpiOn (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  //
+  // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
+  // recommendation. This is required to fix the keyboard stuck issue when playing games under Windows
+  //
+
+  //
+  // Disable Power Button SMI
+  //
+  RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
new file mode 100644
index 0000000000..af1d1ba1b1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
@@ -0,0 +1,484 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH routine definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#ifndef _FCH_DEF_H_
+#define _FCH_DEF_H_
+
+
+UINT32        ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID          WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID          RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
+VOID          ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32  Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE  *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ProgramFchSciMapTbl (IN SCI_MAP_CONTROL  *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID          ProgramFchGpioTbl (IN GPIO_CONTROL  *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID          ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL  *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID          GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN       IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          RwPmio2 (IN UINT8 Address, IN UINT8  OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          GetFchAcpiPmBase (OUT  UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8         ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Fch Ab Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetAb (IN VOID* FchDataPtr);
+VOID  FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvAb (IN VOID* FchDataPtr);
+VOID  FchInitEnvAbSpecial (IN VOID* FchDataPtr);
+VOID  FchInitMidAb (IN VOID* FchDataPtr);
+VOID  FchInitLateAb (IN VOID* FchDataPtr);
+///
+///  Other Public Routines
+///
+VOID  FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
+BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchAbLateProgram (IN VOID* FchDataPtr);
+
+///
+/// Fch Pcie Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetPcie    (IN VOID* FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvPcie        (IN VOID* FchDataPtr);
+VOID  FchInitMidPcie        (IN VOID* FchDataPtr);
+VOID  FchInitLatePcie       (IN VOID* FchDataPtr);
+VOID  ProgramPcieNativeMode (IN VOID* FchDataPtr);
+
+///
+/// Fch Gpp Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetGpp (IN VOID* FchDataPtr);
+VOID  ProgramFchGppInitReset (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchResetPcie (IN RESET_BLOCK  ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvGpp (IN VOID* FchDataPtr);
+VOID  FchInitMidGpp (IN VOID* FchDataPtr);
+VOID  FchInitLateGpp (IN VOID* FchDataPtr);
+
+///
+///  Common Gpp Routines
+///
+VOID  ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchGppForceGen1 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchGppForceGen2 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 GppPortPollingLtssm (IN FCH_GPP *FchGpp, IN UINT8 ActivePorts, IN BOOLEAN IsGen2, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  GppGen2Workaround (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchGppPortInit (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchGppPortInitPhaseII (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchGppPortInitS3Phase (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+///
+///  Pei Phase
+///
+VOID  Fchdef174     (IN VOID  *FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  Fchdef178       (IN VOID  *FchDataPtr);
+VOID  Fchdef179       (IN VOID  *FchDataPtr);
+VOID  Fchdef180      (IN VOID  *FchDataPtr);
+
+
+///
+/// Fch GEC Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetGec (IN VOID*   FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID FchInitEnvGec (IN VOID*   FchDataPtr);
+VOID FchInitMidGec (IN VOID*   FchDataPtr);
+VOID FchInitLateGec (IN VOID*   FchDataPtr);
+///
+///  Other Public Routines
+///
+VOID FchInitGecController (IN VOID*   FchDataPtr);
+VOID FchSwInitGecBootRom (IN VOID*   FchDataPtr);
+
+///
+/// Fch HwAcpi Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetHwAcpiP    (IN VOID  *FchDataPtr);
+VOID  FchInitResetHwAcpi     (IN VOID  *FchDataPtr);
+VOID  ProgramFchHwAcpiResetP (IN VOID  *FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvHwAcpiP                      (IN VOID  *FchDataPtr);
+VOID  FchInitEnvHwAcpi                       (IN VOID  *FchDataPtr);
+VOID  ProgramEnvPFchAcpiMmio                 (IN VOID *FchDataPtr);
+VOID  ProgramFchEnvHwAcpiPciReg              (IN VOID *FchDataPtr);
+VOID  ProgramSpecificFchInitEnvAcpiMmio      (IN VOID *FchDataPtr);
+VOID  ProgramFchEnvSpreadSpectrum            (IN VOID *FchDataPtr);
+VOID  FchInitMidHwAcpi      (IN VOID  *FchDataPtr);
+VOID  FchInitLateHwAcpi     (IN VOID  *FchDataPtr);
+
+///
+///  Other Public Routines
+///
+VOID HpetInit               (IN VOID  *FchDataPtr);
+VOID C3PopupSetting         (IN VOID  *FchDataPtr);
+VOID MtC1eEnable            (IN VOID  *FchDataPtr);
+VOID GcpuRelatedSetting     (IN VOID  *FchDataPtr);
+VOID StressResetModeLate    (IN VOID  *FchDataPtr);
+
+///
+/// Fch Hwm Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetHwm (IN VOID* FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvHwm (IN VOID* FchDataPtr);
+VOID  FchInitMidHwm (IN VOID* FchDataPtr);
+VOID  FchInitLateHwm (IN VOID* FchDataPtr);
+///
+///  Other Public Routines
+///
+VOID  HwmInitRegister (IN VOID* FchDataPtr);
+VOID  HwmProcessParameter (IN VOID* FchDataPtr);
+VOID  HwmSetRegister (IN VOID* FchDataPtr);
+VOID  HwmGetCalibrationFactor (IN VOID* FchDataPtr);
+VOID  HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
+VOID  HwmGetRawData (IN VOID* FchDataPtr);
+VOID  HwmCaculate (IN VOID* FchDataPtr);
+VOID  HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
+VOID  FchECfancontrolservice (IN VOID* FchDataPtr);
+
+
+///
+/// Fch Ide Routines
+///
+VOID  FchInitEnvIde (IN VOID* FchDataPtr);
+VOID  FchInitMidIde (IN VOID* FchDataPtr);
+VOID  FchInitLateIde (IN VOID* FchDataPtr);
+
+
+///
+/// Fch Imc Routines
+///
+///  Pei Phase
+///
+VOID    FchInitResetImc    (IN VOID  *FchDataPtr);
+VOID    FchInitResetEc     (IN VOID  *FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID    FchInitEnvImc      (IN VOID  *FchDataPtr);
+VOID    FchInitMidImc      (IN VOID  *FchDataPtr);
+VOID    FchInitLateImc     (IN VOID  *FchDataPtr);
+VOID    FchInitEnvEc       (IN VOID  *FchDataPtr);
+VOID    FchInitMidEc       (IN VOID  *FchDataPtr);
+VOID    FchInitLateEc      (IN VOID  *FchDataPtr);
+///
+///  Other Public Routines
+///
+VOID    EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    ReadEc8    (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    WriteEc8   (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    RwEc8      (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    ReadECmsg  (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID    WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
+
+VOID    ImcSleep                   (IN VOID  *FchDataPtr);
+VOID    ImcEnableSurebootTimer     (IN VOID  *FchDataPtr);
+VOID    ImcDisarmSurebootTimer     (IN VOID  *FchDataPtr);
+VOID    ImcDisableSurebootTimer    (IN VOID  *FchDataPtr);
+VOID    ImcWakeup                  (IN VOID  *FchDataPtr);
+VOID    ImcIdle                    (IN VOID  *FchDataPtr);
+BOOLEAN ValidateImcFirmware        (IN VOID  *FchDataPtr);
+VOID    SoftwareToggleImcStrapping (IN VOID  *FchDataPtr);
+
+
+///
+/// Fch Ir Routines
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvIr (IN VOID* FchDataPtr);
+VOID  FchInitMidIr (IN VOID* FchDataPtr);
+VOID  FchInitLateIr (IN VOID* FchDataPtr);
+
+///
+/// Fch Pcib Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetPcib (IN VOID* FchDataPtr);
+VOID  FchInitResetPcibPort80Enable (IN VOID* FchDataPtr);
+
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvPcib (IN VOID* FchDataPtr);
+VOID  FchInitMidPcib (IN VOID* FchDataPtr);
+VOID  FchInitLatePcib (IN VOID* FchDataPtr);
+
+
+///
+/// Fch SATA Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetSata          (IN VOID  *FchDataPtr);
+VOID  FchInitResetSataProgram   (IN VOID  *FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitMidSata                   (IN VOID  *FchDataPtr);
+VOID  FchInitEnvSata                   (IN VOID  *FchDataPtr);
+VOID  FchInitEnvProgramSataPciRegs     (IN VOID  *FchDataPtr);
+VOID  FchInitMidProgramSataRegs        (IN VOID  *FchDataPtr);
+VOID  FchInitLateProgramSataRegs       (IN VOID  *FchDataPtr);
+
+VOID  FchInitLateSata           (IN VOID  *FchDataPtr);
+VOID  FchInitEnvSataIde         (IN VOID  *FchDataPtr);
+VOID  FchInitMidSataIde         (IN VOID  *FchDataPtr);
+VOID  FchInitLateSataIde        (IN VOID  *FchDataPtr);
+VOID  FchInitEnvSataAhci        (IN VOID  *FchDataPtr);
+VOID  FchInitMidSataAhci        (IN VOID  *FchDataPtr);
+VOID  FchInitLateSataAhci       (IN VOID  *FchDataPtr);
+VOID  FchInitEnvSataRaid        (IN VOID  *FchDataPtr);
+VOID  FchInitMidSataRaid        (IN VOID  *FchDataPtr);
+VOID  FchInitLateSataRaid       (IN VOID  *FchDataPtr);
+VOID  FchInitEnvSataIde2Ahci    (IN VOID  *FchDataPtr);
+VOID  FchInitMidSataIde2Ahci    (IN VOID  *FchDataPtr);
+VOID  FchInitLateSataIde2Ahci   (IN VOID  *FchDataPtr);
+
+VOID SataAhciSetDeviceNumMsi     (IN VOID  *FchDataPtr);
+VOID SataRaidSetDeviceNumMsi     (IN VOID  *FchDataPtr);
+VOID SataIde2AhciSetDeviceNumMsi (IN VOID  *FchDataPtr);
+VOID  SataSetIrqIntResource (IN VOID  *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID  SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  SataSetDeviceNumMsi (IN VOID  *FchDataPtr);
+VOID  FchSataSetDeviceNumMsi (IN VOID  *FchDataPtr);
+VOID  ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID  FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID  SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID  FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID  FchSataGpioInitial (IN  VOID  *FchDataPtr);
+VOID  SataBar5RegSet (IN  VOID  *FchDataPtr);
+VOID  SataSetPortGenMode (IN  VOID  *FchDataPtr);
+VOID  FchSataSetPortGenMode (IN  VOID  *FchDataPtr);
+VOID  FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchSataDriveFpga (IN  VOID  *FchDataPtr);
+VOID  FchInitEnvSataRaidProgram  (IN VOID  *FchDataPtr);
+
+///
+/// FCH USB Controller Public Function
+///
+///  Pei Phase
+///
+VOID  FchInitResetUsb            (IN VOID  *FchDataPtr);
+VOID  FchInitResetOhci           (IN VOID  *FchDataPtr);
+VOID  FchInitResetEhci           (IN VOID  *FchDataPtr);
+VOID  FchInitResetXhci           (IN VOID  *FchDataPtr);
+VOID  FchInitResetXhciProgram    (IN VOID  *FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvUsb              (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsb              (IN VOID  *FchDataPtr);
+VOID  FchInitLateUsb             (IN VOID  *FchDataPtr);
+VOID  FchInitEnvUsbOhci          (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbOhci          (IN VOID  *FchDataPtr);
+VOID  FchInitLateUsbOhci         (IN VOID  *FchDataPtr);
+VOID  FchInitEnvUsbEhci          (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbEhci          (IN VOID  *FchDataPtr);
+VOID  FchInitLateUsbEhci         (IN VOID  *FchDataPtr);
+VOID  FchInitEnvUsbXhci          (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbXhci          (IN VOID  *FchDataPtr);
+VOID  FchInitLateUsbXhci         (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbOhci1         (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbOhci2         (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbOhci3         (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbOhci4         (IN VOID  *FchDataPtr);
+VOID  FchInitMidUsbEhci1         (IN FCH_DATA_BLOCK  *FchDataPtr);
+VOID  FchInitMidUsbEhci2         (IN FCH_DATA_BLOCK  *FchDataPtr);
+VOID  FchInitMidUsbEhci3         (IN FCH_DATA_BLOCK  *FchDataPtr);
+///
+///  Other Public Routines
+///
+VOID  FchSetUsbEnableReg         (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID  FchOhciInitAfterPciInit    (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+VOID  FchEhciInitAfterPciInit    (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+VOID  FchXhciInitBeforePciInit   (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID  FchXhciInitIndirectReg     (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchInitLateUsbXhciProgram  (IN VOID  *FchDataPtr);
+VOID  FchXhciPowerSavingProgram  (IN FCH_DATA_BLOCK* FchDataPtr);
+
+
+
+///
+/// Fch Sd Routines
+///
+VOID  FchInitEnvSd  (IN VOID  *FchDataPtr);
+VOID  FchInitMidSd  (IN VOID  *FchDataPtr);
+VOID  FchInitLateSd (IN VOID  *FchDataPtr);
+
+///
+///  Other Public Routines
+///
+
+VOID FchInitEnvSdProgram (IN VOID  *FchDataPtr);
+
+///
+/// Fch Spi Routines
+///
+///  Pei Phase
+///
+VOID  FchInitResetSpi        (IN VOID  *FchDataPtr);
+VOID  FchInitResetLpc        (IN VOID  *FchDataPtr);
+VOID  FchInitResetLpcProgram (IN VOID  *FchDataPtr);
+///
+///  Dxe Phase
+///
+VOID  FchInitEnvSpi          (IN VOID  *FchDataPtr);
+VOID  FchInitMidSpi          (IN VOID  *FchDataPtr);
+VOID  FchInitLateSpi         (IN VOID  *FchDataPtr);
+VOID  FchInitEnvLpc          (IN VOID  *FchDataPtr);
+VOID  FchInitMidLpc          (IN VOID  *FchDataPtr);
+VOID  FchInitLateLpc         (IN VOID  *FchDataPtr);
+VOID  FchInitEnvLpcProgram   (IN VOID  *FchDataPtr);
+///
+///  Other Public Routines
+///
+VOID  FchSpiUnlock       (IN VOID  *FchDataPtr);
+VOID  FchSpiLock         (IN VOID  *FchDataPtr);
+
+/*--------------------------- Documentation Pages ---------------------------*/
+VOID  FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  TurnOffCG2 (OUT VOID);
+VOID  BackUpCG2 (OUT VOID);
+VOID  FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
+VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID  AcLossControl (IN UINT8 AcLossControlValue);
+VOID  FchVgaInit (OUT VOID);
+VOID  RecordFchConfigPtr (IN UINT32 FchConfigPtr);
+VOID  ValidateFchVariant (IN VOID  *FchDataPtr);
+VOID  RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN  IsGCPU (IN VOID  *FchDataPtr);
+BOOLEAN  IsExternalClockMode (IN VOID  *FchDataPtr);
+BOOLEAN  IsLpcRom (OUT VOID);
+VOID  SbSleepTrapControl (IN BOOLEAN SleepTrap);
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c
new file mode 100644
index 0000000000..dba06968e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c
@@ -0,0 +1,629 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE
+
+/**< FchStall - Reserved  */
+VOID
+FchStall (
+  IN       UINT32              uSec,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16 timerAddr;
+  UINT32 startTime;
+  UINT32 elapsedTime;
+
+  LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
+  if ( timerAddr == 0 ) {
+    uSec = uSec / 2;
+    while ( uSec != 0 ) {
+      LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader);
+      uSec--;
+    }
+  } else {
+    LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
+    for ( ;; ) {
+      LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
+      if ( elapsedTime < startTime ) {
+        elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
+      } else {
+        elapsedTime = elapsedTime - startTime;
+      }
+      if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
+        break;
+      }
+    }
+  }
+}
+
+/**< cimFchStall - Reserved  */
+VOID
+CimFchStall (
+  IN       UINT32              uSec,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16 timerAddr;
+  UINT32 startTime;
+  UINT32 elapsedTime;
+
+  LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
+  if ( timerAddr == 0 ) {
+    uSec = uSec / 2;
+    while ( uSec != 0 ) {
+      LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
+      uSec--;
+    }
+  } else {
+    LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
+    for ( ;; ) {
+      LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
+      if ( elapsedTime < startTime ) {
+        elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
+      } else {
+        elapsedTime = elapsedTime - startTime;
+      }
+      if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
+        break;
+      }
+    }
+  }
+}
+
+/**< FchReset - Reserved  */
+VOID
+FchPciReset (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   PciRstValue;
+
+  PciRstValue = 0x06;
+  LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader);
+}
+
+/**< outPort80 - Reserved  */
+VOID
+OutPort80 (
+  IN       UINT32              pcode,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader);
+  return;
+}
+
+/**< outPort1080 - Reserved  */
+VOID
+OutPort1080 (
+  IN       UINT32              pcode,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader);
+  return;
+}
+
+/**< FchCopyMem - Reserved  */
+VOID
+FchCopyMem (
+  IN      VOID*   pDest,
+  IN      VOID*   pSource,
+  IN      UINTN   Length
+  )
+{
+  UINTN  i;
+  UINT8  *Ptr;
+  UINT8  *Source;
+  Ptr = (UINT8*)pDest;
+  Source = (UINT8*)pSource;
+  for (i = 0; i < Length; i++) {
+    *Ptr = *Source;
+    Source++;
+    Ptr++;
+  }
+}
+
+/** GetRomSigPtr - Reserved **/
+VOID*
+GetRomSigPtr (
+  IN      UINTN               *RomSigPtr,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32   RomPtr;
+  UINT32   RomSig;
+  UINT16   MswAddr;
+
+  *RomSigPtr = 0;
+  MswAddr = 0xFFF0;
+  do {
+    RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO;
+    LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader);
+    if (RomSig == FCH_ROMSIG_SIGNATURE) {
+      *RomSigPtr = RomPtr;
+      break;
+    }
+    MswAddr <<= 1;
+  } while (MswAddr != 0xFE00);
+  return RomSigPtr;
+}
+
+/** RwXhciIndReg - Reserved **/
+VOID
+RwXhciIndReg (
+  IN       UINT32              Index,
+  IN       UINT32              AndMask,
+  IN       UINT32              OrMask,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32    RevReg;
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+  PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
+  RevReg = ~AndMask;
+  LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+
+  PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+  PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
+  RevReg = ~AndMask;
+  LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+}
+
+/** RwXhci0IndReg - Reserved **/
+VOID
+RwXhci0IndReg (
+  IN       UINT32              Index,
+  IN       UINT32              AndMask,
+  IN       UINT32              OrMask,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32    RevReg;
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+  PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
+  RevReg = ~AndMask;
+  LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+}
+
+/** RwXhci1IndReg - Reserved **/
+VOID
+RwXhci1IndReg (
+  IN       UINT32              Index,
+  IN       UINT32              AndMask,
+  IN       UINT32              OrMask,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32    RevReg;
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+  PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
+  RevReg = ~AndMask;
+  LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+}
+
+/** AcLossControl - Reserved **/
+VOID
+AcLossControl (
+  IN       UINT8 AcLossControlValue
+  )
+{
+  AcLossControlValue &= 0x03;
+  AcLossControlValue |= BIT2;
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue);
+}
+
+/** RecordFchConfigPtr - Reserved **/
+VOID
+RecordFchConfigPtr (
+  IN       UINT32 FchConfigPtr
+  )
+{
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) );
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) );
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) );
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) );
+}
+
+/** ReadAlink - Reserved **/
+UINT32
+ReadAlink (
+  IN       UINT32              Index,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 Data;
+  LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+  LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
+  //Clear Index
+  Index = 0;
+  LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+  return Data;
+}
+
+/** WriteAlink - Reserved **/
+VOID
+WriteAlink (
+  IN       UINT32              Index,
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+  LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
+  //Clear Index
+  Index = 0;
+  LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+}
+
+/** RwAlink - Reserved **/
+VOID
+RwAlink (
+  IN       UINT32              Index,
+  IN       UINT32              AndMask,
+  IN       UINT32              OrMask,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 AccessType;
+
+  AccessType = Index & 0xE0000000;
+  if (AccessType == (AXINDC << 29)) {
+    WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader);
+    Index = FCH_AX_DATAC_REG34 | AccessType;
+  } else if (AccessType == (AXINDP << 29)) {
+    WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
+    Index = FCH_AX_DATAP_REG3C | AccessType;
+  }
+  WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] Address  - PMIO Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadPmio (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8    i;
+
+  OpFlag = OpFlag & 0x7f;
+  OpFlag = 1 << (OpFlag - 1);
+  for (i = 0; i < OpFlag; i++) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
+    Address++;
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO
+ *
+ *
+ *
+ * @param[in] Address  - PMIO Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WritePmio (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8    i;
+
+  OpFlag = OpFlag & 0x7f;
+  OpFlag = 1 << (OpFlag - 1);
+  for (i = 0; i < OpFlag; i++) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
+    Address++;
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RwPmio - Read/Write PMIO
+ *
+ *
+ *
+ * @param[in] Address    - PMIO Offset value
+ * @param[in] OpFlag     - Access sizes
+ * @param[in] AndMask    - Data And Mask 32 bits
+ * @param[in] OrMask     - Data OR Mask 32 bits
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RwPmio (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       UINT32              AndMask,
+  IN       UINT32              OrMask,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 Result;
+
+  ReadPmio (Address, OpFlag, &Result, StdHeader);
+  Result = (Result & AndMask) | OrMask;
+  WritePmio (Address, OpFlag, &Result, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO2
+ *
+ *
+ *
+ * @param[in] Address  - PMIO2 Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadPmio2 (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8 i;
+
+  OpFlag = OpFlag & 0x7f;
+  OpFlag = 1 << (OpFlag - 1);
+  for ( i = 0; i < OpFlag; i++ ) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
+    Address++;
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO 2
+ *
+ *
+ *
+ * @param[in] Address  - PMIO2 Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WritePmio2 (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8 i;
+
+  OpFlag = OpFlag & 0x7f;
+  OpFlag = 1 << (OpFlag - 1);
+
+  for ( i = 0; i < OpFlag; i++ ) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
+    Address++;
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RwPmio2 - Read/Write PMIO2
+ *
+ *
+ *
+ * @param[in] Address    - PMIO2 Offset value
+ * @param[in] OpFlag     - Access sizes
+ * @param[in] AndMask    - Data And Mask 32 bits
+ * @param[in] OrMask     - Data OR Mask 32 bits
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RwPmio2 (
+  IN       UINT8 Address,
+  IN       UINT8  OpFlag,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 Result;
+
+  ReadPmio2 (Address, OpFlag, &Result, StdHeader);
+  Result = (Result & AndMask) | OrMask;
+  WritePmio2 (Address, OpFlag, &Result, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read BIOSRAM
+ *
+ *
+ *
+ * @param[in] Address  - BIOSRAM Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadBiosram (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8    i;
+
+  OpFlag = OpFlag & 0x7f;
+  OpFlag = 1 << (OpFlag - 1);
+  for (i = 0; i < OpFlag; i++) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
+    Address++;
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write BIOSRAM
+ *
+ *
+ *
+ * @param[in] Address  - BIOSRAM Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WriteBiosram (
+  IN       UINT8               Address,
+  IN       UINT8               OpFlag,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8    i;
+
+  OpFlag = OpFlag & 0x7f;
+  OpFlag = 1 << (OpFlag - 1);
+  for (i = 0; i < OpFlag; i++) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
+    Address++;
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Record SMI Status
+ *
+ *
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RecordSmiStatus (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINTN   Index;
+  UINT8   SwSmiValue;
+
+  ACPIMMIO8 (0xfed80320) |= 0x01;
+  for ( Index = 0; Index < 20; Index++ ) {
+    ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index);
+  }
+  LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader);
+  ACPIMMIO8 (0xfed10040) = SwSmiValue;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c
new file mode 100644
index 0000000000..7cd64b7c26
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c
@@ -0,0 +1,351 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramPciByteTable - Program PCI register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pPciByteTable    - Table data pointer
+ * @param[in] dwTableSize      - Table length
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ProgramPciByteTable (
+  IN       REG8_MASK           *pPciByteTable,
+  IN       UINT16              dwTableSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8     i;
+  UINT8     dbBusNo;
+  UINT8     dbDevFnNo;
+  UINT8     Or8;
+  UINT8     Mask8;
+  PCI_ADDR  PciAddress;
+
+  dbBusNo = pPciByteTable->RegIndex;
+  dbDevFnNo = pPciByteTable->AndMask;
+  pPciByteTable++;
+
+  for ( i = 1; i < dwTableSize; i++ ) {
+    if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {
+      pPciByteTable++;
+      dbBusNo = pPciByteTable->RegIndex;
+      dbDevFnNo = pPciByteTable->AndMask;
+      pPciByteTable++;
+      i++;
+    } else {
+      PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;
+      Or8 = pPciByteTable->OrMask;
+      Mask8 = ~pPciByteTable->AndMask;
+      LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);
+      pPciByteTable++;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pAcpiTbl   - Table data pointer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ProgramFchAcpiMmioTbl (
+  IN       ACPI_REG_WRITE      *pAcpiTbl,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   i;
+  UINT8   Or8;
+  UINT8   Mask8;
+  UINT32  ddtempVar;
+
+  if (pAcpiTbl != NULL) {
+    if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
+      // Signature Checking
+      pAcpiTbl++;
+      for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
+        ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
+        Or8 = pAcpiTbl->DataOrMask;
+        Mask8 = ~pAcpiTbl->DataAndMask;
+        LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader);
+        pAcpiTbl++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pSciMapTbl   - Table data pointer
+ * @param[in] FchResetDataBlock
+ *
+ */
+VOID
+ProgramFchSciMapTbl (
+  IN       SCI_MAP_CONTROL  *pSciMapTbl,
+  IN       FCH_RESET_DATA_BLOCK *FchResetDataBlock
+  )
+{
+  AMD_CONFIG_PARAMS   *StdHeader;
+
+  UINT32  ddtempVar;
+  StdHeader = FchResetDataBlock->StdHeader;
+
+  if (pSciMapTbl != NULL) {
+    while (pSciMapTbl->InputPin != 0xFF) {
+      if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) {
+        ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin;
+        if (((pSciMapTbl->InputPin == 0x78 ) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \
+           ((pSciMapTbl->InputPin == 0x79 ) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) {
+        } else {
+          LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader);
+        }
+      } else {
+        //Assert Warning "SCI map is invalid"
+      }
+      pSciMapTbl++;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pGpioTbl   - Table data pointer
+ * @param[in] FchResetDataBlock
+ *
+ */
+VOID
+ProgramFchGpioTbl (
+  IN       GPIO_CONTROL  *pGpioTbl,
+  IN       FCH_RESET_DATA_BLOCK *FchResetDataBlock
+  )
+{
+  AMD_CONFIG_PARAMS   *StdHeader;
+
+  UINT32  ddtempVar;
+  StdHeader = FchResetDataBlock->StdHeader;
+
+  if (pGpioTbl != NULL) {
+    while (pGpioTbl->GpioPin != 0xFF) {
+      ddtempVar = ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin;
+      LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->PinFunction, StdHeader);
+      ddtempVar = ACPI_MMIO_BASE | GPIO_BASE | pGpioTbl->GpioPin;
+      LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->CfgByte, StdHeader);
+      pGpioTbl++;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pSataPhyTbl   - Table data pointer
+ * @param[in] FchResetDataBlock
+ *
+ */
+VOID
+ProgramFchSataPhyTbl (
+  IN       SATA_PHY_CONTROL  *pSataPhyTbl,
+  IN       FCH_RESET_DATA_BLOCK *FchResetDataBlock
+  )
+{
+  AMD_CONFIG_PARAMS   *StdHeader;
+
+  //UINT32  ddtempVar;
+  StdHeader = FchResetDataBlock->StdHeader;
+
+  if (pSataPhyTbl != NULL) {
+    while (pSataPhyTbl->PhyData != 0xFFFFFFFF) {
+      //to be implemented
+      pSataPhyTbl++;
+    }
+  }
+}
+
+/**
+ * GetChipSysMode - Get Chip status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ *   StrapStatus [15.0] - Hudson-2 chip Strap Status
+ *    @li <b>0001</b> - Not USED FWH
+ *    @li <b>0002</b> - Not USED LPC ROM
+ *    @li <b>0004</b> - EC enabled
+ *    @li <b>0008</b> - Reserved
+ *    @li <b>0010</b> - Internal Clock mode
+ * @param[in] StdHeader
+ *
+ */
+VOID
+GetChipSysMode (
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader);
+}
+
+/**
+ * IsImcEnabled - Is IMC Enabled
+ * @retval  TRUE for IMC Enabled; FALSE for IMC Disabled
+ */
+BOOLEAN
+IsImcEnabled (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   dbSysConfig;
+  GetChipSysMode (&dbSysConfig, StdHeader);
+  if (dbSysConfig & ChipSysEcEnable) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+
+/**
+ * GetEfuseStatue - Get Efuse status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ * @param[in] StdHeader
+ *
+ */
+VOID
+GetEfuseStatus (
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8    Or8;
+  UINT8    Mask8;
+
+  Or8 = BIT5;
+  Mask8 = BIT5;
+  LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
+  LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 ), Value, StdHeader);
+  LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8  + 1), Value, StdHeader);
+  Or8 = 0;
+  Mask8 = BIT5;
+  LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SbSleepTrapControl - SB Sleep Trap Control
+ *
+ *
+ *
+ * @param[in] SleepTrap    - Whether sleep trap is enabled
+ *
+ */
+VOID
+SbSleepTrapControl (
+  IN        BOOLEAN          SleepTrap
+  )
+{
+  if (SleepTrap) {
+    ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
+    ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2;
+
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) &= ~ (BIT5);
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1;
+  } else {
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) |= BIT5;
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0;
+
+    ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c
new file mode 100644
index 0000000000..d80f74e100
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c
@@ -0,0 +1,171 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH memory access lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE
+
+
+/**
+ * ReadMem - Read FCH BAR Memory
+ *
+ * @param[in] Address    - Memory BAR address
+ * @param[in] OpFlag     - Access width
+ * @param[in] *ValuePtr  - In/Out value pointer
+ *
+ */
+VOID
+ReadMem (
+  IN  UINT32     Address,
+  IN  UINT8      OpFlag,
+  IN  VOID       *ValuePtr
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+
+  switch ( OpFlag ) {
+  case AccessWidth8:
+    *((UINT8*)ValuePtr) = *((UINT8*) ((UINTN)Address));
+    break;
+
+  case AccessWidth16:
+    *((UINT16*)ValuePtr) = *((UINT16*) ((UINTN)Address));
+    break;
+
+  case AccessWidth32:
+    *((UINT32*)ValuePtr) = *((UINT32*) ((UINTN)Address));
+    break;
+
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+}
+
+/**
+ * WriteMem - Write FCH BAR Memory
+ *
+ * @param[in] Address    - Memory BAR address
+ * @param[in] OpFlag     - Access width
+ * @param[in] *ValuePtr  - In/Out Value pointer
+ *
+ */
+VOID
+WriteMem (
+  IN  UINT32     Address,
+  IN  UINT8      OpFlag,
+  IN  VOID       *ValuePtr
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+
+  switch ( OpFlag ) {
+  case AccessWidth8 :
+    *((UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr);
+    break;
+
+  case AccessWidth16:
+    *((UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr);
+    break;
+
+  case AccessWidth32:
+    *((UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr);
+    break;
+
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+}
+
+/**
+ * RwMem - Read & Write FCH BAR Memory
+ *
+ * @param[in] Address    - Memory BAR address
+ * @param[in] OpFlag     - Access width
+ * @param[in] Mask       - Mask Value of data
+ * @param[in] Data       - Write data
+ *
+ */
+VOID
+RwMem (
+  IN  UINT32     Address,
+  IN  UINT8      OpFlag,
+  IN  UINT32     Mask,
+  IN  UINT32     Data
+  )
+{
+  UINT32 Result;
+
+  ReadMem (Address, OpFlag, &Result);
+  Result = (Result & Mask) | Data;
+  WriteMem (Address, OpFlag, &Result);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c
new file mode 100644
index 0000000000..f63710ed64
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH PCI access lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE
+
+VOID
+ReadPci (
+  IN       UINT32                  Address,
+  IN       UINT8                   OpFlag,
+  IN       VOID*                   Value,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
+  LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
+}
+
+
+VOID
+WritePci (
+  IN       UINT32                  Address,
+  IN       UINT8                   OpFlag,
+  IN       VOID                    *Value,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
+  LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
+}
+
+
+VOID
+RwPci (
+  IN       UINT32                  Address,
+  IN       UINT8                   OpFlag,
+  IN       UINT32                  Mask,
+  IN       UINT32                  Data,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    rMask;
+
+  PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
+  rMask = ~Mask;
+  LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
new file mode 100644
index 0000000000..963d96da66
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
@@ -0,0 +1,1653 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH registers definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 64988 $   @e \$Date: 2012-02-06 03:07:17 -0600 (Mon, 06 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#define FCH_REVISION       "0.0.5.0"
+#define FCH_ID             "FCH_A05"
+#define FCH_VERSION        0x0000
+
+/**
+ * @page fchinitguide FCH implement phase in AGESA
+ *
+ * FCH provides below access to supported FCH service functions
+ * and data.
+ *   - @subpage fchreset "FCH_INIT_RESET"
+ *   - @subpage fchenv "FCH_INIT_ENV"
+ *   - @subpage fchmid "FCH_INIT_MID"
+ *   - @subpage fchlate "FCH_INIT_LATE"
+ *   - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE"
+ *   - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE"
+ *   - @subpage fchsmm "FCH_SMM_SERVICE"
+ *   - @subpage fchsmmacpion "FCH_SMM_ACPION"
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchreset FCH_INIT_RESET
+ *  @section FCH_INIT_RESET Interface Call
+ *  @par
+ *     Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value.
+ *  @subsection FCH_INIT_RESET_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams);
+ *  @subsection FCH_INIT_RESET_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_INIT_RESET_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase   </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr   </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr    </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr     </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable      </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable       </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchenv FCH_INIT_ENV
+ *  @section FCH_INIT_ENV Interface Call
+ *  @par
+ *     Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ *  @subsection FCH_INIT_ENV_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams);
+ *  @subsection FCH_INIT_ENV_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_INIT_ENV_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig              </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig              </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass             </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchmid FCH_INIT_MID
+ *  @section FCH_INIT_MID Interface Call
+ *  @par
+ *     Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ *  @subsection FCH_INIT_MID_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams);
+ *  @subsection FCH_INIT_MID_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_INIT_MID_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable             </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @section FCH_INIT_LATE Interface Call
+ *  @par
+ *     Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ *  @subsection FCH_INIT_LATE_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS FchInitLate (IN AMD_S3SAVE_PARAMS *LateParams);
+ *  @subsection FCH_INIT_LATE_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_INIT_LATE_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass             </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchs3early FCH_INIT_S3_EARLY_RESTORE
+ *  @section FCH_INIT_S3_EARLY_RESTORE Interface Call
+ *  @par
+ *     Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ *  @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype
+ *  @par
+ *     VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ *  @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig              </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig              </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass             </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable           </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchs3late FCH_INIT_S3_LATE_RESTORE
+ *  @section FCH_INIT_S3_LATE_RESTORE Interface Call
+ *  @par
+ *     Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ *  @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype
+ *  @par
+ *     VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ *  @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass             </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable             </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch            </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress  </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchsmm FCH_SMM_SERVICE
+ *  @section FCH_SMM_SERVICE Interface Call
+ *  Initialize structure referenced by FCHCFG to default recommended value.
+ *  @subsection FCH_SMM_SERVICE_CallIn Call Prototype
+ *  @par
+ *     FchSmmService ((FCHCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection FCH_SMM_SERVICE_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE  --> 0x00010060 </TD></TR>
+ *  </TABLE>
+ *  @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_SERVICE              0x00010060ul
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page fchsmmacpion FCH_SMM_ACPION
+ *  @section FCH_SMM_ACPION Interface Call
+ *  Initialize structure referenced by FCHCFG to default recommended value.
+ *  @subsection FCH_SMM_ACPION_CallIn Call Prototype
+ *  @par
+ *     FchSmmAcpiOn ((FCHCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection FCH_SMM_ACPION_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> FCH_SMM_ACPION  --> 0x00010061 </TD></TR>
+ *  </TABLE>
+ *  @subsection FCH_SMM_ACPION_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_ACPION               0x00010061ul
+
+#ifndef OEM_CALLBACK_BASE
+  #define OEM_CALLBACK_BASE         0x00010100ul
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING        OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS  OEM_CALLBACK_BASE + 0x20
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ *  @section CB_SBGPP_RESET_ASSERT Interface Call
+ *  Initialize structure referenced by FCHCFG to default recommended value.
+ *  @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT  --> 0x00010130 </TD></TR>
+ *  </TABLE>
+ *  @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_ASSERT       OEM_CALLBACK_BASE + 0x30
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ *  @section CB_SBGPP_RESET_DEASSERT  Interface Call
+ *  Initialize structure referenced by FCHCFG to default recommended value.
+ *  @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT   --> 0x00010131 </TD></TR>
+ *  </TABLE>
+ *  @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_DEASSERT     OEM_CALLBACK_BASE + 0x31
+
+#define CFG_ADDR_PORT               0xCF8
+#define CFG_DATA_PORT               0xCFC
+
+#define ALINK_ACCESS_INDEX          0x0CD8
+#define ALINK_ACCESS_DATA           ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT                  0x0E0
+
+#define FCH_8259_CONTROL_REG_MASTER 0x20
+#define FCH_8259_MASK_REG_MASTER    0x21
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+// ASIC VendorID and DeviceIDs
+#define ATI_VID                      0x1002
+#define AMD_FCH_VID                  0x1022
+#define FCH_DEVICE_ID                0x780B
+#define FCH_SATA_VID                 AMD_FCH_VID      // Dev 17 Func 0
+#define FCH_SATA_DID                 0x7800
+#define FCH_SATA_AHCI_DID            0x7801
+#define FCH_SATA_RAID_DID            0x7802
+#define FCH_SATA_RAID5_DID           0x7803
+#define FCH_SATA_AMDAHCI_DID         0x7804
+#define FCH_USB_OHCI_VID             AMD_FCH_VID      // Dev 18 Func 0, Dev 19 Func 0
+#define FCH_USB_OHCI_DID             0x7807
+#define FCH_USB_EHCI_VID             AMD_FCH_VID      // Dev 18 Func 2, Dev 19 Func 2
+#define FCH_USB_EHCI_DID             0x7808
+#define FCH_USB_XHCI_VID             AMD_FCH_VID      // Dev 10 Func 0, Dev 10 Func 1
+#define FCH_USB_XHCI_DID             0x7812
+#define FCH_SMBUS_VID                AMD_FCH_VID      // Dev 20 Func 0
+#define FCH_SMBUS_DID                0x780B
+#define FCH_IDE_VID                  AMD_FCH_VID      // Dev 20 Func 1
+#define FCH_IDE_DID                  0x780C
+#define FCH_LPC_VID                  AMD_FCH_VID      // Dev 20 Func 3
+#define FCH_LPC_DID                  0x780E
+#define FCH_PCIB_VID                 AMD_FCH_VID      // Dev 20 Func 4
+#define FCH_PCIB_DID                 0x780F
+#define FCH_USB_OHCIF_VID            AMD_FCH_VID      // dev 20 Func 5
+#define FCH_USB_OHCIF_DID            0x7809
+#define FCH_NIC_VID                  0x14E4          // Dev 20 Func 6
+#define FCH_NIC_DID                  0x1699
+#define FCH_SD_VID                   AMD_FCH_VID      // Dev 20 Func 7
+#define FCH_SD_DID                   0x7806
+
+//FCH Variant
+#define FCH_Variant_EFUSE_LOCATION        0x1E        // EFUSE bit 240-247
+
+#define FCH_M2                            0x01
+#define FCH_M3                            0x03
+#define FCH_M3T                           0x07
+#define FCH_D2                            0x0F
+#define FCH_D3                            0x1F
+#define FCH_D4                            0x3F
+
+
+//Misc
+#define R_FCH_ACPI_PM1_STATUS              0x00
+#define R_FCH_ACPI_PM1_ENABLE              0x02
+#define R_FCH_ACPI_PM_CONTROL              0x04
+#define R_FCH_ACPI_EVENT_STATUS            0x20
+#define R_FCH_ACPI_EVENT_ENABLE            0x24
+#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO       0x2C
+
+// ACPI Sleep Type
+#define ACPI_SLPTYP_S0                     0
+#define ACPI_SLPTYP_S1                     1
+#define ACPI_SLPTYP_S3                     3
+#define ACPI_SLPTYP_S4                     4
+#define ACPI_SLPTYP_S5                     5
+
+//#define SATA_BUS_DEV_FUN_FPGA            0x228
+#define SATA_BUS_DEV_FUN            ((0x11 << 3) + 0)
+#define FCH_SATA1_BUS        0
+#define FCH_SATA1_DEV        17
+#define FCH_SATA1_FUNC       0
+
+#define FC_BUS_DEV_FUN              ((0x11 << 3) + 1)
+#define FCH_XHCI_BUS        0
+#define FCH_XHCI_DEV        16
+#define FCH_XHCI_FUNC       0
+#define USB_XHCI_BUS_DEV_FUN        ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC)
+#define FCH_XHCI1_BUS        0
+#define FCH_XHCI1_DEV        16
+#define FCH_XHCI1_FUNC       1
+#define USB_XHCI1_BUS_DEV_FUN       ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC)
+#define USB1_OHCI_BUS_DEV_FUN       ((0x12 << 3) + 0)    // PORT 0-4
+#define FCH_OHCI1_BUS        0
+#define FCH_OHCI1_DEV        18
+#define FCH_OHCI1_FUNC       0
+#define USB2_OHCI_BUS_DEV_FUN       ((0x13 << 3) + 0)    // PORT 5-9
+#define FCH_OHCI2_BUS        0
+#define FCH_OHCI2_DEV        19
+#define FCH_OHCI2_FUNC       0
+#define USB3_OHCI_BUS_DEV_FUN       ((0x16 << 3) + 0)    // PORT 10-13
+#define FCH_OHCI3_BUS        0
+#define FCH_OHCI3_DEV        22
+#define FCH_OHCI3_FUNC       0
+#define USB1_EHCI_BUS_DEV_FUN       ((0x12 << 3) + 2)    // PORT 0-4
+#define FCH_EHCI1_BUS        0
+#define FCH_EHCI1_DEV        18
+#define FCH_EHCI1_FUNC       2
+#define USB2_EHCI_BUS_DEV_FUN       ((0x13 << 3) + 2)    // PORT 5-9
+#define FCH_EHCI2_BUS        0
+#define FCH_EHCI2_DEV        19
+#define FCH_EHCI2_FUNC       2
+#define USB3_EHCI_BUS_DEV_FUN       ((0x16 << 3) + 2)  // PORT 10-13
+#define FCH_EHCI3_BUS        0
+#define FCH_EHCI3_DEV        22
+#define FCH_EHCI3_FUNC       2
+#define SMBUS_BUS_DEV_FUN           ((0x14 << 3) + 0)
+#define FCH_ISA_BUS          0
+#define FCH_ISA_DEV          20
+#define FCH_ISA_FUNC         0
+#define IDE_BUS_DEV_FUN             ((0x14 << 3) + 1)
+#define FCH_IDE_BUS          0
+#define FCH_IDE_DEV          20
+#define FCH_IDE_FUNC         1
+#define LPC_BUS_DEV_FUN             ((0x14 << 3) + 3)
+#define FCH_LPC_BUS          0
+#define FCH_LPC_DEV          20
+#define FCH_LPC_FUNC         3
+#define PCIB_BUS_DEV_FUN            ((0x14 << 3) + 4)    // P2P in SB700
+#define FCH_PCI_BUS          0
+#define FCH_PCI_DEV          20
+#define FCH_PCI_FUNC         4
+#define USB4_OHCI_BUS_DEV_FUN       ((0x14 << 3) + 5)    // PORT FL0 - FL1
+#define FCH_OHCI4_BUS        0
+#define FCH_OHCI4_DEV        20
+#define FCH_OHCI4_FUNC       5
+//Gigabyte Ethernet Controller
+#define GEC_BUS_DEV_FUN             ((0x14 << 3) + 6)
+#define FCH_GBEC_BUS         0
+#define FCH_GBEC_DEV         20
+#define FCH_GBEC_FUNC        6
+
+#define SD_BUS_DEV_FUN            ((0x14 << 3) + 7)      // SD Controller
+#define SD_PCI_BUS          0
+#define SD_PCI_DEV          20
+#define SD_PCI_FUNC         7
+#define SD_PCI_REG10        0x10
+#define SD_PCI_REG2C        0x2C
+#define SD_PCI_REGA4        0xA4
+#define SD_PCI_REGA8        0xA8
+#define SD_PCI_REGAC        0xAC
+#define SD_PCI_REGB0        0xB0
+
+
+#define FCH_GPP_BUS          0
+#define FCH_GPP_DEV          21
+#define FCH_GPP_FUNC         0
+#define GPP0_BUS_DEV_FUN            ((0x15 << 3) + 0)    // GPP P2P bridge PORT0
+#define GPP1_BUS_DEV_FUN            ((0x15 << 3) + 1)    // GPP P2P bridge PORT1
+#define GPP2_BUS_DEV_FUN            ((0x15 << 3) + 2)    // GPP P2P bridge PORT2
+#define GPP3_BUS_DEV_FUN            ((0x15 << 3) + 3)    // GPP P2P bridge PORT3
+
+#define ACPI_MMIO_BASE  0xFED80000ul
+#define FCH_CFG_BASE     0x000   // DWORD
+#define GPIO_BASE       0x100   // BYTE
+#define SMI_BASE        0x200   // DWORD
+#define PMIO_BASE       0x300   // DWORD
+#define PMIO2_BASE      0x400   // BYTE
+#define BIOS_RAM_BASE   0x500   // BYTE
+#define CMOS_RAM_BASE   0x600   // BYTE
+#define CMOS_BASE       0x700   // BYTE
+#define ASF_BASE        0x900   // DWORD
+#define SMBUS_BASE      0xA00   // DWORD
+#define WATCHDOG_BASE   0xB00   //
+#define HPET_BASE       0xC00   // DWORD
+#define IOMUX_BASE      0xD00   // BYTE
+#define MISC_BASE       0xE00
+#define SERIAL_DEBUG_BASE  0x1000
+#define GFX_DAC_BASE       0x1400
+#define CEC_BASE           0x1800
+#define XHCI_BASE          0x1C00
+
+
+// RegSpace field (AB_INDEX[31:29]
+#define AXINDC         0               // AXINDC
+#define AXINDP         2               // AXINDP
+#define ABCFG          6               // ABCFG
+#define AXCFG          4               // AXCFG
+#define RCINDXC        1               // PCIEIND
+#define RCINDXP        3               // PCIEIND_P
+
+#define GPP_DEV_NUM    21              //
+#define MAX_GPP_PORTS  4
+
+#define PCIE_FORCE_GEN1_EFUSE_LOCATION     0x14    // EFUSE bit 160
+//
+// ABCFG Registers
+//
+#define FCH_ABCFG_REG00     0x00  // VENDOR ID
+#define FCH_ABCFG_REG08     0x08  // REVISION ID
+#define FCH_ABCFG_REG40     0x40  // BL_EVENTCNT0LO
+#define FCH_ABCFG_REG44     0x44  // BL_EVENTCNT1LO
+#define FCH_ABCFG_REG48     0x48  // BL_EVENTCNTSEL
+#define FCH_ABCFG_REG4A     0x4A  // BL_EVENTCNT0HI
+#define FCH_ABCFG_REG4B     0x4B  // BL_EVENTCNT1HI
+#define FCH_ABCFG_REG4C     0x4C  // BL_EVENTCNTCTL
+#define FCH_ABCFG_REG50     0x50  // MISCCTL_50
+#define FCH_ABCFG_REG54     0x54  // MISCCTL_54
+#define FCH_ABCFG_REG58     0x58  // BL RAB CONTROL
+
+#define FCH_ABCFG_REG60     0x60  // LINKWIDTH_CTL
+#define FCH_ABCFG_REG64     0x64  // LINKWIDTH_UP_INTERVAL
+#define FCH_ABCFG_REG68     0x68  // LINKWIDTH_DN_INVERVAL
+#define FCH_ABCFG_REG6C     0x6C  // LINKWIDTH_UPSTREAM_DWORDS
+#define FCH_ABCFG_REG70     0x70  // LINKWIDTH_DOWNSTREAM_DWORDS
+#define FCH_ABCFG_REG74     0x74  // LINKWIDTH_THRESHOLD_INCREASE
+#define FCH_ABCFG_REG78     0x78  // LINKWIDTH_THRESHOLD_DECREASE
+
+#define FCH_ABCFG_REG80     0x80  // BL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG88     0x88  //
+#define FCH_ABCFG_REG90     0x90  // BIF CONTROL 0
+#define FCH_ABCFG_REG94     0x94  // MSI CONTROL
+#define FCH_ABCFG_REG98     0x98  // BIF CONTROL 1
+#define FCH_ABCFG_REG9C     0x9C  // MISCCTL_9C
+#define FCH_ABCFG_REGA0     0xA0  // BIF PHY CONTROL ENABLE
+#define FCH_ABCFG_REGA4     0xA4  // BIF PHY CONTROL A4
+#define FCH_ABCFG_REGA8     0xA8  // BIF PHY CONTROL A8
+#define FCH_ABCFG_REGB4     0xB4  //
+#define FCH_ABCFG_REGC0     0xC0  // PCIE_GPP_ENABLE
+#define FCH_ABCFG_REGF0     0xF0  // GPP_UPSTREAM_CONTROL
+#define FCH_ABCFG_REGF4     0xF4  // GPP_SYSTEM_ERROR_CONTROL
+#define FCH_ABCFG_REG208    0x208 // KR New
+#define FCH_ABCFG_REG300    0x300 // MCTP_VDM_RX_SMI_CONTROL
+#define FCH_ABCFG_REG31C    0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
+#define FCH_ABCFG_REG330    0x330 // BIF_GPP_STRAP_BIF_0
+#define FCH_ABCFG_REG340    0x340 // BIF_GPP_STRAP_BIF_LANE_A
+#define FCH_ABCFG_REG344    0x344 // BIF_GPP_STRAP_BIF_LANE_B
+#define FCH_ABCFG_REG348    0x348 // BIF_GPP_STRAP_BIF_LANE_C
+#define FCH_ABCFG_REG34C    0x34C // BIF_GPP_STRAP_BIF_LANE_D
+#define FCH_ABCFG_REG404    0x404 // GPP0_SHADOW_COMMAND
+#define FCH_ABCFG_REG418    0x418 // GPP0_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG41C    0x41C // GPP0_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG420    0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG424    0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG428    0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG42C    0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG430    0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG43C    0x43C // GPP0_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG444    0x444 // GPP1_SHADOW_COMMAND
+#define FCH_ABCFG_REG458    0x458 // GPP1_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG45C    0x45C // GPP1_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG460    0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG464    0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG468    0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG46C    0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG470    0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG47C    0x47C // GPP1_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG484    0x484 // GPP2_SHADOW_COMMAND
+#define FCH_ABCFG_REG498    0x498 // GPP2_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG49C    0x49C // GPP2_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4A0    0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A4    0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A8    0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4AC    0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4B0    0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4BC    0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG4C4    0x4C4 // GPP3_SHADOW_COMMAND
+#define FCH_ABCFG_REG4D8    0x4D8 // GPP3_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG4DC    0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4E0    0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E4    0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E8    0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4EC    0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4F0    0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4FC    0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG10040  0x10040ul  // AL_EVENTCNT0LO
+#define FCH_ABCFG_REG10044  0x10044ul  // AL_EVENTCNT1LO
+#define FCH_ABCFG_REG1004A  0x1004Aul  // AL_EVENTCNT0HI
+#define FCH_ABCFG_REG1004B  0x1004Bul  // AL_EVENTCNT1HI
+#define FCH_ABCFG_REG10050  0x10050ul  // MISCCTL_10050
+#define FCH_ABCFG_REG10054  0x10054ul  // AL_ARB_CTL
+#define FCH_ABCFG_REG10056  0x10056ul  // AL_CLK_CTL
+#define FCH_ABCFG_REG10058  0x10058ul  // AL RAB CONTROL
+#define FCH_ABCFG_REG1005C  0x1005Cul  // AL MLT CONTROL
+#define FCH_ABCFG_REG10060  0x10060ul  // AL DMA PREFETCH ENABLE
+#define FCH_ABCFG_REG10064  0x10064ul  // AL DMA PREFETCH FLUSH CONTROL
+#define FCH_ABCFG_REG10068  0x10068ul  // AL PREFETCH LIMIT
+#define FCH_ABCFG_REG1006C  0x1006Cul  // AL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG10070  0x10070ul  // MISCCTL_10070
+#define FCH_ABCFG_REG10080  0x10080ul  // CLKMUXSTATUS
+#define FCH_ABCFG_REG10090  0x10090ul  // BIF CONTROL 0
+#define FCH_ABCFG_REG1009C  0x1009Cul  // MISCCTL_1009C
+
+//
+// RCINDX_P Registers
+//
+#define FCH_RCINDXP_REG01   0x01 | RCINDXP << 29 // PCIEP_SCRATCH
+#define FCH_RCINDXP_REG02   0x02 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG10   0x10 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG20   0x20 | RCINDXP << 29 // PCIE_TX_CNTL
+#define FCH_RCINDXP_REG21   0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
+#define FCH_RCINDXP_REG50   0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
+#define FCH_RCINDXP_REG6A   0x6A | RCINDXP << 29 //
+#define FCH_RCINDXP_REG70   0x70 | RCINDXP << 29 // PCIE_RX_CNTL
+#define FCH_RCINDXP_REGA0   0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
+#define FCH_RCINDXP_REGA1   0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
+#define FCH_RCINDXP_REGA2   0xA2 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA4   0xA4 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA5   0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
+#define FCH_RCINDXP_REGC0   0xC0 | RCINDXP << 29 //
+
+//
+// RCINDX_C Registers
+//
+#define FCH_RCINDXC_REG02   0x02 | RCINDXC << 29  // PCIE_HW_DEBUG
+#define FCH_RCINDXC_REG10   0x10 | RCINDXC << 29  // PCIE_CNTL
+#define FCH_RCINDXC_REG40   0x40 | RCINDXC << 29  // PCIE_P_CNTL
+#define FCH_RCINDXC_REG65   0x65 | RCINDXC << 29  // PCIE_P_PAD_FORCE_DIS
+#define FCH_RCINDXC_REGC0   0xC0 | RCINDXC << 29  // PCIE_STRAP_MISC
+#define FCH_RCINDXC_REGC1   0xC1 | RCINDXC << 29  // PCIE_STRAP_MISC2
+
+
+//
+// AXINDC Registers
+//
+#define FCH_AX_INDXC_REG02  0x02 // PCIEP_HW_DEBUG
+#define FCH_AX_INDXC_REG10  0x10
+#define FCH_AX_INDXC_REG30  0x30
+#define FCH_AX_DATAC_REG34  0x34
+#define FCH_AX_INDXP_REG38  0x38
+#define FCH_AX_DATAP_REG3C  0x3C
+#define FCH_AX_INDXC_REG40  0x40 | AXINDC << 29
+#define FCH_AX_INDXC_REGA4  0xA4 | AXINDC << 29
+
+#define FCH_AX_INDXP_REG02  0x02 | AXINDP << 29
+#define FCH_AX_INDXP_REGA0  0xA0 | AXINDP << 29
+#define FCH_AX_INDXP_REGA4  0xA4 | AXINDP << 29
+#define FCH_AX_INDXP_REGB1  0xB1 | AXINDP << 29
+
+#define FCH_AX_CFG_REG68  0x68 | AXCFG << 29
+#define FCH_AX_CFG_REG88  0x88 | AXCFG << 29
+
+#define FCH_AB_REG04         0x04
+#define FCH_AB_REG40         0x40
+
+//Sata Port Configuration
+#define SIX_PORTS       0
+#define FOUR_PORTS      1
+
+#define SATA_EFUSE_LOCATION     0x10    // EFUSE bit 133
+#define SATA_FIS_BASE_EFUSE_LOC 0x15    // EFUSE bit 169
+#define SATA_EFUSE_BIT          0x20    //
+
+#define FCH_SATA_BAR5_REG100     0x0100  // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define FCH_SATA_BAR5_REG104     0x0104  // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define FCH_SATA_BAR5_REG108     0x0108  // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define FCH_SATA_BAR5_REG10C     0x010C  // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define FCH_SATA_BAR5_REG120     0x0120  //
+#define FCH_SATA_BAR5_REG128     0x0128  // Port Serial ATA Status
+#define FCH_SATA_BAR5_REG12C     0x012C  // Port Serial ATA Control
+#define FCH_SATA_BAR5_REG130     0x0130
+#define FCH_SATA_BAR5_REG1B0     0x01B0
+#define FCH_SATA_BAR5_REG230     0x0230
+#define FCH_SATA_BAR5_REG2B0     0x02B0
+#define FCH_SATA_BAR5_REG330     0x0330
+#define FCH_SATA_BAR5_REG3B0     0x03B0
+
+
+// USB ports
+#define NUM_USB1_PORTS           5
+#define NUM_USB2_PORTS           5
+#define NUM_USB3_PORTS           4
+#define NUM_USB4_PORTS           2
+#define NUM_XHC0_PORTS           2
+#define NUM_XHC1_PORTS           2
+
+
+// Chip type definition
+#define CHIPTYPE_HUDSON2         (1 << 0)
+#define CHIPTYPE_YUBA            (1 << 1)
+
+
+//
+//  USB XHCI Device 0x7812
+//  Device 16 (0x10) Func 0/1
+//
+#define XHCI_EFUSE_LOCATION      0x18        // EFUSE bit 192, 193
+#define FCH_XHCI_REG48           0x48        // Port Force Reset - RW (800)
+#define FCH_XHCI_REG4C           0x4C        // MSI - RW   (800)
+//
+//  USB OHCI Device 0x7807
+//  Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
+//  Device 20 (0x14) Func 5 (FL) 0x7809
+//
+#define FCH_OHCI_REG00           0x00        // Device/Vendor ID - R (0x43971002ul)
+#define FCH_OHCI_REG04           0x04        // Command - RW
+#define FCH_OHCI_REG06           0x06        // Status - R
+#define FCH_OHCI_REG08           0x08        // Revision ID/Class Code - R
+#define FCH_OHCI_REG0C           0x0C        // Miscellaneous - RW
+#define FCH_OHCI_REG10           0x10        // Bar_OCI - RW
+#define FCH_OHCI_REG2C           0x2C        // Subsystem Vendor ID/ Subsystem ID - RW
+#define FCH_OHCI_REG34           0x34        // Capability Pointer - R
+#define FCH_OHCI_REG3C           0x3C        // Interrupt Line - RW
+#define FCH_OHCI_REG3D           0x3D        // Interrupt Line - RW
+#define FCH_OHCI_REG40           0x40        // Config Timers - RW
+#define FCH_OHCI_REG42           0x42        // Port Disable Control - RW (800)
+#define FCH_OHCI_REG46           0x46        // USB PHY Battery Charger - RW (800)
+#define FCH_OHCI_REG48           0x48        // Port Force Reset - RW (800)
+#define FCH_OHCI_REG4C           0x4C        // MSI - RW   (800)
+#define FCH_OHCI_REG51           0x51
+#define FCH_OHCI_REG58           0x58        // Over Current Control - RW
+#define FCH_OHCI_REG5C           0x5C        // Over Current Control - RW
+#define FCH_OHCI_REG60           0x60        // Serial Bus Release Number - RW
+#define FCH_OHCI_REG74           0x74        // Target Timeout Control - RW
+#define FCH_OHCI_REG80           0x80        //
+#define FCH_OHCI_REGD0           0x0D0       // MSI Control - RW
+#define FCH_OHCI_REGD4           0x0D4       // MSI Address - RW
+#define FCH_OHCI_REGD8           0x0D8       // MSI Data - RW
+
+#define FCH_OHCI_BAR_REG00       0x00        // cRevision - R
+#define FCH_OHCI_BAR_REG04       0x04        // cControl
+#define FCH_OHCI_BAR_REG08       0x08        // cCommandStatus
+#define FCH_OHCI_BAR_REG0C       0x0C        // cInterruptStatus  RW
+#define FCH_OHCI_BAR_REG10       0x10        // cInterruptEnable
+#define FCH_OHCI_BAR_REG14       0x14        // cInterruptDisable
+#define FCH_OHCI_BAR_REG18       0x18        // HcCCA
+#define FCH_OHCI_BAR_REG1C       0x1C        // cPeriodCurrentED
+#define FCH_OHCI_BAR_REG20       0x20        // HcControleadED
+#define FCH_OHCI_BAR_REG24       0x24        // cControlCurrentED  RW
+#define FCH_OHCI_BAR_REG28       0x28        // HcBulkeadED
+#define FCH_OHCI_BAR_REG2C       0x2C        // cBulkCurrentED- RW
+#define FCH_OHCI_BAR_REG30       0x30        // HcDoneead
+#define FCH_OHCI_BAR_REG34       0x34        // cFmInterval
+#define FCH_OHCI_BAR_REG38       0x38        // cFmRemaining
+#define FCH_OHCI_BAR_REG3C       0x3C        // cFmNumber
+#define FCH_OHCI_BAR_REG40       0x40        // cPeriodicStart
+#define FCH_OHCI_BAR_REG44       0x44        // HcLSThresold
+#define FCH_OHCI_BAR_REG48       0x48        // HcRDescriptorA
+#define FCH_OHCI_BAR_REG4C       0x4C        // HcRDescriptorB
+#define FCH_OHCI_BAR_REG50       0x50        // HcRStatus
+#define FCH_OHCI_BAR_REG54       0x54        // HcRhPortStatus (800)
+#define FCH_OHCI_BAR_REG58       0x58        // HcRhPortStatus NPD (800)
+
+//
+//  USB EHCI Device 0x7808
+//  Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
+//
+#define FCH_EHCI_REG00           0x00        // DEVICE/VENDOR ID - R
+#define FCH_EHCI_REG04           0x04        // Command - RW
+#define FCH_EHCI_REG06           0x06        // Status - R
+#define FCH_EHCI_REG08           0x08        // Revision ID/Class Code - R
+#define FCH_EHCI_REG0C           0x0C        // Miscellaneous - RW
+#define FCH_EHCI_REG10           0x10        // BAR - RW
+#define FCH_EHCI_REG2C           0x2C        // Subsystem ID/Subsystem Vendor ID - RW
+#define FCH_EHCI_REG34           0x34        // Capability Pointer - R
+#define FCH_EHCI_REG3C           0x3C        // Interrupt Line - RW
+#define FCH_EHCI_REG3D           0x3D        // Interrupt Line - RW
+#define FCH_EHCI_REG40           0x40        // Config Timers - RW
+#define FCH_EHCI_REG4C           0x4C        // MSI - RW
+#define FCH_EHCI_REG60           0x60        // SBRN - R
+#define FCH_EHCI_REG61           0x61        // FLADJ - RW
+#define FCH_EHCI_REGC0           0x0C0       // PME control - RW (800)
+#define FCH_EHCI_REGC4           0x0C4       // PME Data /Status - RW (800)
+#define FCH_EHCI_REGD0           0x0D0       // MSI Control - RW
+#define FCH_EHCI_REGD4           0x0D4       // MSI Address - RW
+#define FCH_EHCI_REGD8           0x0D8       // MSI Data - RW
+#define FCH_EHCI_REGF0           0x0F0       // Function Level Reset Capability - R (800)
+#define FCH_EHCI_REGF4           0x0F4       // Function Level Reset Capability - R (800)
+
+#define FCH_EHCI_BAR_REG00       0x00        // CAPLENGT - R
+#define FCH_EHCI_BAR_REG02       0x002       // CIVERSION- R
+#define FCH_EHCI_BAR_REG04       0x004       // CSPARAMS - R
+#define FCH_EHCI_BAR_REG08       0x008       // CCPARAMS - R
+#define FCH_EHCI_BAR_REG0C       0x00C       // CSP-PORTROUTE - R
+
+#define FCH_EHCI_BAR_REG20       0x020       // USBCMD - RW - 32 bits
+#define FCH_EHCI_BAR_REG24       0x024       // USBSTS - RW - 32 bits
+#define FCH_EHCI_BAR_REG28       0x028       // USBINTR -RW - 32 bits
+#define FCH_EHCI_BAR_REG2C       0x02C       // FRINDEX -RW - 32 bits
+#define FCH_EHCI_BAR_REG30       0x030       // CTRLDSSEGMENT -RW - 32 bits
+#define FCH_EHCI_BAR_REG34       0x034       // PERIODICLISTBASE -RW - 32 bits
+#define FCH_EHCI_BAR_REG38       0x038       // ASYNCLISTADDR -RW - 32 bits
+#define FCH_EHCI_BAR_REG60       0x060       // CONFIGFLAG -RW - 32 bits
+#define FCH_EHCI_BAR_REG64       0x064       // PORTSC (1-N_PORTS) -RW - 32 bits
+#define FCH_EHCI_BAR_REGA4       0x0A4       // Packet Buffer Threshold Values - RW - 32 bits
+#define FCH_EHCI_BAR_REGA8       0x0A8       // USB PHY Status 0 - R
+#define FCH_EHCI_BAR_REGAC       0x0AC       // USB PHY Status 1 - R
+#define FCH_EHCI_BAR_REGB4       0x0B4       // UTMI Control - RW (800)
+#define FCH_EHCI_BAR_REGB8       0x0B8       // Loopback Test
+#define FCH_EHCI_BAR_REGBC       0x0BC       // EHCI MISC Control
+#define FCH_EHCI_BAR_REGC4       0x0C4       // USB Common PHY Control
+#define FCH_EHCI_BAR_REGC8       0x0C8       // EHCI Debug Purpose
+#define FCH_EHCI_BAR_REGCC       0x0CC       // Ehci Spare 1 (800) **
+#define FCH_EHCI_BAR_REG100      0x100       // USB debug port
+
+//
+//  USB EHCI Device 0x7812
+//  Device 16 (0x10) Func 0/1
+//
+#define FCH_XHCI_REG00           0x00        // DEVICE/VENDOR ID - R
+#define FCH_XHCI_REG04           0x04        // Command - RW
+#define FCH_XHCI_REG10           0x10        // Bar0
+#define FCH_XHCI_REG2C           0x2C        // Sub System ID
+#define FCH_XHCI_REG40           0x40        // Index0
+#define FCH_XHCI_REG44           0x44        // Data0
+#define FCH_XHCI_REG48           0x48        // Index1
+#define FCH_XHCI_REG4C           0x4C        // Data0
+#define FCH_XHCI_REG54           0x54        // PME Control/Status
+
+//
+//  FCH CFG device  0x780B
+//  Device 20 (0x14) Func 0
+//
+#define FCH_CFG_REG00            0x000       // VendorID - R
+#define FCH_CFG_REG02            0x002       // DeviceID - R
+#define FCH_CFG_REG04            0x004       // Command- RW
+#define FCH_CFG_REG05            0x005       // Command- RW
+#define FCH_CFG_REG06            0x006       // STATUS- RW
+#define FCH_CFG_REG08            0x008       // Revision ID/Class Code- R
+#define FCH_CFG_REG0A            0x00A       //
+#define FCH_CFG_REG0B            0x00B       //
+#define FCH_CFG_REG0C            0x00C       // Cache Line Size- R
+#define FCH_CFG_REG0D            0x00D       // Latency Timer- R
+#define FCH_CFG_REG0E            0x00E       // Header Type- R
+#define FCH_CFG_REG0F            0x00F       // BIST- R
+#define FCH_CFG_REG10            0x010       // Base Address 0- R
+#define FCH_CFG_REG11            0x011       //;
+#define FCH_CFG_REG12            0x012       //;
+#define FCH_CFG_REG13            0x013       //;
+#define FCH_CFG_REG14            0x014       // Base Address 1- R
+#define FCH_CFG_REG18            0x018       // Base Address 2- R
+#define FCH_CFG_REG1C            0x01C       // Base Address 3- R
+#define FCH_CFG_REG20            0x020       // Base Address 4- R
+#define FCH_CFG_REG24            0x024       // Base Address 5- R
+#define FCH_CFG_REG28            0x028       // Cardbus CIS Pointer- R
+#define FCH_CFG_REG2C            0x02C       // Subsystem Vendor ID- W
+#define FCH_CFG_REG2E            0x02E       // Subsystem ID- W
+#define FCH_CFG_REG30            0x030       // Expansion ROM Base Address - R
+#define FCH_CFG_REG34            0x034       // Capability Pointer - R  (800) default changed as 0x00
+#define FCH_CFG_REG3C            0x03C       // Interrupt Line - R
+#define FCH_CFG_REG3D            0x03D       // Interrupt Pin - R
+#define FCH_CFG_REG3E            0x03E       // Min_Gnt - R
+#define FCH_CFG_REG3F            0x03F       // Max_Lat - R
+#define FCH_CFG_REG90            0x090       // Smbus Base Address - R
+#define FCH_CFG_REG9C            0x09C       // SBResourceMMIO_BASE
+
+//
+//  FCH SATA IDE device
+//  Device 20 (0x14) Func 1
+//
+
+#define FCH_IDE_REG00            0x00        // Vendor ID
+#define FCH_IDE_REG02            0x02        // Device ID
+#define FCH_IDE_REG04            0x04        // Command
+#define FCH_IDE_REG06            0x06        // Status
+#define FCH_IDE_REG08            0x08        // Revision ID/Class Code
+#define FCH_IDE_REG09            0x09        // Class Code
+#define FCH_IDE_REG2C            0x2C        // Subsystem ID and Subsystem Vendor ID
+#define FCH_IDE_REG40            0x40        // Configuration - RW - 32 bits
+#define FCH_IDE_REG34            0x34
+//
+//  Device 20 (0x14) Func 2
+//
+
+#define FCH_AZ_REG00             0x00        // Vendor ID - R
+#define FCH_AZ_REG02             0x02        // Device ID - R/W
+#define FCH_AZ_REG04             0x04        // PCI Command
+#define FCH_AZ_REG06             0x06        // PCI Status - R/W
+#define FCH_AZ_REG08             0x08        // Revision ID
+#define FCH_AZ_REG09             0x09        // Programming Interface
+#define FCH_AZ_REG0A             0x0A        // Sub Class Code
+#define FCH_AZ_REG0B             0x0B        // Base Class Code
+#define FCH_AZ_REG0C             0x0C        // Cache Line Size - R/W
+#define FCH_AZ_REG0D             0x0D        // Latency Timer
+#define FCH_AZ_REG0E             0x0E        // Header Type
+#define FCH_AZ_REG0F             0x0F        // BIST
+#define FCH_AZ_REG10             0x10        // Lower Base Address Register
+#define FCH_AZ_REG14             0x14        // Upper Base Address Register
+#define FCH_AZ_REG2C             0x2C        // Subsystem Vendor ID
+#define FCH_AZ_REG2D             0x2D        // Subsystem ID
+#define FCH_AZ_REG34             0x34        // Capabilities Pointer
+#define FCH_AZ_REG3C             0x3C        // Interrupt Line
+#define FCH_AZ_REG3D             0x3D        // Interrupt Pin
+#define FCH_AZ_REG3E             0x3E        // Minimum Grant
+#define FCH_AZ_REG3F             0x3F        // Maximum Latency
+#define FCH_AZ_REG40             0x40        // Misc Control 1
+#define FCH_AZ_REG42             0x42        // Misc Control 2 Register
+#define FCH_AZ_REG43             0x43        // Misc Control 3 Register
+#define FCH_AZ_REG44             0x44        // Interrupt Pin Control Register
+#define FCH_AZ_REG46             0x46        // Debug Control Register
+#define FCH_AZ_REG4C             0x4C
+#define FCH_AZ_REG50             0x50        // Power Management Capability ID
+#define FCH_AZ_REG52             0x52        // Power Management Capabilities
+#define FCH_AZ_REG54             0x54        // Power Management Control/Status
+#define FCH_AZ_REG60             0x60        // MSI Capability ID
+#define FCH_AZ_REG62             0x62        // MSI Message Control
+#define FCH_AZ_REG64             0x64        // MSI Message Lower Address
+#define FCH_AZ_REG68             0x68        // MSI Message Upper Address
+#define FCH_AZ_REG6C             0x6C        // MSI Message Data
+
+#define FCH_AZ_BAR_REG00         0x00        // Global Capabilities - R
+#define FCH_AZ_BAR_REG02         0x02        // Minor Version - R
+#define FCH_AZ_BAR_REG03         0x03        // Major Version - R
+#define FCH_AZ_BAR_REG04         0x04        // Output Payload Capability - R
+#define FCH_AZ_BAR_REG06         0x06        // Input Payload Capability - R
+#define FCH_AZ_BAR_REG08         0x08        // Global Control - R/W
+#define FCH_AZ_BAR_REG0C         0x0C        // Wake Enable - R/W
+#define FCH_AZ_BAR_REG0E         0x0E        // State Change Status - R/W
+#define FCH_AZ_BAR_REG10         0x10        // Global Status - R/W
+#define FCH_AZ_BAR_REG18         0x18        // Output Stream Payload Capability - R
+#define FCH_AZ_BAR_REG1A         0x1A        // Input Stream Payload Capability - R
+#define FCH_AZ_BAR_REG20         0x20        // Interrupt Control - R/W
+#define FCH_AZ_BAR_REG24         0x24        // Interrupt Status - R/W
+#define FCH_AZ_BAR_REG30         0x30        // Wall Clock Counter - R
+#define FCH_AZ_BAR_REG38         0x38        // Stream Synchronization - R/W
+#define FCH_AZ_BAR_REG40         0x40        // CORB Lower Base Address - R/W
+#define FCH_AZ_BAR_REG44         0x44        // CORB Upper Base Address - RW
+#define FCH_AZ_BAR_REG48         0x48        // CORB Write Pointer - R/W
+#define FCH_AZ_BAR_REG4A         0x4A        // CORB Read Pointer - R/W
+#define FCH_AZ_BAR_REG4C         0x4C        // CORB Control - R/W
+#define FCH_AZ_BAR_REG4D         0x4D        // CORB Status - R/W
+#define FCH_AZ_BAR_REG4E         0x4E        // CORB Size - R/W
+#define FCH_AZ_BAR_REG50         0x50        // RIRB Lower Base Address - RW
+#define FCH_AZ_BAR_REG54         0x54        // RIRB Upper Address - RW
+#define FCH_AZ_BAR_REG58         0x58        // RIRB Write Pointer - RW
+#define FCH_AZ_BAR_REG5A         0x5A        // RIRB Response Interrupt Count - R/W
+#define FCH_AZ_BAR_REG5C         0x5C        // RIRB Control - R/W
+#define FCH_AZ_BAR_REG5D         0x5D        // RIRB Status - R/W
+#define FCH_AZ_BAR_REG5E         0x5E        // RIRB Size - R/W
+#define FCH_AZ_BAR_REG60         0x60        // Immediate Command Output Interface - R/W
+#define FCH_AZ_BAR_REG64         0x64        // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG68         0x68        // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG70         0x70        // DMA Position Lower Base Address - R/W
+#define FCH_AZ_BAR_REG74         0x74        // DMA Position Upper Base Address - R/W
+#define FCH_AZ_BAR_REG2030       0x2030      // Wall Clock Counter Alias - R
+
+//
+//  FCH LPC Device  0x780E
+//  Device 20 (0x14) Func 3
+//
+#define FCH_LPC_REG00            0x00        // VID- R
+#define FCH_LPC_REG02            0x02        // DID- R
+#define FCH_LPC_REG04            0x04        // CMD- RW
+#define FCH_LPC_REG06            0x06        // STATUS- RW
+#define FCH_LPC_REG08            0x08        // Revision  ID/Class Code - R
+#define FCH_LPC_REG0C            0x0C        // Cache Line Size - R
+#define FCH_LPC_REG0D            0x0D        // Latency Timer - R
+#define FCH_LPC_REG0E            0x0E        // Header Type - R
+#define FCH_LPC_REG0F            0x0F        // BIST- R
+#define FCH_LPC_REG10            0x10        // Base Address Reg 0- RW*
+#define FCH_LPC_REG2C            0x2C        // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define FCH_LPC_REG34            0x34        // Capabilities Pointer - Ro
+#define FCH_LPC_REG40            0x40        // PCI Control - RW
+#define FCH_LPC_REG44            0x44        // IO Port Decode Enable Register 1- RW
+#define FCH_LPC_REG45            0x45        // IO Port Decode Enable Register 2- RW
+#define FCH_LPC_REG46            0x46        // IO Port Decode Enable Register 3- RW
+#define FCH_LPC_REG47            0x47        // IO Port Decode Enable Register 4- RW
+#define FCH_LPC_REG48            0x48        // IO/Mem Port Decode Enable Register 5- RW
+#define FCH_LPC_REG49            0x49        // LPC Sync Timeout Count - RW
+#define FCH_LPC_REG4A            0x4A        // IO/Mem Port Decode Enable Register 6- RW
+#define FCH_LPC_REG4C            0x4C        // Memory Range Register - RW
+#define FCH_LPC_REG50            0x50        // Rom Protect 0 - RW
+#define FCH_LPC_REG54            0x54        // Rom Protect 1 - RW
+#define FCH_LPC_REG58            0x58        // Rom Protect 2 - RW
+#define FCH_LPC_REG5C            0x5C        // Rom Protect 3 - RW
+#define FCH_LPC_REG60            0x60        // PCI Memory Start Address of LPC Target Cycles -
+#define FCH_LPC_REG62            0x62        // PCI Memory End Address of LPC Target Cycles -
+#define FCH_LPC_REG64            0x64        // PCI IO base Address of Wide Generic Port - RW
+#define FCH_LPC_REG65            0x65
+#define FCH_LPC_REG66            0x66
+#define FCH_LPC_REG67            0x67
+#define FCH_LPC_REG68            0x68        // LPC ROM Address Range 1 (Start Address) - RW
+#define FCH_LPC_REG69            0x69
+#define FCH_LPC_REG6A            0x6A        // LPC ROM Address Range 1 (End Address) - RW
+#define FCH_LPC_REG6B            0x6B
+#define FCH_LPC_REG6C            0x6C        // LPC ROM Address Range 2 (Start Address)- RW
+#define FCH_LPC_REG6D            0x6D
+#define FCH_LPC_REG6E            0x6E        // LPC ROM Address Range 2 (End Address) - RW
+#define FCH_LPC_REG6F            0x6F
+#define FCH_LPC_REG71            0x71
+#define FCH_LPC_REG72            0x72
+#define FCH_LPC_REG73            0x73
+#define FCH_LPC_REG74            0x74        // Alternative Wide IO Range Enable- W/R
+#define FCH_LPC_REG7C            0x7C        // TPM (trusted plant form module) reg- W/R
+#define FCH_LPC_REG9C            0x9C
+#define FCH_LPC_REG80            0x80        // MSI Capability Register- R
+#define FCH_LPC_REGA0            0x0A0       // SPI base address
+#define FCH_LPC_REGA1            0x0A1       // SPI base address
+#define FCH_LPC_REGA2            0x0A2       // SPI base address
+#define FCH_LPC_REGA3            0x0A3       // SPI base address
+#define FCH_LPC_REGA4            0x0A4
+#define FCH_LPC_REGBA            0x0BA       // EcControl
+#define FCH_LPC_REGBB            0x0BB       // HostControl
+#define FCH_LPC_REGCC            0x0CC       // AutoRomCfg
+#define FCH_LPC_REGD0            0x0D0
+
+//
+//  FCH PCIB  0x780F
+//  Device 20 (0x14) Func 4
+//
+#define FCH_PCIB_REG04            0x04       // Command
+#define FCH_PCIB_REG0D            0x0D       // Primary Master Latency Timer
+#define FCH_PCIB_REG1B            0x1B       // Secondary Latency Timer
+#define FCH_PCIB_REG1C            0x1C       // IO Base
+#define FCH_PCIB_REG1D            0x1D       // IO Limit
+#define FCH_PCIB_REG40            0x40       // CPCTRL
+#define FCH_PCIB_REG42            0x42       // CLKCTRL
+#define FCH_PCIB_REG48            0x48       //
+#define FCH_PCIB_REG4A            0x4A       // PCICLK Enable Bits
+#define FCH_PCIB_REG4B            0x4B       // Misc Control
+#define FCH_PCIB_REG4C            0x4C       // AutoClockRun Control
+#define FCH_PCIB_REG50            0x50       // Dual Address Cycle Enable and PCIB_CLK_Stop Override
+#define FCH_PCIB_REG65            0x65       // Misc Control
+#define FCH_PCIB_REG66            0x66       // Misc Control
+//
+//  FCH GEC 0x14E4 0x1699
+//  Device 20 (0x14) Func 6
+//
+#define FCH_GEC_REG10             0x10       // GEC BAR
+//
+//  FCH MMIO Base (SMI)
+//    offset : 0x200
+//
+#define FCH_SMI_REG00            0x00         // EventStatus
+#define FCH_SMI_REG04            0x04         // EventEnable
+#define FCH_SMI_REG08            0x08         // SciTrig
+#define FCH_SMI_REG0C            0x0C         // SciLevl
+#define FCH_SMI_REG10            0x10         // SmiSciStatus
+#define FCH_SMI_REG14            0x14         // SmiSciEn
+#define FCH_SMI_REG18            0x18         // ForceSciEn
+#define FCH_SMI_REG1C            0x1C         // SciRwData
+#define FCH_SMI_REG3C            0x3C         // DataErrorStatus
+#define FCH_SMI_REG20            0x20         // SciS0En
+
+// Empty from 0x72-0x7F
+//#Define FCH_SMI_REG7C            0x7F         // SciMap63  ***
+
+#define FCH_SMI_REG80            0x80         //  SmiStatus0
+#define FCH_SMI_REG84            0x84         // SmiStatus1
+#define FCH_SMI_REG88            0x88         // SmiStatus2
+#define FCH_SMI_REG8C            0x8C         // SmiStatus3
+#define FCH_SMI_REG90            0x90         // SmiStatus4
+#define FCH_SMI_REG94            0x94         // SmiPointer
+#define FCH_SMI_REG96            0x96         // SmiTimer
+#define FCH_SMI_REG98            0x98         // SmiTrig
+#define FCH_SMI_REG9C            0x9C         // SmiTrig
+#define FCH_SMI_REGA0            0xA0
+#define FCH_SMI_REGA1            0xA1
+#define FCH_SMI_REGA2            0xA2
+#define FCH_SMI_REGA3            0xA3
+#define FCH_SMI_REGA4            0xA4
+#define FCH_SMI_REGA5            0xA5
+#define FCH_SMI_REGA6            0xA6
+#define FCH_SMI_REGA7            0xA7
+#define FCH_SMI_REGA8            0xA8
+#define FCH_SMI_REGA9            0xA9
+#define FCH_SMI_REGAA            0xAA
+#define FCH_SMI_REGAB            0xAB
+#define FCH_SMI_REGAC            0xAC
+#define FCH_SMI_REGAD            0xAD
+#define FCH_SMI_REGAE            0xAE
+#define FCH_SMI_REGAF            0xAF
+#define FCH_SMI_REGB0            0xB0
+#define FCH_SMI_REGB1            0xB1
+#define FCH_SMI_REGB2            0xB2
+#define FCH_SMI_REGB3            0xB3
+#define FCH_SMI_REGB4            0xB4
+#define FCH_SMI_REGB5            0xB5
+#define FCH_SMI_REGB6            0xB6
+#define FCH_SMI_REGB7            0xB7
+#define FCH_SMI_REGB8            0xB8
+#define FCH_SMI_REGB9            0xB9
+#define FCH_SMI_REGBA            0xBA
+#define FCH_SMI_REGBB            0xBB
+#define FCH_SMI_REGBC            0xBC
+#define FCH_SMI_REGBD            0xBD
+#define FCH_SMI_REGBE            0xBE
+#define FCH_SMI_REGBF            0xBF
+#define FCH_SMI_REGC0            0xC0
+#define FCH_SMI_REGC1            0xC1
+#define FCH_SMI_REGC2            0xC2
+#define FCH_SMI_REGC3            0xC3
+#define FCH_SMI_REGC4            0xC4
+#define FCH_SMI_REGC5            0xC5
+#define FCH_SMI_REGC6            0xC6
+#define FCH_SMI_REGC7            0xC7
+#define FCH_SMI_REGC8            0xC8
+#define FCH_SMI_REGCA            0xCA         //  IoTrapping1
+#define FCH_SMI_REGCC            0xCC         //  IoTrapping2
+#define FCH_SMI_REGCE            0xCE         //  IoTrapping3
+#define FCH_SMI_REGD0            0xD0         //  MemTrapping0
+#define FCH_SMI_REGD4            0xD4         //  MemRdOvrData0
+#define FCH_SMI_REGD8            0xD8         //  MemTrapping1
+#define FCH_SMI_REGDC            0xDC         //  MemRdOvrData1
+#define FCH_SMI_REGE0            0xE0         //  MemTrapping2
+#define FCH_SMI_REGE4            0xE4         //  MemRdOvrData2
+#define FCH_SMI_REGE8            0xE8         //  MemTrapping3
+#define FCH_SMI_REGEC            0xEC         //  MemRdOvrData3
+#define FCH_SMI_REGF0            0xF0         //  CfgTrapping0
+#define FCH_SMI_REGF4            0xF4         //  CfgTrapping1
+#define FCH_SMI_REGF8            0xF8         //  CfgTrapping2
+#define FCH_SMI_REGFC            0xFC         //  CfgTrapping3
+
+//
+//  FCH MMIO Base (PMIO)
+//    offset : 0x300
+//
+#define FCH_PMIOA_REG00          0x00        // ISA Decode
+#define FCH_PMIOA_REG04          0x04        // ISA Control
+#define FCH_PMIOA_REG08          0x08        // PCI Control
+#define FCH_PMIOA_REG0C          0x0C        // StpClkSmaf
+#define FCH_PMIOA_REG10          0x10        // RetryDetect
+#define FCH_PMIOA_REG14          0x14        // StuckDetect
+#define FCH_PMIOA_REG20          0x20        // BiosRamEn
+#define FCH_PMIOA_REG24          0x24        //  AcpiMmioEn
+#define FCH_PMIOA_REG2C          0x2C         // Smbus0En
+#define FCH_PMIOA_REG2E          0x2E         // Smbus0Sel
+#define FCH_PMIOA_REG34          0x34         // IoApicEn
+#define FCH_PMIOA_REG3C          0x3C         // SmartVoltEn
+#define FCH_PMIOA_REG40          0x40         // SmartVolt2En
+#define FCH_PMIOA_REG44          0x44         // BootTimerEn
+#define FCH_PMIOA_REG48          0x48         // WatchDogTimerEn
+#define FCH_PMIOA_REG4C          0x4C         // WatchDogTimerConfig
+#define FCH_PMIOA_REG50          0x50         // HPETEn
+#define FCH_PMIOA_REG54          0x54         // SerialIrqConfig
+#define FCH_PMIOA_REG56          0x56         // RtcControl
+#define FCH_PMIOA_REG58          0x58         // VRT_T1
+#define FCH_PMIOA_REG59          0x59         // VRT_T2
+#define FCH_PMIOA_REG5A          0x5A         // IntruderControl
+#define FCH_PMIOA_REG5B          0x5B         // RtcShadow
+#define FCH_PMIOA_REG5C          0x5C
+#define FCH_PMIOA_REG5E          0x5E         // RtcExtIndex
+#define FCH_PMIOA_REG5F          0x5F         // RtcExtData
+#define FCH_PMIOA_REG60          0x60         // AcpiPm1EvtBlk
+#define FCH_PMIOA_REG62          0x62         // AcpiPm1CntBlk
+#define FCH_PMIOA_REG64          0x64         // AcpiPmTmrBlk
+#define FCH_PMIOA_REG66          0x66         // P_CNTBlk
+#define FCH_PMIOA_REG68          0x68         // AcpiGpe0Blk
+#define FCH_PMIOA_REG6A          0x6A         // AcpiSmiCmd
+#define FCH_PMIOA_REG6C          0x6C         // AcpiPm2CntBlk
+#define FCH_PMIOA_REG6E          0x6E         // AcpiPmaCntBlk
+#define FCH_PMIOA_REG74          0x74         // AcpiConfig
+#define FCH_PMIOA_REG78          0x78         // WakeIoAddr
+#define FCH_PMIOA_REG7A          0x7A         // HaltCountEn
+#define FCH_PMIOA_REG7C          0x7C         // C1eWrPortAdr
+#define FCH_PMIOA_REG7E          0x7E         // CStateEn
+#define FCH_PMIOA_REG7F          0x7F         // CStateEn
+#define FCH_PMIOA_REG80          0x80         // BreakEvent
+#define FCH_PMIOA_REG88          0x88         // CStateControl
+#define FCH_PMIOA_REG89          0x89         //
+#define FCH_PMIOA_REG8C          0x8C         // StpClkHoldTime
+#define FCH_PMIOA_REG8E          0x8E         // PopUpEndTime
+#define FCH_PMIOA_REG90          0x90         // C4Control
+#define FCH_PMIOA_REG94          0x94         // CStateTiming0
+#define FCH_PMIOA_REG96          0x96         //
+#define FCH_PMIOA_REG97          0x97         //
+#define FCH_PMIOA_REG98          0x98         // CStateTiming1
+#define FCH_PMIOA_REG99          0x99         //
+#define FCH_PMIOA_REG9B          0x9B         //
+#define FCH_PMIOA_REG9C          0x9C         // C2Count
+#define FCH_PMIOA_REG9D          0x9D         // C3Count
+#define FCH_PMIOA_REGA0          0xA0         // MessageCState
+#define FCH_PMIOA_REGA4          0xA4         //
+#define FCH_PMIOA_REGA8          0xA8         // TrafficMonitorIdleTime
+#define FCH_PMIOA_REGAA          0xAA         // TrafficMonitorIntTime
+#define FCH_PMIOA_REGAC          0xAC         // TrafficMonitorTrafficCount
+#define FCH_PMIOA_REGAE          0xAE         // TrafficMonitorIntrCount
+#define FCH_PMIOA_REGB0          0xB0         // TrafficMonitorTimeTick
+#define FCH_PMIOA_REGB4          0xB4         // FidVidControl
+#define FCH_PMIOA_REGB7          0xB7         // Tpreset1b
+#define FCH_PMIOA_REGB8          0xB8         // TPRESET2
+#define FCH_PMIOA_REGBA          0xBA         // S_StateControl
+#define FCH_PMIOA_REGBB          0xBB         //
+#define FCH_PMIOA_REGBC          0xBC         // ThrottlingControl
+#define FCH_PMIOA_REGBE          0xBE         // ResetControl
+#define FCH_PMIOA_REGBF          0xBF         // ResetControl
+#define FCH_PMIOA_REGC0          0xC0         // S5Status
+#define FCH_PMIOA_REGC2          0xC2         // ResetStatus
+#define FCH_PMIOA_REGC4          0xC4         // ResetCommand
+#define FCH_PMIOA_REGC5          0xC5         // CF9Shadow
+#define FCH_PMIOA_REGC6          0xC6         // HTControl
+#define FCH_PMIOA_REGC8          0xC8         // Misc
+#define FCH_PMIOA_REGCC          0xCC         // IoDrvSth
+#define FCH_PMIOA_REGD0          0xD0         // CLKRunEn
+#define FCH_PMIOA_REGD2          0xD2         // PmioDebug
+#define FCH_PMIOA_REGD6          0xD6         // IMCGating
+#define FCH_PMIOA_REGE0          0xE0         // ABRegBar
+#define FCH_PMIOA_REGE7          0xE7
+#define FCH_PMIOA_REGEA          0xEA         // PcibConfig
+#define FCH_PMIOA_REGEC          0xEC         // LpcGating
+#define FCH_PMIOA_REGED          0xED         // UsbGating
+#define FCH_PMIOA_REGEE          0xEE         // UsbCntrl
+#define FCH_PMIOA_REGEF          0xEF         // UsbEnable
+#define FCH_PMIOA_REGF0          0xF0         // UsbControl
+#define FCH_PMIOA_REGF3          0xF3         // UsbDebug
+#define FCH_PMIOA_REGF6          0xF6         // GecEn
+#define FCH_PMIOA_REGF8          0xF8         // GecConfig
+#define FCH_PMIOA_REGFC          0xFC         // TraceMemoryEn
+
+//
+//  FCH MMIO Base (PMIO2)
+//    offset : 0x400
+//
+
+
+#define FCH_PMIO2_REG63          0x63        // SampleFreqDiv
+#define FCH_PMIO2_REG69          0x69        // Fan0 Speed
+#define FCH_PMIO2_REG95          0x95        // Temperature
+#define FCH_PMIO2_REGB8          0xB8        // Voltage
+#define FCH_PMIO2_REGEA          0xEA        // Hwm_Calibration
+
+#define FCH_PMIO2_REG92          0x92        //
+
+#define FCH_PMIO2_REG          0xFC         // TraceMemoryEn
+
+
+//
+//  FCH MMIO Base (GPIO/IoMux)
+//    offset : 0x100/0xD00
+//
+/*
+GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
+*/
+#define FCH_GPIO_REG60           0x3C
+#define FCH_GPIO_REG61           0x3D
+#define FCH_GPIO_REG62           0x3E
+#define FCH_GPIO_REG63           0x3F
+#define FCH_GPIO_REG64           0x40
+#define FCH_GPIO_REG65           0x41
+#define FCH_GPIO_REG66           0x42
+#define FCH_GPIO_REG67           0x43
+#define FCH_GPIO_REG68           0x44
+#define FCH_GPIO_REG69           0x45
+#define FCH_GPIO_REG70           0x46
+#define FCH_GPIO_REG71           0x47
+#define FCH_GPIO_REG72           0x48
+#define FCH_GPIO_REG73           0x49
+#define FCH_GPIO_REG74           0x4A
+#define FCH_GPIO_REG75           0x4B
+#define FCH_GPIO_REG76           0x4C
+#define FCH_GPIO_REG77           0x4D
+#define FCH_GPIO_REG78           0x4E
+#define FCH_GPIO_REG79           0x4F
+#define FCH_GPIO_REG80           0x50
+
+#define FCH_GEVENT_REG00         0x60
+#define FCH_GEVENT_REG01         0x61
+#define FCH_GEVENT_REG02         0x62
+#define FCH_GEVENT_REG03         0x63
+#define FCH_GEVENT_REG04         0x64
+#define FCH_GEVENT_REG05         0x65
+#define FCH_GEVENT_REG06         0x66
+#define FCH_GEVENT_REG07         0x67
+#define FCH_GEVENT_REG08         0x68
+#define FCH_GEVENT_REG09         0x69
+#define FCH_GEVENT_REG10         0x6A
+#define FCH_GEVENT_REG11         0x6B
+#define FCH_GEVENT_REG12         0x6C
+#define FCH_GEVENT_REG13         0x6D
+#define FCH_GEVENT_REG14         0x6E
+#define FCH_GEVENT_REG15         0x6F
+#define FCH_GEVENT_REG16         0x70
+#define FCH_GEVENT_REG17         0x71
+#define FCH_GEVENT_REG18         0x72
+#define FCH_GEVENT_REG19         0x73
+#define FCH_GEVENT_REG20         0x74
+#define FCH_GEVENT_REG21         0x75
+#define FCH_GEVENT_REG22         0x76
+#define FCH_GEVENT_REG23         0x77
+// S5-DOMAIN GPIO
+#define FCH_GPIO_REG166          0xA6
+#define FCH_GPIO_REG167          0xA7
+#define FCH_GPIO_REG168          0xA8
+#define FCH_GPIO_REG169          0xA9
+#define FCH_GPIO_REG170          0xAA
+
+//
+//  FCH MMIO Base (SMBUS)
+//    offset : 0xA00
+//
+#define FCH_SMBUS_REG12           0x12        //   I2CbusConfig
+
+//
+//  FCH MMIO Base (MISC)
+//    offset : 0xE00
+//
+#define FCH_MISC_REG00           0x00        //  ClkCntrl0
+/*
+FCH_MISC_REG00                   EQU     000h
+  ClkCntrl0                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG04           0x04        //  ClkCntrl1
+/*
+FCH_MISC_REG04                   EQU     004h
+  ClkCntrl1                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG08           0x08        //  ClkCntrl2
+/*
+FCH_MISC_REG08                   EQU     008h
+  ClkCntrl2                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG0C           0x0C        //  ClkCntrl3
+/*
+FCH_MISC_REG0C                   EQU     00Ch
+  ClkCntrl3                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG10           0x10        //  ClkCntrl4
+/*
+FCH_MISC_REG10                   EQU     010h
+  ClkCntrl4                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG14           0x14        //   ClkCntrl5
+/*
+FCH_MISC_REG14                   EQU     014h
+  ClkCntrl5                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG18           0x18        //   ClkCntrl6
+/*
+FCH_MISC_REG18                   EQU     018h
+  ClkCntrl6                   EQU     0FFFFFFFFh
+*/
+#define FCH_MISC_REG1C           0x1C
+#define FCH_MISC_REG30           0x30         // OscFreqCounter
+/*
+FCH_MISC_REG30                   EQU     030h
+  OscCounter                  EQU     0FFFFFFFFh                  ; The 32bit register shows the number of OSC clock per second.
+*/
+#define FCH_MISC_REG34           0x34         //  HpetClkPeriod
+/*
+FCH_MISC_REG34                   EQU     034h
+  HpetClkPeriod               EQU     0FFFFFFFFh                  ; default - 0x429B17Eh (14.31818M).
+*/
+#define FCH_MISC_REG28           0x28         //  ClkDrvSth2
+#define FCH_MISC_REG40           0x40         //  MiscCntrl      for clock only
+#define FCH_MISC_REG41           0x41         //  MiscCntr2
+#define FCH_MISC_REG42           0x42         //  MiscCntr3
+#define FCH_MISC_REG44           0x44         //  ValueOnPort80
+#define FCH_MISC_REG50           0x50         //
+/*
+FCH_MISC_REG40                   EQU     040h
+*/
+
+#define FCH_MISC_REG80           0x80        /**< FCH_MISC_REG80
+                                   *   @par
+                                   *   StrapStatus [15.0] - FCH chip Strap Status
+                                   *    @li <b>0001</b> - Not USED FWH
+                                   *    @li <b>0002</b> - Not USED LPC ROM
+                                   *    @li <b>0004</b> - EC enabled
+                                   *    @li <b>0008</b> - Reserved
+                                   *    @li <b>0010</b> - Internal Clock mode
+                                   */
+#define FCH_MISC_REGB6           0xB6         //
+
+#define  ChipSysNotUseFWHRom    0x0001                            // EcPwm3 pad
+#define  ChipSysNotUseLpcRom    0x0002                            // Inverted version from EcPwm2 pad (default - 1)
+                                                                  // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
+#define  ChipSysEcEnable        0x0004                            // Enable Embedded Controller (EC)
+#define  ChipSysBootFailTmrEn   0x0008                            // Enable Watchdog function
+#define  ChipSysIntClkGen       0x0010                            // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
+
+#define FCH_MISC_REG84           0x84         //  StrapOverride
+/*
+FCH_MISC_REG84                   EQU     084h
+  Override FWHDisableStrap    EQU     BIT0                        ; Override FWHDiableStrap value from external pin.
+  Override UseLpcRomStrap     EQU     BIT1                        ; Override UseLpcRomStrap value from external pin.
+  Override EcEnableStrap      EQU     BIT2                        ; Override EcEnableStrap value from external pin.
+  Override BootFailTmrEnStrap EQU     BIT3                        ; Override BootFailTmrEnStrap value from external pin.
+  Override DefaultModeStrap   EQU     BIT5                        ; Override DefaultModeStrap value from external pin.
+  Override I2CRomStrap        EQU     BIT7                        ; Override I2CRomStrap value from external pin.
+  Override ILAAutorunEnBStrap EQU     BIT8                        ; Override ILAAutorunEnBStrap value from external pin.
+  Override FcPllBypStrap      EQU     BIT9                        ; Override FcPllBypStrap value from external pin.
+  Override PciPllBypStrap     EQU     BIT10                       ; Override PciPllBypStrap value from external pin.
+  Override ShortResetStrap    EQU     BIT11                       ; Override ShortResetStrap value from external pin.
+  Override FastBif2ClkStrap   EQU     BIT13                       ; Override FastBif2ClkStrap value from external pin
+  PciRomBootStrap             EQU     BIT15                       ; Override PCI Rom Boot Strap value from external pin
+  BlinkSlowModestrap          EQU     BIT16                       ; Override Blink Slow mode (100Mhz) from external pin
+  ClkGenStrap                 EQU     BIT17                       ; Override CLKGEN from external pin.
+  BIF_GEN2_COMPL_Strap        EQU     BIT18                       ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
+  StrapOverrideEn             EQU     BIT31                       ; Enable override strapping feature.
+*/
+#define FCH_MISC_REGC0           0xC0        //  CPU_Pstate0
+/*
+FCH_MISC_REGC0                   EQU     0C0h
+  Core0_PState                EQU     BIT0+BIT1+BIT2              ; 000: P0  001: P1  010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+  Core1_PState                EQU     BIT4+BIT5+BIT6
+  Core2_PState                EQU     BIT8+BIT9+BIT10
+  Core3_PState                EQU     BIT12+BIT13+BIT14
+  Core4_PState                EQU     BIT16++BIT17+BIT18
+  Core5_PState                EQU     BIT20+BIT21+BIT22
+  Core6_PState                EQU     BIT24+BIT25+BIT26
+  Core7_PState                EQU     BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGC4           0xC4         //  CPU_Pstate1
+/*
+FCH_MISC_REGC4                   EQU     0C4h
+  Core8_PState                EQU     BIT0+BIT1+BIT2              ; 000: P0  001: P1  010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+  Core9_PState                EQU     BIT4+BIT5+BIT6
+  Core10_PState               EQU     BIT8+BIT9+BIT10
+  Core11_PState               EQU     BIT12+BIT13+BIT14
+  Core12_PState               EQU     BIT16++BIT17+BIT18
+  Core13_PState               EQU     BIT20+BIT21+BIT22
+  Core14_PState               EQU     BIT24+BIT25+BIT26
+  Core15_PState               EQU     BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD0           0xD0         //  CPU_Cstate0
+/*
+FCH_MISC_REGD0                   EQU     0D0h
+  Core0_CState                EQU     BIT0+BIT1+BIT2              ; 000: C0  001: C1  010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+  Core1_CState                EQU     BIT4+BIT5+BIT6
+  Core2_CState                EQU     BIT8+BIT9+BIT10
+  Core3_CState                EQU     BIT12+BIT13+BIT14
+  Core4_CState                EQU     BIT16++BIT17+BIT18
+  Core5_CState                EQU     BIT20+BIT21+BIT22
+  Core6_CState                EQU     BIT24+BIT25+BIT26
+  Core7_CState                EQU     BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD4           0xD4         //  CPU_Cstate1
+/*
+FCH_MISC_REGD4                   EQU     0D4h
+  Core8_CState                EQU     BIT0+BIT1+BIT2              ; 000: C0  001: C1  010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+  Core9_CState                EQU     BIT4+BIT5+BIT6
+  Core10_CState               EQU     BIT8+BIT9+BIT10
+  Core11_CState               EQU     BIT12+BIT13+BIT14
+  Core12_CState               EQU     BIT16++BIT17+BIT18
+  Core13_CState               EQU     BIT20+BIT21+BIT22
+  Core14_CState               EQU     BIT24+BIT25+BIT26
+  Core15_CState               EQU     BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGF0           0xF0         //  SataPortSts
+/*
+FCH_MISC_REGF0                   EQU     0F0h
+  Port0Sts                    EQU     BIT0                        ; The selected status of Port 0.
+  Port1Sts                    EQU     BIT1                        ; The selected status of Port 1
+  Port2Sts                    EQU     BIT2                        ; The selected status of Port 2.
+  Port3Sts                    EQU     BIT3                        ; The selected status of Port 3
+  Port4Sts                    EQU     BIT4                        ; The selected status of Port 4.
+  Port5Sts                    EQU     BIT5                        ; The selected status of Port 5
+  SataPortSel                 EQU     BIT24+BIT25                 ; 00  - Select "led" for Port 0 to 5
+                                  ; 01 - Select "delete" for Port 0 to 5
+                                  ; 10 - Select "err" for Port 0 to 5
+                                  ; 11 - Select "led" for Port 0 to 5
+*/
+
+//
+//  FCH MMIO Base (SERIAL_DEBUG_BASE)
+//    offset : 0x1000
+//
+#define FCH_SDB_REG00            0x00        //
+#define FCH_SDB_REG74            0x74
+
+
+
+
+#define FCH_IOMAP_REG70          0x070   // Nmi_Enable
+#define FCH_IOMAP_REG71          0x071   // RtcDataPort
+#define FCH_IOMAP_REG72          0x072   // AlternatRtcAddrPort
+#define FCH_IOMAP_REG73          0x073   // AlternatRtcDataPort
+#define FCH_IOMAP_REGC0          0x0C0   // Dma2_C4Addr
+#define FCH_IOMAP_REGC2          0x0C2   // Dma2_C4Cnt
+#define FCH_IOMAP_REGC4          0x0C4   // Dma2_C5Addr
+#define FCH_IOMAP_REGC6          0x0C6   // Dma2_C5Cnt
+#define FCH_IOMAP_REGC8          0x0C8   // Dma2_C6Addr
+#define FCH_IOMAP_REGCA          0x0CA   // Dma2_C6Cnt
+#define FCH_IOMAP_REGCC          0x0CC   // Dma2_C7Addr
+#define FCH_IOMAP_REGCE          0x0CE   // Dma2_C7Cnt
+#define FCH_IOMAP_REGD0          0x0D0   // Dma_Status
+#define FCH_IOMAP_REGD2          0x0D2   // Dma_WriteRest
+#define FCH_IOMAP_REGD4          0x0D4   // Dma_WriteMask
+#define FCH_IOMAP_REGD6          0x0D6   // Dma_WriteMode
+#define FCH_IOMAP_REGD8          0x0D8   // Dma_Clear
+#define FCH_IOMAP_REGDA          0x0DA   // Dma_Clear
+#define FCH_IOMAP_REGDC          0x0DC   // Dma_ClrMask
+#define FCH_IOMAP_REGDE          0x0DE   // Dma_ClrMask
+#define FCH_IOMAP_REGF0          0x0F0   // NCP_Error
+#define FCH_IOMAP_REG40B         0x040B  // DMA1_Extend
+#define FCH_IOMAP_REG4D0         0x04D0  // IntrEdgeControl
+#define FCH_IOMAP_REG4D6         0x04D6  // DMA2_Extend
+#define FCH_IOMAP_REGC00         0x0C00  // Pci_Intr_Index
+#define FCH_IOMAP_REGC01         0x0C01  // Pci_Intr_Data
+#define FCH_IOMAP_REGC14         0x0C14  // Pci_Error
+#define FCH_IOMAP_REGC50         0x0C50  // CMIndex
+#define FCH_IOMAP_REGC51         0x0C51  // CMData
+#define FCH_IOMAP_REGC52         0x0C52  // GpmPort
+#define FCH_IOMAP_REGC6F         0x0C6F  // Isa_Misc
+#define FCH_IOMAP_REGCD0         0x0CD0  // PMio2_Index
+#define FCH_IOMAP_REGCD1         0x0CD1  // PMio2_Data
+#define FCH_IOMAP_REGCD4         0x0CD4  // BIOSRAM_Index
+#define FCH_IOMAP_REGCD5         0x0CD5  // BIOSRAM_Data
+#define FCH_IOMAP_REGCD6         0x0CD6  // PM_Index
+#define FCH_IOMAP_REGCD7         0x0CD7  // PM_Data
+#define FCH_IOMAP_REGCF9         0x0CF9          // CF9Rst reg
+
+#define FCH_IRQ_INTA             0x00    // INTA#
+#define FCH_IRQ_INTB             0x01    // INTB#
+#define FCH_IRQ_INTC             0x02    // INTC#
+#define FCH_IRQ_INTD             0x03    // INTD#
+#define FCH_IRQ_INTE             0x04    // INTE#
+#define FCH_IRQ_INTF             0x05    // INTF#
+#define FCH_IRQ_INTG             0x06    // INTG#
+#define FCH_IRQ_INTH             0x07    // INTH#
+#define FCH_IRQ_SCI              0x10    // SCI
+#define FCH_IRQ_SMBUS0           0x11    // SMBUS0
+#define FCH_IRQ_ASF              0x12    // ASF
+#define FCH_IRQ_HDAUDIO          0x13    // HD Audio
+#define FCH_IRQ_FC               0x14    // FC
+#define FCH_IRQ_GEC              0x15    // GEC
+#define FCH_IRQ_SD               0x17    // SD
+#define FCH_IRQ_IMCINT0          0x20    // IMC INT0
+#define FCH_IRQ_IMCINT1          0x21    // IMC INT1
+#define FCH_IRQ_IMCINT2          0x22    // IMC INT2
+#define FCH_IRQ_IMCINT3          0x23    // IMC INT3
+#define FCH_IRQ_IMCINT4          0x24    // IMC INT4
+#define FCH_IRQ_IMCINT5          0x25    // IMC INT5
+#define FCH_IRQ_USB18INTA        0x30    // Dev 18 (USB) INTA#
+#define FCH_IRQ_USB18INTB        0x31    // Dev 18 (USB) INTB#
+#define FCH_IRQ_USB19INTA        0x32    // Dev 19 (USB) INTA#
+#define FCH_IRQ_USB19INTB        0x33    // Dev 19 (USB) INTB#
+#define FCH_IRQ_USB22INTA        0x34    // Dev 22 (USB) INTA#
+#define FCH_IRQ_USB22INTB        0x35    // Dev 22 (USB) INTB#
+#define FCH_IRQ_USB20INTC        0x36    // Dev 20 (USB) INTC#
+#define FCH_IRQ_IDE              0x40    // IDE pci interrupt
+#define FCH_IRQ_SATA             0x41    // SATA pci interrupt
+#define FCH_IRQ_GPPINT0          0x50    // Gpp Int0
+#define FCH_IRQ_GPPINT1          0x51    // Gpp Int1
+#define FCH_IRQ_GPPINT2          0x52    // Gpp Int2
+#define FCH_IRQ_GPPINT3          0x53    // Gpp Int3
+#define FCH_IRQ_IOAPIC           0x80    // Select IRQ routing to IoApic mode
+#define FCH_IRQ_PIC              0x00    // Select IRQ routing to PIC mode
+
+#define FCH_SPI_MMIO_REG00       0x00        //SPI_
+#define FCH_SPI_MMIO_REG0C       0x0C        //SPI_Cntrl1 Register
+#define FCH_SPI_MMIO_REG1C       0x1C        //
+
+#define FCH_SPI_MODE_FAST        0x7        //
+#define FCH_SPI_MODE_NORMAL      0x6        //
+#define FCH_SPI_MODE_QUAL_144    0x5        //
+#define FCH_SPI_MODE_QUAL_122    0x4        //
+#define FCH_SPI_MODE_QUAL_114    0x3        //
+#define FCH_SPI_MODE_QUAL_112    0x2        //
+
+#define AMD_NB_REG78            0x78
+#define AMD_NB_SCRATCH          AMD_NB_REG78
+#define MailBoxPort             0x3E
+
+#define MAX_LT_POLLINGS         0x4000
+#define SMI_TIMER_ENABLE        BIT15
+
+
+#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x))
+#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x))
+#define ACPIMMIO8(x)  (*(volatile UINT8*)(UINTN)(x))
+
+#define XHCI_ACPI_MMIO_AMD_REG00     0x00
+#define U3PLL_LOCK                   BIT7
+#define U3PLL_RESET                  BIT8
+#define U3PHY_RESET                  BIT9
+#define U3CORE_RESET                 BIT10
+#define XHC0_FUNC_RESET              BIT11
+#define XHC1_FUNC_RESET              BIT12
+
+#define XHCI_ACPI_MMIO_AMD_REG04     0x04
+#define XHCI_ACPI_MMIO_AMD_REG08     0x08
+#define XHCI_ACPI_MMIO_AMD_REG20     0x20
+#define XHCI_ACPI_MMIO_AMD_REG90     0x90 // adaptation timer settings
+#define XHCI_ACPI_MMIO_AMD_REG98     0x98
+#define XHCI_ACPI_MMIO_AMD_REGA0     0xA0 // BAR 0
+#define XHCI_ACPI_MMIO_AMD_REGA4     0xA4 // BAR 1
+#define XHCI_ACPI_MMIO_AMD_REGA8     0xA8 // BAR 2
+#define XHCI_ACPI_MMIO_AMD_REGB0     0xB0 // SPI_Valid_Base.
+#define XHCI_ACPI_MMIO_AMD_REGC0     0xC0 // Firmware starting offset for coping
+#define XHCI_ACPI_MMIO_AMD_REGB4     0xB4
+#define XHCI_ACPI_MMIO_AMD_REGD0     0xD0
+
+#define FCH_XHCI_REG48                0x48 // XHCI IND_REG Index registers
+#define FCH_XHCI_REG4C                0x4C // XHCI IND_REG Data registers
+
+#define FCH_XHCI_IND60_BASE           0x40000000ul //
+
+#define FCH_XHCI_IND60_REG00           FCH_XHCI_IND60_BASE + 0x00 //
+#define FCH_XHCI_IND60_REG04           FCH_XHCI_IND60_BASE + 0x04 //
+#define FCH_XHCI_IND60_REG08           FCH_XHCI_IND60_BASE + 0x08 //
+#define FCH_XHCI_IND60_REG0C           FCH_XHCI_IND60_BASE + 0x0C //
+#define FCH_XHCI_IND60_REG18           FCH_XHCI_IND60_BASE + 0x18 //
+
+
+#define FCH_XHCI_IND_REG00            0x00 //
+#define FCH_XHCI_IND_REG04            0x04 //
+#define FCH_XHCI_IND_REG88            0x88 //
+#define FCH_XHCI_IND_REG94            0x94 // adaptation mode settings
+#define FCH_XHCI_IND_REG98            0x98 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REGC8            0xC8 //
+#define FCH_XHCI_IND_REGD4            0xD4 // adaptation mode settings
+#define FCH_XHCI_IND_REGD8            0xD8 // CR phase and frequency filter settings
+
+#define SPI_HEAD_LENGTH 0x0E
+#define SPI_BAR0_VLD  0x01
+#define SPI_BASE0     (0x00 << 7)
+#define SPI_BAR1_VLD  (0x01 << 8)
+#define SPI_BASE1     (SPI_HEAD_LENGTH << 10)
+#define SPI_BAR2_VLD  (0x01 << 16)
+#define SPI_BASE2(x)  ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
+
+#define FW_TO_SIGADDR_OFFSET  0x0C
+#define BCD_ADDR_OFFSET       0x02
+#define BCD_SIZE_OFFSET       0x04
+#define FW_ADDR_OFFSET        0x06
+#define FW_SIZE_OFFSET        0x08
+#define ACD_ADDR_OFFSET       0x0A
+#define ACD_SIZE_OFFSET       0x0C
+
+#define PKT_DATA_REG       ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
+#define PKT_LEN_REG        ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
+#define PKT_CTRL_REG       ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
+#define EFUS_DAC_ADJUSTMENT_CONTROL    0x850A8ul
+#define BGADJ                             0x1F
+#define DACADJ                            0x1B
+#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA  (BGADJ + (DACADJ << 8) + BIT16 )
+
+#ifndef FCH_DEADLOOP
+  #define FCH_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPage.h
new file mode 100644
index 0000000000..9d536214ba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPage.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for FCH Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/**
+ * @page fchmain FCH Component Documentation
+ *
+ * Additional documentation for the FCH component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage fchinitguide  "FCH Implementation Guide"
+ *   - @subpage fchauxguide  "FCH UEFI Auxiliary driver"
+ *   - @subpage fchhwmguide  "FCH Hardware Monitor driver"
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h
new file mode 100644
index 0000000000..8e5072ca2b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH platform definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#ifndef  _FCH_PLATFORM_H_
+#define  _FCH_PLATFORM_H_
+
+#define MAX_SATA_PORTS 8
+
+#include "AGESA.h"
+
+#ifndef FCHOEM_ACPI_RESTORE_SWSMI
+  #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI    0xD3
+  #define FCHOEM_AFTER_PCI_RESTORE_SWSMI     0xD4
+  #define FCHOEM_ENABLE_ACPI_SWSMI           0xA0
+  #define FCHOEM_DISABLE_ACPI_SWSMI          0xA1
+  #define FCHOEM_START_TIMER_SMI             0xBC
+  #define FCHOEM_STOP_TIMER_SMI              0xBD
+#endif
+
+#ifndef FCHOEM_SPI_UNLOCK_SWSMI
+  #define FCHOEM_SPI_UNLOCK_SWSMI            0xAA
+#endif
+#ifndef FCHOEM_SPI_LOCK_SWSMI
+  #define FCHOEM_SPI_LOCK_SWSMI              0xAB
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
+  #define FCHOEM_ACPI_TABLE_RANGE_LOW        0xE0000ul
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
+  #define FCHOEM_ACPI_TABLE_RANGE_HIGH       0xFFFF0ul
+#endif
+
+#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
+  #define FCHOEM_ACPI_BYTE_CHECHSUM          0x100
+#endif
+
+#ifndef FCHOEM_IO_DELAY_PORT
+  #define FCHOEM_IO_DELAY_PORT               0x80
+#endif
+
+#ifndef FCHOEM_OUTPUT_DEBUG_PORT
+  #define FCHOEM_OUTPUT_DEBUG_PORT           0x80
+#endif
+
+#define FCH_PCIRST_BASE_IO                   0xCF9
+#define FCH_PCI_RESET_COMMAND06              0x06
+#define FCH_PCI_RESET_COMMAND0E              0x0E
+#define FCH_KBDRST_BASE_IO                   0x64
+#define FCH_KBC_RESET_COMMAND                0xFE
+#define FCH_ROMSIG_BASE_IO                   0x20000l
+#define FCH_ROMSIG_SIGNATURE                 0x55AA55AAul
+#define FCH_MAX_TIMER                        0xFFFFFFFFul
+#define FCH_GEC_INTERNAL_REG                 0x6804
+#define FCH_HPET_REG_MASK                    0xFFFFF800ul
+#define FCH_FAKE_USB_BAR_ADDRESS             0x58830000ul
+
+
+#ifndef FCHOEM_ELAPSED_TIME_UNIT
+  #define FCHOEM_ELAPSED_TIME_UNIT           28
+#endif
+
+#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
+  #define FCHOEM_ELAPSED_TIME_DIVIDER        100
+#endif
+
+#include "Fch.h"
+#include "amdlib.h"
+#include "FchCommonCfg.h"
+#include "AcpiLib.h"
+#include "FchDef.h"
+#include "FchBiosRamUsage.h"
+#include "AmdFch.h"
+
+extern BUILD_OPT_CFG    UserOptions;
+
+#endif // _FCH_PLATFORM_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
new file mode 100644
index 0000000000..01aeae991b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
@@ -0,0 +1,130 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE
+
+/**
+ * FchInitGecController - Config GEC controller
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitGecController (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8              FchSBGecDebugBus;
+  UINT8              FchSBGecPwr;
+  FCH_DATA_BLOCK     *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  FchSBGecDebugBus = (UINT8) LocalCfgPtr->Gec.GecDebugBus;
+  FchSBGecPwr = (UINT8) LocalCfgPtr->Gec.GecPowerPolicy;
+
+  if ( LocalCfgPtr->Misc.Cg2Pll == 1 ) {
+    LocalCfgPtr->Gec.GecEnable = FALSE;
+  }
+
+  if ( LocalCfgPtr->Gec.GecEnable == TRUE) {
+    //
+    // GEC Enabled
+    //
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xF6 , AccessWidth8, (UINT32)~BIT0, 0x00);
+
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG11, AccessWidth8, 0, 0x00);
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG21, AccessWidth8, 0, 0x01);
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG166, AccessWidth8, 0, 0x01);
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xB5 , AccessWidth8, 0, 0x01);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF8, AccessWidth8, (UINT32)~(BIT5 + BIT6), (UINT8) ((FchSBGecPwr) << 5));
+
+    if (FchSBGecDebugBus == 1) {
+      //
+      // GEC Debug Bus Enabled
+      //
+      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT3, BIT3);
+    } else {
+      //
+      // GEC Debug Bus Disabled
+      //
+      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT3, 0x00);
+    }
+  } else {
+    //
+    // GEC Disabled
+    //
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT0, BIT0);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
new file mode 100644
index 0000000000..ccbeec27a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE
+
+/**
+ * FchSwInitGecBootRom - Config GEC Boot ROM by Platform define
+ * ROM address
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSwInitGecBootRom (
+  IN  VOID     *FchDataPtr
+  )
+{
+  VOID*        GecRomAddress;
+  VOID*        GecShadowRomAddress;
+  UINT32       Temp;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( !LocalCfgPtr->Gec.PtrDynamicGecRomAddress == 0 ) {
+    GecRomAddress = LocalCfgPtr->Gec.PtrDynamicGecRomAddress;
+    GecShadowRomAddress = (VOID*) (UINTN) LocalCfgPtr->Gec.GecShadowRomBase;
+    FchCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
+    ReadPci ((GEC_BUS_DEV_FUN << 16) + FCH_GEC_REG10, AccessWidth32, &Temp, StdHeader);
+    Temp = Temp & 0xFFFFFFF0;
+    RwMem (Temp + FCH_GEC_INTERNAL_REG, AccessWidth32, 0, BIT0 + BIT29);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c
new file mode 100644
index 0000000000..5a6c27f77e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_GEC_GECENV_FILECODE
+
+
+/**
+ * FchInitEnvGec - Config GEC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvGec (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitGecController (FchDataPtr);
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c
new file mode 100644
index 0000000000..1178ebffa9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_GEC_GECLATE_FILECODE
+
+/**
+ * FchInitLateGec - Prepare GEC controller to boot to OS.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateGec (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecMid.c
new file mode 100644
index 0000000000..11cba8eaf7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecMid.c
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_GEC_GECMID_FILECODE
+
+
+
+/**
+ * FchInitMidGec - Config GEC controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidGec (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchSwInitGecBootRom (FchDataPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c
new file mode 100644
index 0000000000..a3ce6293ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH GEC controller
+ *
+ * Init Gec Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_GEC_GECRESET_FILECODE
+
+/**
+ * FchInitResetGec - Config Gec controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetGec (
+  IN  VOID     *FchDataPtr
+  )
+{
+  //
+  // Init Gec SHADOW Rom Base Address
+  //
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG9C, AccessWidth32, 0, \
+    UserOptions.FchBldCfg->CfgGecShadowRomBase + 1, ((FCH_RESET_DATA_BLOCK *) FchDataPtr)->StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
new file mode 100644
index 0000000000..4d8a917b69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
@@ -0,0 +1,586 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE
+
+#define AMD_CPUID_APICID_LPC_BID    0x00000001ul  // Local APIC ID, Logical Processor Count, Brand ID
+
+/**
+ * FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial
+ * during POST.
+ *
+ */
+ACPI_REG_WRITE FchHudson2InitEnvHwAcpiMmioTable[] =
+{
+  {00, 00, 0xB0, 0xAC},                                         /// Signature
+
+  //
+  // HPET workaround
+  //
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
+  //
+  // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3]
+  // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
+  // UsbGoodClkDlyEn         4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
+  // ForceNBCPUPwr           5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
+  // MergeUsbPerReq          6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
+  // IMCWatchDogRstEn        7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
+  // GeventStsFixEn          8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
+  // PmeTimerFixEn           9 Set to 1 to reset Pme Timer when going to sleep state.
+  // UserRst2EcEn           10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
+  // Smbus0ClkSEn           30 Set to 1 to enable SMBus0 controller clock stretch support.
+  //
+  {PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0xF9},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x04, 0x07},
+  //
+  // RtcSts              19-17 RTC_STS set only in Sleep State.
+  // GppPme                 20 Set to 1 to enable PME request from SB GPP.
+  // Pcireset               22 Set to 1 to allow SW to reset PCIe.
+  //
+  {PMIO_BASE >> 8, 0xC2 , 0x20, 0x58},
+  {PMIO_BASE >> 8, 0xC2  + 1, 0, 0x40},
+  {PMIO_BASE >> 8, 0xC2 , (UINT8)~(BIT4), BIT4},
+
+  {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x01},
+  {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
+  {PMIO_BASE >> 8, FCH_PMIOA_REG74 + 3, (UINT8)~BIT5, 0},
+  {PMIO_BASE >> 8, 0xDE  + 1, (UINT8)~(BIT0 + BIT1), BIT0 + BIT1},
+  {PMIO_BASE >> 8, 0xDE , (UINT8)~BIT4, BIT4},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0},
+  {PMIO_BASE >> 8, 0xDC , 0x7C, BIT0},                 /// Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
+  {PMIO_BASE >> 8, FCH_PMIOA_REGBF, (UINT8)~BIT0, 0},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGBE, (UINT8)~BIT0, BIT0},
+
+  {SMI_BASE >> 8, 0x41 , 0, 1},
+  {SMI_BASE >> 8, 0x43 , 0, 3},
+  {SMI_BASE >> 8, 0x44 , 0, 4},
+  {SMI_BASE >> 8, 0x45 , 0, 5},
+  {SMI_BASE >> 8, 0x46 , 0, 6},
+  {SMI_BASE >> 8, 0x57 , 0, 23},
+  {SMI_BASE >> 8, 0x78 , 0, 11},
+  {SMI_BASE >> 8, 0x79 , 0, 11},
+  {SMI_BASE >> 8, 0x58 , 0, 11},
+  {SMI_BASE >> 8, 0x59 , 0, 11},
+  {SMI_BASE >> 8, 0x5A , 0, 11},
+  {SMI_BASE >> 8, 0x5B , 0, 11},
+  {SMI_BASE >> 8, 0x68 , 0, 12},
+  {SMI_BASE >> 8, 0x6C , 0, 13},
+  {SMI_BASE >> 8, 0x5C , 0, 15},
+  {SMI_BASE >> 8, 0x5D , 0, 16},
+  {SMI_BASE >> 8, 0x5E , 0, 17},
+  {SMI_BASE >> 8, 0x5F , 0, 18},
+  {SMI_BASE >> 8, 0x67 , 0, 19},
+  {SMI_BASE >> 8, 0x6A , 0, 28},
+  {SMI_BASE >> 8, 0x48 , 0, 24},
+  {SMI_BASE >> 8, 0x64 , 0, 27},
+  {SMI_BASE >> 8, 0x65 , 0, 30},
+  {SMI_BASE >> 8, 0x66 , 0, 31},
+  {SMI_BASE >> 8, FCH_SMI_REG08,  0xE7, 0},
+  {SMI_BASE >> 8, FCH_SMI_REG0C + 2, (UINT8)~BIT3, BIT3},
+  {SMI_BASE >> 8, 0x70 , 0, 9},
+  {SMI_BASE >> 8, FCH_SMI_REG3C,  0, BIT6},
+  {SMI_BASE >> 8, 0x84  + 2,  0, BIT7},
+
+  //
+  // CG PLL CMOX Clock Driver Setting for power saving
+  //
+  {MISC_BASE >> 8, FCH_MISC_REG18 + 0x06, 0, 0xE0},
+  {MISC_BASE >> 8, FCH_MISC_REG18 + 0x07, 0, 0x1F},
+
+  {MISC_BASE >> 8, 0x50  + 3, (UINT8)~BIT5, BIT5},
+  {MISC_BASE >> 8, 0x50  + 2, (UINT8)~BIT3, BIT3},
+  //{SERIAL_DEBUG_BASE >> 8, FCH_SDB_REG74, 0, 0},
+  {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * FchHudson2InitEnvHwAcpiPciTable - PCI device registers initial
+ * during early POST.
+ *
+ */
+REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] =
+{
+  //
+  // SMBUS Device (Bus 0, Dev 20, Func 0)
+  //
+  {0x00, SMBUS_BUS_DEV_FUN, 0},
+  {FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)},                ///Program the version information
+  {FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)},
+  {0xFF, 0xFF, 0xFF},
+};
+
+
+/**
+ * ProgramPFchAcpiMmio - Config HwAcpi MMIO registers
+ *   Acpi S3 resume won't execute this procedure (POST only)
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ProgramEnvPFchAcpiMmio (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchHudson2InitEnvHwAcpiMmioTable[0]), StdHeader);
+}
+
+/**
+ * ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller
+ * before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ProgramFchEnvHwAcpiPciReg (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // FCH CFG programming
+  //
+  // Make BAR registers of smbus visible.
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, (UINT8)~BIT6, 0);
+
+  //
+  //Early post initialization of pci config space
+  //
+  ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader);
+
+  if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
+    RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
+  }
+
+  //
+  //Make BAR registers of smbus invisible.
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, (UINT8)~BIT6, BIT6);
+}
+
+/**
+ * FchVgaInit - Config VGA CODEC
+ *
+ * @param[in] VOID empty
+ *
+ */
+VOID
+FchVgaInit (
+  OUT VOID
+  )
+{
+  //
+  // Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xff, BIT5 );
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 , AccessWidth8, 0x00, 0x17 );
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD9 , AccessWidth8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3)));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 , AccessWidth8, 0x00, 0x16 );
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD9 , AccessWidth8, 0x0f, ((DACADJ & 0x0f) << 4));
+
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08;
+  *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01;
+}
+
+/**
+ * ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before
+ * PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ProgramSpecificFchInitEnvAcpiMmio (
+  IN  VOID     *FchDataPtr
+  )
+{
+  CPUID_DATA      CpuId;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  //
+  // Set ASF SMBUS master function enabled here (temporary)
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x28 , AccessWidth16, (UINT32)~(BIT0 + BIT2), BIT0 + BIT2);
+
+#ifdef ACPI_SLEEP_TRAP
+  //
+  // Set SLP_TYPE as SMI event
+  //
+  RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, AccessWidth8, (UINT32)~(BIT2 + BIT3), BIT2);
+
+  //
+  // Disabled SLP function for S1/S3/S4/S5
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE, AccessWidth8, (UINT32)~BIT5, 0x00);
+
+  //
+  // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG08 + 3, AccessWidth8, (UINT32)~(BIT0 + BIT1), BIT1);
+
+  //
+  // Enabled Global Smi ( BIT7 clear as 0 to enable )
+  //
+  RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98 + 3 , AccessWidth8, (UINT32)~BIT7, 0x00);
+#endif
+
+  //
+  // Set Stutter timer settings
+  //
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 1, AccessWidth8, (UINT32)~(BIT3 + BIT4), BIT3 + BIT4);
+
+  //
+  // Set LDTSTP# duration to 10us for Specific CPU, or when HT link is 200MHz
+  //
+  if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x28);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x20);
+  }
+
+  //
+  // SSC will provide better jitter margin
+  //
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccessWidth8, 0xFC, 0x01);
+  //
+  // Ac Loss Control
+  //
+  AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow);
+  //
+  //FCH VGA Init
+  //
+  FchVgaInit ();
+
+  //
+  // 2.16 Enable DMAACTIVE
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7F, AccessWidth8, 0xFE, 0x01);
+
+  //
+  // Set ACPIMMIO by OEM Input table
+  //
+  ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader);
+}
+
+/**
+ * ValidateFchVariant - Validate FCH Variant
+ *
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+ValidateFchVariant (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                  XhciEfuse;
+  UINT8                  PcieEfuse;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  switch ( LocalCfgPtr->Misc.FchVariant ) {
+  case FCH_M3T:
+    //Disable Devices for M3T
+    LocalCfgPtr->Gec.GecEnable = 1;
+    LocalCfgPtr->Hwm.HwMonitorEnable = 0;
+    LocalCfgPtr->Sd.SdConfig = 0;
+    LocalCfgPtr->Ir.IrConfig = 0;
+    break;
+
+  default:
+    break;
+  }
+
+  // add Efuse checking for Xhci enable/disable
+  XhciEfuse = XHCI_EFUSE_LOCATION;
+  GetEfuseStatus (&XhciEfuse, StdHeader);
+  if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) {
+    LocalCfgPtr->Usb.Xhci0Enable = 0;
+    LocalCfgPtr->Usb.Xhci1Enable = 0;
+  }
+
+  // add Efuse checking for PCIE Gen2 enable
+  PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
+  GetEfuseStatus (&PcieEfuse, StdHeader);
+  if ( PcieEfuse & BIT0 ) {
+    LocalCfgPtr->Gpp.GppGen2 = 0;
+  }
+}
+
+/**
+ * IsExternalClockMode - Is External Clock Mode?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsExternalClockMode (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8    MISC80;
+  ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80, AccessWidth8, &MISC80);
+  return ( (BOOLEAN) ((MISC80 & BIT4) == 0) );
+}
+
+
+/**
+ * ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before
+ * PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ProgramFchEnvSpreadSpectrum (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        PortStatus;
+  UINT8        FchSpreadSpectrum;
+
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum;
+
+  if ((FchSpreadSpectrum > 0) && !(IsExternalClockMode (FchDataPtr))) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth32, (UINT32) (~(0x1 << 25)), (0x1 << 25));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 0)), (0x0 << 0));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0x7FF << 5)), (0x318 << 5));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0xF << 16)), (0x0 << 16));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFFFF << 8)), (0x6F83 << 8));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFF << 0)), (0x90 << 0));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth32, (UINT32) (~(0x3F << 0)), (0x0 << 0));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0xF << 28)), (0x7 << 28));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 7)), (0x0 << 8));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 8)), (0x1 << 8));
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0x3 << 24)), (0x1 << 24));
+
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x01);
+  } else {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
+  }
+
+  //
+  // PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
+  // OSC Clock setting for  internal clock generator mode (BIT6)
+  //
+  GetChipSysMode (&PortStatus, StdHeader);
+  if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE +  0x04  + 1, AccessWidth8, (UINT32)~(BIT5 + BIT6), BIT5 + BIT6);
+  }
+}
+
+/**
+ * TurnOffCG2
+ *
+ *
+ * @retval  VOID
+ *
+ */
+VOID
+TurnOffCG2 (
+  OUT VOID
+  )
+{
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth8, (UINT32)~BIT6, 0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0x0F, 0xA0);
+  RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccessWidth8, (UINT32)~(BIT1 + BIT0), (BIT1 + BIT0));
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~( BIT4), (BIT4));
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~(BIT6), (BIT6));
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth8, (UINT32)~BIT6, BIT6);
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, (UINT32)~BIT6, BIT6);
+}
+
+/**
+ * BackUpCG2
+ *
+ *
+ * @retval  VOID
+ *
+ */
+VOID
+BackUpCG2 (
+  OUT VOID
+  )
+{
+  UINT8 Byte;
+  ReadMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, &Byte);
+  if (Byte & BIT6) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~(BIT6), (0));
+  }
+}
+
+/**
+ * HpetInit - Program Fch HPET function
+ *
+ *
+ *
+ * @param[in] FchDataPtr         Fch configuration structure pointer.
+ *
+ */
+VOID
+HpetInit (
+  IN  VOID     *FchDataPtr
+  )
+{
+  DESCRIPTION_HEADER   *HpetTable;
+  UINT8                FchHpetTimer;
+  UINT8                FchHpetMsiDis;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetEnable;
+  FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis;
+
+  HpetTable = NULL;
+  if ( FchHpetTimer == TRUE ) {
+    //
+    //Program the HPET BAR address
+    //
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase);
+
+    //
+    //Enabling decoding of HPET MMIO
+    //Enable HPET MSI support
+    //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
+    //
+    if ( FchHpetMsiDis == FALSE ) {
+      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
+#ifdef FCH_TIMER_TICK_INTERVAL_WA
+      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
+#endif
+    } else {
+      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
+    }
+
+  } else {
+    if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
+      HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable (Int32FromChar('H','P','E','T')); /* 'TEPH' */
+    }
+    if ( HpetTable != NULL ) {
+      HpetTable->Signature = Int32FromChar('T','E','P','H'); /* 'HPET' */
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
new file mode 100644
index 0000000000..ee19fb92ce
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
@@ -0,0 +1,315 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE
+
+#define AMD_CPUID_APICID_LPC_BID    0x00000001ul  // Local APIC ID, Logical Processor Count, Brand ID
+
+/**
+ * C3PopupSetting - Program Fch C state function
+ *
+ *
+ *
+ * @param[in] FchDataPtr   Fch configuration structure pointer.
+ *
+ */
+VOID
+C3PopupSetting (
+  IN  VOID     *FchDataPtr
+  )
+{
+#define NON_SUPPORT_PREVIOUS_C3 TRUE
+#ifndef NON_SUPPORT_PREVIOUS_C3
+  UINT32       Value;
+  BOOLEAN      ProcessorPresent;
+
+  //
+  // C-State and VID/FID Change
+  //
+  ProcessorPresent = GetActiveCoresInGivenSocket (0, &Value, ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader);
+
+  if (ProcessorPresent && (Value > 1)) {
+    //
+    //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
+    //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
+    //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the FCH will de-assert
+    //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
+    //
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth8, (UINT32)~(BIT1 + BIT2), (BIT1 + BIT2));
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, (UINT32)~BIT6, BIT6);
+  }
+
+  //
+  //PM 0x80 [8] = 0 for system with NB
+  //Note: North bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
+  //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
+  //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
+
+  //
+  //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
+  //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
+  //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
+  //link is disconnected.
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94 + 2, AccessWidth8, 0, 0x10);
+
+  //
+  //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 1, AccessWidth8, 0, 0x10);
+
+  //
+  // ASIC info
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C, AccessWidth8, 0, 0x85);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C + 1, AccessWidth8, 0, 0x01);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E + 1, AccessWidth8, (UINT32)~(BIT7 + BIT5), BIT7 + BIT5);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88 + 1, AccessWidth8, (UINT32)~BIT4, BIT4);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 3, AccessWidth8, 0, 0x10);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4 + 1, AccessWidth8, 0, 0x0B);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, (UINT32)~(BIT4 + BIT5), BIT4 + BIT5);
+#else
+  // C-State and VID/FID Change
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, (UINT32)~(BIT5), BIT5);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT2), BIT2);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT1), BIT1);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, (UINT32)~(BIT6), BIT6);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG89, AccessWidth8, (UINT32)~BIT4, BIT4);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, (UINT32)~BIT4, BIT4);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, (UINT32)~(BIT6 + BIT5 + BIT4), BIT4);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x9B , AccessWidth8, (UINT32)~(BIT1 + BIT0), 0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG96, AccessWidth8, 0, 0x10);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG99, AccessWidth8, 0, 0x10);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG8E, AccessWidth8, 0, 0x80);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG97, AccessWidth8, (UINT32)~(BIT1 + BIT0), 0);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT4), BIT4);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT9), BIT9);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT7), 0);
+#endif
+
+}
+
+/**
+ * GcpuRelatedSetting - Program Gcpu C related function
+ *
+ *
+ *
+ * @param[in] FchDataPtr   Fch configuration structure pointer.
+ *
+ */
+VOID
+GcpuRelatedSetting (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        FchAcDcMsg;
+  UINT8        FchTimerTickTrack;
+  UINT8        FchClockInterruptTag;
+  UINT8        FchOhciTrafficHanding;
+  UINT8        FchEhciTrafficHanding;
+  UINT8        FchGcpuMsgCMultiCore;
+  UINT8        FchGcpuMsgCStage;
+  UINT32       Value;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  FchAcDcMsg = (UINT8) LocalCfgPtr->Gcpu.AcDcMsg;
+  FchTimerTickTrack = (UINT8) LocalCfgPtr->Gcpu.TimerTickTrack;
+  FchClockInterruptTag = (UINT8) LocalCfgPtr->Gcpu.ClockInterruptTag;
+  FchOhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.OhciTrafficHanding;
+  FchEhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.EhciTrafficHanding;
+  FchGcpuMsgCMultiCore = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCMultiCore;
+  FchGcpuMsgCStage = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCStage;
+
+  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
+  Value = Value & 0xC07F00A0;
+
+  if ( FchAcDcMsg ) {
+    Value = Value | BIT0;
+  }
+
+  if ( FchTimerTickTrack ) {
+    Value = Value | BIT1;
+  }
+
+  if ( FchClockInterruptTag ) {
+    Value = Value | BIT10;
+  }
+
+  if ( FchOhciTrafficHanding ) {
+    Value = Value | BIT13;
+  }
+
+  if ( FchEhciTrafficHanding ) {
+    Value = Value | BIT15;
+  }
+
+  if ( FchGcpuMsgCMultiCore ) {
+    Value = Value | BIT23;
+  }
+
+  if ( FchGcpuMsgCMultiCore ) {
+    Value = (Value | (BIT6 + BIT4 + BIT3 + BIT2));
+  }
+
+  WriteMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
+}
+
+/**
+ * MtC1eEnable - Program Mt C1E Enable Function
+ *
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+MtC1eEnable (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  if ( LocalCfgPtr->HwAcpi.MtC1eEnable ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, (UINT32)~BIT15, BIT15);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, (UINT32)~(BIT3 + BIT2 + BIT1 + BIT0), 0x01);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT13 + BIT7), BIT13 + BIT7);
+  }
+}
+
+/**
+ * StressResetModeLate - Stress Reset Mode
+ *
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+StressResetModeLate (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                  ResetValue;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  switch ( LocalCfgPtr->HwAcpi.StressResetMode ) {
+  case 0:
+    return;
+  case 1:
+    ResetValue = FCH_KBC_RESET_COMMAND;
+    LibAmdIoWrite (AccessWidth8, FCH_KBDRST_BASE_IO, &ResetValue, StdHeader);
+    break;
+  case 2:
+    ResetValue = FCH_PCI_RESET_COMMAND06;
+    LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader);
+    break;
+  case 3:
+    ResetValue = FCH_PCI_RESET_COMMAND0E;
+    LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader);
+    break;
+  case 4:
+    LocalCfgPtr->HwAcpi.StressResetMode = 3;
+    return;
+  default:
+    ASSERT (FALSE);
+    return;
+  }
+  while (LocalCfgPtr->HwAcpi.StressResetMode) {
+  }
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
new file mode 100644
index 0000000000..319c92ee81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
new file mode 100644
index 0000000000..383ab8d247
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init Spread Spectrum features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE
+
+/**
+ * FchInitResetAcpiMmioTable - Fch ACPI MMIO initial
+ * during the power on stage.
+ *
+ *
+ *
+ *
+ */
+ACPI_REG_WRITE FchInitResetAcpiMmioTable[] =
+{
+  {00, 00, 0xB0, 0xAC},                                         /// Signature
+  {MISC_BASE >> 8,  FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
+  //
+  // USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
+  //
+  {MISC_BASE >> 8,  FCH_MISC_REG40, 0xEF, 0x00},
+
+  {PMIO_BASE >> 8,  0x5D , 0x00, BIT0},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
+  {SMBUS_BASE >> 8, FCH_SMBUS_REG12, 0x00, BIT0},
+  {PMIO_BASE >> 8,  0x28 , 0xFF, BIT0 + BIT2},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG44 + 3, 0x67, 0},            /// Stop Boot timer
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG48, 0xFF, BIT0},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG00, 0xFF, 0x0E},
+  {PMIO_BASE >> 8,  0x00  + 2, 0xFF, 0x40},
+  {PMIO_BASE >> 8,  0x00  + 3, 0xFF, 0x08},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG34, 0xEF, BIT0 + BIT1},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REGEC, 0xFD, BIT1},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG08, 0xFE, BIT2 + BIT4},
+  {PMIO_BASE >> 8,  0x04  + 1, 0xFF, BIT0},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
+  {PMIO_BASE >> 8,  0x04  + 3, 0xFD, BIT1},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REG74, 0xF6, BIT0 + BIT3},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REGF0, (UINT8)~BIT2, 0x00},
+
+  //
+  // GEC I/O Termination Setting
+  // PM_Reg 0xF6 = Power-on default setting
+  // PM_Reg 0xF7 = Power-on default setting
+  // PM_Reg 0xF8 = 0x6C
+  // PM_Reg 0xF9 = 0x21
+  // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
+  //
+  {PMIO_BASE >> 8, FCH_PMIOA_REGF8,     0x00, 0x6C},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 1, 0x00, 0x07},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 2, 0x00, 0x00},
+  //
+  // GEC -end
+  //
+
+  {PMIO_BASE >> 8, FCH_PMIOA_REGC4, 0xee, 0x04},                 /// Release NB_PCIE_RST
+  {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 2, 0xBF, 0x40},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGBE, 0xDF, BIT5},
+
+  //
+  // Enabling ClkRun Function
+  //
+  {PMIO_BASE >> 8,  FCH_PMIOA_REGBB, 0xFF, BIT2},
+  {PMIO_BASE >> 8,  FCH_PMIOA_REGD0, (UINT8)~BIT2, 0},
+
+  {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * ProgramFchHwAcpiResetP  - Config SpreadSpectrum before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ProgramFchHwAcpiResetP (
+  IN VOID  *FchDataPtr
+  )
+{
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
+
+  RwPmio (0xD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader);
+  RwPmio (0xD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
+
+  if ( LocalCfgPtr->Cg2Pll == 1 ) {
+    TurnOffCG2 ();
+    LocalCfgPtr->SataClkMode = 0x0a;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c
new file mode 100644
index 0000000000..38a54a6134
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c
@@ -0,0 +1,135 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_HWACPIENV_FILECODE
+
+
+
+
+
+
+
+/**
+ * FchInitEnvHwAcpiP - Config HwAcpi controller preliminary
+ *   (Special)
+ *   Acpi S3 resume won't execute this procedure (POST only)
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvHwAcpiP (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  RecordFchConfigPtr ( (UINT32) ((UINTN) (LocalCfgPtr)));
+
+  ValidateFchVariant (LocalCfgPtr);
+
+  ProgramEnvPFchAcpiMmio (FchDataPtr);
+
+  ProgramFchEnvSpreadSpectrum (FchDataPtr);
+}
+
+/**
+ * FchInitEnvHwAcpi - Config HwAcpi controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvHwAcpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  ProgramFchEnvHwAcpiPciReg (FchDataPtr);
+  //
+  // FCH Specific Function programming
+  //
+  ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr);
+  HpetInit (LocalCfgPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
new file mode 100644
index 0000000000..e3f5beb56d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
@@ -0,0 +1,205 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE
+
+#define AMD_CPUID_APICID_LPC_BID    0x00000001ul  // Local APIC ID, Logical Processor Count, Brand ID
+
+
+
+
+
+
+
+///
+/// PCI_IRQ_REG_BLOCK- FCH PCI IRQ registers block
+///
+typedef struct _PCI_IRQ_REG_BLOCK {
+  UINT8                PciIrqIndex;       // PciIrqIndex - selects which PCI interrupt to map
+  UINT8                PciIrqData;        // PciIrqData  - Interrupt #
+} PCI_IRQ_REG_BLOCK;
+
+STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = {
+    { (FCH_IRQ_INTA | FCH_IRQ_IOAPIC), 0x10},
+    { (FCH_IRQ_INTB | FCH_IRQ_IOAPIC), 0x11},
+    { (FCH_IRQ_INTC | FCH_IRQ_IOAPIC), 0x12},
+    { (FCH_IRQ_INTD | FCH_IRQ_IOAPIC), 0x13},
+    { (FCH_IRQ_INTE | FCH_IRQ_IOAPIC), 0x14},
+    { (FCH_IRQ_INTF | FCH_IRQ_IOAPIC), 0x15},
+    { (FCH_IRQ_INTG | FCH_IRQ_IOAPIC), 0x16},
+    { (FCH_IRQ_INTH | FCH_IRQ_IOAPIC), 0x17},
+    { (FCH_IRQ_HDAUDIO | FCH_IRQ_IOAPIC), 0x10},
+    { (FCH_IRQ_GEC | FCH_IRQ_IOAPIC), 0x10},
+    { (FCH_IRQ_SD | FCH_IRQ_IOAPIC), 0x10},
+    { (FCH_IRQ_GPPINT0 | FCH_IRQ_IOAPIC), 0x10},
+    { (FCH_IRQ_IDE | FCH_IRQ_IOAPIC), 0x11},
+    { (FCH_IRQ_USB18INTB | FCH_IRQ_IOAPIC), 0x11},
+    { (FCH_IRQ_USB19INTB | FCH_IRQ_IOAPIC), 0x11},
+    { (FCH_IRQ_USB22INTB | FCH_IRQ_IOAPIC), 0x11},
+    { (FCH_IRQ_GPPINT1 + FCH_IRQ_IOAPIC), 0x11},
+    { (FCH_IRQ_USB18INTA | FCH_IRQ_IOAPIC), 0x12},
+    { (FCH_IRQ_USB19INTA | FCH_IRQ_IOAPIC), 0x12},
+    { (FCH_IRQ_USB22INTA | FCH_IRQ_IOAPIC), 0x12},
+    { (FCH_IRQ_USB20INTC | FCH_IRQ_IOAPIC), 0x12},
+    { (FCH_IRQ_GPPINT2 | FCH_IRQ_IOAPIC), 0x12},
+    { (FCH_IRQ_SATA | FCH_IRQ_IOAPIC), 0x13},
+    { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13},
+  };
+
+#define NUM_OF_DEVICE_FOR_APICIRQ  sizeof (FchInternalDeviceIrqForApicMode) / sizeof (PCI_IRQ_REG_BLOCK)
+
+/**
+ * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateHwAcpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+  UINT8                  i;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( IsGCPU (LocalCfgPtr) ) {
+    GcpuRelatedSetting (LocalCfgPtr);
+  } else {
+    //TNBU C3PopupSetting (LocalCfgPtr);
+  }
+
+  // Mt C1E Enable
+  MtC1eEnable (LocalCfgPtr);
+
+  if (LocalCfgPtr->Gpp.SerialDebugBusEnable == TRUE ) {
+    RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE +  FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05);
+  }
+
+  StressResetModeLate (LocalCfgPtr);
+  SbSleepTrapControl (FALSE); /* TODO: Checkout if we need to disable sleep trap in Non-SMI mode. */
+  for (i = 0; i < NUM_OF_DEVICE_FOR_APICIRQ; i++) {
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &FchInternalDeviceIrqForApicMode[i].PciIrqIndex, StdHeader);
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &FchInternalDeviceIrqForApicMode[i].PciIrqData, StdHeader);
+  }
+}
+
+/**
+ * IsGCPU - Is Gcpu Cpu?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsGCPU (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                   ExtendedFamily;
+  UINT8                   ExtendedModel;
+  UINT8                   BaseFamily;
+  UINT8                   BaseModel;
+  UINT8                   Stepping;
+  UINT8                   Family;
+  UINT8                   Model;
+  CPUID_DATA              CpuId;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
+
+  ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
+  ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
+  BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
+  BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
+  Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
+  Family = BaseFamily + ExtendedFamily;
+  Model = (ExtendedModel << 4) + BaseModel;
+
+  if ( (Family == 0x12) || \
+       (Family == 0x14) || \
+       (Family == 0x16)  ) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiMid.c
new file mode 100644
index 0000000000..6f391968d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiMid.c
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_HWACPIMID_FILECODE
+
+/**
+ * FchInitMidHwAcpi - Config HwAcpi controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidHwAcpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c
new file mode 100644
index 0000000000..5387f8c366
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c
@@ -0,0 +1,229 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch HwAcpi controller
+ *
+ * Init HwAcpi Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWACPI_HWACPIRESET_FILECODE
+
+extern ACPI_REG_WRITE FchInitResetAcpiMmioTable[];
+
+
+/**
+ * FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary
+ * ) during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetHwAcpiP (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+
+  StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
+
+  //
+  // Enabled (Mmio_mem_enable)
+  //
+  RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader);
+
+  ProgramFchHwAcpiResetP (FchDataPtr);
+
+  //
+  // enable CF9
+  //
+  RwPmio (0xD2, AccessWidth8, (UINT32)~BIT6, 0, StdHeader);
+}
+
+/**
+ * FchInitResetHwAcpi - Config HwAcpi controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetHwAcpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT16       SmbusBase;
+  UINT8        Value;
+  UINT16       AsfPort;
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Set Build option into SB
+  //
+  WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.FchBldCfg->CfgSioPmeBaseAddress), StdHeader);
+
+  //
+  // Enabled SMBUS0/SMBUS1 (ASF) Base Address
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus0BaseAddress) + BIT0);     ///protect BIT[2:1]
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x28 , AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus1BaseAddress) + BIT0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgCpuControlBlkAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr) + 8);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.FchBldCfg->CfgWatchDogTimerBase));
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0);                                    ///clear BIT[2:1]
+  SmbusBase = (UINT16) (UserOptions.FchBldCfg->CfgSmbus0BaseAddress);
+  Value = 0x00;
+  LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
+
+  ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
+
+  if (UserOptions.FchBldCfg->CfgFchSciMapControl != NULL) {
+    ProgramFchSciMapTbl ((UserOptions.FchBldCfg->CfgFchSciMapControl), LocalCfgPtr);
+  }
+
+  if (UserOptions.FchBldCfg->CfgFchGpioControl != NULL) {
+    ProgramFchGpioTbl ((UserOptions.FchBldCfg->CfgFchGpioControl), LocalCfgPtr);
+  }
+
+  if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) {
+    ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr);
+  }
+
+  //
+  // Prevent RTC error
+  //
+  Value = 0x0A;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
+  LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+  Value &= 0xEF;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+
+  Value = 0x08;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
+  LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
+  if ( !LocalCfgPtr->EcKbd ) {
+    //
+    // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+    //
+    Value = Value | 0x0A;
+  }
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
+
+  Value = 0x09;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
+  LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
+  if ( !LocalCfgPtr->EcKbd ) {
+    //
+    // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+    //
+    Value = Value & 0xF9;
+  }
+
+  if ( LocalCfgPtr->LegacyFree ) {
+    //
+    // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
+    //
+    Value = Value & 0x9F;
+  }
+  //
+  // Enabled IRQ input
+  //
+  Value = Value | BIT4;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
+
+  AsfPort = ((UINT16) UserOptions.FchBldCfg->CfgSmbus1BaseAddress & 0xFFF0);
+  if ( AsfPort != 0 ) {
+    UINT8  dbValue;
+    dbValue = 0x70;
+    LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
+  }
+  //
+  // Set ACPIMMIO by OEM Input table
+  //
+  if ( LocalCfgPtr->OemResetProgrammingTablePtr != NULL ) {
+    ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader);
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
new file mode 100644
index 0000000000..64315c8964
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
@@ -0,0 +1,294 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE
+
+FCH_HWM_TEMP_PAR TempParDefault[] = {
+  { 5220, 27365 , 0 },
+  { 5225, 27435 , 0 },
+  { 5220, 27516 , BIT0 },         ///High Ratio
+  { 5212, 27580 , BIT1 },         ///High Current
+  { 5123, 27866 , 0 }
+};
+
+/**
+ * HwmInitRegister - Init Hardware Monitor Register.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmInitRegister (
+  IN  VOID     *FchDataPtr
+  )
+{
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccessWidth8, 0, 0x55);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccessWidth8, 0, 0x55);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccessWidth8, 0, 0x55);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccessWidth8, 0, 0x55);
+
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccessWidth8, 0, 0x06);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccessWidth8, 0, 0x06);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccessWidth8, 0, 0x06);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccessWidth8, 0, 0x06);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccessWidth8, 0, 0x06);
+
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccessWidth8, 0, 0x01);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccessWidth8, 0, 0x01);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccessWidth8, 0, 0x01);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccessWidth8, 0, 0x01);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccessWidth8, 0, 0x01);
+
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccessWidth8, 0xff, 0x02);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccessWidth8, 0, 0x05);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccessWidth8, 0, 0x06);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccessWidth8, 0, 0x42);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccessWidth8, 0, 0xFF);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccessWidth8, 0, 0x1F);
+  //RPR 2.12 HWM Sensor Clk
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccessWidth8, 0, 0x0A);
+  RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccessWidth8, 0, 0x00);
+  //2.9 Enhancement of FanOut0 Control
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x50 , AccessWidth32, (UINT32)~ (BIT11 + BIT20), (BIT11 + BIT20));
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xB6 , AccessWidth8, 0x0F, 0x10);
+}
+
+/**
+ * HwmProcessParameter - Hardware Monitor process Parameter
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmProcessParameter (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Index;
+  UINT8        TempChannel;
+  UINT8        ValueByte;
+  UINT16       ValueWord;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  LibAmdMemCopy ((VOID *) (LocalCfgPtr->Hwm.HwmFanControlCooked), (VOID *) (LocalCfgPtr->Hwm.HwmFanControl), (sizeof (FCH_HWM_FAN_CTR) * 5), LocalCfgPtr->StdHeader);
+
+  HwmGetCalibrationFactor (LocalCfgPtr);
+  //
+  //temperatue parameter
+  //
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    if ( LocalCfgPtr->Hwm.HwmTempPar[Index].At == 0 ) {
+      LocalCfgPtr->Hwm.HwmTempPar[Index] = TempParDefault[Index];
+    }
+  }
+
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    if ( LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 == 100 ) {
+      LocalCfgPtr->Hwm.HwmFanControlCooked[Index].LowDutyReg03 = 255;
+    } else {
+      LocalCfgPtr->Hwm.HwmFanControlCooked[Index].LowDutyReg03 = (LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 << 8) / 100;
+    }
+
+    if ( LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 == 100 ) {
+      LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MedDutyReg04 = 255;
+    } else {
+      LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MedDutyReg04 = (LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 << 8) / 100;
+    }
+
+    ValueByte = (UINT8) ((256 - LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03) / (LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A - LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08));
+    ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].LowTempReg06;
+
+    if (LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00 > 4) {
+      TempChannel = 0;
+    } else {
+      TempChannel = LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00;
+    }
+
+    if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
+      ValueWord = ValueWord << 8;
+    } else {
+      ValueByte = (UINT8) (ValueByte * 10000 / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At);
+      ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
+    }
+    LocalCfgPtr->Hwm.HwmFanControlCooked[Index].LowTempReg06 = ValueWord;
+    LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MultiplierReg05 = ValueByte & 0x3f;
+
+    ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08;
+    if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
+      ValueWord = ValueWord << 8;
+    } else {
+      ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
+    }
+    LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MedTempReg08 = ValueWord;
+
+    ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A;
+    if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
+      ValueWord = ValueWord << 8;
+    } else {
+      ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
+    }
+    LocalCfgPtr->Hwm.HwmFanControlCooked[Index].HighTempReg0A = ValueWord;
+  }
+}
+
+/**
+ * hwmSetRegister - Hardware Monitor Set Parameter
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmSetRegister (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        *DbValuePtr;
+  UINT8        Index;
+  UINT8        RegisterN;
+  UINT8        RegisterPM2RegF8;
+  UINT8        RegisterPM2RegF9;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //Configure Fans
+  //
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    DbValuePtr = &(LocalCfgPtr->Hwm.HwmFanControlCooked[Index].InputControlReg00);
+    for ( RegisterN = 0; RegisterN < 0x0E ; RegisterN++ ) {
+      WritePmio2 (Index * 0x10 + RegisterN, AccessWidth8, DbValuePtr, StdHeader);
+      DbValuePtr ++;
+    }
+  }
+
+  //
+  //Configure Sample Frequency Divider
+  //
+  WritePmio2 (0x63 , AccessWidth8, &(LocalCfgPtr->Hwm.FanSampleFreqDiv), StdHeader);
+
+  //
+  //Configure Mode
+  //
+  ReadPmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader);
+  ReadPmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader);
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT0) {
+      RegisterPM2RegF8 |= 1 << (Index + 3);
+    } else if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT1) {
+      RegisterPM2RegF9 |= 1 << (Index + 3);
+    }
+  }
+  WritePmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader);
+  WritePmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader);
+}
+
+/**
+ * hwmGetCalibrationFactor - Hardware Monitor Get Calibration
+ * Factor
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmGetCalibrationFactor (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        ValueByte;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //temperatue parameter
+  //
+  ReadPmio2 (FCH_PMIO2_REGEA, AccessWidth8, &ValueByte, StdHeader);
+  if ( ValueByte & BIT7 ) {
+    if ( ValueByte & BIT6 ) {
+      LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x100 + ValueByte;
+    } else {
+      LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200 + (ValueByte & 0x3f );
+    }
+  } else {
+    LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
new file mode 100644
index 0000000000..7c1839b392
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
@@ -0,0 +1,216 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 64785 $   @e \$Date: 2012-01-30 21:46:59 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE
+
+/**
+ * Table for Function Number
+ *
+ *
+ *
+ *
+ */
+STATIC UINT8 FunctionNumber[] =
+{
+  Fun_81,
+  Fun_83,
+  Fun_85,
+  Fun_89,
+};
+
+/**
+ * Table for Max Thermal Zone
+ *
+ *
+ *
+ *
+ */
+UINT8 MaxZone[] =
+{
+  4,
+  4,
+  4,
+  4,
+};
+
+
+/**
+ * Table for Max Register
+ *
+ *
+ *
+ *
+ */
+UINT8 MaxRegister[] =
+{
+  MSG_REG9,
+  MSG_REGB,
+  MSG_REG9,
+  MSG_REGA,
+};
+
+/*-------------------------------------------------------------------------------
+;Procedure:  IsZoneFuncEnable
+;
+;Description:  This routine will check every zone support function with BitMap from user define
+;
+;
+;Exit:  None
+;
+;Modified:  None
+;
+;-----------------------------------------------------------------------------
+*/
+STATIC BOOLEAN
+IsZoneFuncEnable (
+  IN     UINT16 Flag,
+  IN     UINT8  func,
+  IN     UINT8  Zone
+  )
+{
+  return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
+}
+
+/*-------------------------------------------------------------------------------
+;Procedure:  FchECfancontrolservice
+;
+;Description:  This routine service EC fan policy
+;
+;
+;Exit:  None
+;
+;Modified:  None
+;
+;-----------------------------------------------------------------------------
+*/
+VOID
+FchECfancontrolservice (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        ZoneNum;
+  UINT8        FunNum;
+  UINT8        RegNum;
+  UINT8        *CurPoint;
+  UINT8        FunIndex;
+  BOOLEAN      IsSendEcMsg;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if (!IsImcEnabled (StdHeader)) {
+    return;                                                    //IMC is not enabled
+  }
+
+  CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
+
+  for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
+    FunNum = FunctionNumber[FunIndex];
+    for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+      IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+      if (IsSendEcMsg) {
+        for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+          WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
+          CurPoint += 1;
+        }
+        WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader);     // function number
+        WaitForEcLDN9MailboxCmdAck (StdHeader);
+      } else {
+        CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
+      }
+    }
+  }
+
+  CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0;
+  for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
+    FunNum = FunctionNumber[FunIndex];
+    for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+      IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+      if (IsSendEcMsg) {
+        for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+          if (RegNum == MSG_REG2) {
+            *CurPoint &= 0xFE;
+          }
+          WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
+          CurPoint += 1;
+        }
+        WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader);      // function number
+        WaitForEcLDN9MailboxCmdAck (StdHeader);
+      } else {
+        CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
new file mode 100644
index 0000000000..71f883a309
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
@@ -0,0 +1,275 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE
+
+/**
+ * hwmFchtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmFchtsiAutoPolling (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        ValueByte;
+  UINT16       SmbusBase;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress);
+
+  if (LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), BIT2);
+    ValueByte = 0xff;
+    LibAmdIoWrite (AccessWidth8, SmbusBase, &ValueByte, StdHeader);
+    ValueByte = 0x08;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
+    ValueByte = 0x09;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader);
+    ValueByte = 0x98;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader);
+    ValueByte = 0x20;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 5, &ValueByte, StdHeader);
+    ValueByte = 0x48;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
+
+    LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader);
+    while ( ValueByte & BIT0 ) {
+      LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader);
+    }
+
+    ValueByte = 0x08;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
+    ValueByte = 0x10;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader);
+    ValueByte = 0x99;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader);
+
+    ValueByte = 0x80;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
+    ValueByte = 0x01;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 0x17, &ValueByte, StdHeader);
+    ValueByte = 0x81;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
+
+    //
+    //map SB-TSI to tempin0
+    //
+    RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, (UINT32)~BIT3, BIT3);
+  } else {
+    HwmFchtsiAutoPollingOff (LocalCfgPtr);
+  }
+}
+
+/**
+ * HwmFchtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI
+ * Off.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmFchtsiAutoPollingOff (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        ValueByte;
+  UINT16       SmbusBase;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
+    SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress);
+    ValueByte = 0x00;
+    LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0);
+    RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, (UINT32)~BIT3, 0x00);
+  }
+}
+
+/**
+ * HwmGetRawData - Hardware Monitor Get Raw Data.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmGetRawData (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Index;
+  UINT16       ValueWord;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //fan speed
+  //
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    ReadPmio2 (FCH_PMIO2_REG69 + Index * 5, AccessWidth16, &ValueWord, StdHeader);
+    if ( (ValueWord & 0xFFC0) != 0xFFC0 ) {
+      LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index] = ValueWord;
+    }
+  }
+  //
+  //temperatue
+  //
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    ReadPmio2 (FCH_PMIO2_REG95 + Index * 4, AccessWidth16, &ValueWord, StdHeader);
+    if ( ( Index == 1 ) || (ValueWord > 0x4000) ) {
+      LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index] = ValueWord;
+    }
+  }
+  //
+  //voltage
+  //
+  for ( Index = 0; Index < 8 ; Index++ ) {
+    ReadPmio2 (FCH_PMIO2_REGB8 + Index * 4, AccessWidth16, &ValueWord, StdHeader);
+    if ( (ValueWord & 0xFFC0) != 0xFFC0 ) {
+      LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index] = ValueWord;
+    }
+  }
+}
+
+/**
+ * HwmCaculate - Hardware Monitor Caculate Raw Data to Display Data.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+HwmCaculate (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Index;
+  UINT16       ValueWord;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  //
+  //fan speed
+  //
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index];
+    if ((ValueWord == 0xffff) || (ValueWord == 0x0000)) {
+      LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = 0;
+    } else {
+      LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = ( 22720 >> LocalCfgPtr->Hwm.FanSampleFreqDiv ) * 60 / ValueWord / 2;
+    }
+  }
+  //
+  //temperatue
+  //
+  for ( Index = 0; Index < 5 ; Index++ ) {
+    ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index];
+    if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 1)) {
+      ValueWord = ((ValueWord & 0xff00) >> 8) * 10 + (((ValueWord & 0x00ff) * 10 ) >> 8);
+    } else {
+      ValueWord = ((ValueWord << 3) * LocalCfgPtr->Hwm.HwmTempPar[Index].At / LocalCfgPtr->Hwm.HwmCalibrationFactor / 100 - LocalCfgPtr->Hwm.HwmTempPar[Index].Ct) / 100  ;
+    }
+    if ( LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] == 0 ) {
+      ValueWord = 0;
+    }
+    if ( ValueWord < 10000 ) {
+      LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = ValueWord;
+    } else {
+      LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = 0;
+    }
+  }
+  //
+  //voltage
+  //
+  for ( Index = 0; Index < 8 ; Index++ ) {
+    ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index];
+    LocalCfgPtr->Hwm.HwmCurrent.Voltage[Index] = (ValueWord >> 6) * 512 / LocalCfgPtr->Hwm.HwmCalibrationFactor;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c
new file mode 100644
index 0000000000..c6704483e4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_HWMENV_FILECODE
+
+/**
+ * FchInitEnvHwm - Config Hwm controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvHwm (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c
new file mode 100644
index 0000000000..c63efc4912
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_HWMLATE_FILECODE
+
+
+
+/**
+ * FchInitLateHwm - Prepare Hwm controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateHwm (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  ImcWakeup (LocalCfgPtr);
+  if (( LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == FALSE ) && ( LocalCfgPtr->Hwm.HwMonitorEnable )) {
+    FchECfancontrolservice (LocalCfgPtr);
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmMid.c
new file mode 100644
index 0000000000..59f25ac611
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmMid.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_HWMMID_FILECODE
+
+/**
+ * FchInitMidHwm - Config Hwm controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidHwm (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c
new file mode 100644
index 0000000000..71f5ea3a96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_HWMRESET_FILECODE
+
+/**
+ * FchInitResetHwm - Config Hwm controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetHwm (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c
new file mode 100644
index 0000000000..6d0f3a4d54
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch IDE controller
+ *
+ * Init IDE Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IDE_IDEENV_FILECODE
+
+/**
+ * FchInitEnvIde - Config Ide controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvIde (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Channel;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, 0xff, BIT0, StdHeader);
+
+  //
+  // Enabling IDE Explicit Pre-Fetch  IDE PCI Config 0x62[8]=0
+  //
+  RwPci (((IDE_BUS_DEV_FUN << 16) + 0x62  + 1), AccessWidth8,  (UINT32)~BIT0, BIT5, StdHeader);
+
+  //
+  // Disable SATA MSI
+  //
+  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG34), AccessWidth8, 0x00, 0x00, StdHeader);
+  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG06), AccessWidth8, 0xEF, 0x00, StdHeader);
+
+  //
+  // Set Ide Channel enable/disable by parameter
+  //
+  ReadPci (((IDE_BUS_DEV_FUN << 16) + 0x040  + 11), AccessWidth8, &Channel, StdHeader);
+  Channel &= 0xCF;
+  if ( LocalCfgPtr->Sata.IdeDisUnusedIdePChannel ) {
+    Channel |= 0x10;
+  }
+  if ( LocalCfgPtr->Sata.IdeDisUnusedIdeSChannel ) {
+    Channel |= 0x20;
+  }
+  WritePci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40 + 11), AccessWidth8, &Channel, StdHeader);
+
+  //
+  // IDE Controller Class ID & SSID
+  // ** Get Sata Configuration ** for sync Sata & Ide with only one Legacy Ide device
+  //
+  if ( (LocalCfgPtr->Sata.SataIdeMode == 1) && (LocalCfgPtr->Sata.SataClass != SataLegacyIde) ) {
+    //
+    // Write the class code to IDE PCI register 08h-0Bh
+    //
+    RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
+  }
+  if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
+    //
+    //Set SATA controller to native mode
+    //
+    RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG09), AccessWidth8, 0x00, 0x08F, StdHeader);
+  }
+  if (LocalCfgPtr->Ide.IdeSsid != 0 ) {
+    RwPci ((IDE_BUS_DEV_FUN << 16) + 0x2C , AccessWidth32, 0x00, LocalCfgPtr->Ide.IdeSsid, StdHeader);
+  }
+
+  //
+  // Disable write access to PCI header
+  //
+  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, (UINT32)~BIT0, 0, StdHeader);
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c
new file mode 100644
index 0000000000..a60abaa77a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch IDE controller
+ *
+ * Init IDE Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IDE_IDELATE_FILECODE
+/**
+ * FchInitLateIde - Prepare IDE controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateIde (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c
new file mode 100644
index 0000000000..4b9085c97d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch IDE controller
+ *
+ * Init IDE Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IDE_IDEMID_FILECODE
+
+/**
+ * FchInitMidIde - Config IDE controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidIde (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
new file mode 100644
index 0000000000..4920372b92
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
@@ -0,0 +1,153 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Imc controller
+ *
+ * Init Imc Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE
+
+//
+// Declaration of local functions
+//
+
+
+/**
+ * SoftwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SoftwareToggleImcStrapping (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8    ValueByte;
+  UINT8    PortStatusByte;
+  UINT32   AbValue;
+  UINT32   ABStrapOverrideReg;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+  GetChipSysMode (&PortStatusByte, StdHeader);
+
+  ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
+
+  //
+  //if ( (ValueByte & (BIT6 + BIT7)) != 0xC0 ) {  // PwrGoodOut =1, PwrGoodEnB=1
+  //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
+  //
+  //StrapStatus                               StrapOverride
+  //   bit4                                            bit17
+  //   bit6                                            bit12
+  //   bit12                                           bit15
+  //   bit15                                           bit16
+  //   bit16                                           bit18
+  //
+  ReadMem ((ACPI_MMIO_BASE + MISC_BASE + 0x80 ), AccessWidth32, &AbValue);
+  ABStrapOverrideReg = AbValue;
+
+  if (AbValue & BIT4) {
+    ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT4) | BIT17;
+  }
+
+  if (AbValue & BIT6) {
+    ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT6) | BIT12;
+  }
+
+  if (AbValue & BIT12) {
+    ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT12) | BIT15;
+  }
+
+  if (AbValue & BIT15) {
+    ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT15) | BIT16;
+  }
+
+  if (AbValue & BIT16) {
+    ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT16) | BIT18;
+  }
+
+  ABStrapOverrideReg |= BIT31;                             /// Overwrite enable
+
+  if ((PortStatusByte & ChipSysEcEnable) == 0) {
+    ABStrapOverrideReg |= BIT2;                            /// bit2- EcEnableStrap
+  } else {
+    ABStrapOverrideReg &= ~BIT2;                           /// bit2=0 EcEnableStrap
+  }
+
+  WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84 ), AccessWidth32, &ABStrapOverrideReg);
+  ValueByte |= (BIT6 + BIT7);                    /// PwrGoodOut =1, PwrGoodEnB=1
+  WritePmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
+
+  ValueByte = 06;
+  LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
+  FchStall (0xffffffff, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c
new file mode 100644
index 0000000000..ee5d1cbd1e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c
@@ -0,0 +1,212 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Embedded Controller
+ *
+ * Init Ec Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_FCHECENV_FILECODE
+
+
+/**
+ * FchInitEnvEc - Config Ec controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvEc (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * EnterEcConfig - Force EC into Config mode
+ *
+ *
+ *
+ *
+ */
+VOID
+EnterEcConfig (
+  IN AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT16   EcIndexPortDword;
+  UINT8    FchEcData8;
+
+  ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
+  EcIndexPortDword &= ~(BIT0);
+  FchEcData8 = 0x5A;
+  LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ExitEcConfig - Force EC exit Config mode
+ *
+ *
+ *
+ *
+ */
+VOID
+ExitEcConfig (
+  IN AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT16   EcIndexPortDword;
+  UINT8    FchEcData8;
+
+  ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
+  EcIndexPortDword &= ~(BIT0);
+  FchEcData8 = 0xA5;
+  LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ReadEc8 - Read EC register data
+ *
+ *
+ *
+ * @param[in] Address  - EC Register Offset Value
+ * @param[in] Value    - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadEc8 (
+  IN  UINT8     Address,
+  IN  UINT8     *Value,
+  IN AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT16   EcIndexPortDword;
+
+  ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
+  EcIndexPortDword &= ~(BIT0);
+  LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
+  LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RwEc8 - Read/Write EC register
+ *
+ *
+ *
+ * @param[in] Address    - EC Register Offset Value
+ * @param[in] AndMask    - Data And Mask 8 bits
+ * @param[in] OrMask     - Data OR Mask 8 bits
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RwEc8 (
+  IN  UINT8     Address,
+  IN  UINT8     AndMask,
+  IN  UINT8     OrMask,
+  IN AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8   Result;
+
+  ReadEc8 (Address, &Result, StdHeader);
+  Result = (Result & AndMask) | OrMask;
+  WriteEc8 (Address, &Result, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * WriteEc8 - Write date into EC register
+ *
+ *
+ *
+ * @param[in] Address  - EC Register Offset Value
+ * @param[in] Value    - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WriteEc8 (
+  IN  UINT8     Address,
+  IN  UINT8     *Value,
+  IN AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT16   EcIndexPortDword;
+
+  ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
+  EcIndexPortDword &= ~(BIT0);
+  LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
+  LibAmdIoWrite (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c
new file mode 100644
index 0000000000..2ecf1cb7b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Embedded Controller
+ *
+ * Init Ec Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_FCHECLATE_FILECODE
+
+/**
+ * FchInitLateEc - Prepare Ec controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateEc (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcMid.c
new file mode 100644
index 0000000000..ce865f10f1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcMid.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Embedded Controller
+ *
+ * Init Ec Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_FCHECMID_FILECODE
+
+/**
+ * FchInitMidIde - Config Ec controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidEc (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c
new file mode 100644
index 0000000000..db43b3d190
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c
@@ -0,0 +1,143 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ec controller
+ *
+ * Init Ec Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_FCHECRESET_FILECODE
+
+/**
+ * FchInitResetEc - Config Ec controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetEc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //Enable config mode
+  //
+  EnterEcConfig (StdHeader);
+
+  //
+  //Do settings for mailbox - logical device 0x09
+  //
+  RwEc8 (0x07, 0x00, 0x09, StdHeader);                      ///switch to device 9 (Mailbox)
+  RwEc8 (0x60, 0x00, (MailBoxPort >> 8), StdHeader);        ///set MSB of Mailbox port
+  RwEc8 (0x61, 0x00, (MailBoxPort & 0xFF), StdHeader);      ///set LSB of Mailbox port
+  RwEc8 (0x30, 0x00, 0x01, StdHeader);                      ///;Enable Mailbox Registers Interface, bit0=1
+
+  if ( LocalCfgPtr->EcKbd == ENABLED) {
+    //
+    //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
+    //
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6, AccessWidth8, (UINT32)~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
+
+    //
+    //Disable LPC Decoding of port 60/64
+    //
+    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG47), AccessWidth8, (UINT32)~BIT5, 0, StdHeader);
+
+    //
+    //Enable logical device 0x07 (Keyboard controller)
+    //
+    RwEc8 (0x07, 0x00, 0x07, StdHeader);
+    RwEc8 (0x30, 0x00, 0x01, StdHeader);
+  }
+
+  if (IsImcEnabled (StdHeader) && ( LocalCfgPtr->EcChannel0 == ENABLED)) {
+    //
+    //Logical device 0x03
+    //
+    RwEc8 (0x07, 0x00, 0x03, StdHeader);
+    RwEc8 (0x60, 0x00, 0x00, StdHeader);
+    RwEc8 (0x61, 0x00, 0x62, StdHeader);
+    RwEc8 (0x30, 0x00, 0x01, StdHeader);                    ///;Enable Device 3
+  }
+
+  //
+  //Enable EC (IMC) to generate SMI to BIOS
+  //
+  RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB3, AccessWidth8, (UINT32)~BIT6, BIT6);
+  ExitEcConfig (StdHeader);
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c
new file mode 100644
index 0000000000..4bc73bbb40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c
@@ -0,0 +1,179 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Imc controller
+ *
+ * Init Imc Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_IMCENV_FILECODE
+
+
+
+//
+// Declaration of local functions
+//
+
+
+/**
+ * FchInitEnvImc - Config Imc controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvImc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        PortStatusByte;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  GetChipSysMode (&PortStatusByte, LocalCfgPtr->StdHeader);
+
+  //
+  // Software IMC enable
+  //
+  if (((LocalCfgPtr->Imc.ImcEnableOverWrite == 1) && ((PortStatusByte & ChipSysEcEnable) == 0)) || ((LocalCfgPtr->Imc.ImcEnableOverWrite == 2) && ((PortStatusByte & ChipSysEcEnable) == ChipSysEcEnable))) {
+    if (ValidateImcFirmware (LocalCfgPtr)) {
+      SoftwareToggleImcStrapping (LocalCfgPtr);
+    }
+  }
+
+  FchInitEnvEc (LocalCfgPtr);
+}
+
+/**
+ * ValidateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ * @retval        TRUE   Pass
+ * @retval        FALSE  Failed
+ */
+BOOLEAN
+ValidateImcFirmware (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32   ImcSig;
+  UINT32   ImcSigAddr;
+  UINT32   ImcAddr;
+  UINT32   CurAddr;
+  UINT32   ImcBinSig0;
+  UINT32   ImcBinSig1;
+  UINT16   ImcBinSig2;
+  UINT8    IMCChecksumeByte;
+  UINT8    IMCByte;
+
+  ImcAddr = 0;
+
+  //
+  // Software IMC enable
+  //
+  ImcSigAddr = 0x80000;                          /// start from 512k to 64M
+  ImcSig = 0x0;
+
+  while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
+    CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
+    ReadMem (CurAddr, AccessWidth32, &ImcSig);
+    ReadMem ((CurAddr + 4), AccessWidth32, &ImcAddr);
+    ImcSigAddr <<= 1;
+  }
+
+  IMCChecksumeByte = 0xff;
+
+  if ( ImcSig == 0x55aa55aa ) {
+    //
+    // "_AMD_IMC_C" at offset 0x2000 of the binary
+    //
+    ReadMem ((ImcAddr + 0x2000), AccessWidth32, &ImcBinSig0);
+    ReadMem ((ImcAddr + 0x2004), AccessWidth32, &ImcBinSig1);
+    ReadMem ((ImcAddr + 0x2008), AccessWidth16, &ImcBinSig2);
+
+    if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
+      IMCChecksumeByte = 0;
+
+      for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
+        ReadMem (CurAddr, AccessWidth8, &IMCByte);
+        IMCChecksumeByte = IMCChecksumeByte + IMCByte;
+      }
+    }
+  }
+
+  if ( IMCChecksumeByte ) {
+    return  FALSE;
+  } else {
+    return  TRUE;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c
new file mode 100644
index 0000000000..43f8669485
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c
@@ -0,0 +1,108 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Imc controller
+ *
+ * Init Imc Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_IMCLATE_FILECODE
+
+/**
+ * FchInitLateImc - Prepare Imc controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateImc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitLateEc (FchDataPtr);
+}
+
+/**
+ * ImcDisarmSurebootTimer - IMC Disarm Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcDisarmSurebootTimer (
+  IN VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  ImcDisableSurebootTimer (LocalCfgPtr);
+  LocalCfgPtr->Imc.ImcSureBootTimer = 0;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c
new file mode 100644
index 0000000000..6f8903c487
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c
@@ -0,0 +1,312 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH IMC lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_IMCLIB_FILECODE
+
+VOID
+WriteECmsg (
+  IN       UINT8     Address,
+  IN       UINT8     OpFlag,
+  IN       VOID      *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   Index;
+
+  OpFlag = OpFlag & 0x7f;
+  if (OpFlag == 0x02) {
+    OpFlag = 0x03;
+  }
+
+  for (Index = 0; Index <= OpFlag; Index++) {
+    /// EC_LDN9_MAILBOX_BASE_ADDRESS
+    LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
+    Address++;
+    /// EC_LDN9_MAILBOX_BASE_ADDRESS
+    LibAmdIoWrite (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
+  }
+}
+
+VOID
+ReadECmsg (
+  IN       UINT8     Address,
+  IN       UINT8     OpFlag,
+     OUT   VOID      *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 Index;
+
+  OpFlag = OpFlag & 0x7f;
+  if (OpFlag == 0x02) {
+    OpFlag = 0x03;
+  }
+
+  for (Index = 0; Index <= OpFlag; Index++) {
+    /// EC_LDN9_MAILBOX_BASE_ADDRESS
+    LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
+    Address++;
+    /// EC_LDN9_MAILBOX_BASE_ADDRESS
+    LibAmdIoRead (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
+  }
+}
+
+VOID
+WaitForEcLDN9MailboxCmdAck (
+  IN AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8    Msgdata;
+  UINT16   Delaytime;
+
+  Msgdata = 0;
+
+  for (Delaytime = 0; Delaytime <= 100000; Delaytime++) {
+    ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+    if ( Msgdata == 0xfa) {
+      break;
+    }
+
+    FchStall (5, StdHeader);                            /// Wait for 1ms
+  }
+}
+
+/**
+ * ImcSleep - IMC Sleep.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcSleep (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Msgdata;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if (!(IsImcEnabled (StdHeader)) ) {
+    return;                                                ///IMC is not enabled
+  }
+
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0xB4;
+  WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x96;
+  WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+  WaitForEcLDN9MailboxCmdAck (StdHeader);
+}
+
+
+/**
+ * ImcEnableSurebootTimer - IMC Enable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcEnableSurebootTimer (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                  Msgdata;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  ImcDisableSurebootTimer (LocalCfgPtr);
+
+  Msgdata = 0x00;
+
+  if (!(IsImcEnabled (StdHeader)) || (LocalCfgPtr->Imc.ImcSureBootTimer == 0)) {
+    return;                                      ///IMC is not enabled
+  }
+
+  ImcWakeup (FchDataPtr);
+  WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x01;
+  WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = ( (LocalCfgPtr->Imc.ImcSureBootTimer) << 6) -1;
+  WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x94;
+  WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+  WaitForEcLDN9MailboxCmdAck (StdHeader);
+  ImcSleep (FchDataPtr);
+}
+
+/**
+ * ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcDisableSurebootTimer (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8   Msgdata;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+
+  if (!(IsImcEnabled (StdHeader)) ) {
+    return;                                      ///IMC is not enabled
+  }
+
+  ImcWakeup (FchDataPtr);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x01;
+  WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x94;
+  WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+  WaitForEcLDN9MailboxCmdAck (StdHeader);
+  ImcSleep (FchDataPtr);
+}
+
+/**
+ * ImcWakeup - IMC Wakeup.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcWakeup (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8   Msgdata;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+  if (!(IsImcEnabled (StdHeader)) ) {
+    return;                                      ///IMC is not enabled
+  }
+
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0xB5;
+  WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x96;
+  WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+  WaitForEcLDN9MailboxCmdAck (StdHeader);
+}
+
+/**
+ * ImcIdle - IMC Idle.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcIdle (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8   Msgdata;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+
+  if (!(IsImcEnabled (StdHeader)) ) {
+    return;                                      ///IMC is not enabled
+  }
+
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x01;
+  WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+  Msgdata = 0x98;
+  WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+  WaitForEcLDN9MailboxCmdAck (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcMid.c
new file mode 100644
index 0000000000..78d9a975fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcMid.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Imc controller
+ *
+ * Init Imc Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63441 $   @e \$Date: 2011-12-22 17:18:09 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_IMCMID_FILECODE
+
+/**
+ * FchInitMidImc - Config Imc controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidImc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitMidEc (FchDataPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c
new file mode 100644
index 0000000000..4c851e400b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Imc controller
+ *
+ * Init Imc Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IMC_IMCRESET_FILECODE
+
+/**
+ * FchInitResetImc - Config Imc controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetImc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                     PortStatusByte;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
+  GetChipSysMode (&PortStatusByte, StdHeader);
+
+  if ( ((PortStatusByte & ChipSysEcEnable) == 0x00) ) {
+    //
+    // EC is disabled by jumper setting or board config
+    //
+    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4), AccessWidth16, 0xFFFE, BIT0, StdHeader);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xF7, 0x08);
+    FchInitResetEc (FchDataPtr);
+    // ecPowerOnInit ( FchDataPtr);
+    ImcSleep (FchDataPtr);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
new file mode 100644
index 0000000000..f9c29d9789
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
@@ -0,0 +1,377 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics Controller family specific service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "FchPlatform.h"
+#include  "Filecode.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * Default FCH interface settings at InitEnv phase.
+ *----------------------------------------------------------------------------------------
+ */
+CONST FCH_INTERFACE ROMDATA FchInterfaceDefault = {
+  SdAmda,              // SdConfig
+  hdaconf2 ,            // AzaliaControl
+  IrRxTx0Tx1,          // IrConfig
+  TRUE,                // UmiGen2
+  SataAhci,            // SataClass
+  TRUE,                // SataEnable
+  TRUE,                // IdeEnable
+  TRUE,                // SataIdeMode
+  TRUE,                // Ohci1Enable
+  TRUE,                // Ohci2Enable
+  TRUE,                // Ohci3Enable
+  TRUE,                // Ohci4Enable
+  TRUE,                // XhciSwitch
+  TRUE,                // GppEnable
+  AlwaysOff            // FchPowerFail
+};
+
+
+/*----------------------------------------------------------------
+ *  InitEnv Phase Data Block Default (Failsafe)
+ *----------------------------------------------------------------
+ */
+FCH_DATA_BLOCK   InitEnvCfgDefault = {
+  NULL,                      // StdHeader
+
+  {                          // FCH_ACPI
+    0xB00,                   // Smbus0BaseAddress
+    0xB20,                   // Smbus1BaseAddress
+    0xE00,                   // SioPmeBaseAddress
+    0xFEC000F0,              // WatchDogTimerBase
+    0x800,                   // AcpiPm1EvtBlkAddr
+    0x804,                   // AcpiPm1CntBlkAddr
+    0x808,                   // AcpiPmTmrBlkAddr
+    0x810,                   // CpuControlBlkAddr
+    0x820,                   // AcpiGpe0BlkAddr
+    0x00B0,                  // SmiCmdPortAddr
+    0xFE00,                  // AcpiPmaCntBlkAddr
+    TRUE,                    // AnyHt200MhzLink
+    TRUE,                    // SpreadSpectrum
+    AlwaysOff,             // PwrFailShadow
+    0,                       // StressResetMode
+    FALSE,                   // MtC1eEnable
+    NULL                     // OemProgrammingTablePtr
+  },
+
+  {                          // FCH_AB
+    FALSE,                   // AbMsiEnable
+    0,                       // ALinkClkGateOff
+    0,                       // BLinkClkGateOff
+    0,                       // AbClockGating
+    0,                       // GppClockGating
+    0,                       // UmiL1TimerOverride
+    0,                       // UmiLinkWidth
+    0,                       // UmiDynamicSpeedChange
+    0,                       // PcieRefClockOverClocking
+    0,                       // UmiGppTxDriverStrength
+    TRUE,                    // NbSbGen2
+    0,                       // FchPcieOrderRule
+    0,                       // SlowSpeedAbLinkClock
+    0,                       // ResetCpuOnSyncFlood
+    FALSE,                   // AbDmaMemoryWrtie3264B
+    FALSE,                   // AbMemoryPowerSaving
+    FALSE,                   // SbgDmaMemoryWrtie3264ByteCount
+    FALSE                    // SbgMemoryPowerSaving
+  },
+
+  {{{0}}},                       // FCH_GPP
+
+  {                          // FCH_USB
+    TRUE,                    // Ohci1Enable
+    TRUE,                    // Ohci2Enable
+    TRUE,                    // Ohci3Enable
+    TRUE,                    // Ohci4Enable
+    TRUE,                    // Ehci1Enable
+    TRUE,                    // Ehci2Enable
+    TRUE,                    // Ehci3Enable
+    TRUE,                    // Xhci0Enable
+    TRUE,                    // Xhci1Enable
+    FALSE,                   // UsbMsiEnable
+    0,                       // OhciSsid
+    0,                       // Ohci4Ssid
+    0,                       // EhciSsid
+    0,                       // XhciSsid
+    FALSE,                   // UsbPhyPowerDown
+    0                        // UserDefineXhciRomAddr
+  },
+
+  {                          // FCH_SATA
+    FALSE,                   // SataMsiEnable
+    0x00000000,              // SataIdeSsid
+    0x00000000,              // SataRaidSsid
+    0x00000000,              // SataRaid5Ssid
+    0x00000000,              // SataAhciSsid
+    {                        // SATA_ST
+      0,                     // SataModeReg
+      TRUE,                  // SataEnable
+      0,                     // Sata6AhciCap
+      FALSE,                  // SataSetMaxGen2
+      TRUE,                  // IdeEnable
+      9,                     // SataClkMode
+    },
+    SataAhci,           // SataClass
+    1,                       // SataIdeMode
+    0,                       // SataDisUnusedIdePChannel
+    0,                       // SataDisUnusedIdeSChannel
+    0,                       // IdeDisUnusedIdePChannel
+    0,                       // IdeDisUnusedIdeSChannel
+    0,                       // SataOptionReserved
+    {                        // SATA_PORT_ST
+      0,                     // SataPortReg
+      FALSE,                  // Port0
+      FALSE,                  // Port1
+      FALSE,                  // Port2
+      FALSE,                  // Port3
+      FALSE,                  // Port4
+      FALSE,                  // Port5
+      FALSE,                  // Port6
+      FALSE,                  // Port7
+    },
+    {                        // SATA_PORT_ST
+      0,                     // SataPortReg
+      FALSE,                 // Port0
+      FALSE,                 // Port1
+      FALSE,                 // Port2
+      FALSE,                 // Port3
+      FALSE,                 // Port4
+      FALSE,                 // Port5
+      FALSE,                 // Port6
+      FALSE,                 // Port7
+    },
+    {                        // SATA_PORT_MD
+      0,                     // SataPortMode
+      0,                     // Port0
+      0,                     // Port1
+      0,                     // Port2
+      0,                     // Port3
+      0,                     // Port4
+      0,                     // Port5
+      0,                     // Port6
+      0,                     // Port7
+    },
+    0,                       // SataAggrLinkPmCap
+    0,                       // SataPortMultCap
+    0,                       // SataClkAutoOff
+    0,                       // SataPscCap
+    0,                       // BiosOsHandOff
+    0,                       // SataFisBasedSwitching
+    0,                       // SataCccSupport
+    0,                       // SataSscCap
+    0,                       // SataMsiCapability
+    0,                       // SataForceRaid
+    0,                       // SataInternal100Spread
+    0,                       // SataDebugDummy
+    0,                       // SataTargetSupport8Device
+    0,                       // SataDisableGenericMode
+    FALSE,                   // SataAhciEnclosureManagement
+    0,                       // SataSgpio0
+    0,                       // SataSgpio1
+    0,                       // SataPhyPllShutDown
+    TRUE,                    // SataHotRemovalEnh
+    {                        // SATA_PORT_ST
+      0,                     // SataPortReg
+      FALSE,                 // Port0
+      FALSE,                 // Port1
+      FALSE,                 // Port2
+      FALSE,                 // Port3
+      FALSE,                 // Port4
+      FALSE,                 // Port5
+      FALSE,                 // Port6
+      FALSE,                 // Port7
+    },
+    0                        // TempMmio
+  },
+
+  {                          // FCH_SMBUS
+    0x00000000               // SmbusSsid
+  },
+
+  {                          // FCH_IDE
+    TRUE,                    // IdeEnable
+    FALSE,                   // IdeMsiEnable
+    0x00000000               // IdeSsid
+  },
+
+  {                          // FCH_AZALIA
+    hdaconf2,               // AzaliaEnable
+    FALSE,                   // AzaliaMsiEnable
+    0x00000000,              // AzaliaSsid
+    1,                       // AzaliaPinCfg
+    0,                       // AzaliaFrontPanel
+    0,                       // FrontPanelDetected
+    0,                       // AzaliaSnoop
+    0,                       // AzaliaDummy
+    {                        // AZALIA_PIN
+      2,                     // AzaliaSdin0
+      2,                     // AzaliaSdin1
+      2,                     // AzaliaSdin2
+      2,                     // AzaliaSdin3
+    },
+    NULL,                    // *AzaliaOemCodecTablePtr
+    NULL,                    // *AzaliaOemFpCodecTablePtr
+  },
+
+  {                          // FCH_SPI
+    FALSE,                   // LpcMsiEnable
+    0x00000000,              // LpcSsid
+    0,                       // RomBaseAddress
+    0,                       // Speed
+    0,                       // FastSpeed
+    0,                       // WriteSpeed
+    0,                       // Mode
+    0,                       // AutoMode
+    0,                       // BurstWrite
+  },
+
+  {                          // FCH_PCIB
+    FALSE,                   // PcibMsiEnable
+    0x00000000,              // PcibSsid
+    0x0F,                    // PciClks
+    0,                       // PcibClkStopOverride
+    FALSE,                   // PcibClockRun
+  },
+
+  {                          // FCH_GEC
+    FALSE,                   // GecEnable
+    0,                       // GecPhyStatus
+    0,                       // GecPowerPolicy
+    0,                       // GecDebugBus
+    0xFED61000,              // GecShadowRomBase
+    NULL,                    // *PtrDynamicGecRomAddress
+  },
+
+  {                          // FCH_SD
+    SdAmda,               // SdConfig
+    0,                       // Speed
+    0,                       // BitWidth
+    0x00000000,              // SdSsid
+    Sd50MhzTraceCableLengthWithinSixInches,   // SdClockControl
+    FALSE,
+    0,
+    0
+  },
+
+  {0},                       // FCH_HWM
+
+  {0,                        // FCH_IR
+   0x23,                     // IrPinControl
+  },
+
+  {                          // FCH_HPET
+    TRUE,                    // HpetEnable
+    TRUE,                    // HpetMsiDis
+    0xFED00000               // HpetBase
+  },
+
+  {                          // FCH_GCPU
+    0,                       // AcDcMsg
+    0,                       // TimerTickTrack
+    0,                       // ClockInterruptTag
+    0,                       // OhciTrafficHanding
+    0,                       // EhciTrafficHanding
+    0,                       // GcpuMsgCMultiCore
+    0,                       // GcpuMsgCStage
+  },
+
+  {0},                       // FCH_IMC
+
+  {                          // FCH_MISC
+    FALSE,                   // NativePcieSupport
+    FALSE,                   // S3Resume
+    FALSE,                   // RebootRequired
+    0,                       // FchVariant
+    0,                       // CG2PLL
+    {                        // TIMER_SMI-LongTimer
+      FALSE,                 // Enable
+      FALSE,                 // StartNow
+      1000                   // CycleDuration
+    },
+    {                        // TIMER_SMI-ShortTimer
+      FALSE,                 // Enable
+      FALSE,                 // StartNow
+      0x7FFF                 // CycleDuration
+    }
+  }
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
new file mode 100644
index 0000000000..37e7a42ff6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
@@ -0,0 +1,185 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics Controller family specific service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "FchPlatform.h"
+#include  "Filecode.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ * Default FCH interface settings at InitReset phase.
+ *----------------------------------------------------------------------------------------
+ */
+CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = {
+  TRUE,                // UmiGen2
+  TRUE,                // SataEnable
+  TRUE,                // IdeEnable
+  TRUE,                // GppEnable
+  TRUE,                // Xhci0Enable
+  TRUE                 // Xhci1Enable
+};
+
+
+/*----------------------------------------------------------------
+ *  InitReset Phase Data Block Default (Failsafe)
+ *----------------------------------------------------------------
+ */
+FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
+  NULL,                  // StdHeader
+  {0},                   // FchReset
+
+  0,                     // FastSpeed
+  0,                     // WriteSpeed
+  0,                     // Mode
+  0,                     // AutoMode
+  0,                     // BurstWrite
+  FALSE,                 // SataIdeCombMdPriSecOpt
+  0,                     // Cg2Pll
+  FALSE,                 // EcKbd
+  FALSE,                 // LegacyFree
+  FALSE,                 // SataSetMaxGen2
+  9,                     // SataClkMode
+  0,                     // SataModeReg
+  FALSE,                 // SataInternal100Spread
+  2,                     // SpiSpeed
+  FALSE,                 // EcChannel0
+
+  {                      // FCH_GPP
+    {                    // Array of FCH_GPP_PORT_CONFIG       PortCfg[4]
+      {
+        FALSE,           // PortPresent
+        FALSE,           // PortDetected
+        FALSE,           // PortIsGen2
+        FALSE,           // PortHotPlug
+        0,               // PortMisc
+      },
+      {
+        FALSE,           // PortPresent
+        FALSE,           // PortDetected
+        FALSE,           // PortIsGen2
+        FALSE,           // PortHotPlug
+        0,               // PortMisc
+      },
+      {
+        FALSE,           // PortPresent
+        FALSE,           // PortDetected
+        FALSE,           // PortIsGen2
+        FALSE,           // PortHotPlug
+        0,               // PortMisc
+      },
+      {
+        FALSE,           // PortPresent
+        FALSE,           // PortDetected
+        FALSE,           // PortIsGen2
+        FALSE,           // PortHotPlug
+        0,               // PortMisc
+      },
+    },
+    PortA1B1C1D1,        // GppLinkConfig
+    FALSE,               // GppFunctionEnable
+    FALSE,               // GppToggleReset
+    0,                   // GppHotPlugGeventNum
+    0,                   // GppFoundGfxDev
+    FALSE,               // GppGen2
+    0,                   // GppGen2Strap
+    FALSE,               // GppMemWrImprove
+    FALSE,               // GppUnhidePorts
+    0,                   // GppPortAspm
+    FALSE,               // GppLaneReversal
+    TRUE,                // GppPhyPllPowerDown
+    TRUE ,               // GppDynamicPowerSaving
+    FALSE,               // PcieAer
+    FALSE,               // PcieRas
+    FALSE,               // PcieCompliance
+    FALSE,               // PcieSoftwareDownGrade
+    TRUE,                // UmiPhyPllPowerDown
+    FALSE,               // SerialDebugBusEnable
+    0,                   // GppHardwareDownGrade
+    0,                   // GppL1ImmediateAck
+    TRUE,                // NewGppAlgorithm
+    0,                   // HotPlugPortsStatus
+    0,                   // FailPortsStatus
+    40,                  // GppPortMinPollingTime
+  },
+  NULL                   // OemResetProgrammingTablePtr
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
new file mode 100644
index 0000000000..2929a8a292
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
@@ -0,0 +1,142 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "FchTaskLauncher.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_INTERFACE_FCHINITENV_FILECODE
+
+extern FCH_TASK_ENTRY    *FchInitEnvTaskTable[];
+extern FCH_INTERFACE     FchInterfaceDefault;
+
+FCH_DATA_BLOCK*
+FchInitEnvCreatePrivateData (
+  IN       AMD_ENV_PARAMS        *EnvParams
+  );
+
+AGESA_STATUS
+FchInitEnv (
+  IN       AMD_ENV_PARAMS            *EnvParams
+  );
+
+AGESA_STATUS
+FchEnvConstructor (
+  IN       AMD_ENV_PARAMS            *EnvParams
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * FchInitEnv - Config Fch before PCI emulation
+ *
+ *
+ *
+ * @param[in] EnvParams
+ *
+ */
+AGESA_STATUS
+FchInitEnv (
+  IN       AMD_ENV_PARAMS            *EnvParams
+  )
+{
+  FCH_DATA_BLOCK      *FchParams;
+  AGESA_STATUS        Status;
+
+  IDS_HDT_CONSOLE (FCH_TRACE, "  FchInitEnv Enter... \n");
+  FchParams = FchInitEnvCreatePrivateData (EnvParams);
+
+  // Override internal data with IDS (Optional, internal build only)
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_ENV, FchParams, FchParams->StdHeader);
+
+  AgesaFchOemCallout (FchParams);
+  Status = FchTaskLauncher (&FchInitEnvTaskTable[0], FchParams, TpFchInitEnvDispatching);
+  IDS_HDT_CONSOLE (FCH_TRACE, "  FchInitEnv Exit... Status = [0x%x]\n", Status);
+  return Status;
+}
+
+
+/**
+ * A constructor for FCH build parameter structure at InitEnv stage
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in,out] EnvParams       InitEnv configuration data block
+ *
+ * @retval AGESA_SUCCESS          Constructors are not allowed to fail
+*/
+AGESA_STATUS
+FchEnvConstructor (
+  IN       AMD_ENV_PARAMS            *EnvParams
+  )
+{
+  EnvParams->FchInterface = FchInterfaceDefault;
+  return AGESA_SUCCESS;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
new file mode 100644
index 0000000000..19016a3021
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
@@ -0,0 +1,129 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "FchTaskLauncher.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_INTERFACE_FCHINITLATE_FILECODE
+
+extern FCH_TASK_ENTRY   *FchInitLateTaskTable[];
+
+AGESA_STATUS
+FchInitLate (
+  IN      AMD_S3SAVE_PARAMS     *LateParams
+  );
+
+AGESA_STATUS
+FchLateConstructor (
+  IN       AMD_LATE_PARAMS          *LateParams
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  FchInitLate - Prepare Fch to boot to OS.
+ *
+ *
+ *
+ * @param[in] LateParams
+ *
+ */
+AGESA_STATUS
+FchInitLate (
+  IN      AMD_S3SAVE_PARAMS     *LateParams
+  )
+{
+  FCH_DATA_BLOCK      *FchParams;
+  AGESA_STATUS        Status;
+
+  IDS_HDT_CONSOLE (FCH_TRACE, "  FchInitLate Enter... \n");
+  FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader);
+  Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams, TpFchInitLateDispatching);
+  IDS_HDT_CONSOLE (FCH_TRACE, "  FchInitLate Exit... Status = [0x%x]\n", Status);
+  return Status;
+}
+
+
+/**
+ * A constructor for FCH build parameter structure at InitLate stage
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in,out] LateParams
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+FchLateConstructor (
+  IN       AMD_LATE_PARAMS          *LateParams
+  )
+{
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c
new file mode 100644
index 0000000000..0ab68177a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c
@@ -0,0 +1,127 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "FchTaskLauncher.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_INTERFACE_FCHINITMID_FILECODE
+
+extern FCH_TASK_ENTRY   *FchInitMidTaskTable[];
+
+AGESA_STATUS
+FchInitMid (
+  IN  AMD_MID_PARAMS     *MidParams
+  );
+
+AGESA_STATUS
+FchMidConstructor (
+  IN       AMD_MID_PARAMS            *MidParams
+  );
+/**
+ *  FchInitMid - Config Fch after PCI emulation
+ *
+ *
+ *
+ * @param[in] MidParams Fch configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+FchInitMid (
+  IN  AMD_MID_PARAMS     *MidParams
+  )
+{
+  FCH_DATA_BLOCK      *FchParams;
+  AGESA_STATUS        Status;
+
+  IDS_HDT_CONSOLE (FCH_TRACE, "  FchInitMid Enter... \n");
+  FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader);
+  Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams, TpFchInitMidDispatching);
+  IDS_HDT_CONSOLE (FCH_TRACE, "  FchInitMid Exit... Status = [0x%x]\n", Status);
+  return Status;
+}
+
+
+/**
+ * A constructor for FCH build parameter structure at InitEnv stage
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in] MidParams
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+FchMidConstructor (
+  IN       AMD_MID_PARAMS            *MidParams
+  )
+{
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c
new file mode 100644
index 0000000000..79561ac11a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c
@@ -0,0 +1,143 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Init during Power-On Reset
+ *
+ * Prepare FCH environment during power on stage
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include    "FchPlatform.h"
+#include    "FchTaskLauncher.h"
+#include    "heapManager.h"
+#include    "Ids.h"
+#include    "Filecode.h"
+#define FILECODE PROC_FCH_INTERFACE_FCHINITRESET_FILECODE
+
+extern FCH_TASK_ENTRY        *FchInitResetTaskTable[];
+extern FCH_RESET_INTERFACE   FchResetInterfaceDefault;
+
+FCH_RESET_DATA_BLOCK*
+FchInitResetLoadPrivateDefault (
+  IN       AMD_RESET_PARAMS      *ResetParams
+  );
+
+AGESA_STATUS
+FchInitReset (
+  IN  AMD_RESET_PARAMS     *ResetParams
+  );
+
+AGESA_STATUS
+FchResetConstructor (
+  IN       AMD_RESET_PARAMS          *ResetParams
+  );
+
+/**
+ * FchInitReset - Config Fch during power on stage.
+ *
+ *
+ *
+ * @param[in] ResetParams
+ *
+ */
+AGESA_STATUS
+FchInitReset (
+  IN  AMD_RESET_PARAMS     *ResetParams
+  )
+{
+  FCH_RESET_DATA_BLOCK         *FchParams;
+
+  // Load private data block with default
+  FchParams = FchInitResetLoadPrivateDefault (ResetParams);
+
+  // Override external data with input parameters
+  FchParams->StdHeader = &ResetParams->StdHeader;
+  FchParams->FchReset  = ResetParams->FchInterface;
+  FchParams->Gpp.GppFunctionEnable = ResetParams->FchInterface.GppEnable;
+
+  // Override internal data with IDS (Optional, internal build only)
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_RESET, FchParams, &ResetParams->StdHeader);
+
+  AgesaFchOemCallout (FchParams);
+  return FchTaskLauncher (&FchInitResetTaskTable[0], FchParams, TpFchInitResetDispatching);
+}
+
+
+/**
+ * A constructor for FCH build parameter structure at InitReset stage
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in] ResetParams
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+FchResetConstructor (
+  IN       AMD_RESET_PARAMS          *ResetParams
+  )
+{
+  ResetParams->FchInterface = FchResetInterfaceDefault;
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
new file mode 100644
index 0000000000..5abec4c252
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
@@ -0,0 +1,129 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include "FchPlatform.h"
+#include "FchTaskLauncher.h"
+#define FILECODE PROC_FCH_INTERFACE_FCHINITS3_FILECODE
+
+extern FCH_TASK_ENTRY   *FchInitS3EarlyTaskTable[];
+extern FCH_TASK_ENTRY   *FchInitS3LateTaskTable[];
+
+VOID
+FchInitS3EarlyRestore (
+  IN      FCH_DATA_BLOCK     *FchDataPtr
+  );
+
+VOID
+FchInitS3LateRestore (
+  IN      FCH_DATA_BLOCK     *FchDataPtr
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+
+VOID
+FchInitS3EarlyRestore (
+  IN      FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  AGESA_STATUS    AgesaStatus;
+
+  FchDataPtr->Misc.S3Resume = 1;
+  AgesaStatus = FchTaskLauncher (&FchInitS3EarlyTaskTable[0], FchDataPtr, TpFchInitS3EarlyDispatching);
+  FchDataPtr->Misc.S3Resume = 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+
+VOID
+FchInitS3LateRestore (
+  IN      FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  AGESA_STATUS    AgesaStatus;
+
+  FchDataPtr->Misc.S3Resume = 1;
+  AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr, TpFchInitS3LateDispatching);
+  FchDataPtr->Misc.S3Resume = 0;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c
new file mode 100644
index 0000000000..b6d94f905d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH task launcher
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#include "FchTaskLauncher.h"
+#define FILECODE PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE
+
+
+AGESA_STATUS
+FchTaskLauncher (
+  IN       FCH_TASK_ENTRY     **TaskPtr,
+  IN       VOID               *FchCfg,
+  IN       AGESA_TP           TestPoint
+  )
+{
+  AGESA_TESTPOINT (TestPoint, *(AMD_CONFIG_PARAMS **) FchCfg);
+  while (*TaskPtr != NULL) {
+    (*TaskPtr) (FchCfg);
+    TaskPtr++;
+  }
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.h
new file mode 100644
index 0000000000..8cc1a2064b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.h
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH task launcher
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#ifndef  _FCH_TASK_LAUNCHER_H_
+#define  _FCH_TASK_LAUNCHER_H_
+
+#include "Ids.h"
+
+FCH_DATA_BLOCK*
+FchInitLoadDataBlock (
+  IN       FCH_INTERFACE        *FchInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+AGESA_STATUS
+FchTaskLauncher (
+  IN       FCH_TASK_ENTRY     **TaskPtr,
+  IN       VOID               *FchCfg,
+  IN       AGESA_TP           TestPoint
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c
new file mode 100644
index 0000000000..b4ff312c1f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c
@@ -0,0 +1,223 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch Init during POWER-ON
+ *
+ * Prepare Fch environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include    "FchPlatform.h"
+#include    "Ids.h"
+#include    "heapManager.h"
+#include    "Filecode.h"
+
+#define FILECODE PROC_FCH_INTERFACE_INITENVDEF_FILECODE
+
+extern FCH_DATA_BLOCK InitEnvCfgDefault;
+
+FCH_DATA_BLOCK*
+FchInitEnvCreatePrivateData (
+  IN       AMD_ENV_PARAMS        *EnvParams
+  );
+
+FCH_DATA_BLOCK*
+FchInitLoadDataBlock (
+  IN       FCH_INTERFACE        *FchInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+FCH_DATA_BLOCK*
+FchInitLoadDataBlock (
+  IN       FCH_INTERFACE        *FchInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  FCH_DATA_BLOCK            *FchParams;
+  LOCATE_HEAP_PTR           LocHeapPtr;
+  AMD_CONFIG_PARAMS         TempStdHeader;
+  AGESA_STATUS              AgesaStatus;
+
+  TempStdHeader = *StdHeader;
+  TempStdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+
+  // Locate the internal data block via heap manager
+  LocHeapPtr.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE;
+  AgesaStatus = HeapLocateBuffer (&LocHeapPtr, &TempStdHeader);
+  ASSERT (!AgesaStatus);
+
+  FchParams = (FCH_DATA_BLOCK *) LocHeapPtr.BufferPtr;
+  ASSERT (FchParams != NULL);
+  FchParams->StdHeader = StdHeader;
+  return FchParams;
+}
+
+
+STATIC VOID
+RetrieveDataBlockFromInitReset (
+  IN       FCH_DATA_BLOCK       *FchParams
+  )
+{
+  LOCATE_HEAP_PTR           LocHeapPtr;
+  FCH_RESET_DATA_BLOCK      *ResetDb;
+  AGESA_STATUS              AgesaStatus;
+
+  LocHeapPtr.BufferHandle = AMD_FCH_RESET_DATA_BLOCK_HANDLE;
+  AgesaStatus = HeapLocateBuffer (&LocHeapPtr, FchParams->StdHeader);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    ASSERT (LocHeapPtr.BufferPtr != NULL);
+    ResetDb = (FCH_RESET_DATA_BLOCK *) (LocHeapPtr.BufferPtr - sizeof (ResetDb) + sizeof (UINT32));
+    // Override FchParams with contents in ResetDb
+
+    FchParams->Usb.Xhci0Enable              = ResetDb->FchReset.Xhci0Enable;
+    FchParams->Usb.Xhci1Enable              = ResetDb->FchReset.Xhci1Enable;
+    FchParams->Spi.SpiFastSpeed             = ResetDb->FastSpeed;
+    FchParams->Spi.WriteSpeed               = ResetDb->WriteSpeed;
+    FchParams->Spi.SpiMode                  = ResetDb->Mode;
+    FchParams->Spi.AutoMode                 = ResetDb->AutoMode;
+    FchParams->Spi.SpiBurstWrite            = ResetDb->BurstWrite;
+    FchParams->Sata.SataMode.Sata6AhciCap   = (UINT8) ResetDb->Sata6AhciCap;
+    FchParams->Misc.Cg2Pll                  = ResetDb->Cg2Pll;
+    FchParams->Sata.SataMode.SataSetMaxGen2 = ResetDb->SataSetMaxGen2;
+    FchParams->Sata.SataMode.SataClkMode    = ResetDb->SataClkMode;
+    FchParams->Sata.SataMode.SataModeReg    = ResetDb->SataModeReg;
+    FchParams->Sata.SataInternal100Spread   = (UINT8) ResetDb->SataInternal100Spread;
+    FchParams->Spi.SpiSpeed                 = ResetDb->SpiSpeed;
+    FchParams->Gpp                          = ResetDb->Gpp;
+  }
+}
+
+
+FCH_DATA_BLOCK*
+FchInitEnvCreatePrivateData (
+  IN       AMD_ENV_PARAMS        *EnvParams
+  )
+{
+  FCH_DATA_BLOCK            *FchParams;
+  ALLOCATE_HEAP_PARAMS      AllocHeapParams;
+  AGESA_STATUS              AgesaStatus;
+
+  // First allocate internal data block via heap manager
+  AllocHeapParams.RequestedBufferSize = sizeof (FCH_DATA_BLOCK);
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  AllocHeapParams.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &EnvParams->StdHeader);
+  ASSERT (!AgesaStatus);
+
+  FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr;
+  ASSERT (FchParams != NULL);
+  IDS_HDT_CONSOLE (FCH_TRACE, "    FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
+
+  // Load private data block with default
+  *FchParams = InitEnvCfgDefault;
+  FchParams->StdHeader = &EnvParams->StdHeader;
+
+  RetrieveDataBlockFromInitReset (FchParams);
+
+  // Update with external parameters
+  FchParams->Sd.SdConfig                 = EnvParams->FchInterface.SdConfig;
+  FchParams->Ir.IrConfig                 = EnvParams->FchInterface.IrConfig;
+  FchParams->Ab.NbSbGen2                 = EnvParams->FchInterface.UmiGen2;
+  FchParams->Sata.SataClass              = EnvParams->FchInterface.SataClass;
+  FchParams->Sata.SataMode.SataEnable    = EnvParams->FchInterface.SataEnable;
+  FchParams->Sata.SataMode.IdeEnable     = EnvParams->FchInterface.IdeEnable;
+  FchParams->Sata.SataIdeMode            = EnvParams->FchInterface.SataIdeMode;
+  FchParams->Usb.Ohci1Enable             = EnvParams->FchInterface.Ohci1Enable;
+  FchParams->Usb.Ehci1Enable             = EnvParams->FchInterface.Ohci1Enable;
+  FchParams->Usb.Ohci2Enable             = EnvParams->FchInterface.Ohci2Enable;
+  FchParams->Usb.Ehci2Enable             = EnvParams->FchInterface.Ohci2Enable;
+  FchParams->Usb.Ohci3Enable             = EnvParams->FchInterface.Ohci3Enable;
+  FchParams->Usb.Ehci3Enable             = EnvParams->FchInterface.Ohci3Enable;
+  FchParams->Usb.Ohci4Enable             = EnvParams->FchInterface.Ohci4Enable;
+  FchParams->HwAcpi.PwrFailShadow        = EnvParams->FchInterface.FchPowerFail;
+  FchParams->HwAcpi.Smbus0BaseAddress    = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
+  FchParams->HwAcpi.Smbus1BaseAddress    = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
+  FchParams->HwAcpi.SioPmeBaseAddress    = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
+  FchParams->HwAcpi.AcpiPm1EvtBlkAddr    = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
+  FchParams->HwAcpi.AcpiPm1CntBlkAddr    = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
+  FchParams->HwAcpi.AcpiPmTmrBlkAddr     = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
+  FchParams->HwAcpi.CpuControlBlkAddr    = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
+  FchParams->HwAcpi.AcpiGpe0BlkAddr      = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
+  FchParams->HwAcpi.SmiCmdPortAddr       = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
+  FchParams->HwAcpi.AcpiPmaCntBlkAddr    = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
+  FchParams->HwAcpi.WatchDogTimerBase    = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
+  FchParams->Sata.SataRaid5Ssid          = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
+  FchParams->Sata.SataRaidSsid           = UserOptions.FchBldCfg->CfgSataRaidSsid;
+  FchParams->Sata.SataAhciSsid           = UserOptions.FchBldCfg->CfgSataAhciSsid;
+  FchParams->Sata.SataIdeSsid            = UserOptions.FchBldCfg->CfgSataIdeSsid;
+  FchParams->Gec.GecShadowRomBase        = UserOptions.FchBldCfg->CfgGecShadowRomBase;
+  FchParams->Spi.RomBaseAddress          = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
+  FchParams->Sd.SdSsid                   = UserOptions.FchBldCfg->CfgSdSsid;
+  FchParams->Spi.LpcSsid                 = UserOptions.FchBldCfg->CfgLpcSsid;
+  FchParams->Hpet.HpetBase               = UserOptions.FchBldCfg->CfgHpetBaseAddress;
+  FchParams->Smbus.SmbusSsid             = UserOptions.FchBldCfg->CfgSmbusSsid;
+  FchParams->Ide.IdeSsid                 = UserOptions.FchBldCfg->CfgIdeSsid;
+  FchParams->Usb.EhciSsid                = UserOptions.FchBldCfg->CfgEhciSsid;
+  FchParams->Usb.OhciSsid                = UserOptions.FchBldCfg->CfgOhciSsid;
+  FchParams->Usb.XhciSsid                = UserOptions.FchBldCfg->CfgXhciSsid;
+  FchParams->Ir.IrPinControl             = UserOptions.FchBldCfg->CfgFchIrPinControl;
+  FchParams->Sd.SdClockControl           = UserOptions.FchBldCfg->CfgFchSdClockControl;
+  return FchParams;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c
new file mode 100644
index 0000000000..b0c44d5b41
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch Init during POWER-ON
+ *
+ * Prepare Fch environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#include    "FchPlatform.h"
+#include    "Ids.h"
+#include    "heapManager.h"
+#include    "Filecode.h"
+#define FILECODE PROC_FCH_INTERFACE_INITRESETDEF_FILECODE
+
+extern FCH_RESET_DATA_BLOCK  InitResetCfgDefault;
+
+FCH_RESET_DATA_BLOCK*
+FchInitResetLoadPrivateDefault (
+  IN       AMD_RESET_PARAMS      *ResetParams
+  );
+
+FCH_RESET_DATA_BLOCK*
+FchInitResetLoadPrivateDefault (
+  IN       AMD_RESET_PARAMS      *ResetParams
+  )
+{
+  FCH_RESET_DATA_BLOCK      *FchParams;
+  ALLOCATE_HEAP_PARAMS      AllocHeapParams;
+  AGESA_STATUS              AgesaStatus;
+
+  // First allocate internal data block via heap manager
+  AllocHeapParams.RequestedBufferSize = sizeof (FCH_RESET_DATA_BLOCK);
+  AllocHeapParams.Persist = HEAP_TEMP_MEM + 1;
+  AllocHeapParams.BufferHandle = AMD_FCH_RESET_DATA_BLOCK_HANDLE;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &ResetParams->StdHeader);
+  ASSERT (!AgesaStatus);
+
+  FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr;
+  ASSERT (FchParams != NULL);
+  IDS_HDT_CONSOLE (FCH_TRACE, "    FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
+
+  *FchParams = InitResetCfgDefault;
+
+  FchParams->Gpp.GppLinkConfig           = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
+  FchParams->Gpp.PortCfg[0].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort0Present;
+  FchParams->Gpp.PortCfg[1].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort1Present;
+  FchParams->Gpp.PortCfg[2].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort2Present;
+  FchParams->Gpp.PortCfg[3].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort3Present;
+  FchParams->Gpp.PortCfg[0].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
+  FchParams->Gpp.PortCfg[1].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
+  FchParams->Gpp.PortCfg[2].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
+  FchParams->Gpp.PortCfg[3].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
+
+  return FchParams;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrEnv.c
new file mode 100644
index 0000000000..59780b4d3f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrEnv.c
@@ -0,0 +1,135 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ir controller
+ *
+ * Init Ir Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IR_IRENV_FILECODE
+
+/**
+ * FchInitEnvIr - Config Ir controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvIr (
+  IN  VOID     *FchDataPtr
+  )
+{
+  IR_CONFIG    FchIrConfig;
+  UINT8    FchIrPinControl;
+  UINT8        Data;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  FchIrConfig = LocalCfgPtr->Ir.IrConfig;
+  FchIrPinControl = LocalCfgPtr->Ir.IrPinControl;
+
+  //
+  //IR init Logical device 0x05
+  //
+  if (FchIrConfig != IrDisable) {
+    EnterEcConfig (StdHeader);
+
+    RwEc8 (0x07, 0x00, 0x05, StdHeader);         ///Select logical device 05, IR controller
+    RwEc8 (0x60, 0x00, 0x05, StdHeader);         ///Set Base Address to 550h
+    RwEc8 (0x61, 0x00, 0x50, StdHeader);
+    RwEc8 (0x70, 0xF0, 0x05, StdHeader);         ///Set IRQ to 05h
+    RwEc8 (0x30, 0x00, 0x01, StdHeader);         ///Enable logical device 5, IR controller
+
+    Data = 0xAB;
+    LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader);
+    LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader);
+    Data = (UINT8) (FchIrPinControl & 0xFC);      ///Take out enable bits
+    Data |= FchIrPinControl & FchIrConfig & 0x03; ///Put back enable bits
+    LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader);
+
+    ExitEcConfig (StdHeader);
+
+    Data = 0xA0;                      /// EC APIC index
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader);
+    Data = 0x05;                      /// IRQ5
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader);
+  } else {
+    EnterEcConfig (StdHeader);
+
+    RwEc8 (0x07, 0x00, 0x05, StdHeader);         ///Select logical device 05, IR controller
+    RwEc8 (0x30, 0x00, 0x00, StdHeader);         ///Disable logical device 5, IR controller
+    Data = 0xAB;
+    LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader);
+    LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader);
+    Data = ((UINT8) FchIrPinControl) & 0xFC;     //Clear Enable bits
+    LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader);
+    ExitEcConfig (StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c
new file mode 100644
index 0000000000..c8dcfc02df
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ir controller
+ *
+ * Init Ir Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IR_IRLATE_FILECODE
+
+/**
+ * FchInitLateIr - Prepare Ir controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateIr (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrMid.c
new file mode 100644
index 0000000000..7ec4513aac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrMid.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ir controller
+ *
+ * Init Ir Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_IR_IRMID_FILECODE
+
+/**
+ * FchInitMidIr - Config Ir controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidIr (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
new file mode 100644
index 0000000000..e0c604a1e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcib controller
+ *
+ * Init Pcib Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE
+
+/**
+ * FchInitEnvPcibPciTable - PCI device registers initial during
+ * early POST.
+ *
+ */
+REG8_MASK FchInitEnvPcibPciTable[] =
+{
+  //
+  // PCIB Bridge (Bus 0, Dev 20, Func 4)
+  //
+  {0x00, PCIB_BUS_DEV_FUN, 0},
+  {FCH_PCIB_REG40, 0xFF, BIT5},      /// PCI-bridge Subtractive Decode
+  {FCH_PCIB_REG4B, 0xFF, BIT7},      ///
+  {0x66 , 0xFF, BIT4},      /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
+  {0x65 , 0xFF, BIT7},      /// proper operation of CLKRUN#.
+  {FCH_PCIB_REG0D, 0x00, 0x40},      /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
+  {FCH_PCIB_REG1B, 0x00, 0x40},      /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
+  {FCH_PCIB_REG66 + 1, 0xFF, BIT1},  /// Enable PCI bus GNT3#..
+  {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * FchInitEnvPcib - Config Pcib controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvPcib (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        VerbPciClks;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //Early post initialization of pci config space
+  //
+  ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader);
+
+  //
+  //Disable or Enable PCI Clks based on input
+  //
+  VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2);
+  RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, (UINT32)~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader);
+  VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x10) >> 4);
+  RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x4A , AccessWidth8, (UINT32)~BIT0, VerbPciClks, StdHeader);
+  //
+  // PCIB MSI
+  //
+  if (LocalCfgPtr->Pcib.PcibMsiEnable) {
+    RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x40 , AccessWidth8, (UINT32)~BIT3, BIT3, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibLate.c
new file mode 100644
index 0000000000..91b3a6503b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibLate.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcib controller
+ *
+ * Init Pcib Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_PCIB_PCIBLATE_FILECODE
+
+/**
+ * FchInitLatePcib - Prepare Pcib controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLatePcib (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Value;
+  UINT8        NStBit;
+  UINT8        NSBit;
+  UINT32       VarDd;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // We need to do the following setting in late post also because some bios core pci enumeration changes these values
+  // programmed during early post.
+  //  Master Latency Timer
+  //
+  Value = 0x40;
+  WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG0D, AccessWidth8, &Value, StdHeader);
+  WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG1B, AccessWidth8, &Value, StdHeader);
+
+  //
+  // CLKRUN#
+  // FCH P2P AutoClock control settings.
+  // VarDd = (FchDataPtr->PcibAutoClkCtrlLow) | (FchDataPtr->PcibAutoClkCtrlLow);
+  //
+  if ( LocalCfgPtr->Pcib.PcibClockRun ) {
+    ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG54, AccessWidth8, &Value);
+    NStBit = Value & 0x03;
+    NSBit = (Value & 0x3F ) >> 2;
+    VarDd = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;
+
+    VarDd = 9; // for A12
+    WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG4C, AccessWidth32, &VarDd, StdHeader);
+  }
+
+  VarDd = (LocalCfgPtr->Pcib.PcibClkStopOverride);
+  RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x50 , AccessWidth16, 0x3F, (UINT16) (VarDd << 6), StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibMid.c
new file mode 100644
index 0000000000..02f6dd76ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibMid.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcib controller
+ *
+ * Init Pcib Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_PCIB_PCIBMID_FILECODE
+
+/**
+ * FchInitMidPcib - Config Pcib controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidPcib (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
new file mode 100644
index 0000000000..231b9f2328
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
@@ -0,0 +1,163 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcib controller
+ *
+ * Init Pcib Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE
+/**
+ * FchInitResetPcibPciTable - Pcib device registers initial
+ * during the power on stage.
+ *
+ *
+ *
+ *
+ */
+REG8_MASK FchInitResetPcibPciTable[] =
+{
+  //
+  // P2P Bridge (Bus 0, Dev 20, Func 4)
+  //
+  {0x00, PCIB_BUS_DEV_FUN, 0},
+  {FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
+  {FCH_PCIB_REG40, 0xDF, 0x20},
+  {0x50 , 0x02, 0x01},
+  {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * FchInitResetPcib - Config Pcib controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetPcib (
+  IN  VOID     *FchDataPtr
+  )
+{
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
+
+  ProgramPciByteTable (
+    (REG8_MASK*) (&FchInitResetPcibPciTable[0]),
+    sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK),
+    StdHeader
+    );
+  if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) {
+    FchInitResetPcibPort80Enable (FchDataPtr);
+  }
+}
+
+/**
+ * FchInitResetPcibPort80Enable - Pcib device registers initial
+ * during the power on stage.
+ *
+ *
+ *
+ *
+ */
+REG8_MASK FchInitResetPcibPort80EnableTable[] =
+{
+  //
+  // P2P Bridge (Bus 0, Dev 20, Func 4)
+  //
+  {0x00, PCIB_BUS_DEV_FUN, 0},
+  {0x1C , 0x00, 0xF0},
+  {0x1D , 0x00, 0x00},
+  {0x04 , 0x00, 0x21},
+  {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * FchInitResetPcibPort80Enable - Enable Port80 Behind PCIB
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetPcibPort80Enable (
+  IN  VOID     *FchDataPtr
+  )
+{
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
+
+  ProgramPciByteTable (
+    (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]),
+    sizeof (FchInitResetPcibPort80EnableTable) / sizeof (REG8_MASK),
+    StdHeader
+    );
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c
new file mode 100644
index 0000000000..e72ed2537b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ab Bridge
+ *
+ * Init Ab Bridge features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_ABENV_FILECODE
+
+/**
+ * FchInitEnvAb - Config Ab Bridge before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvAb (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitEnvAbLinkInit (FchDataPtr);
+}
+
+/**
+ * FchInitEnvAbSpecial - Config Ab Bridge special timing
+ *
+ *  This routine must separate with FchInitEnvAb and give Ab
+ *  bridge little time to get ready
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvAbSpecial (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c
new file mode 100644
index 0000000000..d610b2aead
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ab Bridge
+ *
+ * Init Ab Bridge features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_ABLATE_FILECODE
+
+/**
+ * FchInitLateAb - Prepare Ab Bridge to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateAb (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchAbLateProgram (FchDataPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c
new file mode 100644
index 0000000000..a883876800
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ab Bridge
+ *
+ * Init Ab Bridge features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_ABMID_FILECODE
+
+/**
+ * FchInitMidAb - Config Ab Bridge after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidAb (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c
new file mode 100644
index 0000000000..dbb3973a20
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ab Bridge
+ *
+ * Init Ab Bridge features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#include "FchDef.h"
+#define FILECODE PROC_FCH_PCIE_ABRESET_FILECODE
+
+/**
+ * FchInitResetAb - Config Ab Bridge during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetAb (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchProgramAbPowerOnReset (FchDataPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
new file mode 100644
index 0000000000..af00e01bcc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
@@ -0,0 +1,387 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 AB
+ *
+ * Init AB bridge.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE
+
+//
+// Declaration of local functions
+//
+VOID AbCfgTbl (IN AB_TBL_ENTRY  *ABTbl, IN AMD_CONFIG_PARAMS *StdHeader);
+
+/**
+ * Hudson2PcieOrderRule - AB-Link Configuration Table for ablink
+ * Post Pass Np Downstream/Upstream Feature
+ *
+ */
+AB_TBL_ENTRY Hudson2PcieOrderRule[] =
+{
+  //
+  // abPostPassNpDownStreamTbl
+  //
+  {ABCFG, FCH_ABCFG_REG10060, BIT31, BIT31},
+  {ABCFG, FCH_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
+  {ABCFG, FCH_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
+  {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
+  {ABCFG, FCH_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
+  {AXINDC, FCH_AX_INDXC_REG02, BIT9, BIT9},
+  {ABCFG, FCH_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
+
+  //
+  // abPostPassNpUpStreamTbl
+  //
+  {ABCFG, FCH_ABCFG_REG58, BIT10, BIT10},
+  {ABCFG, FCH_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
+  {ABCFG, FCH_ABCFG_REG54, BIT1, BIT1},
+  { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
+};
+
+/**
+ * Hudson2InitEnvAbTable - AB-Link Configuration Table for Hudson2
+ *
+ */
+AB_TBL_ENTRY Hudson2InitEnvAbTable[] =
+{
+  //
+  // Enable downstream posted transactions to pass non-posted transactions.
+  //
+  {ABCFG, FCH_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
+
+  //
+  // Enable Hudson-2 to issue memory read/write requests in the upstream direction.
+  //
+  {AXCFG, FCH_AB_REG04, BIT2, BIT2},
+
+  //
+  // Enabling IDE/PCIB Prefetch for Performance Enhancement
+  // PCIB prefetch   ABCFG 0x10060 [20] = 1   ABCFG 0x10064 [20] = 1
+  //
+  {ABCFG, FCH_ABCFG_REG10060, BIT20, BIT20},                                    ///  PCIB prefetch enable
+  {ABCFG, FCH_ABCFG_REG10064, BIT20, BIT20},                                    ///  PCIB prefetch enable
+
+  //
+  // Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
+  // Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
+  //
+  {ABCFG, FCH_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
+
+  //
+  // Enabled SMI ordering enhancement. ABCFG 0x90[21]
+  // USB Delay A-Link Express L1 State. ABCFG 0x90[17]
+  //
+  {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},
+
+  //
+  // Disable the credit variable in the downstream arbitration equation
+  // Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
+  //
+  {ABCFG, FCH_ABCFG_REG9C, BIT0, BIT0},
+
+  //
+  // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
+  // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
+  //
+  {ABCFG, FCH_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
+
+  //
+  // Programming cycle delay for AB and BIF clock gating
+  // Enable the AB and BIF clock-gating logic.
+  // Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
+  // Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
+  //
+  {ABCFG, FCH_ABCFG_REG10054,  0x00FFFFFF, 0x010407FF},
+  {ABCFG, FCH_ABCFG_REG98,  0xFFFC00FF, 0x00034700},
+  {ABCFG, FCH_ABCFG_REG54,  0x00FF0000, 0x00040000},
+
+  //
+  // Non-Posted Memory Write Support
+  //
+  {AXINDC, FCH_AX_INDXC_REG10, BIT9, BIT9},
+
+  //
+  // UMI L1 Configuration
+  //Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off.
+  //Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.
+  //
+  {AXINDC, FCH_AX_INDXC_REG02, BIT0, BIT0},
+  {AXINDP, FCH_AX_INDXP_REG02, BIT15, BIT15},
+  {ABCFG, 0, 0, (UINT8) 0xFF},                                                 /// This dummy entry is to clear ab index
+  { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
+};
+
+/**
+ * FchInitEnvAbLinkInit - Set ABCFG registers before PCI
+ * emulation.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvAbLinkInit (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                 AbValue;
+  UINT16                 AbTempVar;
+  UINT8                  AbValue8;
+  UINT8                  FchALinkClkGateOff;
+  UINT8                  FchBLinkClkGateOff;
+  UINT32                 FchResetCpuOnSyncFlood;
+  AB_TBL_ENTRY           *AbTblPtr;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff;
+  FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff;
+  //
+  // AB CFG programming
+  //
+  if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, BIT1);
+  } else {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, 0);
+  }
+
+  //
+  // Read Arbiter address, Arbiter address is in PMIO 6Ch
+  //
+  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + 0x6C , AccessWidth16, &AbTempVar);
+  /// Write 0 to enable the arbiter
+  AbValue8 = 0;
+  LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader);
+
+
+  FchResetCpuOnSyncFlood = LocalCfgPtr->Ab.ResetCpuOnSyncFlood;
+
+  if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) {
+    AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]);
+    AbCfgTbl (AbTblPtr, StdHeader);
+  }
+
+  if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) {
+    RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader);
+    RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader);
+    RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader);
+  }
+
+  AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]);
+  AbCfgTbl (AbTblPtr, StdHeader);
+
+  if ( FchResetCpuOnSyncFlood ) {
+    RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), (UINT32)~BIT2, BIT2, StdHeader);
+  }
+
+  if ( LocalCfgPtr->Ab.AbClockGating ) {
+    RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
+    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
+    RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
+    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
+  } else {
+    RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
+    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
+  }
+
+
+  if ( LocalCfgPtr->Ab.GppClockGating ) {
+    RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader);
+    RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader);
+    RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
+  } else {
+    RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader);
+    RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader);
+  }
+
+  if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) {
+    RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride  << 12), StdHeader);
+    RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1  << 15), StdHeader);
+  }
+
+  if ( LocalCfgPtr->Ab.UmiLinkWidth ) {
+//    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+
+  if ( LocalCfgPtr->Ab.UmiDynamicSpeedChange ) {
+    RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
+    RwAlink ((UINT32) FCH_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0), StdHeader);
+    RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18), StdHeader);
+  }
+
+  if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) {
+//    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+
+  if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength  ) {
+    RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader);
+    RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader);
+  }
+
+  if ( LocalCfgPtr->Gpp.PcieAer ) {
+//    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+
+  if ( LocalCfgPtr->Gpp.PcieRas ) {
+//    RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+
+  //
+  // Ab Bridge MSI
+  //
+  if ( LocalCfgPtr->Ab.AbMsiEnable) {
+    AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader);
+    AbValue = AbValue | BIT20;
+    WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
+  }
+
+  //
+  // A/B Clock Gate-OFF
+  //
+  if ( FchALinkClkGateOff ) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, BIT0);
+  } else {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, 0x00);
+  }
+
+  if ( FchBLinkClkGateOff ) {
+    //RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10);      /// A11 Only
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, BIT1);
+  } else {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, 0x00);
+  }
+}
+
+/**
+ * AbCfgTbl - Program ABCFG by input table.
+ *
+ *
+ * @param[in] ABTbl  ABCFG config table.
+ * @param[in] StdHeader
+ *
+ */
+VOID
+AbCfgTbl (
+  IN  AB_TBL_ENTRY     *ABTbl,
+  IN AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32   AbValue;
+
+  while ( (ABTbl->RegType) != 0xFF ) {
+    if ( ABTbl->RegType == AXINDC ) {
+      AbValue = 0x30 | (ABTbl->RegType << 29);
+      WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader);
+      AbValue = 0x34 | (ABTbl->RegType << 29);
+      WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
+    } else if ( ABTbl->RegType == AXINDP ) {
+      AbValue = 0x38 | (ABTbl->RegType << 29);
+      WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader);
+      AbValue = 0x3C | (ABTbl->RegType << 29);
+      WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
+    } else {
+      AbValue = ABTbl->RegIndex | (ABTbl->RegType << 29);
+      WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
+    }
+
+    ++ABTbl;
+  }
+
+  //
+  //Clear ALink Access Index
+  //
+  AbValue = 0;
+  LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &AbValue, StdHeader);
+}
+
+/**
+ * Is UMI One Lane GEN1 Mode?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsUmiOneLaneGen1Mode (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32   AbValue;
+
+  AbValue = ReadAlink ((UINT32) (FCH_AX_CFG_REG68), StdHeader);
+  AbValue >>= 16;
+  if (((AbValue & 0x0f) == 1) && ((AbValue & 0x03f0) == 0x0010)) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
new file mode 100644
index 0000000000..ffed1fff4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 AB
+ *
+ * Init AB bridge.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE
+
+
+/**
+ * FchProgramAbPowerOnReset - Config Ab Bridge during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchProgramAbPowerOnReset (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       AbValue;
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+  UINT8                     EfuseValue;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Set A-Link bridge access address.
+  // This is an I/O address. The I/O address must be on 16-byte boundary.
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX);
+
+  //
+  // Enable Hudson-2 to issue memory read/write requests in the upstream direction
+  //
+  WriteAlink (0x80000004, 0x04, StdHeader);
+
+  //
+  // Disable the credit variable in the downstream arbitration equation
+  //
+  AbValue = ReadAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), StdHeader);
+  AbValue = AbValue | BIT0;
+  WriteAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), AbValue, StdHeader);
+
+  //
+  // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+  //
+  WriteAlink (0x30, 0x10, StdHeader);
+  WriteAlink (0x34, ReadAlink (0x34, StdHeader) | BIT9, StdHeader);
+
+  RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), (UINT32)~BIT2, 0x00, StdHeader);
+
+  //
+  // Configure UMI target link speed
+  //
+  EfuseValue = PCIE_FORCE_GEN1_EFUSE_LOCATION;
+  GetEfuseStatus (&EfuseValue, StdHeader);
+  if ( EfuseValue & BIT0 ) {
+    LocalCfgPtr->FchReset.UmiGen2 = FALSE;
+  }
+
+  EfuseValue = FCH_Variant_EFUSE_LOCATION;
+  GetEfuseStatus (&EfuseValue, StdHeader);
+  if ((EfuseValue == 0x07) || (EfuseValue == 0x08)) {
+    LocalCfgPtr->FchReset.UmiGen2 = FALSE;
+  }
+
+  AbValue = LocalCfgPtr->FchReset.UmiGen2 ? 2 : 1;
+  RwAlink ((UINT32)FCH_AX_CFG_REG88, 0xFFFFFFF0, AbValue, StdHeader);
+
+  AbValue = LocalCfgPtr->FchReset.UmiGen2 ? BIT0 : 0;
+  RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader);
+
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
new file mode 100644
index 0000000000..46a7253778
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 AB
+ *
+ * Init AB bridge.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE
+
+/**
+ * FchAbLateProgram - Set ABCFG registers during late POST
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchAbLateProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                 AbValue;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
+  AbValue &= 0xf0;
+
+  if ( LocalCfgPtr->Ab.PcieOrderRule && AbValue ) {
+    AbValue = ReadAlink (FCH_RCINDXC_REG02, StdHeader);
+    AbValue = AbValue | BIT9;
+    WriteAlink (FCH_RCINDXC_REG02, AbValue, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
new file mode 100644
index 0000000000..5635a5ed76
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
@@ -0,0 +1,150 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 Pcie controller
+ *
+ * Init GPP (pcie Controller) features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE
+
+
+/**
+ * ProgramFchGppInitReset - Config Gpp at PowerOnReset
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+ProgramFchGppInitReset (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  //
+  // Toggle GEVENT4 to reset all GPP devices
+  //
+  ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader);
+  if (FchGpp->SerialDebugBusEnable) {
+    RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), (UINT32)~BIT12, 0x00);
+  }
+}
+
+/**
+ * FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device
+ * reset
+ *
+ *
+ * @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE
+ * @param[in] ResetOp    - Assert or deassert PCIE reset
+ * @param[in] StdHeader
+ *
+ */
+VOID
+FchResetPcie (
+  IN       RESET_BLOCK         ResetBlock,
+  IN       RESET_OP            ResetOp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8    Or8;
+  UINT8    Mask8;
+
+  if (ResetBlock == NbBlock) {
+    if (ResetOp == AssertReset) {
+      Or8 = BIT4;
+      Mask8 = 0;
+      LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader);
+    } else if (ResetOp == DeassertReset) {
+      Or8 = 0;
+      Mask8 = BIT4;
+      LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader);
+    }
+  } else if (ResetBlock == FchBlock) {
+    Or8 = BIT1;
+    Mask8 = BIT1 + BIT0;
+    LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
+    if (ResetOp == AssertReset) {
+      Or8 = 0;
+      Mask8 = BIT5;
+      LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
+      Or8 = BIT4;
+      Mask8 = 0;
+      LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader);
+    } else if (ResetOp == DeassertReset) {
+      Or8 = 0;
+      Mask8 = BIT4;
+      LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader);
+      Or8 = BIT5;
+      Mask8 = 0;
+      LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
new file mode 100644
index 0000000000..f1e2f4280e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
@@ -0,0 +1,223 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 Pcie controller
+ *
+ * Init GPP (pcie Controller) features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE
+
+/**
+ * ProgramGppTogglePcieReset - Toggle PCIE_RST2#
+ *
+ *
+ * @param[in] DoToggling
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ProgramGppTogglePcieReset (
+  IN     BOOLEAN                DoToggling,
+  IN     AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  if (DoToggling) {
+    FchResetPcie (FchBlock, AssertReset, StdHeader);
+    FchStall (500, StdHeader);
+    FchResetPcie (FchBlock, DeassertReset, StdHeader);
+  } else {
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, (UINT32)~(BIT1 + BIT0), 0x02);
+  }
+}
+
+/**
+ * FchGppDynamicPowerSaving - GPP Dynamic Power Saving
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+FchGppDynamicPowerSaving (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  FCH_GPP_PORT_CONFIG    *PortCfg;
+  UINT32                 GppData32;
+  UINT32                 HoldGppData32;
+  UINT32                 AbValue;
+
+  if (!FchGpp->GppDynamicPowerSaving || FchGpp->SerialDebugBusEnable) {
+    return;
+  }
+
+  if (FchGpp->GppHardwareDownGrade) {
+    PortCfg = &FchGpp->PortCfg[FchGpp->GppHardwareDownGrade - 1];
+    PortCfg->PortDetected = TRUE;
+  }
+
+  GppData32 = 0;
+  HoldGppData32 = 0;
+
+  switch ( FchGpp->GppLinkConfig ) {
+  case PortA4:
+    PortCfg = &FchGpp->PortCfg[0];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= 0x0f0f;
+      HoldGppData32 |= 0x1000;
+    }
+    break;
+
+  case PortA2B2:
+    PortCfg = &FchGpp->PortCfg[0];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303;
+      HoldGppData32 |= 0x1000;
+    }
+
+    PortCfg = &FchGpp->PortCfg[1];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0303:0x0c0c;
+      HoldGppData32 |= 0x2000;
+    }
+    break;
+
+  case PortA2B1C1:
+    PortCfg = &FchGpp->PortCfg[0];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303;
+      HoldGppData32 |= 0x1000;
+    }
+
+    PortCfg = &FchGpp->PortCfg[1];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404;
+      HoldGppData32 |= 0x2000;
+    }
+
+    PortCfg = &FchGpp->PortCfg[2];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808;
+      HoldGppData32 |= 0x4000;
+    }
+    break;
+
+  case PortA1B1C1D1:
+    PortCfg = &FchGpp->PortCfg[0];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0808:0x0101;
+      HoldGppData32 |= 0x1000;
+    }
+
+    PortCfg = &FchGpp->PortCfg[1];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0404:0x0202;
+      HoldGppData32 |= 0x2000;
+    }
+
+    PortCfg = &FchGpp->PortCfg[2];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404;
+      HoldGppData32 |= 0x4000;
+    }
+
+    PortCfg = &FchGpp->PortCfg[3];
+    if ( PortCfg->PortDetected == FALSE ) {
+      GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808;
+      HoldGppData32 |= 0x8000;
+    }
+    break;
+
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+  //
+  // Power Saving With GPP Disable
+  // ABCFG 0xC0[8] = 0x0
+  // ABCFG 0xC0[15:12] = 0xF
+  // Enable "Power Saving Feature for A-Link Express Lanes"
+  // Enable "Power Saving Feature for GPP Lanes"
+  // ABCFG 0x90[19] = 1
+  // ABCFG 0x90[6] = 1
+  // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
+  // ABCFG 0xC0[7:4] = 0x0
+  //
+  if (FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown ) {
+    AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
+    WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader);
+    RwAlink (FCH_AX_INDXC_REG40, (UINT32)~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
+    RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader);
+    RwAlink (FCH_RCINDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
new file mode 100644
index 0000000000..0b554daf64
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 Pcie controller
+ *
+ * Init Pcie Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE
+
+
+/**
+ * ProgramPcieNativeMode - Config Pcie Native Mode
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ProgramPcieNativeMode (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        FchNativepciesupport;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  FchNativepciesupport = (UINT8) LocalCfgPtr->Misc.NativePcieSupport;
+
+  //
+  // PCIE Native setting
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBA + 1, AccessWidth8, (UINT32)~BIT14, 0);
+  if ( FchNativepciesupport == 1) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x74  + 3, AccessWidth8, (UINT32)~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x74  + 3, AccessWidth8, (UINT32)~(BIT3 + BIT1 + BIT0), BIT3 + BIT2);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
new file mode 100644
index 0000000000..2d93377ff2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
@@ -0,0 +1,73 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 Pcie controller
+ *
+ * Init Pcie Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c
new file mode 100644
index 0000000000..6f1f51d659
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c
@@ -0,0 +1,127 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Gpp controller
+ *
+ * Init Gpp Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_GPPENV_FILECODE
+
+VOID
+FchInitEnvGppPhaseII (
+  IN  VOID     *FchDataPtr
+  );
+
+/**
+ * FchInitEnvGpp - Config Gpp controller before PCI emulation
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvGpp (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) {
+    ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader);
+    FchStall (5000, StdHeader);
+  }
+  FchGppPortInit (&LocalCfgPtr->Gpp, StdHeader);
+}
+
+/**
+ * FchInitEnvGppPhaseII - Config Gpp controller before PCI emulation (For New Algorithm)
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvGppPhaseII (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Gpp.NewGppAlgorithm == TRUE ) {
+    FchGppPortInitPhaseII (&LocalCfgPtr->Gpp, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppHp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppHp.c
new file mode 100644
index 0000000000..5a52f892b8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppHp.c
@@ -0,0 +1,220 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch GPP controller
+ *
+ * Init GPP features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_GPPHP_FILECODE
+
+VOID
+FchGppHotplugSmiCallback (
+  IN       VOID           *DataPtr
+  );
+
+/**
+ * GPP hot plug handler
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] HpPort      The hot plug port number
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC VOID
+FchGppHotPlugSmiProcess (
+  IN       FCH_GPP             *FchGpp,
+  IN       UINT32              HpPort,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                  FailedPort;
+  UINT8                  GppS3Data;
+
+  GppS3Data = 0x00;
+  ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data);
+  RwAlink (FCH_RCINDXC_REG40, (UINT32)~BIT3, 0, StdHeader);
+
+  //
+  // First restore GPP pads if needed
+  //
+  if (FchGpp->GppDynamicPowerSaving && FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown) {
+    RwAlink (0xC0  | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0, StdHeader);
+    RwAlink (FCH_RCINDXC_REG65, ~(UINT32) (0x101 << HpPort), 0, StdHeader);
+    FchStall (1000, StdHeader);
+  }
+
+  FailedPort = (UINT8) (1 << HpPort);
+  if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) {
+    GppS3Data &= (UINT8) !(1 << HpPort);
+    if (GppPortPollingLtssm (FchGpp, FailedPort, TRUE, StdHeader)) {
+      FchGppForceGen1 (FchGpp, FailedPort, StdHeader);
+      FailedPort = GppPortPollingLtssm (FchGpp, FailedPort, FALSE, StdHeader);
+      GppS3Data |= (UINT8) (1 << HpPort);
+    }
+  } else {
+    FchGppForceGen1 (FchGpp, FailedPort, StdHeader);
+    FailedPort = GppPortPollingLtssm (FchGpp, FailedPort, FALSE, StdHeader);
+    GppS3Data |= (UINT8) (1 << HpPort);
+  }
+  GppS3Data |= (UINT8) (1 << (HpPort + 4));
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data);
+  GppGen2Workaround (FchGpp, StdHeader);
+}
+
+
+/**
+ * GPP hot-unplug handler
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] HpPort      The hot plug port number.
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC VOID
+FchGppHotUnplugSmiProcess (
+  IN       FCH_GPP             *FchGpp,
+  IN       UINT32              HpPort,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                  GppS3Data;
+
+  GppS3Data = 0x00;
+  ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data);
+  FchGpp->PortCfg[HpPort].PortDetected = FALSE;
+  GppS3Data &= (UINT8) !(1 << (HpPort + 4));
+
+  if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) {
+    FchGppForceGen2 (FchGpp, (UINT8) (1 << HpPort), StdHeader);
+  }
+
+  if (FchGpp->GppDynamicPowerSaving && FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown) {
+    RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17, StdHeader);
+    RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8, StdHeader);
+    RwAlink (0xC0  | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)), StdHeader);
+    RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0, StdHeader);
+
+    GppGen2Workaround (FchGpp, StdHeader);
+
+    // Finally re-configure GPP pads if needed
+    FchGppDynamicPowerSaving (FchGpp, StdHeader);
+  }
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data);
+}
+
+
+/**
+ * SMI handler for GPP hot-plug
+ *
+ *
+ * @param[in] DataPtr     Fch configuration structure pointer.
+ *
+ */
+VOID
+FchGppHotplugSmiCallback (
+  IN       VOID           *DataPtr
+  )
+{
+  UINT32             PortNum;
+  UINT32             HpPort;
+  FCH_DATA_BLOCK     *FchDb;
+  UINT8              HpGeventNum;
+  UINT8              GpioPinState;
+
+  FchDb = (FCH_DATA_BLOCK*) DataPtr;
+  if (!FchDb->Gpp.GppFunctionEnable) {
+    return;
+  }
+
+  HpPort = 0xff;
+  for (PortNum = 0; PortNum < MAX_GPP_PORTS; PortNum++) {
+    if (FchDb->Gpp.PortCfg[PortNum].PortHotPlug == TRUE) {
+      HpPort = PortNum;
+      break;
+    }
+  }
+
+  if (HpPort == 0xff) {
+    return;
+  }
+
+  HpGeventNum = FchDb->Gpp.GppHotPlugGeventNum & 31;
+  GpioPinState = ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG00 + HpGeventNum) >> 7;
+  if (!GpioPinState) {
+    AGESA_TESTPOINT (TpFchGppHotPlugging, FchDb->StdHeader);
+    FchGppHotPlugSmiProcess (&FchDb->Gpp, HpPort, FchDb->StdHeader);
+  } else {
+    AGESA_TESTPOINT (TpFchGppHotUnplugging, FchDb->StdHeader);
+    FchGppHotUnplugSmiProcess (&FchDb->Gpp, HpPort, FchDb->StdHeader);
+  }
+
+  ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98) ^= (1 << HpGeventNum);     // Swap SmiTrig
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c
new file mode 100644
index 0000000000..bf1064726a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c
@@ -0,0 +1,313 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Gpp controller
+ *
+ * Init Gpp Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_GPPLATE_FILECODE
+
+//
+// Declaration of local functions
+//
+
+
+/**
+ * FchGppSetAspm - Set GPP ASPM
+ *
+ *
+ * @param[in] PciAddress PCI Address.
+ * @param[in] LxState    Lane State.
+ * @param[in] StdHeader
+ *
+ */
+STATIC VOID
+FchGppSetAspm (
+  IN  UINT32                    PciAddress,
+  IN  UINT8                     LxState,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT8      PcieCapOffset;
+  UINT8      DeviceType;
+
+  PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader);
+
+  if (PcieCapOffset) {
+    //
+    // Read link capabilities register (0x0C[11:10] - ASPM support)
+    //
+    ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
+    if (DeviceType & BIT2) {
+      DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
+      //
+      // Set ASPM state in link control register
+      //
+      RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader);
+    }
+  }
+}
+
+/**
+ * FchGppSetEpAspm - Set EP ASPM
+ *
+ *
+ * @param[in] PciAddress PCI Address.
+ * @param[in] LxState    Lane State.
+ * @param[in] StdHeader
+ *
+ */
+STATIC VOID
+FchGppSetEpAspm (
+  IN  UINT32                    PciAddress,
+  IN  UINT8                     LxState,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT8      DeviceType;
+  UINT8      MaxFuncs;
+  UINT32     DevBDF;
+
+  MaxFuncs = 1;
+  ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader);
+
+  if (DeviceType & BIT7) {
+    MaxFuncs = 8;                                                                   /// multi-function device
+  }
+
+  while (MaxFuncs != 0) {
+    DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16);
+    FchGppSetAspm (DevBDF, LxState, StdHeader);
+    MaxFuncs--;
+  }
+}
+
+/**
+ * FchGppValidateAspm - Validate EndPoint support for GPP ASPM
+ *
+ *
+ * @param[in] PciAddress PCI Address.
+ * @param[in] LxState    Lane State.
+ * @param[in] StdHeader
+ *
+ */
+STATIC VOID
+FchGppValidateAspm (
+  IN  UINT32                    PciAddress,
+  IN  UINT8                     *LxState,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT8      PcieCapOffset;
+  UINT8      DeviceType;
+  UINT8      MaxFuncs;
+  UINT32     DevBDF;
+
+  MaxFuncs = 1;
+  ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader);
+
+  if (DeviceType & BIT7) {
+    MaxFuncs = 8;                                                                   /// multi-function device
+  }
+
+  while (MaxFuncs != 0) {
+    DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16);
+    PcieCapOffset = FchFindPciCap (DevBDF, PCIE_CAP_ID, StdHeader);
+
+    if (PcieCapOffset) {
+      //
+      // Read link capabilities register (0x0C[11:10] - ASPM support)
+      //
+      ReadPci (DevBDF + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
+      if (DeviceType & BIT2) {
+        DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
+        //
+        // Update ASPM state as what endpoint support
+        //
+        *LxState &= DeviceType;
+      }
+    }
+    MaxFuncs--;
+  }
+}
+
+
+/**
+ * FchInitLateGpp - Prepare Gpp controller to boot to OS.
+ *
+ *  PcieGppLateInit
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateGpp (
+  IN       VOID     *FchDataPtr
+  )
+{
+  UINT8                  PortId;
+  UINT8                  BusNum;
+  UINT8                  PortAspmValue;
+  UINT8                  AllowStrapControlByAB;
+  UINT8                  GppS3Data;
+  FCH_GPP_PORT_CONFIG    *PortCfg;
+  UINT32                 PciAspmValue;
+  UINT32                 AbValue;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Disable hidden register decode and serial number capability
+  //
+  AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader);
+  WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader);
+  //
+  // Configure ASPM & Save GPP port status into CMOS
+  //
+  AllowStrapControlByAB = 0x01;
+  GppS3Data = 0x00;
+
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    //
+    // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS
+    // when native PCIE is enabled but MSI is not available
+    // BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
+    //
+    PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
+    if (PortCfg->PortDetected) {
+      GppS3Data |= 1 << (PortId + 4);
+      if (PortCfg->PortIsGen2 == FALSE) {
+        GppS3Data |= 1 << (PortId);
+      }
+    }
+    if (PortCfg->PortHotPlug) {
+      RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader);         ///clear IO enable to fix possible hotplug hang
+    }
+
+    WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader);
+    ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader);
+
+    if (BusNum != 0xFF) {
+      ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader);
+      if (PciAspmValue != 0xffffffff) {
+        PortAspmValue = LocalCfgPtr->Gpp.GppPortAspm;
+        //
+        // Validate ASPM support on EP side
+        //
+        FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader);
+        //
+        // Set ASPM on EP side
+        //
+        FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader);
+        //
+        // Set ASPM on port side
+        //
+        FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader);
+      }
+    }
+    RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (PortId << 24)), (UINT32)~BIT15, BIT15, StdHeader);
+  }
+  RwAlink (FCH_RCINDXC_REG02, (UINT32)~BIT0, BIT0, StdHeader);
+
+  if ( LocalCfgPtr->Gpp.GppPhyPllPowerDown == TRUE ) {
+    //
+    // Power Saving Feature for GPP Lanes
+    //
+    // Set PCIE_P_CNTL in Alink PCIEIND space
+    //
+    AbValue = ReadAlink (FCH_RCINDXC_REG40, StdHeader);
+    AbValue |= BIT12 + BIT0;
+    AbValue &= ~(BIT9 + BIT4);
+    WriteAlink (FCH_RCINDXC_REG40, AbValue, StdHeader);
+    RwAlink (FCH_RCINDXC_REG02, (UINT32)~(BIT8 + BIT3), BIT8 + BIT3, StdHeader);
+    GppGen2Workaround (&LocalCfgPtr->Gpp, StdHeader);
+  }
+
+  //
+  // Configure Lock HWInit registers
+  //
+  AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
+  if (AbValue & 0xF0) {
+    AbValue = ReadAlink (FCH_RCINDXC_REG10, StdHeader);
+    WriteAlink (FCH_RCINDXC_REG10, AbValue | BIT0, StdHeader);    /// Set HWINIT_WR_LOCK
+  }
+
+  //
+  // Restore strap0 via override
+  //
+  if (LocalCfgPtr->Gpp.PcieAer) {
+    RwAlink (0x310  | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader);
+    RwAlink (FCH_RCINDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader);
+  }
+  RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLib.c
new file mode 100644
index 0000000000..0a20d0f1d9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLib.c
@@ -0,0 +1,361 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch Gpp Library
+ *
+ * Gpp Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#include "FchDef.h"
+#define FILECODE PROC_FCH_PCIE_GPPLIB_FILECODE
+
+/**
+ * FchGppForceGen2 - Set GPP to Gen2
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] ActivePorts Activate Ports
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+FchGppForceGen2 (
+  IN       FCH_GPP             *FchGpp,
+  IN       CONST UINT8         ActivePorts,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32            PortId;
+
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    if (ActivePorts & (1 << PortId)) {
+      RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, 0xFFFFFFFF, BIT29 + BIT0, StdHeader);
+      RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21, StdHeader);
+      RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, (UINT32)~BIT13, 0, StdHeader);
+      RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, (UINT32)~BIT15, 0, StdHeader);
+      RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x02, StdHeader);
+
+      (&FchGpp->PortCfg[PortId])->PortIsGen2 = TRUE;
+    }
+  }
+}
+
+/**
+ * FchGppForceGen1 - Set GPP to Gen1
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] ActivePorts Activate Ports
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+FchGppForceGen1 (
+  IN       FCH_GPP             *FchGpp,
+  IN       CONST UINT8         ActivePorts,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32            PortId;
+
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    if (ActivePorts & (1 << PortId) && FchGpp->GppHardwareDownGrade != PortId + 1) {
+      RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), (UINT32)~BIT21, 0, StdHeader);
+      RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, (UINT32)~BIT0, BIT29, StdHeader);
+      RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, 0xFFFFFFFF, BIT13, StdHeader);
+      RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, (UINT32)~BIT15, 0, StdHeader);
+      RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x01, StdHeader);
+
+      (&FchGpp->PortCfg[PortId])->PortIsGen2 = FALSE;
+    }
+  }
+}
+
+/**
+ * GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap
+ *
+ *
+ * @param[in] FchGpp        Pointer to Fch GPP configuration structure
+ * @param[in] ActivePorts   A bitmap of ports which should be polled
+ * @param[in] IsGen2        TRUE if the polling is in Gen2 mode
+ * @param[in] StdHeader     Pointer to AMD_CONFIG_PARAMS
+ *
+ * @retval       FailedPorts     A bitmap of ports which failed to train
+ *
+ */
+UINT8
+GppPortPollingLtssm (
+  IN       FCH_GPP             *FchGpp,
+  IN       UINT8               ActivePorts,
+  IN       BOOLEAN             IsGen2,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                 RetryCounter;
+  UINT8                  PortId;
+  UINT8                  FailedPorts;
+  UINT8                  HotPlugPorts;
+  FCH_GPP_PORT_CONFIG    *PortCfg;
+  UINT32                 AbIndex;
+  UINT32                 GppData32;
+  UINT8                  EmptyPorts;
+  UINT8                  Index;
+  UINT8                  FixedPolling;
+
+  FailedPorts = 0;
+  HotPlugPorts = 0;
+  RetryCounter = MAX_LT_POLLINGS;
+  EmptyPorts = ActivePorts;
+  FixedPolling = 200;
+  if ( FchGpp->NewGppAlgorithm == TRUE ) {
+    FixedPolling = FchGpp->GppPortMinPollingTime;
+  }
+  while (RetryCounter-- && ActivePorts) {
+    for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
+      if (ActivePorts & (1 << PortId)) {
+        PortCfg = &FchGpp->PortCfg[PortId];
+        if ( PortCfg->PortHotPlug == TRUE ) {
+          HotPlugPorts |= ( 1 << PortId);
+        }
+        AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (PortId << 24);
+        GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F;
+
+        if ((UINT8) (GppData32) > 0x04) {
+          EmptyPorts &= ~(1 << PortId);
+        }
+
+        if ((UINT8) (GppData32) == 0x10) {
+          ActivePorts &= ~(1 << PortId);
+          PortCfg->PortDetected = TRUE;
+          break;
+        }
+
+        if (IsGen2) {
+          for (Index = 0; Index < 4; Index++) {
+            if ((UINT8) (GppData32) == 0x29 || (UINT8) (GppData32) == 0x2A ) {
+              ActivePorts &= ~(1 << PortId);
+              FailedPorts |= (1 << PortId);
+              break;
+            }
+            GppData32 >>= 8;
+          }
+        }
+      }
+    }
+    if (EmptyPorts && RetryCounter < (MAX_LT_POLLINGS - (UINT32) FixedPolling)) {
+      ActivePorts &= ~EmptyPorts;
+    }
+    FchStall (1000, StdHeader);
+  }
+  FchGpp->HotPlugPortsStatus = HotPlugPorts;
+
+  FailedPorts |= ActivePorts;
+  return FailedPorts;
+}
+
+
+/**
+ * FchFindPciCap - Find PCI Cap
+ *
+ *
+ * @param[in] PciAddress     PCI Address.
+ * @param[in] TargetCapId    Target Cap ID.
+ * @param[in] StdHeader
+ *
+ */
+UINT8
+FchFindPciCap (
+  IN  UINT32                PciAddress,
+  IN  UINT8                 TargetCapId,
+  IN  AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8   NextCapPtr;
+  UINT8   CapId;
+
+  NextCapPtr = 0x34;
+  while (NextCapPtr != 0) {
+    ReadPci (PciAddress + NextCapPtr, AccessWidth8, &NextCapPtr, StdHeader);
+
+    if (NextCapPtr == 0xff) {
+      return 0;
+    }
+
+    if (NextCapPtr != 0) {
+      ReadPci (PciAddress + NextCapPtr, AccessWidth8, &CapId, StdHeader);
+      if (CapId == TargetCapId) {
+        break;
+      } else {
+        NextCapPtr++;
+      }
+    }
+  }
+  return NextCapPtr;
+}
+
+STATIC
+BOOLEAN
+IsDeviceGen2Capable (
+  IN       UINT32              pciAddress,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8      pcieCapOffset;
+  UINT8      value8;
+  UINT16     value16;
+
+  pcieCapOffset = FchFindPciCap (pciAddress, PCIE_CAP_ID, StdHeader);
+  if (pcieCapOffset) {
+    ReadPci (pciAddress + pcieCapOffset + 0x0C, AccessWidth8, &value8, StdHeader);
+    if (value8 & BIT1) {
+      return TRUE;
+    } else {
+      ReadPci (pciAddress, AccessWidth16, &value16, StdHeader);
+      if ((value16 == AMD_FCH_VID) || (value16 == ATI_VID)) {
+        return TRUE;
+      }
+    }
+  }
+  return FALSE;
+}
+
+
+/**
+ *
+ * 5/10/2011 - BIOS workaround for PLLPD hangup issue (applied for both POST and hotplug phases):
+ *
+ * if (GppPhyPllPowerDown == TRUE) {
+ *   if (GppGen2 == TRUE && GppGen2Strap == TRUE) {
+ *     if ((Any EP is GEN2 capable) || (Any EP is AMD/ATI GFX card)) {
+ *       INDXC_REG40[3] = 0;
+ *     } else {
+ *       INDXC_REG40[3] = 1;
+ *     }
+ *   } else {
+ *     INDXC_REG40[3] = 1;
+ *   }
+ * }
+ *
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+GppGen2Workaround (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8            portId;
+  UINT8            busNum;
+  UINT32           reg32Value;
+  BOOLEAN          DisablePllPdInL1;
+
+  if (FchGpp->GppPhyPllPowerDown == TRUE) {
+    DisablePllPdInL1 = FALSE;
+    if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) {
+      // Search all EP for max link speed capability
+      for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+        ReadPci (PCI_ADDRESS (0, FCH_GPP_DEV, portId, 0x19), AccessWidth8, &busNum, StdHeader);
+        if (busNum != 0xFF) {
+          ReadPci (PCI_ADDRESS (busNum, 0, 0, 0x00), AccessWidth32, &reg32Value, StdHeader);
+          if (reg32Value != 0xffffffff) {
+            DisablePllPdInL1 = IsDeviceGen2Capable (PCI_ADDRESS (busNum, 0, 0, 0), StdHeader);
+            if (DisablePllPdInL1 == TRUE) {
+              break;
+            }
+          }
+        }
+      }
+    }
+
+    if (DisablePllPdInL1 == TRUE) {
+      RwAlink (FCH_RCINDXC_REG40, (UINT32)~BIT3, 0, StdHeader);
+    } else {
+      RwAlink (FCH_RCINDXC_REG40, (UINT32)~BIT3, BIT3, StdHeader);
+    }
+  }
+}
+
+UINT32
+GppGetFchTempBus (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                FchTempBus;
+  UINT8                 TempValue;
+  UINT64                MmioMsr;
+
+  LibAmdMsrRead (0xC0010058, &MmioMsr, StdHeader);
+  TempValue = (UINT8) ((MmioMsr & 0x03C) >> 2);
+  FchTempBus = ( 0x01 << TempValue);
+  FchTempBus--;
+  FchTempBus--;
+  return ( FchTempBus);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppMid.c
new file mode 100644
index 0000000000..a32e9b5ce7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppMid.c
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Gpp controller
+ *
+ * Init Gpp Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_GPPMID_FILECODE
+//
+// Declaration of local functions
+//
+
+/**
+ * FchInitMidGpp - Config Gpp controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidGpp (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c
new file mode 100644
index 0000000000..e9b8056688
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c
@@ -0,0 +1,760 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config and Train Fch Gpp Ports
+ *
+ * Init Gpp Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_GPPPORTINIT_FILECODE
+
+//
+// Declaration of local functions
+//
+/**
+ * GppPortPollingLtssmS3 - Loop polling the LTSSM for each GPP port marked in PortMap (New Algorithm S3)
+ *
+ *
+ * @param[in] FchGpp        Pointer to Fch GPP configuration structure
+ * @param[in] ActivePorts   A bitmap of ports which should be polled
+ * @param[in] IsGen2        TRUE if the polling is in Gen2 mode
+ * @param[in] StdHeader     Pointer to AMD_CONFIG_PARAMS
+ *
+ * @retval       FailedPorts     A bitmap of ports which failed to train
+ *
+ */
+STATIC UINT8
+GppPortPollingLtssmS3 (
+  IN       FCH_GPP             *FchGpp,
+  IN       UINT8               ActivePorts,
+  IN       BOOLEAN             IsGen2,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                  PortId;
+  UINT8                  FailedPorts;
+  FCH_GPP_PORT_CONFIG    *PortCfg;
+  UINT32                 AbIndex;
+  UINT32                 GppData32;
+  UINT8                  EmptyPorts;
+  UINT8                  RetryCounter;
+
+  FailedPorts = 0;
+  EmptyPorts = ActivePorts;
+  RetryCounter = 2;
+
+  while (RetryCounter-- ) {
+    for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
+      if (ActivePorts & (1 << PortId)) {
+        PortCfg = &FchGpp->PortCfg[PortId];
+        if ( PortCfg->PortDetected == TRUE ) {
+          AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (PortId << 24);
+          GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F;
+
+          if ((UINT8) (GppData32) > 0x04) {
+            EmptyPorts &= ~(1 << PortId);
+          }
+
+          if ((UINT8) (GppData32) == 0x10) {
+            break;
+          }
+        }
+      }
+    }
+    FchStall (180, StdHeader);
+  }
+  FailedPorts |= ActivePorts;
+  return FailedPorts;
+}
+
+/**
+ * PreInitGppLink - Enable GPP link training.
+ *
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC VOID
+PreInitGppLink (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  GPP_LINKMODE          CfgMode;
+  UINT8                 PortId;
+  UINT32                GppPortCfg;
+  UINT16                Tmp16Value;
+  UINT8                 GppS3Data;
+  UINT8                 HotPlugPorts;
+
+  UINT8               PortMask[5] = {
+    0x01,
+    0x00,
+    0x03,
+    0x07,
+    0x0F
+  };
+
+  HotPlugPorts = 0;
+  //
+  //  PCIE_GPP_ENABLE (abcfg:0xC0):
+  //
+  //     GPP_LINK_CONFIG ([3:0])  PortA   PortB   PortC   PortD    Description
+  //    ----------------------------------------------------------------------------------
+  //                       0000    0-3                             x4 Config
+  //                       0001                                    N/A
+  //                       0010    0-1     2-3      0              2:2 Config
+  //                       0011    0-1      2       3              2:1:1 Config
+  //                       0100     0       1       2       3      1:1:1:1 Config
+  //
+  //  For A12 and above:
+  //                  ABCFG:0xC0[12] - Port A hold training (default 1)
+  //                  ABCFG:0xC0[13] - Port B hold training (default 1)
+  //                  ABCFG:0xC0[14] - Port C hold training (default 1)
+  //                  ABCFG:0xC0[15] - Port D hold training (default 1)
+  //
+  //
+  //
+  // Set port enable bit fields based on current GPP link configuration mode
+  //
+  CfgMode = FchGpp->GppLinkConfig;
+  ASSERT (CfgMode == PortA4 || CfgMode == PortA2B2 || CfgMode == PortA2B1C1 || CfgMode == PortA1B1C1D1);
+  GppPortCfg = (UINT32) PortMask[CfgMode];
+
+  //
+  // Mask out non-applicable ports according to the target link configuration mode
+  //
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    FchGpp->PortCfg[PortId].PortPresent &= (UINT8 ) (GppPortCfg >> PortId) & BIT0;
+    if ( FchGpp->PortCfg[PortId].PortHotPlug == TRUE ) {
+      HotPlugPorts |= ( 1 << PortId);
+    }
+  }
+
+  //
+  // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
+  //
+  Tmp16Value = (UINT16) (~GppPortCfg << 12);
+  GppPortCfg = (UINT32) (Tmp16Value + (GppPortCfg << 4) + CfgMode);
+  WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), GppPortCfg, StdHeader);
+
+  GppPortCfg = ReadAlink (0xC0 | (UINT32) (RCINDXC << 29), StdHeader);
+  WriteAlink (0xC0 | (UINT32) (RCINDXC << 29), GppPortCfg | 0x400, StdHeader);      /// Set STRAP_F0_MSI_EN
+
+  //
+  // A-Link L1 Entry Delay Shortening
+  // AXINDP_Reg 0xA0[7:4] = 0x3
+  // KR Does not need this portion of code.
+  RwAlink (FCH_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30, StdHeader);
+  RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19, StdHeader);
+  RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28, StdHeader);
+
+  //
+  // GPP L1 Entry Delay Shortening
+  // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.
+  // This is done to reduce number of NAK received with L1 enabled.
+  //
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    RwAlink (FCH_RCINDXP_REGA0 | PortId << 24, 0xFFFFFF0F, 0x10, StdHeader);
+    // Hard System Hang running MeatGrinder Test on multiple blocks
+    // GPP Error Reporting Configuration
+    RwAlink (FCH_RCINDXP_REG6A | PortId << 24, (UINT32)~(BIT1), 0, StdHeader);
+  }
+
+
+  if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) {
+
+    ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data);
+    for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+      if ( GppS3Data & (1 << (PortId + 4))) {
+        if ( GppS3Data & (1 << PortId)) {
+          FchGppForceGen1 (FchGpp, (1 << PortId), StdHeader);
+        } else {
+          FchGppForceGen2 (FchGpp, (1 << PortId), StdHeader);
+        }
+      }
+    }
+  }
+  //
+  // Obtain original Gen2 strap value (LC_GEN2_EN_STRAP)
+  //
+  FchGpp->GppGen2Strap = (UINT8) (ReadAlink (FCH_RCINDXP_REGA4 | 0 << 24, StdHeader) & BIT0);
+  FchGpp->HotPlugPortsStatus = HotPlugPorts;
+}
+
+
+/**
+ * CheckGppLinkStatus - loop polling the link status for each GPP port
+ *
+ *
+ * Return:     ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC UINT8
+CheckGppLinkStatus (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32              PortId;
+  UINT8               PortScanMap;
+  UINT8               GppHwDowngrade;
+  FCH_GPP_PORT_CONFIG  *PortCfg;
+  UINT8               FailedPorts;
+
+  PortScanMap = 0;
+  FailedPorts = 0;
+
+  //
+  // Obtain a list of ports to be checked
+  //
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    PortCfg = &FchGpp->PortCfg[PortId];
+    if ( PortCfg->PortPresent == TRUE && PortCfg->PortDetected == FALSE ) {
+      PortScanMap |= 1 << PortId;
+    }
+  }
+
+  GppHwDowngrade = (UINT8) FchGpp->GppHardwareDownGrade;
+  if (GppHwDowngrade != 0) {
+    //
+    // Skip polling and always assume this port to be present
+    //
+    PortScanMap &= ~(1 << (GppHwDowngrade - 1));
+  }
+
+  FchStall (5000, StdHeader);
+  if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) {
+    AGESA_TESTPOINT (TpFchGppGen2PortPolling, StdHeader);
+    FchGppForceGen2 (FchGpp, PortScanMap, StdHeader);
+    FailedPorts = GppPortPollingLtssm (FchGpp, PortScanMap, TRUE, StdHeader);
+
+    if (FailedPorts) {
+      AGESA_TESTPOINT (TpFchGppGen1PortPolling, StdHeader);
+      FchGppForceGen1 (FchGpp, FailedPorts, StdHeader);
+      FailedPorts = GppPortPollingLtssm (FchGpp, FailedPorts, FALSE, StdHeader);
+    }
+  } else {
+    AGESA_TESTPOINT (TpFchGppGen1PortPolling, StdHeader);
+    FchGppForceGen1 (FchGpp, PortScanMap, StdHeader);
+    FailedPorts = GppPortPollingLtssm (FchGpp, PortScanMap, FALSE, StdHeader);
+  }
+  return FailedPorts;
+}
+
+STATIC
+BOOLEAN
+FoundInfiniteCrs (
+  IN     FCH_GPP             *FchGpp,
+  IN     AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                PortId;
+  UINT32                Value32;
+  UINT32                RegBusNo;
+  UINT32                FchTempBus;
+  FCH_GPP_PORT_CONFIG   *PortCfg;
+
+  FchTempBus = GppGetFchTempBus (StdHeader);
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    PortCfg = &FchGpp->PortCfg[PortId];
+    if ( PortCfg->PortDetected == TRUE ) {
+      RegBusNo = (FchTempBus << 16) + (FchTempBus << 8);
+      WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNo, StdHeader);
+      ReadPci (PCI_ADDRESS (FchTempBus, 0, 0, 0x08), AccessWidth32, &Value32, StdHeader);
+      RegBusNo = 0;
+      WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNo, StdHeader);
+
+      if ( Value32 == 0xFFFFFFFF ) {
+        return TRUE;
+      }
+    }
+  }
+  return FALSE;
+}
+
+
+/**
+ * AfterGppLinkInit
+ *       - Search for display device behind each GPP port
+ *       - If the port is empty AND not hotplug-capable:
+ *           * Turn off link training
+ *           * (optional) Power down the port
+ *           * Hide the configuration space (Turn off the port)
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC VOID
+AfterGppLinkInit (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                PortId;
+  FCH_GPP_PORT_CONFIG   *PortCfg;
+  UINT32                RegBusNumber;
+  UINT32                FchTempBus;
+  UINT32                AbValue;
+  UINT32                AbIndex;
+  UINT8                 Value;
+
+  FchGpp->GppFoundGfxDev = 0;
+  AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
+  //
+  // Link Bandwidth Notification Capability Enable
+  //RCINDC:0xC1[0] = 1
+  //
+  RwAlink (FCH_RCINDXC_REGC1, 0xFFFFFFFF, BIT0, StdHeader);
+
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    //
+    // Program requester ID for every port
+    //
+    AbIndex = FCH_RCINDXP_REG21 | (UINT32) (PortId << 24);
+    WriteAlink (AbIndex, (FCH_GPP_DEV << 3) + PortId, StdHeader);
+    //
+    // Link Bandwidth Notification Capability Enable
+    //PCIe Cfg 0x68[10] = 0
+    //PCIe Cfg 0x68[11] = 0
+    //
+    RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x68), AccessWidth16, (UINT32)~(BIT10 + BIT11), 0, StdHeader);
+
+    PortCfg = &FchGpp->PortCfg[PortId];
+    //
+    // Check if there is GFX device behind each GPP port
+    //
+    FchTempBus = GppGetFchTempBus (StdHeader);
+    if ( PortCfg->PortDetected == TRUE ) {
+      RegBusNumber = (FchTempBus << 16) + (FchTempBus << 8);
+      WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader);
+      ReadPci (PCI_ADDRESS (FchTempBus, 0, 0, 0x0B), AccessWidth8, &Value, StdHeader);
+      if ( Value == 3 ) {
+        FchGpp->GppFoundGfxDev |= (1 << PortId);
+      }
+
+      RegBusNumber = 0;
+      WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader);
+    } else if ( PortCfg->PortPresent == FALSE || PortCfg->PortHotPlug == FALSE ) {
+      //
+      // Mask off non-applicable ports
+      //
+      AbValue &= ~(1 << (PortId + 4));
+    }
+
+    if ( PortCfg->PortHotPlug == TRUE ) {
+      //
+      // Hot Plug: PCIe Native Support
+      // RCINDP_Reg 0x10[3] = 0x1
+      // PCIe_Cfg 0x5A[8] = 0x1
+      // PCIe_Cfg 0x6C[6] = 0x1
+      // RCINDP_Reg 0x20[19] = 0x0
+      //
+      RwAlink ((FCH_RCINDXP_REG10 | (UINT32) (PortId << 24)), 0xFFFFFFFF, BIT3, StdHeader);
+      RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x5b), AccessWidth8, 0xff, BIT0, StdHeader);
+      RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x6c), AccessWidth8, 0xff, BIT6, StdHeader);
+      RwAlink ((FCH_RCINDXP_REG20 | (UINT32) (PortId << 24)), (UINT32)~BIT19, 0, StdHeader);
+    }
+  }
+
+  if ( FchGpp->GppUnhidePorts == FALSE ) {
+    if ((AbValue & 0xF0) == 0) {
+      //comment out the following line for BUG284426: GPP_RESET causes S3 resume hard hang on Pumori
+      //AbValue = BIT8;                // if all ports are empty set GPP_RESET
+    } else if ((AbValue & 0xE0) != 0 && (AbValue & 0x10) == 0) {
+      AbValue |= BIT4;               // PortA should always be visible whenever other ports are exist
+    }
+
+    //
+    // Update GPP_Portx_Enable (abcfg:0xC0[7:5])
+    //
+    WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
+  }
+
+  //
+  // Common initialization for open GPP ports
+  //
+  for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
+    ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader);
+    if (Value != 0xff) {
+      //
+      // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])
+      //
+      Value &= 0xf0;
+      Value |= 0x06;
+      WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader);
+
+      //
+      // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1
+      //
+      AbIndex = FCH_RCINDXP_REG70 | (UINT32) (PortId << 24);
+      AbValue = ReadAlink (AbIndex, StdHeader) | BIT19;
+      WriteAlink (AbIndex, AbValue, StdHeader);
+
+      //
+      // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0
+      //
+      AbIndex = FCH_RCINDXP_REG20 | (UINT32) (PortId << 24);
+      AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT19;
+      WriteAlink (AbIndex, AbValue, StdHeader);
+
+      //
+      // Set Immediate Ack PM_Active_State_Request_L1 (0xA0:[23]) = 1
+      //
+      AbIndex = FCH_RCINDXP_REGA0 | (UINT32) (PortId << 24);
+      AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT23;
+      if ( FchGpp->GppL1ImmediateAck == 0) {
+        AbValue |= BIT23;
+      }
+      WriteAlink (AbIndex, AbValue, StdHeader);
+    }
+  }
+}
+
+
+/**
+ * FchGppAerInitialization - Initializing AER
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC VOID
+FchGppAerInitialization (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  if (FchGpp->PcieAer) {
+    //
+    // GPP strap configuration
+    //
+    RwAlink (0x310  | (UINT32) (ABCFG << 29), (UINT32)~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1, StdHeader);
+    RwAlink (0x314  | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0, StdHeader);
+
+    //
+    // AB strap configuration
+    //
+    RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14, StdHeader);
+    RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3, StdHeader);
+  } else {
+    //
+    // Hard System Hang running MeatGrinder Test on multiple blocks
+    // GPP Error Reporting Configuration
+    RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), (UINT32)~(BIT1), 0, StdHeader);
+  }
+
+}
+
+/**
+ * FchGppRasInitialization - Initializing RAS
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+STATIC VOID
+FchGppRasInitialization (
+  IN       FCH_GPP             *FchGpp,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  if (FchGpp->PcieRas) {
+    RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0, StdHeader);
+  }
+}
+
+
+/**
+ * FchGppPortInit - GPP port training and initialization
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+FchGppPortInit (
+  IN       FCH_GPP               *FchGpp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  //
+  // GppEarlyInit
+  //
+  UINT32             AbValue;
+  UINT8              ResetCounter;
+  UINT8              FailPorts;
+
+  AGESA_TESTPOINT (TpFchGppBeforePortTraining, StdHeader);
+
+  //
+  // Configure NB-FCH link PCIE PHY PLL power down for L1
+  //
+  if ( FchGpp->UmiPhyPllPowerDown == TRUE ) {
+    //
+    // Set PCIE_P_CNTL in Alink PCIEIND space
+    //
+    WriteAlink (FCH_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40, StdHeader);
+    AbValue = ReadAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), StdHeader);
+    AbValue |= BIT12 + BIT3 + BIT0;
+    AbValue &= (UINT32)~(BIT9 + BIT4);
+    WriteAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), AbValue, StdHeader);
+    RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), (UINT32)~(BIT8), (BIT8), StdHeader);
+    RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), (UINT32)~(BIT3), (BIT3), StdHeader);
+  }
+
+  //
+  // AXINDC_Reg 0xA4[18] = 0x1
+  //
+  WriteAlink (FCH_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4, StdHeader);
+  AbValue = ReadAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), StdHeader);
+  AbValue |= BIT18;
+  WriteAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), AbValue, StdHeader);
+
+  //
+  // Set ABCFG 0x031C[0] = 1 to enable lane reversal
+  //
+  AbValue = ReadAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), StdHeader);
+  if ( FchGpp->GppLaneReversal == TRUE ) {
+    WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | BIT0, StdHeader);
+  } else {
+    WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | 0x00, StdHeader);
+  }
+
+  //
+  // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function
+  //
+  AbValue = ReadAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), StdHeader);
+  WriteAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), AbValue | BIT20, StdHeader);
+
+  //
+  // Initialize and configure GPP
+  //
+  if (FchGpp->GppFunctionEnable) {
+    if (( FchGpp->NewGppAlgorithm == FALSE ) || ( (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) )) {
+      ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader);
+    }
+    FchGppAerInitialization (FchGpp, StdHeader);
+    FchGppRasInitialization (FchGpp, StdHeader);
+
+    //
+    // PreInit - Enable GPP link training
+    //
+    if (( FchGpp->NewGppAlgorithm == FALSE ) || ( (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) )) {
+      PreInitGppLink (FchGpp, StdHeader);
+    }
+    //
+    // GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1
+    // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4
+    //
+    if ( FchGpp->GppMemWrImprove == TRUE ) {
+      RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), (UINT32)~BIT26, (BIT26), StdHeader);
+      RwAlink (FCH_RCINDXC_REG10, (UINT32)~(BIT12 + BIT11 + BIT10), (BIT12), StdHeader);
+    }
+
+    if ( FchGpp->NewGppAlgorithm == TRUE ) {
+      if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) {
+        if ( FchGpp->HotPlugPortsStatus == 0 ) {
+        // S3 Procedure
+          FchStall (5000, StdHeader);
+          FailPorts = FchGpp->FailPortsStatus;
+          if ( FchGpp->FailPortsStatus != 0 ) {
+            AGESA_TESTPOINT (TpFchGppGen1PortPolling, StdHeader);
+            FchGppForceGen1 (FchGpp, FailPorts, StdHeader);
+          }
+        }
+      }
+    } else {
+      ResetCounter = 3;
+      while (ResetCounter--) {
+        FailPorts = CheckGppLinkStatus (FchGpp, StdHeader);
+        if (FoundInfiniteCrs (FchGpp, StdHeader)) {
+          ProgramGppTogglePcieReset (TRUE, StdHeader);
+        } else if ((FailPorts != 0) && (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3)) {
+          ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader);
+        } else {
+          break;
+        }
+      }
+    }
+
+    //
+    // Misc operations after link training
+    //
+    if ( FchGpp->NewGppAlgorithm == FALSE ) {
+      AfterGppLinkInit (FchGpp, StdHeader);
+    }
+  }
+  if ( FchGpp->NewGppAlgorithm == FALSE ) {
+    FchGppDynamicPowerSaving (FchGpp, StdHeader);
+    AGESA_TESTPOINT (TpFchGppAfterPortTraining, StdHeader);
+  }
+}
+
+/**
+ * FchGppPortInitS3Phase - GPP port training and initialization S3 phase for new algorithm
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+FchGppPortInitS3Phase (
+  IN       FCH_GPP               *FchGpp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8              ResetCounter;
+  UINT8              FailPorts;
+
+  if (FchGpp->GppFunctionEnable) {
+    ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader);
+    PreInitGppLink (FchGpp, StdHeader);
+    // For S3 With HotPlug port setting.
+    if ( FchGpp->HotPlugPortsStatus != 0 ) {
+      ResetCounter = 3;
+      while (ResetCounter--) {
+        FailPorts = CheckGppLinkStatus (FchGpp, StdHeader);
+        if (FoundInfiniteCrs (FchGpp, StdHeader)) {
+          ProgramGppTogglePcieReset (TRUE, StdHeader);
+        } else if (FailPorts != 0) {
+          ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader);
+        } else {
+          break;
+        }
+      }
+      AfterGppLinkInit (FchGpp, StdHeader);
+    }
+  }
+}
+
+/**
+ * FchGppPortInitPhaseII - GPP port training and initialization phase II for new algorithm
+ *
+ *
+ * @param[in] FchGpp      Pointer to Fch GPP configuration structure
+ * @param[in] StdHeader   Pointer to AMD_CONFIG_PARAMS
+ *
+ */
+VOID
+FchGppPortInitPhaseII (
+  IN       FCH_GPP               *FchGpp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8              ResetCounter;
+  UINT8              FailPorts;
+  UINT8              HotPlugPorts;
+
+  if (FchGpp->GppFunctionEnable) {
+    //
+    // Check Link status for the new algorithm
+    //
+    HotPlugPorts = 0;
+    FailPorts = 0;
+    //
+    // Read previously HotPlug port status
+    //
+    if ( ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) {
+      if ( FchGpp->HotPlugPortsStatus == 0 ) {
+        FailPorts = FchGpp->FailPortsStatus;
+        FailPorts = GppPortPollingLtssmS3 (FchGpp, FailPorts, FALSE, StdHeader);
+        AfterGppLinkInit (FchGpp, StdHeader);
+      }
+    } else {
+      ResetCounter = 3;
+      while (ResetCounter--) {
+        FailPorts = CheckGppLinkStatus (FchGpp, StdHeader);
+        if (FoundInfiniteCrs (FchGpp, StdHeader)) {
+          ProgramGppTogglePcieReset (TRUE, StdHeader);
+        } else if ((FailPorts != 0) && (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3)) {
+          // CMOS record need
+          FchGpp->FailPortsStatus = FailPorts;
+          ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader);
+        } else {
+          // CMOS clear need
+          FchGpp->FailPortsStatus = FailPorts;
+          break;
+        }
+      }
+      AfterGppLinkInit (FchGpp, StdHeader);
+    }
+  }
+  FchGppDynamicPowerSaving (FchGpp, StdHeader);
+  AGESA_TESTPOINT (TpFchGppAfterPortTraining, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c
new file mode 100644
index 0000000000..b12d2c58c1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Gpp controller
+ *
+ * Init Gpp features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE
+
+
+//
+//-----------------------------------------------------------------------------------
+// Early GPP initialization sequence:
+//
+// 1) Set port enable bit fields by current GPP link configuration mode
+// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
+// 3) Loop polling for the link status of all ports
+// 4) Misc operations after link training:
+//      - (optional) Detect GFX device
+//      - Hide empty GPP configuration spaces (Disable empty GPP ports)
+//      - (optional) Power down unused GPP ports
+//      - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
+// 5) GPP init completed
+//
+//
+// *) Gen2 vs Gen1
+//                                   Gen2 mode     Gen1 mode
+//  ---------------------------------------------------------------
+//    STRAP_PHY_PLL_CLKF[6:0]          7'h32         7'h19
+//    STRAP_BIF_GEN2_EN                  1             0
+//
+//    PCIE_PHY_PLL clock locks @       5GHz
+//
+//
+
+/**
+ * FchInitResetGpp - Config Gpp during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetGpp (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  if ( LocalCfgPtr->Gpp.NewGppAlgorithm == TRUE ) {
+    if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) {
+      FchGppPortInitS3Phase (&LocalCfgPtr->Gpp, StdHeader);
+    }
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c
new file mode 100644
index 0000000000..c68064c823
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcie controller
+ *
+ * Init Pcie Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#include "FchDef.h"
+#define FILECODE PROC_FCH_PCIE_PCIEENV_FILECODE
+
+/**
+ * FchInitEnvPcie - Config Pcie before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvPcie (
+  IN  VOID     *FchDataPtr
+  )
+{
+  //
+  // PCIE Native setting
+  //
+  ProgramPcieNativeMode (FchDataPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c
new file mode 100644
index 0000000000..f580710da5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcie controller
+ *
+ * Init Pcie Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_PCIELATE_FILECODE
+
+/**
+ * FchInitLatePcie - Prepare Pcie to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLatePcie (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieMid.c
new file mode 100644
index 0000000000..1474301092
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieMid.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcie controller
+ *
+ * Init Pcie Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_PCIEMID_FILECODE
+
+/**
+ * FchInitMidPcie - Config Pcie after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidPcie (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c
new file mode 100644
index 0000000000..ae79e2ef29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Pcie Component
+ *
+ * Init Pcie features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_PCIE_PCIERESET_FILECODE
+
+/**
+ * FchInitResetPcie - Config Pcie controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetPcie (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciEnv.c
new file mode 100644
index 0000000000..e4b4d5199b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciEnv.c
@@ -0,0 +1,113 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (AHCI mode)
+ *
+ * Init SATA AHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_AHCIENV_FILECODE
+
+/**
+ * FchInitEnvSataAhci - Config SATA Ahci controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSataAhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Class code
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01060140, StdHeader);
+  //
+  // Device ID
+  //
+  if ( LocalCfgPtr->Sata.SataClass == SataAhci7804 ) {
+	  RwPci (((SATA_BUS_DEV_FUN << 16) +  0x02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
+  } else {
+	  RwPci (((SATA_BUS_DEV_FUN << 16) +  0x02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
+  }
+  //
+  // SSID
+  //
+  if (LocalCfgPtr->Sata.SataAhciSsid != 0 ) {
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLate.c
new file mode 100644
index 0000000000..9eb22d1d0f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLate.c
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (AHCI mode)
+ *
+ * Init SATA AHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_AHCILATE_FILECODE
+
+/**
+ * FchInitLateSataAhci - Prepare SATA AHCI controller to boot to
+ * OS.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSataAhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLib.c
new file mode 100644
index 0000000000..625c803a5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLib.c
@@ -0,0 +1,95 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch SATA AHCI controller Library
+ *
+ * SATA AHCI Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_AHCILIB_FILECODE
+
+/**
+ * sataAhciSetDeviceNumMsi - Program AHCI controller support
+ * device number cap & MSI cap
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SataAhciSetDeviceNumMsi (
+  IN  VOID     *FchDataPtr
+  )
+{
+
+  FCH_INTERFACE   *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
+
+  SataSetDeviceNumMsi (LocalCfgPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c
new file mode 100644
index 0000000000..a7ed24d632
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (AHCI mode)
+ *
+ * Init SATA AHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_AHCIMID_FILECODE
+
+/**
+ * FchInitMidSataAhci - Config SATA Ahci controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSataAhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  SataAhciSetDeviceNumMsi (LocalCfgPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
new file mode 100644
index 0000000000..a90771f04b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
@@ -0,0 +1,307 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics Controller family specific service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63460 $   @e \$Date: 2011-12-22 19:04:22 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "FchPlatform.h"
+#include  "Filecode.h"
+#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+//
+// Local Routine
+//
+VOID FchSataCombineControlDataByte (IN UINT8  *ControlReg);
+VOID FchSataCombineControlDataWord (IN UINT16  *ControlReg);
+
+SATA_PHY_SETTING SataPhyTable[] =
+{
+  //Gen3
+  {0x0030, 0x0057A607},
+  {0x0031, 0x0057A607},
+  {0x0032, 0x0057A407},
+  {0x0033, 0x0057A407},
+  {0x0034, 0x0057A607},
+  {0x0035, 0x0057A607},
+  {0x0036, 0x0057A403},
+  {0x0037, 0x0057A403},
+
+  //Gen2
+  {0x0120, 0x00071302},
+
+  //Gen1
+  {0x0110, 0x00174101}
+};
+
+/**
+ * FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
+ * register setting
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvProgramSataPciRegs (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                  *PortRegByte;
+  UINT16                 *PortRegWord;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  //
+  // Caculate SataPortReg for SATA_ESP_PORT
+  //
+  PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
+  FchSataCombineControlDataByte (PortRegByte);
+  PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
+  FchSataCombineControlDataByte (PortRegByte);
+  PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
+  FchSataCombineControlDataWord (PortRegWord);
+  PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
+  FchSataCombineControlDataByte (PortRegByte);
+
+  //
+  // Set Sata PCI Configuration Space Write enable
+  //
+  SataEnableWriteAccess (StdHeader);
+
+  //
+  // Enables the SATA watchdog timer register prior to the SATA BIOS post
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader);
+
+  //
+  // SATA PCI Watchdog timer setting
+  //  Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader);
+
+  //
+  // BIT4:disable fast boot
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, 0xff, BIT4, StdHeader);
+
+  //
+  // Enable IDE DMA read enhancement
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
+
+  //
+  // Unused SATA Ports Disabled
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040  + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
+  //RPR 9.22 Design Enhancement
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 18)), (UINT32) (0x1 << 18), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 20)), (UINT32) (0x1 << 20), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 21)), (UINT32) (0x1 << 21), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x7 << 26)), (UINT32) (0x7 << 26), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x3 << 30)), (UINT32) (0x3 << 30), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x1 << 30)), (UINT32) (0x1 << 30), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 29)), (UINT32) (0x1 << 29), StdHeader);
+}
+
+/**
+ * FchSataCombineControlDataByte - Combine port control options
+ * to one control byte.
+ *
+ *
+ * @param[in] *ControlReg - Data pointer for control byte.
+ *
+ */
+VOID
+FchSataCombineControlDataByte (
+  IN  UINT8    *ControlReg
+  )
+{
+  UINT8   Index;
+  UINT8   PortControl;
+
+  *ControlReg = 0;
+  for ( Index = 0; Index < 8; Index++ ) {
+    PortControl = *( ControlReg + 1 + Index );
+    *ControlReg |= PortControl << Index;
+  }
+}
+/**
+ * FchSataCombineControlDataWord - Combine port control options
+ * to one control Word.
+ *
+ *
+ * @param[in] *ControlReg - Data pointer for control byte.
+ *
+ */
+VOID
+FchSataCombineControlDataWord (
+  IN  UINT16    *ControlReg
+  )
+{
+  UINT8   Index;
+  UINT8   PortControl;
+
+  *ControlReg = 0;
+  for ( Index = 0; Index < 8; Index++ ) {
+    PortControl = *( (UINT8 *)ControlReg + 2 + Index );
+    *ControlReg |= PortControl << (Index * 2);
+  }
+}
+
+
+VOID
+FchProgramSataPhy (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  SATA_PHY_SETTING         *PhyTablePtr;
+  UINT16                   Index;
+
+  PhyTablePtr = &SataPhyTable[0];
+
+  for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader);
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
+    ++PhyTablePtr;
+  }
+
+
+  RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x110, StdHeader);
+  RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C , AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader);
+  RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x10, StdHeader);
+}
+
+/**
+ * FchInitEnvSataRaidProgram - Configuration SATA Raid
+ * controller
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSataRaidProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       SataSSIDValue;
+  UINT32       DeviceId;
+  UINT8        EfuseValue;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Class code
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01040040, StdHeader);
+  //
+  // Device ID
+  //
+  SataSSIDValue = 0;
+  if (LocalCfgPtr->Sata.SataRaid5Ssid != 0 ) {
+    SataSSIDValue = LocalCfgPtr->Sata.SataRaid5Ssid;
+  }
+
+  DeviceId = FCH_SATA_RAID5_DID;
+  EfuseValue = SATA_EFUSE_LOCATION;
+  GetEfuseStatus (&EfuseValue, StdHeader);
+
+  if (( EfuseValue & SATA_EFUSE_BIT ) || ( LocalCfgPtr->Sata.SataForceRaid == 1 )) {
+    DeviceId = FCH_SATA_RAID_DID;
+    if (LocalCfgPtr->Sata.SataRaidSsid != 0 ) {
+      SataSSIDValue = LocalCfgPtr->Sata.SataRaidSsid;
+    }
+  }
+
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, DeviceId, StdHeader);
+  //
+  // SSID
+  //
+  if (SataSSIDValue != 0 ) {
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0, SataSSIDValue, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
new file mode 100644
index 0000000000..be32489094
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
@@ -0,0 +1,166 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Sata controller
+ *
+ * Init Sata Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE
+
+/**
+ * FchInitResetSataProgram - Config Sata controller during
+ * Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetSataProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        SataPortNum;
+  UINT8        PortStatusByte;
+  UINT8        EfuseByte;
+  UINT8        FchSataMode;
+  UINT8        FchSataInternal100Spread;
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //FchSataMode = LocalCfgPtr->Sata.SATA_MODE.SataMode.SataModeReg;
+  //New structure need calculate Sata Register value
+  //
+  FchSataMode = 0;
+  if ( LocalCfgPtr->FchReset.SataEnable ) {
+    FchSataMode |= 0x01;
+  }
+  if ( LocalCfgPtr->Sata6AhciCap ) {
+    FchSataMode |= 0x02;
+  }
+  if ( LocalCfgPtr->SataSetMaxGen2 ) {
+    FchSataMode |= 0x04;
+  }
+  if ( LocalCfgPtr->FchReset.IdeEnable ) {
+    FchSataMode |= 0x08;
+  }
+
+  FchSataMode |= (( LocalCfgPtr->SataClkMode ) << 4 ) ;
+  LocalCfgPtr->SataModeReg = FchSataMode;            ///Save Back to Structure
+
+  FchSataInternal100Spread = ( UINT8 ) LocalCfgPtr->SataInternal100Spread;
+  SataPortNum = 0;
+
+  //
+  // Sata Workaround
+  //
+  for ( SataPortNum = 0; SataPortNum < 0x08; SataPortNum++ ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040  + 2), AccessWidth8, 0xFF, 1 << SataPortNum, StdHeader);
+    FchStall (2, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040  + 2), AccessWidth8, (0xFF ^ (1 << SataPortNum)) , 0x00, StdHeader);
+    FchStall (2, StdHeader);
+  }
+
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084  + 3), AccessWidth8,  (UINT32)~BIT2, 0, StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x0A0 ), AccessWidth8, (UINT32)~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5, StdHeader);
+
+  //
+  // Sata Setting for clock mode only
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0, FchSataMode);
+
+  if ( FchSataInternal100Spread ) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, 0xFF, BIT4);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, 0xFFFFFFFB, 0x00, StdHeader);
+  } else {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, (UINT32)~BIT4, 0x00);
+  }
+
+  EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
+  GetEfuseStatus (&EfuseByte, StdHeader);
+
+  if (EfuseByte & BIT0) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0xFB, 0x04);
+  }
+
+  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, &PortStatusByte);
+  if ( ((PortStatusByte & 0xF0) == 0x10) ) {
+    RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_PMIOA_REG08, AccessWidth8, 0, BIT5);
+  }
+
+  if ( FchSataInternal100Spread ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader);
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
new file mode 100644
index 0000000000..d3eb26308d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
@@ -0,0 +1,711 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics Controller family specific service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "FchPlatform.h"
+#include  "Filecode.h"
+#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8  NumOfSataPorts = 8;
+
+/**
+ * FchSataGpioInitial - Sata GPIO function Procedure
+ *
+ *   - Private function
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSataGpioInitial (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  UINT32       FchSataBarRegDword;
+  UINT32       EMb;
+  UINT32       SataGpioVariableDword;
+  UINT8        FchSataSgpio0;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  Bar5 = 0;
+  EMb = 0;
+  FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0;
+
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  ReadMem (Bar5 + 0x1C , AccessWidth32, &FchSataBarRegDword);
+  EMb = (Bar5 + (( FchSataBarRegDword & 0xFFFF0000) >> 14));
+
+  if ( EMb ) {
+    SataGpioVariableDword = 0x03040C00;
+    WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword);
+    SataGpioVariableDword = 0x00C08240;
+    WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword);
+    SataGpioVariableDword = 0x00000001;
+    WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword);
+
+    if ( FchSataSgpio0 ) {
+      SataGpioVariableDword = 0x00000060;
+    } else {
+      SataGpioVariableDword = 0x00000061;
+    }
+
+    WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
+    RwMem ((Bar5 + 0x20), AccessWidth16, (UINT32)~(BIT8), BIT8);
+
+    do {
+      ReadMem (Bar5 + 0x20 , AccessWidth32, &FchSataBarRegDword);
+      FchSataBarRegDword = FchSataBarRegDword & BIT8;
+    } while ( FchSataBarRegDword != 0 );
+
+    SataGpioVariableDword = 0x03040F00;
+    WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword);
+    SataGpioVariableDword = 0x00008240;
+    WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword);
+    SataGpioVariableDword = 0x00000002;
+    WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword);
+    SataGpioVariableDword = 0x00800000;
+    WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
+    SataGpioVariableDword = 0x0F003700;
+    WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
+    RwMem ((Bar5 + 0x20), AccessWidth16, (UINT32)~(BIT8), BIT8);
+
+    do {
+      ReadMem (Bar5 + 0x20 , AccessWidth32, &FchSataBarRegDword);
+      FchSataBarRegDword = FchSataBarRegDword & BIT8;
+    } while ( FchSataBarRegDword != 0 );
+  }
+}
+
+/**
+ * FchInitMidProgramSataRegs - Sata Pci Configuration Space
+ * register setting
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidProgramSataRegs (
+  IN VOID  *FchDataPtr
+  )
+{
+  UINT8        FchSataMsiCapability;
+  UINT8        FchSataTargetSupport8Device;
+  UINT8        FchSataDisableGenericMode;
+  UINT8        FchSataSgpio0;
+  UINT8        FchSataSgpio1;
+  UINT8        FchSataPhyPllShutDown;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchSataMsiCapability = (UINT8) LocalCfgPtr->Sata.SataMsiCapability;
+  FchSataTargetSupport8Device = (UINT8) LocalCfgPtr->Sata.SataTargetSupport8Device;
+  FchSataDisableGenericMode = (UINT8) LocalCfgPtr->Sata.SataDisableGenericMode;
+  FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0;
+  FchSataSgpio1 = (UINT8) LocalCfgPtr->Sata.SataSgpio1;
+  FchSataPhyPllShutDown = (UINT8) LocalCfgPtr->Sata.SataPhyPllShutDown;
+
+  if ((LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde)) {
+    FchSataMsiCapability = 0;
+  }
+  //
+  // Enabled SATA MSI capability
+  // SATA MSI and D3 Power State Capability
+  //
+  if ( FchSataMsiCapability ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x34), AccessWidth8, 0, 0x50, StdHeader);
+  } else {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x34), AccessWidth8, 0, 0x70, StdHeader);
+  }
+
+  //
+  // Disable SATA FLR Capability
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x70), AccessWidth16, 0x00FF, 0x00, StdHeader);
+
+  //
+  // Sata Target Support 8 devices function
+  //
+  if ( FchSataTargetSupport8Device ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT12, BIT12);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT12, 0x00);
+  }
+
+  //
+  // Sata Generic Mode setting
+  //
+  if ( FchSataDisableGenericMode ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT13, BIT13);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT13, 0x00);
+  }
+
+  //
+  // Sata GPIO Initial
+  //
+  if ( FchSataSgpio0 ) {
+    FchSataGpioInitial ( LocalCfgPtr );
+  }
+
+  if ( FchSataSgpio1 ) {
+    FchSataGpioInitial ( LocalCfgPtr );
+  }
+
+  //
+  // Sata Phy Pll Shutdown setting
+  //
+  if ( FchSataPhyPllShutDown ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, (UINT32)~(BIT6), BIT6, StdHeader);
+  } else {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, (UINT32)~(BIT6), 0x00, StdHeader);
+  }
+
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
+}
+
+
+/**
+ * FchInitLateProgramSataRegs - Sata Pci Configuration Space
+ * register setting
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateProgramSataRegs (
+  IN VOID  *FchDataPtr
+  )
+{
+  UINT8        PortNumByte;
+  UINT32       Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  //
+  //Clear error status
+  //
+  RwMem ((Bar5 + FCH_SATA_BAR5_REG130), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + FCH_SATA_BAR5_REG1B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + FCH_SATA_BAR5_REG230), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + FCH_SATA_BAR5_REG2B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + FCH_SATA_BAR5_REG330), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + FCH_SATA_BAR5_REG3B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + 0x0430 ), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+  RwMem ((Bar5 + 0x04B0 ), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
+
+  for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) {
+    RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00);
+  }
+}
+
+/**
+ * sataBar5RegSet - Sata Bar5 register setting
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SataBar5RegSet (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       AndMaskDword;
+  UINT32       OrMaskDword;
+  UINT32       Bar5;
+  UINT8        EfuseByte;
+  UINT8        FchSataAggrLinkPmCap;
+  UINT8        FchSataPortMultCap;
+  UINT8        FchSataPscCap;
+  UINT8        FchSataSscCap;
+  UINT8        FchSataFisBasedSwitching;
+  UINT8        FchSataCccSupport;
+  UINT8        FchSataAhciEnclosureManagement;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  FchSataAggrLinkPmCap = (UINT8) LocalCfgPtr->Sata.SataAggrLinkPmCap;
+  FchSataPortMultCap = (UINT8) LocalCfgPtr->Sata.SataPortMultCap;
+  FchSataPscCap = (UINT8) LocalCfgPtr->Sata.SataPscCap;
+  FchSataSscCap = (UINT8) LocalCfgPtr->Sata.SataSscCap;
+  FchSataFisBasedSwitching = (UINT8) LocalCfgPtr->Sata.SataFisBasedSwitching;
+  FchSataCccSupport = (UINT8) LocalCfgPtr->Sata.SataCccSupport;
+  FchSataAhciEnclosureManagement = (UINT8) LocalCfgPtr->Sata.SataAhciEnclosureManagement;
+
+  AndMaskDword = 0;
+  OrMaskDword = 0;
+  Bar5 = 0;
+
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
+  GetEfuseStatus (&EfuseByte, LocalCfgPtr->StdHeader);
+
+  if ( !FchSataPortMultCap ) {
+    AndMaskDword |= BIT12;
+  }
+
+  if ( FchSataAggrLinkPmCap ) {
+    OrMaskDword |= BIT11;
+  } else {
+    AndMaskDword |= BIT11;
+  }
+
+  if ( FchSataPscCap ) {
+    OrMaskDword |= BIT1;
+  } else {
+    AndMaskDword |= BIT1;
+  }
+
+  if ( FchSataSscCap ) {
+    OrMaskDword |= BIT26;
+  } else {
+    AndMaskDword |= BIT26;
+  }
+
+  if ( FchSataFisBasedSwitching ) {
+    if (EfuseByte & BIT1) {
+      AndMaskDword |= BIT10;
+    } else {
+      OrMaskDword |= BIT10;
+    }
+  } else {
+    AndMaskDword |= BIT10;
+  }
+
+  //
+  // Disabling CCC (Command Completion Coalescing) support.
+  //
+  if ( FchSataCccSupport ) {
+    OrMaskDword |= BIT19;
+  } else {
+    AndMaskDword |= BIT19;
+  }
+
+  if ( FchSataAhciEnclosureManagement ) {
+    OrMaskDword |= BIT27;
+  } else {
+    AndMaskDword |= BIT27;
+  }
+
+  RwMem ((Bar5 + 0xFC), AccessWidth32, ~AndMaskDword, OrMaskDword);
+
+  //
+  // SATA ESP port setting
+  // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
+  // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
+  // not enable power management (HIPM & DIPM) for these ports.
+  //
+  if ( LocalCfgPtr->Sata.SataEspPort.SataPortReg != 0 ) {
+    RwMem ((Bar5 + 0xF8), AccessWidth32, ~(LocalCfgPtr->Sata.SataEspPort.SataPortReg), 0);
+    RwMem ((Bar5 + 0xF8), AccessWidth32, 0xFF00FF00, (LocalCfgPtr->Sata.SataEspPort.SataPortReg << 16));
+    //
+    // External SATA Port Indication Registers
+    // If any of the ports was programmed as an external port, HCAP.SXS should also be set
+    //
+    RwMem ((Bar5 + 0xFC), AccessWidth32, (UINT32)~(BIT20), BIT20);
+  } else {
+    //
+    // External SATA Port Indication Registers
+    // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
+    //
+    RwMem ((Bar5 + 0xF8), AccessWidth32, 0xFF00FF00, 0x00);
+    RwMem ((Bar5 + 0xFC), AccessWidth32, (UINT32)~(BIT20), 0x00);
+  }
+
+  if ( FchSataFisBasedSwitching ) {
+    if (EfuseByte & BIT1) {
+      RwMem ((Bar5 + 0xF8), AccessWidth32, 0x00FFFFFF, 0x00);
+    } else {
+      RwMem ((Bar5 + 0xF8), AccessWidth32, 0x00FFFFFF, 0xFF000000);
+    }
+  } else {
+    RwMem ((Bar5 + 0xF8), AccessWidth32, 0x00FFFFFF, 0x00);
+  }
+
+  if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) {
+    RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, BIT0);
+  } else {
+    RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, 0x00);
+  }
+}
+
+/**
+ * FchSataSetDeviceNumMsi - Program Sata controller support
+ * device number cap & MSI cap
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSataSetDeviceNumMsi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                 Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  Bar5 = 0;
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  //
+  // RAID or AHCI
+  //
+  if (LocalCfgPtr->Sata.SataMode.IdeEnable == DISABLED) {
+    //
+    // IDE2 Controller is enabled
+    //
+    if (LocalCfgPtr->Sata.SataMode.Sata6AhciCap == ENABLED) {
+      //
+      // 6 AHCI mode
+      //
+      RwMem ((Bar5 + 0x0C), AccessWidth8, 0x00, 0x3F);
+      RwMem ((Bar5 + 0x00), AccessWidth8, (UINT32)~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
+      RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
+      RwMem ((Bar5 + 0xFC), AccessWidth8, 0x07, 0x30);
+    } else {
+      RwMem ((Bar5 + 0x0C), AccessWidth8, 0x00, 0x0F);
+      if ( LocalCfgPtr->Sata.SataCccSupport ) {
+        RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
+        RwMem ((Bar5 + 0xFC), AccessWidth8, 0x07, 0x20);
+      } else {
+        RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2, StdHeader);
+      }
+    }
+  } else {
+    //
+    // IDE2 Controller is disabled
+    //
+    RwMem ((Bar5 + 0x00), AccessWidth8, (UINT32)~(BIT2 + BIT1 + BIT0), BIT2 + BIT1 + BIT0);
+    RwMem ((Bar5 + 0x0C), AccessWidth8, 0x00, 0xFF);
+    if ( LocalCfgPtr->Sata.SataCccSupport ) {
+      RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT3, StdHeader);
+      RwMem ((Bar5 + 0xFC), AccessWidth8, 0x07, 0x40);
+    } else {
+      RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
+    }
+  }
+}
+
+
+/**
+ * FchSataDriveDetection - Sata drive detection
+ *
+ *   - Sata Ide & Sata Ide to Ahci only
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ * @param[in] *Bar5Ptr Sata BAR5 base address.
+ *
+ */
+VOID
+FchSataDriveDetection (
+  IN  VOID       *FchDataPtr,
+  IN  UINT32     *Bar5Ptr
+  )
+{
+  UINT32       SataBarInfo;
+  UINT8        PortNumByte;
+  UINT8        SataPortType;
+  UINT16       IoBaseWord;
+  UINT32       SataLoopVarDWord;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  for ( PortNumByte = 0; PortNumByte < 4; PortNumByte++ ) {
+
+    ReadMem (*Bar5Ptr + FCH_SATA_BAR5_REG128 + PortNumByte * 0x80, AccessWidth32, &SataBarInfo);
+
+    if ( ( SataBarInfo & 0x0F ) == 0x03 ) {
+      if ( PortNumByte & BIT0 ) {
+        //
+        //this port belongs to secondary channel
+        //
+        ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + 0x18), AccessWidth16, &IoBaseWord, StdHeader);
+      } else {
+        //
+        //this port belongs to primary channel
+        //
+        ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + 0x10), AccessWidth16, &IoBaseWord, StdHeader);
+      }
+
+      //
+      //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+      //
+      if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
+        IoBaseWord = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNumByte & BIT0) << 7)) & 0x80 )) );
+      }
+
+      if ( PortNumByte & BIT1 ) {
+        //
+        //this port is slave
+        //
+        SataPortType = 0xB0;
+      } else {
+        //
+        //this port is master
+        //
+        SataPortType = 0xA0;
+      }
+
+      IoBaseWord &= 0xFFF8;
+      LibAmdIoWrite (AccessWidth8, IoBaseWord + 6, &SataPortType, StdHeader);
+
+      //
+      //Wait in loop for 30s for the drive to become ready
+      //
+      for ( SataLoopVarDWord = 0; SataLoopVarDWord < 300000; SataLoopVarDWord++ ) {
+        LibAmdIoRead (AccessWidth8, IoBaseWord + 7, &SataPortType, StdHeader);
+        if ( (SataPortType & 0x88) == 0 ) {
+          break;
+        }
+        FchStall (100, StdHeader);
+      }
+    }
+  }
+}
+
+/**
+ * FchShutdownUnconnectedSataPortClock - Shutdown unconnected
+ * Sata port clock
+ *
+ *   - Sata Ide & Sata Ide to Ahci only
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ * @param[in] Bar5 Sata BAR5 base address.
+ *
+ */
+VOID
+FchShutdownUnconnectedSataPortClock (
+  IN  VOID       *FchDataPtr,
+  IN  UINT32     Bar5
+  )
+{
+  UINT8                  PortNumByte;
+  UINT8                  PortSataStatusByte;
+  UINT8                  NumOfPorts;
+  UINT8                  FchSataClkAutoOff;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  FchSataClkAutoOff = (UINT8) LocalCfgPtr->Sata.SataClkAutoOff;
+
+  NumOfPorts = 0;
+  //
+  // Enable SATA auto clock control by default
+  //
+  for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) {
+    ReadMem (Bar5 + FCH_SATA_BAR5_REG128 + (PortNumByte * 0x80), AccessWidth8, &PortSataStatusByte);
+    //
+    // Shutdown the clock for the port and do the necessary port reporting changes.
+    // Error port status should be 1 not 3
+    //
+    if ( ((PortSataStatusByte & 0x0F) != 0x03) && (! ((LocalCfgPtr->Sata.SataEspPort.SataPortReg) & (1 << PortNumByte))) ) {
+      RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040  + 2), AccessWidth8, 0xFF, (1 << PortNumByte), StdHeader);
+      RwMem (Bar5 + 0x0C, AccessWidth8, ~(1 << PortNumByte), 00);
+    }
+  }                                            ///end of for (PortNumByte=0;PortNumByte<6;PortNumByte++)
+
+  ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte);
+
+  //
+  //if all ports are in disabled state, report at least one port
+  //
+  if ( (PortSataStatusByte & 0xFF) == 0) {
+    RwMem (Bar5 + 0x0C, AccessWidth8, (UINT32) ~(0xFF), 01);
+  }
+
+  ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte);
+
+  for (PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte ++) {
+    if (PortSataStatusByte & (1 << PortNumByte)) {
+      NumOfPorts++;
+    }
+  }
+
+  if ( NumOfPorts == 0) {
+    NumOfPorts = 0x01;
+  }
+
+  RwMem (Bar5 + 0x00, AccessWidth8, 0xE0, NumOfPorts - 1);
+}
+
+/**
+ * FchSataSetPortGenMode - Set Sata port mode (each) for
+ * Gen1/Gen2/Gen3
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSataSetPortGenMode (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  UINT8        PortNumByte;
+  UINT8        PortModeByte;
+  UINT16       SataPortMode;
+  BOOLEAN      FchSataHotRemovalEnh;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchSataHotRemovalEnh = LocalCfgPtr->Sata.SataHotRemovalEnh;
+
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode;
+  PortNumByte = 0;
+
+  while ( PortNumByte < 8 ) {
+    PortModeByte = (UINT8) (SataPortMode & 3);
+    if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) {
+      if ( PortModeByte == BIT0 ) {
+        //
+        // set GEN 1
+        //
+        RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x10);
+      }
+
+      if ( PortModeByte == BIT1 ) {
+        //
+        // set GEN2 (default is GEN3)
+        //
+        RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x20);
+      }
+
+      RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFF, 0x01);
+    }
+
+    SataPortMode >>= 2;
+    PortNumByte ++;
+  }
+
+  FchStall (1000, StdHeader);
+  SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode;
+  PortNumByte = 0;
+
+  while ( PortNumByte < 8 ) {
+    PortModeByte = (UINT8) (SataPortMode & 3);
+
+    if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) {
+      RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFE, 0x00);
+    }
+
+    PortNumByte ++;
+    SataPortMode >>= 2;
+  }
+
+  //
+  // Sata Hot Removal Enhance setting
+  //
+  if ( FchSataHotRemovalEnh ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x80), AccessWidth16, (UINT32)~BIT8, BIT8, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x0A8 ), AccessWidth16, (UINT32)~BIT0, BIT0, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x80), AccessWidth16, (UINT32)~BIT8, 0, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciEnv.c
new file mode 100644
index 0000000000..6f07174fed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciEnv.c
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (Ide2Ahci mode)
+ *
+ * Init SATA Ide2Ahci features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_IDE2AHCIENV_FILECODE
+
+/**
+ * FchInitEnvSataIde2Ahci - Config SATA Ide2Ahci controller
+ * before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSataIde2Ahci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Class code
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01018F40, StdHeader);
+  //
+  // Device ID
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_DID, StdHeader);
+  //
+  // SSID
+  //
+  if (LocalCfgPtr->Sata.SataAhciSsid != 0 ) {
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLate.c
new file mode 100644
index 0000000000..3ff2bdf11f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLate.c
@@ -0,0 +1,116 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (Ide2Ahci mode)
+ *
+ * Init SATA Ide2Ahci features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_IDE2AHCILATE_FILECODE
+
+/**
+ * FchInitLateSataIde2Ahci - Prepare SATA Ide2Ahci controller to
+ * boot to OS.
+ *
+ *              - Set class ID to Ide2Ahci (if set to Ide2Ahci * Mode)
+ *              - Enable Ide2Ahci interrupt
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSataIde2Ahci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //program the AHCI class code
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01060100, StdHeader);
+  //
+  // Device ID
+  //
+  if ( LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
+  } else {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
+  }
+  SataBar5setting (LocalCfgPtr, &Bar5);
+
+  //
+  //Set interrupt enable bit
+  //
+  RwMem ((Bar5 + 0x04), AccessWidth8, (UINT32)~0, BIT1);
+  ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLib.c
new file mode 100644
index 0000000000..9007b51913
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLib.c
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch SATA Ide2Ahci controller Library
+ *
+ * SATA Ide2Ahci Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_IDE2AHCILIB_FILECODE
+
+/**
+ * sataIde2AhciSetDeviceNumMsi - Program Ide2Ahci controller support
+ * device number cap & MSI cap
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SataIde2AhciSetDeviceNumMsi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_INTERFACE   *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
+
+  SataSetDeviceNumMsi (LocalCfgPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c
new file mode 100644
index 0000000000..8cb2fc96f4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c
@@ -0,0 +1,103 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (Ide2Ahci mode)
+ *
+ * Init SATA Ide2Ahci features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_IDE2AHCIMID_FILECODE
+
+/**
+ * FchInitMidSataIde2Ahci - Config SATA Ide2Ahci controller
+ * after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSataIde2Ahci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  SataIde2AhciSetDeviceNumMsi (LocalCfgPtr);
+
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  //
+  //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround.
+  //
+  if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
+    SataDriveDetection (LocalCfgPtr, &Bar5);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c
new file mode 100644
index 0000000000..02b6c258c6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c
@@ -0,0 +1,103 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (Raid mode)
+ *
+ * Init SATA Raid features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_RAIDENV_FILECODE
+
+
+
+//
+// Declaration of local functions
+//
+
+/**
+ * FchInitEnvSataRaid - Config SATA Raid controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSataRaid  (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchInitEnvSataRaidProgram  (FchDataPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c
new file mode 100644
index 0000000000..e5dad1a61b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (Raid mode)
+ *
+ * Init SATA Raid features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_RAIDLATE_FILECODE
+//
+// Declaration of local functions
+//
+
+/**
+ * FchInitLateSataRaid - Prepare SATA Raid controller to boot to
+ * OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSataRaid (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c
new file mode 100644
index 0000000000..a99716285c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c
@@ -0,0 +1,96 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch SATA AHCI/RAID controller Library
+ *
+ * SATA AHCI/RAID Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_RAIDLIB_FILECODE
+
+/**
+ * sataRaidSetDeviceNumMsi - Program RAID controller support
+ * device number cap & MSI cap
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SataRaidSetDeviceNumMsi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_INTERFACE   *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
+
+  SataSetDeviceNumMsi (LocalCfgPtr);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c
new file mode 100644
index 0000000000..fe0fb7cb6d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller (Raid mode)
+ *
+ * Init SATA Raid features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_RAIDMID_FILECODE
+//
+// Declaration of local functions
+//
+
+/**
+ * FchInitMidSataRaid  - Config SATA Raid controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSataRaid (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  SataRaidSetDeviceNumMsi (LocalCfgPtr);
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c
new file mode 100644
index 0000000000..eb9cf10ea7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c
@@ -0,0 +1,132 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller
+ *
+ * Init SATA features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAENV_FILECODE
+
+
+
+/**
+ * FchInitEnvSata - Config SATA controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSata (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
+    return;                                                //return if SATA controller is disabled.
+  }
+
+  FchInitEnvProgramSataPciRegs (FchDataPtr);
+  //
+  // Call Sub-function for each Sata mode
+  //
+  if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
+    FchInitEnvSataAhci ( LocalCfgPtr );
+  }
+
+  if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
+    FchInitEnvSataIde2Ahci ( LocalCfgPtr );
+  }
+
+  if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
+    FchInitEnvSataIde ( LocalCfgPtr );
+  }
+
+  if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
+    FchInitEnvSataRaid ( LocalCfgPtr );
+  }
+
+  //
+  // SATA IRQ Resource
+  //
+  SataSetIrqIntResource (LocalCfgPtr, StdHeader);
+
+  //
+  // SATA PHY Programming Sequence
+  //
+  FchProgramSataPhy (StdHeader);
+
+  SataDisableWriteAccess (StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c
new file mode 100644
index 0000000000..8e2bf7f528
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c
@@ -0,0 +1,115 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch SATA controller Library
+ *
+ * SATA Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAENVLIB_FILECODE
+
+/**
+ * sataSetIrqIntResource - Config SATA IRQ/INT# resource
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ * @param[in] StdHeader
+ *
+ */
+VOID
+SataSetIrqIntResource (
+  IN  VOID                 *FchDataPtr,
+  IN  AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8                  ValueByte;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  //
+  // IRQ14/IRQ15 come from IDE or SATA
+  //
+  ValueByte = 0x08;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &ValueByte, StdHeader);
+  LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
+  ValueByte = ValueByte & 0x0F;
+
+  if (LocalCfgPtr->Sata.SataClass == SataLegacyIde) {
+    ValueByte = ValueByte | 0x50;
+  } else {
+    if (LocalCfgPtr->Sata.SataIdeMode == 1) {
+      //
+      // Both IDE & SATA set to Native mode
+      //
+      ValueByte = ValueByte | 0xF0;
+    }
+  }
+
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeEnv.c
new file mode 100644
index 0000000000..ea6a23da0e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeEnv.c
@@ -0,0 +1,130 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA (IDE mode) controller
+ *
+ * Init SATA IDE (Native IDE) mode features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAIDEENV_FILECODE
+
+/**
+ * FchInitEnvSataIde - Config SATA IDE controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSataIde (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        ChannelByte;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // Class code
+  //
+  if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01018A40, StdHeader);
+  } else {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01018F40, StdHeader);
+  }
+  //
+  // Device ID
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_DID, StdHeader);
+  //
+  // SSID
+  //
+  if (LocalCfgPtr->Sata.SataIdeSsid != 0 ) {
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
+  }
+  //
+  // Sata IDE Channel configuration
+  //
+  ChannelByte = 0x00;
+  ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, &ChannelByte, StdHeader);
+  ChannelByte &= 0xCF;
+
+  if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
+    ChannelByte |= 0x10;
+  }
+
+  if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
+    ChannelByte |= 0x20;
+  }
+
+  WritePci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, &ChannelByte, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c
new file mode 100644
index 0000000000..fac4766e5f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA (IDE mode) controller
+ *
+ * Init SATA IDE (Native IDE) mode features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAIDELATE_FILECODE
+
+/**
+ * FchInitLateSataIde - Prepare SATA controller to boot to OS.
+ *
+ *              - Set class ID to AHCI (if set to AHCI * Mode)
+ *              - Enable AHCI interrupt
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSataIde (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLib.c
new file mode 100644
index 0000000000..6463e25a2b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLib.c
@@ -0,0 +1,73 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch SATA Ide controller Library
+ *
+ * SATA Ide2Ahci Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAIDELIB_FILECODE
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c
new file mode 100644
index 0000000000..ba89d4575c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA (IDE mode) controller
+ *
+ * Init SATA IDE (Native IDE) mode features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAIDEMID_FILECODE
+
+/**
+ * FchInitMidSataIde - Config SATA controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSataIde (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                 Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  Bar5 = 0;
+  SataBar5setting (LocalCfgPtr, &Bar5);
+  //
+  //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround.
+  //
+  if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
+    SataDriveDetection (LocalCfgPtr, &Bar5);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c
new file mode 100644
index 0000000000..3049e92364
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller
+ *
+ * Init SATA features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATALATE_FILECODE
+
+
+
+/**
+ * FchInitLateSata - Prepare SATA controller to boot to OS.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSata (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        SataPciCommandByte;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //Return immediately is sata controller is not enabled
+  //
+  if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
+    return;
+  }
+
+  //
+  // Set Sata PCI Configuration Space Write enable
+  //
+  SataEnableWriteAccess (StdHeader);
+
+  //
+  // Set Sata Controller Memory & IO access enable
+  //
+  ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader);
+
+  //
+  // Call Sub-function for each Sata mode
+  //
+  if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
+    FchInitLateSataAhci ( LocalCfgPtr );
+  }
+
+  if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
+    FchInitLateSataIde2Ahci ( LocalCfgPtr );
+  }
+
+  if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
+    FchInitLateSataIde ( LocalCfgPtr );
+  }
+
+  if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
+    FchInitLateSataRaid ( LocalCfgPtr );
+  }
+
+  FchInitLateProgramSataRegs  ( LocalCfgPtr );
+
+  //
+  // Restore Sata Controller Memory & IO access status
+  //
+  WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
+
+  //
+  // Set Sata PCI Configuration Space Write disable
+  //
+  SataDisableWriteAccess (StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
new file mode 100644
index 0000000000..9208cf77ea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
@@ -0,0 +1,287 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fch SATA controller Library
+ *
+ * SATA Library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATALIB_FILECODE
+
+
+
+/**
+ * sataBar5setting - Config SATA BAR5
+ *
+ *
+ * @param[in] FchDataPtr - Fch configuration structure pointer.
+ * @param[in] *Bar5Ptr   - SATA BAR5 buffer.
+ *
+ */
+VOID
+SataBar5setting (
+  IN  VOID       *FchDataPtr,
+  IN  UINT32     *Bar5Ptr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  //Get BAR5 value
+  //
+  ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x24), AccessWidth32, Bar5Ptr, StdHeader);
+
+  //
+  //Assign temporary BAR if is not already assigned
+  //
+  if ( (*Bar5Ptr == 0) || (*Bar5Ptr == - 1) ) {
+    //
+    //assign temporary BAR5
+    //
+    if ( (LocalCfgPtr->Sata.TempMmio == 0) || (LocalCfgPtr->Sata.TempMmio == - 1) ) {
+      *Bar5Ptr = 0xFEC01000;
+    } else {
+      *Bar5Ptr = LocalCfgPtr->Sata.TempMmio;
+    }
+    WritePci (((SATA_BUS_DEV_FUN << 16) + 0x24), AccessWidth32, Bar5Ptr, StdHeader);
+  }
+
+  //
+  //Clear Bits 9:0
+  //
+  *Bar5Ptr = *Bar5Ptr & 0xFFFFFC00;
+}
+
+/**
+ * sataEnableWriteAccess - Enable Sata PCI configuration space
+ *
+ * @param[in]   StdHeader
+ *
+ */
+VOID
+SataEnableWriteAccess (
+  IN  AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  //
+  // BIT0 Enable write access to PCI header
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, 0xff, BIT0, StdHeader);
+}
+
+/**
+ * sataDisableWriteAccess - Disable Sata PCI configuration space
+ *
+ * @param[in]   StdHeader
+ *
+ */
+VOID
+SataDisableWriteAccess (
+  IN  AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  //
+  // Disable write access to PCI header
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, (UINT32)~BIT0, 0, StdHeader);
+}
+
+
+
+#ifdef SATA_BUS_DEV_FUN_FPGA
+
+/**
+ * FchSataBar5settingFpga
+ *
+ * @param[in]   LocalCfgPtr
+ * @param[in]   Bar5
+ *
+ */
+VOID
+FchSataBar5settingFpga (
+  IN       FCH_DATA_BLOCK     *LocalCfgPtr,
+  IN       UINT32             *Bar5
+  )
+{
+  UINT8  Value;
+
+  //Get BAR5 value
+  ReadPci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x24), AccWidthUint32, Bar5);
+
+  //Assign temporary BAR if is not already assigned
+  if ( (*Bar5 == 0) || (*Bar5 == - 1) ) {
+    //assign temporary BAR5
+    if ( (LocalCfgPtr->Sata.TempMMIO == 0) || (LocalCfgPtr->Sata.TempMMIO == - 1) ) {
+      *Bar5 = 0xFEC01000;
+    } else {
+      *Bar5 = LocalCfgPtr->Sata.TempMMIO;
+    }
+    WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x24), AccWidthUint32, Bar5);
+  }
+
+  //Clear Bits 9:0
+  *Bar5 = *Bar5 & 0xFFFFFC00;
+  Value = 0x07;
+  WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &Value);
+  WritePci (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &Value);
+}
+
+/**
+ * FchSataDriveDetectionFpga
+ *
+ * @param[in]   LocalCfgPtr
+ * @param[in]   Bar5
+ *
+ */
+VOID
+FchSataDriveDetectionFpga (
+  IN       FCH_DATA_BLOCK     *LocalCfgPtr,
+  IN       UINT32             *Bar5
+  )
+{
+  UINT32                 SataBarFpgaInfo;
+  UINT8                  PortNum;
+  UINT8                  SataFpaPortType;
+  UINT16                 IoBase;
+  UINT16                 SataFpgaLoopVarWord;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
+  TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
+
+  for ( PortNum = 0; PortNum < 4; PortNum++ ) {
+    ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
+    if ( ( SataBarFpgaInfo & 0x0F ) == 0x03 ) {
+      if ( PortNum & BIT0 ) {
+        //this port belongs to secondary channel
+        ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + 0x18), AccWidthUint16, &IoBase);
+      } else {
+        //this port belongs to primary channel
+        ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + 0x10), AccWidthUint16, &IoBase);
+      }
+
+      //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+      if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
+        IoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNum & BIT0) << 7)) & 0x80 )) );
+      }
+
+      if ( PortNum & BIT1 ) {
+        //this port is slave
+        SataFpaPortType = 0xB0;
+      } else {
+        //this port is master
+        SataFpaPortType = 0xA0;
+      }
+
+      IoBase &= 0xFFF8;
+      LibAmdIoWrite (AccessWidth8, IoBase + 6, &SataFpaPortType, StdHeader);
+
+      //Wait in loop for 30s for the drive to become ready
+      for ( SataFpgaLoopVarWord = 0; SataFpgaLoopVarWord < 300000; SataFpgaLoopVarWord++ ) {
+        LibAmdIoRead (AccessWidth8, IoBase + 7, &SataFpaPortType, StdHeader);
+        if ( (SataFpaPortType & 0x88) == 0 ) {
+          break;
+        }
+        FchStall (100, StdHeader);
+      }
+    }
+  }
+}
+
+/**
+ * FchSataDriveFpga -
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSataDriveFpga (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                 Bar5;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  Bar5 = 0;
+  SataBar5setting (LocalCfgPtr, &Bar5);
+
+  FchSataBar5settingFpga (LocalCfgPtr, &Bar5);
+  FchSataDriveDetectionFpga (LocalCfgPtr, &Bar5);
+}
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataMid.c
new file mode 100644
index 0000000000..09d6dc7f5d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataMid.c
@@ -0,0 +1,225 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SATA controller
+ *
+ * Init SATA features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATAMID_FILECODE
+
+
+
+/**
+ * FchInitMidSata - Config SATA controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSata (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        SataPciCommandByte;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
+    return;                                                ///return if SATA controller is disabled.
+  }
+
+  //
+  // Set Sata PCI Configuration Space Write enable
+  //
+  SataEnableWriteAccess (StdHeader);
+
+  //
+  // Set Sata Controller Memory & IO access enable
+  //
+  ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader);
+
+  //
+  // Sata Bar5 register setting for Index 0xFC
+  //
+  SataBar5RegSet ( LocalCfgPtr );
+
+  FchInitMidProgramSataRegs ( LocalCfgPtr );
+
+  //
+  // Set Sata port mode (each) for Gen1/Gen2/Gen3
+  //
+  SataSetPortGenMode ( LocalCfgPtr );
+
+  //
+  // Call Sub-function for each Sata mode
+  //
+  if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
+    FchInitMidSataAhci ( LocalCfgPtr );
+  }
+
+  if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
+    FchInitMidSataIde2Ahci ( LocalCfgPtr );
+  }
+
+  if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
+    FchInitMidSataIde ( LocalCfgPtr );
+  }
+
+  if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
+    FchInitMidSataRaid ( LocalCfgPtr );
+  }
+
+#ifdef SATA_BUS_DEV_FUN_FPGA
+  FchSataDriveFpga ( LocalCfgPtr );
+#endif
+
+  //
+  // Restore Sata Controller Memory & IO access status
+  //
+  WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
+
+  //
+  // Set Sata PCI Configuration Space Write disable
+  //
+  SataDisableWriteAccess (StdHeader);
+}
+
+/**
+ * SataSetDeviceNumMsi - Program Sata controller support device
+ * number cap & MSI cap
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SataSetDeviceNumMsi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchSataSetDeviceNumMsi ( FchDataPtr );
+}
+
+/**
+ * SataDriveDetection - Sata drive detection
+ *
+ *   - Sata Ide & Sata Ide to Ahci only
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ * @param[in] *Bar5Ptr Sata BAR5 base address.
+ *
+ */
+VOID
+SataDriveDetection (
+  IN  VOID       *FchDataPtr,
+  IN  UINT32     *Bar5Ptr
+  )
+{
+  FchSataDriveDetection ( FchDataPtr, Bar5Ptr );
+}
+
+/**
+ * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
+ *
+ *   - Sata Ide & Sata Ide to Ahci only
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ * @param[in] Bar5 Sata BAR5 base address.
+ *
+ */
+VOID
+ShutdownUnconnectedSataPortClock (
+  IN  VOID       *FchDataPtr,
+  IN  UINT32     Bar5
+  )
+{
+  FchShutdownUnconnectedSataPortClock ( FchDataPtr, Bar5);
+}
+
+/**
+ * SataSetPortGenMode - Set Sata port mode (each) for
+ * Gen1/Gen2/Gen3
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SataSetPortGenMode (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchSataSetPortGenMode ( FchDataPtr );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c
new file mode 100644
index 0000000000..f790887886
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Sata controller
+ *
+ * Init Sata Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SATA_SATARESET_FILECODE
+
+
+
+/**
+ * FchInitResetSata - Config Sata controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetSata (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitResetSataProgram ( FchDataPtr );
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c
new file mode 100644
index 0000000000..5df3a78094
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c
@@ -0,0 +1,133 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 SD
+ *
+ * Init SD Controller.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE
+
+/**
+ * FchInitEnvSdProgram - Config SD controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSdProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                 SdData32;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+  UINT8                  SdClockControl;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  SdClockControl = (UINT8) (LocalCfgPtr->Sd.SdClockControl);
+  if (( SdClockControl != 4 ) && ( SdClockControl != 6 ) && ( SdClockControl != 7 ))  {
+    SdClockControl = 4;
+  }
+  SdClockControl = SdClockControl << 1;
+  //
+  // SD Configuration
+  //
+  if ( LocalCfgPtr->Sd.SdConfig != SdDisable) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE +  0xD3 , AccessWidth8, 0xBF, 0x40);
+    RwMem (ACPI_MMIO_BASE + MISC_BASE +  FCH_MISC_REG41, AccessWidth8, 0xF1, 0x40 | SdClockControl );
+    RwMem (ACPI_MMIO_BASE + MISC_BASE +  FCH_MISC_REG42, AccessWidth8, 0xFE, 0x00);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE +  FCH_PMIOA_REGE7, AccessWidth8, 0x00, 0x12);
+
+    ReadPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccessWidth32, &SdData32, StdHeader);
+    SdData32 |= BIT31 + BIT24 + BIT18 + BIT16;     ///ADMA
+
+    if ( LocalCfgPtr->Sd.SdConfig == SdDma) {
+      SdData32 &=  ~(BIT16 + BIT24);               ///DMA
+    } else if ( LocalCfgPtr->Sd.SdConfig == SdPio) {
+      SdData32 &=  ~(BIT16 + BIT18 + BIT24);       ///PIO
+    }
+
+    SdData32 &= ~(BIT17 + BIT23);                  ///clear bitwidth
+    SdData32 |= (LocalCfgPtr->Sd.SdSpeed << 17) + (LocalCfgPtr->Sd.SdBitWidth << 23);
+    RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccessWidth32, 0, SdData32, StdHeader);
+
+    // SD: Some SD cards cannot be detected in HIGH speed mode
+    RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0, AccessWidth32, (UINT32) (~ (0x03 << 10)), (UINT32) (0x03 << 10), StdHeader);
+    if (LocalCfgPtr->Sd.SdSsid != 0 ) {
+      RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REG2C, AccessWidth32, 0, LocalCfgPtr->Sd.SdSsid, StdHeader);
+    }
+    RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGAC, AccessWidth32, ~(UINT32)BIT1, 0, StdHeader);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE +  0xD3 , AccessWidth8, 0xBF, 0x00);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c
new file mode 100644
index 0000000000..0c7f93ff06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c
@@ -0,0 +1,73 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 SD Controller
+ *
+ * Init SD Controller.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
new file mode 100644
index 0000000000..c7b59b74f2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Hudson2 SD Controller
+ *
+ * Init SD Controller.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c
new file mode 100644
index 0000000000..547ebad029
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c
@@ -0,0 +1,93 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SD controller
+ *
+ * Init SD Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SD_SDENV_FILECODE
+
+
+/**
+ * FchInitEnvSd - Config SD controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSd (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  FchInitEnvSdProgram (FchDataPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c
new file mode 100644
index 0000000000..f6da5d8fc2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SD controller
+ *
+ * Init SD Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SD_SDLATE_FILECODE
+
+/**
+ * FchInitLateSd - Prepare SD controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSd (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c
new file mode 100644
index 0000000000..0b1e7b79a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch SD controller
+ *
+ * Init SD Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SD_SDMID_FILECODE
+
+/**
+ * FchInitMidSd - Config SD controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSd (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
new file mode 100644
index 0000000000..236b4c5e93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch LPC controller
+ *
+ * Init LPC Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE
+
+/**
+ * FchInitHudson2EnvLpcPciTable - PCI device registers initial
+ * during early POST.
+ *
+ */
+REG8_MASK FchInitHudson2EnvLpcPciTable[] =
+{
+  //
+  // LPC Device (Bus 0, Dev 20, Func 3)
+  //
+  {0x00, LPC_BUS_DEV_FUN, 0},
+  {FCH_LPC_REG40, (UINT8)~BIT2, BIT2},                             /// Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b
+  {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+  {0x78 , 0xFC, 00},                                /// Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b / Disables MSI capability
+  {FCH_LPC_REGBB, (UINT8)~BIT0, (BIT0 + BIT3 + BIT4 + BIT5)},        /// Enabled SPI Prefetch from HOST.
+  {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * FchInitEnvLpcProgram - Config LPC controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvLpcProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), sizeof (FchInitHudson2EnvLpcPciTable) / sizeof (REG8_MASK), StdHeader);
+
+  //
+  // Disable LPC A-Link Cycle Bypass
+  //
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 2, AccessWidth8, 0xF7, BIT3);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
new file mode 100644
index 0000000000..cd8ac2fb29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch LPC controller
+ *
+ * Init LPC Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCRESETSERVICE_FILECODE
+
+/**
+ * FchInitHudson2ResetLpcPciTable - Lpc (Spi) device registers
+ * initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+REG8_MASK FchInitHudson2ResetLpcPciTable[] =
+{
+  //
+  // LPC Device (Bus 0, Dev 20, Func 3)
+  //
+  {0x00, LPC_BUS_DEV_FUN, 0},
+
+  {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+  {FCH_LPC_REG7C, 0x00, BIT0 + BIT2},
+  {0x78 , 0xF0, BIT2 + BIT3},                       /// Enable LDRQ pin
+  {FCH_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
+  //
+  // Set 0xBB [5:3] = 111 to improve SPI timing margin.
+  // Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
+  //
+  {FCH_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
+  {FCH_LPC_REGBA, 0x9F, BIT5 + BIT6},
+  // Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
+  {FCH_LPC_REGA4, (UINT8)~ BIT0, BIT0},
+  {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * FchInitResetLpcProgram - Config Lpc controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetLpcProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  //
+  // enable prefetch on Host, set LPC cfg 0xBB bit 0 to 1
+  //
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
+
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader);
+
+  ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
+
+  //
+  // Enabling ClkRun Function
+  //
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, 0xFB, BIT2, StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGD0, AccessWidth8, 0xFB, 0, StdHeader);
+  //
+  // LPC CLK0 Power-Down Function
+  //
+  if (!IsImcEnabled (StdHeader)) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, 0xFF, BIT3);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, (UINT32)~ (BIT3), 0);
+  }
+
+  if ( LocalCfgPtr->LegacyFree ) {
+    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C000, StdHeader);
+  } else {
+    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0xFF03FFD5, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c
new file mode 100644
index 0000000000..8c154a5fa1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch LPC controller
+ *
+ * Init LPC Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_LPCENV_FILECODE
+
+
+
+/**
+ * FchInitEnvLpc - Config LPC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvLpc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  //
+  // LPC CFG programming
+  //
+  //
+  // Turn on and configure LPC clock (48MHz)
+  //
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 2 << 19);
+  RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT7, 0);
+
+  //
+  // Initialization of pci config space
+  //
+  FchInitEnvLpcProgram (FchDataPtr);
+
+  //
+  // SSID for LPC Controller
+  //
+  if (LocalCfgPtr->Spi.LpcSsid != 0 ) {
+    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Spi.LpcSsid, StdHeader);
+  }
+  //
+  // LPC MSI
+  //
+  if ( LocalCfgPtr->Spi.LpcMsiEnable ) {
+    RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78 , AccessWidth32, (UINT32)~BIT1, (UINT32)BIT1, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcLate.c
new file mode 100644
index 0000000000..4d2d7e6b7d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcLate.c
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch LPC controller
+ *
+ * Init LPC Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_LPCLATE_FILECODE
+
+/**
+ * FchInitLateLpc - Prepare Ir controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateLpc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, 0xBF, BIT3 + BIT4 + BIT5, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcMid.c
new file mode 100644
index 0000000000..428cb7e2ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcMid.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch LPC controller
+ *
+ * Init LPC Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_LPCMID_FILECODE
+
+/**
+ * FchInitMidLpc - Config Lpc controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidLpc (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c
new file mode 100644
index 0000000000..0c3607afe1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch LPC controller
+ *
+ * Init LPC Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_LPCRESET_FILECODE
+
+
+
+/**
+ * FchInitResetLpc - Config Lpc controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetLpc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  FchInitResetLpcProgram (FchDataPtr);
+
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiEnv.c
new file mode 100644
index 0000000000..562c274907
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiEnv.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Spi (Lpc) controller
+ *
+ * Init Spi (Lpc) Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_SPIENV_FILECODE
+
+/**
+ * FchInitEnvSpi - Config Spi controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvSpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitEnvLpc (FchDataPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiLate.c
new file mode 100644
index 0000000000..b8016ae934
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiLate.c
@@ -0,0 +1,140 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Spi (Lpc) controller
+ *
+ * Init Spi (Lpc) Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_SPILATE_FILECODE
+
+/**
+ * FchInitLateSpi - Prepare Spi controller to boot to OS.
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateSpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitLateLpc (FchDataPtr);
+}
+
+/**
+ * FchSpiUnlock - Fch SPI Unlock
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+FchSpiUnlock (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                  SpiRomBase;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  SpiRomBase = LocalCfgPtr->Spi.RomBaseAddress;
+
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader);
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~(BIT22 + BIT23), (UINT32)(BIT22 + BIT23));
+}
+
+/**
+ * FchSpiLock - Fch SPI lock
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+FchSpiLock (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                  SpiRomBase;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  SpiRomBase = LocalCfgPtr->Spi.RomBaseAddress;
+
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader);
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~(BIT22 + BIT23), 0);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiMid.c
new file mode 100644
index 0000000000..c924ee2a58
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiMid.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Spi (Lpc) controller
+ *
+ * Init Spi (Lpc) Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_SPIMID_FILECODE
+
+/**
+ * FchInitMidSpi - Config Spi controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidSpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitMidLpc (FchDataPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c
new file mode 100644
index 0000000000..f1f62b1b3f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c
@@ -0,0 +1,543 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Spi controller
+ *
+ * Init Spi Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 64064 $   @e \$Date: 2012-01-15 22:36:53 -0600 (Sun, 15 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_SPI_SPIRESET_FILECODE
+
+/**
+ * FchDummy2 - Dummy2
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ *
+ */
+VOID
+FchDummy2 (
+  IN  UINT32     SpiRomBase
+  );
+
+VOID
+FchDummy (
+  IN  UINT32     SpiRomBase
+  );
+
+VOID
+FchSpiExecute (
+  IN  UINT32     SpiRomBase
+  );
+
+VOID
+FchResetFifo (
+  IN  UINT32     SpiRomBase
+  );
+
+VOID
+FchResetFifoToLast (
+  IN  UINT32     SpiRomBase
+  );
+
+UINT32
+FchReadSpiId (
+  IN  UINT32     SpiRomBase,
+  IN  BOOLEAN    Flag
+  );
+
+BOOLEAN
+FchReadSpiQe (
+  IN  UINT32     SpiRomBase,
+  IN  UINT32     DeviceID
+  );
+
+VOID
+FchWriteSpiQe (
+  IN  UINT32     SpiRomBase,
+  IN  UINT32     DeviceID
+  );
+
+VOID
+FchSetQualMode (
+  IN  UINT32      SpiQualMode,
+  IN  UINT32     SpiRomBase,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+VOID
+FchClearQualMode (
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+BOOLEAN
+FchCheckSpiQe (
+  IN  UINT32     SpiRomBase,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/**
+ * FchDummy - Dummy
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ *
+ */
+VOID
+FchDummy (
+  IN  UINT32     SpiRomBase
+  )
+{
+  ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00);
+}
+/**
+ * FchSpiExecute - SPI Execute
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ *
+ */
+VOID
+FchSpiExecute (
+  IN  UINT32     SpiRomBase
+  )
+{
+  UINT32 SpiReg00;
+  SpiReg00 = BIT31 + BIT16;
+  ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT16;
+  do {
+    SpiReg00 = ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00);
+  } while ((SpiReg00 & (BIT31 + BIT16)));
+}
+/**
+ * FchResetFifo - Reset SPI FIFO
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ *
+ */
+VOID
+FchResetFifo (
+  IN  UINT32     SpiRomBase
+  )
+{
+  ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT20;
+  //ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT21;
+}
+/**
+ * FchResetFifoToLast - Reset SPI FIFO to last
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ *
+ */
+VOID
+FchResetFifoToLast (
+  IN  UINT32     SpiRomBase
+  )
+{
+  ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT20;
+}
+
+/**
+ * FchReadSpiId - Read SPI ID
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ * @param[in] Flag       - Read Flag.
+ *
+ */
+UINT32
+FchReadSpiId (
+  IN  UINT32     SpiRomBase,
+  IN  BOOLEAN    Flag
+  )
+{
+  UINT32 DeviceID;
+  UINT8 i;
+  DeviceID = 0;
+  if (Flag) {
+    ACPIMMIO16 (SpiRomBase + FCH_SPI_MMIO_REG00) = 0x409F;
+    FchSpiExecute (SpiRomBase);
+    FchResetFifo (SpiRomBase);
+    for (i = 0; i < 3; i++) {
+      DeviceID |= ((UINT32) (ACPIMMIO8 (SpiRomBase + FCH_SPI_MMIO_REG0C)) << (i*8));
+    }
+  } else {
+    FchDummy (SpiRomBase);
+    FchDummy2 (SpiRomBase);
+  }
+  return DeviceID;
+}
+/**
+ * FchReadSpiQe - Read SPI Qual Enable
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ * @param[in] DeviceID   - Devic ID.
+ *
+ */
+BOOLEAN
+FchReadSpiQe (
+  IN  UINT32     SpiRomBase,
+  IN  UINT32     DeviceID
+  )
+{
+  UINT8 StatusLen;
+  UINT8 dbStatus;
+  UINT8 dbStatus1;
+  UINT8 StatusRead;
+  UINT8 StatusWrite;
+  UINT8 QualEnable;
+  UINT8 QualEnable1;
+
+  StatusLen = 0x02;
+  StatusRead = 0x05;
+  StatusWrite = 0x01;
+  QualEnable = 0;
+  QualEnable1 = 0;
+
+  switch (DeviceID) {
+  case 0x0024C2: //Macronix_MX25L1633E
+  case 0x0025C2: //Macronix_MX25L1636E
+  case 0x005EC2: //Macronix_MX25L3235D
+  case 0x165EC2: //Macronix_MX25L3235D:tested
+    QualEnable = 0x40;
+    break;
+
+  case 0x0014ef: //Wnbond_W25X16= S25FL016K
+  case 0x004015: //Wnbond_W25Q16CV
+    StatusLen = 0x02;
+    StatusRead = 0x35;
+    QualEnable1 = 0x02;
+    break;
+
+  case 0x00861F: //Atmel_AT25DQ161
+    StatusRead = 0x3F;
+    StatusRead = 0x3E;
+    QualEnable = 0x80;
+    break;
+
+  default:
+    return FALSE;
+  }
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, (StatusLen << 12) | StatusRead);
+  FchSpiExecute (SpiRomBase);
+  FchResetFifo (SpiRomBase);
+  ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus);
+  ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus);
+  ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus1);
+  if ((dbStatus & QualEnable) || (dbStatus1 & QualEnable1) ) {
+    return TRUE;
+  }
+  return FALSE;
+}
+/**
+ * FchWriteSpiQe - Write SPI Qual Enable
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ * @param[in] DeviceID   - Devic ID.
+ *
+ */
+VOID
+FchWriteSpiQe (
+  IN  UINT32     SpiRomBase,
+  IN  UINT32     DeviceID
+  )
+{
+  UINT8 StatusLen;
+  UINT8 StatusWriteLen;
+  UINT8 dbStatus;
+  UINT8 dbStatus1;
+  UINT8 StatusRead;
+  UINT8 StatusWrite;
+  UINT8 QualEnable;
+  UINT8 QualEnable1;
+
+  StatusLen = 0x02;
+  StatusRead = 0x05;
+  StatusWrite = 0x01;
+  StatusWriteLen = 0x01;
+  QualEnable = 0;
+  QualEnable1 = 0;
+
+  switch (DeviceID) {
+  case 0x0024C2: //Macronix_MX25L1633E
+  case 0x0025C2: //Macronix_MX25L1636E
+  case 0x005EC2: //Macronix_MX25L3235D
+  case 0x165EC2: //Macronix_MX25L3235D:tested
+    QualEnable = 0x40;
+    break;
+
+  case 0x0014ef: //Wnbond_W25X16= S25FL016K
+  case 0x004015: //Wnbond_W25Q16CV
+    StatusLen = 0x02;
+    StatusRead = 0x35;
+    QualEnable1 = 0x02;
+    break;
+
+  case 0x00861F: //Atmel_AT25DQ161
+    StatusRead = 0x3F;
+    StatusRead = 0x3E;
+    QualEnable = 0x80;
+    break;
+
+  default:
+    return ;
+  }
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, (StatusLen << 12) | StatusRead);
+  FchSpiExecute (SpiRomBase);
+  FchResetFifo (SpiRomBase);
+  ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus);
+  ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus1);
+
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, 0x0006);
+  FchSpiExecute (SpiRomBase);
+
+  FchResetFifo (SpiRomBase);
+  dbStatus |= QualEnable;
+  dbStatus1 |= QualEnable1;
+  WriteMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus);
+  WriteMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus1);
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, (StatusWriteLen << 8) | StatusWrite);
+  FchSpiExecute (SpiRomBase);
+}
+/**
+ * FchSetQualMode - Set SPI Qual Mode
+ *
+ *
+ *
+ * @param[in] SpiQualMode- Spi Qual Mode.
+ * @param[in] SpiRomBase - Spi Rom Base.
+ * @param[in] StdHeader  - Standard Header.
+ *
+ */
+VOID
+FchSetQualMode (
+  IN  UINT32      SpiQualMode,
+  IN  UINT32     SpiRomBase,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG09, AccessWidth8, (UINT32)~BIT3, (UINT32)BIT3);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, (UINT32)~BIT0, (UINT32)BIT0, StdHeader);
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~( BIT18 + BIT29 + BIT30), ((SpiQualMode & 1) << 18) + ((SpiQualMode & 6) << 28));
+}
+/**
+ * FchClearQualMode - Clear SPI Qual Mode
+ *
+ *
+ *
+ * @param[in] StdHeader  - Standard Header.
+ *
+ */
+VOID
+FchClearQualMode (
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT32                    SpiRomBase;
+  //
+  // Get Spi ROM Base Address
+  //
+  ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA0, AccessWidth32, &SpiRomBase, StdHeader);
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~( BIT18 + BIT29 + BIT30), 0);
+  RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG09, AccessWidth8, (UINT32)~BIT3, 0);
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, (UINT32)~ BIT0, 0, StdHeader);
+}
+/**
+ * FchCheckSpiQe - Check SPI Qual Enable
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ * @param[in] StdHeader  - Standard Header.
+ *
+ */
+BOOLEAN
+FchCheckSpiQe (
+  IN  UINT32     SpiRomBase,
+  IN  AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT32 DeviceID;
+  //FchClearQualMode (SpiRomBase, StdHeader);
+  FchReadSpiId (SpiRomBase, FALSE);
+  DeviceID = FchReadSpiId (SpiRomBase, TRUE);
+  //if (DeviceID != 0x165EC2) FCH_DEADLOOP();
+  switch (DeviceID) {
+  case 0x0024C2: //Macronix_MX25L1633E
+  case 0x0025C2: //Macronix_MX25L1636E
+  case 0x005EC2: //Macronix_MX25L3235D
+  case 0x165EC2: //Macronix_MX25L3235D:tested
+  case 0x0014ef: //Wnbond_W25X16= S25FL016K
+  case 0x004015: //Wnbond_W25Q16CV
+  case 0x00861F: //Atmel_AT25DQ161
+    if (FchReadSpiQe (SpiRomBase, DeviceID)) {
+      return TRUE;
+    } else {
+      do {
+        FchWriteSpiQe (SpiRomBase, DeviceID);
+        if (FchReadSpiQe (SpiRomBase, DeviceID)) {
+          return TRUE;
+        }
+      } while (!FchReadSpiQe (SpiRomBase, DeviceID));
+    }
+    break;
+  }
+  return FALSE;
+}
+/**
+ * FchInitResetSpi - Config Spi controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetSpi (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32                    SpiModeByte;
+  UINT32                    SpiRomBase;
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  SpiRomBase = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
+
+  //
+  // Set Spi ROM Base Address
+  //
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA0, AccessWidth32, 0x001F, SpiRomBase, StdHeader);
+
+  //
+  //  Spi Mode Initial
+  //
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, 0xFFC0FFFF, 0 );
+
+  if (LocalCfgPtr->SpiSpeed) {
+    RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, (UINT32)~(BIT13 + BIT12), ((LocalCfgPtr->SpiSpeed - 1 ) << 12));
+  }
+
+  if (LocalCfgPtr->FastSpeed) {
+    RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, (UINT32)~(BIT15 + BIT14), ((LocalCfgPtr->FastSpeed - 1 ) << 14));
+  }
+
+  RwMem (SpiRomBase + FCH_SPI_MMIO_REG1C, AccessWidth32, (UINT32)~(BIT10), ((LocalCfgPtr->BurstWrite) << 10));
+
+  SpiModeByte = LocalCfgPtr->Mode;
+  if (LocalCfgPtr->Mode) {
+    if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144)) {
+      if (FchCheckSpiQe (SpiRomBase, StdHeader)) {
+        FchSetQualMode (SpiModeByte, SpiRomBase, StdHeader);
+      }
+    } else {
+      RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~( BIT18 + BIT29 + BIT30), ((LocalCfgPtr->Mode & 1) << 18) + ((LocalCfgPtr->Mode & 6) << 28));
+    }
+  } else {
+    if (FchCheckSpiQe (SpiRomBase, StdHeader)) {
+      SpiModeByte = FCH_SPI_MODE_QUAL_144;
+      //FchSetQualMode (SpiModeByte, SpiRomBase, StdHeader);
+    }
+  }
+  // Enabling SPI ROM Prefetch
+  // Set LPC cfg 0xBA bit 8
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
+
+  // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1.
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT7, StdHeader);
+}
+/**
+ * FchDummy2 - Dummy2
+ *
+ *
+ *
+ * @param[in] SpiRomBase - Spi Rom Base.
+ *
+ */
+VOID
+FchDummy2 (
+  IN  UINT32     SpiRomBase
+  )
+{
+  ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciEnv.c
new file mode 100644
index 0000000000..babd852dcc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciEnv.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB EHCI controller
+ *
+ * Init USB EHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_EHCIENV_FILECODE
+
+/**
+ * FchInitEnvUsbEhci - Config USB EHCI controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvUsbEhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciLate.c
new file mode 100644
index 0000000000..819aa1a06d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciLate.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB EHCI controller
+ *
+ * Init USB EHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_EHCILATE_FILECODE
+
+/**
+ * FchInitLateUsbEhci - Config USB EHCI controller before OS
+ * boot
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateUsbEhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c
new file mode 100644
index 0000000000..8afb6d0130
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB EHCI controller
+ *
+ * Init USB EHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_EHCIMID_FILECODE
+
+/* extern VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); */
+//
+// Declaration of local functions
+//
+/**
+ * EhciInitAfterPciInit - Config USB controller after PCI emulation
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ */
+VOID EhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+
+/**
+ * FchInitMidUsbEhci - Config USB EHCI controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbEhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+
+  FchInitMidUsbEhci1 (LocalCfgPtr);
+  FchInitMidUsbEhci2 (LocalCfgPtr);
+  FchInitMidUsbEhci3 (LocalCfgPtr);
+}
+
+/**
+ * FchInitMidUsbEhci1 - Config USB1 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbEhci1 (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+
+  DeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
+  EhciInitAfterPciInit (DeviceId, FchDataPtr);
+
+}
+
+/**
+ * FchInitMidUsbEhci2 - Config USB2 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbEhci2 (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+
+  DeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
+  EhciInitAfterPciInit (DeviceId, FchDataPtr);
+
+}
+
+/**
+ * FchInitMidUsbEhci3 - Config USB3 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+
+VOID
+FchInitMidUsbEhci3 (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+
+  DeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
+  EhciInitAfterPciInit (DeviceId, FchDataPtr);
+
+}
+
+/**
+ * EhciInitAfterPciInit - Config EHCI controller after PCI
+ * emulation
+ *
+ *
+ * @param[in] Value EHCI Controler info.
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+EhciInitAfterPciInit (
+  IN  UINT32           Value,
+  IN  FCH_DATA_BLOCK   *FchDataPtr
+  )
+{
+  FchEhciInitAfterPciInit ( Value, FchDataPtr);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c
new file mode 100644
index 0000000000..e6e8c5d342
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ehci controller
+ *
+ * Init Ehci Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_EHCIRESET_FILECODE
+
+/**
+ * FchInitResetEhci - Config Ehci controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetEhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c
new file mode 100644
index 0000000000..d3fc9b4231
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c
@@ -0,0 +1,71 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB EHCI controller
+ *
+ * Init USB EHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c
new file mode 100644
index 0000000000..91122ff7b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB EHCI controller
+ *
+ * Init USB EHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE
+//
+// Declaration of local functions
+//
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
new file mode 100644
index 0000000000..31b1079eff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
@@ -0,0 +1,210 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB EHCI controller
+ *
+ * Init USB EHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE
+//
+// Declaration of local functions
+//
+
+/**
+ * FchEhciInitAfterPciInit - Config USB controller after PCI emulation
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ */
+VOID
+FchEhciInitAfterPciInit (
+  IN  UINT32           Value,
+  IN  FCH_DATA_BLOCK   *FchDataPtr
+  )
+{
+  UINT32  BarAddress;
+  UINT32  Var;
+
+  //
+  //Get BAR address
+  //
+  ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader);
+  if ( (BarAddress != - 1) && (BarAddress != 0) ) {
+    //
+    //Enable Memory access
+    //
+    RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader);
+    if (FchDataPtr->Usb.EhciSsid != 0 ) {
+      RwPci ((UINT32) Value + FCH_EHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.EhciSsid, FchDataPtr->StdHeader);
+    }
+    //
+    //USB Common PHY CAL & Control Register setting
+    //
+    Var = 0x00020F00;
+    WriteMem (BarAddress + 0x0C0 , AccessWidth32, &Var);
+    //
+    // IN AND OUT DATA PACKET FIFO THRESHOLD
+    // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
+    //
+    RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040);
+    //
+    // EHCI Dynamic Clock Gating Feature
+    // Enable Global Clock Gating (BIT14)
+    //
+    RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), (UINT32)(BIT12 + BIT14));
+    RwMem (BarAddress + 0x0B0 , AccessWidth32, (UINT32)~BIT5, (UINT32)BIT5);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, (UINT32)~BIT12, (UINT32)BIT12);
+    //RPR 8.26 Incorrect gated signals in xhc_to_s5
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, (UINT32)~BIT16, (UINT32)BIT16);
+    //
+    // Enable adding extra flops to PHY rsync path
+    // Step 1:
+    //  EHCI_BAR 0xB4 [6] = 1
+    //  EHCI_BAR 0xB4 [7] = 0
+    //  EHCI_BAR 0xB4 [12] = 0 ("VLoad")
+    //  All other bit field untouched
+    // Step 2:
+    //  EHCI_BAR 0xB4[12] = 1
+    //
+    // USB 2.0 Ports Driving Strength
+    // Step1 is done by default
+    // Step2
+    RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, (UINT32)~BIT12, (UINT32)BIT12);
+    // Step3
+    RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200);
+    RwMem (BarAddress + 0x0C0 , AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00);
+
+    //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
+    RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), FchDataPtr->StdHeader);
+    // EHCI Async Park Mode
+    //Set EHCI_pci_configx50[11:8]=0x1
+    //Set EHCI_pci_configx50[15:12]=0x1
+    //Set EHCI_pci_configx50[17]=0x1
+    RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), FchDataPtr->StdHeader);
+    RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), FchDataPtr->StdHeader);
+    RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), FchDataPtr->StdHeader);
+    //RPR 7.14 Extend InterPacket Gap
+    RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), FchDataPtr->StdHeader);
+
+    // Enabling EHCI Async Stop Enhancement
+    //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
+    //
+    RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), FchDataPtr->StdHeader);
+    //
+    // recommended setting "EHCI Advance PHY Power Savings"
+    // Set EHCI_pci_configx50[31]='1'
+    // Fix for EHCI controller driver  yellow sign issue under device manager
+    // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
+    // Disable USB data cache to resolve USB controller hang issue with Lan adaptor.
+    // EHCI PCI config register 50h bit 26 to `1'.
+    //
+    RwPci ((UINT32) Value + 0x50  + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, FchDataPtr->StdHeader);
+    //
+    // USB Delay A-Link Express L1 State
+    // PING Response Fix Enable EHCI_PCI_Config  x54[1] = 1
+    // Enable empty list mode. x54[3]
+    // Enable "L1 Early Exit" functionality. 0x54 [6:5] = 0x3 0x54 [9:7] = 0x4
+    //
+    RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT0, 0x0000027b, FchDataPtr->StdHeader);
+    RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFEFFFF, (UINT32)BIT16, FchDataPtr->StdHeader);
+    if ( FchDataPtr->Usb.UsbMsiEnable) {
+      RwPci ((UINT32) Value + 0x50 , AccessWidth32, (UINT32)~BIT6, 0x00, FchDataPtr->StdHeader);
+    }
+    // Long Delay on Framelist Read Causing EHCI DMA to Address 0 - Fix
+    // RWPCI ((UINT32) Value + 0x54 , AccWidthUint32 | S3_SAVE, ~BIT13, BIT13);
+    // LS connection can't wake up system from S3/S4/S5 when EHCI owns the port - Fix
+    RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT4, (UINT32)BIT4, FchDataPtr->StdHeader);
+    // EHCI lMU Hangs when Run/Stop is Set First and PDC is Enabled Near End uFrame 7 - Fix Enable
+    RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT11, (UINT32)BIT11, FchDataPtr->StdHeader);
+    // RPR 7.25  SB02674
+    RwPci ((UINT32) Value + 0x54 , AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, FchDataPtr->StdHeader);
+    // RPR 7.26  SB02684
+    RwPci ((UINT32) Value + 0x50  + 2, AccessWidth16, (UINT32)~BIT3, (UINT32)BIT3, FchDataPtr->StdHeader);
+    // RPR 7.26  SB02687
+    RwPci ((UINT32) Value + 0x54  + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, FchDataPtr->StdHeader);
+    // RPR 7.28  SB02700
+    RwPci ((UINT32) Value + 0x54  + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, FchDataPtr->StdHeader);
+    // RPR 7.29  SB02703
+    RwPci ((UINT32) Value + 0x54  + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, FchDataPtr->StdHeader);
+  } else {
+    //
+    // Fake Bar
+    //
+    BarAddress = FCH_FAKE_USB_BAR_ADDRESS;
+    WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader);
+    //
+    //Enable Memory access
+    //
+    RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader);
+    //
+    // Enable Global Clock Gating (BIT14)
+    //
+    RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), (UINT32)(BIT12 + BIT14));
+    RwMem (BarAddress + 0x0B0 , AccessWidth32, (UINT32)~BIT5, (UINT32)BIT5);
+    RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, FchDataPtr->StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
new file mode 100644
index 0000000000..3d40cb455f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
@@ -0,0 +1,130 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH USB OHCI controller
+ *
+ * Init USB OHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE
+//
+// Declaration of local functions
+//
+//
+// Declaration of local functions
+//
+/**
+ * FchSetUsbEnableReg
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchSetUsbEnableReg (
+  IN  FCH_DATA_BLOCK   *FchDataPtr
+  )
+{
+  UINT8                  UsbModeReg;
+  UINT8                  XhciReg00;
+  UsbModeReg = 0;
+
+  // Overwrite EHCI3/OHCI3 by Xhci1Enable
+  ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth8, &XhciReg00);
+  if (XhciReg00 & BIT0) {
+    FchDataPtr->Usb.Ohci3Enable = FALSE;
+    FchDataPtr->Usb.Ehci3Enable = FALSE;
+    UsbModeReg |= 0x80;
+  } else {
+    UsbModeReg &= 0x7F;
+  }
+
+  if ( FchDataPtr->Usb.Ohci1Enable ) {
+    UsbModeReg |= 0x01;
+  }
+  if ( FchDataPtr->Usb.Ehci1Enable ) {
+    UsbModeReg |= 0x02;
+  }
+  if ( FchDataPtr->Usb.Ohci2Enable ) {
+    UsbModeReg |= 0x04;
+  }
+  if ( FchDataPtr->Usb.Ehci2Enable ) {
+    UsbModeReg |= 0x08;
+  }
+  if ( FchDataPtr->Usb.Ohci3Enable ) {
+    UsbModeReg |= 0x10;
+  }
+  if ( FchDataPtr->Usb.Ehci3Enable ) {
+    UsbModeReg |= 0x20;
+  }
+  if ( FchDataPtr->Usb.Ohci4Enable ) {
+    UsbModeReg |= 0x40;
+  }
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEF , AccessWidth8, 0, UsbModeReg);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
new file mode 100644
index 0000000000..b1498a4242
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH USB OHCI controller
+ *
+ * Init USB OHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE
+//
+// Declaration of local functions
+//
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c
new file mode 100644
index 0000000000..1fd30353b5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c
@@ -0,0 +1,133 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH USB OHCI controller
+ *
+ * Init USB OHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE
+//
+// Declaration of local functions
+//
+
+/**
+ * FchOhciInitAfterPciInit - Config USB OHCI controller after
+ * PCI emulation
+ *
+ * @param[in] Value  Controller PCI config address (bus# + device# + function#)
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ */
+VOID
+FchOhciInitAfterPciInit (
+  IN  UINT32           Value,
+  IN  FCH_DATA_BLOCK   *FchDataPtr
+  )
+{
+  //
+  // Disable the MSI capability of USB host controllers
+  //
+  RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, 0xFF, BIT0, FchDataPtr->StdHeader);
+  RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~(BIT0 + BIT5 + BIT12), 0, FchDataPtr->StdHeader);
+  //
+  // USB SMI Handshake
+  //
+  RwPci ((UINT32) Value + 0x50  + 1, AccessWidth8, (UINT32)~BIT4, 0x00, FchDataPtr->StdHeader);
+
+  if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
+    if ( FchDataPtr->Usb.OhciSsid != 0 ) {
+      RwPci ((UINT32) Value + FCH_OHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.OhciSsid, FchDataPtr->StdHeader);
+    }
+  }
+  //
+  // recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
+  //OHCI 0_PCI_Config 0x50[30] = 1
+  //
+  RwPci ((UINT32) Value + 0x50  + 3, AccessWidth8, (UINT32)~BIT6, (UINT32)BIT6, FchDataPtr->StdHeader);
+  //
+  // L1 Early Exit
+  // Set OHCI Arbiter Mode.
+  // Set Enable Global Clock Gating.
+  //
+  RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth8, (UINT32)~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), (UINT32)(BIT0 + BIT4 + BIT7), FchDataPtr->StdHeader);
+  RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth16, (UINT32)~(BIT4 + BIT5 + BIT8), (UINT32)(BIT4 + BIT5 + BIT8), FchDataPtr->StdHeader);
+  //
+  // Enable OHCI SOF Synchronization.
+  // Enable OHCI Periodic List Advance.
+  //
+  RwPci ((UINT32) Value + 0x50  + 2, AccessWidth8, (UINT32)~(BIT3 + BIT4 + BIT6 + BIT7), (UINT32)(BIT3 + BIT4 + BIT6 + BIT7), FchDataPtr->StdHeader);
+  if ( FchDataPtr->Usb.UsbMsiEnable) {
+    RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, (UINT32)~BIT0, 0x00, FchDataPtr->StdHeader);
+    RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT5, (UINT32)BIT5, FchDataPtr->StdHeader);
+  }
+  // full-speed false crc errors detected. Issue - fix enable
+  RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth32, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10), FchDataPtr->StdHeader);
+  // SB02643
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4, AccessWidth8, (UINT32)~BIT7, (UINT32)BIT7);
+  // RPR 7.27 SB02686
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, (UINT32)~BIT2, (UINT32)BIT2);
+  // SB02698
+  RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT0, 0, FchDataPtr->StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c
new file mode 100644
index 0000000000..26f9626e2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c
@@ -0,0 +1,432 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH USB3 controller
+ *
+ * Init USB3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 65854 $   @e \$Date: 2012-02-26 01:52:07 -0600 (Sun, 26 Feb 2012) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE
+
+//
+// Declaration of local functions
+//
+
+/**
+ * FchXhciInitIndirectReg - Config XHCI Indirect Registers
+ *
+ *
+ *
+ * @param[in] StdHeader AMD Standard Header
+ *
+ */
+VOID
+FchXhciInitIndirectReg (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 DrivingStrength;
+  UINT32 Port;
+  UINT32 Register;
+  UINT32 RegValue;
+  UINT8  Index;
+  DrivingStrength = 0;
+  Port = 0;
+  //
+  // SuperSpeed PHY Configuration (adaptation mode setting)
+  //
+  RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
+  RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
+  //
+  // SuperSpeed PHY Configuration (CR phase and frequency filter settings)
+  //
+  RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
+  RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
+  //
+  // BLM Meaasge
+  //
+  RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
+  //
+  // xHCI USB 2.0 PHY Settings
+  // Step 1 is done by hardware default
+  // Step 2
+  for (Port = 0; Port < 4; Port ++) {
+    DrivingStrength = BIT2;
+    if (Port < 2) {
+      RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + DrivingStrength, StdHeader);
+      RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
+      RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
+      Register = FCH_XHCI_IND60_REG00;
+      Index = 0;
+      do {
+        WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
+        ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
+        Index++;
+        FchStall (10, StdHeader);
+      } while ((RegValue & BIT17) && (Index < 10 ));
+      RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
+    } else {
+      RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + DrivingStrength, StdHeader);
+      RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
+      RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
+      Register = FCH_XHCI_IND60_REG00;
+      Index = 0;
+      do {
+        WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
+        ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
+        Index++;
+        FchStall (10, StdHeader);
+      } while ((RegValue & BIT17) && (Index < 10 ));
+      RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
+    }
+  }
+
+  // Step 3
+  RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
+  RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
+}
+
+/**
+ * XhciA12Fix - Config XHCI A12 Fix
+ *
+ *
+ */
+STATIC
+VOID
+XhciA12Fix (
+     OUT   VOID
+  )
+{
+  //
+  // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable
+  // ACPI_USB3.0_REG 0x20[12:11] = 2'b11
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11));
+  //
+  // XHC 2 USB2 ports interactional issue - fix enable
+  // ACPI_USB3.0_REG 0x20[16] = 1'b1
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
+  //
+  // XHC USB2.0 Ports suspend Enhancement
+  // ACPI_USB3.0_REG 0x20[15] = 1'b1
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15));
+  //
+  // XHC HS/FS IN Data Buffer Underflow issue - fix enable
+  // ACPI_USB3.0_REG 0x20[20:18] = 0x7
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18));
+  //
+  // XHC stuck in U3 after system resuming from S3 -fix enable
+  // ACPI_USB3.0_REG 0x98[19] = 1'b1
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19));
+  //
+  // Change XHC1 ( Dev 16 function 1) Interrupt Pin register to INTB# - Fix enable
+  // ACPI_PMIO_F0[18] =1
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18));
+  //
+  // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled
+  // ACPI_PMIO_F0[13] =1
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13));
+  //
+  // Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable
+  // ACPI_PMIO_F0[17] =1
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17));
+  //
+  // USB leakage current on differential lines when ports are switched to XHCI - Fix enable
+  // ACPI_PMIO_F0[14] =1
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14));
+}
+
+/**
+ * IsLpcRom - Is LPC Rom?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsLpcRom (
+  OUT VOID
+  )
+{
+  return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80) & BIT1) == 0) );
+}
+
+/**
+ * FchXhciInitBeforePciInit - Config XHCI controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchXhciInitBeforePciInit (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  UINT16                BcdAddress;
+  UINT16                BcdSize;
+  UINT16                AcdAddress;
+  UINT16                AcdSize;
+  UINT16                FwAddress;
+  UINT16                FwSize;
+  UINTN                 XhciFwStarting;
+  UINT32                SpiValidBase;
+  UINT32                RegData;
+  UINT16                Index;
+  BOOLEAN               Xhci0Enable;
+  BOOLEAN               Xhci1Enable;
+  FCH_DATA_BLOCK        *LocalCfgPtr;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  Xhci0Enable = LocalCfgPtr->Usb.Xhci0Enable;
+  Xhci1Enable = LocalCfgPtr->Usb.Xhci1Enable;
+
+  if (( Xhci0Enable == 0 ) && (Xhci1Enable == 0)) {
+    return;
+  }
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700);
+  FchStall (20, StdHeader);
+
+  if ( LocalCfgPtr->Usb.UserDefineXhciRomAddr == 0 ) {
+    //
+    // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
+    //
+    GetRomSigPtr (&XhciFwStarting, StdHeader);
+
+    if (XhciFwStarting == 0) {
+      return;
+    }
+    XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
+  } else {
+    XhciFwStarting = ( UINTN ) LocalCfgPtr->Usb.UserDefineXhciRomAddr;
+  }
+  if (IsLpcRom ()) {
+    //
+    // XHCI firmware re-load
+    //
+    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, (UINT32)~BIT2, (UINT32)(BIT2 + BIT1 + BIT0), StdHeader);
+    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, 0x00000FFF, (UINT32) (XhciFwStarting), StdHeader);
+  }
+
+  //
+  // Enable SuperSpeed receive special error case logic. 0x20 bit8
+  // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
+  // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700);
+  //
+  // SuperSpeed PHY Configuration (adaptation timer setting)
+  // XHC U1 LFPS Exit time
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA);
+  //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA);
+
+  //
+  // Step 1. to enable Xhci IO and Firmware load mode
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0);                /// Disable Device 22
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7);                    /// Enable 2.0 devices
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, (Xhci0Enable + (Xhci1Enable << 1)) & 0x03);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000);
+
+  //
+  // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16));
+
+  BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
+  BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize);
+
+  AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
+  AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize);
+
+  SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase);
+  //
+  //   Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
+  //
+  for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) {
+    RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index));
+  }
+
+  for (Index = 0; Index < BcdSize; Index++) {
+    RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index));
+  }
+
+  for (Index = 0; Index < AcdSize; Index++) {
+    RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index));
+  }
+
+  //
+  // Step 3. to enable the instruction RAM preload functionality.
+  //
+  FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
+  FwAddress += 2;
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress);
+
+  FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize);
+  //
+  //   Set the starting address offset for Instruction RAM preload.
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0);
+
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, (UINT32)BIT29);
+
+  for (;;) {
+    ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
+    if (RegData & BIT30) {
+      break;
+    }
+  }
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, 0);
+
+  //
+  // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
+  //
+
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PLL_RESET, 0);       ///Release U3PLLreset
+  for (;;) {
+    ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
+    if (RegData & U3PLL_LOCK) {
+      break;
+    }
+  }
+
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PHY_RESET, 0);       ///Release U3PHY
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3CORE_RESET, 0);      ///Release core reset
+
+  //
+  // SuperSpeed PHY Configuration
+  //
+  //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA);
+  //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA);
+
+  FchXhciInitIndirectReg (StdHeader);
+
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0);                /// Disable Device 22
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7);                    /// Enable 2.0 devices
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT21), (UINT32)BIT21);
+  //
+  // Step 5.
+  //
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT17 + BIT18 + BIT19), (UINT32)(BIT17 + BIT18));
+
+  XhciA12Fix ();
+
+  //
+  // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices
+  //
+  if (!(IsUmiOneLaneGen1Mode (StdHeader))) {
+    RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT25 + BIT24), (UINT32)BIT24);
+  }
+  // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699)
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT22), (UINT32)BIT22);
+  // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
+  RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, (UINT32)~(BIT20), (UINT32)BIT20);
+}
+
+/**
+ * FchXhciPowerSavingProgram - Config XHCI for Power Saving mode
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchXhciPowerSavingProgram (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  UINT8                 XhciEfuse;
+  FCH_DATA_BLOCK        *LocalCfgPtr;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  // add Efuse checking for Xhci enable/disable
+  XhciEfuse = XHCI_EFUSE_LOCATION;
+  GetEfuseStatus (&XhciEfuse, StdHeader);
+  if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
+    RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c
new file mode 100644
index 0000000000..664b7efc30
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c
@@ -0,0 +1,158 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH USB3 controller
+ *
+ * Init USB3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE
+
+//
+// Declaration of local functions
+//
+
+/**
+ * FchInitLateUsbXhciProgram - Config USB3 controller before OS
+ * Boot
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateUsbXhciProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                 IndexValue;
+  UINT8                 Value;
+  FCH_DATA_BLOCK        *LocalCfgPtr;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_BAR00;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_BAR01;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_BAR02;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_BAR03;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_04H;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_0CH;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI_REGISTER_3CH;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_BAR00;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_BAR01;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_BAR02;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_BAR03;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_04H;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_0CH;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+
+    ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader);
+    IndexValue = XHCI1_REGISTER_3CH;
+    WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
+  }
+  //RPR 8.12 xHCI controller PCI configuration space "Read Only" registers write lock enable
+  RwXhciIndReg ( FCH_XHCI_IND_REG04, (UINT32)~BIT8, (UINT32)BIT8, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c
new file mode 100644
index 0000000000..92b292817d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH USB3 controller
+ *
+ * Init USB3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE
+
+//
+// Declaration of local functions
+//
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
new file mode 100644
index 0000000000..bf5227fcd4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Xhci controller
+ *
+ * Init Xhci Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE
+
+/**
+ * FchInitResetXhciProgram - Config Xhci controller during
+ * Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetXhciProgram (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8                     IndexValue;
+  UINT32                    ValueDword;
+  UINT8                     ValueByte;
+  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
+  AMD_CONFIG_PARAMS         *StdHeader;
+  BOOLEAN               Xhci0Enable;
+  BOOLEAN               Xhci1Enable;
+
+  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  Xhci0Enable = LocalCfgPtr->FchReset.Xhci0Enable;
+  Xhci1Enable = LocalCfgPtr->FchReset.Xhci1Enable;
+
+  if ( Xhci0Enable ) {
+    ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
+    if ( ValueDword == (FCH_USB_XHCI_DID << 16) + FCH_USB_XHCI_VID) {
+      //
+      // First Xhci controller.
+      //
+      ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
+      ValueDword = 0;
+
+      IndexValue = XHCI_REGISTER_BAR00;
+      ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
+      WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
+
+      IndexValue = XHCI_REGISTER_04H;
+      ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
+      WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
+
+      IndexValue = XHCI_REGISTER_0CH;
+      ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
+      WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
+
+      IndexValue = XHCI_REGISTER_3CH;
+      ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
+      WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
+      //
+      // Second Xhci controller.
+      //
+      ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
+      ValueDword = 0;
+
+      IndexValue = XHCI1_REGISTER_BAR00;
+      ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
+      WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
+
+      IndexValue = XHCI1_REGISTER_04H;
+      ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
+      WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
+
+      IndexValue = XHCI1_REGISTER_0CH;
+      ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
+      WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
+
+      IndexValue = XHCI1_REGISTER_3CH;
+      ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
+      WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
+    }
+  } else {
+    RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciEnv.c
new file mode 100644
index 0000000000..7ad99cb33d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciEnv.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB OHCI controller
+ *
+ * Init USB OHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_OHCIENV_FILECODE
+
+/**
+ * FchInitEnvUsbOhci - Config USB OHCI controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvUsbOhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciLate.c
new file mode 100644
index 0000000000..b54b624517
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciLate.c
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB OHCI controller
+ *
+ * Init USB OHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_OHCILATE_FILECODE
+
+/**
+ * FchInitLateUsbOhci - Config USB OHCI controller before OS
+ * Boot
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateUsbOhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciMid.c
new file mode 100644
index 0000000000..71b203b3bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciMid.c
@@ -0,0 +1,241 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB OHCI controller
+ *
+ * Init USB OHCI features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_OHCIMID_FILECODE
+//
+// Declaration of local functions
+//
+
+/* extern VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); */
+/**
+ * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
+ *
+ * @param[in] Value  Controller PCI config address (bus# + device# + function#)
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ */
+VOID OhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+
+/**
+ * FchInitMidUsbOhci - Config USB OHCI controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbOhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_INTERFACE   *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
+
+  FchInitMidUsbOhci1 (LocalCfgPtr);
+  FchInitMidUsbOhci2 (LocalCfgPtr);
+  FchInitMidUsbOhci3 (LocalCfgPtr);
+  FchInitMidUsbOhci4 (LocalCfgPtr);
+}
+
+/**
+ * FchInitMidUsbOhci1 - Config USB1 OHCI controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbOhci1 (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  DeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
+  OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
+
+  if (LocalCfgPtr->Usb.OhciSsid != 0 ) {
+    RwPci ((USB1_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
+  }
+}
+
+/**
+ * FchInitMidUsbOhci2 - Config USB2 OHCI controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbOhci2 (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  DeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
+  OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
+
+  if (LocalCfgPtr->Usb.OhciSsid != 0 ) {
+    RwPci ((USB2_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
+  }
+}
+
+/**
+ * FchInitMidUsbOhci3 - Config USB3 OHCI controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbOhci3 (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  DeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
+  OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
+
+  if (LocalCfgPtr->Usb.OhciSsid != 0 ) {
+    RwPci ((USB3_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
+  }
+}
+
+/**
+ * FchInitMidUsbOhci4 - Config USB4 OHCI controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbOhci4 (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT32       DeviceId;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  DeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
+  OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
+
+  if (LocalCfgPtr->Usb.OhciSsid != 0 ) {
+    RwPci ((USB4_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
+  }
+}
+
+/**
+ * OhciInitAfterPciInit - Config OHCI controller after PCI
+ * emulation
+ *
+ *
+ * @param[in] Value OHCI Controler info.
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+OhciInitAfterPciInit (
+  IN  UINT32           Value,
+  IN  FCH_DATA_BLOCK   *FchDataPtr
+  )
+{
+  FchOhciInitAfterPciInit ( Value, FchDataPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c
new file mode 100644
index 0000000000..ba6baabd51
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Ohci controller
+ *
+ * Init Ohci Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_OHCIRESET_FILECODE
+
+/**
+ * FchInitResetOhci - Config Ohci controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetOhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c
new file mode 100644
index 0000000000..09fca7dc1b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB controller
+ *
+ * Init USB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_USBENV_FILECODE
+
+/* extern  VOID  FchSetUsbEnableReg         (IN FCH_DATA_BLOCK *FchDataPtr); */
+
+/**
+ * FchInitEnvUsb - Config USB controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvUsb (
+  IN  VOID     *FchDataPtr
+  )
+{
+  //
+  // Disabled All USB controller *** Move to each controller ***
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, BIT7, 0);
+  //
+  // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
+  // USB SleepCtrl set as BIT9+BIT8 (6 uframes)
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xF0 , AccessWidth16, (UINT32)~BIT2, (UINT32)(BIT2 + BIT7 + BIT8 + BIT9));
+
+  FchSetUsbEnableReg (FchDataPtr);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEE, AccessWidth8, (UINT32)~(BIT2), 0 );
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c
new file mode 100644
index 0000000000..5702bdd059
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB controller
+ *
+ * Init USB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_USBLATE_FILECODE
+
+/**
+ * FchInitLateUsb - Config USB controller before OS Boot
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateUsb (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c
new file mode 100644
index 0000000000..764ad6e9d1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c
@@ -0,0 +1,95 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB controller
+ *
+ * Init USB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_USBMID_FILECODE
+
+/**
+ * FchInitMidUsb - Config USB controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsb (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  if ( LocalCfgPtr->Usb.UsbPhyPowerDown ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, (UINT32)~BIT0, (UINT32)BIT0);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, (UINT32)~BIT0, 0);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c
new file mode 100644
index 0000000000..d4d4461a8e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Usb controller
+ *
+ * Init Usb Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_USBRESET_FILECODE
+
+/**
+ * FchInitResetUsb - Config Usb controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetUsb (
+  IN  VOID     *FchDataPtr
+  )
+{
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciEnv.c
new file mode 100644
index 0000000000..9116e6793f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciEnv.c
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB3 controller
+ *
+ * Init USB3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_XHCIENV_FILECODE
+
+/* extern VOID  FchXhciInitBeforePciInit  (IN FCH_DATA_BLOCK* FchDataPtr); */
+/* extern VOID  FchXhciInitIndirectReg    (IN AMD_CONFIG_PARAMS *StdHeader); */
+/* extern VOID  FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr); */
+//
+// Declaration of local functions
+//
+VOID XhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID XhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader);
+
+/**
+ * FchInitEnvUsbXhci - Config XHCI controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitEnvUsbXhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK        *LocalCfgPtr;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  if ( LocalCfgPtr->Usb.Xhci0Enable == TRUE ) {
+    if ( LocalCfgPtr->Misc.S3Resume == 0 ) {
+      XhciInitBeforePciInit (LocalCfgPtr);
+    } else {
+      XhciInitIndirectReg (StdHeader);
+    }
+  } else {
+    //
+    // for power saving.
+    //
+    FchXhciPowerSavingProgram (LocalCfgPtr);
+  }
+}
+
+/**
+ * XhciInitIndirectReg - Config XHCI Indirect Registers
+ *
+ *
+ *
+ * @param[in] StdHeader AMD Standard Header
+ *
+ */
+VOID
+XhciInitIndirectReg (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  FchXhciInitIndirectReg (StdHeader);
+}
+
+/**
+ * XhciInitBeforePciInit - Config XHCI controller before PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+XhciInitBeforePciInit (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  FchXhciInitBeforePciInit ( FchDataPtr );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c
new file mode 100644
index 0000000000..bd9ef1b775
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB3 controller
+ *
+ * Init USB3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_XHCILATE_FILECODE
+
+/* extern VOID  FchInitLateUsbXhciProgram (IN VOID  *FchDataPtr); */
+
+/**
+ * FchInitLateUsbXhci - Config USB3 controller before OS Boot
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitLateUsbXhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitLateUsbXhciProgram ( FchDataPtr );
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c
new file mode 100644
index 0000000000..e8dd235bfd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch USB3 controller
+ *
+ * Init USB3 features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_XHCIMID_FILECODE
+
+/**
+ * FchInitMidUsbXhci - Config USB3 controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidUsbXhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK   *LocalCfgPtr;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
+  if ( LocalCfgPtr->Usb.Xhci0Enable == TRUE ) {
+    RwPci ((USB_XHCI_BUS_DEV_FUN << 16) + FCH_XHCI_REG04, AccessWidth8, 0, BIT1, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
+    if (((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid != 0 ) {
+      RwPci ((USB_XHCI_BUS_DEV_FUN << 16) + FCH_XHCI_REG2C, AccessWidth32, 0x00, ((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
+    }
+  }
+
+  if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
+    RwPci ((USB_XHCI1_BUS_DEV_FUN << 16) + FCH_XHCI_REG04, AccessWidth8, 0, BIT1, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
+    if (((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid != 0 ) {
+      RwPci ((USB_XHCI1_BUS_DEV_FUN << 16) + FCH_XHCI_REG2C, AccessWidth32, 0x00, ((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
+    }
+    //
+    // Block Write to DID & SID to pass DTM
+    //
+    RwXhciIndReg (FCH_XHCI_IND_REG04, (UINT32)~BIT8, (UINT32)BIT8, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c
new file mode 100644
index 0000000000..82ea9b70b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Xhci controller
+ *
+ * Init Xhci Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_XHCIRECOVERY_FILECODE
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c
new file mode 100644
index 0000000000..f2438aff0d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config Fch Xhci controller
+ *
+ * Init Xhci Controller features (PEI phase).
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_USB_XHCIRESET_FILECODE
+
+
+
+/**
+ * FchInitResetXhci - Config Xhci controller during Power-On
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitResetXhci (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FchInitResetXhciProgram ( FchDataPtr );
+}
+
+/**
+ * FchInitRecoveryLpc - Config Xhci controller during Crisis
+ * Recovery
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h
new file mode 100644
index 0000000000..32bfc95353
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h
@@ -0,0 +1,194 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Misc common definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNB_H_
+#define _GNB_H_
+
+#pragma pack (push, 1)
+
+#define GNB_DEADLOOP() \
+{ \
+  VOLATILE BOOLEAN k; \
+  k = TRUE; \
+  while (k) { \
+  } \
+}
+#ifdef IDSOPT_TRACING_ENABLED
+  #if (IDSOPT_TRACING_ENABLED == TRUE)
+    #define GNB_TRACE_ENABLE
+  #endif
+#endif
+
+
+#ifndef GNB_DEBUG_CODE
+  #ifdef GNB_TRACE_ENABLE
+    #define  GNB_DEBUG_CODE(Code) Code
+  #else
+    #define  GNB_DEBUG_CODE(Code)
+  #endif
+#endif
+
+#ifndef MIN
+  #define MIN(x, y) (((x) > (y))? (y):(x))
+#endif
+
+#ifndef MAX
+  #define MAX(x, y) (((x) > (y))? (x):(y))
+#endif
+
+#define OFF 0
+
+#define PVOID UINT64
+
+#define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a))
+
+#define GnbLibGetHeader(x)  ((AMD_CONFIG_PARAMS*) (x)->StdHeader)
+
+#define AGESA_STATUS_UPDATE(Current, Aggregated) \
+if (Current > Aggregated) { \
+  Aggregated = Current; \
+}
+
+#ifndef offsetof
+  #define offsetof(s, m) (UINTN)&(((s *)0)->m)
+#endif
+
+
+//Table properties
+
+#define TABLE_PROPERTY_DEAFULT                     0x00000000ul
+#define TABLE_PROPERTY_IGFX_DISABLED               0x00000001ul
+#define TABLE_PROPERTY_IOMMU_DISABLED              0x00000002ul
+#define TABLE_PROPERTY_LCLK_DEEP_SLEEP             0x00000004ul
+#define TABLE_PROPERTY_ORB_CLK_GATING              0x00000008ul
+#define TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING       0x00000010ul
+#define TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING       0x00000020ul
+#define TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING       0x00000040ul
+#define TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING       0x00000080ul
+#define TABLE_PROPERTY_BAPM                        0x00000100ul
+#define TABLE_PROPERTY_SECONDARY_GNB               0x00000200ul
+#define TABLE_PROPERTY_NMI_SYNCFLOOD               0x00000400ul
+#define TABLE_PROPERTY_NBDPM                       0x00000800ul
+#define TABLE_PROPERTY_LOADLINE_ENABLE             0x00001000ul
+#define TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING       0x00002000ul
+
+//Register access flags Flags
+#define GNB_REG_ACC_FLAG_S3SAVE                    0x00000001ul
+
+/// LCLK DPM enable control
+typedef enum {
+  LclkDpmDisabled,          ///<LCLK DPM disabled
+  LclkDpmRcActivity,        ///<LCLK DPM enabled and use Root Complex Activity monitor method
+} LCLK_DPM_MODE;
+
+
+/// Power gaiter data setting (do not change this structure definition)
+typedef struct {
+  UINT16  pwrdata0 ;
+  UINT16  pwrdata1 ;
+  UINT16  pwrdata2 ;
+  UINT16  pwrdata3 ;
+  UINT16  ResetTimer;           ///< Reset Timer
+  UINT16  IsoTimer;             ///< Isolation Timer
+} POWER_GATE_DATA;
+
+
+/// Topology information
+typedef struct {
+  BOOLEAN   PhantomFunction;    ///< PCIe topology have device with phantom function
+  BOOLEAN   PcieToPciexBridge;  ///< PCIe topology have device with Pcieto Pcix bridge
+} GNB_TOPOLOGY_INFO;
+
+
+/// GNB installable services
+typedef enum {
+  GnbPcieFamConfigService,                ///< PCIe config service
+  GnbPcieFamInitService,                  ///< PCIe Init service
+  GnbPcieFamDebugService,                 ///< PCIe Debug service
+  GnbRegisterAccessService,               ///< GNB register access service
+  GnbIommuService                         ///< GNB IOMMU config service
+} GNB_SERVICE_ID;
+
+/// GNB service entry
+typedef struct _GNB_SERVICE {
+  GNB_SERVICE_ID        ServiceId;        ///< Service ID
+  UINT64                Family;           ///< CPU family
+  VOID                  *ServiceProtocol; ///< Service protocol
+  struct  _GNB_SERVICE  *NextService;     ///< Pointer to next service
+} GNB_SERVICE;
+
+#define GNB_STRINGIZE(x)                  #x
+#define GNB_SERVICE_DEFINITIONS(x)        GNB_STRINGIZE (Services/x/x.h)
+#define GNB_MODULE_DEFINITIONS(x)         GNB_STRINGIZE (Modules/x/x.h)
+#define GNB_MODULE_INSTALL(x)             GNB_STRINGIZE (Modules/x/x##Install.h)
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h
new file mode 100644
index 0000000000..3a54cf9992
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe family specific services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBFAMSERVICES_H_
+#define _GNBFAMSERVICES_H_
+
+#include "Gnb.h"
+#include "GnbPcie.h"
+#include "GnbIommu.h"
+
+typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       UINT8                      RegisterSpaceType,
+  IN       UINT32                     Address,
+  IN       VOID                       *Value,
+  IN       UINT32                     Flags,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+);
+
+/// Register Read/Write protocol
+typedef struct {
+  F_GNB_REGISTER_ACCESS               *Read;    ///< Read Register
+  F_GNB_REGISTER_ACCESS               *Write;   ///< Write Register
+} GNB_REGISTER_SERVICE;
+
+AGESA_STATUS
+GnbFmCreateIvrsEntry (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+typedef AGESA_STATUS F_GNBFMCREATEIVRSENTRY (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GnbFmCheckIommuPresent (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+typedef BOOLEAN F_GNBFMCHECKIOMMUPRESENT (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+/// GNB IOMMU services
+typedef struct {
+  F_GNBFMCHECKIOMMUPRESENT             *GnbFmCheckIommuPresent;       ///< GnbFmCheckIommuPresent
+  F_GNBFMCREATEIVRSENTRY               *GnbFmCreateIvrsEntry;         ///< GnbFmCreateIvrsEntry
+} GNB_FAM_IOMMU_SERVICES;
+
+
+PCI_ADDR
+GnbFmGetPciAddress (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbFmGetBusDecodeRange (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *StartBusNumber,
+     OUT   UINT8                      *EndBusNumber,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbFmGetLinkId (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *LinkId,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
new file mode 100644
index 0000000000..02c38d684c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics controller BIF straps control services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GNBFUSETABLE_H_
+#define _GNBFUSETABLE_H_
+
+#pragma pack (push, 1)
+
+#define PP_FUSE_MAX_NUM_DPM_STATE 5
+#define PP_FUSE_MAX_NUM_SW_STATE  6
+
+/// Fuse definition structure
+typedef struct  {
+  UINT8                       PPlayTableRev;              ///< PP table revision
+  UINT8                       SclkDpmValid[6];            ///< Valid DPM states
+  UINT8                       SclkDpmDid[6];              ///< Sclk DPM DID
+  UINT8                       SclkDpmVid[6];              ///< Sclk DPM VID
+  UINT8                       SclkDpmCac[5];              ///< Sclk DPM Cac
+  UINT8                       PolicyFlags[6];             ///< State policy flags
+  UINT8                       PolicyLabel[6];             ///< State policy label
+  UINT8                       VclkDid[4];                 ///< VCLK DID
+  UINT8                       DclkDid[4];                 ///< DCLK DID
+  UINT8                       SclkThermDid;               ///< Thermal SCLK
+  UINT8                       VclkDclkSel[6];             ///< Vclk/Dclk selector
+  UINT8                       LclkDpmValid[4];            ///< Valid Lclk DPM states
+  UINT8                       LclkDpmDid[4];              ///< Lclk DPM DID
+  UINT8                       LclkDpmVid[4];              ///< Lclk DPM VID
+  UINT8                       DisplclkDid[4];             ///< Displclk DID
+  UINT8                       PcieGen2Vid;                ///< Pcie Gen 2 VID
+  UINT8                       MainPllId;                  ///< Main PLL Id from fuses
+  UINT8                       WrCkDid;                    ///< WRCK SMU clock Divisor
+  UINT8                       SclkVid[4];                 ///< Sclk VID
+  UINT8                       GpuBoostCap;                ///< GPU boost cap
+  UINT16                      SclkDpmTdpLimit[6];         ///< Sclk DPM TDP limit
+  UINT16                      SclkDpmTdpLimitPG;          ///< TDP limit PG
+  UINT32                      SclkDpmBoostMargin;         ///< Boost margin
+  UINT32                      SclkDpmThrottleMargin;      ///< Throttle margin
+  BOOLEAN                     VceSateTableSupport;        ///< Support VCE in PP table
+  UINT8                       VceFlags[4];                ///< VCE Flags
+  UINT8                       VceMclk[4];                 ///< MCLK for VCE
+  UINT8                       VceReqSclkSel[4];           ///< SCLK selector for VCE
+  UINT8                       EclkDid[4];                 ///< Eclk DID
+} PP_FUSE_ARRAY;
+
+#pragma pack (pop)
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
new file mode 100644
index 0000000000..1c8eab082b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
@@ -0,0 +1,472 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64730 $   @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBGFX_H_
+#define _GNBGFX_H_
+
+//#ifndef PVOID
+//  typedef UINT64 PVOID;
+//#endif
+
+#define DEVICE_DFP                                0x1
+#define DEVICE_CRT                                0x2
+#define DEVICE_LCD                                0x3
+
+
+#define CONNECTOR_DISPLAYPORT_ENUM                0x3013
+#define CONNECTOR_HDMI_TYPE_A_ENUM                0x300c
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM          0x3003
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM            0x3004
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM          0x3001
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM            0x3002
+#define CONNECTOR_VGA_ENUM                        0x3005
+#define CONNECTOR_LVDS_ENUM                       0x300E
+#define CONNECTOR_eDP_ENUM                        0x3014
+#define CONNECTOR_LVDS_eDP_ENUM                   0x3016
+#define ENCODER_TRAVIS_ENUM_ID1                   0x2123
+#define ENCODER_TRAVIS_ENUM_ID2                   0x2223
+#define ENCODER_ALMOND_ENUM_ID1                   0x2122
+#define ENCODER_NOT_PRESENT                       0x0000
+
+// no eDP->LVDS translator chip
+#define eDP_TO_LVDS_RX_DISABLE                    0x00
+// common eDP->LVDS translator chip without AMD SW init
+#define eDP_TO_LVDS_COMMON_ID                     0x01
+// Realtek tansaltor which require AMD SW init
+#define eDP_TO_LVDS_REALTEK_ID                    0x02
+
+
+#define ATOM_DEVICE_CRT1_SUPPORT                  0x0001
+#define ATOM_DEVICE_DFP1_SUPPORT                  0x0008
+#define ATOM_DEVICE_DFP6_SUPPORT                  0x0040
+#define ATOM_DEVICE_DFP2_SUPPORT                  0x0080
+#define ATOM_DEVICE_DFP3_SUPPORT                  0x0200
+#define ATOM_DEVICE_DFP4_SUPPORT                  0x0400
+#define ATOM_DEVICE_DFP5_SUPPORT                  0x0800
+#define ATOM_DEVICE_LCD1_SUPPORT                  0x0002
+
+/// Graphics card information structure
+typedef struct {
+  UINT32   AmdPcieGfxCardBitmap;                  ///< AMD PCIE graphics card information
+  UINT32   PcieGfxCardBitmap;                     ///< All PCIE graphics card information
+  UINT32   PciGfxCardBitmap;                      ///< All PCI graphics card information
+} GFX_CARD_CARD_INFO;
+
+typedef enum {
+  iGpuVgaAdapter,                                       ///< Configure iGPU as VGA adapter
+  iGpuVgaNonAdapter                                     ///< Configure iGPU as non VGA adapter
+} GFX_IGPU_VGA_MODE;
+
+typedef enum {
+  excel992,
+  excel993
+} UMA_STEERING;
+
+/// User Options
+typedef enum {
+  OptionDisabled,                                       ///< Disabled
+  OptionEnabled                                         ///< Enabled
+} CONTROL_OPTION;
+
+/// GFX enable Policy
+typedef enum {
+  GmcPowerGatingDisabled,                               ///< Disable Power gating
+  GmcPowerGatingStutterOnly,                            ///< GMC Stutter Only mode
+  GmcPowerGatingWidthStutter                            ///< GMC Power gating with Stutter mode
+} GMC_POWER_GATING;
+
+/// Internal GFX mode
+typedef enum {
+  GfxControllerLegacyBridgeMode,                        ///< APC bridge Legacy mode
+  GfxControllerPcieEndpointMode,                        ///< IGFX PCIE Bus 0, Device 1
+} GFX_CONTROLLER_MODE;
+
+/// Graphics Platform Configuration
+typedef struct {
+  UINT32                       StdHeader;                ///< Standard Header TODO: Used to be PVOID
+  PCI_ADDR                    GfxPciAddress;            ///< Graphics PCI Address
+  UMA_INFO                    UmaInfo;                  ///< UMA Information
+  UINT32                      GmmBase;                  ///< GMM Base
+  UINT8                       GnbHdAudio;               ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                        ///< essentially it enables function 1 of graphics device.
+                                                        ///< @li 0 = HD Audio disable
+                                                        ///< @li 1 = HD Audio enable
+  UINT8                       AbmSupport;               ///< Automatic adjust LVDS/eDP Back light level support.It is
+                                                        ///< characteristic specific to display panel which used by platform design.
+                                                        ///< @li 0 = ABM support disabled
+                                                        ///< @li 1 = ABM support enabled
+  UINT8                       DynamicRefreshRate;       ///< Adjust refresh rate on LVDS/eDP.
+  UINT16                      LcdBackLightControl;      ///< The PWM frequency to LCD backlight control.
+                                                        ///< If equal to 0 backlight not controlled by iGPU.
+  UINT32                      AmdPlatformType;          ///< Platform type
+  UMA_STEERING                UmaSteering;              ///< UMA Steering
+  GFX_IGPU_VGA_MODE           iGpuVgaMode;              ///< iGPU VGA mode
+  BOOLEAN                     GmcClockGating;           ///< Clock gating
+  BOOLEAN                     GmcLockRegisters;         ///< GmcLock Registers
+  BOOLEAN                     GfxFusedOff;              ///< Record if GFX is fused off.
+  GMC_POWER_GATING            GmcPowerGating;           ///< Gmc Power Gating.
+  UINT8                       Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID
+  GFX_CONTROLLER_MODE         GfxControllerMode;        ///< Gfx controller mode
+  UINT16                      LvdsSpreadSpectrum;       ///< Spread spectrum value in 0.01 %
+  UINT16                      LvdsSpreadSpectrumRate;   ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+  UINT8                       LvdsPowerOnSeqDigonToDe;    ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqDeToVaryBl;   ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqDeToDigon;    ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqVaryBlToDe;   ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing.
+  UINT16                      LvdsMaxPixelClockFreq;      ///< The maximum pixel clock frequency supported.
+  UINT32                      LcdBitDepthControlValue;    ///< The LCD bit depth control settings.
+  UINT8                       Lvds24bbpPanelMode;         ///< The LVDS 24 BBP mode.
+  LVDS_MISC_CONTROL           LvdsMiscControl;            ///< THe LVDS swap/Hsync/Vsync/BLON/Volt-overwrite control
+  GFX_CARD_CARD_INFO          GfxDiscreteCardInfo;        ///< Discrete GFX card info
+  UINT16                      PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
+  BOOLEAN                     GnbRemoteDisplaySupport;    ///< Wireless Display Enable
+  UINT8                       gfxplmcfg0 ;
+  DISPLAY_MISC_CONTROL        DisplayMiscControl;         ///< The Display misc control
+} GFX_PLATFORM_CONFIG;
+
+
+typedef UINT32 ULONG;
+typedef UINT16 USHORT;
+typedef UINT8  UCHAR;
+
+/// Driver interface header structure
+typedef struct _ATOM_COMMON_TABLE_HEADER {
+  USHORT                      usStructureSize;             ///< Structure size
+  UCHAR                       ucTableFormatRevision;       ///< Format revision number
+  UCHAR                       ucTableContentRevision;      ///< Contents revision number
+} ATOM_COMMON_TABLE_HEADER;
+
+/// Link ping mapping for DP/eDP/LVDS
+typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING {
+  UCHAR ucDP_Lane0_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDP_Lane1_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDP_Lane2_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDP_Lane3_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+} ATOM_DP_CONN_CHANNEL_MAPPING;
+
+/// Link ping mapping for DVI/HDMI
+typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING {
+  UCHAR ucDVI_DATA2_Source  :2;                     ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDVI_DATA1_Source  :2;                     ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDVI_DATA0_Source  :2;                     ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDVI_CLK_Source    :2;                     ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+} ATOM_DVI_CONN_CHANNEL_MAPPING;
+
+
+/// External Display Path
+typedef struct _EXT_DISPLAY_PATH {
+  USHORT                      usDeviceTag;          ///< A bit vector to show what devices are supported
+  USHORT                      usDeviceACPIEnum;     ///< 16bit device ACPI id.
+  USHORT                      usDeviceConnector;    ///< A physical connector for displays to plug in, using object connector definitions
+  UCHAR                       ucExtAUXDDCLutIndex;  ///< An index into external AUX/DDC channel LUT
+  UCHAR                       ucExtHPDPINLutIndex;  ///< An index into external HPD pin LUT
+  USHORT                      usExtEncoderObjId;    ///< external encoder object id
+  union {                                           ///< Lane mapping
+    UCHAR                     ucChannelMapping;     ///< lane mapping on connector (ucChannelMapping=0 use default)
+    ATOM_DP_CONN_CHANNEL_MAPPING  asDPMapping;      ///< lane mapping on connector (ucChannelMapping=0 use default)
+    ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;     ///< lane mapping on connector (ucChannelMapping=0 use default)
+  } ChannelMapping;
+  UCHAR                       ucChPNInvert;         ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted
+  USHORT                      usCaps;               ///< Capabilities IF BIT[0] == 1, downgrade phy link to DP1.1
+  USHORT                      usReserved;           ///< Reserved
+} EXT_DISPLAY_PATH;
+
+/// External Display Connection Information
+typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO {
+  ATOM_COMMON_TABLE_HEADER    sHeader;              ///< Standard Header
+  UCHAR                       ucGuid [16];          ///< Guid
+  EXT_DISPLAY_PATH            sPath[7];             ///< External Display Path
+  UCHAR                       ucChecksum;           ///< Checksum
+  UCHAR                       uc3DStereoPinId;      ///< 3D Stereo Pin ID
+  UCHAR                       ucRemoteDisplayConfig;   ///< Bit0=1:Enable Wireless Display through APU VCE HW function
+  UCHAR                       uceDPToLVDSRxId;      ///< 3rd party eDP to LVDS translator chip presented. 0:no, 1:chip without AMD SW init, 2:Realtek tansaltor which require AMD SW init
+  UCHAR                       Reserved [4];         ///< Reserved
+} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
+
+/// Displclk to VID relation table
+typedef struct _ATOM_CLK_VOLT_CAPABILITY {
+  ULONG                       ulVoltageIndex;       ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
+  ULONG                       ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz
+} ATOM_CLK_VOLT_CAPABILITY;
+
+/// Available Sclk table
+typedef struct _ATOM_AVAILABLE_SCLK_LIST {
+  ULONG                        ulSupportedSCLK;     ///< Maximum clock supported with specified voltage index,  unit in 10kHz
+  USHORT                       usVoltageIndex;      ///< The Voltage Index indicated by FUSE for specified SCLK
+  USHORT                       usVoltageID;         ///< The Voltage ID indicated by FUSE for specified SCLK
+} ATOM_AVAILABLE_SCLK_LIST;
+
+/// Integrate System Info Table is used for Llano/Ontario APU
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 {
+  ATOM_COMMON_TABLE_HEADER    sHeader;                       ///< Standard Header
+  ULONG                       ulBootUpEngineClock;           ///< VBIOS bootup Engine clock frequency, in 10kHz unit.
+  ULONG                       excel994;
+  ULONG                       ulBootUpUMAClock;              ///< System memory boot up clock frequency in 10Khz unit.
+  ATOM_CLK_VOLT_CAPABILITY    sDISPCLK_Voltage[4];           ///< Report Display clock voltage requirement.
+  ULONG                       ulBootUpReqDisplayVector;      /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects:
+                                                               * ATOM_DEVICE_CRT1_SUPPORT                  0x0001
+                                                               * ATOM_DEVICE_CRT2_SUPPORT                  0x0010
+                                                               * ATOM_DEVICE_DFP1_SUPPORT                  0x0008
+                                                               * ATOM_DEVICE_DFP6_SUPPORT                  0x0040
+                                                               * ATOM_DEVICE_DFP2_SUPPORT                  0x0080
+                                                               * ATOM_DEVICE_DFP3_SUPPORT                  0x0200
+                                                               * ATOM_DEVICE_DFP4_SUPPORT                  0x0400
+                                                               * ATOM_DEVICE_DFP5_SUPPORT                  0x0800
+                                                               * ATOM_DEVICE_LCD1_SUPPORT                  0x0002
+                                                               */
+  ULONG                       ulOtherDisplayMisc;            ///< Other display related flags, not defined yet.
+  ULONG                       ulGPUCapInfo;                  /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode.
+                                                               *  @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode
+                                                               *  @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable
+                                                               */
+  ULONG                       ulSB_MMIO_Base_Addr;           ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage.
+  USHORT                      usRequestedPWMFreqInHz;        ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled.
+  UCHAR                       ucHtcTmpLmt;                   ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt.
+  UCHAR                       ucHtcHystLmt;                  ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt.
+  ULONG                       ulMinEngineClock;              ///< Min SCLK
+  ULONG                       ulSystemConfig;                /**< System configuration
+                                                               *  @li BIT[0] - 0: PCIE Power Gating Disabled, 1: PCIE Power Gating Enabled.
+                                                               *  @li BIT[1] - 0: DDR-DLL shut-down feature disabled, 1: DDR-DLL shut-down feature enabled.
+                                                               *  @li BIT[2] - 0: DDR-PLL Power down feature disabled, 1: DDR-PLL Power down feature enabled.
+                                                               */
+  ULONG                       ulCPUCapInfo;                  ///< TBD
+  USHORT                      usNBP0Voltage;                 ///< VID for voltage on NB P0 State
+  USHORT                      usNBP1Voltage;                 ///< VID for voltage on NB P1 State
+  USHORT                      usBootUpNBVoltage;             ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement.
+  USHORT                      usExtDispConnInfoOffset;       ///< Offset to sExtDispConnInfo inside the structure
+  USHORT                      usPanelRefreshRateRange;       /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set.
+                                                               * SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
+                                                               * SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
+                                                               * SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
+                                                               * SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
+                                                               */
+  UCHAR                       ucMemoryType;                  ///< Memory type (3 for DDR3)
+  UCHAR                       ucUMAChannelNumber;            ///< System memory channel numbers.
+  ULONG                       ulCSR_M3_ARB_CNTL_DEFAULT[10]; ///< Arrays with values for CSR M3 arbiter for default.
+  ULONG                       ulCSR_M3_ARB_CNTL_UVD[10];     ///< Arrays with values for CSR M3 arbiter for UVD playback.
+  ULONG                       ulCSR_M3_ARB_CNTL_FS3D[10];    ///< Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
+  ATOM_AVAILABLE_SCLK_LIST    sAvail_SCLK[5];                ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
+  ULONG                       ulGMCRestoreResetTime;         ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
+  ULONG                       ulMinimumNClk;                 ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
+  ULONG                       ulIdleNClk;                    ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
+  ULONG                       ulDDR_DLL_PowerUpTime;         ///< DDR PHY DLL power up time. Unit in ns.
+  ULONG                       ulDDR_PLL_PowerUpTime;         ///< DDR PHY PLL power up time. Unit in ns
+  USHORT                      usPCIEClkSSPercentage;         ///< usPCIEClkSSPercentage
+  USHORT                      usPCIEClkSSType;               ///< usPCIEClkSSType
+  USHORT                      usLvdsSSPercentage;            ///< usLvdsSSPercentage
+  USHORT                      usLvdsSSpreadRateIn10Hz;       ///< usLvdsSSpreadRateIn10Hz
+  USHORT                      usHDMISSPercentage;            ///< usHDMISSPercentage
+  USHORT                      usHDMISSpreadRateIn10Hz;       ///< usHDMISSpreadRateIn10Hz
+  USHORT                      usDVISSPercentage;             ///< usDVISSPercentage
+  USHORT                      usDVISSpreadRateIn10Hz;        ///< usDVISSpreadRateIn10Hz
+  ULONG                       SclkDpmBoostMargin;            ///< SclkDpmBoostMargin
+  ULONG                       SclkDpmThrottleMargin;         ///< SclkDpmThrottleMargin
+  USHORT                      SclkDpmTdpLimitPG;             ///< SclkDpmTdpLimitPG
+  USHORT                      SclkDpmTdpLimitBoost;          ///< SclkDpmTdpLimitBoost
+  ULONG                       ulBoostEngineCLock;            ///< ulBoostEngineCLock
+  UCHAR                       ulBoostVid_2bit;               ///< ulBoostVid_2bit
+  UCHAR                       EnableBoost;                   ///< EnableBoost
+  USHORT                      GnbTdpLimit;                   ///< GnbTdpLimit
+  USHORT                      usMaxLVDSPclkFreqInSingleLink; ///< usMaxLVDSPclkFreqInSingleLink
+  UCHAR                       ucLvdsMisc;                    ///< ucLvdsMisc
+  UCHAR                       ucLVDSReserved;                ///< ucLVDSReserved
+  ULONG                       ulReserved3[15];               ///< Reserved
+  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;    ///< Display connector definition
+} ATOM_INTEGRATED_SYSTEM_INFO_V6;
+
+/// this Table is used for Llano/Ontario APU
+typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 {
+  ATOM_INTEGRATED_SYSTEM_INFO_V6    sIntegratedSysInfo;      ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
+  ULONG                             ulPowerplayTable[128];   ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
+} ATOM_FUSION_SYSTEM_INFO_V1;
+
+/// Integrated Info table
+/// Upgrade is followed by Trinity SBIOS/VBIOS & Driver interface Design Document VER 0.5
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 {
+  ATOM_COMMON_TABLE_HEADER    sHeader;                       ///< Standard Header
+  ULONG                       ulBootUpEngineClock;           ///< VBIOS bootup Engine clock frequency, in 10kHz unit.
+  ULONG                       ulDentistVCOFreq;              ///< Dentist VCO clock in 10kHz unit.
+  ULONG                       ulBootUpUMAClock;              ///< System memory boot up clock frequency in 10Khz unit.
+  ATOM_CLK_VOLT_CAPABILITY    sDISPCLK_Voltage[4];           ///< Report Display clock voltage requirement.
+  ULONG                       ulBootUpReqDisplayVector;      /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects:
+                                                               * ATOM_DEVICE_CRT1_SUPPORT                  0x0001
+                                                               * ATOM_DEVICE_CRT2_SUPPORT                  0x0010
+                                                               * ATOM_DEVICE_DFP1_SUPPORT                  0x0008
+                                                               * ATOM_DEVICE_DFP6_SUPPORT                  0x0040
+                                                               * ATOM_DEVICE_DFP2_SUPPORT                  0x0080
+                                                               * ATOM_DEVICE_DFP3_SUPPORT                  0x0200
+                                                               * ATOM_DEVICE_DFP4_SUPPORT                  0x0400
+                                                               * ATOM_DEVICE_DFP5_SUPPORT                  0x0800
+                                                               * ATOM_DEVICE_LCD1_SUPPORT                  0x0002
+                                                               */
+  ULONG                       ulOtherDisplayMisc;            ///< Other display related flags, not defined yet.
+  ULONG                       ulGPUCapInfo;                  /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode.
+                                                               *  @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode
+                                                               *  @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable
+                                                               */
+  ULONG                       ulSB_MMIO_Base_Addr;           ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage.
+  USHORT                      usRequestedPWMFreqInHz;        ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled.
+  UCHAR                       ucHtcTmpLmt;                   ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt.
+  UCHAR                       ucHtcHystLmt;                  ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt.
+  ULONG                       ulMinEngineClock;              ///< Min SCLK
+  ULONG                       ulSystemConfig;                ///< TBD
+  ULONG                       ulCPUCapInfo;                  ///< TBD
+  USHORT                      usNBP0Voltage;                 ///< VID for voltage on NB P0 State
+  USHORT                      usNBP1Voltage;                 ///< VID for voltage on NB P1 State
+  USHORT                      usBootUpNBVoltage;             ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement.
+  USHORT                      usExtDispConnInfoOffset;       ///< Offset to sExtDispConnInfo inside the structure
+  USHORT                      usPanelRefreshRateRange;       /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set.
+                                                               * SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
+                                                               * SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
+                                                               * SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
+                                                               * SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
+                                                               */
+  UCHAR                       ucMemoryType;                  ///< Memory type (3 for DDR3)
+  UCHAR                       ucUMAChannelNumber;            ///< System memory channel numbers.
+  UCHAR                       strVBIOSMsg[40];               ///< Allow customer to have its own VBIOS message
+  ULONG                       ulReserved[20];                ///<
+  ATOM_AVAILABLE_SCLK_LIST    sAvail_SCLK[5];                ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
+  ULONG                       ulGMCRestoreResetTime;         ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
+  ULONG                       ulMinimumNClk;                 ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
+  ULONG                       ulIdleNClk;                    ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
+  ULONG                       ulDDR_DLL_PowerUpTime;         ///< DDR PHY DLL power up time. Unit in ns.
+  ULONG                       ulDDR_PLL_PowerUpTime;         ///< DDR PHY PLL power up time. Unit in ns
+  USHORT                      usPCIEClkSSPercentage;         ///<
+  USHORT                      usPCIEClkSSType;               ///<
+  USHORT                      usLvdsSSPercentage;            ///<
+  USHORT                      usLvdsSSpreadRateIn10Hz;       ///<
+  USHORT                      usHDMISSPercentage;            ///<
+  USHORT                      usHDMISSpreadRateIn10Hz;       ///<
+  USHORT                      usDVISSPercentage;             ///<
+  USHORT                      usDVISSpreadRateIn10Hz;        ///<
+  ULONG                       SclkDpmBoostMargin;            ///<
+  ULONG                       SclkDpmThrottleMargin;         ///<
+  USHORT                      SclkDpmTdpLimitPG;             ///<
+  USHORT                      SclkDpmTdpLimitBoost;          ///<
+  ULONG                       ulBoostEngineCLock;            ///<
+  UCHAR                       ulBoostVid_2bit;               ///<
+  UCHAR                       EnableBoost;                   ///<
+  USHORT                      GnbTdpLimit;                   ///<
+  USHORT                      usMaxLVDSPclkFreqInSingleLink; ///<
+  UCHAR                       ucLvdsMisc;                    ///<
+  UCHAR                       gnbgfxline429 ;        ///<
+  UCHAR                       ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///<
+  UCHAR                       ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;    ///<
+  UCHAR                       ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;   ///<
+  UCHAR                       ucLVDSPwrOffSeqDEtoDIGON_in4Ms;     ///<
+  UCHAR                       ucLVDSOffToOnDelay_in4Ms;           ///<
+  UCHAR                       ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;  ///<
+  UCHAR                       ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///<
+  UCHAR                       ucLVDSReserved1;                    ///<
+  ULONG                       ulLCDBitDepthControlVal;            ///<
+  ULONG                       ulNbpStateMemclkFreq[4];            ///<
+  USHORT                      usNBP2Voltage;                      ///<
+  USHORT                      usNBP3Voltage;                      ///<
+  ULONG                       ulNbpStateNClkFreq[4];              ///<
+  UCHAR                       ucNBDPMEnable;                      ///<
+  UCHAR                       ucReserved[3];                      ///<
+  UCHAR                       ucDPMState0VclkFid;                 ///<
+  UCHAR                       ucDPMState0DclkFid;                 ///<
+  UCHAR                       ucDPMState1VclkFid;                 ///<
+  UCHAR                       ucDPMState1DclkFid;                 ///<
+  UCHAR                       ucDPMState2VclkFid;                 ///<
+  UCHAR                       ucDPMState2DclkFid;                 ///<
+  UCHAR                       ucDPMState3VclkFid;                 ///<
+  UCHAR                       ucDPMState3DclkFid;                 ///<
+  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;         ///<
+} ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
+
+/// this Table is used for Llano/Ontario APU
+typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 {
+  ATOM_INTEGRATED_SYSTEM_INFO_V1_7  sIntegratedSysInfo;      ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_7 definition.
+  ULONG                             ulPowerplayTable[128];   ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
+} ATOM_FUSION_SYSTEM_INFO_V2;
+
+#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0)
+
+/// Define configuration values for ulGPUCapInfo
+// BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode.
+#define GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE      0x00ul
+#define GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE       0x01ul
+
+// BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode
+#define GPUCAPINFO_DP_MODE_USE_CASCADE_PLL_MODE        0x00ul
+#define GPUCAPINFO_DP_USE_SINGLE_PLL_MODE              0x02ul
+
+// BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable
+#define GPUCAPINFO_AUX_HW_MODE_DETECTION_ENABLE        0x00ul
+#define GPUCAPINFO_AUX_HW_MODE_DETECTION_DISABLE       0x08ul
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h
new file mode 100644
index 0000000000..0957f9d194
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h
@@ -0,0 +1,108 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe family specific services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBGFXFAMSERVICES_H_
+#define _GNBGFXFAMSERVICES_H_
+
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbPcie.h"
+
+
+AGESA_STATUS
+GfxFmMapEngineToDisplayPath (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+VOID
+GfxFmSetIdleVoltageMode (
+  IN      GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+VOID
+GfxFmDisableController (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h
new file mode 100644
index 0000000000..2a3d02414c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h
@@ -0,0 +1,222 @@
+/**
+ * @file
+ *
+ * Misc common definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBIOMMU_H_
+#define _GNBIOMMU_H_
+
+#pragma pack (push, 1)
+
+
+/// IVRS block
+typedef enum {
+  IvrsIvhdBlock               = 0x10,       ///< I/O Virtualization Hardware Definition Block
+  IvrsIvmdBlock               = 0x20,       ///< I/O Virtualization Memory Definition Block for all peripherals
+  IvrsIvmdBlockSingle         = 0x21,       ///< IVMD block for specified peripheral
+  IvrsIvmdBlockRange          = 0x22,       ///< IVMD block for peripheral range
+  IvrsIvhdrBlock              = 0x40,       ///< IVHDR (Relative) block
+  IvrsIvmdrBlock              = 0x50,       ///< IVMDR (Relative) block for all peripherals
+  IvrsIvmdrBlockSingle        = 0x51        ///< IVMDR block for last IVHDR
+} IVRS_BLOCK_TYPE;
+
+#define DEVICE_ID(PciAddress) (UINT16) (((PciAddress).Address.Bus << 8) | ((PciAddress).Address.Device << 3) | (PciAddress).Address.Function)
+
+/// IVHD entry types
+typedef enum {
+  IvhdEntryPadding            =  0,         ///< Table padding
+  IvhdEntrySelect             =  2,         ///< Select
+  IvhdEntryStartRange         =  3,         ///< Start Range
+  IvhdEntryEndRange           =  4,         ///< End Range
+  IvhdEntryAliasSelect        =  66,        ///< Alias select
+  IvhdEntryAliasStartRange    =  67,        ///< Alias start range
+  IvhdEntryExtendedSelect     =  70,        ///< Extended select
+  IvhdEntryExtendedStartRange =  71,        ///< Extended Start range
+  IvhdEntrySpecialDevice      =  72         ///< Special device
+} IVHD_ENTRY_TYPE;
+
+/// Special device variety
+typedef enum {
+  IvhdSpecialDeviceIoapic     = 0x1,        ///< IOAPIC
+  IvhdSpecialDeviceHpet       = 0x2         ///< HPET
+} IVHD_SPECIAL_DEVICE;
+
+
+#define IVHD_FLAG_COHERENT          BIT5
+#define IVHD_FLAG_IOTLBSUP          BIT4
+#define IVHD_FLAG_ISOC              BIT3
+#define IVHD_FLAG_RESPASSPW         BIT2
+#define IVHD_FLAG_PASSPW            BIT1
+#define IVHD_FLAG_PPRSUB            BIT7
+#define IVHD_FLAG_PREFSUP           BIT6
+
+#define IVHD_EFR_XTSUP_OFFSET       0
+#define IVHD_EFR_NXSUP_OFFSET       1
+#define IVHD_EFR_GTSUP_OFFSET       2
+#define IVHD_EFR_GLXSUP_OFFSET      3
+#define IVHD_EFR_IASUP_OFFSET       5
+#define IVHD_EFR_GASUP_OFFSET       6
+#define IVHD_EFR_HESUP_OFFSET       7
+#define IVHD_EFR_PASMAX_OFFSET      8
+#define IVHD_EFR_PNCOUNTERS_OFFSET  13
+#define IVHD_EFR_PNBANKS_OFFSET     17
+#define IVHD_EFR_MSINUMPPR_OFFSET   23
+#define IVHD_EFR_GATS_OFFSET        28
+#define IVHD_EFR_HATS_OFFSET        30
+
+#define IVINFO_HTATSRESV_MASK       0x00400000ul
+#define IVINFO_VASIZE_MASK          0x003F8000ul
+#define IVINFO_PASIZE_MASK          0x00007F00ul
+#define IVINFO_GASIZE_MASK          0x000000E0ul
+
+#define IVHD_INFO_MSINUM_OFFSET     0
+#define IVHD_INFO_UNITID_OFFSET     8
+
+#define IVMD_FLAG_EXCLUSION_RANGE   BIT3
+#define IVMD_FLAG_IW                BIT2
+#define IVMD_FLAG_IR                BIT1
+#define IVMD_FLAG_UNITY             BIT0
+
+/// IVRS header
+typedef struct {
+  UINT8   Sign[4];           ///< Signature
+  UINT32  TableLength;       ///< Table Length
+  UINT8   Revision;          ///< Revision
+  UINT8   Checksum;          ///< Checksum
+  UINT8   OemId[6];          ///< OEM ID
+  UINT8   OemTableId[8];     ///< OEM Tabled ID
+  UINT32  OemRev;            ///< OEM Revision
+  UINT8   CreatorId[4];      ///< Creator ID
+  UINT32  CreatorRev;        ///< Creator Revision
+  UINT32  IvInfo;            ///< IvInfo
+  UINT64  Reserved;          ///< Reserved
+} IOMMU_IVRS_HEADER;
+
+/// IVRS IVHD Entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT8   Flags;              ///< Flags
+  UINT16  Length;             ///< Length
+  UINT16  DeviceId;           ///< DeviceId
+  UINT16  CapabilityOffset;   ///< CapabilityOffset
+  UINT64  BaseAddress;        ///< BaseAddress
+  UINT16  PciSegment;         ///< Pci segment
+  UINT16  IommuInfo;          ///< IOMMU info
+  UINT32  IommuEfr;           ///< reserved
+} IVRS_IVHD_ENTRY;
+
+/// IVHD generic entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  DeviceId;           ///< Device id
+  UINT8   DataSetting;        ///< Data settings
+} IVHD_GENERIC_ENTRY;
+
+///IVHD alias entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  DeviceId;           ///< Device id
+  UINT8   DataSetting;        ///< Data settings
+  UINT8   Reserved;           ///< Reserved
+  UINT16  AliasDeviceId;      ///< Alias device id
+  UINT8   Reserved2;          ///< Reserved
+} IVHD_ALIAS_ENTRY;
+
+///IVHD extended entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  DeviceId;           ///< Device id
+  UINT8   DataSetting;        ///< Data settings
+  UINT32  ExtSetting;         ///< Extended settings
+} IVHD_EXT_ENTRY;
+
+/// IVHD special entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  Reserved;           ///< Reserved
+  UINT8   DataSetting;        ///< Data settings
+  UINT8   Handle;             ///< Handle
+  UINT16  AliasDeviceId;      ///< Alis device id
+  UINT8   Variety;            ///< Variety
+} IVHD_SPECIAL_ENTRY;
+
+/// IVRS IVMD Entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT8   Flags;              ///< Flags
+  UINT16  Length;             ///< Length
+  UINT16  DeviceId;           ///< DeviceId
+  UINT16  AuxiliaryData;      ///< Auxiliary data
+  UINT64  Reserved;           ///< Reserved (0000_0000_0000_0000)
+  UINT64  BlockStart;         ///< IVMD start address
+  UINT64  BlockLength;        ///< IVMD memory block length
+} IVRS_IVMD_ENTRY;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
new file mode 100644
index 0000000000..1985beb3a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
@@ -0,0 +1,132 @@
+/* $NoKeywords:$ */
+ /**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "GeneralServices.h"
+#include  "cpuFamilyTranslation.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define  FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DIspathc feature tanle
+ *
+ *
+ */
+
+AGESA_STATUS
+GnbLibDispatchFeatures (
+  IN      OPTION_GNB_CONFIGURATION  *ConfigTable,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS    Status;
+  AGESA_STATUS    AgesaStatus;
+  CPU_LOGICAL_ID  LogicalId;
+
+  AgesaStatus = AGESA_SUCCESS;
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  while (ConfigTable->GnbFeature != NULL) {
+    if ((ConfigTable->Type & LogicalId.Family) != 0) {
+      Status = ConfigTable->GnbFeature (StdHeader);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+    ConfigTable++;
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h
new file mode 100644
index 0000000000..dfbbc9e708
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBLIBFEATURES_H_
+#define _GNBLIBFEATURES_H_
+
+
+AGESA_STATUS
+GnbLibDispatchFeatures (
+  IN      OPTION_GNB_CONFIGURATION  *ConfigTable,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
new file mode 100644
index 0000000000..fbb8d3b6a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
@@ -0,0 +1,418 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe component definitions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+
+*
+*/
+
+#ifndef _GNBPCIE_H_
+#define _GNBPCIE_H_
+
+#pragma pack (push, 1)
+
+#define MAX_NUMBER_OF_COMPLEXES                4
+
+#define DESCRIPTOR_TERMINATE_GNB               0x40000000ull
+#define DESCRIPTOR_TERMINATE_TOPOLOGY          0x20000000ull
+#define DESCRIPTOR_ALLOCATED                   0x10000000ull
+#define DESCRIPTOR_VIRTUAL                     0x08000000ull
+#define DESCRIPTOR_PLATFORM                    0x04000000ull
+#define DESCRIPTOR_COMPLEX                     0x02000000ull
+#define DESCRIPTOR_SILICON                     0x01000000ull
+#define DESCRIPTOR_PCIE_WRAPPER                0x00800000ull
+#define DESCRIPTOR_DDI_WRAPPER                 0x00400000ull
+#define DESCRIPTOR_PCIE_ENGINE                 0x00200000ull
+#define DESCRIPTOR_DDI_ENGINE                  0x00100000ull
+
+#define DESCRIPTOR_ALL_WRAPPERS                (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER)
+#define DESCRIPTOR_ALL_ENGINES                 (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
+
+#define DESCRIPTOR_ALL_TYPES                   (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM)
+
+#define UNUSED_LANE_ID                         128
+//#define PCIE_LINK_RECEIVER_DETECTION_POOLING   (60 * 1000)
+//#define PCIE_LINK_L0_POOLING                   (60 * 1000)
+//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME       (2  * 1000)
+//#define PCIE_LINK_RESET_TO_TRAINING_TIME       (2  * 1000)
+
+// Get lowest PHY lane on engine
+#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0)
+// Get highest PHY lane on engine
+#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0)
+// Get number of lanes on wrapper
+#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0)
+// Check if virtual descriptor
+#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE)
+// Check if it is allocated descriptor
+#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE)
+// Check if it is last descriptor in list
+#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : TRUE)
+// Check if descriptor a PCIe engine
+#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE)
+// Check if descriptor a DDI engine
+#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE)
+// Check if descriptor a DDI wrapper
+#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE)
+// Check if descriptor a PCIe wrapper
+#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE)
+// Check if descriptor a PCIe wrapper
+#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1)) : NULL)
+
+#define LANE_TYPE_PCIE_CORE_CONFIG              0x00000001ul
+#define LANE_TYPE_PCIE_CORE_ALLOC               0x00000002ul
+#define LANE_TYPE_PCIE_CORE_ACTIVE              0x00000004ul
+#define LANE_TYPE_PCIE_SB_CORE_CONFIG           0x00000008ul
+#define LANE_TYPE_PCIE_CORE_HOTPLUG             0x00000010ul
+#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE        0x00000020ul
+#define LANE_TYPE_PCIE_PHY                      0x00000100ul
+#define LANE_TYPE_PCIE_PHY_NATIVE               0x00000200ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE        0x00000400ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG       0x00000800ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE  0x00001000ul
+#define LANE_TYPE_DDI_PHY                       0x00010000ul
+#define LANE_TYPE_DDI_PHY_NATIVE                0x00020000ul
+#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE         0x00040000ul
+#define LANE_TYPE_PHY_NATIVE_ALL                0x00100000ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL    0x00200000ul
+#define LANE_TYPE_CORE_ALL                      LANE_TYPE_PHY_NATIVE_ALL
+#define LANE_TYPE_ALL                           LANE_TYPE_PHY_NATIVE_ALL
+
+#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \
+                              LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \
+                              LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \
+                              LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \
+                              LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \
+                              LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)
+
+#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE)
+
+
+#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY          0x00000001ull
+#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY   0x00000002ull
+#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL          0x00000004ull
+#define INIT_STATUS_PCIE_TRAINING_SUCCESS            0x00000008ull
+#define INIT_STATUS_PCIE_EP_NOT_PRESENT              0x00000010ull
+#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE          0x00000020ull
+#define INIT_STATUS_DDI_ACTIVE                       0x00000040ull
+#define INIT_STATUS_ALLOCATED                        0x00000080ull
+
+#define PCIE_PORT_GEN_CAP_BOOT                       0x00000001ul
+#define PCIE_PORT_GEN_CAP_MAX                        0x00000002ul
+#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS                0x00000010ul
+#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS            0x00000011ul
+#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS            0x00000012ul
+
+#define PCIE_POWERGATING_SKIP_CORE                   0x00000001ul
+#define PCIE_POWERGATING_SKIP_PHY                    0x00000002ul
+
+/// PCIe Link Training State
+typedef enum {
+  PcieTrainingStandard,                                ///< Standard training algorithm. Training contained to AmdEarlyInit.
+                                                       ///< PCIe device accessible after AmdEarlyInit complete
+  PcieTrainingDistributed,                             ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore
+                                                       ///< PCIe device accessible after AmdPostInit complete.
+                                                       ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots.
+} PCIE_TRAINING_ALGORITHM;
+
+/// PCIe Link Training State
+typedef enum {
+  LinkStateResetAssert,                                 ///< Assert port GPIO reset
+  LinkStateResetDuration,                               ///< Timeout for reset duration
+  LinkStateResetExit,                                   ///< Deassert port GPIO reset
+  LinkTrainingResetTimeout,                             ///< Port GPIO reset timeout
+  LinkStateReleaseTraining,                             ///< Release link training
+  LinkStateDetectPresence,                              ///< Detect device presence
+  LinkStateDetecting,                                   ///< Detect link training.
+  LinkStateBrokenLane,                                  ///< Check and handle broken lane
+  LinkStateGen2Fail,                                    ///< Check and handle device that fail training if GEN2 capability advertised
+  LinkStateL0,                                          ///< Device trained to L0
+  LinkStateVcoNegotiation,                              ///< Check VCO negotiation complete
+  LinkStateRetrain,                                     ///< Force retrain link.
+  LinkStateTrainingFail,                                ///< Link training fail
+  LinkStateTrainingSuccess,                             ///< Link training success
+  LinkStateGfxWorkaround,                               ///< GFX workaround
+  LinkStateCompliance,                                  ///< Link in compliance mode
+  LinkStateDeviceNotPresent,                            ///< Link is not connected
+  LinkStateTrainingCompleted                            ///< Link training completed
+} PCIE_LINK_TRAINING_STATE;
+
+/// PCIe Port Visibility
+typedef enum {
+  UnhidePorts,                                          ///< Command to unhide port
+  HidePorts,                                            ///< Command to hide unused ports
+} PCIE_PORT_VISIBILITY;
+
+
+/// Table Register Entry
+typedef struct {
+  UINT16          Reg;                                  ///< Address
+  UINT32          Mask;                                 ///< Mask
+  UINT32          Data;                                 ///< Data
+} PCIE_PORT_REGISTER_ENTRY;
+
+/// Table Register Entry
+typedef struct {
+  PCIE_PORT_REGISTER_ENTRY  *Table;                     ///< Table
+  UINT32                    Length;                     ///< Length
+} PCIE_PORT_REGISTER_TABLE_HEADER;
+
+/// Table Register Entry
+typedef struct {
+  UINT32          Reg;                                  ///< Address
+  UINT32          Mask;                                 ///< Mask
+  UINT32          Data;                                 ///< Data
+} PCIE_HOST_REGISTER_ENTRY;
+
+/// Table Register Entry
+typedef struct {
+  PCIE_HOST_REGISTER_ENTRY  *Table;                     ///< Table
+  UINT32                    Length;                     ///< Length
+} PCIE_HOST_REGISTER_TABLE_HEADER;
+
+///Link ASPM info
+typedef struct {
+  PCI_ADDR        DownstreamPort;                       ///< PCI address of downstream port
+  PCIE_ASPM_TYPE  DownstreamAspm;                       ///< Downstream Device Aspm
+  PCI_ADDR        UpstreamPort;                         ///< PCI address of upstream port
+  PCIE_ASPM_TYPE  UpstreamAspm;                         ///< Upstream Device Capability
+  PCIE_ASPM_TYPE  RequestedAspm;                        ///< Requested ASPM
+} PCIe_LINK_ASPM;
+
+///PCIe ASPM Latency Information
+typedef struct {
+  UINT8  MaxL0sExitLatency;                             ///< Max L0s exit latency in us
+  UINT8  MaxL1ExitLatency;                              ///< Max L1 exit latency in us
+} PCIe_ASPM_LATENCY_INFO;
+
+/// PCI address association
+typedef struct {
+  UINT8 NewDeviceAddress;                                ///< New PCI address (Device,Fucntion)
+  UINT8 NativeDeviceAddress;                             ///< Native PCI address (Device,Fucntion)
+} PCI_ADDR_LIST;
+
+/// The return status for GFX Card Workaround.
+typedef enum {
+  GFX_WORKAROUND_DEVICE_NOT_READY,                       ///< GFX Workaround device is not ready.
+  GFX_WORKAROUND_RESET_DEVICE,                           ///< GFX Workaround device need reset.
+  GFX_WORKAROUND_SUCCESS                                 ///< The service completed normally.
+} GFX_WORKAROUND_STATUS;
+
+/// GFX workaround control
+typedef enum {
+  GfxWorkaroundDisable,                                   ///< GFX Workaround disabled
+  GfxWorkaroundEnable                                     ///< GFX Workaround enabled
+} GFX_WORKAROUND_CONTROL;
+
+/// PIF lane power state
+typedef enum {
+  PifPowerStateL0,                                        ///<
+  PifPowerStateLS1,                                       ///<
+  PifPowerStateLS2,                                       ///<
+  PifPowerStateOff = 0x7,                                 ///<
+} PCIE_PIF_POWER_STATE;
+
+/// PIF lane power control
+typedef enum {
+  PowerDownPifs,                                          ///<
+  PowerUpPifs                                             ///<
+} PCIE_PIF_POWER_CONTROL;
+
+///PLL rumup time
+typedef enum {
+  NormalRampup,                                           ///<
+  LongRampup,                                             ///<
+} PCIE_PLL_RAMPUP_TIME;
+
+typedef UINT16 PCIe_ENGINE_INIT_STATUS;
+
+/// PCIe port configuration info
+typedef struct {
+  PCIe_PORT_DATA          PortData;                     ///< Port data
+  UINT8                   StartCoreLane;                ///< Start Core Lane
+  UINT8                   EndCoreLane;                  ///< End Core lane
+  UINT8                   NativeDevNumber :5;           ///< Native PCI device number of the port
+  UINT8                   NativeFunNumber :3;           ///< Native PCI function number of the port
+  UINT8                   CoreId :4;                    ///< PCIe core ID
+  UINT8                   PortId :4;                    ///< Port ID on wrapper
+  PCI_ADDR                Address;                      ///< PCI address of the port
+  UINT8                   State;                        ///< Training state
+  UINT8                   PcieBridgeId:4;               ///< IOC PCIe bridge ID
+  UINT16                  UnitId:12;                    ///< Port start unit ID
+  UINT16                  NumberOfUnitId:4;             ///< Def number of unitIDs assigned to port
+  UINT8                   GfxWrkRetryCount:4;           ///< Number of retry for GFX workaround
+  UINT32                  TimeStamp;                    ///< Time stamp used to during training process
+  UINT8                   LogicalBridgeId;              ///< Logical Bridge ID
+} PCIe_PORT_CONFIG;
+
+///Descriptor header
+typedef struct {
+  UINT32                  DescriptorFlags;              ///< Descriptor flags
+  UINT16                  Parent;                       ///< Offset of parent descriptor
+  UINT16                  Peer;                         ///< Offset of the peer descriptor
+  UINT16                  Child;                        ///< Offset of the list of child descriptors
+} PCIe_DESCRIPTOR_HEADER;
+
+/// DDI (Digital Display Interface) configuration info
+typedef struct {
+  PCIe_DDI_DATA           DdiData;                      ///< DDI Data
+  UINT8                   DisplayPriorityIndex;         ///< Display priority index
+  UINT8                   ConnectorId;                  ///< Connector id determined by enumeration
+  UINT8                   DisplayDeviceId;              ///< Display device id determined by enumeration
+} PCIe_DDI_CONFIG;
+
+
+/// Engine configuration data
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descripto header
+  PCIe_ENGINE_DATA        EngineData;                   ///< Engine Data
+  PCIe_ENGINE_INIT_STATUS InitStatus;                   ///< Initialization Status
+  UINT8                   Scratch;                      ///< Scratch pad
+  union {
+    PCIe_PORT_CONFIG      Port;                         ///< PCIe port configuration data
+    PCIe_DDI_CONFIG       Ddi;                          ///< DDI configuration data
+  } Type;
+} PCIe_ENGINE_CONFIG;
+
+/// Wrapper configuration data
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT8                   WrapId;                       ///< Wrapper ID
+  UINT8                   NumberOfPIFs;                 ///< Number of PIFs on wrapper
+  UINT8                   StartPhyLane;                 ///< Start PHY Lane
+  UINT8                   EndPhyLane;                   ///< End PHY Lane
+  UINT8                   StartPcieCoreId:4;            ///< Start PCIe Core ID
+  UINT8                   EndPcieCoreId:4;              ///< End PCIe Core ID
+  UINT8                   NumberOfLanes;                ///< Number of lanes
+  struct {
+    UINT8                 PowerOffUnusedLanes:1;        ///< Power Off unused lanes
+    UINT8                 PowerOffUnusedPlls:1;         ///< Power Off unused Plls
+    UINT8                 ClkGating:1;                  ///< TXCLK gating
+    UINT8                 LclkGating:1;                 ///< LCLK gating
+    UINT8                 TxclkGatingPllPowerDown:1;    ///< TXCLK clock gating PLL power down
+    UINT8                 PllOffInL1:1;                 ///< PLL off in L1
+    UINT8                 AccessEncoding:1;             ///< Reg access encoding
+  } Features;
+  UINT8                   MasterPll;                    ///< Bitmap of master PLL
+} PCIe_WRAPPER_CONFIG;
+
+
+/// Silicon configuration data
+typedef struct  {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT8                   SiliconId;                    ///< Gnb silicon(module) ID
+  UINT8                   NodeId;                       ///< Node to which GNB connected
+  UINT8                   LinkId;                       ///< Link to which GNB connected if LinkId > 3 GNB connected to sublink = LinkId - 4
+  PCI_ADDR                Address;                      ///< PCI address of GNB host bridge
+} PCIe_SILICON_CONFIG;
+
+typedef PCIe_SILICON_CONFIG GNB_HANDLE;
+
+/// Complex configuration data
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT8                   SocketId;                     ///< Processor socket ID
+} PCIe_COMPLEX_CONFIG;
+
+/// PCIe platform configuration info
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT32                  StdHeader;                    ///< Standard configuration header TODO:Used to be PVOID
+  UINT32                  LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+  UINT32                  LinkL0Pooling;                ///< Pooling for link to get to L0 in us
+  UINT32                  LinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
+  UINT32                  LinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us                                                      ///
+  UINT8                   GfxCardWorkaround;            ///< GFX Card Workaround
+  UINT8                   PsppPolicy;                   ///< PSPP policy
+  UINT8                   TrainingExitState;            ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE)
+  UINT8                   TrainingAlgorithm;            ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
+  PCIe_COMPLEX_CONFIG     ComplexList[MAX_NUMBER_OF_COMPLEXES];  ///< Complex
+} PCIe_PLATFORM_CONFIG;
+
+/// PCIe Engine Description
+typedef struct {
+  UINT32                  Flags;                        /**< Descriptor flags
+                                                         * @li @b Bit31 - last descriptor on wrapper
+                                                         * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
+                                                         */
+  PCIe_ENGINE_DATA        EngineData;                   ///< Engine Data
+} PCIe_ENGINE_DESCRIPTOR;
+
+/// PCIe Lane allocation descriptor
+typedef struct {
+  UINT32                  Flags;                        ///< Flags
+  UINT8                   WrapId;                       ///< Wrapper ID
+  UINT8                   EngineType;                   ///< Engine Type
+  UINT8                   NumberOfEngines;              ///< Number of engines to configure
+  UINT8                   NumberOfConfigurations;       ///< Number of possible configurations
+  UINT8                   *ConfigTable;                 ///< Pointer to config table
+} PCIe_LANE_ALLOC_DESCRIPTOR;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h
new file mode 100644
index 0000000000..5942a71df6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h
@@ -0,0 +1,275 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe family specific services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIEFAMSERVICES_H_
+#define _GNBPCIEFAMSERVICES_H_
+
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+
+AGESA_STATUS
+PcieFmGetComplexDataLength (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieFmBuildComplexConfiguration (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieFmConfigureEnginesLaneAllocation (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIE_ENGINE_TYPE              EngineType,
+  IN       UINT8                         ConfigurationId
+  );
+
+typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIE_ENGINE_TYPE              EngineType,
+  IN       UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+PcieFmGetCoreConfigurationValue (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         CoreId,
+  IN       UINT64                        ConfigurationSignature,
+  IN       UINT8                         *ConfigurationValue
+  );
+
+typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         CoreId,
+  IN       UINT64                        ConfigurationSignature,
+  IN       UINT8                         *ConfigurationValue
+  );
+
+BOOLEAN
+PcieFmCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+AGESA_STATUS
+PcieFmMapPortPciAddress (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+BOOLEAN
+PcieFmCheckPortPcieLaneCanBeMuxed (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+CONST CHAR8*
+PcieFmDebugGetCoreConfigurationString (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         ConfigurationValue
+ );
+
+typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         ConfigurationValue
+ );
+
+CONST CHAR8*
+PcieFmDebugGetWrapperNameString (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper
+ );
+
+typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper
+ );
+
+CONST CHAR8*
+PcieFmDebugGetHostRegAddressSpaceString (
+  IN      PCIe_SILICON_CONFIG            *Silicon,
+  IN      UINT16                         AddressFrame
+  );
+
+typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING (
+  IN      PCIe_SILICON_CONFIG            *Silicon,
+  IN      UINT16                         AddressFrame
+  );
+
+PCIE_LINK_SPEED_CAP
+PcieFmGetLinkSpeedCap (
+  IN       UINT32                        Flags,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP (
+  IN       UINT32                        Flags,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+VOID
+PcieFmSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP            LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+typedef VOID F_PCIEFMSETLINKSPEEDCAP (
+  IN      PCIE_LINK_SPEED_CAP            LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+UINT32
+PcieFmGetNativePhyLaneBitmap (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+AGESA_STATUS
+PcieFmAlibBuildAcpiTable (
+  IN       VOID                          *AlibSsdtPtr,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieFmGetSbConfigInfo (
+  IN       UINT8                        SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR         *SbPort,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO (
+  IN       UINT8                        SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR         *SbPort,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+
+/// PCIe config services
+typedef struct {
+  F_PCIEFMGETCOMPLEXDATALENGTH              *PcieFmGetComplexDataLength;              ///< PcieFmGetComplexDataLength
+  F_PCIEFMBUILDCOMPLEXCONFIGURATION         *PcieFmBuildComplexConfiguration;         ///< PcieFmBuildComplexConfiguration
+  F_PCIEFMCONFIGUREENGINESLANEALLOCATION    *PcieFmConfigureEnginesLaneAllocation;    ///< PcieFmConfigureEnginesLaneAllocation
+  F_PCIEFMCHECKPORTPCIDEVICEMAPPING         *PcieFmCheckPortPciDeviceMapping;         ///< PcieFmCheckPortPciDeviceMapping
+  F_PCIEFMMAPPORTPCIADDRESS                 *PcieFmMapPortPciAddress;                 ///< PcieFmMapPortPciAddress
+  F_PCIEFMCHECKPORTPCIELANECANBEMUXED       *PcieFmCheckPortPcieLaneCanBeMuxed;       ///< PcieFmCheckPortPcieLaneCanBeMuxed
+  F_PCIEFMGETSBCONFIGINFO                   *PcieFmGetSbConfigInfo;                   ///< PcieFmGetSbConfigInfo
+} PCIe_FAM_CONFIG_SERVICES;
+
+/// PCIe init services
+typedef struct {
+  F_PCIEFMGETCORECONFIGURATIONVALUE         *PcieFmGetCoreConfigurationValue;         ///< PcieFmGetCoreConfigurationValue
+  F_PCIEFMGETLINKSPEEDCAP                   *PcieFmGetLinkSpeedCap;                   ///< PcieFmGetLinkSpeedCap
+  F_PCIEFMGETNATIVEPHYLANEBITMAP            *PcieFmGetNativePhyLaneBitmap;            ///< PcieFmGetNativePhyLaneBitmap
+  F_PCIEFMSETLINKSPEEDCAP                   *PcieFmSetLinkSpeedCap;                   ///< PcieFmSetLinkSpeedCap
+} PCIe_FAM_INIT_SERVICES;
+
+///PCIe debug services
+typedef struct {
+  F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue
+  F_PCIEFMDEBUGGETWRAPPERNAMESTRING         *PcieFmDebugGetWrapperNameString;         ///< PcieFmDebugGetWrapperNameString
+  F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING   *PcieFmDebugGetCoreConfigurationString;   ///< PcieFmDebugGetCoreConfigurationString
+} PCIe_FAM_DEBUG_SERVICES;
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h
new file mode 100644
index 0000000000..42824205ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h
@@ -0,0 +1,10111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Register definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBREGISTERSLN_H_
+#define _GNBREGISTERSLN_H_
+#define  TYPE_D0F0                  0x1
+#define  TYPE_D0F0x64               0x2
+#define  TYPE_D0F0x98               0x3
+#define  TYPE_D0F0xE4               0x5
+#define  TYPE_DxF0                  0x6
+#define  TYPE_DxF0xE4               0x7
+#define  TYPE_D18F1                 0xb
+#define  TYPE_D18F2                 0xc
+#define  TYPE_D18F3                 0xd
+#define  TYPE_MSR                   0x10
+#define  TYPE_D1F0                  0x11
+#define  TYPE_GMM                   0x12
+#define  D18F2x9C  0xe
+#define  GMM       0x11
+#ifndef WRAP_SPACE
+  #define  WRAP_SPACE(w, x)   (0x01300000 | (w << 16) | (x))
+#endif
+#ifndef CORE_SPACE
+  #define  CORE_SPACE(c, x)   (0x00010000 | (c << 24) | (x))
+#endif
+#ifndef PHY_SPACE
+  #define  PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+#ifndef  PIF_SPACE
+  #define  PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+// **** D0F0x00 Register Definition ****
+// Address
+#define D0F0x00_ADDRESS                                         0x0
+
+// Type
+#define D0F0x00_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x00_VendorID_OFFSET                                 0
+#define D0F0x00_VendorID_WIDTH                                  16
+#define D0F0x00_VendorID_MASK                                   0xffff
+#define D0F0x00_DeviceID_OFFSET                                 16
+#define D0F0x00_DeviceID_WIDTH                                  16
+#define D0F0x00_DeviceID_MASK                                   0xffff0000
+
+/// D0F0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x00_STRUCT;
+
+// **** D0F0x04 Register Definition ****
+// Address
+#define D0F0x04_ADDRESS                                         0x4
+
+// Type
+#define D0F0x04_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x04_IoAccessEn_OFFSET                               0
+#define D0F0x04_IoAccessEn_WIDTH                                1
+#define D0F0x04_IoAccessEn_MASK                                 0x1
+#define D0F0x04_MemAccessEn_OFFSET                              1
+#define D0F0x04_MemAccessEn_WIDTH                               1
+#define D0F0x04_MemAccessEn_MASK                                0x2
+#define D0F0x04_BusMasterEn_OFFSET                              2
+#define D0F0x04_BusMasterEn_WIDTH                               1
+#define D0F0x04_BusMasterEn_MASK                                0x4
+#define D0F0x04_SpecialCycleEn_OFFSET                           3
+#define D0F0x04_SpecialCycleEn_WIDTH                            1
+#define D0F0x04_SpecialCycleEn_MASK                             0x8
+#define D0F0x04_MemWriteInvalidateEn_OFFSET                     4
+#define D0F0x04_MemWriteInvalidateEn_WIDTH                      1
+#define D0F0x04_MemWriteInvalidateEn_MASK                       0x10
+#define D0F0x04_PalSnoopEn_OFFSET                               5
+#define D0F0x04_PalSnoopEn_WIDTH                                1
+#define D0F0x04_PalSnoopEn_MASK                                 0x20
+#define D0F0x04_ParityErrorEn_OFFSET                            6
+#define D0F0x04_ParityErrorEn_WIDTH                             1
+#define D0F0x04_ParityErrorEn_MASK                              0x40
+#define D0F0x04_Reserved_7_7_OFFSET                             7
+#define D0F0x04_Reserved_7_7_WIDTH                              1
+#define D0F0x04_Reserved_7_7_MASK                               0x80
+#define D0F0x04_SerrEn_OFFSET                                   8
+#define D0F0x04_SerrEn_WIDTH                                    1
+#define D0F0x04_SerrEn_MASK                                     0x100
+#define D0F0x04_FastB2BEn_OFFSET                                9
+#define D0F0x04_FastB2BEn_WIDTH                                 1
+#define D0F0x04_FastB2BEn_MASK                                  0x200
+#define D0F0x04_Reserved_19_10_OFFSET                           10
+#define D0F0x04_Reserved_19_10_WIDTH                            10
+#define D0F0x04_Reserved_19_10_MASK                             0xffc00
+#define D0F0x04_CapList_OFFSET                                  20
+#define D0F0x04_CapList_WIDTH                                   1
+#define D0F0x04_CapList_MASK                                    0x100000
+#define D0F0x04_PCI66En_OFFSET                                  21
+#define D0F0x04_PCI66En_WIDTH                                   1
+#define D0F0x04_PCI66En_MASK                                    0x200000
+#define D0F0x04_Reserved_22_22_OFFSET                           22
+#define D0F0x04_Reserved_22_22_WIDTH                            1
+#define D0F0x04_Reserved_22_22_MASK                             0x400000
+#define D0F0x04_FastBackCapable_OFFSET                          23
+#define D0F0x04_FastBackCapable_WIDTH                           1
+#define D0F0x04_FastBackCapable_MASK                            0x800000
+#define D0F0x04_Reserved_24_24_OFFSET                           24
+#define D0F0x04_Reserved_24_24_WIDTH                            1
+#define D0F0x04_Reserved_24_24_MASK                             0x1000000
+#define D0F0x04_DevselTiming_OFFSET                             25
+#define D0F0x04_DevselTiming_WIDTH                              2
+#define D0F0x04_DevselTiming_MASK                               0x6000000
+#define D0F0x04_SignalTargetAbort_OFFSET                        27
+#define D0F0x04_SignalTargetAbort_WIDTH                         1
+#define D0F0x04_SignalTargetAbort_MASK                          0x8000000
+#define D0F0x04_ReceivedTargetAbort_OFFSET                      28
+#define D0F0x04_ReceivedTargetAbort_WIDTH                       1
+#define D0F0x04_ReceivedTargetAbort_MASK                        0x10000000
+#define D0F0x04_ReceivedMasterAbort_OFFSET                      29
+#define D0F0x04_ReceivedMasterAbort_WIDTH                       1
+#define D0F0x04_ReceivedMasterAbort_MASK                        0x20000000
+#define D0F0x04_SignaledSystemError_OFFSET                      30
+#define D0F0x04_SignaledSystemError_WIDTH                       1
+#define D0F0x04_SignaledSystemError_MASK                        0x40000000
+#define D0F0x04_ParityErrorDetected_OFFSET                      31
+#define D0F0x04_ParityErrorDetected_WIDTH                       1
+#define D0F0x04_ParityErrorDetected_MASK                        0x80000000
+
+/// D0F0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                           SpecialCycleEn:1 ; ///<
+    UINT32                                     MemWriteInvalidateEn:1 ; ///<
+    UINT32                                               PalSnoopEn:1 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                FastB2BEn:1 ; ///<
+    UINT32                                           Reserved_19_10:10; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x04_STRUCT;
+
+// **** D0F0x08 Register Definition ****
+// Address
+#define D0F0x08_ADDRESS                                         0x8
+
+// Type
+#define D0F0x08_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x08_RevID_OFFSET                                    0
+#define D0F0x08_RevID_WIDTH                                     8
+#define D0F0x08_RevID_MASK                                      0xff
+#define D0F0x08_ClassCode_OFFSET                                8
+#define D0F0x08_ClassCode_WIDTH                                 24
+#define D0F0x08_ClassCode_MASK                                  0xffffff00
+
+/// D0F0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x08_STRUCT;
+
+// **** D0F0x0C Register Definition ****
+// Address
+#define D0F0x0C_ADDRESS                                         0xc
+
+// Type
+#define D0F0x0C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x0C_CacheLineSize_OFFSET                            0
+#define D0F0x0C_CacheLineSize_WIDTH                             8
+#define D0F0x0C_CacheLineSize_MASK                              0xff
+#define D0F0x0C_LatencyTimer_OFFSET                             8
+#define D0F0x0C_LatencyTimer_WIDTH                              8
+#define D0F0x0C_LatencyTimer_MASK                               0xff00
+#define D0F0x0C_HeaderTypeReg_OFFSET                            16
+#define D0F0x0C_HeaderTypeReg_WIDTH                             8
+#define D0F0x0C_HeaderTypeReg_MASK                              0xff0000
+#define D0F0x0C_BIST_OFFSET                                     24
+#define D0F0x0C_BIST_WIDTH                                      8
+#define D0F0x0C_BIST_MASK                                       0xff000000
+
+/// D0F0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x0C_STRUCT;
+
+// **** D0F0x2C Register Definition ****
+// Address
+#define D0F0x2C_ADDRESS                                         0x2c
+
+// Type
+#define D0F0x2C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x2C_SubsystemVendorID_OFFSET                        0
+#define D0F0x2C_SubsystemVendorID_WIDTH                         16
+#define D0F0x2C_SubsystemVendorID_MASK                          0xffff
+#define D0F0x2C_SubsystemID_OFFSET                              16
+#define D0F0x2C_SubsystemID_WIDTH                               16
+#define D0F0x2C_SubsystemID_MASK                                0xffff0000
+
+/// D0F0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorID:16; ///<
+    UINT32                                              SubsystemID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x2C_STRUCT;
+
+// **** D0F0x34 Register Definition ****
+// Address
+#define D0F0x34_ADDRESS                                         0x34
+
+// Type
+#define D0F0x34_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x34_CapPtr_OFFSET                                   0
+#define D0F0x34_CapPtr_WIDTH                                    8
+#define D0F0x34_CapPtr_MASK                                     0xff
+#define D0F0x34_Reserved_31_8_OFFSET                            8
+#define D0F0x34_Reserved_31_8_WIDTH                             24
+#define D0F0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x34_STRUCT;
+
+// **** D0F0x4C Register Definition ****
+// Address
+#define D0F0x4C_ADDRESS                                         0x4c
+
+// Type
+#define D0F0x4C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x4C_Function1Enable_OFFSET                          0
+#define D0F0x4C_Function1Enable_WIDTH                           1
+#define D0F0x4C_Function1Enable_MASK                            0x1
+#define D0F0x4C_ApicEnable_OFFSET                               1
+#define D0F0x4C_ApicEnable_WIDTH                                1
+#define D0F0x4C_ApicEnable_MASK                                 0x2
+#define D0F0x4C_Reserved_2_2_OFFSET                             2
+#define D0F0x4C_Reserved_2_2_WIDTH                              1
+#define D0F0x4C_Reserved_2_2_MASK                               0x4
+#define D0F0x4C_Cf8Dis_OFFSET                                   3
+#define D0F0x4C_Cf8Dis_WIDTH                                    1
+#define D0F0x4C_Cf8Dis_MASK                                     0x8
+#define D0F0x4C_PMEDis_OFFSET                                   4
+#define D0F0x4C_PMEDis_WIDTH                                    1
+#define D0F0x4C_PMEDis_MASK                                     0x10
+#define D0F0x4C_SerrDis_OFFSET                                  5
+#define D0F0x4C_SerrDis_WIDTH                                   1
+#define D0F0x4C_SerrDis_MASK                                    0x20
+#define D0F0x4C_Reserved_10_6_OFFSET                            6
+#define D0F0x4C_Reserved_10_6_WIDTH                             5
+#define D0F0x4C_Reserved_10_6_MASK                              0x7c0
+#define D0F0x4C_CRS_OFFSET                                      11
+#define D0F0x4C_CRS_WIDTH                                       1
+#define D0F0x4C_CRS_MASK                                        0x800
+#define D0F0x4C_CfgRdTime_OFFSET                                12
+#define D0F0x4C_CfgRdTime_WIDTH                                 3
+#define D0F0x4C_CfgRdTime_MASK                                  0x7000
+#define D0F0x4C_Reserved_22_15_OFFSET                           15
+#define D0F0x4C_Reserved_22_15_WIDTH                            8
+#define D0F0x4C_Reserved_22_15_MASK                             0x7f8000
+#define D0F0x4C_MMIOEnable_OFFSET                               23
+#define D0F0x4C_MMIOEnable_WIDTH                                1
+#define D0F0x4C_MMIOEnable_MASK                                 0x800000
+#define D0F0x4C_Reserved_25_24_OFFSET                           24
+#define D0F0x4C_Reserved_25_24_WIDTH                            2
+#define D0F0x4C_Reserved_25_24_MASK                             0x3000000
+#define D0F0x4C_HPDis_OFFSET                                    26
+#define D0F0x4C_HPDis_WIDTH                                     1
+#define D0F0x4C_HPDis_MASK                                      0x4000000
+#define D0F0x4C_Reserved_31_27_OFFSET                           27
+#define D0F0x4C_Reserved_31_27_WIDTH                            5
+#define D0F0x4C_Reserved_31_27_MASK                             0xf8000000
+
+/// D0F0x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          Function1Enable:1 ; ///<
+    UINT32                                               ApicEnable:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                   Cf8Dis:1 ; ///<
+    UINT32                                                   PMEDis:1 ; ///<
+    UINT32                                                  SerrDis:1 ; ///<
+    UINT32                                            Reserved_10_6:5 ; ///<
+    UINT32                                                      CRS:1 ; ///<
+    UINT32                                                CfgRdTime:3 ; ///<
+    UINT32                                           Reserved_22_15:8 ; ///<
+    UINT32                                               MMIOEnable:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    HPDis:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x4C_STRUCT;
+
+// **** D0F0x60 Register Definition ****
+// Address
+#define D0F0x60_ADDRESS                                         0x60
+
+// Type
+#define D0F0x60_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x60_MiscIndAddr_OFFSET                              0
+#define D0F0x60_MiscIndAddr_WIDTH                               7
+#define D0F0x60_MiscIndAddr_MASK                                0x7f
+#define D0F0x60_MiscIndWrEn_OFFSET                              7
+#define D0F0x60_MiscIndWrEn_WIDTH                               1
+#define D0F0x60_MiscIndWrEn_MASK                                0x80
+#define D0F0x60_Reserved_31_8_OFFSET                            8
+#define D0F0x60_Reserved_31_8_WIDTH                             24
+#define D0F0x60_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndAddr:7 ; ///<
+    UINT32                                              MiscIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x60_STRUCT;
+
+// **** D0F0x64 Register Definition ****
+// Address
+#define D0F0x64_ADDRESS                                         0x64
+
+// Type
+#define D0F0x64_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x64_MiscIndData_OFFSET                              0
+#define D0F0x64_MiscIndData_WIDTH                               32
+#define D0F0x64_MiscIndData_MASK                                0xffffffff
+
+/// D0F0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_STRUCT;
+
+
+/// D0F0x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Scratch:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x78_STRUCT;
+
+// **** D0F0x7C Register Definition ****
+// Address
+#define D0F0x7C_ADDRESS                                         0x7c
+
+// Type
+#define D0F0x7C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x7C_ForceIntGFXDisable_OFFSET                       0
+#define D0F0x7C_ForceIntGFXDisable_WIDTH                        1
+#define D0F0x7C_ForceIntGFXDisable_MASK                         0x1
+#define D0F0x7C_Reserved_31_1_OFFSET                            1
+#define D0F0x7C_Reserved_31_1_WIDTH                             31
+#define D0F0x7C_Reserved_31_1_MASK                              0xfffffffe
+
+/// D0F0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       ForceIntGFXDisable:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x7C_STRUCT;
+
+// **** D0F0x84 Register Definition ****
+// Address
+#define D0F0x84_ADDRESS                                         0x84
+
+// Type
+#define D0F0x84_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x84_Reserved_3_0_OFFSET                             0
+#define D0F0x84_Reserved_3_0_WIDTH                              4
+#define D0F0x84_Reserved_3_0_MASK                               0xf
+#define D0F0x84_Ev6Mode_OFFSET                                  4
+#define D0F0x84_Ev6Mode_WIDTH                                   1
+#define D0F0x84_Ev6Mode_MASK                                    0x10
+#define D0F0x84_Reserved_7_5_OFFSET                             5
+#define D0F0x84_Reserved_7_5_WIDTH                              3
+#define D0F0x84_Reserved_7_5_MASK                               0xe0
+#define D0F0x84_PmeMode_OFFSET                                  8
+#define D0F0x84_PmeMode_WIDTH                                   1
+#define D0F0x84_PmeMode_MASK                                    0x100
+#define D0F0x84_PmeTurnOff_OFFSET                               9
+#define D0F0x84_PmeTurnOff_WIDTH                                1
+#define D0F0x84_PmeTurnOff_MASK                                 0x200
+#define D0F0x84_Reserved_31_10_OFFSET                           10
+#define D0F0x84_Reserved_31_10_WIDTH                            22
+#define D0F0x84_Reserved_31_10_MASK                             0xfffffc00
+
+/// D0F0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                  Ev6Mode:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                  PmeMode:1 ; ///<
+    UINT32                                               PmeTurnOff:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x84_STRUCT;
+
+// **** D0F0x90 Register Definition ****
+// Address
+#define D0F0x90_ADDRESS                                         0x90
+
+// Type
+#define D0F0x90_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x90_Reserved_22_0_OFFSET                            0
+#define D0F0x90_Reserved_22_0_WIDTH                             23
+#define D0F0x90_Reserved_22_0_MASK                              0x7fffff
+#define D0F0x90_TopOfDram_OFFSET                                23
+#define D0F0x90_TopOfDram_WIDTH                                 9
+#define D0F0x90_TopOfDram_MASK                                  0xff800000
+
+/// D0F0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                                TopOfDram:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x90_STRUCT;
+
+// **** D0F0x94 Register Definition ****
+// Address
+#define D0F0x94_ADDRESS                                         0x94
+
+// Type
+#define D0F0x94_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x94_OrbIndAddr_OFFSET                               0
+#define D0F0x94_OrbIndAddr_WIDTH                                7
+#define D0F0x94_OrbIndAddr_MASK                                 0x7f
+#define D0F0x94_Reserved_7_7_OFFSET                             7
+#define D0F0x94_Reserved_7_7_WIDTH                              1
+#define D0F0x94_Reserved_7_7_MASK                               0x80
+#define D0F0x94_OrbIndWrEn_OFFSET                               8
+#define D0F0x94_OrbIndWrEn_WIDTH                                1
+#define D0F0x94_OrbIndWrEn_MASK                                 0x100
+#define D0F0x94_Reserved_31_9_OFFSET                            9
+#define D0F0x94_Reserved_31_9_WIDTH                             23
+#define D0F0x94_Reserved_31_9_MASK                              0xfffffe00
+
+/// D0F0x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndAddr:7 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                               OrbIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x94_STRUCT;
+
+// **** D0F0x98 Register Definition ****
+// Address
+#define D0F0x98_ADDRESS                                         0x98
+
+// Type
+#define D0F0x98_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x98_OrbIndData_OFFSET                               0
+#define D0F0x98_OrbIndData_WIDTH                                32
+#define D0F0x98_OrbIndData_MASK                                 0xffffffff
+
+/// D0F0x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_STRUCT;
+
+// **** D0F0xE0 Register Definition ****
+// Address
+#define D0F0xE0_ADDRESS                                         0xe0
+
+// Type
+#define D0F0xE0_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE0_PcieIndxAddr_OFFSET                             0
+#define D0F0xE0_PcieIndxAddr_WIDTH                              16
+#define D0F0xE0_PcieIndxAddr_MASK                               0xffff
+#define D0F0xE0_FrameType_OFFSET                                16
+#define D0F0xE0_FrameType_WIDTH                                 8
+#define D0F0xE0_FrameType_MASK                                  0xff0000
+#define D0F0xE0_BlockSelect_OFFSET                              24
+#define D0F0xE0_BlockSelect_WIDTH                               8
+#define D0F0xE0_BlockSelect_MASK                                0xff000000
+
+/// D0F0xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxAddr:16; ///<
+    UINT32                                                FrameType:8 ; ///<
+    UINT32                                              BlockSelect:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE0_STRUCT;
+
+// **** D0F0xE4 Register Definition ****
+// Address
+#define D0F0xE4_ADDRESS                                         0xe4
+
+// Type
+#define D0F0xE4_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE4_PcieIndxData_OFFSET                             0
+#define D0F0xE4_PcieIndxData_WIDTH                              32
+#define D0F0xE4_PcieIndxData_MASK                               0xffffffff
+
+/// D0F0xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_STRUCT;
+
+// **** D18F1xF0 Register Definition ****
+// Address
+#define D18F1xF0_ADDRESS                                        0xf0
+
+// Type
+#define D18F1xF0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xF0_DramHoleValid_OFFSET                           0
+#define D18F1xF0_DramHoleValid_WIDTH                            1
+#define D18F1xF0_DramHoleValid_MASK                             0x1
+#define D18F1xF0_Reserved_6_1_OFFSET                            1
+#define D18F1xF0_Reserved_6_1_WIDTH                             6
+#define D18F1xF0_Reserved_6_1_MASK                              0x7e
+#define D18F1xF0_DramHoleOffset_31_23__OFFSET                   7
+#define D18F1xF0_DramHoleOffset_31_23__WIDTH                    9
+#define D18F1xF0_DramHoleOffset_31_23__MASK                     0xff80
+#define D18F1xF0_Reserved_23_16_OFFSET                          16
+#define D18F1xF0_Reserved_23_16_WIDTH                           8
+#define D18F1xF0_Reserved_23_16_MASK                            0xff0000
+#define D18F1xF0_DramHoleBase_31_24__OFFSET                     24
+#define D18F1xF0_DramHoleBase_31_24__WIDTH                      8
+#define D18F1xF0_DramHoleBase_31_24__MASK                       0xff000000
+
+/// D18F1xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DramHoleValid:1 ; ///<
+    UINT32                                             Reserved_6_1:6 ; ///<
+    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
+    UINT32                                           Reserved_23_16:8 ; ///<
+    UINT32                                      DramHoleBase_31_24_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xF0_STRUCT;
+
+// **** D18F2x00 Register Definition ****
+// Address
+#define D18F2x00_ADDRESS                                        0x0
+
+// Type
+#define D18F2x00_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x00_VendorID_OFFSET                                0
+#define D18F2x00_VendorID_WIDTH                                 16
+#define D18F2x00_VendorID_MASK                                  0xffff
+#define D18F2x00_DeviceID_OFFSET                                16
+#define D18F2x00_DeviceID_WIDTH                                 16
+#define D18F2x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F2x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x00_STRUCT;
+
+
+// **** D18F2x08 Register Definition ****
+// Address
+#define D18F2x08_ADDRESS                                        0x8
+
+// Type
+#define D18F2x08_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x08_RevID_OFFSET                                   0
+#define D18F2x08_RevID_WIDTH                                    8
+#define D18F2x08_RevID_MASK                                     0xff
+#define D18F2x08_ClassCode_OFFSET                               8
+#define D18F2x08_ClassCode_WIDTH                                24
+#define D18F2x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F2x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x08_STRUCT;
+
+// **** D18F2x0C Register Definition ****
+// Address
+#define D18F2x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F2x0C_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x0C_HeaderTypeReg_OFFSET                           0
+#define D18F2x0C_HeaderTypeReg_WIDTH                            32
+#define D18F2x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F2x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x0C_STRUCT;
+
+
+// **** D18F2x040 Register Definition ****
+// Address
+#define D18F2x040_ADDRESS                                       0x40
+
+// Type
+#define D18F2x040_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x040_CSEnable_OFFSET                               0
+#define D18F2x040_CSEnable_WIDTH                                1
+#define D18F2x040_CSEnable_MASK                                 0x1
+#define D18F2x040_Reserved_1_1_OFFSET                           1
+#define D18F2x040_Reserved_1_1_WIDTH                            1
+#define D18F2x040_Reserved_1_1_MASK                             0x2
+#define D18F2x040_TestFail_OFFSET                               2
+#define D18F2x040_TestFail_WIDTH                                1
+#define D18F2x040_TestFail_MASK                                 0x4
+#define D18F2x040_OnDimmMirror_OFFSET                           3
+#define D18F2x040_OnDimmMirror_WIDTH                            1
+#define D18F2x040_OnDimmMirror_MASK                             0x8
+#define D18F2x040_Reserved_4_4_OFFSET                           4
+#define D18F2x040_Reserved_4_4_WIDTH                            1
+#define D18F2x040_Reserved_4_4_MASK                             0x10
+#define D18F2x040_Reserved_31_29_OFFSET                         29
+#define D18F2x040_Reserved_31_29_WIDTH                          3
+#define D18F2x040_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x040_STRUCT;
+
+// **** D18F2x044 Register Definition ****
+// Address
+#define D18F2x044_ADDRESS                                       0x44
+
+// Type
+#define D18F2x044_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x044_CSEnable_OFFSET                               0
+#define D18F2x044_CSEnable_WIDTH                                1
+#define D18F2x044_CSEnable_MASK                                 0x1
+#define D18F2x044_Reserved_1_1_OFFSET                           1
+#define D18F2x044_Reserved_1_1_WIDTH                            1
+#define D18F2x044_Reserved_1_1_MASK                             0x2
+#define D18F2x044_TestFail_OFFSET                               2
+#define D18F2x044_TestFail_WIDTH                                1
+#define D18F2x044_TestFail_MASK                                 0x4
+#define D18F2x044_OnDimmMirror_OFFSET                           3
+#define D18F2x044_OnDimmMirror_WIDTH                            1
+#define D18F2x044_OnDimmMirror_MASK                             0x8
+#define D18F2x044_Reserved_4_4_OFFSET                           4
+#define D18F2x044_Reserved_4_4_WIDTH                            1
+#define D18F2x044_Reserved_4_4_MASK                             0x10
+#define D18F2x044_Reserved_31_29_OFFSET                         29
+#define D18F2x044_Reserved_31_29_WIDTH                          3
+#define D18F2x044_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x044
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x044_STRUCT;
+
+// **** D18F2x048 Register Definition ****
+// Address
+#define D18F2x048_ADDRESS                                       0x48
+
+// Type
+#define D18F2x048_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x048_CSEnable_OFFSET                               0
+#define D18F2x048_CSEnable_WIDTH                                1
+#define D18F2x048_CSEnable_MASK                                 0x1
+#define D18F2x048_Reserved_1_1_OFFSET                           1
+#define D18F2x048_Reserved_1_1_WIDTH                            1
+#define D18F2x048_Reserved_1_1_MASK                             0x2
+#define D18F2x048_TestFail_OFFSET                               2
+#define D18F2x048_TestFail_WIDTH                                1
+#define D18F2x048_TestFail_MASK                                 0x4
+#define D18F2x048_OnDimmMirror_OFFSET                           3
+#define D18F2x048_OnDimmMirror_WIDTH                            1
+#define D18F2x048_OnDimmMirror_MASK                             0x8
+#define D18F2x048_Reserved_4_4_OFFSET                           4
+#define D18F2x048_Reserved_4_4_WIDTH                            1
+#define D18F2x048_Reserved_4_4_MASK                             0x10
+#define D18F2x048_Reserved_31_29_OFFSET                         29
+#define D18F2x048_Reserved_31_29_WIDTH                          3
+#define D18F2x048_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x048
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x048_STRUCT;
+
+// **** D18F2x04C Register Definition ****
+// Address
+#define D18F2x04C_ADDRESS                                       0x4c
+
+// Type
+#define D18F2x04C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x04C_CSEnable_OFFSET                               0
+#define D18F2x04C_CSEnable_WIDTH                                1
+#define D18F2x04C_CSEnable_MASK                                 0x1
+#define D18F2x04C_Reserved_1_1_OFFSET                           1
+#define D18F2x04C_Reserved_1_1_WIDTH                            1
+#define D18F2x04C_Reserved_1_1_MASK                             0x2
+#define D18F2x04C_TestFail_OFFSET                               2
+#define D18F2x04C_TestFail_WIDTH                                1
+#define D18F2x04C_TestFail_MASK                                 0x4
+#define D18F2x04C_OnDimmMirror_OFFSET                           3
+#define D18F2x04C_OnDimmMirror_WIDTH                            1
+#define D18F2x04C_OnDimmMirror_MASK                             0x8
+#define D18F2x04C_Reserved_4_4_OFFSET                           4
+#define D18F2x04C_Reserved_4_4_WIDTH                            1
+#define D18F2x04C_Reserved_4_4_MASK                             0x10
+#define D18F2x04C_Reserved_31_29_OFFSET                         29
+#define D18F2x04C_Reserved_31_29_WIDTH                          3
+#define D18F2x04C_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x04C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x04C_STRUCT;
+
+// **** D18F2x060 Register Definition ****
+// Address
+#define D18F2x060_ADDRESS                                       0x60
+
+// Type
+#define D18F2x060_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x060_Reserved_4_0_OFFSET                           0
+#define D18F2x060_Reserved_4_0_WIDTH                            5
+#define D18F2x060_Reserved_4_0_MASK                             0x1f
+#define D18F2x060_Reserved_31_29_OFFSET                         29
+#define D18F2x060_Reserved_31_29_WIDTH                          3
+#define D18F2x060_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x060_STRUCT;
+
+// **** D18F2x064 Register Definition ****
+// Address
+#define D18F2x064_ADDRESS                                       0x64
+
+// Type
+#define D18F2x064_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x064_Reserved_4_0_OFFSET                           0
+#define D18F2x064_Reserved_4_0_WIDTH                            5
+#define D18F2x064_Reserved_4_0_MASK                             0x1f
+#define D18F2x064_Reserved_31_29_OFFSET                         29
+#define D18F2x064_Reserved_31_29_WIDTH                          3
+#define D18F2x064_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x064
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x064_STRUCT;
+
+// **** D18F2x078 Register Definition ****
+// Address
+#define D18F2x078_ADDRESS                                       0x78
+
+// Type
+#define D18F2x078_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x078_Reserved_14_14_OFFSET                         14
+#define D18F2x078_Reserved_14_14_WIDTH                          1
+#define D18F2x078_Reserved_14_14_MASK                           0x4000
+#define D18F2x078_Reserved_15_15_OFFSET                         15
+#define D18F2x078_Reserved_15_15_WIDTH                          1
+#define D18F2x078_Reserved_15_15_MASK                           0x8000
+#define D18F2x078_Reserved_16_16_OFFSET                         16
+#define D18F2x078_Reserved_16_16_WIDTH                          1
+#define D18F2x078_Reserved_16_16_MASK                           0x10000
+#define D18F2x078_AddrCmdTriEn_OFFSET                           17
+#define D18F2x078_AddrCmdTriEn_WIDTH                            1
+#define D18F2x078_AddrCmdTriEn_MASK                             0x20000
+#define D18F2x078_Reserved_18_18_OFFSET                         18
+#define D18F2x078_Reserved_18_18_WIDTH                          1
+#define D18F2x078_Reserved_18_18_MASK                           0x40000
+#define D18F2x078_Reserved_19_19_OFFSET                         19
+#define D18F2x078_Reserved_19_19_WIDTH                          1
+#define D18F2x078_Reserved_19_19_MASK                           0x80000
+
+/// D18F2x078
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                :4 ; ///<
+    UINT32                                             :2 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                           Reserved_16_16:1 ; ///<
+    UINT32                                             AddrCmdTriEn:1 ; ///<
+    UINT32                                           Reserved_18_18:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                        :1 ; ///<
+    UINT32                                             :10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x078_STRUCT;
+
+
+
+// **** D18F2x084 Register Definition ****
+// Address
+#define D18F2x084_ADDRESS                                       0x84
+
+// Type
+#define D18F2x084_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x084_BurstCtrl_OFFSET                              0
+#define D18F2x084_BurstCtrl_WIDTH                               2
+#define D18F2x084_BurstCtrl_MASK                                0x3
+#define D18F2x084_Reserved_3_2_OFFSET                           2
+#define D18F2x084_Reserved_3_2_WIDTH                            2
+#define D18F2x084_Reserved_3_2_MASK                             0xc
+#define D18F2x084_Reserved_19_7_OFFSET                          7
+#define D18F2x084_Reserved_19_7_WIDTH                           13
+#define D18F2x084_Reserved_19_7_MASK                            0xfff80
+#define D18F2x084_PchgPDModeSel_OFFSET                          23
+#define D18F2x084_PchgPDModeSel_WIDTH                           1
+#define D18F2x084_PchgPDModeSel_MASK                            0x800000
+#define D18F2x084_Reserved_31_24_OFFSET                         24
+#define D18F2x084_Reserved_31_24_WIDTH                          8
+#define D18F2x084_Reserved_31_24_MASK                           0xff000000
+
+/// D18F2x084
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                BurstCtrl:2 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                      :3 ; ///<
+    UINT32                                            Reserved_19_7:13; ///<
+    UINT32                                                     :3 ; ///<
+    UINT32                                            PchgPDModeSel:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x084_STRUCT;
+
+// **** D18F2x088 Register Definition ****
+// Address
+#define D18F2x088_ADDRESS                                       0x88
+
+// Type
+#define D18F2x088_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x088_Reserved_23_4_OFFSET                          4
+#define D18F2x088_Reserved_23_4_WIDTH                           20
+#define D18F2x088_Reserved_23_4_MASK                            0xfffff0
+
+/// D18F2x088
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      :4 ; ///<
+    UINT32                                            Reserved_23_4:20; ///<
+    UINT32                                                :8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x088_STRUCT;
+
+
+
+
+// **** D18F2x098 Register Definition ****
+// Address
+#define D18F2x098_ADDRESS                                       0x98
+
+// Type
+#define D18F2x098_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x098_DctOffset_OFFSET                              0
+#define D18F2x098_DctOffset_WIDTH                               30
+#define D18F2x098_DctOffset_MASK                                0x3fffffff
+#define D18F2x098_DctAccessWrite_OFFSET                         30
+#define D18F2x098_DctAccessWrite_WIDTH                          1
+#define D18F2x098_DctAccessWrite_MASK                           0x40000000
+#define D18F2x098_Reserved_31_31_OFFSET                         31
+#define D18F2x098_Reserved_31_31_WIDTH                          1
+#define D18F2x098_Reserved_31_31_MASK                           0x80000000
+
+/// D18F2x098
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctOffset:30; ///<
+    UINT32                                           DctAccessWrite:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x098_STRUCT;
+
+// **** D18F2x09C Register Definition ****
+// Address
+#define D18F2x09C_ADDRESS                                       0x9c
+
+// Type
+#define D18F2x09C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x09C_DctDataPort_OFFSET                            0
+#define D18F2x09C_DctDataPort_WIDTH                             32
+#define D18F2x09C_DctDataPort_MASK                              0xffffffff
+
+/// D18F2x09C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DctDataPort:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_STRUCT;
+
+
+// **** D18F2xA4 Register Definition ****
+// Address
+#define D18F2xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F2xA4_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xA4_DoubleTrefRateEn_OFFSET                        0
+#define D18F2xA4_DoubleTrefRateEn_WIDTH                         1
+
+
+// **** D18F2xAC Register Definition ****
+// Address
+#define D18F2xAC_ADDRESS                                        0xac
+
+// Type
+#define D18F2xAC_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xAC_Reserved_31_1_OFFSET                           1
+#define D18F2xAC_Reserved_31_1_WIDTH                            31
+#define D18F2xAC_Reserved_31_1_MASK                             0xfffffffe
+
+/// D18F2xAC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               MemTempHot:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xAC_STRUCT;
+
+
+
+// **** D18F2x114 Register Definition ****
+// Address
+#define D18F2x114_ADDRESS                                       0x114
+
+// Type
+#define D18F2x114_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x114_Reserved_8_0_OFFSET                           0
+#define D18F2x114_Reserved_8_0_WIDTH                            9
+#define D18F2x114_Reserved_8_0_MASK                             0x1ff
+#define D18F2x114_DctSelIntLvAddr_2__OFFSET                     9
+#define D18F2x114_DctSelIntLvAddr_2__WIDTH                      1
+#define D18F2x114_DctSelIntLvAddr_2__MASK                       0x200
+
+/// D18F2x114
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
+    UINT32                                  :14; ///<
+    UINT32                                           :8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x114_STRUCT;
+
+
+// **** D18F3x00 Register Definition ****
+// Address
+#define D18F3x00_ADDRESS                                        0x0
+
+// Type
+#define D18F3x00_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x00_VendorID_OFFSET                                0
+#define D18F3x00_VendorID_WIDTH                                 16
+#define D18F3x00_VendorID_MASK                                  0xffff
+#define D18F3x00_DeviceID_OFFSET                                16
+#define D18F3x00_DeviceID_WIDTH                                 16
+#define D18F3x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F3x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x00_STRUCT;
+
+// **** D18F3x04 Register Definition ****
+// Address
+#define D18F3x04_ADDRESS                                        0x4
+
+// Type
+#define D18F3x04_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x04_Command_OFFSET                                 0
+#define D18F3x04_Command_WIDTH                                  16
+#define D18F3x04_Command_MASK                                   0xffff
+#define D18F3x04_Status_OFFSET                                  16
+#define D18F3x04_Status_WIDTH                                   16
+#define D18F3x04_Status_MASK                                    0xffff0000
+
+/// D18F3x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x04_STRUCT;
+
+// **** D18F3x08 Register Definition ****
+// Address
+#define D18F3x08_ADDRESS                                        0x8
+
+// Type
+#define D18F3x08_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x08_RevID_OFFSET                                   0
+#define D18F3x08_RevID_WIDTH                                    8
+#define D18F3x08_RevID_MASK                                     0xff
+#define D18F3x08_ClassCode_OFFSET                               8
+#define D18F3x08_ClassCode_WIDTH                                24
+#define D18F3x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F3x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x08_STRUCT;
+
+// **** D18F3x0C Register Definition ****
+// Address
+#define D18F3x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F3x0C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x0C_HeaderTypeReg_OFFSET                           0
+#define D18F3x0C_HeaderTypeReg_WIDTH                            32
+#define D18F3x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F3x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x0C_STRUCT;
+
+// **** D18F3x34 Register Definition ****
+// Address
+#define D18F3x34_ADDRESS                                        0x34
+
+// Type
+#define D18F3x34_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x34_CapPtr_OFFSET                                  0
+#define D18F3x34_CapPtr_WIDTH                                   8
+#define D18F3x34_CapPtr_MASK                                    0xff
+#define D18F3x34_Reserved_31_8_OFFSET                           8
+#define D18F3x34_Reserved_31_8_WIDTH                            24
+#define D18F3x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F3x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x34_STRUCT;
+
+
+// **** D18F3x48 Register Definition ****
+// Address
+#define D18F3x48_ADDRESS                                        0x48
+
+// Type
+#define D18F3x48_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x48_ErrorCode_OFFSET                               0
+#define D18F3x48_ErrorCode_WIDTH                                16
+#define D18F3x48_ErrorCode_MASK                                 0xffff
+#define D18F3x48_ErrorCodeExt_OFFSET                            16
+#define D18F3x48_ErrorCodeExt_WIDTH                             5
+#define D18F3x48_ErrorCodeExt_MASK                              0x1f0000
+#define D18F3x48_Reserved_31_21_OFFSET                          21
+#define D18F3x48_Reserved_31_21_WIDTH                           11
+#define D18F3x48_Reserved_31_21_MASK                            0xffe00000
+
+/// D18F3x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrorCode:16; ///<
+    UINT32                                             ErrorCodeExt:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x48_STRUCT;
+
+
+// **** D18F3x64 Register Definition ****
+// Address
+#define D18F3x64_ADDRESS                                        0x64
+
+// Type
+#define D18F3x64_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x64_HtcEn_OFFSET                                   0
+#define D18F3x64_HtcEn_WIDTH                                    1
+#define D18F3x64_HtcEn_MASK                                     0x1
+#define D18F3x64_Reserved_3_1_OFFSET                            1
+#define D18F3x64_Reserved_3_1_WIDTH                             3
+#define D18F3x64_Reserved_3_1_MASK                              0xe
+#define D18F3x64_HtcAct_OFFSET                                  4
+#define D18F3x64_HtcAct_WIDTH                                   1
+#define D18F3x64_HtcAct_MASK                                    0x10
+#define D18F3x64_HtcActSts_OFFSET                               5
+#define D18F3x64_HtcActSts_WIDTH                                1
+#define D18F3x64_HtcActSts_MASK                                 0x20
+#define D18F3x64_PslApicHiEn_OFFSET                             6
+#define D18F3x64_PslApicHiEn_WIDTH                              1
+#define D18F3x64_PslApicHiEn_MASK                               0x40
+#define D18F3x64_PslApicLoEn_OFFSET                             7
+#define D18F3x64_PslApicLoEn_WIDTH                              1
+#define D18F3x64_PslApicLoEn_MASK                               0x80
+#define D18F3x64_Reserved_15_8_OFFSET                           8
+#define D18F3x64_Reserved_15_8_WIDTH                            8
+#define D18F3x64_Reserved_15_8_MASK                             0xff00
+#define D18F3x64_HtcTmpLmt_OFFSET                               16
+#define D18F3x64_HtcTmpLmt_WIDTH                                7
+#define D18F3x64_HtcTmpLmt_MASK                                 0x7f0000
+#define D18F3x64_HtcSlewSel_OFFSET                              23
+#define D18F3x64_HtcSlewSel_WIDTH                               1
+#define D18F3x64_HtcSlewSel_MASK                                0x800000
+#define D18F3x64_HtcHystLmt_OFFSET                              24
+#define D18F3x64_HtcHystLmt_WIDTH                               4
+#define D18F3x64_HtcHystLmt_MASK                                0xf000000
+#define D18F3x64_HtcPstateLimit_OFFSET                          28
+#define D18F3x64_HtcPstateLimit_WIDTH                           3
+#define D18F3x64_HtcPstateLimit_MASK                            0x70000000
+
+/// D18F3x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    HtcEn:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                                   HtcAct:1 ; ///<
+    UINT32                                                HtcActSts:1 ; ///<
+    UINT32                                              PslApicHiEn:1 ; ///<
+    UINT32                                              PslApicLoEn:1 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                                HtcTmpLmt:7 ; ///<
+    UINT32                                               HtcSlewSel:1 ; ///<
+    UINT32                                               HtcHystLmt:4 ; ///<
+    UINT32                                           HtcPstateLimit:3 ; ///<
+    UINT32                                                  :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x64_STRUCT;
+
+
+// **** D18F3x88 Register Definition ****
+// Address
+#define D18F3x88_ADDRESS                                        0x88
+
+// Type
+#define D18F3x88_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x88_Reserved_31_0_OFFSET                           0
+#define D18F3x88_Reserved_31_0_WIDTH                            32
+#define D18F3x88_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x88_STRUCT;
+
+
+// **** D18F3xE4 Register Definition ****
+// Address
+#define D18F3xE4_ADDRESS                                        0xe4
+
+// Type
+#define D18F3xE4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xE4_Reserved_0_0_OFFSET                            0
+#define D18F3xE4_Reserved_0_0_WIDTH                             1
+#define D18F3xE4_Reserved_0_0_MASK                              0x1
+#define D18F3xE4_Thermtp_OFFSET                                 1
+#define D18F3xE4_Thermtp_WIDTH                                  1
+#define D18F3xE4_Thermtp_MASK                                   0x2
+#define D18F3xE4_Reserved_2_2_OFFSET                            2
+#define D18F3xE4_Reserved_2_2_WIDTH                             1
+#define D18F3xE4_Reserved_2_2_MASK                              0x4
+#define D18F3xE4_ThermtpSense_OFFSET                            3
+#define D18F3xE4_ThermtpSense_WIDTH                             1
+#define D18F3xE4_ThermtpSense_MASK                              0x8
+#define D18F3xE4_Reserved_4_4_OFFSET                            4
+#define D18F3xE4_Reserved_4_4_WIDTH                             1
+#define D18F3xE4_Reserved_4_4_MASK                              0x10
+#define D18F3xE4_ThermtpEn_OFFSET                               5
+#define D18F3xE4_ThermtpEn_WIDTH                                1
+#define D18F3xE4_ThermtpEn_MASK                                 0x20
+#define D18F3xE4_Reserved_7_6_OFFSET                            6
+#define D18F3xE4_Reserved_7_6_WIDTH                             2
+#define D18F3xE4_Reserved_7_6_MASK                              0xc0
+#define D18F3xE4_Reserved_30_8_OFFSET                           8
+#define D18F3xE4_Reserved_30_8_WIDTH                            23
+#define D18F3xE4_Reserved_30_8_MASK                             0x7fffff00
+#define D18F3xE4_SwThermtp_OFFSET                               31
+#define D18F3xE4_SwThermtp_WIDTH                                1
+#define D18F3xE4_SwThermtp_MASK                                 0x80000000
+
+/// D18F3xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  Thermtp:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             ThermtpSense:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                                ThermtpEn:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                            Reserved_30_8:23; ///<
+    UINT32                                                SwThermtp:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xE4_STRUCT;
+
+
+// **** D18F3xF0 Register Definition ****
+// Address
+#define D18F3xF0_ADDRESS                                        0xf0
+
+// Type
+#define D18F3xF0_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xF0_Reserved_31_0_OFFSET                           0
+#define D18F3xF0_Reserved_31_0_WIDTH                            32
+#define D18F3xF0_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xF0_STRUCT;
+
+// **** D18F3xF4 Register Definition ****
+// Address
+#define D18F3xF4_ADDRESS                                        0xf4
+
+// Type
+#define D18F3xF4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xF4_Reserved_31_0_OFFSET                           0
+#define D18F3xF4_Reserved_31_0_WIDTH                            32
+#define D18F3xF4_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3xF4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xF4_STRUCT;
+
+// **** D18F3xF8 Register Definition ****
+// Address
+#define D18F3xF8_ADDRESS                                        0xf8
+
+// Type
+#define D18F3xF8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xF8_Reserved_31_0_OFFSET                           0
+#define D18F3xF8_Reserved_31_0_WIDTH                            32
+#define D18F3xF8_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3xF8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xF8_STRUCT;
+
+// **** D18F3xFC Register Definition ****
+// Address
+#define D18F3xFC_ADDRESS                                        0xfc
+
+// Type
+#define D18F3xFC_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xFC_Stepping_OFFSET                                0
+#define D18F3xFC_Stepping_WIDTH                                 4
+#define D18F3xFC_Stepping_MASK                                  0xf
+#define D18F3xFC_BaseModel_OFFSET                               4
+#define D18F3xFC_BaseModel_WIDTH                                4
+#define D18F3xFC_BaseModel_MASK                                 0xf0
+#define D18F3xFC_BaseFamily_OFFSET                              8
+#define D18F3xFC_BaseFamily_WIDTH                               4
+#define D18F3xFC_BaseFamily_MASK                                0xf00
+#define D18F3xFC_Reserved_15_12_OFFSET                          12
+#define D18F3xFC_Reserved_15_12_WIDTH                           4
+#define D18F3xFC_Reserved_15_12_MASK                            0xf000
+#define D18F3xFC_ExtModel_OFFSET                                16
+#define D18F3xFC_ExtModel_WIDTH                                 4
+#define D18F3xFC_ExtModel_MASK                                  0xf0000
+#define D18F3xFC_ExtFamily_OFFSET                               20
+#define D18F3xFC_ExtFamily_WIDTH                                8
+#define D18F3xFC_ExtFamily_MASK                                 0xff00000
+#define D18F3xFC_Reserved_31_28_OFFSET                          28
+#define D18F3xFC_Reserved_31_28_WIDTH                           4
+#define D18F3xFC_Reserved_31_28_MASK                            0xf0000000
+
+/// D18F3xFC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Stepping:4 ; ///<
+    UINT32                                                BaseModel:4 ; ///<
+    UINT32                                               BaseFamily:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                 ExtModel:4 ; ///<
+    UINT32                                                ExtFamily:8 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xFC_STRUCT;
+
+
+
+
+
+
+
+// **** D18F3x1CC Register Definition ****
+// Address
+#define D18F3x1CC_ADDRESS                                       0x1cc
+
+// Type
+#define D18F3x1CC_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1CC_LvtOffset_OFFSET                              0
+#define D18F3x1CC_LvtOffset_WIDTH                               4
+#define D18F3x1CC_LvtOffset_MASK                                0xf
+#define D18F3x1CC_Reserved_7_4_OFFSET                           4
+#define D18F3x1CC_Reserved_7_4_WIDTH                            4
+#define D18F3x1CC_Reserved_7_4_MASK                             0xf0
+#define D18F3x1CC_LvtOffsetVal_OFFSET                           8
+#define D18F3x1CC_LvtOffsetVal_WIDTH                            1
+#define D18F3x1CC_LvtOffsetVal_MASK                             0x100
+#define D18F3x1CC_Reserved_31_9_OFFSET                          9
+#define D18F3x1CC_Reserved_31_9_WIDTH                           23
+#define D18F3x1CC_Reserved_31_9_MASK                            0xfffffe00
+
+/// D18F3x1CC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LvtOffset:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             LvtOffsetVal:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1CC_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+// **** DxF0x00 Register Definition ****
+// Address
+#define DxF0x00_ADDRESS                                         0x0
+
+// Type
+#define DxF0x00_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x00_VendorID_OFFSET                                 0
+#define DxF0x00_VendorID_WIDTH                                  16
+#define DxF0x00_VendorID_MASK                                   0xffff
+#define DxF0x00_DeviceID_OFFSET                                 16
+#define DxF0x00_DeviceID_WIDTH                                  16
+#define DxF0x00_DeviceID_MASK                                   0xffff0000
+
+/// DxF0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x00_STRUCT;
+
+
+// **** DxF0x08 Register Definition ****
+// Address
+#define DxF0x08_ADDRESS                                         0x8
+
+// Type
+#define DxF0x08_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x08_RevID_OFFSET                                    0
+#define DxF0x08_RevID_WIDTH                                     8
+#define DxF0x08_RevID_MASK                                      0xff
+#define DxF0x08_ClassCode_OFFSET                                8
+#define DxF0x08_ClassCode_WIDTH                                 24
+#define DxF0x08_ClassCode_MASK                                  0xffffff00
+
+/// DxF0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x08_STRUCT;
+
+// **** DxF0x0C Register Definition ****
+// Address
+#define DxF0x0C_ADDRESS                                         0xc
+
+// Type
+#define DxF0x0C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x0C_CacheLineSize_OFFSET                            0
+#define DxF0x0C_CacheLineSize_WIDTH                             8
+#define DxF0x0C_CacheLineSize_MASK                              0xff
+#define DxF0x0C_LatencyTimer_OFFSET                             8
+#define DxF0x0C_LatencyTimer_WIDTH                              8
+#define DxF0x0C_LatencyTimer_MASK                               0xff00
+#define DxF0x0C_HeaderTypeReg_OFFSET                            16
+#define DxF0x0C_HeaderTypeReg_WIDTH                             8
+#define DxF0x0C_HeaderTypeReg_MASK                              0xff0000
+#define DxF0x0C_BIST_OFFSET                                     24
+#define DxF0x0C_BIST_WIDTH                                      8
+#define DxF0x0C_BIST_MASK                                       0xff000000
+
+/// DxF0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x0C_STRUCT;
+
+// **** DxF0x18 Register Definition ****
+// Address
+#define DxF0x18_ADDRESS                                         0x18
+
+// Type
+#define DxF0x18_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x18_PrimaryBus_OFFSET                               0
+#define DxF0x18_PrimaryBus_WIDTH                                8
+#define DxF0x18_PrimaryBus_MASK                                 0xff
+#define DxF0x18_SecondaryBus_OFFSET                             8
+#define DxF0x18_SecondaryBus_WIDTH                              8
+#define DxF0x18_SecondaryBus_MASK                               0xff00
+#define DxF0x18_SubBusNumber_OFFSET                             16
+#define DxF0x18_SubBusNumber_WIDTH                              8
+#define DxF0x18_SubBusNumber_MASK                               0xff0000
+#define DxF0x18_SecondaryLatencyTimer_OFFSET                    24
+#define DxF0x18_SecondaryLatencyTimer_WIDTH                     8
+#define DxF0x18_SecondaryLatencyTimer_MASK                      0xff000000
+
+/// DxF0x18
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PrimaryBus:8 ; ///<
+    UINT32                                             SecondaryBus:8 ; ///<
+    UINT32                                             SubBusNumber:8 ; ///<
+    UINT32                                    SecondaryLatencyTimer:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x18_STRUCT;
+
+
+// **** DxF0x20 Register Definition ****
+// Address
+#define DxF0x20_ADDRESS                                         0x20
+
+// Type
+#define DxF0x20_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x20_Reserved_3_0_OFFSET                             0
+#define DxF0x20_Reserved_3_0_WIDTH                              4
+#define DxF0x20_Reserved_3_0_MASK                               0xf
+#define DxF0x20_MemBase_OFFSET                                  4
+#define DxF0x20_MemBase_WIDTH                                   12
+#define DxF0x20_MemBase_MASK                                    0xfff0
+#define DxF0x20_Reserved_19_16_OFFSET                           16
+#define DxF0x20_Reserved_19_16_WIDTH                            4
+#define DxF0x20_Reserved_19_16_MASK                             0xf0000
+#define DxF0x20_MemLimit_OFFSET                                 20
+#define DxF0x20_MemLimit_WIDTH                                  12
+#define DxF0x20_MemLimit_MASK                                   0xfff00000
+
+/// DxF0x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                  MemBase:12; ///<
+    UINT32                                           Reserved_19_16:4 ; ///<
+    UINT32                                                 MemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x20_STRUCT;
+
+// **** DxF0x24 Register Definition ****
+// Address
+#define DxF0x24_ADDRESS                                         0x24
+
+// Type
+#define DxF0x24_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x24_PrefMemBaseR_OFFSET                             0
+#define DxF0x24_PrefMemBaseR_WIDTH                              4
+#define DxF0x24_PrefMemBaseR_MASK                               0xf
+#define DxF0x24_PrefMemBase_31_20__OFFSET                       4
+#define DxF0x24_PrefMemBase_31_20__WIDTH                        12
+#define DxF0x24_PrefMemBase_31_20__MASK                         0xfff0
+#define DxF0x24_PrefMemLimitR_OFFSET                            16
+#define DxF0x24_PrefMemLimitR_WIDTH                             4
+#define DxF0x24_PrefMemLimitR_MASK                              0xf0000
+#define DxF0x24_PrefMemLimit_OFFSET                             20
+#define DxF0x24_PrefMemLimit_WIDTH                              12
+#define DxF0x24_PrefMemLimit_MASK                               0xfff00000
+
+/// DxF0x24
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PrefMemBaseR:4 ; ///<
+    UINT32                                       PrefMemBase_31_20_:12; ///<
+    UINT32                                            PrefMemLimitR:4 ; ///<
+    UINT32                                             PrefMemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x24_STRUCT;
+
+// **** DxF0x28 Register Definition ****
+// Address
+#define DxF0x28_ADDRESS                                         0x28
+
+// Type
+#define DxF0x28_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x28_PrefMemBase_63_32__OFFSET                       0
+#define DxF0x28_PrefMemBase_63_32__WIDTH                        32
+#define DxF0x28_PrefMemBase_63_32__MASK                         0xffffffff
+
+/// DxF0x28
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PrefMemBase_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x28_STRUCT;
+
+// **** DxF0x2C Register Definition ****
+// Address
+#define DxF0x2C_ADDRESS                                         0x2c
+
+// Type
+#define DxF0x2C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x2C_PrefMemLimit_63_32__OFFSET                      0
+#define DxF0x2C_PrefMemLimit_63_32__WIDTH                       32
+#define DxF0x2C_PrefMemLimit_63_32__MASK                        0xffffffff
+
+/// DxF0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      PrefMemLimit_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x2C_STRUCT;
+
+// **** DxF0x30 Register Definition ****
+// Address
+#define DxF0x30_ADDRESS                                         0x30
+
+// Type
+#define DxF0x30_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x30_IOBase_31_16__OFFSET                            0
+#define DxF0x30_IOBase_31_16__WIDTH                             16
+#define DxF0x30_IOBase_31_16__MASK                              0xffff
+#define DxF0x30_IOLimit_31_16__OFFSET                           16
+#define DxF0x30_IOLimit_31_16__WIDTH                            16
+#define DxF0x30_IOLimit_31_16__MASK                             0xffff0000
+
+/// DxF0x30
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            IOBase_31_16_:16; ///<
+    UINT32                                           IOLimit_31_16_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x30_STRUCT;
+
+// **** DxF0x34 Register Definition ****
+// Address
+#define DxF0x34_ADDRESS                                         0x34
+
+// Type
+#define DxF0x34_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x34_CapPtr_OFFSET                                   0
+#define DxF0x34_CapPtr_WIDTH                                    8
+#define DxF0x34_CapPtr_MASK                                     0xff
+#define DxF0x34_Reserved_31_8_OFFSET                            8
+#define DxF0x34_Reserved_31_8_WIDTH                             24
+#define DxF0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// DxF0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x34_STRUCT;
+
+// **** DxF0x3C Register Definition ****
+// Address
+#define DxF0x3C_ADDRESS                                         0x3c
+
+// Type
+#define DxF0x3C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x3C_IntLine_OFFSET                                  0
+#define DxF0x3C_IntLine_WIDTH                                   8
+#define DxF0x3C_IntLine_MASK                                    0xff
+#define DxF0x3C_IntPin_OFFSET                                   8
+#define DxF0x3C_IntPin_WIDTH                                    3
+#define DxF0x3C_IntPin_MASK                                     0x700
+#define DxF0x3C_IntPinR_OFFSET                                  11
+#define DxF0x3C_IntPinR_WIDTH                                   5
+#define DxF0x3C_IntPinR_MASK                                    0xf800
+#define DxF0x3C_ParityResponseEn_OFFSET                         16
+#define DxF0x3C_ParityResponseEn_WIDTH                          1
+#define DxF0x3C_ParityResponseEn_MASK                           0x10000
+#define DxF0x3C_SerrEn_OFFSET                                   17
+#define DxF0x3C_SerrEn_WIDTH                                    1
+#define DxF0x3C_SerrEn_MASK                                     0x20000
+#define DxF0x3C_IsaEn_OFFSET                                    18
+#define DxF0x3C_IsaEn_WIDTH                                     1
+#define DxF0x3C_IsaEn_MASK                                      0x40000
+#define DxF0x3C_VgaEn_OFFSET                                    19
+#define DxF0x3C_VgaEn_WIDTH                                     1
+#define DxF0x3C_VgaEn_MASK                                      0x80000
+#define DxF0x3C_Vga16En_OFFSET                                  20
+#define DxF0x3C_Vga16En_WIDTH                                   1
+#define DxF0x3C_Vga16En_MASK                                    0x100000
+#define DxF0x3C_MasterAbortMode_OFFSET                          21
+#define DxF0x3C_MasterAbortMode_WIDTH                           1
+#define DxF0x3C_MasterAbortMode_MASK                            0x200000
+#define DxF0x3C_SecondaryBusReset_OFFSET                        22
+#define DxF0x3C_SecondaryBusReset_WIDTH                         1
+#define DxF0x3C_SecondaryBusReset_MASK                          0x400000
+#define DxF0x3C_FastB2BCap_OFFSET                               23
+#define DxF0x3C_FastB2BCap_WIDTH                                1
+#define DxF0x3C_FastB2BCap_MASK                                 0x800000
+#define DxF0x3C_Reserved_31_24_OFFSET                           24
+#define DxF0x3C_Reserved_31_24_WIDTH                            8
+#define DxF0x3C_Reserved_31_24_MASK                             0xff000000
+
+/// DxF0x3C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  IntLine:8 ; ///<
+    UINT32                                                   IntPin:3 ; ///<
+    UINT32                                                  IntPinR:5 ; ///<
+    UINT32                                         ParityResponseEn:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                    IsaEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                          MasterAbortMode:1 ; ///<
+    UINT32                                        SecondaryBusReset:1 ; ///<
+    UINT32                                               FastB2BCap:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x3C_STRUCT;
+
+// **** DxF0x50 Register Definition ****
+// Address
+#define DxF0x50_ADDRESS                                         0x50
+
+// Type
+#define DxF0x50_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x50_CapID_OFFSET                                    0
+#define DxF0x50_CapID_WIDTH                                     8
+#define DxF0x50_CapID_MASK                                      0xff
+#define DxF0x50_NextPtr_OFFSET                                  8
+#define DxF0x50_NextPtr_WIDTH                                   8
+#define DxF0x50_NextPtr_MASK                                    0xff00
+#define DxF0x50_Version_OFFSET                                  16
+#define DxF0x50_Version_WIDTH                                   3
+#define DxF0x50_Version_MASK                                    0x70000
+#define DxF0x50_PmeClock_OFFSET                                 19
+#define DxF0x50_PmeClock_WIDTH                                  1
+#define DxF0x50_PmeClock_MASK                                   0x80000
+#define DxF0x50_Reserved_20_20_OFFSET                           20
+#define DxF0x50_Reserved_20_20_WIDTH                            1
+#define DxF0x50_Reserved_20_20_MASK                             0x100000
+#define DxF0x50_DevSpecificInit_OFFSET                          21
+#define DxF0x50_DevSpecificInit_WIDTH                           1
+#define DxF0x50_DevSpecificInit_MASK                            0x200000
+#define DxF0x50_AuxCurrent_OFFSET                               22
+#define DxF0x50_AuxCurrent_WIDTH                                3
+#define DxF0x50_AuxCurrent_MASK                                 0x1c00000
+#define DxF0x50_D1Support_OFFSET                                25
+#define DxF0x50_D1Support_WIDTH                                 1
+#define DxF0x50_D1Support_MASK                                  0x2000000
+#define DxF0x50_D2Support_OFFSET                                26
+#define DxF0x50_D2Support_WIDTH                                 1
+#define DxF0x50_D2Support_MASK                                  0x4000000
+#define DxF0x50_PmeSupport_OFFSET                               27
+#define DxF0x50_PmeSupport_WIDTH                                5
+#define DxF0x50_PmeSupport_MASK                                 0xf8000000
+
+/// DxF0x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:3 ; ///<
+    UINT32                                                 PmeClock:1 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                          DevSpecificInit:1 ; ///<
+    UINT32                                               AuxCurrent:3 ; ///<
+    UINT32                                                D1Support:1 ; ///<
+    UINT32                                                D2Support:1 ; ///<
+    UINT32                                               PmeSupport:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x50_STRUCT;
+
+// **** DxF0x54 Register Definition ****
+// Address
+#define DxF0x54_ADDRESS                                         0x54
+
+// Type
+#define DxF0x54_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x54_PowerState_OFFSET                               0
+#define DxF0x54_PowerState_WIDTH                                2
+#define DxF0x54_PowerState_MASK                                 0x3
+#define DxF0x54_Reserved_2_2_OFFSET                             2
+#define DxF0x54_Reserved_2_2_WIDTH                              1
+#define DxF0x54_Reserved_2_2_MASK                               0x4
+#define DxF0x54_NoSoftReset_OFFSET                              3
+#define DxF0x54_NoSoftReset_WIDTH                               1
+#define DxF0x54_NoSoftReset_MASK                                0x8
+#define DxF0x54_Reserved_7_4_OFFSET                             4
+#define DxF0x54_Reserved_7_4_WIDTH                              4
+#define DxF0x54_Reserved_7_4_MASK                               0xf0
+#define DxF0x54_PmeEn_OFFSET                                    8
+#define DxF0x54_PmeEn_WIDTH                                     1
+#define DxF0x54_PmeEn_MASK                                      0x100
+#define DxF0x54_DataSelect_OFFSET                               9
+#define DxF0x54_DataSelect_WIDTH                                4
+#define DxF0x54_DataSelect_MASK                                 0x1e00
+#define DxF0x54_DataScale_OFFSET                                13
+#define DxF0x54_DataScale_WIDTH                                 2
+#define DxF0x54_DataScale_MASK                                  0x6000
+#define DxF0x54_PmeStatus_OFFSET                                15
+#define DxF0x54_PmeStatus_WIDTH                                 1
+#define DxF0x54_PmeStatus_MASK                                  0x8000
+#define DxF0x54_Reserved_21_16_OFFSET                           16
+#define DxF0x54_Reserved_21_16_WIDTH                            6
+#define DxF0x54_Reserved_21_16_MASK                             0x3f0000
+#define DxF0x54_B2B3Support_OFFSET                              22
+#define DxF0x54_B2B3Support_WIDTH                               1
+#define DxF0x54_B2B3Support_MASK                                0x400000
+#define DxF0x54_BusPwrEn_OFFSET                                 23
+#define DxF0x54_BusPwrEn_WIDTH                                  1
+#define DxF0x54_BusPwrEn_MASK                                   0x800000
+#define DxF0x54_PmeData_OFFSET                                  24
+#define DxF0x54_PmeData_WIDTH                                   8
+#define DxF0x54_PmeData_MASK                                    0xff000000
+
+/// DxF0x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PowerState:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                              NoSoftReset:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    PmeEn:1 ; ///<
+    UINT32                                               DataSelect:4 ; ///<
+    UINT32                                                DataScale:2 ; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                           Reserved_21_16:6 ; ///<
+    UINT32                                              B2B3Support:1 ; ///<
+    UINT32                                                 BusPwrEn:1 ; ///<
+    UINT32                                                  PmeData:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x54_STRUCT;
+
+// **** DxF0x58 Register Definition ****
+// Address
+#define DxF0x58_ADDRESS                                         0x58
+
+// Type
+#define DxF0x58_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x58_CapID_OFFSET                                    0
+#define DxF0x58_CapID_WIDTH                                     8
+#define DxF0x58_CapID_MASK                                      0xff
+#define DxF0x58_NextPtr_OFFSET                                  8
+#define DxF0x58_NextPtr_WIDTH                                   8
+#define DxF0x58_NextPtr_MASK                                    0xff00
+#define DxF0x58_Version_OFFSET                                  16
+#define DxF0x58_Version_WIDTH                                   4
+#define DxF0x58_Version_MASK                                    0xf0000
+#define DxF0x58_DeviceType_OFFSET                               20
+#define DxF0x58_DeviceType_WIDTH                                4
+#define DxF0x58_DeviceType_MASK                                 0xf00000
+#define DxF0x58_SlotImplemented_OFFSET                          24
+#define DxF0x58_SlotImplemented_WIDTH                           1
+#define DxF0x58_SlotImplemented_MASK                            0x1000000
+#define DxF0x58_IntMessageNum_OFFSET                            25
+#define DxF0x58_IntMessageNum_WIDTH                             5
+#define DxF0x58_IntMessageNum_MASK                              0x3e000000
+#define DxF0x58_Reserved_31_30_OFFSET                           30
+#define DxF0x58_Reserved_31_30_WIDTH                            2
+#define DxF0x58_Reserved_31_30_MASK                             0xc0000000
+
+/// DxF0x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:4 ; ///<
+    UINT32                                               DeviceType:4 ; ///<
+    UINT32                                          SlotImplemented:1 ; ///<
+    UINT32                                            IntMessageNum:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x58_STRUCT;
+
+// **** DxF0x5C Register Definition ****
+// Address
+#define DxF0x5C_ADDRESS                                         0x5c
+
+// Type
+#define DxF0x5C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x5C_MaxPayloadSupport_OFFSET                        0
+#define DxF0x5C_MaxPayloadSupport_WIDTH                         3
+#define DxF0x5C_MaxPayloadSupport_MASK                          0x7
+#define DxF0x5C_PhantomFunc_OFFSET                              3
+#define DxF0x5C_PhantomFunc_WIDTH                               2
+#define DxF0x5C_PhantomFunc_MASK                                0x18
+#define DxF0x5C_ExtendedTag_OFFSET                              5
+#define DxF0x5C_ExtendedTag_WIDTH                               1
+#define DxF0x5C_ExtendedTag_MASK                                0x20
+#define DxF0x5C_L0SAcceptableLatency_OFFSET                     6
+#define DxF0x5C_L0SAcceptableLatency_WIDTH                      3
+#define DxF0x5C_L0SAcceptableLatency_MASK                       0x1c0
+#define DxF0x5C_L1AcceptableLatency_OFFSET                      9
+#define DxF0x5C_L1AcceptableLatency_WIDTH                       3
+#define DxF0x5C_L1AcceptableLatency_MASK                        0xe00
+#define DxF0x5C_Reserved_14_12_OFFSET                           12
+#define DxF0x5C_Reserved_14_12_WIDTH                            3
+#define DxF0x5C_Reserved_14_12_MASK                             0x7000
+#define DxF0x5C_RoleBasedErrReporting_OFFSET                    15
+#define DxF0x5C_RoleBasedErrReporting_WIDTH                     1
+#define DxF0x5C_RoleBasedErrReporting_MASK                      0x8000
+#define DxF0x5C_Reserved_17_16_OFFSET                           16
+#define DxF0x5C_Reserved_17_16_WIDTH                            2
+#define DxF0x5C_Reserved_17_16_MASK                             0x30000
+#define DxF0x5C_CapturedSlotPowerLimit_OFFSET                   18
+#define DxF0x5C_CapturedSlotPowerLimit_WIDTH                    8
+#define DxF0x5C_CapturedSlotPowerLimit_MASK                     0x3fc0000
+#define DxF0x5C_CapturedSlotPowerScale_OFFSET                   26
+#define DxF0x5C_CapturedSlotPowerScale_WIDTH                    2
+#define DxF0x5C_CapturedSlotPowerScale_MASK                     0xc000000
+#define DxF0x5C_FlrCapable_OFFSET                               28
+#define DxF0x5C_FlrCapable_WIDTH                                1
+#define DxF0x5C_FlrCapable_MASK                                 0x10000000
+#define DxF0x5C_Reserved_31_29_OFFSET                           29
+#define DxF0x5C_Reserved_31_29_WIDTH                            3
+#define DxF0x5C_Reserved_31_29_MASK                             0xe0000000
+
+/// DxF0x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        MaxPayloadSupport:3 ; ///<
+    UINT32                                              PhantomFunc:2 ; ///<
+    UINT32                                              ExtendedTag:1 ; ///<
+    UINT32                                     L0SAcceptableLatency:3 ; ///<
+    UINT32                                      L1AcceptableLatency:3 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                    RoleBasedErrReporting:1 ; ///<
+    UINT32                                           Reserved_17_16:2 ; ///<
+    UINT32                                   CapturedSlotPowerLimit:8 ; ///<
+    UINT32                                   CapturedSlotPowerScale:2 ; ///<
+    UINT32                                               FlrCapable:1 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x5C_STRUCT;
+
+// **** DxF0x60 Register Definition ****
+// Address
+#define DxF0x60_ADDRESS                                         0x60
+
+// Type
+#define DxF0x60_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x60_CorrErrEn_OFFSET                                0
+#define DxF0x60_CorrErrEn_WIDTH                                 1
+#define DxF0x60_CorrErrEn_MASK                                  0x1
+#define DxF0x60_NonFatalErrEn_OFFSET                            1
+#define DxF0x60_NonFatalErrEn_WIDTH                             1
+#define DxF0x60_NonFatalErrEn_MASK                              0x2
+#define DxF0x60_FatalErrEn_OFFSET                               2
+#define DxF0x60_FatalErrEn_WIDTH                                1
+#define DxF0x60_FatalErrEn_MASK                                 0x4
+#define DxF0x60_UsrReportEn_OFFSET                              3
+#define DxF0x60_UsrReportEn_WIDTH                               1
+#define DxF0x60_UsrReportEn_MASK                                0x8
+#define DxF0x60_RelaxedOrdEn_OFFSET                             4
+#define DxF0x60_RelaxedOrdEn_WIDTH                              1
+#define DxF0x60_RelaxedOrdEn_MASK                               0x10
+#define DxF0x60_MaxPayloadSize_OFFSET                           5
+#define DxF0x60_MaxPayloadSize_WIDTH                            3
+#define DxF0x60_MaxPayloadSize_MASK                             0xe0
+#define DxF0x60_ExtendedTagEn_OFFSET                            8
+#define DxF0x60_ExtendedTagEn_WIDTH                             1
+#define DxF0x60_ExtendedTagEn_MASK                              0x100
+#define DxF0x60_PhantomFuncEn_OFFSET                            9
+#define DxF0x60_PhantomFuncEn_WIDTH                             1
+#define DxF0x60_PhantomFuncEn_MASK                              0x200
+#define DxF0x60_AuxPowerPmEn_OFFSET                             10
+#define DxF0x60_AuxPowerPmEn_WIDTH                              1
+#define DxF0x60_AuxPowerPmEn_MASK                               0x400
+#define DxF0x60_NoSnoopEnable_OFFSET                            11
+#define DxF0x60_NoSnoopEnable_WIDTH                             1
+#define DxF0x60_NoSnoopEnable_MASK                              0x800
+#define DxF0x60_MaxRequestSize_OFFSET                           12
+#define DxF0x60_MaxRequestSize_WIDTH                            3
+#define DxF0x60_MaxRequestSize_MASK                             0x7000
+#define DxF0x60_BridgeCfgRetryEn_OFFSET                         15
+#define DxF0x60_BridgeCfgRetryEn_WIDTH                          1
+#define DxF0x60_BridgeCfgRetryEn_MASK                           0x8000
+#define DxF0x60_CorrErr_OFFSET                                  16
+#define DxF0x60_CorrErr_WIDTH                                   1
+#define DxF0x60_CorrErr_MASK                                    0x10000
+#define DxF0x60_NonFatalErr_OFFSET                              17
+#define DxF0x60_NonFatalErr_WIDTH                               1
+#define DxF0x60_NonFatalErr_MASK                                0x20000
+#define DxF0x60_FatalErr_OFFSET                                 18
+#define DxF0x60_FatalErr_WIDTH                                  1
+#define DxF0x60_FatalErr_MASK                                   0x40000
+#define DxF0x60_UsrDetected_OFFSET                              19
+#define DxF0x60_UsrDetected_WIDTH                               1
+#define DxF0x60_UsrDetected_MASK                                0x80000
+#define DxF0x60_AuxPwr_OFFSET                                   20
+#define DxF0x60_AuxPwr_WIDTH                                    1
+#define DxF0x60_AuxPwr_MASK                                     0x100000
+#define DxF0x60_TransactionsPending_OFFSET                      21
+#define DxF0x60_TransactionsPending_WIDTH                       1
+#define DxF0x60_TransactionsPending_MASK                        0x200000
+#define DxF0x60_Reserved_31_22_OFFSET                           22
+#define DxF0x60_Reserved_31_22_WIDTH                            10
+#define DxF0x60_Reserved_31_22_MASK                             0xffc00000
+
+/// DxF0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CorrErrEn:1 ; ///<
+    UINT32                                            NonFatalErrEn:1 ; ///<
+    UINT32                                               FatalErrEn:1 ; ///<
+    UINT32                                              UsrReportEn:1 ; ///<
+    UINT32                                             RelaxedOrdEn:1 ; ///<
+    UINT32                                           MaxPayloadSize:3 ; ///<
+    UINT32                                            ExtendedTagEn:1 ; ///<
+    UINT32                                            PhantomFuncEn:1 ; ///<
+    UINT32                                             AuxPowerPmEn:1 ; ///<
+    UINT32                                            NoSnoopEnable:1 ; ///<
+    UINT32                                           MaxRequestSize:3 ; ///<
+    UINT32                                         BridgeCfgRetryEn:1 ; ///<
+    UINT32                                                  CorrErr:1 ; ///<
+    UINT32                                              NonFatalErr:1 ; ///<
+    UINT32                                                 FatalErr:1 ; ///<
+    UINT32                                              UsrDetected:1 ; ///<
+    UINT32                                                   AuxPwr:1 ; ///<
+    UINT32                                      TransactionsPending:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x60_STRUCT;
+
+
+// **** DxF0x68 Register Definition ****
+// Address
+#define DxF0x68_ADDRESS                                         0x68
+
+// Type
+#define DxF0x68_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x68_PmControl_OFFSET                                0
+#define DxF0x68_PmControl_WIDTH                                 2
+#define DxF0x68_PmControl_MASK                                  0x3
+#define DxF0x68_Reserved_2_2_OFFSET                             2
+#define DxF0x68_Reserved_2_2_WIDTH                              1
+#define DxF0x68_Reserved_2_2_MASK                               0x4
+#define DxF0x68_ReadCplBoundary_OFFSET                          3
+#define DxF0x68_ReadCplBoundary_WIDTH                           1
+#define DxF0x68_ReadCplBoundary_MASK                            0x8
+#define DxF0x68_LinkDis_OFFSET                                  4
+#define DxF0x68_LinkDis_WIDTH                                   1
+#define DxF0x68_LinkDis_MASK                                    0x10
+#define DxF0x68_RetrainLink_OFFSET                              5
+#define DxF0x68_RetrainLink_WIDTH                               1
+#define DxF0x68_RetrainLink_MASK                                0x20
+#define DxF0x68_CommonClockCfg_OFFSET                           6
+#define DxF0x68_CommonClockCfg_WIDTH                            1
+#define DxF0x68_CommonClockCfg_MASK                             0x40
+#define DxF0x68_ExtendedSync_OFFSET                             7
+#define DxF0x68_ExtendedSync_WIDTH                              1
+#define DxF0x68_ExtendedSync_MASK                               0x80
+#define DxF0x68_ClockPowerManagementEn_OFFSET                   8
+#define DxF0x68_ClockPowerManagementEn_WIDTH                    1
+#define DxF0x68_ClockPowerManagementEn_MASK                     0x100
+#define DxF0x68_HWAutonomousWidthDisable_OFFSET                 9
+#define DxF0x68_HWAutonomousWidthDisable_WIDTH                  1
+#define DxF0x68_HWAutonomousWidthDisable_MASK                   0x200
+#define DxF0x68_LinkBWManagementEn_OFFSET                       10
+#define DxF0x68_LinkBWManagementEn_WIDTH                        1
+#define DxF0x68_LinkBWManagementEn_MASK                         0x400
+#define DxF0x68_LinkAutonomousBWIntEn_OFFSET                    11
+#define DxF0x68_LinkAutonomousBWIntEn_WIDTH                     1
+#define DxF0x68_LinkAutonomousBWIntEn_MASK                      0x800
+#define DxF0x68_Reserved_15_12_OFFSET                           12
+#define DxF0x68_Reserved_15_12_WIDTH                            4
+#define DxF0x68_Reserved_15_12_MASK                             0xf000
+#define DxF0x68_LinkSpeed_OFFSET                                16
+#define DxF0x68_LinkSpeed_WIDTH                                 4
+#define DxF0x68_LinkSpeed_MASK                                  0xf0000
+#define DxF0x68_NegotiatedLinkWidth_OFFSET                      20
+#define DxF0x68_NegotiatedLinkWidth_WIDTH                       6
+#define DxF0x68_NegotiatedLinkWidth_MASK                        0x3f00000
+#define DxF0x68_Reserved_26_26_OFFSET                           26
+#define DxF0x68_Reserved_26_26_WIDTH                            1
+#define DxF0x68_Reserved_26_26_MASK                             0x4000000
+#define DxF0x68_LinkTraining_OFFSET                             27
+#define DxF0x68_LinkTraining_WIDTH                              1
+#define DxF0x68_LinkTraining_MASK                               0x8000000
+#define DxF0x68_SlotClockCfg_OFFSET                             28
+#define DxF0x68_SlotClockCfg_WIDTH                              1
+#define DxF0x68_SlotClockCfg_MASK                               0x10000000
+#define DxF0x68_DlActive_OFFSET                                 29
+#define DxF0x68_DlActive_WIDTH                                  1
+#define DxF0x68_DlActive_MASK                                   0x20000000
+#define DxF0x68_LinkBWManagementStatus_OFFSET                   30
+#define DxF0x68_LinkBWManagementStatus_WIDTH                    1
+#define DxF0x68_LinkBWManagementStatus_MASK                     0x40000000
+#define DxF0x68_LinkAutonomousBWStatus_OFFSET                   31
+#define DxF0x68_LinkAutonomousBWStatus_WIDTH                    1
+#define DxF0x68_LinkAutonomousBWStatus_MASK                     0x80000000
+
+/// DxF0x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PmControl:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          ReadCplBoundary:1 ; ///<
+    UINT32                                                  LinkDis:1 ; ///<
+    UINT32                                              RetrainLink:1 ; ///<
+    UINT32                                           CommonClockCfg:1 ; ///<
+    UINT32                                             ExtendedSync:1 ; ///<
+    UINT32                                   ClockPowerManagementEn:1 ; ///<
+    UINT32                                 HWAutonomousWidthDisable:1 ; ///<
+    UINT32                                       LinkBWManagementEn:1 ; ///<
+    UINT32                                    LinkAutonomousBWIntEn:1 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                LinkSpeed:4 ; ///<
+    UINT32                                      NegotiatedLinkWidth:6 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                             LinkTraining:1 ; ///<
+    UINT32                                             SlotClockCfg:1 ; ///<
+    UINT32                                                 DlActive:1 ; ///<
+    UINT32                                   LinkBWManagementStatus:1 ; ///<
+    UINT32                                   LinkAutonomousBWStatus:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x68_STRUCT;
+
+// **** DxF0x6C Register Definition ****
+// Address
+#define DxF0x6C_ADDRESS                                         0x6c
+
+// Type
+#define DxF0x6C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x6C_AttnButtonPresent_OFFSET                        0
+#define DxF0x6C_AttnButtonPresent_WIDTH                         1
+#define DxF0x6C_AttnButtonPresent_MASK                          0x1
+#define DxF0x6C_PwrControllerPresent_OFFSET                     1
+#define DxF0x6C_PwrControllerPresent_WIDTH                      1
+#define DxF0x6C_PwrControllerPresent_MASK                       0x2
+#define DxF0x6C_MrlSensorPresent_OFFSET                         2
+#define DxF0x6C_MrlSensorPresent_WIDTH                          1
+#define DxF0x6C_MrlSensorPresent_MASK                           0x4
+#define DxF0x6C_AttnIndicatorPresent_OFFSET                     3
+#define DxF0x6C_AttnIndicatorPresent_WIDTH                      1
+#define DxF0x6C_AttnIndicatorPresent_MASK                       0x8
+#define DxF0x6C_PwrIndicatorPresent_OFFSET                      4
+#define DxF0x6C_PwrIndicatorPresent_WIDTH                       1
+#define DxF0x6C_PwrIndicatorPresent_MASK                        0x10
+#define DxF0x6C_HotplugSurprise_OFFSET                          5
+#define DxF0x6C_HotplugSurprise_WIDTH                           1
+#define DxF0x6C_HotplugSurprise_MASK                            0x20
+#define DxF0x6C_HotplugCapable_OFFSET                           6
+#define DxF0x6C_HotplugCapable_WIDTH                            1
+#define DxF0x6C_HotplugCapable_MASK                             0x40
+#define DxF0x6C_SlotPwrLimitValue_OFFSET                        7
+#define DxF0x6C_SlotPwrLimitValue_WIDTH                         8
+#define DxF0x6C_SlotPwrLimitValue_MASK                          0x7f80
+#define DxF0x6C_SlotPwrLimitScale_OFFSET                        15
+#define DxF0x6C_SlotPwrLimitScale_WIDTH                         2
+#define DxF0x6C_SlotPwrLimitScale_MASK                          0x18000
+#define DxF0x6C_ElecMechIlPresent_OFFSET                        17
+#define DxF0x6C_ElecMechIlPresent_WIDTH                         1
+#define DxF0x6C_ElecMechIlPresent_MASK                          0x20000
+#define DxF0x6C_NoCmdCplSupport_OFFSET                          18
+#define DxF0x6C_NoCmdCplSupport_WIDTH                           1
+#define DxF0x6C_NoCmdCplSupport_MASK                            0x40000
+#define DxF0x6C_PhysicalSlotNumber_OFFSET                       19
+#define DxF0x6C_PhysicalSlotNumber_WIDTH                        13
+#define DxF0x6C_PhysicalSlotNumber_MASK                         0xfff80000
+
+/// DxF0x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AttnButtonPresent:1 ; ///<
+    UINT32                                     PwrControllerPresent:1 ; ///<
+    UINT32                                         MrlSensorPresent:1 ; ///<
+    UINT32                                     AttnIndicatorPresent:1 ; ///<
+    UINT32                                      PwrIndicatorPresent:1 ; ///<
+    UINT32                                          HotplugSurprise:1 ; ///<
+    UINT32                                           HotplugCapable:1 ; ///<
+    UINT32                                        SlotPwrLimitValue:8 ; ///<
+    UINT32                                        SlotPwrLimitScale:2 ; ///<
+    UINT32                                        ElecMechIlPresent:1 ; ///<
+    UINT32                                          NoCmdCplSupport:1 ; ///<
+    UINT32                                       PhysicalSlotNumber:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x6C_STRUCT;
+
+// **** DxF0x70 Register Definition ****
+// Address
+#define DxF0x70_ADDRESS                                         0x70
+
+// Type
+#define DxF0x70_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x70_AttnButtonPressedEn_OFFSET                      0
+#define DxF0x70_AttnButtonPressedEn_WIDTH                       1
+#define DxF0x70_AttnButtonPressedEn_MASK                        0x1
+#define DxF0x70_PwrFaultDetectedEn_OFFSET                       1
+#define DxF0x70_PwrFaultDetectedEn_WIDTH                        1
+#define DxF0x70_PwrFaultDetectedEn_MASK                         0x2
+#define DxF0x70_MrlSensorChangedEn_OFFSET                       2
+#define DxF0x70_MrlSensorChangedEn_WIDTH                        1
+#define DxF0x70_MrlSensorChangedEn_MASK                         0x4
+#define DxF0x70_PresenceDetectChangedEn_OFFSET                  3
+#define DxF0x70_PresenceDetectChangedEn_WIDTH                   1
+#define DxF0x70_PresenceDetectChangedEn_MASK                    0x8
+#define DxF0x70_CmdCplIntrEn_OFFSET                             4
+#define DxF0x70_CmdCplIntrEn_WIDTH                              1
+#define DxF0x70_CmdCplIntrEn_MASK                               0x10
+#define DxF0x70_HotplugIntrEn_OFFSET                            5
+#define DxF0x70_HotplugIntrEn_WIDTH                             1
+#define DxF0x70_HotplugIntrEn_MASK                              0x20
+#define DxF0x70_AttnIndicatorControl_OFFSET                     6
+#define DxF0x70_AttnIndicatorControl_WIDTH                      2
+#define DxF0x70_AttnIndicatorControl_MASK                       0xc0
+#define DxF0x70_PwrIndicatorCntl_OFFSET                         8
+#define DxF0x70_PwrIndicatorCntl_WIDTH                          2
+#define DxF0x70_PwrIndicatorCntl_MASK                           0x300
+#define DxF0x70_PwrControllerCntl_OFFSET                        10
+#define DxF0x70_PwrControllerCntl_WIDTH                         1
+#define DxF0x70_PwrControllerCntl_MASK                          0x400
+#define DxF0x70_ElecMechIlCntl_OFFSET                           11
+#define DxF0x70_ElecMechIlCntl_WIDTH                            1
+#define DxF0x70_ElecMechIlCntl_MASK                             0x800
+#define DxF0x70_DlStateChangedEn_OFFSET                         12
+#define DxF0x70_DlStateChangedEn_WIDTH                          1
+#define DxF0x70_DlStateChangedEn_MASK                           0x1000
+#define DxF0x70_Reserved_15_13_OFFSET                           13
+#define DxF0x70_Reserved_15_13_WIDTH                            3
+#define DxF0x70_Reserved_15_13_MASK                             0xe000
+#define DxF0x70_AttnButtonPressed_OFFSET                        16
+#define DxF0x70_AttnButtonPressed_WIDTH                         1
+#define DxF0x70_AttnButtonPressed_MASK                          0x10000
+#define DxF0x70_PwrFaultDetected_OFFSET                         17
+#define DxF0x70_PwrFaultDetected_WIDTH                          1
+#define DxF0x70_PwrFaultDetected_MASK                           0x20000
+#define DxF0x70_MrlSensorChanged_OFFSET                         18
+#define DxF0x70_MrlSensorChanged_WIDTH                          1
+#define DxF0x70_MrlSensorChanged_MASK                           0x40000
+#define DxF0x70_PresenceDetectChanged_OFFSET                    19
+#define DxF0x70_PresenceDetectChanged_WIDTH                     1
+#define DxF0x70_PresenceDetectChanged_MASK                      0x80000
+#define DxF0x70_CmdCpl_OFFSET                                   20
+#define DxF0x70_CmdCpl_WIDTH                                    1
+#define DxF0x70_CmdCpl_MASK                                     0x100000
+#define DxF0x70_MrlSensorState_OFFSET                           21
+#define DxF0x70_MrlSensorState_WIDTH                            1
+#define DxF0x70_MrlSensorState_MASK                             0x200000
+#define DxF0x70_PresenceDetectState_OFFSET                      22
+#define DxF0x70_PresenceDetectState_WIDTH                       1
+#define DxF0x70_PresenceDetectState_MASK                        0x400000
+#define DxF0x70_ElecMechIlSts_OFFSET                            23
+#define DxF0x70_ElecMechIlSts_WIDTH                             1
+#define DxF0x70_ElecMechIlSts_MASK                              0x800000
+#define DxF0x70_DlStateChanged_OFFSET                           24
+#define DxF0x70_DlStateChanged_WIDTH                            1
+#define DxF0x70_DlStateChanged_MASK                             0x1000000
+#define DxF0x70_Reserved_31_25_OFFSET                           25
+#define DxF0x70_Reserved_31_25_WIDTH                            7
+#define DxF0x70_Reserved_31_25_MASK                             0xfe000000
+
+/// DxF0x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      AttnButtonPressedEn:1 ; ///<
+    UINT32                                       PwrFaultDetectedEn:1 ; ///<
+    UINT32                                       MrlSensorChangedEn:1 ; ///<
+    UINT32                                  PresenceDetectChangedEn:1 ; ///<
+    UINT32                                             CmdCplIntrEn:1 ; ///<
+    UINT32                                            HotplugIntrEn:1 ; ///<
+    UINT32                                     AttnIndicatorControl:2 ; ///<
+    UINT32                                         PwrIndicatorCntl:2 ; ///<
+    UINT32                                        PwrControllerCntl:1 ; ///<
+    UINT32                                           ElecMechIlCntl:1 ; ///<
+    UINT32                                         DlStateChangedEn:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                        AttnButtonPressed:1 ; ///<
+    UINT32                                         PwrFaultDetected:1 ; ///<
+    UINT32                                         MrlSensorChanged:1 ; ///<
+    UINT32                                    PresenceDetectChanged:1 ; ///<
+    UINT32                                                   CmdCpl:1 ; ///<
+    UINT32                                           MrlSensorState:1 ; ///<
+    UINT32                                      PresenceDetectState:1 ; ///<
+    UINT32                                            ElecMechIlSts:1 ; ///<
+    UINT32                                           DlStateChanged:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x70_STRUCT;
+
+// **** DxF0x74 Register Definition ****
+// Address
+#define DxF0x74_ADDRESS                                         0x74
+
+// Type
+#define DxF0x74_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x74_SerrOnCorrErrEn_OFFSET                          0
+#define DxF0x74_SerrOnCorrErrEn_WIDTH                           1
+#define DxF0x74_SerrOnCorrErrEn_MASK                            0x1
+#define DxF0x74_SerrOnNonFatalErrEn_OFFSET                      1
+#define DxF0x74_SerrOnNonFatalErrEn_WIDTH                       1
+#define DxF0x74_SerrOnNonFatalErrEn_MASK                        0x2
+#define DxF0x74_SerrOnFatalErrEn_OFFSET                         2
+#define DxF0x74_SerrOnFatalErrEn_WIDTH                          1
+#define DxF0x74_SerrOnFatalErrEn_MASK                           0x4
+#define DxF0x74_PmIntEn_OFFSET                                  3
+#define DxF0x74_PmIntEn_WIDTH                                   1
+#define DxF0x74_PmIntEn_MASK                                    0x8
+#define DxF0x74_CrsSoftVisibilityEn_OFFSET                      4
+#define DxF0x74_CrsSoftVisibilityEn_WIDTH                       1
+#define DxF0x74_CrsSoftVisibilityEn_MASK                        0x10
+#define DxF0x74_Reserved_15_5_OFFSET                            5
+#define DxF0x74_Reserved_15_5_WIDTH                             11
+#define DxF0x74_Reserved_15_5_MASK                              0xffe0
+#define DxF0x74_CrsSoftVisibility_OFFSET                        16
+#define DxF0x74_CrsSoftVisibility_WIDTH                         1
+#define DxF0x74_CrsSoftVisibility_MASK                          0x10000
+#define DxF0x74_Reserved_31_17_OFFSET                           17
+#define DxF0x74_Reserved_31_17_WIDTH                            15
+#define DxF0x74_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          SerrOnCorrErrEn:1 ; ///<
+    UINT32                                      SerrOnNonFatalErrEn:1 ; ///<
+    UINT32                                         SerrOnFatalErrEn:1 ; ///<
+    UINT32                                                  PmIntEn:1 ; ///<
+    UINT32                                      CrsSoftVisibilityEn:1 ; ///<
+    UINT32                                            Reserved_15_5:11; ///<
+    UINT32                                        CrsSoftVisibility:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x74_STRUCT;
+
+// **** DxF0x78 Register Definition ****
+// Address
+#define DxF0x78_ADDRESS                                         0x78
+
+// Type
+#define DxF0x78_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x78_PmeRequestorId_OFFSET                           0
+#define DxF0x78_PmeRequestorId_WIDTH                            16
+#define DxF0x78_PmeRequestorId_MASK                             0xffff
+#define DxF0x78_PmeStatus_OFFSET                                16
+#define DxF0x78_PmeStatus_WIDTH                                 1
+#define DxF0x78_PmeStatus_MASK                                  0x10000
+#define DxF0x78_PmePending_OFFSET                               17
+#define DxF0x78_PmePending_WIDTH                                1
+#define DxF0x78_PmePending_MASK                                 0x20000
+#define DxF0x78_Reserved_31_18_OFFSET                           18
+#define DxF0x78_Reserved_31_18_WIDTH                            14
+#define DxF0x78_Reserved_31_18_MASK                             0xfffc0000
+
+/// DxF0x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PmeRequestorId:16; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                               PmePending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x78_STRUCT;
+
+// **** DxF0x7C Register Definition ****
+// Address
+#define DxF0x7C_ADDRESS                                         0x7c
+
+// Type
+#define DxF0x7C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x7C_CplTimeoutRangeSup_OFFSET                       0
+#define DxF0x7C_CplTimeoutRangeSup_WIDTH                        4
+#define DxF0x7C_CplTimeoutRangeSup_MASK                         0xf
+#define DxF0x7C_CplTimeoutDisSup_OFFSET                         4
+#define DxF0x7C_CplTimeoutDisSup_WIDTH                          1
+#define DxF0x7C_CplTimeoutDisSup_MASK                           0x10
+#define DxF0x7C_AriForwardingSupported_OFFSET                   5
+#define DxF0x7C_AriForwardingSupported_WIDTH                    1
+#define DxF0x7C_AriForwardingSupported_MASK                     0x20
+#define DxF0x7C_Reserved_31_6_OFFSET                            6
+#define DxF0x7C_Reserved_31_6_WIDTH                             26
+#define DxF0x7C_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       CplTimeoutRangeSup:4 ; ///<
+    UINT32                                         CplTimeoutDisSup:1 ; ///<
+    UINT32                                   AriForwardingSupported:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x7C_STRUCT;
+
+// **** DxF0x80 Register Definition ****
+// Address
+#define DxF0x80_ADDRESS                                         0x80
+
+// Type
+#define DxF0x80_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x80_CplTimeoutValue_OFFSET                          0
+#define DxF0x80_CplTimeoutValue_WIDTH                           4
+#define DxF0x80_CplTimeoutValue_MASK                            0xf
+#define DxF0x80_CplTimeoutDis_OFFSET                            4
+#define DxF0x80_CplTimeoutDis_WIDTH                             1
+#define DxF0x80_CplTimeoutDis_MASK                              0x10
+#define DxF0x80_AriForwardingEn_OFFSET                          5
+#define DxF0x80_AriForwardingEn_WIDTH                           1
+#define DxF0x80_AriForwardingEn_MASK                            0x20
+#define DxF0x80_Reserved_31_6_OFFSET                            6
+#define DxF0x80_Reserved_31_6_WIDTH                             26
+#define DxF0x80_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CplTimeoutValue:4 ; ///<
+    UINT32                                            CplTimeoutDis:1 ; ///<
+    UINT32                                          AriForwardingEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x80_STRUCT;
+
+// **** DxF0x84 Register Definition ****
+// Address
+#define DxF0x84_ADDRESS                                         0x84
+
+// Type
+#define DxF0x84_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x84_Reserved_31_0_OFFSET                            0
+#define DxF0x84_Reserved_31_0_WIDTH                             32
+#define DxF0x84_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x84_STRUCT;
+
+// **** DxF0x88 Register Definition ****
+// Address
+#define DxF0x88_ADDRESS                                         0x88
+
+// Type
+#define DxF0x88_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x88_TargetLinkSpeed_OFFSET                          0
+#define DxF0x88_TargetLinkSpeed_WIDTH                           4
+#define DxF0x88_TargetLinkSpeed_MASK                            0xf
+#define DxF0x88_EnterCompliance_OFFSET                          4
+#define DxF0x88_EnterCompliance_WIDTH                           1
+#define DxF0x88_EnterCompliance_MASK                            0x10
+#define DxF0x88_HwAutonomousSpeedDisable_OFFSET                 5
+#define DxF0x88_HwAutonomousSpeedDisable_WIDTH                  1
+#define DxF0x88_HwAutonomousSpeedDisable_MASK                   0x20
+#define DxF0x88_SelectableDeemphasis_OFFSET                     6
+#define DxF0x88_SelectableDeemphasis_WIDTH                      1
+#define DxF0x88_SelectableDeemphasis_MASK                       0x40
+#define DxF0x88_XmitMargin_OFFSET                               7
+#define DxF0x88_XmitMargin_WIDTH                                3
+#define DxF0x88_XmitMargin_MASK                                 0x380
+#define DxF0x88_EnterModCompliance_OFFSET                       10
+#define DxF0x88_EnterModCompliance_WIDTH                        1
+#define DxF0x88_EnterModCompliance_MASK                         0x400
+#define DxF0x88_ComplianceSOS_OFFSET                            11
+#define DxF0x88_ComplianceSOS_WIDTH                             1
+#define DxF0x88_ComplianceSOS_MASK                              0x800
+#define DxF0x88_ComplianceDeemphasis_OFFSET                     12
+#define DxF0x88_ComplianceDeemphasis_WIDTH                      1
+#define DxF0x88_ComplianceDeemphasis_MASK                       0x1000
+#define DxF0x88_Reserved_15_13_OFFSET                           13
+#define DxF0x88_Reserved_15_13_WIDTH                            3
+#define DxF0x88_Reserved_15_13_MASK                             0xe000
+#define DxF0x88_CurDeemphasisLevel_OFFSET                       16
+#define DxF0x88_CurDeemphasisLevel_WIDTH                        1
+#define DxF0x88_CurDeemphasisLevel_MASK                         0x10000
+#define DxF0x88_Reserved_31_17_OFFSET                           17
+#define DxF0x88_Reserved_31_17_WIDTH                            15
+#define DxF0x88_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TargetLinkSpeed:4 ; ///<
+    UINT32                                          EnterCompliance:1 ; ///<
+    UINT32                                 HwAutonomousSpeedDisable:1 ; ///<
+    UINT32                                     SelectableDeemphasis:1 ; ///<
+    UINT32                                               XmitMargin:3 ; ///<
+    UINT32                                       EnterModCompliance:1 ; ///<
+    UINT32                                            ComplianceSOS:1 ; ///<
+    UINT32                                     ComplianceDeemphasis:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                       CurDeemphasisLevel:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x88_STRUCT;
+
+// **** DxF0x8C Register Definition ****
+// Address
+#define DxF0x8C_ADDRESS                                         0x8c
+
+// Type
+#define DxF0x8C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x8C_Reserved_31_0_OFFSET                            0
+#define DxF0x8C_Reserved_31_0_WIDTH                             32
+#define DxF0x8C_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x8C_STRUCT;
+
+// **** DxF0x90 Register Definition ****
+// Address
+#define DxF0x90_ADDRESS                                         0x90
+
+// Type
+#define DxF0x90_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x90_Reserved_31_0_OFFSET                            0
+#define DxF0x90_Reserved_31_0_WIDTH                             32
+#define DxF0x90_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x90_STRUCT;
+
+// **** DxF0x128 Register Definition ****
+// Address
+#define DxF0x128_ADDRESS                                        0x128
+
+// Type
+#define DxF0x128_TYPE                                           TYPE_D4F0
+// Field Data
+#define DxF0x128_Reserved_15_0_OFFSET                           0
+#define DxF0x128_Reserved_15_0_WIDTH                            16
+#define DxF0x128_Reserved_15_0_MASK                             0xffff
+#define DxF0x128_PortArbTableStatus_OFFSET                      16
+#define DxF0x128_PortArbTableStatus_WIDTH                       1
+#define DxF0x128_PortArbTableStatus_MASK                        0x10000
+#define DxF0x128_VcNegotiationPending_OFFSET                    17
+#define DxF0x128_VcNegotiationPending_WIDTH                     1
+#define DxF0x128_VcNegotiationPending_MASK                      0x20000
+#define DxF0x128_Reserved_31_18_OFFSET                          18
+#define DxF0x128_Reserved_31_18_WIDTH                           14
+#define DxF0x128_Reserved_31_18_MASK                            0xfffc0000
+
+/// DxF0x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                       PortArbTableStatus:1 ; ///<
+    UINT32                                     VcNegotiationPending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x128_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// **** D0F0x64_x00 Register Definition ****
+// Address
+#define D0F0x64_x00_ADDRESS                                     0x0
+
+// Type
+#define D0F0x64_x00_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x00_Reserved_5_0_OFFSET                         0
+#define D0F0x64_x00_Reserved_5_0_WIDTH                          6
+#define D0F0x64_x00_Reserved_5_0_MASK                           0x3f
+#define D0F0x64_x00_NbFchCfgEn_OFFSET                           6
+#define D0F0x64_x00_NbFchCfgEn_WIDTH                            1
+#define D0F0x64_x00_NbFchCfgEn_MASK                             0x40
+#define D0F0x64_x00_HwInitWrLock_OFFSET                         7
+#define D0F0x64_x00_HwInitWrLock_WIDTH                          1
+#define D0F0x64_x00_HwInitWrLock_MASK                           0x80
+#define D0F0x64_x00_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x00_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x00_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_5_0:6 ; ///<
+    UINT32                                               NbFchCfgEn:1 ; ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x00_STRUCT;
+
+// **** D0F0x64_x0B Register Definition ****
+// Address
+#define D0F0x64_x0B_ADDRESS                                     0xb
+
+// Type
+#define D0F0x64_x0B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x0B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x0B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x0B_SetPowEn_OFFSET                             20
+#define D0F0x64_x0B_SetPowEn_WIDTH                              1
+#define D0F0x64_x0B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x0B_IocFchSetPowEn_OFFSET                       21
+#define D0F0x64_x0B_IocFchSetPowEn_WIDTH                        1
+#define D0F0x64_x0B_IocFchSetPowEn_MASK                         0x200000
+#define D0F0x64_x0B_Reserved_22_22_OFFSET                       22
+#define D0F0x64_x0B_Reserved_22_22_WIDTH                        1
+#define D0F0x64_x0B_Reserved_22_22_MASK                         0x400000
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET                23
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH                 1
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK                  0x800000
+#define D0F0x64_x0B_Reserved_31_24_OFFSET                       24
+#define D0F0x64_x0B_Reserved_31_24_WIDTH                        8
+#define D0F0x64_x0B_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x64_x0B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           IocFchSetPowEn:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    IocFchSetPmeTurnOffEn:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0B_STRUCT;
+
+// **** D0F0x64_x0C Register Definition ****
+// Address
+#define D0F0x64_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x64_x0C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0C_Reserved_1_0_OFFSET                         0
+#define D0F0x64_x0C_Reserved_1_0_WIDTH                          2
+#define D0F0x64_x0C_Reserved_1_0_MASK                           0x3
+#define D0F0x64_x0C_Dev2BridgeDis_OFFSET                        2
+#define D0F0x64_x0C_Dev2BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev2BridgeDis_MASK                          0x4
+#define D0F0x64_x0C_Dev3BridgeDis_OFFSET                        3
+#define D0F0x64_x0C_Dev3BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev3BridgeDis_MASK                          0x8
+#define D0F0x64_x0C_Dev4BridgeDis_OFFSET                        4
+#define D0F0x64_x0C_Dev4BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev4BridgeDis_MASK                          0x10
+#define D0F0x64_x0C_Dev5BridgeDis_OFFSET                        5
+#define D0F0x64_x0C_Dev5BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev5BridgeDis_MASK                          0x20
+#define D0F0x64_x0C_Dev6BridgeDis_OFFSET                        6
+#define D0F0x64_x0C_Dev6BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev6BridgeDis_MASK                          0x40
+#define D0F0x64_x0C_Dev7BridgeDis_OFFSET                        7
+#define D0F0x64_x0C_Dev7BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev7BridgeDis_MASK                          0x80
+#define D0F0x64_x0C_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x0C_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x0C_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            Dev2BridgeDis:1 ; ///<
+    UINT32                                            Dev3BridgeDis:1 ; ///<
+    UINT32                                            Dev4BridgeDis:1 ; ///<
+    UINT32                                            Dev5BridgeDis:1 ; ///<
+    UINT32                                            Dev6BridgeDis:1 ; ///<
+    UINT32                                            Dev7BridgeDis:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0C_STRUCT;
+
+// **** D0F0x64_x19 Register Definition ****
+// Address
+#define D0F0x64_x19_ADDRESS                                     0x19
+
+// Type
+#define D0F0x64_x19_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x19_TomEn_OFFSET                                0
+#define D0F0x64_x19_TomEn_WIDTH                                 1
+#define D0F0x64_x19_TomEn_MASK                                  0x1
+#define D0F0x64_x19_Reserved_22_1_OFFSET                        1
+#define D0F0x64_x19_Reserved_22_1_WIDTH                         22
+#define D0F0x64_x19_Reserved_22_1_MASK                          0x7ffffe
+#define D0F0x64_x19_Tom2_31_23__OFFSET                          23
+#define D0F0x64_x19_Tom2_31_23__WIDTH                           9
+#define D0F0x64_x19_Tom2_31_23__MASK                            0xff800000
+
+/// D0F0x64_x19
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    TomEn:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                              Tom2_31_23_:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x19_STRUCT;
+
+// **** D0F0x64_x1A Register Definition ****
+// Address
+#define D0F0x64_x1A_ADDRESS                                     0x1a
+
+// Type
+#define D0F0x64_x1A_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1A_Tom2_39_32__OFFSET                          0
+#define D0F0x64_x1A_Tom2_39_32__WIDTH                           8
+#define D0F0x64_x1A_Tom2_39_32__MASK                            0xff
+#define D0F0x64_x1A_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x1A_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x1A_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x1A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Tom2_39_32_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1A_STRUCT;
+
+// **** D0F0x64_x1D Register Definition ****
+// Address
+#define D0F0x64_x1D_ADDRESS                                     0x1d
+
+// Type
+#define D0F0x64_x1D_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET                       0
+#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH                        1
+#define D0F0x64_x1D_IntGfxAsPcieEn_MASK                         0x1
+#define D0F0x64_x1D_VgaEn_OFFSET                                1
+#define D0F0x64_x1D_VgaEn_WIDTH                                 1
+#define D0F0x64_x1D_VgaEn_MASK                                  0x2
+#define D0F0x64_x1D_Reserved_2_2_OFFSET                         2
+#define D0F0x64_x1D_Reserved_2_2_WIDTH                          1
+#define D0F0x64_x1D_Reserved_2_2_MASK                           0x4
+#define D0F0x64_x1D_Vga16En_OFFSET                              3
+#define D0F0x64_x1D_Vga16En_WIDTH                               1
+#define D0F0x64_x1D_Vga16En_MASK                                0x8
+#define D0F0x64_x1D_Reserved_31_4_OFFSET                        4
+#define D0F0x64_x1D_Reserved_31_4_WIDTH                         28
+#define D0F0x64_x1D_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F0x64_x1D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           IntGfxAsPcieEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1D_STRUCT;
+
+
+
+
+
+
+
+
+// **** D0F0x64_x53 Register Definition ****
+// Address
+#define D0F0x64_x53_ADDRESS                                     0x53
+
+// Type
+#define D0F0x64_x53_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x53_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x53_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x53_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x53_SetPowEn_OFFSET                             20
+#define D0F0x64_x53_SetPowEn_WIDTH                              1
+#define D0F0x64_x53_SetPowEn_MASK                               0x100000
+#define D0F0x64_x53_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x53_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x53_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x53
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x53_STRUCT;
+
+// **** D0F0x64_x55 Register Definition ****
+// Address
+#define D0F0x64_x55_ADDRESS                                     0x55
+
+// Type
+#define D0F0x64_x55_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x55_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x55_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x55_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x55_SetPowEn_OFFSET                             20
+#define D0F0x64_x55_SetPowEn_WIDTH                              1
+#define D0F0x64_x55_SetPowEn_MASK                               0x100000
+#define D0F0x64_x55_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x55_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x55_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x55
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x55_STRUCT;
+
+// **** D0F0x64_x57 Register Definition ****
+// Address
+#define D0F0x64_x57_ADDRESS                                     0x57
+
+// Type
+#define D0F0x64_x57_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x57_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x57_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x57_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x57_SetPowEn_OFFSET                             20
+#define D0F0x64_x57_SetPowEn_WIDTH                              1
+#define D0F0x64_x57_SetPowEn_MASK                               0x100000
+#define D0F0x64_x57_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x57_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x57_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x57
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x57_STRUCT;
+
+// **** D0F0x64_x59 Register Definition ****
+// Address
+#define D0F0x64_x59_ADDRESS                                     0x59
+
+// Type
+#define D0F0x64_x59_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x59_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x59_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x59_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x59_SetPowEn_OFFSET                             20
+#define D0F0x64_x59_SetPowEn_WIDTH                              1
+#define D0F0x64_x59_SetPowEn_MASK                               0x100000
+#define D0F0x64_x59_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x59_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x59_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x59
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x59_STRUCT;
+
+// **** D0F0x64_x5B Register Definition ****
+// Address
+#define D0F0x64_x5B_ADDRESS                                     0x5b
+
+// Type
+#define D0F0x64_x5B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x5B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x5B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x5B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x5B_SetPowEn_OFFSET                             20
+#define D0F0x64_x5B_SetPowEn_WIDTH                              1
+#define D0F0x64_x5B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x5B_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x5B_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x5B_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x5B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x5B_STRUCT;
+
+/// D0F0x64_x6A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             VoltageLevel:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex488_STRUCT;
+
+/// D0F0x64_x6B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:2 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex489_STRUCT;
+
+// **** D0F0x98_x06 Register Definition ****
+// Address
+#define D0F0x98_x06_ADDRESS                                     0x6
+
+// Type
+#define D0F0x98_x06_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x06_Reserved_25_0_OFFSET                        0
+#define D0F0x98_x06_Reserved_25_0_WIDTH                         26
+#define D0F0x98_x06_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x98_x06_UmiNpMemWrEn_OFFSET                         26
+#define D0F0x98_x06_UmiNpMemWrEn_WIDTH                          1
+#define D0F0x98_x06_UmiNpMemWrEn_MASK                           0x4000000
+#define D0F0x98_x06_Reserved_31_27_OFFSET                       27
+#define D0F0x98_x06_Reserved_31_27_WIDTH                        5
+#define D0F0x98_x06_Reserved_31_27_MASK                         0xf8000000
+
+/// D0F0x98_x06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                             UmiNpMemWrEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x06_STRUCT;
+
+
+
+
+
+// **** D0F0x98_x1E Register Definition ****
+// Address
+#define D0F0x98_x1E_ADDRESS                                     0x1e
+
+// Type
+#define D0F0x98_x1E_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x1E_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x1E_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x1E_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x1E_HiPriEn_OFFSET                              1
+#define D0F0x98_x1E_HiPriEn_WIDTH                               1
+#define D0F0x98_x1E_HiPriEn_MASK                                0x2
+#define D0F0x98_x1E_Reserved_31_2_OFFSET                        2
+#define D0F0x98_x1E_Reserved_31_2_WIDTH                         30
+#define D0F0x98_x1E_Reserved_31_2_MASK                          0xfffffffc
+
+/// D0F0x98_x1E
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  HiPriEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x1E_STRUCT;
+
+
+/// D0F0x98_x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32           ex495_1:1;
+    UINT32                                            Reserved_15_2:14; ///<
+    UINT32           ex495_3:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex495_STRUCT;
+
+
+// **** D0F0x98_x49 Register Definition ****
+// Address
+#define D0F0x98_x49_ADDRESS                                     0x49
+
+// Type
+#define D0F0x98_x49_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x49_Reserved_3_0_OFFSET                         0
+#define D0F0x98_x49_Reserved_3_0_WIDTH                          4
+#define D0F0x98_x49_Reserved_3_0_MASK                           0xf
+#define D0F0x98_x49_Reserved_23_12_OFFSET                       12
+#define D0F0x98_x49_Reserved_23_12_WIDTH                        12
+#define D0F0x98_x49_Reserved_23_12_MASK                         0xfff000
+#define D0F0x98_x49_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x49_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x49_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x49_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x49_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x49_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x49_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x49_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x49_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x49_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x49_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x49_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x49_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x49_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x49_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x49_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x49_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x49
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                            :8 ; ///<
+    UINT32                                           Reserved_23_12:12; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x49_STRUCT;
+
+// **** D0F0x98_x4A Register Definition ****
+// Address
+#define D0F0x98_x4A_ADDRESS                                     0x4a
+
+// Type
+#define D0F0x98_x4A_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x4A_Reserved_3_0_OFFSET                         0
+#define D0F0x98_x4A_Reserved_3_0_WIDTH                          4
+#define D0F0x98_x4A_Reserved_3_0_MASK                           0xf
+#define D0F0x98_x4A_Reserved_23_12_OFFSET                       12
+#define D0F0x98_x4A_Reserved_23_12_WIDTH                        12
+#define D0F0x98_x4A_Reserved_23_12_MASK                         0xfff000
+#define D0F0x98_x4A_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x4A_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x4A_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x4A_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x4A_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x4A_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x4A_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x4A_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x4A_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x4A_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x4A_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x4A_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x4A_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x4A_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x4A_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x4A_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x4A_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x4A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                            :8 ; ///<
+    UINT32                                           Reserved_23_12:12; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x4A_STRUCT;
+
+
+// **** D0F0xE4_WRAP_0080 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0080_ADDRESS                               0x80
+
+// Type
+#define D0F0xE4_WRAP_0080_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET             0
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH              4
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK               0xf
+#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET                  4
+#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH                   28
+#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK                    0xfffffff0
+
+/// D0F0xE4_WRAP_0080
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       StrapBifLinkConfig:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0080_STRUCT;
+
+// **** D0F0xE4_WRAP_0800 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0800_ADDRESS                               0x800
+
+// Type
+#define D0F0xE4_WRAP_0800_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET                   0
+#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH                    1
+#define D0F0xE4_WRAP_0800_HoldTraining_MASK                     0x1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_WRAP_0800
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HoldTraining:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0800_STRUCT;
+
+// **** D0F0xE4_WRAP_0803 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0803_ADDRESS                               0x803
+
+// Type
+#define D0F0xE4_WRAP_0803_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0803
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0803_STRUCT;
+
+// **** D0F0xE4_WRAP_0903 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0903_ADDRESS                               0x903
+
+// Type
+#define D0F0xE4_WRAP_0903_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0903
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0903_STRUCT;
+
+
+/// D0F0xE4_WRAP_8011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      TxclkDynGateLatency:6 ; ///<
+    UINT32                                        TxclkPermGateEven:1 ; ///<
+    UINT32                                       TxclkDynGateEnable:1 ; ///<
+    UINT32                                            TxclkPermStop:1 ; ///<
+    UINT32                                      TxclkRegsGateEnable:1 ; ///<
+    UINT32                                     TxclkRegsGateLatency:6 ; ///<
+    UINT32                                         RcvrDetClkEnable:1 ; ///<
+    UINT32                                     TxclkPermGateLatency:6 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                      TxclkLcntGateEnable:1 ; ///<
+    UINT32                                           Reserved_30_25:6 ; ///<
+    UINT32                                            StrapBifValid:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex501_STRUCT;
+
+// **** D0F0xE4_WRAP_8012 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8012_ADDRESS                               0x8012
+
+// Type
+#define D0F0xE4_WRAP_8012_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET           0
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK             0x3f
+#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET            7
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK              0x80
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET         8
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK           0x3f00
+#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET         16
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK           0x3f0000
+#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET          23
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH           1
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK            0x800000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET       24
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH        6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK         0x3f000000
+#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     Pif1xIdleGateLatency:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                      Pif1xIdleGateEnable:1 ; ///<
+    UINT32                                   Pif1xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                   Pif2p5xIdleGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    Pif2p5xIdleGateEnable:1 ; ///<
+    UINT32                                 Pif2p5xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8012_STRUCT;
+
+
+// **** D0F0xE4_WRAP_8021 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8021_ADDRESS                               0x8021
+
+// Type
+#define D0F0xE4_WRAP_8021_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8021_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8021_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8021_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8021_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8021_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8021_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8021_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8021_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8021_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8021_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8021
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8021_STRUCT;
+
+// **** D0F0xE4_WRAP_8022 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8022_ADDRESS                               0x8022
+
+// Type
+#define D0F0xE4_WRAP_8022_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8022_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8022_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8022_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8022_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8022_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8022_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8022_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8022_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8022_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8022_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8022
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8022_STRUCT;
+
+// **** D0F0xE4_WRAP_8023 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8023_ADDRESS                               0x8023
+
+// Type
+#define D0F0xE4_WRAP_8023_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET                     0
+#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH                      16
+#define D0F0xE4_WRAP_8023_LaneEnable_MASK                       0xffff
+#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_WRAP_8023
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               LaneEnable:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8023_STRUCT;
+
+// **** D0F0xE4_WRAP_8025 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8025_ADDRESS                               0x8025
+
+// Type
+#define D0F0xE4_WRAP_8025_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET                    0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK                      0x7
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET                    3
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK                      0x18
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET                   5
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK                     0x20
+#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET                   6
+#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH                    2
+#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK                     0xc0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET                    8
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK                      0x700
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET                    11
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK                      0x1800
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET                   13
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK                     0x2000
+#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET                    16
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK                      0x70000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET                    19
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK                      0x180000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET                   21
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK                     0x200000
+#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET                 22
+#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK                   0xc00000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET                    24
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK                      0x7000000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET                    27
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK                      0x18000000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET                   29
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK                     0x20000000
+#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8025
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LMTxPhyCmd0:3 ; ///<
+    UINT32                                              LMRxPhyCmd0:2 ; ///<
+    UINT32                                             LMLinkSpeed0:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                              LMTxPhyCmd1:3 ; ///<
+    UINT32                                              LMRxPhyCmd1:2 ; ///<
+    UINT32                                             LMLinkSpeed1:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                              LMTxPhyCmd2:3 ; ///<
+    UINT32                                              LMRxPhyCmd2:2 ; ///<
+    UINT32                                             LMLinkSpeed2:1 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              LMTxPhyCmd3:3 ; ///<
+    UINT32                                              LMRxPhyCmd3:2 ; ///<
+    UINT32                                             LMLinkSpeed3:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8025_STRUCT;
+
+// **** D0F0xE4_WRAP_8031 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8031_ADDRESS                               0x8031
+
+// Type
+#define D0F0xE4_WRAP_8031_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET                 0
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH                  10
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK                   0x3ff
+#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET                 10
+#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH                  6
+#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK                   0xfc00
+#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET                     16
+#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH                      1
+#define D0F0xE4_WRAP_8031_LnCntValid_MASK                       0x10000
+#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET                 17
+#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH                  15
+#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xE4_WRAP_8031
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LnCntBandwidth:10; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                               LnCntValid:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8031_STRUCT;
+
+/// D0F0xE4_WRAP_8040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  OwnPhyA:1 ; ///<
+    UINT32                                                  OwnPhyB:1 ; ///<
+    UINT32                                                  OwnPhyC:1 ; ///<
+    UINT32                                                  OwnPhyD:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                           DigaPwrdnValue:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           DigbPwrdnValue:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                  CntPhyA:1 ; ///<
+    UINT32                                                  CntPhyB:1 ; ///<
+    UINT32                                                  CntPhyC:1 ; ///<
+    UINT32                                                  CntPhyD:1 ; ///<
+    UINT32                                                  CntDigA:1 ; ///<
+    UINT32                                                  CntDigB:1 ; ///<
+    UINT32                                              ChangeLnSpd:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex502_STRUCT;
+
+// **** D0F0xE4_WRAP_8060 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8060_ADDRESS                               0x8060
+
+// Type
+#define D0F0xE4_WRAP_8060_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET                    0
+#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH                     1
+#define D0F0xE4_WRAP_8060_Reconfigure_MASK                      0x1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET                  2
+#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH                   1
+#define D0F0xE4_WRAP_8060_ResetComplete_MASK                    0x4
+#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET                  3
+#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH                   13
+#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK                    0xfff8
+#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET                 18
+#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH                  14
+#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xE4_WRAP_8060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reconfigure:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                            ResetComplete:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                      :1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8060_STRUCT;
+
+// **** D0F0xE4_WRAP_8062 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8062_ADDRESS                               0x8062
+
+// Type
+#define D0F0xE4_WRAP_8062_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET                  0
+#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH                   1
+#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK                    0x1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET                    2
+#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH                     3
+#define D0F0xE4_WRAP_8062_ResetPeriod_MASK                      0x1c
+#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET                   5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH                    5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK                     0x3e0
+#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET                    10
+#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH                     1
+#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK                      0x400
+#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET                 11
+#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH                  1
+#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK                   0x800
+#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET                 12
+#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH                  20
+#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK                   0xfffff000
+
+/// D0F0xE4_WRAP_8062
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ReconfigureEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              ResetPeriod:3 ; ///<
+    UINT32                                             Reserved_9_5:5 ; ///<
+    UINT32                                              BlockOnIdle:1 ; ///<
+    UINT32                                           ConfigXferMode:1 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8062_STRUCT;
+
+// **** D0F0xE4_WRAP_80F0 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F0_ADDRESS                               0x80f0
+
+// Type
+#define D0F0xE4_WRAP_80F0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET                   0
+#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH                    32
+#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK                     0xffffffff
+
+/// D0F0xE4_WRAP_80F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             MicroSeconds:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F0_STRUCT;
+
+// **** D0F0xE4_WRAP_80F1 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F1_ADDRESS                               0x80f1
+
+// Type
+#define D0F0xE4_WRAP_80F1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET                      0
+#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH                       8
+#define D0F0xE4_WRAP_80F1_ClockRate_MASK                        0xff
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET                  8
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH                   24
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK                    0xffffff00
+
+/// D0F0xE4_WRAP_80F1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ClockRate:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F1_STRUCT;
+
+// **** D0F0xE4_PIF_0010 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0010_ADDRESS                                0x10
+
+// Type
+#define D0F0xE4_PIF_0010_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET                    0
+#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH                     4
+#define D0F0xE4_PIF_0010_Reserved_3_0_MASK                      0xf
+#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET                  4
+#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH                   1
+#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK                    0x10
+#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET                    5
+#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH                     1
+#define D0F0xE4_PIF_0010_Reserved_5_5_MASK                      0x20
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET           6
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH            1
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK             0x40
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET               7
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH                1
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK                 0x80
+#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET                   8
+#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH                    9
+#define D0F0xE4_PIF_0010_Reserved_16_8_MASK                     0x1ff00
+#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET                     17
+#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK                       0xe0000
+#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET                  23
+#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH                   9
+#define D0F0xE4_PIF_0010_Reserved_31_23_MASK                    0xff800000
+
+/// D0F0xE4_PIF_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                           EiDetCycleMode:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                    RxDetectFifoResetMode:1 ; ///<
+    UINT32                                        RxDetectTxPwrMode:1 ; ///<
+    UINT32                                            Reserved_16_8:9 ; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+    UINT32                                           :3 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0010_STRUCT;
+
+// **** D0F0xE4_PIF_0011 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0011_ADDRESS                                0x11
+
+// Type
+#define D0F0xE4_PIF_0011_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0011_X2Lane10_OFFSET                        0
+#define D0F0xE4_PIF_0011_X2Lane10_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane10_MASK                          0x1
+#define D0F0xE4_PIF_0011_X2Lane32_OFFSET                        1
+#define D0F0xE4_PIF_0011_X2Lane32_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane32_MASK                          0x2
+#define D0F0xE4_PIF_0011_X2Lane54_OFFSET                        2
+#define D0F0xE4_PIF_0011_X2Lane54_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane54_MASK                          0x4
+#define D0F0xE4_PIF_0011_X2Lane76_OFFSET                        3
+#define D0F0xE4_PIF_0011_X2Lane76_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane76_MASK                          0x8
+#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET                    4
+#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH                     4
+#define D0F0xE4_PIF_0011_Reserved_7_4_MASK                      0xf0
+#define D0F0xE4_PIF_0011_X4Lane30_OFFSET                        8
+#define D0F0xE4_PIF_0011_X4Lane30_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane30_MASK                          0x100
+#define D0F0xE4_PIF_0011_X4Lane74_OFFSET                        9
+#define D0F0xE4_PIF_0011_X4Lane74_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane74_MASK                          0x200
+#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET                  10
+#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH                   2
+#define D0F0xE4_PIF_0011_Reserved_11_10_MASK                    0xc00
+#define D0F0xE4_PIF_0011_X4Lane52_OFFSET                        12
+#define D0F0xE4_PIF_0011_X4Lane52_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane52_MASK                          0x1000
+#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0011_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0011_X8Lane70_OFFSET                        16
+#define D0F0xE4_PIF_0011_X8Lane70_WIDTH                         1
+#define D0F0xE4_PIF_0011_X8Lane70_MASK                          0x10000
+#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET                  17
+#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH                   8
+#define D0F0xE4_PIF_0011_Reserved_24_17_MASK                    0x1fe0000
+#define D0F0xE4_PIF_0011_MultiPif_OFFSET                        25
+#define D0F0xE4_PIF_0011_MultiPif_WIDTH                         1
+#define D0F0xE4_PIF_0011_MultiPif_MASK                          0x2000000
+#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET                  26
+#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH                   6
+#define D0F0xE4_PIF_0011_Reserved_31_26_MASK                    0xfc000000
+
+/// D0F0xE4_PIF_0011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 X2Lane10:1 ; ///<
+    UINT32                                                 X2Lane32:1 ; ///<
+    UINT32                                                 X2Lane54:1 ; ///<
+    UINT32                                                 X2Lane76:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                 X4Lane30:1 ; ///<
+    UINT32                                                 X4Lane74:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                                                 X4Lane52:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                 X8Lane70:1 ; ///<
+    UINT32                                           Reserved_24_17:8 ; ///<
+    UINT32                                                 MultiPif:1 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0011_STRUCT;
+
+// **** D0F0xE4_PIF_0012 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0012_ADDRESS                                0x12
+
+// Type
+#define D0F0xE4_PIF_0012_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0012_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0012_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0012_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0012_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0012_STRUCT;
+
+// **** D0F0xE4_PIF_0013 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0013_ADDRESS                                0x13
+
+// Type
+#define D0F0xE4_PIF_0013_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0013_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0013_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0013_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0013_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0013_STRUCT;
+
+// **** D0F0xE4_PIF_0015 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0015_ADDRESS                                0x15
+
+// Type
+#define D0F0xE4_PIF_0015_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET                   0
+#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK                     0x1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET                   1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK                     0x2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET                   2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK                     0x4
+#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET                   3
+#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK                     0x8
+#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET                   4
+#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK                     0x10
+#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET                   5
+#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK                     0x20
+#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET                   6
+#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK                     0x40
+#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET                   7
+#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK                     0x80
+#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PIF_0015_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PIF_0015
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            TxPhyStatus00:1 ; ///<
+    UINT32                                            TxPhyStatus01:1 ; ///<
+    UINT32                                            TxPhyStatus02:1 ; ///<
+    UINT32                                            TxPhyStatus03:1 ; ///<
+    UINT32                                            TxPhyStatus04:1 ; ///<
+    UINT32                                            TxPhyStatus05:1 ; ///<
+    UINT32                                            TxPhyStatus06:1 ; ///<
+    UINT32                                            TxPhyStatus07:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0015_STRUCT;
+
+// **** D0F0xE4_CORE_0002 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0002_ADDRESS                               0x2
+
+// Type
+#define D0F0xE4_CORE_0002_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET                     0
+#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH                      1
+#define D0F0xE4_CORE_0002_HwDebug_0__MASK                       0x1
+#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_CORE_0002_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_CORE_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               HwDebug_0_:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0002_STRUCT;
+
+
+
+// **** D0F0xE4_CORE_001C Register Definition ****
+// Address
+#define D0F0xE4_CORE_001C_ADDRESS                               0x1c
+
+// Type
+#define D0F0xE4_CORE_001C_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET              0
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH               1
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK                0x1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET                  1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK                    0x3e
+#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET                  6
+#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK                    0x7c0
+#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET                 11
+#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH                  21
+#define D0F0xE4_CORE_001C_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xE4_CORE_001C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxArbRoundRobinEn:1 ; ///<
+    UINT32                                            TxArbSlvLimit:5 ; ///<
+    UINT32                                            TxArbMstLimit:5 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_001C_STRUCT;
+
+// **** D0F0xE4_CORE_0040 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0040_ADDRESS                               0x40
+
+// Type
+#define D0F0xE4_CORE_0040_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET                  0
+#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH                   14
+#define D0F0xE4_CORE_0040_Reserved_13_0_MASK                    0x3fff
+#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET                  14
+#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH                   2
+#define D0F0xE4_CORE_0040_PElecIdleMode_MASK                    0xc000
+#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_CORE_0040_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_CORE_0040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_13_0:14; ///<
+    UINT32                                            PElecIdleMode:2 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0040_STRUCT;
+
+// **** D0F0xE4_CORE_00B0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00B0_ADDRESS                               0xb0
+
+// Type
+#define D0F0xE4_CORE_00B0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET                   0
+#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK                     0x3
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET                   2
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK                     0x4
+#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET                   3
+#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK                     0x18
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET                   5
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK                     0x20
+#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_CORE_00B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                             StrapF0MsiEn:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                             StrapF0AerEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00B0_STRUCT;
+
+
+// **** D0F0xE4_CORE_00C1 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00C1_ADDRESS                               0xc1
+
+// Type
+#define D0F0xE4_CORE_00C1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET   0
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH    1
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK     0x1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET            1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH             1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK              0x2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET                  2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH                   30
+#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xE4_CORE_00C1
+typedef union {
+  struct {                                                              ///<
+    UINT32                             StrapLinkBwNotificationCapEn:1 ; ///<
+    UINT32                                      StrapGen2Compliance:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00C1_STRUCT;
+
+// **** D0F0xE4_PHY_0009 Register Definition ****
+// Address
+#define D0F0xE4_PHY_0009_ADDRESS                                0x9
+
+// Type
+#define D0F0xE4_PHY_0009_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_0009_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_0009_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_0009_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_0009_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_0009_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_0009_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_0009_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_0009_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_0009_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_0009
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_0009_STRUCT;
+
+// **** D0F0xE4_PHY_000A Register Definition ****
+// Address
+#define D0F0xE4_PHY_000A_ADDRESS                                0xa
+
+// Type
+#define D0F0xE4_PHY_000A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_000A_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_000A_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_000A_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_000A_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_000A_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_000A_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_000A_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_000A_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_000A_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_000A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000A_STRUCT;
+
+// **** D0F0xE4_PHY_000B Register Definition ****
+// Address
+#define D0F0xE4_PHY_000B_ADDRESS                                0xb
+
+// Type
+#define D0F0xE4_PHY_000B_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET                      0
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK                        0x1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET                      1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK                        0x2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET                   2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH                    1
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK                     0x4
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET                    3
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK                      0x8
+#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET                    4
+#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK                      0x10
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET               5
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH                1
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK                 0x20
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET                    6
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK                      0x40
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET              7
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH               1
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK                0x80
+#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET                      8
+#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK                        0x100
+#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET                   9
+#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH                    5
+#define D0F0xE4_PHY_000B_Reserved_13_9_MASK                     0x3e00
+#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET                    14
+#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK                      0x4000
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET                  15
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH                   1
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK                    0x8000
+#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_000B_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_000B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               TxPwrSbiEn:1 ; ///<
+    UINT32                                               RxPwrSbiEn:1 ; ///<
+    UINT32                                            PcieModeSbiEn:1 ; ///<
+    UINT32                                             FreqDivSbiEn:1 ; ///<
+    UINT32                                             DllLockSbiEn:1 ; ///<
+    UINT32                                        OffsetCancelSbiEn:1 ; ///<
+    UINT32                                             SkipBitSbiEn:1 ; ///<
+    UINT32                                       IncoherentClkSbiEn:1 ; ///<
+    UINT32                                               EiDetSbiEn:1 ; ///<
+    UINT32                                            Reserved_13_9:5 ; ///<
+    UINT32                                             MargPktSbiEn:1 ; ///<
+    UINT32                                           PllCmpPktSbiEn:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000B_STRUCT;
+
+// **** D0F0xE4_PHY_2000 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2000_ADDRESS                                0x2000
+
+// Type
+#define D0F0xE4_PHY_2000_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET                  0
+#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH                   3
+#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK                    0x7
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET               3
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH                1
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK                 0x8
+#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET                   4
+#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH                    28
+#define D0F0xE4_PHY_2000_Reserved_31_4_MASK                     0xfffffff0
+
+/// D0F0xE4_PHY_2000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PllPowerDownEn:3 ; ///<
+    UINT32                                        PllAutoPwrDownDis:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2000_STRUCT;
+
+
+// **** D0F0xE4_PHY_2005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2005_ADDRESS                                0x2005
+
+// Type
+#define D0F0xE4_PHY_2005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET                      0
+#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH                       4
+#define D0F0xE4_PHY_2005_PllClkFreq_MASK                        0xf
+#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET                    4
+#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH                     5
+#define D0F0xE4_PHY_2005_Reserved_8_4_MASK                      0x1f0
+#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET                   9
+#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH                    2
+#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK                     0x600
+#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET                  11
+#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH                   2
+#define D0F0xE4_PHY_2005_Reserved_12_11_MASK                    0x1800
+#define D0F0xE4_PHY_2005_PllMode_OFFSET                         13
+#define D0F0xE4_PHY_2005_PllMode_WIDTH                          2
+#define D0F0xE4_PHY_2005_PllMode_MASK                           0x6000
+#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET                  15
+#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH                   17
+#define D0F0xE4_PHY_2005_Reserved_31_15_MASK                    0xffff8000
+
+/// D0F0xE4_PHY_2005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PllClkFreq:4 ; ///<
+    UINT32                                             Reserved_8_4:5 ; ///<
+    UINT32                                            PllClkFreqExt:2 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                  PllMode:2 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2005_STRUCT;
+
+// **** D0F0xE4_PHY_2008 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2008_ADDRESS                                0x2008
+
+// Type
+#define D0F0xE4_PHY_2008_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET                0
+#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH                 1
+#define D0F0xE4_PHY_2008_PllControlUpdate_MASK                  0x1
+#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET                   1
+#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH                    22
+#define D0F0xE4_PHY_2008_Reserved_22_1_MASK                     0x7ffffe
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET              23
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH               3
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK                0x3800000
+#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET                  26
+#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH                   3
+#define D0F0xE4_PHY_2008_Reserved_28_26_MASK                    0x1c000000
+#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET                      29
+#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH                       1
+#define D0F0xE4_PHY_2008_VdDetectEn_MASK                        0x20000000
+#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_2008_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_2008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PllControlUpdate:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                       MeasCycCntVal_2_0_:3 ; ///<
+    UINT32                                           Reserved_28_26:3 ; ///<
+    UINT32                                               VdDetectEn:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2008_STRUCT;
+
+// **** D0F0xE4_PHY_4001 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4001_ADDRESS                                0x4001
+
+// Type
+#define D0F0xE4_PHY_4001_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET                   0
+#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH                    15
+#define D0F0xE4_PHY_4001_Reserved_14_0_MASK                     0x7fff
+#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET                  15
+#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH                   1
+#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK                    0x8000
+#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_4001_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_4001
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                           ForceDccRecalc:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4001_STRUCT;
+
+// **** D0F0xE4_PHY_4002 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4002_ADDRESS                                0x4002
+
+// Type
+#define D0F0xE4_PHY_4002_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET                    0
+#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH                     3
+#define D0F0xE4_PHY_4002_Reserved_2_0_MASK                      0x7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET              3
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH               1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK                0x8
+#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET                  4
+#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH                   3
+#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK                    0x70
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET                7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH                 1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK                  0x80
+#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET                   8
+#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH                    6
+#define D0F0xE4_PHY_4002_Reserved_13_8_MASK                     0x3f00
+#define D0F0xE4_PHY_4002_LfcMin_OFFSET                          14
+#define D0F0xE4_PHY_4002_LfcMin_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMin_MASK                            0x3fc000
+#define D0F0xE4_PHY_4002_LfcMax_OFFSET                          22
+#define D0F0xE4_PHY_4002_LfcMax_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMax_MASK                            0x3fc00000
+#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_4002_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_4002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                       SamClkPiOffsetSign:1 ; ///<
+    UINT32                                           SamClkPiOffset:3 ; ///<
+    UINT32                                         SamClkPiOffsetEn:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                                   LfcMin:8 ; ///<
+    UINT32                                                   LfcMax:8 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4002_STRUCT;
+
+// **** D0F0xE4_PHY_4005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4005_ADDRESS                                0x4005
+
+// Type
+#define D0F0xE4_PHY_4005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET                    0
+#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH                     9
+#define D0F0xE4_PHY_4005_Reserved_8_0_MASK                      0x1ff
+#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET                   9
+#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH                    1
+#define D0F0xE4_PHY_4005_JitterInjHold_MASK                     0x200
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET                 10
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH                  6
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK                   0xfc00
+#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET                  16
+#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH                   7
+#define D0F0xE4_PHY_4005_Reserved_22_16_MASK                    0x7f0000
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET                  23
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH                   6
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK                    0x1f800000
+#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET                    29
+#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH                     1
+#define D0F0xE4_PHY_4005_JitterInjDir_MASK                      0x20000000
+#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET                     30
+#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH                      1
+#define D0F0xE4_PHY_4005_JitterInjEn_MASK                       0x40000000
+#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET                  31
+#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH                   1
+#define D0F0xE4_PHY_4005_Reserved_31_31_MASK                    0x80000000
+
+/// D0F0xE4_PHY_4005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                            JitterInjHold:1 ; ///<
+    UINT32                                          JitterInjOffCnt:6 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                           JitterInjOnCnt:6 ; ///<
+    UINT32                                             JitterInjDir:1 ; ///<
+    UINT32                                              JitterInjEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4005_STRUCT;
+
+// **** D0F0xE4_PHY_4006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4006_ADDRESS                                0x4006
+
+// Type
+#define D0F0xE4_PHY_4006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET                    0
+#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH                     5
+#define D0F0xE4_PHY_4006_Reserved_4_0_MASK                      0x1f
+#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET                      5
+#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH                       2
+#define D0F0xE4_PHY_4006_DfeVoltage_MASK                        0x60
+#define D0F0xE4_PHY_4006_DfeEn_OFFSET                           7
+#define D0F0xE4_PHY_4006_DfeEn_WIDTH                            1
+#define D0F0xE4_PHY_4006_DfeEn_MASK                             0x80
+#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PHY_4006_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PHY_4006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                               DfeVoltage:2 ; ///<
+    UINT32                                                    DfeEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4006_STRUCT;
+
+// **** D0F0xE4_PHY_400A Register Definition ****
+// Address
+#define D0F0xE4_PHY_400A_ADDRESS                                0x400a
+
+// Type
+#define D0F0xE4_PHY_400A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET                 0
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH                  1
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK                   0x1
+#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET                    1
+#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH                     3
+#define D0F0xE4_PHY_400A_Reserved_3_1_MASK                      0xe
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET                4
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH                 1
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK                  0x10
+#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET                    5
+#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH                     2
+#define D0F0xE4_PHY_400A_Reserved_6_5_MASK                      0x60
+#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET                    7
+#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH                     1
+#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK                      0x80
+#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET                   8
+#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH                    5
+#define D0F0xE4_PHY_400A_Reserved_12_8_MASK                     0x1f00
+#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET                  13
+#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH                   2
+#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK                    0x6000
+#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET                  15
+#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH                   2
+#define D0F0xE4_PHY_400A_Reserved_16_15_MASK                    0x18000
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET               17
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH                1
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK                 0x20000
+#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET                  18
+#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH                   11
+#define D0F0xE4_PHY_400A_Reserved_28_18_MASK                    0x1ffc0000
+#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET                     29
+#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK                       0xe0000000
+
+/// D0F0xE4_PHY_400A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          EnCoreLoopFirst:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                         LockDetOnLs2Exit:1 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                             BiasDisInLs2:1 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           AnalogWaitTime:2 ; ///<
+    UINT32                                           Reserved_16_15:2 ; ///<
+    UINT32                                        DllLockFastModeEn:1 ; ///<
+    UINT32                                           Reserved_28_18:11; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_400A_STRUCT;
+
+// **** D0F0xE4_PHY_6005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6005_ADDRESS                                0x6005
+
+// Type
+#define D0F0xE4_PHY_6005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET                   0
+#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH                    29
+#define D0F0xE4_PHY_6005_Reserved_28_0_MASK                     0x1fffffff
+#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET                       29
+#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH                        1
+#define D0F0xE4_PHY_6005_IsOwnMstr_MASK                         0x20000000
+#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET                  30
+#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH                   1
+#define D0F0xE4_PHY_6005_Reserved_30_30_MASK                    0x40000000
+#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET                    31
+#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH                     1
+#define D0F0xE4_PHY_6005_GangedModeEn_MASK                      0x80000000
+
+/// D0F0xE4_PHY_6005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_28_0:29; ///<
+    UINT32                                                IsOwnMstr:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             GangedModeEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6005_STRUCT;
+
+// **** D18F2x09C_x0000_0000 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0000_ADDRESS                            0x0
+
+// Type
+#define D18F2x09C_x0000_0000_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0000_CkeDrvStren_OFFSET                 0
+#define D18F2x09C_x0000_0000_CkeDrvStren_WIDTH                  3
+#define D18F2x09C_x0000_0000_CkeDrvStren_MASK                   0x7
+#define D18F2x09C_x0000_0000_Reserved_3_3_OFFSET                3
+#define D18F2x09C_x0000_0000_Reserved_3_3_WIDTH                 1
+#define D18F2x09C_x0000_0000_Reserved_3_3_MASK                  0x8
+#define D18F2x09C_x0000_0000_CsOdtDrvStren_OFFSET               4
+#define D18F2x09C_x0000_0000_CsOdtDrvStren_WIDTH                3
+#define D18F2x09C_x0000_0000_CsOdtDrvStren_MASK                 0x70
+#define D18F2x09C_x0000_0000_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_0000_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_0000_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_0000_AddrCmdDrvStren_OFFSET             8
+#define D18F2x09C_x0000_0000_AddrCmdDrvStren_WIDTH              3
+#define D18F2x09C_x0000_0000_AddrCmdDrvStren_MASK               0x700
+#define D18F2x09C_x0000_0000_Reserved_11_11_OFFSET              11
+#define D18F2x09C_x0000_0000_Reserved_11_11_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_11_11_MASK                0x800
+#define D18F2x09C_x0000_0000_ClkDrvStren_OFFSET                 12
+#define D18F2x09C_x0000_0000_ClkDrvStren_WIDTH                  3
+#define D18F2x09C_x0000_0000_ClkDrvStren_MASK                   0x7000
+#define D18F2x09C_x0000_0000_Reserved_15_15_OFFSET              15
+#define D18F2x09C_x0000_0000_Reserved_15_15_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_15_15_MASK                0x8000
+#define D18F2x09C_x0000_0000_DataDrvStren_OFFSET                16
+#define D18F2x09C_x0000_0000_DataDrvStren_WIDTH                 3
+#define D18F2x09C_x0000_0000_DataDrvStren_MASK                  0x70000
+#define D18F2x09C_x0000_0000_Reserved_19_19_OFFSET              19
+#define D18F2x09C_x0000_0000_Reserved_19_19_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_19_19_MASK                0x80000
+#define D18F2x09C_x0000_0000_DqsDrvStren_OFFSET                 20
+#define D18F2x09C_x0000_0000_DqsDrvStren_WIDTH                  3
+#define D18F2x09C_x0000_0000_DqsDrvStren_MASK                   0x700000
+#define D18F2x09C_x0000_0000_Reserved_27_23_OFFSET              23
+#define D18F2x09C_x0000_0000_Reserved_27_23_WIDTH               5
+#define D18F2x09C_x0000_0000_Reserved_27_23_MASK                0xf800000
+#define D18F2x09C_x0000_0000_ProcOdt_OFFSET                     28
+#define D18F2x09C_x0000_0000_ProcOdt_WIDTH                      3
+#define D18F2x09C_x0000_0000_ProcOdt_MASK                       0x70000000
+#define D18F2x09C_x0000_0000_Reserved_31_31_OFFSET              31
+#define D18F2x09C_x0000_0000_Reserved_31_31_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_31_31_MASK                0x80000000
+
+/// D18F2x09C_x0000_0000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0000_STRUCT;
+
+// **** D18F2x09C_x0000_0001 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0001_ADDRESS                            0x1
+
+// Type
+#define D18F2x09C_x0000_0001_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_MASK           0xe0
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_OFFSET          8
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_MASK            0x1f00
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_OFFSET         13
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_MASK           0xe000
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_OFFSET          16
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_MASK            0x1f0000
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_OFFSET         21
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_MASK           0xe00000
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_OFFSET          24
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_MASK            0x1f000000
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_OFFSET         29
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_MASK           0xe0000000
+
+/// D18F2x09C_x0000_0001
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDatFineDly_Byte0:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte0:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte1:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte1:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte2:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte2:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte3:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0001_STRUCT;
+
+// **** D18F2x09C_x0000_0002 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0002_ADDRESS                            0x2
+
+// Type
+#define D18F2x09C_x0000_0002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_MASK           0xe0
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_OFFSET          8
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_MASK            0x1f00
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_OFFSET         13
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_MASK           0xe000
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_OFFSET          16
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_MASK            0x1f0000
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_OFFSET         21
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_MASK           0xe00000
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_OFFSET          24
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_MASK            0x1f000000
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_OFFSET         29
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_MASK           0xe0000000
+
+/// D18F2x09C_x0000_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDatFineDly_Byte4:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte4:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte5:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte5:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte6:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte6:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte7:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte7:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0002_STRUCT;
+
+// **** D18F2x09C_x0000_0004 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0004_ADDRESS                            0x4
+
+// Type
+#define D18F2x09C_x0000_0004_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0004_CkeFineDelay_OFFSET                0
+#define D18F2x09C_x0000_0004_CkeFineDelay_WIDTH                 5
+#define D18F2x09C_x0000_0004_CkeFineDelay_MASK                  0x1f
+#define D18F2x09C_x0000_0004_CkeSetup_OFFSET                    5
+#define D18F2x09C_x0000_0004_CkeSetup_WIDTH                     1
+#define D18F2x09C_x0000_0004_CkeSetup_MASK                      0x20
+#define D18F2x09C_x0000_0004_Reserved_7_6_OFFSET                6
+#define D18F2x09C_x0000_0004_Reserved_7_6_WIDTH                 2
+#define D18F2x09C_x0000_0004_Reserved_7_6_MASK                  0xc0
+#define D18F2x09C_x0000_0004_CsOdtFineDelay_OFFSET              8
+#define D18F2x09C_x0000_0004_CsOdtFineDelay_WIDTH               5
+#define D18F2x09C_x0000_0004_CsOdtFineDelay_MASK                0x1f00
+#define D18F2x09C_x0000_0004_CsOdtSetup_OFFSET                  13
+#define D18F2x09C_x0000_0004_CsOdtSetup_WIDTH                   1
+#define D18F2x09C_x0000_0004_CsOdtSetup_MASK                    0x2000
+#define D18F2x09C_x0000_0004_Reserved_15_14_OFFSET              14
+#define D18F2x09C_x0000_0004_Reserved_15_14_WIDTH               2
+#define D18F2x09C_x0000_0004_Reserved_15_14_MASK                0xc000
+#define D18F2x09C_x0000_0004_AddrCmdFineDelay_OFFSET            16
+#define D18F2x09C_x0000_0004_AddrCmdFineDelay_WIDTH             5
+#define D18F2x09C_x0000_0004_AddrCmdFineDelay_MASK              0x1f0000
+#define D18F2x09C_x0000_0004_AddrCmdSetup_OFFSET                21
+#define D18F2x09C_x0000_0004_AddrCmdSetup_WIDTH                 1
+#define D18F2x09C_x0000_0004_AddrCmdSetup_MASK                  0x200000
+#define D18F2x09C_x0000_0004_Reserved_31_22_OFFSET              22
+#define D18F2x09C_x0000_0004_Reserved_31_22_WIDTH               10
+#define D18F2x09C_x0000_0004_Reserved_31_22_MASK                0xffc00000
+
+/// D18F2x09C_x0000_0004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0004_STRUCT;
+
+// **** D18F2x09C_x0000_0005 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0005_ADDRESS                            0x5
+
+// Type
+#define D18F2x09C_x0000_0005_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0005_Reserved_0_0_OFFSET                0
+#define D18F2x09C_x0000_0005_Reserved_0_0_WIDTH                 1
+#define D18F2x09C_x0000_0005_Reserved_0_0_MASK                  0x1
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_OFFSET             1
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_MASK               0x3e
+#define D18F2x09C_x0000_0005_Reserved_8_6_OFFSET                6
+#define D18F2x09C_x0000_0005_Reserved_8_6_WIDTH                 3
+#define D18F2x09C_x0000_0005_Reserved_8_6_MASK                  0x1c0
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_OFFSET             9
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_MASK               0x3e00
+#define D18F2x09C_x0000_0005_Reserved_16_14_OFFSET              14
+#define D18F2x09C_x0000_0005_Reserved_16_14_WIDTH               3
+#define D18F2x09C_x0000_0005_Reserved_16_14_MASK                0x1c000
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_OFFSET             17
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_MASK               0x3e0000
+#define D18F2x09C_x0000_0005_Reserved_24_22_OFFSET              22
+#define D18F2x09C_x0000_0005_Reserved_24_22_WIDTH               3
+#define D18F2x09C_x0000_0005_Reserved_24_22_MASK                0x1c00000
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_OFFSET             25
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_MASK               0x3e000000
+#define D18F2x09C_x0000_0005_Reserved_31_30_OFFSET              30
+#define D18F2x09C_x0000_0005_Reserved_31_30_WIDTH               2
+#define D18F2x09C_x0000_0005_Reserved_31_30_MASK                0xc0000000
+
+/// D18F2x09C_x0000_0005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                          RdDqsTime_Byte0:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                          RdDqsTime_Byte1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                          RdDqsTime_Byte2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                          RdDqsTime_Byte3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0005_STRUCT;
+
+// **** D18F2x09C_x0000_0006 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0006_ADDRESS                            0x6
+
+// Type
+#define D18F2x09C_x0000_0006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0006_Reserved_0_0_OFFSET                0
+#define D18F2x09C_x0000_0006_Reserved_0_0_WIDTH                 1
+#define D18F2x09C_x0000_0006_Reserved_0_0_MASK                  0x1
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_OFFSET             1
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_MASK               0x3e
+#define D18F2x09C_x0000_0006_Reserved_8_6_OFFSET                6
+#define D18F2x09C_x0000_0006_Reserved_8_6_WIDTH                 3
+#define D18F2x09C_x0000_0006_Reserved_8_6_MASK                  0x1c0
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_OFFSET             9
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_MASK               0x3e00
+#define D18F2x09C_x0000_0006_Reserved_16_14_OFFSET              14
+#define D18F2x09C_x0000_0006_Reserved_16_14_WIDTH               3
+#define D18F2x09C_x0000_0006_Reserved_16_14_MASK                0x1c000
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_OFFSET             17
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_MASK               0x3e0000
+#define D18F2x09C_x0000_0006_Reserved_24_22_OFFSET              22
+#define D18F2x09C_x0000_0006_Reserved_24_22_WIDTH               3
+#define D18F2x09C_x0000_0006_Reserved_24_22_MASK                0x1c00000
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_OFFSET             25
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_MASK               0x3e000000
+#define D18F2x09C_x0000_0006_Reserved_31_30_OFFSET              30
+#define D18F2x09C_x0000_0006_Reserved_31_30_WIDTH               2
+#define D18F2x09C_x0000_0006_Reserved_31_30_MASK                0xc0000000
+
+/// D18F2x09C_x0000_0006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                          RdDqsTime_Byte4:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                          RdDqsTime_Byte5:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                          RdDqsTime_Byte6:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                          RdDqsTime_Byte7:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0006_STRUCT;
+
+
+
+// **** D18F2x09C_x0000_000D Register Definition ****
+// Address
+#define D18F2x09C_x0000_000D_ADDRESS                            0xd
+
+// Type
+#define D18F2x09C_x0000_000D_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_OFFSET           0
+#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_WIDTH            4
+#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_MASK             0xf
+#define D18F2x09C_x0000_000D_TxCPUpdPeriod_OFFSET               4
+#define D18F2x09C_x0000_000D_TxCPUpdPeriod_WIDTH                3
+#define D18F2x09C_x0000_000D_TxCPUpdPeriod_MASK                 0x70
+#define D18F2x09C_x0000_000D_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_000D_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_000D_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_000D_TxDLLWakeupTime_OFFSET             8
+#define D18F2x09C_x0000_000D_TxDLLWakeupTime_WIDTH              2
+#define D18F2x09C_x0000_000D_TxDLLWakeupTime_MASK               0x300
+#define D18F2x09C_x0000_000D_Reserved_15_10_OFFSET              10
+#define D18F2x09C_x0000_000D_Reserved_15_10_WIDTH               6
+#define D18F2x09C_x0000_000D_Reserved_15_10_MASK                0xfc00
+#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_OFFSET           16
+#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_WIDTH            4
+#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_MASK             0xf0000
+#define D18F2x09C_x0000_000D_RxCPUpdPeriod_OFFSET               20
+#define D18F2x09C_x0000_000D_RxCPUpdPeriod_WIDTH                3
+#define D18F2x09C_x0000_000D_RxCPUpdPeriod_MASK                 0x700000
+#define D18F2x09C_x0000_000D_Reserved_23_23_OFFSET              23
+#define D18F2x09C_x0000_000D_Reserved_23_23_WIDTH               1
+#define D18F2x09C_x0000_000D_Reserved_23_23_MASK                0x800000
+#define D18F2x09C_x0000_000D_RxDLLWakeupTime_OFFSET             24
+#define D18F2x09C_x0000_000D_RxDLLWakeupTime_WIDTH              2
+#define D18F2x09C_x0000_000D_RxDLLWakeupTime_MASK               0x3000000
+#define D18F2x09C_x0000_000D_Reserved_31_26_OFFSET              26
+#define D18F2x09C_x0000_000D_Reserved_31_26_WIDTH               6
+#define D18F2x09C_x0000_000D_Reserved_31_26_MASK                0xfc000000
+
+/// D18F2x09C_x0000_000D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_000D_STRUCT;
+
+
+// **** D18F2x09C_x0000_0030 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0030_ADDRESS                            0x30
+
+// Type
+#define D18F2x09C_x0000_0030_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_WIDTH          3
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_MASK           0xe0
+#define D18F2x09C_x0000_0030_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0030_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0030_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_OFFSET          16
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_MASK            0x1f0000
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_OFFSET         21
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_WIDTH          3
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_MASK           0xe00000
+#define D18F2x09C_x0000_0030_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0030_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0030_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0030
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte0:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte0:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte1:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte1:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0030_STRUCT;
+
+// **** D18F2x09C_x0000_0031 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0031_ADDRESS                            0x31
+
+// Type
+#define D18F2x09C_x0000_0031_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_OFFSET          0
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_MASK            0x1f
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_OFFSET         5
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_WIDTH          3
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_MASK           0xe0
+#define D18F2x09C_x0000_0031_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0031_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0031_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_OFFSET          16
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_MASK            0x1f0000
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_OFFSET         21
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_WIDTH          3
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_MASK           0xe00000
+#define D18F2x09C_x0000_0031_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0031_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0031_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0031
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte2:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte2:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte3:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte3:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0031_STRUCT;
+
+// **** D18F2x09C_x0000_0033 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0033_ADDRESS                            0x33
+
+// Type
+#define D18F2x09C_x0000_0033_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_WIDTH          3
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_MASK           0xe0
+#define D18F2x09C_x0000_0033_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0033_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0033_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_OFFSET          16
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_MASK            0x1f0000
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_OFFSET         21
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_WIDTH          3
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_MASK           0xe00000
+#define D18F2x09C_x0000_0033_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0033_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0033_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0033
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte0:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte0:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte1:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte1:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0033_STRUCT;
+
+// **** D18F2x09C_x0000_0034 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0034_ADDRESS                            0x34
+
+// Type
+#define D18F2x09C_x0000_0034_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_OFFSET          0
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_MASK            0x1f
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_OFFSET         5
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_WIDTH          3
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_MASK           0xe0
+#define D18F2x09C_x0000_0034_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0034_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0034_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_OFFSET          16
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_MASK            0x1f0000
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_OFFSET         21
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_WIDTH          3
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_MASK           0xe00000
+#define D18F2x09C_x0000_0034_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0034_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0034_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0034
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte2:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte2:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte3:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte3:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0034_STRUCT;
+
+// **** D18F2x09C_x0000_0040 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0040_ADDRESS                            0x40
+
+// Type
+#define D18F2x09C_x0000_0040_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_WIDTH          3
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_MASK           0xe0
+#define D18F2x09C_x0000_0040_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0040_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0040_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_OFFSET          16
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_MASK            0x1f0000
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_OFFSET         21
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_WIDTH          3
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_MASK           0xe00000
+#define D18F2x09C_x0000_0040_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0040_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0040_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte4:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte4:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte5:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte5:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0040_STRUCT;
+
+// **** D18F2x09C_x0000_0041 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0041_ADDRESS                            0x41
+
+// Type
+#define D18F2x09C_x0000_0041_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_OFFSET          0
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_MASK            0x1f
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_OFFSET         5
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_WIDTH          3
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_MASK           0xe0
+#define D18F2x09C_x0000_0041_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0041_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0041_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_OFFSET          16
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_MASK            0x1f0000
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_OFFSET         21
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_WIDTH          3
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_MASK           0xe00000
+#define D18F2x09C_x0000_0041_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0041_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0041_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0041
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte6:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte6:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte7:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte7:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0041_STRUCT;
+
+// **** D18F2x09C_x0000_0043 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0043_ADDRESS                            0x43
+
+// Type
+#define D18F2x09C_x0000_0043_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_WIDTH          3
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_MASK           0xe0
+#define D18F2x09C_x0000_0043_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0043_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0043_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_OFFSET          16
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_MASK            0x1f0000
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_OFFSET         21
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_WIDTH          3
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_MASK           0xe00000
+#define D18F2x09C_x0000_0043_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0043_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0043_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0043
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte4:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte4:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte5:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte5:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0043_STRUCT;
+
+// **** D18F2x09C_x0000_0044 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0044_ADDRESS                            0x44
+
+// Type
+#define D18F2x09C_x0000_0044_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_OFFSET          0
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_MASK            0x1f
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_OFFSET         5
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_WIDTH          3
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_MASK           0xe0
+#define D18F2x09C_x0000_0044_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0044_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0044_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_OFFSET          16
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_MASK            0x1f0000
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_OFFSET         21
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_WIDTH          3
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_MASK           0xe00000
+#define D18F2x09C_x0000_0044_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0044_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0044_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0044
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte6:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte6:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte7:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte7:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0044_STRUCT;
+
+// **** D18F2x09C_x0000_0050 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0050_ADDRESS                            0x50
+
+// Type
+#define D18F2x09C_x0000_0050_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_MASK           0x60
+#define D18F2x09C_x0000_0050_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_0050_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_0050_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_OFFSET          8
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_MASK            0x1f00
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_OFFSET         13
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_MASK           0x6000
+#define D18F2x09C_x0000_0050_Reserved_15_15_OFFSET              15
+#define D18F2x09C_x0000_0050_Reserved_15_15_WIDTH               1
+#define D18F2x09C_x0000_0050_Reserved_15_15_MASK                0x8000
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_OFFSET          16
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_MASK            0x1f0000
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_OFFSET         21
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_MASK           0x600000
+#define D18F2x09C_x0000_0050_Reserved_23_23_OFFSET              23
+#define D18F2x09C_x0000_0050_Reserved_23_23_WIDTH               1
+#define D18F2x09C_x0000_0050_Reserved_23_23_MASK                0x800000
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_OFFSET          24
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_MASK            0x1f000000
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_OFFSET         29
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_MASK           0x60000000
+#define D18F2x09C_x0000_0050_Reserved_31_31_OFFSET              31
+#define D18F2x09C_x0000_0050_Reserved_31_31_WIDTH               1
+#define D18F2x09C_x0000_0050_Reserved_31_31_MASK                0x80000000
+
+/// D18F2x09C_x0000_0050
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PhRecFineDly_Byte0:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte0:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte1:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte1:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte2:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte2:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte3:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte3:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0050_STRUCT;
+
+// **** D18F2x09C_x0000_0051 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0051_ADDRESS                            0x51
+
+// Type
+#define D18F2x09C_x0000_0051_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_MASK           0x60
+#define D18F2x09C_x0000_0051_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_0051_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_0051_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_OFFSET          8
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_MASK            0x1f00
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_OFFSET         13
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_MASK           0x6000
+#define D18F2x09C_x0000_0051_Reserved_15_15_OFFSET              15
+#define D18F2x09C_x0000_0051_Reserved_15_15_WIDTH               1
+#define D18F2x09C_x0000_0051_Reserved_15_15_MASK                0x8000
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_OFFSET          16
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_MASK            0x1f0000
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_OFFSET         21
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_MASK           0x600000
+#define D18F2x09C_x0000_0051_Reserved_23_23_OFFSET              23
+#define D18F2x09C_x0000_0051_Reserved_23_23_WIDTH               1
+#define D18F2x09C_x0000_0051_Reserved_23_23_MASK                0x800000
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_OFFSET          24
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_MASK            0x1f000000
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_OFFSET         29
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_MASK           0x60000000
+#define D18F2x09C_x0000_0051_Reserved_31_31_OFFSET              31
+#define D18F2x09C_x0000_0051_Reserved_31_31_WIDTH               1
+#define D18F2x09C_x0000_0051_Reserved_31_31_MASK                0x80000000
+
+/// D18F2x09C_x0000_0051
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PhRecFineDly_Byte4:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte4:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte5:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte5:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte6:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte6:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte7:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte7:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0051_STRUCT;
+
+
+
+
+
+// **** D18F2x09C_x0D0F_0002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0002_ADDRESS                            0xd0f0002
+
+// Type
+#define D18F2x09C_x0D0F_0002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0002_STRUCT;
+
+// **** D18F2x09C_x0D0F_0006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0006_ADDRESS                            0xd0f0006
+
+// Type
+#define D18F2x09C_x0D0F_0006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0006_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0006_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0006_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0006_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0006_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0006_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0006_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0006_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0006_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0006_STRUCT;
+
+// **** D18F2x09C_x0D0F_000A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_000A_ADDRESS                            0xd0f000a
+
+// Type
+#define D18F2x09C_x0D0F_000A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_000A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_000A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_000A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_000A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_000A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_000A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_000A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_000A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_000A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_000A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_000A_STRUCT;
+
+// **** D18F2x09C_x0D0F_000F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_000F_ADDRESS                            0xd0f000f
+
+// Type
+#define D18F2x09C_x0D0F_000F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_000F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_000F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_000F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_000F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_000F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_000F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_000F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_000F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0010 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0010_ADDRESS                            0xd0f0010
+
+// Type
+#define D18F2x09C_x0D0F_0010_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0010_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0010_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0010_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0010_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0010_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0010_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0010_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0010_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0010_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0010_STRUCT;
+
+
+
+
+// **** D18F2x09C_x0D0F_0102 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0102_ADDRESS                            0xd0f0102
+
+// Type
+#define D18F2x09C_x0D0F_0102_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0102_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0102_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0102_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0102_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0102_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0102_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0102_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0102_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0102_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0102_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0102_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0102_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0102_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0102_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0102_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0102
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0102_STRUCT;
+
+// **** D18F2x09C_x0D0F_0106 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0106_ADDRESS                            0xd0f0106
+
+// Type
+#define D18F2x09C_x0D0F_0106_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0106_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0106_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0106_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0106_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0106_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0106_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0106_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0106_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0106_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0106
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0106_STRUCT;
+
+// **** D18F2x09C_x0D0F_010A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_010A_ADDRESS                            0xd0f010a
+
+// Type
+#define D18F2x09C_x0D0F_010A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_010A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_010A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_010A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_010A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_010A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_010A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_010A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_010A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_010A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_010A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_010A_STRUCT;
+
+// **** D18F2x09C_x0D0F_010F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_010F_ADDRESS                            0xd0f010f
+
+// Type
+#define D18F2x09C_x0D0F_010F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_010F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_010F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_010F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_010F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_010F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_010F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_010F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_010F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0110 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0110_ADDRESS                            0xd0f0110
+
+// Type
+#define D18F2x09C_x0D0F_0110_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0110_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0110_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0110_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0110_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0110_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0110_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0110_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0110_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0110_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0110_STRUCT;
+
+// **** D18F2x09C_x0D0F_011F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_011F_ADDRESS                            0xd0f011f
+
+// Type
+#define D18F2x09C_x0D0F_011F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_011F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_011F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_011F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_011F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_011F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_011F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_011F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_011F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_011F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_011F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_011F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0202 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0202_ADDRESS                            0xd0f0202
+
+// Type
+#define D18F2x09C_x0D0F_0202_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0202_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0202_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0202_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0202_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0202_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0202_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0202_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0202_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0202_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0202_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0202_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0202_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0202_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0202_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0202_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0202
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0202_STRUCT;
+
+// **** D18F2x09C_x0D0F_0206 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0206_ADDRESS                            0xd0f0206
+
+// Type
+#define D18F2x09C_x0D0F_0206_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0206_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0206_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0206_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0206_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0206_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0206_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0206_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0206_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0206_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0206
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0206_STRUCT;
+
+// **** D18F2x09C_x0D0F_020A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_020A_ADDRESS                            0xd0f020a
+
+// Type
+#define D18F2x09C_x0D0F_020A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_020A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_020A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_020A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_020A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_020A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_020A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_020A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_020A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_020A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_020A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_020A_STRUCT;
+
+// **** D18F2x09C_x0D0F_020F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_020F_ADDRESS                            0xd0f020f
+
+// Type
+#define D18F2x09C_x0D0F_020F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_020F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_020F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_020F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_020F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_020F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_020F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_020F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_020F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0210 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0210_ADDRESS                            0xd0f0210
+
+// Type
+#define D18F2x09C_x0D0F_0210_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0210_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0210_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0210_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0210_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0210_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0210_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0210_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0210_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0210_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0210
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0210_STRUCT;
+
+// **** D18F2x09C_x0D0F_021F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_021F_ADDRESS                            0xd0f021f
+
+// Type
+#define D18F2x09C_x0D0F_021F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_021F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_021F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_021F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_021F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_021F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_021F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_021F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_021F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_021F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_021F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_021F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0302 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0302_ADDRESS                            0xd0f0302
+
+// Type
+#define D18F2x09C_x0D0F_0302_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0302_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0302_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0302_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0302_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0302_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0302_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0302_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0302_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0302_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0302_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0302_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0302_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0302_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0302_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0302_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0302
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0302_STRUCT;
+
+// **** D18F2x09C_x0D0F_0306 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0306_ADDRESS                            0xd0f0306
+
+// Type
+#define D18F2x09C_x0D0F_0306_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0306_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0306_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0306_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0306_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0306_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0306_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0306_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0306_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0306_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0306
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0306_STRUCT;
+
+// **** D18F2x09C_x0D0F_030A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_030A_ADDRESS                            0xd0f030a
+
+// Type
+#define D18F2x09C_x0D0F_030A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_030A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_030A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_030A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_030A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_030A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_030A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_030A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_030A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_030A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_030A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_030A_STRUCT;
+
+// **** D18F2x09C_x0D0F_030F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_030F_ADDRESS                            0xd0f030f
+
+// Type
+#define D18F2x09C_x0D0F_030F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_030F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_030F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_030F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_030F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_030F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_030F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_030F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_030F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0310 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0310_ADDRESS                            0xd0f0310
+
+// Type
+#define D18F2x09C_x0D0F_0310_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0310_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0310_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0310_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0310_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0310_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0310_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0310_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0310_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0310_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0310
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0310_STRUCT;
+
+// **** D18F2x09C_x0D0F_031F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_031F_ADDRESS                            0xd0f031f
+
+// Type
+#define D18F2x09C_x0D0F_031F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_031F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_031F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_031F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_031F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_031F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_031F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_031F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_031F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_031F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_031F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_031F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0402 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0402_ADDRESS                            0xd0f0402
+
+// Type
+#define D18F2x09C_x0D0F_0402_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0402_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0402_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0402_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0402_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0402_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0402_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0402_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0402_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0402_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0402_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0402_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0402_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0402_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0402_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0402_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0402
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0402_STRUCT;
+
+// **** D18F2x09C_x0D0F_0406 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0406_ADDRESS                            0xd0f0406
+
+// Type
+#define D18F2x09C_x0D0F_0406_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0406_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0406_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0406_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0406_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0406_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0406_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0406_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0406_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0406_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0406
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0406_STRUCT;
+
+// **** D18F2x09C_x0D0F_040A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_040A_ADDRESS                            0xd0f040a
+
+// Type
+#define D18F2x09C_x0D0F_040A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_040A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_040A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_040A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_040A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_040A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_040A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_040A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_040A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_040A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_040A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_040A_STRUCT;
+
+// **** D18F2x09C_x0D0F_040F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_040F_ADDRESS                            0xd0f040f
+
+// Type
+#define D18F2x09C_x0D0F_040F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_040F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_040F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_040F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_040F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_040F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_040F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_040F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_040F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0410 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0410_ADDRESS                            0xd0f0410
+
+// Type
+#define D18F2x09C_x0D0F_0410_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0410_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0410_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0410_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0410_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0410_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0410_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0410_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0410_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0410_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0410
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0410_STRUCT;
+
+// **** D18F2x09C_x0D0F_041F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_041F_ADDRESS                            0xd0f041f
+
+// Type
+#define D18F2x09C_x0D0F_041F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_041F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_041F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_041F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_041F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_041F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_041F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_041F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_041F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_041F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_041F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_041F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0502 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0502_ADDRESS                            0xd0f0502
+
+// Type
+#define D18F2x09C_x0D0F_0502_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0502_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0502_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0502_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0502_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0502_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0502_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0502_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0502_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0502_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0502_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0502_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0502_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0502_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0502_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0502_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0502
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0502_STRUCT;
+
+// **** D18F2x09C_x0D0F_0506 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0506_ADDRESS                            0xd0f0506
+
+// Type
+#define D18F2x09C_x0D0F_0506_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0506_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0506_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0506_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0506_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0506_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0506_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0506_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0506_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0506_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0506
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0506_STRUCT;
+
+// **** D18F2x09C_x0D0F_050A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_050A_ADDRESS                            0xd0f050a
+
+// Type
+#define D18F2x09C_x0D0F_050A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_050A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_050A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_050A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_050A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_050A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_050A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_050A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_050A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_050A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_050A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_050A_STRUCT;
+
+// **** D18F2x09C_x0D0F_050F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_050F_ADDRESS                            0xd0f050f
+
+// Type
+#define D18F2x09C_x0D0F_050F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_050F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_050F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_050F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_050F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_050F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_050F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_050F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_050F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0510 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0510_ADDRESS                            0xd0f0510
+
+// Type
+#define D18F2x09C_x0D0F_0510_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0510_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0510_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0510_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0510_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0510_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0510_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0510_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0510_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0510_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0510
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0510_STRUCT;
+
+// **** D18F2x09C_x0D0F_051F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_051F_ADDRESS                            0xd0f051f
+
+// Type
+#define D18F2x09C_x0D0F_051F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_051F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_051F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_051F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_051F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_051F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_051F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_051F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_051F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_051F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_051F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_051F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0602 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0602_ADDRESS                            0xd0f0602
+
+// Type
+#define D18F2x09C_x0D0F_0602_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0602_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0602_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0602_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0602_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0602_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0602_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0602_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0602_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0602_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0602_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0602_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0602_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0602_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0602_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0602_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0602
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0602_STRUCT;
+
+// **** D18F2x09C_x0D0F_0606 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0606_ADDRESS                            0xd0f0606
+
+// Type
+#define D18F2x09C_x0D0F_0606_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0606_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0606_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0606_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0606_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0606_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0606_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0606_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0606_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0606_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0606
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0606_STRUCT;
+
+// **** D18F2x09C_x0D0F_060A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_060A_ADDRESS                            0xd0f060a
+
+// Type
+#define D18F2x09C_x0D0F_060A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_060A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_060A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_060A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_060A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_060A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_060A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_060A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_060A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_060A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_060A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_060A_STRUCT;
+
+// **** D18F2x09C_x0D0F_060F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_060F_ADDRESS                            0xd0f060f
+
+// Type
+#define D18F2x09C_x0D0F_060F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_060F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_060F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_060F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_060F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_060F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_060F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_060F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_060F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0610 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0610_ADDRESS                            0xd0f0610
+
+// Type
+#define D18F2x09C_x0D0F_0610_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0610_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0610_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0610_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0610_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0610_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0610_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0610_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0610_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0610_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0610
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0610_STRUCT;
+
+// **** D18F2x09C_x0D0F_061F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_061F_ADDRESS                            0xd0f061f
+
+// Type
+#define D18F2x09C_x0D0F_061F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_061F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_061F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_061F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_061F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_061F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_061F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_061F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_061F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_061F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_061F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_061F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0702 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0702_ADDRESS                            0xd0f0702
+
+// Type
+#define D18F2x09C_x0D0F_0702_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0702_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0702_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0702_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0702_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0702_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0702_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0702_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0702_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0702_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0702_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0702_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0702_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0702_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0702_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0702_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0702
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0702_STRUCT;
+
+// **** D18F2x09C_x0D0F_0706 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0706_ADDRESS                            0xd0f0706
+
+// Type
+#define D18F2x09C_x0D0F_0706_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0706_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0706_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0706_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0706_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0706_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0706_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0706_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0706_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0706_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0706
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0706_STRUCT;
+
+// **** D18F2x09C_x0D0F_070A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_070A_ADDRESS                            0xd0f070a
+
+// Type
+#define D18F2x09C_x0D0F_070A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_070A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_070A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_070A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_070A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_070A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_070A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_070A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_070A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_070A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_070A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_070A_STRUCT;
+
+// **** D18F2x09C_x0D0F_070F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_070F_ADDRESS                            0xd0f070f
+
+// Type
+#define D18F2x09C_x0D0F_070F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_070F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_070F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_070F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_070F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_070F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_070F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_070F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_070F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0710 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0710_ADDRESS                            0xd0f0710
+
+// Type
+#define D18F2x09C_x0D0F_0710_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0710_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0710_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0710_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0710_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0710_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0710_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0710_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0710_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0710_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0710
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0710_STRUCT;
+
+// **** D18F2x09C_x0D0F_071F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_071F_ADDRESS                            0xd0f071f
+
+// Type
+#define D18F2x09C_x0D0F_071F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_071F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_071F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_071F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_071F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_071F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_071F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_071F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_071F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_071F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_071F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_071F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0F02 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F02_ADDRESS                            0xd0f0f02
+
+// Type
+#define D18F2x09C_x0D0F_0F02_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F02_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0F02_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0F02_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0F02_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0F02_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0F02_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0F02_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0F02_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0F02_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0F02_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0F02_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0F02_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0F02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F02_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F06 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F06_ADDRESS                            0xd0f0f06
+
+// Type
+#define D18F2x09C_x0D0F_0F06_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F06_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0F06_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0F06_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0F06_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0F06_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0F06_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0F06_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0F06_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0F06_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0F06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F06_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F0A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F0A_ADDRESS                            0xd0f0f0a
+
+// Type
+#define D18F2x09C_x0D0F_0F0A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F0A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0F0A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0F0A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0F0A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0F0A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0F0A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0F0A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F0A_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F0F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F0F_ADDRESS                            0xd0f0f0f
+
+// Type
+#define D18F2x09C_x0D0F_0F0F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_0F0F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F0F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F10 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F10_ADDRESS                            0xd0f0f10
+
+// Type
+#define D18F2x09C_x0D0F_0F10_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F10_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0F10_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0F10_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0F10_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0F10_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0F10_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0F10
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F10_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F13 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F13_ADDRESS                            0xd0f0f13
+
+// Type
+#define D18F2x09C_x0D0F_0F13_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_OFFSET                0
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_WIDTH                 1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_MASK                  0x1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_OFFSET                1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_WIDTH                 1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_MASK                  0x2
+#define D18F2x09C_x0D0F_0F13_Reserved_6_2_OFFSET                2
+#define D18F2x09C_x0D0F_0F13_Reserved_6_2_WIDTH                 5
+#define D18F2x09C_x0D0F_0F13_Reserved_6_2_MASK                  0x7c
+#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_OFFSET          7
+#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_WIDTH           1
+#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_MASK            0x80
+#define D18F2x09C_x0D0F_0F13_Reserved_13_8_OFFSET               8
+#define D18F2x09C_x0D0F_0F13_Reserved_13_8_WIDTH                6
+#define D18F2x09C_x0D0F_0F13_Reserved_13_8_MASK                 0x3f00
+#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_OFFSET                  14
+#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_WIDTH                   1
+#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_MASK                    0x4000
+#define D18F2x09C_x0D0F_0F13_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_0F13_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_0F13_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_0F13
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DllDisEarlyL:1 ; ///<
+    UINT32                                             DllDisEarlyU:1 ; ///<
+    UINT32                                             Reserved_6_2:5 ; ///<
+    UINT32                                       RxDqsUDllPowerDown:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                               ProcOdtAdv:1 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F13_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F1F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F1F_ADDRESS                            0xd0f0f1f
+
+// Type
+#define D18F2x09C_x0D0F_0F1F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_0F1F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_0F1F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_0F1F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_0F1F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F1F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_2002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2002_ADDRESS                            0xd0f2002
+
+// Type
+#define D18F2x09C_x0D0F_2002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_2002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_2002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_2002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_2002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_2002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_2002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_2002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_2002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_2002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_2002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_2002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_2002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_2002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_2002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_2002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2002_STRUCT;
+
+// **** D18F2x09C_x0D0F_201F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_201F_ADDRESS                            0xd0f201f
+
+// Type
+#define D18F2x09C_x0D0F_201F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_201F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_201F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_201F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_201F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_201F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_201F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_201F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_201F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_201F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_201F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_201F_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_2030 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2030_ADDRESS                            0xd0f2030
+
+// Type
+#define D18F2x09C_x0D0F_2030_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2030_Reserved_3_0_OFFSET                0
+#define D18F2x09C_x0D0F_2030_Reserved_3_0_WIDTH                 4
+#define D18F2x09C_x0D0F_2030_Reserved_3_0_MASK                  0xf
+#define D18F2x09C_x0D0F_2030_PwrDn_OFFSET                       4
+#define D18F2x09C_x0D0F_2030_PwrDn_WIDTH                        1
+#define D18F2x09C_x0D0F_2030_PwrDn_MASK                         0x10
+#define D18F2x09C_x0D0F_2030_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_2030_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_2030_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_2030
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                    PwrDn:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2030_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_2102 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2102_ADDRESS                            0xd0f2102
+
+// Type
+#define D18F2x09C_x0D0F_2102_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2102_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_2102_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_2102_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_2102_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_2102_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_2102_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_2102_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_2102_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_2102_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_2102_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_2102_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_2102_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_2102_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_2102_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_2102_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_2102
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2102_STRUCT;
+
+// **** D18F2x09C_x0D0F_211F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_211F_ADDRESS                            0xd0f211f
+
+// Type
+#define D18F2x09C_x0D0F_211F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_211F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_211F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_211F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_211F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_211F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_211F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_211F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_211F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_211F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_211F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_211F_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_2130 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2130_ADDRESS                            0xd0f2130
+
+// Type
+#define D18F2x09C_x0D0F_2130_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2130_Reserved_3_0_OFFSET                0
+#define D18F2x09C_x0D0F_2130_Reserved_3_0_WIDTH                 4
+#define D18F2x09C_x0D0F_2130_Reserved_3_0_MASK                  0xf
+#define D18F2x09C_x0D0F_2130_PwrDn_OFFSET                       4
+#define D18F2x09C_x0D0F_2130_PwrDn_WIDTH                        1
+#define D18F2x09C_x0D0F_2130_PwrDn_MASK                         0x10
+#define D18F2x09C_x0D0F_2130_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_2130_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_2130_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_2130
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                    PwrDn:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2130_STRUCT;
+
+// Field Data
+#define D18F2x09C_x0D0F_4009_Reserved_1_0_OFFSET                0
+#define D18F2x09C_x0D0F_4009_Reserved_1_0_WIDTH                 2
+#define D18F2x09C_x0D0F_4009_Reserved_1_0_MASK                  0x3
+#define D18F2x09C_x0D0F_4009_ComparatorAdjust_OFFSET            2
+#define D18F2x09C_x0D0F_4009_ComparatorAdjust_WIDTH             2
+#define D18F2x09C_x0D0F_4009_ComparatorAdjust_MASK              0xc
+#define D18F2x09C_x0D0F_4009_Reserved_13_4_OFFSET               4
+#define D18F2x09C_x0D0F_4009_Reserved_13_4_WIDTH                10
+#define D18F2x09C_x0D0F_4009_Reserved_13_4_MASK                 0x3ff0
+#define D18F2x09C_x0D0F_4009_CmpVioLvl_OFFSET                   14
+#define D18F2x09C_x0D0F_4009_CmpVioLvl_WIDTH                    2
+#define D18F2x09C_x0D0F_4009_CmpVioLvl_MASK                     0xc000
+#define D18F2x09C_x0D0F_4009_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_4009_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_4009_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_4009
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                         ComparatorAdjust:2 ; ///<
+    UINT32                                            Reserved_13_4:10; ///<
+    UINT32                                                CmpVioLvl:2 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_4009_STRUCT;
+
+// **** D18F2x09C_x0D0F_8002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8002_ADDRESS                            0xd0f8002
+
+// Type
+#define D18F2x09C_x0D0F_8002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_8002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_8002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_8002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_8002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_8002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_8002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_8002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_8002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_8002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8002_STRUCT;
+
+// **** D18F2x09C_x0D0F_8006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8006_ADDRESS                            0xd0f8006
+
+// Type
+#define D18F2x09C_x0D0F_8006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8006_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8006_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8006_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8006_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8006_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8006_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8006_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_8006_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_8006_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_8006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8006_STRUCT;
+
+// **** D18F2x09C_x0D0F_800A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_800A_ADDRESS                            0xd0f800a
+
+// Type
+#define D18F2x09C_x0D0F_800A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_800A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_800A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_800A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_800A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_800A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_800A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_800A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_800A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_800A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_800A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_800A_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_8102 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8102_ADDRESS                            0xd0f8102
+
+// Type
+#define D18F2x09C_x0D0F_8102_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8102_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8102_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8102_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8102_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8102_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8102_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8102_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_8102_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_8102_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_8102_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_8102_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_8102_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_8102_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_8102_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_8102_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_8102
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8102_STRUCT;
+
+// **** D18F2x09C_x0D0F_8106 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8106_ADDRESS                            0xd0f8106
+
+// Type
+#define D18F2x09C_x0D0F_8106_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8106_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8106_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8106_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8106_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8106_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8106_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8106_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_8106_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_8106_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_8106
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8106_STRUCT;
+
+// **** D18F2x09C_x0D0F_810A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_810A_ADDRESS                            0xd0f810a
+
+// Type
+#define D18F2x09C_x0D0F_810A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_810A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_810A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_810A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_810A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_810A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_810A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_810A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_810A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_810A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_810A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_810A_STRUCT;
+
+
+
+
+// **** D18F2x09C_x0D0F_C000 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C000_ADDRESS                            0xd0fc000
+
+// Type
+#define D18F2x09C_x0D0F_C000_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C000_Reserved_7_0_OFFSET                0
+#define D18F2x09C_x0D0F_C000_Reserved_7_0_WIDTH                 8
+#define D18F2x09C_x0D0F_C000_Reserved_7_0_MASK                  0xff
+#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_OFFSET       8
+#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_WIDTH        1
+#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_MASK         0x100
+#define D18F2x09C_x0D0F_C000_Reserved_31_9_OFFSET               9
+#define D18F2x09C_x0D0F_C000_Reserved_31_9_WIDTH                23
+#define D18F2x09C_x0D0F_C000_Reserved_31_9_MASK                 0xfffffe00
+
+/// D18F2x09C_x0D0F_C000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                    LowPowerDrvStrengthEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C000_STRUCT;
+
+// **** D18F2x09C_x0D0F_C002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C002_ADDRESS                            0xd0fc002
+
+// Type
+#define D18F2x09C_x0D0F_C002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_C002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_C002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_C002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_C002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_C002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_C002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_C002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_C002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_C002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C002_STRUCT;
+
+// **** D18F2x09C_x0D0F_C006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C006_ADDRESS                            0xd0fc006
+
+// Type
+#define D18F2x09C_x0D0F_C006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C006_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C006_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C006_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C006_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C006_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C006_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C006_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C006_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C006_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C006_STRUCT;
+
+// **** D18F2x09C_x0D0F_C00A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C00A_ADDRESS                            0xd0fc00a
+
+// Type
+#define D18F2x09C_x0D0F_C00A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C00A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C00A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C00A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C00A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C00A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C00A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C00A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C00A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C00A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C00A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C00A_STRUCT;
+
+// **** D18F2x09C_x0D0F_C00E Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C00E_ADDRESS                            0xd0fc00e
+
+// Type
+#define D18F2x09C_x0D0F_C00E_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C00E_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C00E_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C00E_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C00E_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C00E_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C00E_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C00E_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C00E_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C00E_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C00E
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C00E_STRUCT;
+
+// **** D18F2x09C_x0D0F_C012 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C012_ADDRESS                            0xd0fc012
+
+// Type
+#define D18F2x09C_x0D0F_C012_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C012_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C012_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C012_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C012_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C012_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C012_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C012_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C012_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C012_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C012_STRUCT;
+
+
+
+
+// **** D18F2x09C_x0D0F_E006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_E006_ADDRESS                            0xd0fe006
+
+// Type
+#define D18F2x09C_x0D0F_E006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_E006_PllLockTime_OFFSET                 0
+#define D18F2x09C_x0D0F_E006_PllLockTime_WIDTH                  16
+#define D18F2x09C_x0D0F_E006_PllLockTime_MASK                   0xffff
+#define D18F2x09C_x0D0F_E006_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_E006_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_E006_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_E006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              PllLockTime:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_E006_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_E013 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_E013_ADDRESS                            0xd0fe013
+
+// Type
+#define D18F2x09C_x0D0F_E013_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_E013_PllRegWaitTime_OFFSET              0
+#define D18F2x09C_x0D0F_E013_PllRegWaitTime_WIDTH               16
+#define D18F2x09C_x0D0F_E013_PllRegWaitTime_MASK                0xffff
+#define D18F2x09C_x0D0F_E013_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_E013_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_E013_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_E013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PllRegWaitTime:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_E013_STRUCT;
+
+
+// **** DxF0xE4_x02 Register Definition ****
+// Address
+#define DxF0xE4_x02_ADDRESS                                     0x2
+
+// Type
+#define DxF0xE4_x02_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x02_Reserved_14_0_OFFSET                        0
+#define DxF0xE4_x02_Reserved_14_0_WIDTH                         15
+#define DxF0xE4_x02_Reserved_14_0_MASK                          0x7fff
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET               15
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH                1
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK                 0x8000
+#define DxF0xE4_x02_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_x02_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_x02_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_x02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                   RegsLcAllowTxL1Control:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x02_STRUCT;
+
+// **** DxF0xE4_x20 Register Definition ****
+// Address
+#define DxF0xE4_x20_ADDRESS                                     0x20
+
+// Type
+#define DxF0xE4_x20_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x20_Reserved_14_0_OFFSET                        0
+#define DxF0xE4_x20_Reserved_14_0_WIDTH                         15
+#define DxF0xE4_x20_Reserved_14_0_MASK                          0x7fff
+#define DxF0xE4_x20_TxFlushTlpDis_OFFSET                        15
+#define DxF0xE4_x20_TxFlushTlpDis_WIDTH                         1
+#define DxF0xE4_x20_TxFlushTlpDis_MASK                          0x8000
+#define DxF0xE4_x20_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_x20_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_x20_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                            TxFlushTlpDis:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x20_STRUCT;
+
+// **** DxF0xE4_x50 Register Definition ****
+// Address
+#define DxF0xE4_x50_ADDRESS                                     0x50
+
+// Type
+#define DxF0xE4_x50_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x50_PortLaneReversal_OFFSET                     0
+#define DxF0xE4_x50_PortLaneReversal_WIDTH                      1
+#define DxF0xE4_x50_PortLaneReversal_MASK                       0x1
+#define DxF0xE4_x50_PhyLinkWidth_OFFSET                         1
+#define DxF0xE4_x50_PhyLinkWidth_WIDTH                          6
+#define DxF0xE4_x50_PhyLinkWidth_MASK                           0x7e
+#define DxF0xE4_x50_Reserved_31_7_OFFSET                        7
+#define DxF0xE4_x50_Reserved_31_7_WIDTH                         25
+#define DxF0xE4_x50_Reserved_31_7_MASK                          0xffffff80
+
+/// DxF0xE4_x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PortLaneReversal:1 ; ///<
+    UINT32                                             PhyLinkWidth:6 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x50_STRUCT;
+
+// **** DxF0xE4_x70 Register Definition ****
+// Address
+#define DxF0xE4_x70_ADDRESS                                     0x70
+
+// Type
+#define DxF0xE4_x70_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x70_Reserved_15_0_OFFSET                        0
+#define DxF0xE4_x70_Reserved_15_0_WIDTH                         16
+#define DxF0xE4_x70_Reserved_15_0_MASK                          0xffff
+#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET                      16
+#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH                       3
+#define DxF0xE4_x70_RxRcbCplTimeout_MASK                        0x70000
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET                  19
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH                   1
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK                    0x80000
+#define DxF0xE4_x70_Reserved_31_20_OFFSET                       20
+#define DxF0xE4_x70_Reserved_31_20_WIDTH                        12
+#define DxF0xE4_x70_Reserved_31_20_MASK                         0xfff00000
+
+/// DxF0xE4_x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                          RxRcbCplTimeout:3 ; ///<
+    UINT32                                      RxRcbCplTimeoutMode:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x70_STRUCT;
+
+// **** DxF0xE4_xA0 Register Definition ****
+// Address
+#define DxF0xE4_xA0_ADDRESS                                     0xa0
+
+// Type
+#define DxF0xE4_xA0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA0_Reserved_3_0_OFFSET                         0
+#define DxF0xE4_xA0_Reserved_3_0_WIDTH                          4
+#define DxF0xE4_xA0_Reserved_3_0_MASK                           0xf
+#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET                     4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH                      4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK                       0xf0
+#define DxF0xE4_xA0_LcL0sInactivity_OFFSET                      8
+#define DxF0xE4_xA0_LcL0sInactivity_WIDTH                       4
+#define DxF0xE4_xA0_LcL0sInactivity_MASK                        0xf00
+#define DxF0xE4_xA0_LcL1Inactivity_OFFSET                       12
+#define DxF0xE4_xA0_LcL1Inactivity_WIDTH                        4
+#define DxF0xE4_xA0_LcL1Inactivity_MASK                         0xf000
+#define DxF0xE4_xA0_Reserved_22_16_OFFSET                       16
+#define DxF0xE4_xA0_Reserved_22_16_WIDTH                        7
+#define DxF0xE4_xA0_Reserved_22_16_MASK                         0x7f0000
+#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET                     23
+#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH                      1
+#define DxF0xE4_xA0_LcL1ImmediateAck_MASK                       0x800000
+#define DxF0xE4_xA0_Reserved_31_24_OFFSET                       24
+#define DxF0xE4_xA0_Reserved_31_24_WIDTH                        8
+#define DxF0xE4_xA0_Reserved_31_24_MASK                         0xff000000
+
+/// DxF0xE4_xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                         Lc16xClearTxPipe:4 ; ///<
+    UINT32                                          LcL0sInactivity:4 ; ///<
+    UINT32                                           LcL1Inactivity:4 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                         LcL1ImmediateAck:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA0_STRUCT;
+
+// **** DxF0xE4_xA1 Register Definition ****
+// Address
+#define DxF0xE4_xA1_ADDRESS                                     0xa1
+
+// Type
+#define DxF0xE4_xA1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA1_Reserved_10_0_OFFSET                        0
+#define DxF0xE4_xA1_Reserved_10_0_WIDTH                         11
+#define DxF0xE4_xA1_Reserved_10_0_MASK                          0x7ff
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET               11
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH                1
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK                 0x800
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET                12
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH                 1
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK                  0x1000
+#define DxF0xE4_xA1_Reserved_31_13_OFFSET                       13
+#define DxF0xE4_xA1_Reserved_31_13_WIDTH                        19
+#define DxF0xE4_xA1_Reserved_31_13_MASK                         0xffffe000
+
+/// DxF0xE4_xA1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_10_0:11; ///<
+    UINT32                                   LcDontGotoL0sifL1Armed:1 ; ///<
+    UINT32                                    LcInitSpdChgWithCsrEn:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA1_STRUCT;
+
+// **** DxF0xE4_xA2 Register Definition ****
+// Address
+#define DxF0xE4_xA2_ADDRESS                                     0xa2
+
+// Type
+#define DxF0xE4_xA2_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA2_LcLinkWidth_OFFSET                          0
+#define DxF0xE4_xA2_LcLinkWidth_WIDTH                           3
+#define DxF0xE4_xA2_LcLinkWidth_MASK                            0x7
+#define DxF0xE4_xA2_Reserved_3_3_OFFSET                         3
+#define DxF0xE4_xA2_Reserved_3_3_WIDTH                          1
+#define DxF0xE4_xA2_Reserved_3_3_MASK                           0x8
+#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET                        4
+#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH                         3
+#define DxF0xE4_xA2_LcLinkWidthRd_MASK                          0x70
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET           7
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH            1
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK             0x80
+#define DxF0xE4_xA2_LcReconfigNow_OFFSET                        8
+#define DxF0xE4_xA2_LcReconfigNow_WIDTH                         1
+#define DxF0xE4_xA2_LcReconfigNow_MASK                          0x100
+#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET               9
+#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH                1
+#define DxF0xE4_xA2_LcRenegotiationSupport_MASK                 0x200
+#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET                      10
+#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH                       1
+#define DxF0xE4_xA2_LcRenegotiateEn_MASK                        0x400
+#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET                    11
+#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH                     1
+#define DxF0xE4_xA2_LcShortReconfigEn_MASK                      0x800
+#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET                 12
+#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH                  1
+#define DxF0xE4_xA2_LcUpconfigureSupport_MASK                   0x1000
+#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET                     13
+#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH                      1
+#define DxF0xE4_xA2_LcUpconfigureDis_MASK                       0x2000
+#define DxF0xE4_xA2_Reserved_19_14_OFFSET                       14
+#define DxF0xE4_xA2_Reserved_19_14_WIDTH                        6
+#define DxF0xE4_xA2_Reserved_19_14_MASK                         0xfc000
+#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET                    20
+#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH                     1
+#define DxF0xE4_xA2_LcUpconfigCapable_MASK                      0x100000
+#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET                   21
+#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH                    2
+#define DxF0xE4_xA2_LcDynLanesPwrState_MASK                     0x600000
+#define DxF0xE4_xA2_Reserved_31_23_OFFSET                       23
+#define DxF0xE4_xA2_Reserved_31_23_WIDTH                        9
+#define DxF0xE4_xA2_Reserved_31_23_MASK                         0xff800000
+
+/// DxF0xE4_xA2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LcLinkWidth:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            LcLinkWidthRd:3 ; ///<
+    UINT32                               LcReconfigArcMissingEscape:1 ; ///<
+    UINT32                                            LcReconfigNow:1 ; ///<
+    UINT32                                   LcRenegotiationSupport:1 ; ///<
+    UINT32                                          LcRenegotiateEn:1 ; ///<
+    UINT32                                        LcShortReconfigEn:1 ; ///<
+    UINT32                                     LcUpconfigureSupport:1 ; ///<
+    UINT32                                         LcUpconfigureDis:1 ; ///<
+    UINT32                                           Reserved_19_14:6 ; ///<
+    UINT32                                        LcUpconfigCapable:1 ; ///<
+    UINT32                                       LcDynLanesPwrState:2 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA2_STRUCT;
+
+// **** DxF0xE4_xA3 Register Definition ****
+// Address
+#define DxF0xE4_xA3_ADDRESS                                     0xa3
+
+// Type
+#define DxF0xE4_xA3_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA3_Reserved_8_0_OFFSET                         0
+#define DxF0xE4_xA3_Reserved_8_0_WIDTH                          9
+#define DxF0xE4_xA3_Reserved_8_0_MASK                           0x1ff
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET              9
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH               1
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK                0x200
+#define DxF0xE4_xA3_Reserved_31_10_OFFSET                       10
+#define DxF0xE4_xA3_Reserved_31_10_WIDTH                        22
+#define DxF0xE4_xA3_Reserved_31_10_MASK                         0xfffffc00
+
+/// DxF0xE4_xA3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                  LcXmitFtsBeforeRecovery:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA3_STRUCT;
+
+/// DxF0xE4_xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LcGen2EnStrap:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                  LcForceDisSwSpeedChange:1 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                LcInitiateLinkSpeedChange:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                               LcSpeedChangeAttemptFailed:1 ; ///<
+    UINT32                                           Reserved_17_11:7 ; ///<
+    UINT32                                           LcGoToRecovery:1 ; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                  LcOtherSideSupportsGen2:1 ; ///<
+    UINT32                                           Reserved_28_25:4 ; ///<
+    UINT32                              LcMultUpstreamAutoSpdChngEn:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex548_STRUCT;
+
+// **** DxF0xE4_xA5 Register Definition ****
+// Address
+#define DxF0xE4_xA5_ADDRESS                                     0xa5
+
+// Type
+#define DxF0xE4_xA5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA5_LcCurrentState_OFFSET                       0
+#define DxF0xE4_xA5_LcCurrentState_WIDTH                        6
+#define DxF0xE4_xA5_LcCurrentState_MASK                         0x3f
+#define DxF0xE4_xA5_Reserved_7_6_OFFSET                         6
+#define DxF0xE4_xA5_Reserved_7_6_WIDTH                          2
+#define DxF0xE4_xA5_Reserved_7_6_MASK                           0xc0
+#define DxF0xE4_xA5_LcPrevState1_OFFSET                         8
+#define DxF0xE4_xA5_LcPrevState1_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState1_MASK                           0x3f00
+#define DxF0xE4_xA5_Reserved_15_14_OFFSET                       14
+#define DxF0xE4_xA5_Reserved_15_14_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_15_14_MASK                         0xc000
+#define DxF0xE4_xA5_LcPrevState2_OFFSET                         16
+#define DxF0xE4_xA5_LcPrevState2_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState2_MASK                           0x3f0000
+#define DxF0xE4_xA5_Reserved_23_22_OFFSET                       22
+#define DxF0xE4_xA5_Reserved_23_22_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_23_22_MASK                         0xc00000
+#define DxF0xE4_xA5_LcPrevState3_OFFSET                         24
+#define DxF0xE4_xA5_LcPrevState3_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState3_MASK                           0x3f000000
+#define DxF0xE4_xA5_Reserved_31_30_OFFSET                       30
+#define DxF0xE4_xA5_Reserved_31_30_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_31_30_MASK                         0xc0000000
+
+/// DxF0xE4_xA5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LcCurrentState:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                             LcPrevState1:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                             LcPrevState2:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                             LcPrevState3:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA5_STRUCT;
+
+// **** DxF0xE4_xB1 Register Definition ****
+// Address
+#define DxF0xE4_xB1_ADDRESS                                     0xb1
+
+// Type
+#define DxF0xE4_xB1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB1_Reserved_18_0_OFFSET                        0
+#define DxF0xE4_xB1_Reserved_18_0_WIDTH                         19
+#define DxF0xE4_xB1_Reserved_18_0_MASK                          0x7ffff
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET                  19
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH                   1
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK                    0x80000
+#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET                    20
+#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH                     1
+#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK                      0x100000
+#define DxF0xE4_xB1_Reserved_31_21_OFFSET                       21
+#define DxF0xE4_xB1_Reserved_31_21_WIDTH                        11
+#define DxF0xE4_xB1_Reserved_31_21_MASK                         0xffe00000
+
+/// DxF0xE4_xB1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_18_0:19; ///<
+    UINT32                                      LcDeassertRxEnInL0s:1 ; ///<
+    UINT32                                        LcBlockElIdleinL0:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB1_STRUCT;
+
+// **** DxF0xE4_xC0 Register Definition ****
+// Address
+#define DxF0xE4_xC0_ADDRESS                                     0xc0
+
+// Type
+#define DxF0xE4_xC0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xC0_Reserved_12_0_OFFSET                        0
+#define DxF0xE4_xC0_Reserved_12_0_WIDTH                         13
+#define DxF0xE4_xC0_Reserved_12_0_MASK                          0x1fff
+#define DxF0xE4_xC0_StrapForceCompliance_OFFSET                 13
+#define DxF0xE4_xC0_StrapForceCompliance_WIDTH                  1
+#define DxF0xE4_xC0_StrapForceCompliance_MASK                   0x2000
+#define DxF0xE4_xC0_Reserved_14_14_OFFSET                       14
+#define DxF0xE4_xC0_Reserved_14_14_WIDTH                        1
+#define DxF0xE4_xC0_Reserved_14_14_MASK                         0x4000
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET       15
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH        1
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK         0x8000
+#define DxF0xE4_xC0_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_xC0_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_xC0_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_xC0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_12_0:13; ///<
+    UINT32                                     StrapForceCompliance:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                           StrapAutoRcSpeedNegotiationDis:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xC0_STRUCT;
+
+
+
+// **** GMMx4D0 Register Definition ****
+// Address
+#define GMMx4D0_ADDRESS                                         0x4d0
+
+// Type
+#define GMMx4D0_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx4D0_DispclkDccgGateDisable_OFFSET                   0
+#define GMMx4D0_DispclkDccgGateDisable_WIDTH                    1
+#define GMMx4D0_DispclkDccgGateDisable_MASK                     0x1
+#define GMMx4D0_DispclkRDccgGateDisable_OFFSET                  1
+#define GMMx4D0_DispclkRDccgGateDisable_WIDTH                   1
+#define GMMx4D0_DispclkRDccgGateDisable_MASK                    0x2
+#define GMMx4D0_SclkGateDisable_OFFSET                          2
+#define GMMx4D0_SclkGateDisable_WIDTH                           1
+#define GMMx4D0_SclkGateDisable_MASK                            0x4
+#define GMMx4D0_Reserved_7_3_OFFSET                             3
+#define GMMx4D0_Reserved_7_3_WIDTH                              5
+#define GMMx4D0_Reserved_7_3_MASK                               0xf8
+#define GMMx4D0_SymclkaGateDisable_OFFSET                       8
+#define GMMx4D0_SymclkaGateDisable_WIDTH                        1
+#define GMMx4D0_SymclkaGateDisable_MASK                         0x100
+#define GMMx4D0_SymclkbGateDisable_OFFSET                       9
+#define GMMx4D0_SymclkbGateDisable_WIDTH                        1
+#define GMMx4D0_SymclkbGateDisable_MASK                         0x200
+#define GMMx4D0_Reserved_31_10_OFFSET                           10
+#define GMMx4D0_Reserved_31_10_WIDTH                            22
+#define GMMx4D0_Reserved_31_10_MASK                             0xfffffc00
+
+/// GMMx4D0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                   DispclkDccgGateDisable:1 ; ///<
+    UINT32                                  DispclkRDccgGateDisable:1 ; ///<
+    UINT32                                          SclkGateDisable:1 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                       SymclkaGateDisable:1 ; ///<
+    UINT32                                       SymclkbGateDisable:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx4D0_STRUCT;
+
+// **** GMMx770 Register Definition ****
+// Address
+#define GMMx770_ADDRESS                                         0x770
+
+// Type
+#define GMMx770_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx770_VoltageChangeReq_OFFSET                         0
+#define GMMx770_VoltageChangeReq_WIDTH                          1
+#define GMMx770_VoltageChangeReq_MASK                           0x1
+#define GMMx770_VoltageLevel_OFFSET                             1
+#define GMMx770_VoltageLevel_WIDTH                              2
+#define GMMx770_VoltageLevel_MASK                               0x6
+#define GMMx770_VoltageChangeEn_OFFSET                          3
+#define GMMx770_VoltageChangeEn_WIDTH                           1
+#define GMMx770_VoltageChangeEn_MASK                            0x8
+#define GMMx770_VoltageForceEn_OFFSET                           4
+#define GMMx770_VoltageForceEn_WIDTH                            1
+#define GMMx770_VoltageForceEn_MASK                             0x10
+#define GMMx770_Reserved_31_5_OFFSET                            5
+#define GMMx770_Reserved_31_5_WIDTH                             27
+#define GMMx770_Reserved_31_5_MASK                              0xffffffe0
+
+/// GMMx770
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             VoltageLevel:2 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx770_STRUCT;
+
+// **** GMMx774 Register Definition ****
+// Address
+#define GMMx774_ADDRESS                                         0x774
+
+// Type
+#define GMMx774_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx774_VoltageChangeAck_OFFSET                         0
+#define GMMx774_VoltageChangeAck_WIDTH                          1
+#define GMMx774_VoltageChangeAck_MASK                           0x1
+#define GMMx774_CurrentVoltageLevel_OFFSET                      1
+#define GMMx774_CurrentVoltageLevel_WIDTH                       2
+#define GMMx774_CurrentVoltageLevel_MASK                        0x6
+#define GMMx774_Reserved_31_3_OFFSET                            3
+#define GMMx774_Reserved_31_3_WIDTH                             29
+#define GMMx774_Reserved_31_3_MASK                              0xfffffff8
+
+/// GMMx774
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:2 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx774_STRUCT;
+
+// **** GMMx15C0 Register Definition ****
+// Address
+#define GMMx15C0_ADDRESS                                        0x15c0
+
+// Type
+#define GMMx15C0_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx15C0_OnDly_OFFSET                                   0
+#define GMMx15C0_OnDly_WIDTH                                    6
+#define GMMx15C0_OnDly_MASK                                     0x3f
+#define GMMx15C0_OffDly_OFFSET                                  6
+#define GMMx15C0_OffDly_WIDTH                                   6
+#define GMMx15C0_OffDly_MASK                                    0xfc0
+#define GMMx15C0_RdyDly_OFFSET                                  12
+#define GMMx15C0_RdyDly_WIDTH                                   6
+#define GMMx15C0_RdyDly_MASK                                    0x3f000
+#define GMMx15C0_Enable_OFFSET                                  18
+#define GMMx15C0_Enable_WIDTH                                   1
+#define GMMx15C0_Enable_MASK                                    0x40000
+#define GMMx15C0_Reserved_31_19_OFFSET                          19
+#define GMMx15C0_Reserved_31_19_WIDTH                           13
+#define GMMx15C0_Reserved_31_19_MASK                            0xfff80000
+
+/// GMMx15C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    OnDly:6 ; ///<
+    UINT32                                                   OffDly:6 ; ///<
+    UINT32                                                   RdyDly:6 ; ///<
+    UINT32                                                   Enable:1 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx15C0_STRUCT;
+
+
+
+
+
+// **** GMMx2024 Register Definition ****
+// Address
+#define GMMx2024_ADDRESS                                        0x2024
+
+// Type
+#define GMMx2024_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2024_Base_OFFSET                                    0
+#define GMMx2024_Base_WIDTH                                     16
+#define GMMx2024_Base_MASK                                      0xffff
+#define GMMx2024_Top_OFFSET                                     16
+#define GMMx2024_Top_WIDTH                                      16
+#define GMMx2024_Top_MASK                                       0xffff0000
+
+/// GMMx2024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Base:16; ///<
+    UINT32                                                      Top:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2024_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// **** GMMx2814 Register Definition ****
+// Address
+#define GMMx2814_ADDRESS                                        0x2814
+
+// Type
+#define GMMx2814_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2814_WriteClks_OFFSET                               0
+#define GMMx2814_WriteClks_WIDTH                                9
+#define GMMx2814_WriteClks_MASK                                 0x1ff
+#define GMMx2814_UvdHarshPriority_OFFSET                        9
+#define GMMx2814_UvdHarshPriority_WIDTH                         1
+#define GMMx2814_UvdHarshPriority_MASK                          0x200
+#define GMMx2814_Reserved_31_10_OFFSET                          10
+#define GMMx2814_Reserved_31_10_WIDTH                           22
+#define GMMx2814_Reserved_31_10_MASK                            0xfffffc00
+
+/// GMMx2814
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WriteClks:9 ; ///<
+    UINT32                                         UvdHarshPriority:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2814_STRUCT;
+
+// **** GMMx281C Register Definition ****
+// Address
+#define GMMx281C_ADDRESS                                        0x281c
+
+// Type
+#define GMMx281C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx281C_CSEnable_OFFSET                                0
+#define GMMx281C_CSEnable_WIDTH                                 1
+#define GMMx281C_CSEnable_MASK                                  0x1
+#define GMMx281C_Reserved_4_1_OFFSET                            1
+#define GMMx281C_Reserved_4_1_WIDTH                             4
+#define GMMx281C_Reserved_4_1_MASK                              0x1e
+#define GMMx281C_BaseAddr_21_13__OFFSET                         5
+#define GMMx281C_BaseAddr_21_13__WIDTH                          9
+#define GMMx281C_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx281C_Reserved_18_14_OFFSET                          14
+#define GMMx281C_Reserved_18_14_WIDTH                           5
+#define GMMx281C_Reserved_18_14_MASK                            0x7c000
+#define GMMx281C_BaseAddr_36_27__OFFSET                         19
+#define GMMx281C_BaseAddr_36_27__WIDTH                          10
+#define GMMx281C_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx281C_Reserved_31_29_OFFSET                          29
+#define GMMx281C_Reserved_31_29_WIDTH                           3
+#define GMMx281C_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx281C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx281C_STRUCT;
+
+// **** GMMx2820 Register Definition ****
+// Address
+#define GMMx2820_ADDRESS                                        0x2820
+
+// Type
+#define GMMx2820_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2820_CSEnable_OFFSET                                0
+#define GMMx2820_CSEnable_WIDTH                                 1
+#define GMMx2820_CSEnable_MASK                                  0x1
+#define GMMx2820_Reserved_4_1_OFFSET                            1
+#define GMMx2820_Reserved_4_1_WIDTH                             4
+#define GMMx2820_Reserved_4_1_MASK                              0x1e
+#define GMMx2820_BaseAddr_21_13__OFFSET                         5
+#define GMMx2820_BaseAddr_21_13__WIDTH                          9
+#define GMMx2820_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2820_Reserved_18_14_OFFSET                          14
+#define GMMx2820_Reserved_18_14_WIDTH                           5
+#define GMMx2820_Reserved_18_14_MASK                            0x7c000
+#define GMMx2820_BaseAddr_36_27__OFFSET                         19
+#define GMMx2820_BaseAddr_36_27__WIDTH                          10
+#define GMMx2820_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2820_Reserved_31_29_OFFSET                          29
+#define GMMx2820_Reserved_31_29_WIDTH                           3
+#define GMMx2820_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2820
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2820_STRUCT;
+
+// **** GMMx2824 Register Definition ****
+// Address
+#define GMMx2824_ADDRESS                                        0x2824
+
+// Type
+#define GMMx2824_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2824_CSEnable_OFFSET                                0
+#define GMMx2824_CSEnable_WIDTH                                 1
+#define GMMx2824_CSEnable_MASK                                  0x1
+#define GMMx2824_Reserved_4_1_OFFSET                            1
+#define GMMx2824_Reserved_4_1_WIDTH                             4
+#define GMMx2824_Reserved_4_1_MASK                              0x1e
+#define GMMx2824_BaseAddr_21_13__OFFSET                         5
+#define GMMx2824_BaseAddr_21_13__WIDTH                          9
+#define GMMx2824_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2824_Reserved_18_14_OFFSET                          14
+#define GMMx2824_Reserved_18_14_WIDTH                           5
+#define GMMx2824_Reserved_18_14_MASK                            0x7c000
+#define GMMx2824_BaseAddr_36_27__OFFSET                         19
+#define GMMx2824_BaseAddr_36_27__WIDTH                          10
+#define GMMx2824_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2824_Reserved_31_29_OFFSET                          29
+#define GMMx2824_Reserved_31_29_WIDTH                           3
+#define GMMx2824_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2824
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2824_STRUCT;
+
+// **** GMMx2828 Register Definition ****
+// Address
+#define GMMx2828_ADDRESS                                        0x2828
+
+// Type
+#define GMMx2828_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2828_CSEnable_OFFSET                                0
+#define GMMx2828_CSEnable_WIDTH                                 1
+#define GMMx2828_CSEnable_MASK                                  0x1
+#define GMMx2828_Reserved_4_1_OFFSET                            1
+#define GMMx2828_Reserved_4_1_WIDTH                             4
+#define GMMx2828_Reserved_4_1_MASK                              0x1e
+#define GMMx2828_BaseAddr_21_13__OFFSET                         5
+#define GMMx2828_BaseAddr_21_13__WIDTH                          9
+#define GMMx2828_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2828_Reserved_18_14_OFFSET                          14
+#define GMMx2828_Reserved_18_14_WIDTH                           5
+#define GMMx2828_Reserved_18_14_MASK                            0x7c000
+#define GMMx2828_BaseAddr_36_27__OFFSET                         19
+#define GMMx2828_BaseAddr_36_27__WIDTH                          10
+#define GMMx2828_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2828_Reserved_31_29_OFFSET                          29
+#define GMMx2828_Reserved_31_29_WIDTH                           3
+#define GMMx2828_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2828
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2828_STRUCT;
+
+// **** GMMx282C Register Definition ****
+// Address
+#define GMMx282C_ADDRESS                                        0x282c
+
+// Type
+#define GMMx282C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx282C_CSEnable_OFFSET                                0
+#define GMMx282C_CSEnable_WIDTH                                 1
+#define GMMx282C_CSEnable_MASK                                  0x1
+#define GMMx282C_Reserved_4_1_OFFSET                            1
+#define GMMx282C_Reserved_4_1_WIDTH                             4
+#define GMMx282C_Reserved_4_1_MASK                              0x1e
+#define GMMx282C_BaseAddr_21_13__OFFSET                         5
+#define GMMx282C_BaseAddr_21_13__WIDTH                          9
+#define GMMx282C_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx282C_Reserved_18_14_OFFSET                          14
+#define GMMx282C_Reserved_18_14_WIDTH                           5
+#define GMMx282C_Reserved_18_14_MASK                            0x7c000
+#define GMMx282C_BaseAddr_36_27__OFFSET                         19
+#define GMMx282C_BaseAddr_36_27__WIDTH                          10
+#define GMMx282C_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx282C_Reserved_31_29_OFFSET                          29
+#define GMMx282C_Reserved_31_29_WIDTH                           3
+#define GMMx282C_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx282C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx282C_STRUCT;
+
+// **** GMMx2830 Register Definition ****
+// Address
+#define GMMx2830_ADDRESS                                        0x2830
+
+// Type
+#define GMMx2830_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2830_CSEnable_OFFSET                                0
+#define GMMx2830_CSEnable_WIDTH                                 1
+#define GMMx2830_CSEnable_MASK                                  0x1
+#define GMMx2830_Reserved_4_1_OFFSET                            1
+#define GMMx2830_Reserved_4_1_WIDTH                             4
+#define GMMx2830_Reserved_4_1_MASK                              0x1e
+#define GMMx2830_BaseAddr_21_13__OFFSET                         5
+#define GMMx2830_BaseAddr_21_13__WIDTH                          9
+#define GMMx2830_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2830_Reserved_18_14_OFFSET                          14
+#define GMMx2830_Reserved_18_14_WIDTH                           5
+#define GMMx2830_Reserved_18_14_MASK                            0x7c000
+#define GMMx2830_BaseAddr_36_27__OFFSET                         19
+#define GMMx2830_BaseAddr_36_27__WIDTH                          10
+#define GMMx2830_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2830_Reserved_31_29_OFFSET                          29
+#define GMMx2830_Reserved_31_29_WIDTH                           3
+#define GMMx2830_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2830
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2830_STRUCT;
+
+// **** GMMx2834 Register Definition ****
+// Address
+#define GMMx2834_ADDRESS                                        0x2834
+
+// Type
+#define GMMx2834_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2834_CSEnable_OFFSET                                0
+#define GMMx2834_CSEnable_WIDTH                                 1
+#define GMMx2834_CSEnable_MASK                                  0x1
+#define GMMx2834_Reserved_4_1_OFFSET                            1
+#define GMMx2834_Reserved_4_1_WIDTH                             4
+#define GMMx2834_Reserved_4_1_MASK                              0x1e
+#define GMMx2834_BaseAddr_21_13__OFFSET                         5
+#define GMMx2834_BaseAddr_21_13__WIDTH                          9
+#define GMMx2834_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2834_Reserved_18_14_OFFSET                          14
+#define GMMx2834_Reserved_18_14_WIDTH                           5
+#define GMMx2834_Reserved_18_14_MASK                            0x7c000
+#define GMMx2834_BaseAddr_36_27__OFFSET                         19
+#define GMMx2834_BaseAddr_36_27__WIDTH                          10
+#define GMMx2834_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2834_Reserved_31_29_OFFSET                          29
+#define GMMx2834_Reserved_31_29_WIDTH                           3
+#define GMMx2834_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2834
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2834_STRUCT;
+
+// **** GMMx2838 Register Definition ****
+// Address
+#define GMMx2838_ADDRESS                                        0x2838
+
+// Type
+#define GMMx2838_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2838_CSEnable_OFFSET                                0
+#define GMMx2838_CSEnable_WIDTH                                 1
+#define GMMx2838_CSEnable_MASK                                  0x1
+#define GMMx2838_Reserved_4_1_OFFSET                            1
+#define GMMx2838_Reserved_4_1_WIDTH                             4
+#define GMMx2838_Reserved_4_1_MASK                              0x1e
+#define GMMx2838_BaseAddr_21_13__OFFSET                         5
+#define GMMx2838_BaseAddr_21_13__WIDTH                          9
+#define GMMx2838_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2838_Reserved_18_14_OFFSET                          14
+#define GMMx2838_Reserved_18_14_WIDTH                           5
+#define GMMx2838_Reserved_18_14_MASK                            0x7c000
+#define GMMx2838_BaseAddr_36_27__OFFSET                         19
+#define GMMx2838_BaseAddr_36_27__WIDTH                          10
+#define GMMx2838_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2838_Reserved_31_29_OFFSET                          29
+#define GMMx2838_Reserved_31_29_WIDTH                           3
+#define GMMx2838_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2838
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2838_STRUCT;
+
+// **** GMMx283C Register Definition ****
+// Address
+#define GMMx283C_ADDRESS                                        0x283c
+
+// Type
+#define GMMx283C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx283C_Reserved_4_0_OFFSET                            0
+#define GMMx283C_Reserved_4_0_WIDTH                             5
+#define GMMx283C_Reserved_4_0_MASK                              0x1f
+#define GMMx283C_AddrMask_21_13__OFFSET                         5
+#define GMMx283C_AddrMask_21_13__WIDTH                          9
+#define GMMx283C_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx283C_Reserved_18_14_OFFSET                          14
+#define GMMx283C_Reserved_18_14_WIDTH                           5
+#define GMMx283C_Reserved_18_14_MASK                            0x7c000
+#define GMMx283C_AddrMask_36_27__OFFSET                         19
+#define GMMx283C_AddrMask_36_27__WIDTH                          10
+#define GMMx283C_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx283C_Reserved_31_29_OFFSET                          29
+#define GMMx283C_Reserved_31_29_WIDTH                           3
+#define GMMx283C_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx283C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx283C_STRUCT;
+
+// **** GMMx2840 Register Definition ****
+// Address
+#define GMMx2840_ADDRESS                                        0x2840
+
+// Type
+#define GMMx2840_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2840_Reserved_4_0_OFFSET                            0
+#define GMMx2840_Reserved_4_0_WIDTH                             5
+#define GMMx2840_Reserved_4_0_MASK                              0x1f
+#define GMMx2840_AddrMask_21_13__OFFSET                         5
+#define GMMx2840_AddrMask_21_13__WIDTH                          9
+#define GMMx2840_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx2840_Reserved_18_14_OFFSET                          14
+#define GMMx2840_Reserved_18_14_WIDTH                           5
+#define GMMx2840_Reserved_18_14_MASK                            0x7c000
+#define GMMx2840_AddrMask_36_27__OFFSET                         19
+#define GMMx2840_AddrMask_36_27__WIDTH                          10
+#define GMMx2840_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx2840_Reserved_31_29_OFFSET                          29
+#define GMMx2840_Reserved_31_29_WIDTH                           3
+#define GMMx2840_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2840
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2840_STRUCT;
+
+// **** GMMx2844 Register Definition ****
+// Address
+#define GMMx2844_ADDRESS                                        0x2844
+
+// Type
+#define GMMx2844_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2844_Reserved_4_0_OFFSET                            0
+#define GMMx2844_Reserved_4_0_WIDTH                             5
+#define GMMx2844_Reserved_4_0_MASK                              0x1f
+#define GMMx2844_AddrMask_21_13__OFFSET                         5
+#define GMMx2844_AddrMask_21_13__WIDTH                          9
+#define GMMx2844_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx2844_Reserved_18_14_OFFSET                          14
+#define GMMx2844_Reserved_18_14_WIDTH                           5
+#define GMMx2844_Reserved_18_14_MASK                            0x7c000
+#define GMMx2844_AddrMask_36_27__OFFSET                         19
+#define GMMx2844_AddrMask_36_27__WIDTH                          10
+#define GMMx2844_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx2844_Reserved_31_29_OFFSET                          29
+#define GMMx2844_Reserved_31_29_WIDTH                           3
+#define GMMx2844_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2844
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2844_STRUCT;
+
+// **** GMMx2848 Register Definition ****
+// Address
+#define GMMx2848_ADDRESS                                        0x2848
+
+// Type
+#define GMMx2848_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2848_Reserved_4_0_OFFSET                            0
+#define GMMx2848_Reserved_4_0_WIDTH                             5
+#define GMMx2848_Reserved_4_0_MASK                              0x1f
+#define GMMx2848_AddrMask_21_13__OFFSET                         5
+#define GMMx2848_AddrMask_21_13__WIDTH                          9
+#define GMMx2848_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx2848_Reserved_18_14_OFFSET                          14
+#define GMMx2848_Reserved_18_14_WIDTH                           5
+#define GMMx2848_Reserved_18_14_MASK                            0x7c000
+#define GMMx2848_AddrMask_36_27__OFFSET                         19
+#define GMMx2848_AddrMask_36_27__WIDTH                          10
+#define GMMx2848_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx2848_Reserved_31_29_OFFSET                          29
+#define GMMx2848_Reserved_31_29_WIDTH                           3
+#define GMMx2848_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2848
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2848_STRUCT;
+
+// **** GMMx284C Register Definition ****
+// Address
+#define GMMx284C_ADDRESS                                        0x284c
+
+// Type
+#define GMMx284C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx284C_Dimm0AddrMap_OFFSET                            0
+#define GMMx284C_Dimm0AddrMap_WIDTH                             4
+#define GMMx284C_Dimm0AddrMap_MASK                              0xf
+#define GMMx284C_Dimm1AddrMap_OFFSET                            4
+#define GMMx284C_Dimm1AddrMap_WIDTH                             4
+#define GMMx284C_Dimm1AddrMap_MASK                              0xf0
+#define GMMx284C_Reserved_15_8_OFFSET                           8
+#define GMMx284C_Reserved_15_8_WIDTH                            8
+#define GMMx284C_Reserved_15_8_MASK                             0xff00
+#define GMMx284C_BankSwizzleMode_OFFSET                         16
+#define GMMx284C_BankSwizzleMode_WIDTH                          1
+#define GMMx284C_BankSwizzleMode_MASK                           0x10000
+#define GMMx284C_Ddr3Mode_OFFSET                                17
+#define GMMx284C_Ddr3Mode_WIDTH                                 1
+#define GMMx284C_Ddr3Mode_MASK                                  0x20000
+#define GMMx284C_BurstLength32_OFFSET                           18
+#define GMMx284C_BurstLength32_WIDTH                            1
+#define GMMx284C_BurstLength32_MASK                             0x40000
+#define GMMx284C_BankSwap_OFFSET                                19
+#define GMMx284C_BankSwap_WIDTH                                 1
+#define GMMx284C_BankSwap_MASK                                  0x80000
+#define GMMx284C_Reserved_31_20_OFFSET                          20
+#define GMMx284C_Reserved_31_20_WIDTH                           12
+#define GMMx284C_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx284C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Dimm0AddrMap:4 ; ///<
+    UINT32                                             Dimm1AddrMap:4 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                                 Ddr3Mode:1 ; ///<
+    UINT32                                            BurstLength32:1 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx284C_STRUCT;
+
+// **** GMMx2850 Register Definition ****
+// Address
+#define GMMx2850_ADDRESS                                        0x2850
+
+// Type
+#define GMMx2850_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2850_Dimm0AddrMap_OFFSET                            0
+#define GMMx2850_Dimm0AddrMap_WIDTH                             4
+#define GMMx2850_Dimm0AddrMap_MASK                              0xf
+#define GMMx2850_Dimm1AddrMap_OFFSET                            4
+#define GMMx2850_Dimm1AddrMap_WIDTH                             4
+#define GMMx2850_Dimm1AddrMap_MASK                              0xf0
+#define GMMx2850_Reserved_15_8_OFFSET                           8
+#define GMMx2850_Reserved_15_8_WIDTH                            8
+#define GMMx2850_Reserved_15_8_MASK                             0xff00
+#define GMMx2850_BankSwizzleMode_OFFSET                         16
+#define GMMx2850_BankSwizzleMode_WIDTH                          1
+#define GMMx2850_BankSwizzleMode_MASK                           0x10000
+#define GMMx2850_Ddr3Mode_OFFSET                                17
+#define GMMx2850_Ddr3Mode_WIDTH                                 1
+#define GMMx2850_Ddr3Mode_MASK                                  0x20000
+#define GMMx2850_BurstLength32_OFFSET                           18
+#define GMMx2850_BurstLength32_WIDTH                            1
+#define GMMx2850_BurstLength32_MASK                             0x40000
+#define GMMx2850_BankSwap_OFFSET                                19
+#define GMMx2850_BankSwap_WIDTH                                 1
+#define GMMx2850_BankSwap_MASK                                  0x80000
+#define GMMx2850_Reserved_31_20_OFFSET                          20
+#define GMMx2850_Reserved_31_20_WIDTH                           12
+#define GMMx2850_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2850
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Dimm0AddrMap:4 ; ///<
+    UINT32                                             Dimm1AddrMap:4 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                                 Ddr3Mode:1 ; ///<
+    UINT32                                            BurstLength32:1 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2850_STRUCT;
+
+// **** GMMx2854 Register Definition ****
+// Address
+#define GMMx2854_ADDRESS                                        0x2854
+
+// Type
+#define GMMx2854_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2854_DctSelHiRngEn_OFFSET                           0
+#define GMMx2854_DctSelHiRngEn_WIDTH                            1
+#define GMMx2854_DctSelHiRngEn_MASK                             0x1
+#define GMMx2854_DctSelHi_OFFSET                                1
+#define GMMx2854_DctSelHi_WIDTH                                 1
+#define GMMx2854_DctSelHi_MASK                                  0x2
+#define GMMx2854_DctSelIntLvEn_OFFSET                           2
+#define GMMx2854_DctSelIntLvEn_WIDTH                            1
+#define GMMx2854_DctSelIntLvEn_MASK                             0x4
+#define GMMx2854_Reserved_5_3_OFFSET                            3
+#define GMMx2854_Reserved_5_3_WIDTH                             3
+#define GMMx2854_Reserved_5_3_MASK                              0x38
+#define GMMx2854_DctSelIntLvAddr_1_0__OFFSET                    6
+#define GMMx2854_DctSelIntLvAddr_1_0__WIDTH                     2
+#define GMMx2854_DctSelIntLvAddr_1_0__MASK                      0xc0
+#define GMMx2854_Reserved_10_8_OFFSET                           8
+#define GMMx2854_Reserved_10_8_WIDTH                            3
+#define GMMx2854_Reserved_10_8_MASK                             0x700
+#define GMMx2854_DctSelBaseAddr_39_27__OFFSET                   11
+#define GMMx2854_DctSelBaseAddr_39_27__WIDTH                    13
+#define GMMx2854_DctSelBaseAddr_39_27__MASK                     0xfff800
+#define GMMx2854_Reserved_31_24_OFFSET                          24
+#define GMMx2854_Reserved_31_24_WIDTH                           8
+#define GMMx2854_Reserved_31_24_MASK                            0xff000000
+
+/// GMMx2854
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DctSelHiRngEn:1 ; ///<
+    UINT32                                                 DctSelHi:1 ; ///<
+    UINT32                                            DctSelIntLvEn:1 ; ///<
+    UINT32                                             Reserved_5_3:3 ; ///<
+    UINT32                                     DctSelIntLvAddr_1_0_:2 ; ///<
+    UINT32                                            Reserved_10_8:3 ; ///<
+    UINT32                                    DctSelBaseAddr_39_27_:13; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2854_STRUCT;
+
+// **** GMMx2858 Register Definition ****
+// Address
+#define GMMx2858_ADDRESS                                        0x2858
+
+// Type
+#define GMMx2858_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2858_Reserved_8_0_OFFSET                            0
+#define GMMx2858_Reserved_8_0_WIDTH                             9
+#define GMMx2858_Reserved_8_0_MASK                              0x1ff
+#define GMMx2858_DctSelIntLvAddr_2__OFFSET                      9
+#define GMMx2858_DctSelIntLvAddr_2__WIDTH                       1
+#define GMMx2858_DctSelIntLvAddr_2__MASK                        0x200
+#define GMMx2858_DctSelBaseOffset_39_26__OFFSET                 10
+#define GMMx2858_DctSelBaseOffset_39_26__WIDTH                  14
+#define GMMx2858_DctSelBaseOffset_39_26__MASK                   0xfffc00
+#define GMMx2858_Reserved_31_24_OFFSET                          24
+#define GMMx2858_Reserved_31_24_WIDTH                           8
+#define GMMx2858_Reserved_31_24_MASK                            0xff000000
+
+/// GMMx2858
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
+    UINT32                                  DctSelBaseOffset_39_26_:14; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2858_STRUCT;
+
+// **** GMMx285C Register Definition ****
+// Address
+#define GMMx285C_ADDRESS                                        0x285c
+
+// Type
+#define GMMx285C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx285C_DramHoleValid_OFFSET                           0
+#define GMMx285C_DramHoleValid_WIDTH                            1
+#define GMMx285C_DramHoleValid_MASK                             0x1
+#define GMMx285C_Reserved_6_1_OFFSET                            1
+#define GMMx285C_Reserved_6_1_WIDTH                             6
+#define GMMx285C_Reserved_6_1_MASK                              0x7e
+#define GMMx285C_DramHoleOffset_31_23__OFFSET                   7
+#define GMMx285C_DramHoleOffset_31_23__WIDTH                    9
+#define GMMx285C_DramHoleOffset_31_23__MASK                     0xff80
+#define GMMx285C_Reserved_23_16_OFFSET                          16
+#define GMMx285C_Reserved_23_16_WIDTH                           8
+#define GMMx285C_Reserved_23_16_MASK                            0xff0000
+#define GMMx285C_DramHoleBase_31_24__OFFSET                     24
+#define GMMx285C_DramHoleBase_31_24__WIDTH                      8
+#define GMMx285C_DramHoleBase_31_24__MASK                       0xff000000
+
+/// GMMx285C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DramHoleValid:1 ; ///<
+    UINT32                                             Reserved_6_1:6 ; ///<
+    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
+    UINT32                                           Reserved_23_16:8 ; ///<
+    UINT32                                      DramHoleBase_31_24_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx285C_STRUCT;
+
+
+
+
+
+// **** GMMx2870 Register Definition ****
+// Address
+#define GMMx2870_ADDRESS                                        0x2870
+
+// Type
+#define GMMx2870_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2870_Base_OFFSET                                    0
+#define GMMx2870_Base_WIDTH                                     20
+#define GMMx2870_Base_MASK                                      0xfffff
+#define GMMx2870_Reserved_31_20_OFFSET                          20
+#define GMMx2870_Reserved_31_20_WIDTH                           12
+#define GMMx2870_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2870
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Base:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2870_STRUCT;
+
+// **** GMMx2874 Register Definition ****
+// Address
+#define GMMx2874_ADDRESS                                        0x2874
+
+// Type
+#define GMMx2874_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2874_Base_OFFSET                                    0
+#define GMMx2874_Base_WIDTH                                     20
+#define GMMx2874_Base_MASK                                      0xfffff
+#define GMMx2874_Reserved_31_20_OFFSET                          20
+#define GMMx2874_Reserved_31_20_WIDTH                           12
+#define GMMx2874_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2874
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Base:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2874_STRUCT;
+
+
+// **** GMMx287C Register Definition ****
+// Address
+#define GMMx287C_ADDRESS                                        0x287c
+
+// Type
+#define GMMx287C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx287C_Top_OFFSET                                     0
+#define GMMx287C_Top_WIDTH                                      20
+#define GMMx287C_Top_MASK                                       0xfffff
+#define GMMx287C_Reserved_31_20_OFFSET                          20
+#define GMMx287C_Reserved_31_20_WIDTH                           12
+#define GMMx287C_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx287C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Top:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx287C_STRUCT;
+
+
+
+// **** GMMx2888 Register Definition ****
+// Address
+#define GMMx2888_ADDRESS                                        0x2888
+
+// Type
+#define GMMx2888_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2888_Top_OFFSET                                     0
+#define GMMx2888_Top_WIDTH                                      20
+#define GMMx2888_Top_MASK                                       0xfffff
+#define GMMx2888_Reserved_31_20_OFFSET                          20
+#define GMMx2888_Reserved_31_20_WIDTH                           12
+#define GMMx2888_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2888
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Top:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2888_STRUCT;
+
+
+
+
+
+
+// **** GMMx28D8 Register Definition ****
+// Address
+#define GMMx28D8_ADDRESS                                        0x28d8
+
+// Type
+#define GMMx28D8_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx28D8_ActRd_OFFSET                                   0
+#define GMMx28D8_ActRd_WIDTH                                    8
+#define GMMx28D8_ActRd_MASK                                     0xff
+#define GMMx28D8_ActWr_OFFSET                                   8
+#define GMMx28D8_ActWr_WIDTH                                    8
+#define GMMx28D8_ActWr_MASK                                     0xff00
+#define GMMx28D8_RasMActRd_OFFSET                               16
+#define GMMx28D8_RasMActRd_WIDTH                                8
+#define GMMx28D8_RasMActRd_MASK                                 0xff0000
+#define GMMx28D8_RasMActWr_OFFSET                               24
+#define GMMx28D8_RasMActWr_WIDTH                                8
+#define GMMx28D8_RasMActWr_MASK                                 0xff000000
+
+/// GMMx28D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    ActRd:8 ; ///<
+    UINT32                                                    ActWr:8 ; ///<
+    UINT32                                                RasMActRd:8 ; ///<
+    UINT32                                                RasMActWr:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx28D8_STRUCT;
+
+
+
+
+
+
+
+// **** GMMx2C04 Register Definition ****
+// Address
+#define GMMx2C04_ADDRESS                                        0x2c04
+
+// Type
+#define GMMx2C04_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2C04_NonsurfBase_OFFSET                             0
+#define GMMx2C04_NonsurfBase_WIDTH                              28
+#define GMMx2C04_NonsurfBase_MASK                               0xfffffff
+#define GMMx2C04_Reserved_31_28_OFFSET                          28
+#define GMMx2C04_Reserved_31_28_WIDTH                           4
+#define GMMx2C04_Reserved_31_28_MASK                            0xf0000000
+
+/// GMMx2C04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              NonsurfBase:28; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2C04_STRUCT;
+
+// **** GMMx5428 Register Definition ****
+// Address
+#define GMMx5428_ADDRESS                                        0x5428
+
+// Type
+#define GMMx5428_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5428_ConfigMemsize_OFFSET                           0
+#define GMMx5428_ConfigMemsize_WIDTH                            32
+#define GMMx5428_ConfigMemsize_MASK                             0xffffffff
+
+/// GMMx5428
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ConfigMemsize:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5428_STRUCT;
+
+// **** GMMx5490 Register Definition ****
+// Address
+#define GMMx5490_ADDRESS                                        0x5490
+
+// Type
+#define GMMx5490_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5490_FbReadEn_OFFSET                                0
+#define GMMx5490_FbReadEn_WIDTH                                 1
+#define GMMx5490_FbReadEn_MASK                                  0x1
+#define GMMx5490_FbWriteEn_OFFSET                               1
+#define GMMx5490_FbWriteEn_WIDTH                                1
+#define GMMx5490_FbWriteEn_MASK                                 0x2
+#define GMMx5490_Reserved_31_2_OFFSET                           2
+#define GMMx5490_Reserved_31_2_WIDTH                            30
+#define GMMx5490_Reserved_31_2_MASK                             0xfffffffc
+
+/// GMMx5490
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 FbReadEn:1 ; ///<
+    UINT32                                                FbWriteEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5490_STRUCT;
+
+
+/// SMUx73
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DisLclkGating:1 ; ///<
+    UINT32                                            DisSclkGating:1 ; ///<
+    UINT32                                            Reserved_15_2:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} SMUx73_STRUCT;
+
+// **** MSRC001_001A Register Definition ****
+// Address
+#define MSRC001_001A_ADDRESS                                    0xc001001a
+
+// Type
+#define MSRC001_001A_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_001A_RAZ_22_0_OFFSET                            0
+#define MSRC001_001A_RAZ_22_0_WIDTH                             23
+#define MSRC001_001A_RAZ_22_0_MASK                              0x7fffff
+#define MSRC001_001A_TOM_39_23__OFFSET                          23
+#define MSRC001_001A_TOM_39_23__WIDTH                           17
+#define MSRC001_001A_TOM_39_23__MASK                            0xffff800000
+#define MSRC001_001A_MBZ_47_40_OFFSET                           40
+#define MSRC001_001A_MBZ_47_40_WIDTH                            8
+#define MSRC001_001A_MBZ_47_40_MASK                             0xff0000000000
+#define MSRC001_001A_RAZ_63_48_OFFSET                           48
+#define MSRC001_001A_RAZ_63_48_WIDTH                            16
+#define MSRC001_001A_RAZ_63_48_MASK                             0xffff000000000000
+
+/// MSRC001_001A
+typedef union {
+  struct {                                                              ///<
+    UINT64                                                 RAZ_22_0:23; ///<
+    UINT64                                               TOM_39_23_:17; ///<
+    UINT64                                                MBZ_47_40:8 ; ///<
+    UINT64                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_001A_STRUCT;
+
+
+
+
+
+
+
+// **** D0F0xE4_WRAP_8013 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8013_ADDRESS                               0x8013
+
+// Field Data
+#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET                 0
+#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH                  1
+#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK                   0x1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET                   2
+#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK                     0x4
+#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET                   3
+#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK                     0x8
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET       4
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH        1
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK         0x10
+#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET                   5
+#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK                     0x20
+#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET                   7
+#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK                     0x80
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET           8
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH            1
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK             0x100
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET           9
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH            1
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK             0x200
+#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET                 10
+#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK                   0x400
+#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET                 11
+#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK                   0x800
+#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET                 12
+#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK                   0x1000
+#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET                 13
+#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH                  3
+#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK                   0xe000
+#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET                 16
+#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK                   0x10000
+#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET                 17
+#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH                  3
+#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK                   0xe0000
+#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET                 20
+#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK                   0x100000
+#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET                 21
+#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH                  11
+#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK                   0xffe00000
+
+/// D0F0xE4_WRAP_8013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MasterPciePllA:1 ; ///<
+    UINT32                                           MasterPciePllB:1 ; ///<
+    UINT32                                           MasterPciePllC:1 ; ///<
+    UINT32                                           MasterPciePllD:1 ; ///<
+    UINT32                                 ClkDividerResetOverrideA:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                     TxclkSelCoreOverride:1 ; ///<
+    UINT32                                     TxclkSelPifAOverride:1 ; ///<
+    UINT32                                           Reserved_10_10:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                           Reserved_16_16:1 ; ///<
+    UINT32                                           Reserved_19_17:3 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8013_STRUCT;
+
+// **** D0F0xE4_WRAP_8014 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8014_ADDRESS                               0x8014
+
+// Field Data
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET            0
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK              0x1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET            1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK              0x2
+#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET                   2
+#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK                     0x4
+#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET                   3
+#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK                     0x8
+#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET                   4
+#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK                     0x10
+#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET                   5
+#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK                     0x20
+#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET                   7
+#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK                     0x80
+#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET                   8
+#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK                     0x100
+#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET                   9
+#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK                     0x200
+#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET                 10
+#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK                   0x400
+#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET                 11
+#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK                   0x800
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET           12
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK             0x1000
+#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET                 13
+#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK                   0x2000
+#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET                 14
+#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK                   0x4000
+#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET                 15
+#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK                   0x8000
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET         16
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK           0x10000
+#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET                 17
+#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK                   0x20000
+#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET                 18
+#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK                   0x40000
+#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET                 19
+#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK                   0x80000
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET  20
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH   1
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK    0x100000
+#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET                 21
+#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH                  11
+#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK                   0xffe00000
+
+/// D0F0xE4_WRAP_8014
+typedef union {
+  struct {
+    UINT32                                      TxclkPermGateEnable:1 ; ///<
+    UINT32                                      TxclkPrbsGateEnable:1 ; ///<
+    UINT32                                      DdiGatePifA1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifB1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifC1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifD1xEnable:1 ; ///<
+    UINT32                                        DdiGateDigAEnable:1 ; ///<
+    UINT32                                        DdiGateDigBEnable:1 ; ///<
+    UINT32                                    DdiGatePifA2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifB2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifC2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifD2p5xEnable:1 ; ///<
+    UINT32                                     PcieGatePifA1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifB1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifC1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifD1xEnable:1 ; ///<
+    UINT32                                   PcieGatePifA2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifB2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifC2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifD2p5xEnable:1 ; ///<
+    UINT32                            TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8014_STRUCT;
+
+
+
+
+
+// **** GMMx6124 Register Definition ****
+// Address
+#define GMMx6124_ADDRESS                                        0x6124
+
+// **** GMMx6124 Register Definition ****
+// Address
+#define GMMx6124_ADDRESS                                        0x6124
+
+// Type
+#define GMMx6124_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx6124_DoutScratch_OFFSET                             0
+#define GMMx6124_DoutScratch_WIDTH                              32
+#define GMMx6124_DoutScratch_MASK                               0xffffffff
+
+
+
+
+
+
+
+
+// **** D0F0xE4_CORE_0020 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0020_ADDRESS                               0x20
+
+// Type
+#define D0F0xE4_CORE_0020_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0020_Reserved_1_0_OFFSET                   0
+#define D0F0xE4_CORE_0020_Reserved_1_0_WIDTH                    2
+#define D0F0xE4_CORE_0020_Reserved_1_0_MASK                     0x3
+#define D0F0xE4_CORE_0020_Reserved_31_12_OFFSET                 12
+#define D0F0xE4_CORE_0020_Reserved_31_12_WIDTH                  20
+#define D0F0xE4_CORE_0020_Reserved_31_12_MASK                   0xfffff000
+
+/// D0F0xE4_CORE_0020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                       :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                         :2 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                          :1 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                        :1 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0020_STRUCT;
+
+// **** D0F0xE4_CORE_0010 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0010_ADDRESS                               0x10
+
+// Type
+#define D0F0xE4_CORE_0010_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET                   0
+#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH                    1
+#define D0F0xE4_CORE_0010_HwInitWrLock_MASK                     0x1
+#define D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET                1
+#define D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH                 3
+#define D0F0xE4_CORE_0010_LcHotPlugDelSel_MASK                  0xe
+#define D0F0xE4_CORE_0010_Reserved_6_4_OFFSET                   4
+#define D0F0xE4_CORE_0010_Reserved_6_4_WIDTH                    3
+#define D0F0xE4_CORE_0010_Reserved_6_4_MASK                     0x70
+
+/// D0F0xE4_CORE_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                          LcHotPlugDelSel:3 ; ///<
+    UINT32                                             Reserved_6_4:3 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                            :1 ; ///<
+    UINT32                                      :3 ; ///<
+    UINT32                                           :3 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                      :1 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                  :1 ; ///<
+    UINT32                                     :1 ; ///<
+    UINT32                                        :1 ; ///<
+    UINT32                                     :1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                               :6 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                      :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0010_STRUCT;
+
+
+// **** D0F0x98_x0C Register Definition ****
+// Address
+#define D0F0x98_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x98_x0C_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x0C_GcmWrrLenA_OFFSET                           0
+#define D0F0x98_x0C_GcmWrrLenA_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenA_MASK                             0xff
+#define D0F0x98_x0C_GcmWrrLenB_OFFSET                           8
+#define D0F0x98_x0C_GcmWrrLenB_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenB_MASK                             0xff00
+#define D0F0x98_x0C_Reserved_29_16_OFFSET                       16
+#define D0F0x98_x0C_Reserved_29_16_WIDTH                        14
+#define D0F0x98_x0C_Reserved_29_16_MASK                         0x3fff0000
+#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET                    30
+#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH                     1
+#define D0F0x98_x0C_StrictSelWinnerEn_MASK                      0x40000000
+
+/// D0F0x98_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               GcmWrrLenA:8 ; ///<
+    UINT32                                               GcmWrrLenB:8 ; ///<
+    UINT32                                           Reserved_29_16:14; ///<
+    UINT32                                        StrictSelWinnerEn:1 ; ///<
+    UINT32                                             :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x0C_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// **** D0F0xE4_WRAP_8063 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8063_ADDRESS                               0x8063
+
+// Type
+#define D0F0xE4_WRAP_8063_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8063_Reserved_0_0_OFFSET                   0
+#define D0F0xE4_WRAP_8063_Reserved_0_0_WIDTH                    1
+#define D0F0xE4_WRAP_8063_Reserved_0_0_MASK                     0x1
+#define D0F0xE4_WRAP_8063_Reserved_25_25_OFFSET                 25
+#define D0F0xE4_WRAP_8063_Reserved_25_25_WIDTH                  1
+#define D0F0xE4_WRAP_8063_Reserved_25_25_MASK                   0x2000000
+#define D0F0xE4_WRAP_8063_Reserved_27_26_OFFSET                 26
+#define D0F0xE4_WRAP_8063_Reserved_27_26_WIDTH                  2
+#define D0F0xE4_WRAP_8063_Reserved_27_26_MASK                   0xc000000
+#define D0F0xE4_WRAP_8063_Reserved_31_28_OFFSET                 28
+#define D0F0xE4_WRAP_8063_Reserved_31_28_WIDTH                  4
+#define D0F0xE4_WRAP_8063_Reserved_31_28_MASK                   0xf0000000
+
+/// D0F0xE4_WRAP_8063
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    line331:1 ; ///<
+    UINT32    line332:1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :2 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    line338:1 ; ///<
+    UINT32    line339:1 ; ///<
+    UINT32    line340:1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :2 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :2 ; ///<
+    UINT32    :1 ; ///<
+    UINT32                                           Reserved_25_25:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8063_STRUCT;
+
+// **** D0F0xE4_WRAP_8015 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8015_ADDRESS                               0x8015
+
+// Type
+#define D0F0xE4_WRAP_8015_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8015_EnableD0StateReport_OFFSET            0
+#define D0F0xE4_WRAP_8015_EnableD0StateReport_WIDTH             1
+#define D0F0xE4_WRAP_8015_EnableD0StateReport_MASK              0x1
+#define D0F0xE4_WRAP_8015_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8015_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8015_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_OFFSET     2
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_WIDTH      1
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_MASK       0x4
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_OFFSET      3
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_WIDTH       1
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_MASK        0x8
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_OFFSET      4
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_WIDTH       2
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_MASK        0x30
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_OFFSET       6
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_WIDTH        2
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_MASK         0xc0
+#define D0F0xE4_WRAP_8015_Reserved_8_8_OFFSET                   8
+#define D0F0xE4_WRAP_8015_Reserved_8_8_WIDTH                    1
+#define D0F0xE4_WRAP_8015_Reserved_8_8_MASK                     0x100
+#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_OFFSET        9
+#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_WIDTH         1
+#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_MASK          0x200
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_OFFSET       10
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_WIDTH        1
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_MASK         0x400
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_OFFSET        11
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_WIDTH         1
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_MASK          0x800
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_OFFSET        12
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_WIDTH         2
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_MASK          0x3000
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_OFFSET         14
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_WIDTH          2
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_MASK           0xc000
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET          16
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK            0x3f0000
+#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET           23
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK             0x800000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET          24
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK            0x3f000000
+#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET                 30
+#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK                   0x40000000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET           31
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK             0x80000000
+
+/// D0F0xE4_WRAP_8015
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      EnableD0StateReport:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                               SlowRefclkThroughTxclk2p5x:1 ; ///<
+    UINT32                                SlowRefclkEnableTxclk2p5x:1 ; ///<
+    UINT32                                SlowRefclkDivideTxclk2p5x:2 ; ///<
+    UINT32                                 SlowRefclkBurstTxclk2p5x:2 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                  SlowRefclkLcntGateForce:1 ; ///<
+    UINT32                                 SlowRefclkThroughTxclk1x:1 ; ///<
+    UINT32                                  SlowRefclkEnableTxclk1x:1 ; ///<
+    UINT32                                  SlowRefclkDivideTxclk1x:2 ; ///<
+    UINT32                                   SlowRefclkBurstTxclk1x:2 ; ///<
+    UINT32                                    RefclkRegsGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                     RefclkRegsGateEnable:1 ; ///<
+    UINT32                                    RefclkBphyGateLatency:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                     RefclkBphyGateEnable:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8015_STRUCT;
+
+// **** DxF0xE4_xB5 Register Definition ****
+// Address
+#define DxF0xE4_xB5_ADDRESS                                     0xb5
+
+// Type
+#define DxF0xE4_xB5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET                   0
+#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH                    1
+#define DxF0xE4_xB5_LcSelectDeemphasis_MASK                     0x1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET               1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH                2
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK                 0x6
+#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET                     3
+#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH                      1
+#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK                       0x8
+#define DxF0xE4_xB5_Reserved_31_23_OFFSET                       23
+#define DxF0xE4_xB5_Reserved_31_23_WIDTH                        9
+#define DxF0xE4_xB5_Reserved_31_23_MASK                         0xff800000
+
+/// DxF0xE4_xB5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       LcSelectDeemphasis:1 ; ///<
+    UINT32                                   LcSelectDeemphasisCntl:2 ; ///<
+    UINT32                                         LcRcvdDeemphasis:1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  line519:1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  line521:2 ; ///<
+    UINT32  line522:2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB5_STRUCT;
+
+
+// **** D0F0xE4_PHY_6006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6006_ADDRESS                                0x6006
+
+// Type
+#define D0F0xE4_PHY_6006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET                     0
+#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH                      8
+#define D0F0xE4_PHY_6006_TxMarginNom_MASK                       0xff
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET                   8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH                    8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK                     0xff00
+#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET                 16
+#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_WIDTH                  8
+#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK                   0xff0000
+#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET                 24
+#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_WIDTH                  8
+#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK                   0xff000000
+
+/// D0F0xE4_PHY_6006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              TxMarginNom:8 ; ///<
+    UINT32                                            DeemphGen1Nom:8 ; ///<
+    UINT32                                          Deemph35Gen2Nom:8 ; ///<
+    UINT32                                          Deemph60Gen2Nom:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6006_STRUCT;
+
+
+
+// **** D0F0x64_x1C Register Definition ****
+// Address
+#define D0F0x64_x1C_ADDRESS                                     0x1c
+
+// Type
+#define D0F0x64_x1C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1C_WriteDis_OFFSET                             0
+#define D0F0x64_x1C_WriteDis_WIDTH                              1
+#define D0F0x64_x1C_WriteDis_MASK                               0x1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET              1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH               1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK                0x2
+#define D0F0x64_x1C_F064BarEn_OFFSET                            2
+#define D0F0x64_x1C_F064BarEn_WIDTH                             1
+#define D0F0x64_x1C_F064BarEn_MASK                              0x4
+#define D0F0x64_x1C_MemApSize_OFFSET                            3
+#define D0F0x64_x1C_MemApSize_WIDTH                             3
+#define D0F0x64_x1C_MemApSize_MASK                              0x38
+#define D0F0x64_x1C_RegApSize_OFFSET                            6
+#define D0F0x64_x1C_RegApSize_WIDTH                             1
+#define D0F0x64_x1C_RegApSize_MASK                              0x40
+
+/// D0F0x64_x1C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 WriteDis:1 ; ///<
+    UINT32                                  F0NonlegacyDeviceTypeEn:1 ; ///<
+    UINT32                                                F064BarEn:1 ; ///<
+    UINT32                                                MemApSize:3 ; ///<
+    UINT32                                                RegApSize:1 ; ///<
+    UINT32  /*                                        DualfuncDisplayEn*/:1 ; ///<
+    UINT32  /*                                                  AudioEn*/:1 ; ///<
+    UINT32  /*                                                   MsiDis*/:1 ; ///<
+    UINT32  /*                               AudioNonlegacyDeviceTypeEn*/:1 ; ///<
+    UINT32  /*                                             Audio64BarEn*/:1 ; ///<
+    UINT32  /*                                                   VgaDis*/:1 ; ///<
+    UINT32  /*                                               FbAlwaysOn*/:1 ; ///<
+    UINT32  /*                                             FbCplTypeSel*/:2 ; ///<
+    UINT32  /*                                                 IoBarDis*/:1 ; ///<
+    UINT32  /*                                                     F0En*/:1 ; ///<
+    UINT32  /*                                                  F0BarEn*/:1 ; ///<
+    UINT32  /*                                                  F1BarEn*/:1 ; ///<
+    UINT32  /*                                                  F2BarEn*/:1 ; ///<
+    UINT32  /*                                                  PcieDis*/:1 ; ///<
+    UINT32  /*                                          BifBxcntlSpare0*/:1 ; ///<
+    UINT32  /*                                                   RcieEn*/:1 ; ///<
+    UINT32  /*                                           BifBxcntlSpare*/:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1C_STRUCT;
+
+// **** GMMx00 Register Definition ****
+// Address
+#define GMMx00_ADDRESS                                          0x0
+
+// Type
+#define GMMx00_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx00_Offset_OFFSET                                    0
+#define GMMx00_Offset_WIDTH                                     31
+#define GMMx00_Offset_MASK                                      0x7fffffff
+#define GMMx00_Aper_OFFSET                                      31
+#define GMMx00_Aper_WIDTH                                       1
+#define GMMx00_Aper_MASK                                        0x80000000
+
+/// GMMx00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   Offset:31; ///<
+    UINT32                                                     Aper:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx00_STRUCT;
+
+// **** GMMx04 Register Definition ****
+// Address
+#define GMMx04_ADDRESS                                          0x4
+
+// Type
+#define GMMx04_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx04_Data_OFFSET                                      0
+#define GMMx04_Data_WIDTH                                       32
+#define GMMx04_Data_MASK                                        0xffffffff
+
+/// GMMx04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx04_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0FE00A Register Definition ****
+// Address
+#define D18F2x09C_x0D0FE00A_ADDRESS                             0x0D0FE00A
+
+// Type
+#define D18F2x09C_x0D0FE00A_TYPE                                TYPE_D18F2x9C
+// Field Data
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET                 0
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH                  4
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK                   0xF
+#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET                   4
+#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH                    1
+#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK                     0x10
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET                5
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH                 7
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK                  0xFE0
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET               15
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH                17
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK                 0xFFFF8000
+
+/// D18F2x09C_x0D0FE00A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved_3_0:4; ///<
+    UINT32                                                SkewMemClk:1; ///<
+    UINT32                                             Reserved_11_5:7; ///<
+    UINT32                                         :2; ///<
+    UINT32                                           :1; ///<
+    UINT32                                            Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0FE00A_STRUCT;
+
+/// D0F0xE4_WRAP_8016
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CalibAckLatency:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                         CalibDoneSelPifA:1 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                           Reserved_10_10:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           Gen1OnlyEngage:1 ; ///<
+    UINT32                                          Gen1OnlyEngaged:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                       LclkDynGateLatency:6 ; ///<
+    UINT32                                             LclkGateFree:1 ; ///<
+    UINT32                                        LclkDynGateEnable:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex688_STRUCT;
+
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
new file mode 100644
index 0000000000..fc9f9d6dd6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
@@ -0,0 +1,41005 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Register definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64732 $   @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBREGISTERSTN_H_
+#define _GNBREGISTERSTN_H_
+#define  TYPE_D0F0                  0x1
+#define  TYPE_D0F0x64               0x2
+#define  TYPE_D0F0x98               0x3
+#define  TYPE_D0F0xBC               0x4
+#define  TYPE_D0F0xE4               0x5
+#define  TYPE_DxF0                  0x6
+#define  TYPE_DxF0xE4               0x7
+#define  TYPE_D0F2                  0x8
+#define  TYPE_D0F2xF4               0x9
+#define  TYPE_D0F2xFC               0xa
+#define  TYPE_D18F1                 0xb
+#define  TYPE_D18F2                 0xc
+#define  TYPE_D18F3                 0xd
+#define  TYPE_D18F4                 0xe
+#define  TYPE_D18F5                 0xf
+#define  TYPE_MSR                   0x10
+#define  TYPE_D1F0                  0x11
+#define  TYPE_GMM                   0x12
+#define  TYPE_D18F2x9C_dct0         0x13
+#define  TYPE_D18F2x9C_dct0_mp0     0x14
+#define  TYPE_D18F2x9C_dct0_mp1     0x15
+#define  TYPE_D18F2x9C_dct1         0x16
+#define  TYPE_D18F2x9C_dct1_mp0     0x17
+#define  TYPE_D18F2x9C_dct1_mp1     0x18
+#define  TYPE_D18F2_dct0            0x19
+#define  TYPE_D18F2_dct1            0x1a
+#define  TYPE_D18F2_dct0_mp0        0x1b
+#define  TYPE_D18F2_dct0_mp1        0x1c
+#define  TYPE_D1F1                  0x1d
+#define  TYPE_D18F2_dct1_mp0        0x1e
+#define  TYPE_D18F2_dct1_mp1        0x1f
+#define  TYPE_CGIND                 0x20
+#define  TYPE_SMU_MSG               0x21
+
+#ifndef WRAP_SPACE
+  #define  WRAP_SPACE(w, x)   (0x01300000 | (w << 16) | (x))
+#endif
+#ifndef CORE_SPACE
+  #define  CORE_SPACE(c, x)   (0x00010000 | (c << 24) | (x))
+#endif
+#ifndef PHY_SPACE
+  #define  PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+#ifndef PIF_SPACE
+  #define  PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+
+#define  L1_SEL_GFX                         0
+#define  L1_SEL_GPPSB                       1
+#define  L1_SEL_GBIF                        2
+#define  L1_SEL_INTGEN                      3
+
+#define  SMU_MSG_TYPE                       TYPE_SMU_MSG
+#define  SMC_MSG_FIRMWARE_AUTH              0
+#define  SMC_MSG_HALT                       1
+#define  SMC_MSG_PHY_LN_OFF                 2
+#define  SMC_MSG_PHY_LN_ON                  3
+#define  SMC_MSG_DDI_PHY_OFF                4
+#define  SMC_MSG_DDI_PHY_ON                 5
+#define  SMC_MSG_CASCADE_PLL_OFF            6
+#define  SMC_MSG_CASCADE_PLL_ON             7
+#define  SMC_MSG_PWR_OFF_x16                8
+#define  SMC_MSG_CONFIG_LCLK_DPM            9
+#define  SMC_MSG_FLUSH_DATA_CACHE           10
+#define  SMC_MSG_FLUSH_INSTRUCTION_CACHE    11
+#define  SMC_MSG_CONFIG_VPC_ACCUMULATOR     12
+#define  SMC_MSG_CONFIG_BAPM                13
+#define  SMC_MSG_CONFIG_TDC_LIMIT           14
+#define  SMC_MSG_CONFIG_LPMx                15
+#define  SMC_MSG_CONFIG_HTC_LIMIT           16
+#define  SMC_MSG_CONFIG_THERMAL_CNTL        17
+#define  SMC_MSG_CONFIG_VOLTAGE_CNTL        18
+#define  SMC_MSG_CONFIG_TDP_CNTL            19
+#define  SMC_MSG_EN_PM_CNTL                 20
+#define  SMC_MSG_DIS_PM_CNTL                21
+#define  SMC_MSG_CONFIG_NBDPM               22
+#define  SMC_MSG_CONFIG_LOADLINE            23
+#define  SMC_MSG_ADJUST_LOADLINE            24
+#define  SMC_MSG_RECONFIGURE                25
+#define  SMC_MSG_PCIE_PLLSWITCH             27
+#define  SMC_MSG_ENABLE_BAPM                32
+#define  SMC_MSG_DISABLE_BAPM               33
+
+// **** D0F0x00 Register Definition ****
+// Address
+#define D0F0x00_ADDRESS                                         0x0
+
+// Type
+#define D0F0x00_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x00_VendorID_OFFSET                                 0
+#define D0F0x00_VendorID_WIDTH                                  16
+#define D0F0x00_VendorID_MASK                                   0xffff
+#define D0F0x00_DeviceID_OFFSET                                 16
+#define D0F0x00_DeviceID_WIDTH                                  16
+#define D0F0x00_DeviceID_MASK                                   0xffff0000
+
+/// D0F0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x00_STRUCT;
+
+// **** D0F0x04 Register Definition ****
+// Address
+#define D0F0x04_ADDRESS                                         0x4
+
+// Type
+#define D0F0x04_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x04_IoAccessEn_OFFSET                               0
+#define D0F0x04_IoAccessEn_WIDTH                                1
+#define D0F0x04_IoAccessEn_MASK                                 0x1
+#define D0F0x04_MemAccessEn_OFFSET                              1
+#define D0F0x04_MemAccessEn_WIDTH                               1
+#define D0F0x04_MemAccessEn_MASK                                0x2
+#define D0F0x04_BusMasterEn_OFFSET                              2
+#define D0F0x04_BusMasterEn_WIDTH                               1
+#define D0F0x04_BusMasterEn_MASK                                0x4
+#define D0F0x04_SpecialCycleEn_OFFSET                           3
+#define D0F0x04_SpecialCycleEn_WIDTH                            1
+#define D0F0x04_SpecialCycleEn_MASK                             0x8
+#define D0F0x04_MemWriteInvalidateEn_OFFSET                     4
+#define D0F0x04_MemWriteInvalidateEn_WIDTH                      1
+#define D0F0x04_MemWriteInvalidateEn_MASK                       0x10
+#define D0F0x04_PalSnoopEn_OFFSET                               5
+#define D0F0x04_PalSnoopEn_WIDTH                                1
+#define D0F0x04_PalSnoopEn_MASK                                 0x20
+#define D0F0x04_ParityErrorEn_OFFSET                            6
+#define D0F0x04_ParityErrorEn_WIDTH                             1
+#define D0F0x04_ParityErrorEn_MASK                              0x40
+#define D0F0x04_Reserved_7_7_OFFSET                             7
+#define D0F0x04_Reserved_7_7_WIDTH                              1
+#define D0F0x04_Reserved_7_7_MASK                               0x80
+#define D0F0x04_SerrEn_OFFSET                                   8
+#define D0F0x04_SerrEn_WIDTH                                    1
+#define D0F0x04_SerrEn_MASK                                     0x100
+#define D0F0x04_FastB2BEn_OFFSET                                9
+#define D0F0x04_FastB2BEn_WIDTH                                 1
+#define D0F0x04_FastB2BEn_MASK                                  0x200
+#define D0F0x04_Reserved_19_10_OFFSET                           10
+#define D0F0x04_Reserved_19_10_WIDTH                            10
+#define D0F0x04_Reserved_19_10_MASK                             0xffc00
+#define D0F0x04_CapList_OFFSET                                  20
+#define D0F0x04_CapList_WIDTH                                   1
+#define D0F0x04_CapList_MASK                                    0x100000
+#define D0F0x04_PCI66En_OFFSET                                  21
+#define D0F0x04_PCI66En_WIDTH                                   1
+#define D0F0x04_PCI66En_MASK                                    0x200000
+#define D0F0x04_Reserved_22_22_OFFSET                           22
+#define D0F0x04_Reserved_22_22_WIDTH                            1
+#define D0F0x04_Reserved_22_22_MASK                             0x400000
+#define D0F0x04_FastBackCapable_OFFSET                          23
+#define D0F0x04_FastBackCapable_WIDTH                           1
+#define D0F0x04_FastBackCapable_MASK                            0x800000
+#define D0F0x04_Reserved_24_24_OFFSET                           24
+#define D0F0x04_Reserved_24_24_WIDTH                            1
+#define D0F0x04_Reserved_24_24_MASK                             0x1000000
+#define D0F0x04_DevselTiming_OFFSET                             25
+#define D0F0x04_DevselTiming_WIDTH                              2
+#define D0F0x04_DevselTiming_MASK                               0x6000000
+#define D0F0x04_SignalTargetAbort_OFFSET                        27
+#define D0F0x04_SignalTargetAbort_WIDTH                         1
+#define D0F0x04_SignalTargetAbort_MASK                          0x8000000
+#define D0F0x04_ReceivedTargetAbort_OFFSET                      28
+#define D0F0x04_ReceivedTargetAbort_WIDTH                       1
+#define D0F0x04_ReceivedTargetAbort_MASK                        0x10000000
+#define D0F0x04_ReceivedMasterAbort_OFFSET                      29
+#define D0F0x04_ReceivedMasterAbort_WIDTH                       1
+#define D0F0x04_ReceivedMasterAbort_MASK                        0x20000000
+#define D0F0x04_SignaledSystemError_OFFSET                      30
+#define D0F0x04_SignaledSystemError_WIDTH                       1
+#define D0F0x04_SignaledSystemError_MASK                        0x40000000
+#define D0F0x04_ParityErrorDetected_OFFSET                      31
+#define D0F0x04_ParityErrorDetected_WIDTH                       1
+#define D0F0x04_ParityErrorDetected_MASK                        0x80000000
+
+/// D0F0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                           SpecialCycleEn:1 ; ///<
+    UINT32                                     MemWriteInvalidateEn:1 ; ///<
+    UINT32                                               PalSnoopEn:1 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                FastB2BEn:1 ; ///<
+    UINT32                                           Reserved_19_10:10; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x04_STRUCT;
+
+// **** D0F0x08 Register Definition ****
+// Address
+#define D0F0x08_ADDRESS                                         0x8
+
+// Type
+#define D0F0x08_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x08_RevID_OFFSET                                    0
+#define D0F0x08_RevID_WIDTH                                     8
+#define D0F0x08_RevID_MASK                                      0xff
+#define D0F0x08_ClassCode_OFFSET                                8
+#define D0F0x08_ClassCode_WIDTH                                 24
+#define D0F0x08_ClassCode_MASK                                  0xffffff00
+
+/// D0F0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x08_STRUCT;
+
+// **** D0F0x0C Register Definition ****
+// Address
+#define D0F0x0C_ADDRESS                                         0xc
+
+// Type
+#define D0F0x0C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x0C_CacheLineSize_OFFSET                            0
+#define D0F0x0C_CacheLineSize_WIDTH                             8
+#define D0F0x0C_CacheLineSize_MASK                              0xff
+#define D0F0x0C_LatencyTimer_OFFSET                             8
+#define D0F0x0C_LatencyTimer_WIDTH                              8
+#define D0F0x0C_LatencyTimer_MASK                               0xff00
+#define D0F0x0C_HeaderTypeReg_OFFSET                            16
+#define D0F0x0C_HeaderTypeReg_WIDTH                             8
+#define D0F0x0C_HeaderTypeReg_MASK                              0xff0000
+#define D0F0x0C_BIST_OFFSET                                     24
+#define D0F0x0C_BIST_WIDTH                                      8
+#define D0F0x0C_BIST_MASK                                       0xff000000
+
+/// D0F0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x0C_STRUCT;
+
+// **** D0F0x2C Register Definition ****
+// Address
+#define D0F0x2C_ADDRESS                                         0x2c
+
+// Type
+#define D0F0x2C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x2C_SubsystemVendorID_OFFSET                        0
+#define D0F0x2C_SubsystemVendorID_WIDTH                         16
+#define D0F0x2C_SubsystemVendorID_MASK                          0xffff
+#define D0F0x2C_SubsystemID_OFFSET                              16
+#define D0F0x2C_SubsystemID_WIDTH                               16
+#define D0F0x2C_SubsystemID_MASK                                0xffff0000
+
+/// D0F0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorID:16; ///<
+    UINT32                                              SubsystemID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x2C_STRUCT;
+
+// **** D0F0x34 Register Definition ****
+// Address
+#define D0F0x34_ADDRESS                                         0x34
+
+// Type
+#define D0F0x34_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x34_CapPtr_OFFSET                                   0
+#define D0F0x34_CapPtr_WIDTH                                    8
+#define D0F0x34_CapPtr_MASK                                     0xff
+#define D0F0x34_Reserved_31_8_OFFSET                            8
+#define D0F0x34_Reserved_31_8_WIDTH                             24
+#define D0F0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x34_STRUCT;
+
+// **** D0F0x4C Register Definition ****
+// Address
+#define D0F0x4C_ADDRESS                                         0x4c
+
+// Type
+#define D0F0x4C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x4C_Function1Enable_OFFSET                          0
+#define D0F0x4C_Function1Enable_WIDTH                           1
+#define D0F0x4C_Function1Enable_MASK                            0x1
+#define D0F0x4C_ApicEnable_OFFSET                               1
+#define D0F0x4C_ApicEnable_WIDTH                                1
+#define D0F0x4C_ApicEnable_MASK                                 0x2
+#define D0F0x4C_Reserved_2_2_OFFSET                             2
+#define D0F0x4C_Reserved_2_2_WIDTH                              1
+#define D0F0x4C_Reserved_2_2_MASK                               0x4
+#define D0F0x4C_Cf8Dis_OFFSET                                   3
+#define D0F0x4C_Cf8Dis_WIDTH                                    1
+#define D0F0x4C_Cf8Dis_MASK                                     0x8
+#define D0F0x4C_PMEDis_OFFSET                                   4
+#define D0F0x4C_PMEDis_WIDTH                                    1
+#define D0F0x4C_PMEDis_MASK                                     0x10
+#define D0F0x4C_SerrDis_OFFSET                                  5
+#define D0F0x4C_SerrDis_WIDTH                                   1
+#define D0F0x4C_SerrDis_MASK                                    0x20
+#define D0F0x4C_Reserved_10_6_OFFSET                            6
+#define D0F0x4C_Reserved_10_6_WIDTH                             5
+#define D0F0x4C_Reserved_10_6_MASK                              0x7c0
+#define D0F0x4C_CRS_OFFSET                                      11
+#define D0F0x4C_CRS_WIDTH                                       1
+#define D0F0x4C_CRS_MASK                                        0x800
+#define D0F0x4C_CfgRdTime_OFFSET                                12
+#define D0F0x4C_CfgRdTime_WIDTH                                 3
+#define D0F0x4C_CfgRdTime_MASK                                  0x7000
+#define D0F0x4C_Reserved_22_15_OFFSET                           15
+#define D0F0x4C_Reserved_22_15_WIDTH                            8
+#define D0F0x4C_Reserved_22_15_MASK                             0x7f8000
+#define D0F0x4C_MMIOEnable_OFFSET                               23
+#define D0F0x4C_MMIOEnable_WIDTH                                1
+#define D0F0x4C_MMIOEnable_MASK                                 0x800000
+#define D0F0x4C_Reserved_25_24_OFFSET                           24
+#define D0F0x4C_Reserved_25_24_WIDTH                            2
+#define D0F0x4C_Reserved_25_24_MASK                             0x3000000
+#define D0F0x4C_HPDis_OFFSET                                    26
+#define D0F0x4C_HPDis_WIDTH                                     1
+#define D0F0x4C_HPDis_MASK                                      0x4000000
+#define D0F0x4C_Reserved_31_27_OFFSET                           27
+#define D0F0x4C_Reserved_31_27_WIDTH                            5
+#define D0F0x4C_Reserved_31_27_MASK                             0xf8000000
+
+/// D0F0x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          Function1Enable:1 ; ///<
+    UINT32                                               ApicEnable:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                   Cf8Dis:1 ; ///<
+    UINT32                                                   PMEDis:1 ; ///<
+    UINT32                                                  SerrDis:1 ; ///<
+    UINT32                                            Reserved_10_6:5 ; ///<
+    UINT32                                                      CRS:1 ; ///<
+    UINT32                                                CfgRdTime:3 ; ///<
+    UINT32                                           Reserved_22_15:8 ; ///<
+    UINT32                                               MMIOEnable:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    HPDis:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x4C_STRUCT;
+
+// **** D0F0x60 Register Definition ****
+// Address
+#define D0F0x60_ADDRESS                                         0x60
+
+// Type
+#define D0F0x60_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x60_MiscIndAddr_OFFSET                              0
+#define D0F0x60_MiscIndAddr_WIDTH                               7
+#define D0F0x60_MiscIndAddr_MASK                                0x7f
+#define D0F0x60_MiscIndWrEn_OFFSET                              7
+#define D0F0x60_MiscIndWrEn_WIDTH                               1
+#define D0F0x60_MiscIndWrEn_MASK                                0x80
+#define D0F0x60_Reserved_31_8_OFFSET                            8
+#define D0F0x60_Reserved_31_8_WIDTH                             24
+#define D0F0x60_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndAddr:7 ; ///<
+    UINT32                                              MiscIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x60_STRUCT;
+
+// **** D0F0x64 Register Definition ****
+// Address
+#define D0F0x64_ADDRESS                                         0x64
+
+// Type
+#define D0F0x64_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x64_MiscIndData_OFFSET                              0
+#define D0F0x64_MiscIndData_WIDTH                               32
+#define D0F0x64_MiscIndData_MASK                                0xffffffff
+
+/// D0F0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_STRUCT;
+
+// **** D0F0x7C Register Definition ****
+// Address
+#define D0F0x7C_ADDRESS                                         0x7c
+
+// Type
+#define D0F0x7C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x7C_ForceIntGFXDisable_OFFSET                       0
+#define D0F0x7C_ForceIntGFXDisable_WIDTH                        1
+#define D0F0x7C_ForceIntGFXDisable_MASK                         0x1
+#define D0F0x7C_Reserved_31_1_OFFSET                            1
+#define D0F0x7C_Reserved_31_1_WIDTH                             31
+#define D0F0x7C_Reserved_31_1_MASK                              0xfffffffe
+
+/// D0F0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       ForceIntGFXDisable:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x7C_STRUCT;
+
+// **** D0F0x84 Register Definition ****
+// Address
+#define D0F0x84_ADDRESS                                         0x84
+
+// Type
+#define D0F0x84_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x84_Reserved_2_0_OFFSET                             0
+#define D0F0x84_Reserved_2_0_WIDTH                              3
+#define D0F0x84_Reserved_2_0_MASK                               0x7
+#define D0F0x84_VgaHole_OFFSET                                  3
+#define D0F0x84_VgaHole_WIDTH                                   1
+#define D0F0x84_VgaHole_MASK                                    0x8
+#define D0F0x84_Ev6Mode_OFFSET                                  4
+#define D0F0x84_Ev6Mode_WIDTH                                   1
+#define D0F0x84_Ev6Mode_MASK                                    0x10
+#define D0F0x84_Reserved_7_5_OFFSET                             5
+#define D0F0x84_Reserved_7_5_WIDTH                              3
+#define D0F0x84_Reserved_7_5_MASK                               0xe0
+#define D0F0x84_PmeMode_OFFSET                                  8
+#define D0F0x84_PmeMode_WIDTH                                   1
+#define D0F0x84_PmeMode_MASK                                    0x100
+#define D0F0x84_PmeTurnOff_OFFSET                               9
+#define D0F0x84_PmeTurnOff_WIDTH                                1
+#define D0F0x84_PmeTurnOff_MASK                                 0x200
+#define D0F0x84_Reserved_31_10_OFFSET                           10
+#define D0F0x84_Reserved_31_10_WIDTH                            22
+#define D0F0x84_Reserved_31_10_MASK                             0xfffffc00
+
+/// D0F0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                  VgaHole:1 ; ///<
+    UINT32                                                  Ev6Mode:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                  PmeMode:1 ; ///<
+    UINT32                                               PmeTurnOff:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x84_STRUCT;
+
+// **** D0F0x90 Register Definition ****
+// Address
+#define D0F0x90_ADDRESS                                         0x90
+
+// Type
+#define D0F0x90_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x90_Reserved_22_0_OFFSET                            0
+#define D0F0x90_Reserved_22_0_WIDTH                             23
+#define D0F0x90_Reserved_22_0_MASK                              0x7fffff
+#define D0F0x90_TopOfDram_OFFSET                                23
+#define D0F0x90_TopOfDram_WIDTH                                 9
+#define D0F0x90_TopOfDram_MASK                                  0xff800000
+
+/// D0F0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                                TopOfDram:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x90_STRUCT;
+
+// **** D0F0x94 Register Definition ****
+// Address
+#define D0F0x94_ADDRESS                                         0x94
+
+// Type
+#define D0F0x94_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x94_OrbIndAddr_OFFSET                               0
+#define D0F0x94_OrbIndAddr_WIDTH                                7
+#define D0F0x94_OrbIndAddr_MASK                                 0x7f
+#define D0F0x94_Reserved_7_7_OFFSET                             7
+#define D0F0x94_Reserved_7_7_WIDTH                              1
+#define D0F0x94_Reserved_7_7_MASK                               0x80
+#define D0F0x94_OrbIndWrEn_OFFSET                               8
+#define D0F0x94_OrbIndWrEn_WIDTH                                1
+#define D0F0x94_OrbIndWrEn_MASK                                 0x100
+#define D0F0x94_Reserved_31_9_OFFSET                            9
+#define D0F0x94_Reserved_31_9_WIDTH                             23
+#define D0F0x94_Reserved_31_9_MASK                              0xfffffe00
+
+/// D0F0x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndAddr:7 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                               OrbIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x94_STRUCT;
+
+// **** D0F0x98 Register Definition ****
+// Address
+#define D0F0x98_ADDRESS                                         0x98
+
+// Type
+#define D0F0x98_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x98_OrbIndData_OFFSET                               0
+#define D0F0x98_OrbIndData_WIDTH                                32
+#define D0F0x98_OrbIndData_MASK                                 0xffffffff
+
+/// D0F0x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_STRUCT;
+
+// **** D0F0xB8 Register Definition ****
+// Address
+#define D0F0xB8_ADDRESS                                         0xb8
+
+// Type
+#define D0F0xB8_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xB8_NbSmuIndAddr_OFFSET                             0
+#define D0F0xB8_NbSmuIndAddr_WIDTH                              32
+#define D0F0xB8_NbSmuIndAddr_MASK                               0xffffffff
+
+/// D0F0xB8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NbSmuIndAddr:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xB8_STRUCT;
+
+// **** D0F0xBC Register Definition ****
+// Address
+#define D0F0xBC_ADDRESS                                         0xbc
+
+// Type
+#define D0F0xBC_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xBC_NbSmuIndData_OFFSET                             0
+#define D0F0xBC_NbSmuIndData_WIDTH                              32
+#define D0F0xBC_NbSmuIndData_MASK                               0xffffffff
+
+/// D0F0xBC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NbSmuIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_STRUCT;
+
+// **** D0F0xE0 Register Definition ****
+// Address
+#define D0F0xE0_ADDRESS                                         0xe0
+
+// Type
+#define D0F0xE0_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE0_PcieIndxAddr_OFFSET                             0
+#define D0F0xE0_PcieIndxAddr_WIDTH                              16
+#define D0F0xE0_PcieIndxAddr_MASK                               0xffff
+#define D0F0xE0_FrameType_OFFSET                                16
+#define D0F0xE0_FrameType_WIDTH                                 8
+#define D0F0xE0_FrameType_MASK                                  0xff0000
+#define D0F0xE0_BlockSelect_OFFSET                              24
+#define D0F0xE0_BlockSelect_WIDTH                               8
+#define D0F0xE0_BlockSelect_MASK                                0xff000000
+
+/// D0F0xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxAddr:16; ///<
+    UINT32                                                FrameType:8 ; ///<
+    UINT32                                              BlockSelect:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE0_STRUCT;
+
+// **** D0F0xE4 Register Definition ****
+// Address
+#define D0F0xE4_ADDRESS                                         0xe4
+
+// Type
+#define D0F0xE4_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE4_PcieIndxData_OFFSET                             0
+#define D0F0xE4_PcieIndxData_WIDTH                              32
+#define D0F0xE4_PcieIndxData_MASK                               0xffffffff
+
+/// D0F0xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_STRUCT;
+
+// **** D0F2x00 Register Definition ****
+// Address
+#define D0F2x00_ADDRESS                                         0x0
+
+// Type
+#define D0F2x00_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x00_VendorId_OFFSET                                 0
+#define D0F2x00_VendorId_WIDTH                                  16
+#define D0F2x00_VendorId_MASK                                   0xffff
+#define D0F2x00_DeviceId_OFFSET                                 16
+#define D0F2x00_DeviceId_WIDTH                                  16
+#define D0F2x00_DeviceId_MASK                                   0xffff0000
+
+/// D0F2x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorId:16; ///<
+    UINT32                                                 DeviceId:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x00_STRUCT;
+
+// **** D0F2x04 Register Definition ****
+// Address
+#define D0F2x04_ADDRESS                                         0x4
+
+// Type
+#define D0F2x04_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x04_IoAccessEn_OFFSET                               0
+#define D0F2x04_IoAccessEn_WIDTH                                1
+#define D0F2x04_IoAccessEn_MASK                                 0x1
+#define D0F2x04_MemAccessEn_OFFSET                              1
+#define D0F2x04_MemAccessEn_WIDTH                               1
+#define D0F2x04_MemAccessEn_MASK                                0x2
+#define D0F2x04_BusMasterEn_OFFSET                              2
+#define D0F2x04_BusMasterEn_WIDTH                               1
+#define D0F2x04_BusMasterEn_MASK                                0x4
+#define D0F2x04_Reserved_5_3_OFFSET                             3
+#define D0F2x04_Reserved_5_3_WIDTH                              3
+#define D0F2x04_Reserved_5_3_MASK                               0x38
+#define D0F2x04_ParityErrorEn_OFFSET                            6
+#define D0F2x04_ParityErrorEn_WIDTH                             1
+#define D0F2x04_ParityErrorEn_MASK                              0x40
+#define D0F2x04_Reserved_7_7_OFFSET                             7
+#define D0F2x04_Reserved_7_7_WIDTH                              1
+#define D0F2x04_Reserved_7_7_MASK                               0x80
+#define D0F2x04_SerrEn_OFFSET                                   8
+#define D0F2x04_SerrEn_WIDTH                                    1
+#define D0F2x04_SerrEn_MASK                                     0x100
+#define D0F2x04_Reserved_9_9_OFFSET                             9
+#define D0F2x04_Reserved_9_9_WIDTH                              1
+#define D0F2x04_Reserved_9_9_MASK                               0x200
+#define D0F2x04_InterruptDis_OFFSET                             10
+#define D0F2x04_InterruptDis_WIDTH                              1
+#define D0F2x04_InterruptDis_MASK                               0x400
+#define D0F2x04_Reserved_18_11_OFFSET                           11
+#define D0F2x04_Reserved_18_11_WIDTH                            8
+#define D0F2x04_Reserved_18_11_MASK                             0x7f800
+#define D0F2x04_IntStatus_OFFSET                                19
+#define D0F2x04_IntStatus_WIDTH                                 1
+#define D0F2x04_IntStatus_MASK                                  0x80000
+#define D0F2x04_CapList_OFFSET                                  20
+#define D0F2x04_CapList_WIDTH                                   1
+#define D0F2x04_CapList_MASK                                    0x100000
+#define D0F2x04_Reserved_23_21_OFFSET                           21
+#define D0F2x04_Reserved_23_21_WIDTH                            3
+#define D0F2x04_Reserved_23_21_MASK                             0xe00000
+#define D0F2x04_MasterDataError_OFFSET                          24
+#define D0F2x04_MasterDataError_WIDTH                           1
+#define D0F2x04_MasterDataError_MASK                            0x1000000
+#define D0F2x04_Reserved_26_25_OFFSET                           25
+#define D0F2x04_Reserved_26_25_WIDTH                            2
+#define D0F2x04_Reserved_26_25_MASK                             0x6000000
+#define D0F2x04_SignalTargetAbort_OFFSET                        27
+#define D0F2x04_SignalTargetAbort_WIDTH                         1
+#define D0F2x04_SignalTargetAbort_MASK                          0x8000000
+#define D0F2x04_ReceivedTargetAbort_OFFSET                      28
+#define D0F2x04_ReceivedTargetAbort_WIDTH                       1
+#define D0F2x04_ReceivedTargetAbort_MASK                        0x10000000
+#define D0F2x04_ReceivedMasterAbort_OFFSET                      29
+#define D0F2x04_ReceivedMasterAbort_WIDTH                       1
+#define D0F2x04_ReceivedMasterAbort_MASK                        0x20000000
+#define D0F2x04_SignaledSystemError_OFFSET                      30
+#define D0F2x04_SignaledSystemError_WIDTH                       1
+#define D0F2x04_SignaledSystemError_MASK                        0x40000000
+#define D0F2x04_ParityErrorDetected_OFFSET                      31
+#define D0F2x04_ParityErrorDetected_WIDTH                       1
+#define D0F2x04_ParityErrorDetected_MASK                        0x80000000
+
+/// D0F2x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                             Reserved_5_3:3 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             InterruptDis:1 ; ///<
+    UINT32                                           Reserved_18_11:8 ; ///<
+    UINT32                                                IntStatus:1 ; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                          MasterDataError:1 ; ///<
+    UINT32                                           Reserved_26_25:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x04_STRUCT;
+
+// **** D0F2x08 Register Definition ****
+// Address
+#define D0F2x08_ADDRESS                                         0x8
+
+// Type
+#define D0F2x08_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x08_RevID_OFFSET                                    0
+#define D0F2x08_RevID_WIDTH                                     8
+#define D0F2x08_RevID_MASK                                      0xff
+#define D0F2x08_ClassCode_OFFSET                                8
+#define D0F2x08_ClassCode_WIDTH                                 24
+#define D0F2x08_ClassCode_MASK                                  0xffffff00
+
+/// D0F2x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x08_STRUCT;
+
+// **** D0F2x0C Register Definition ****
+// Address
+#define D0F2x0C_ADDRESS                                         0xc
+
+// Type
+#define D0F2x0C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x0C_CacheLineSize_OFFSET                            0
+#define D0F2x0C_CacheLineSize_WIDTH                             8
+#define D0F2x0C_CacheLineSize_MASK                              0xff
+#define D0F2x0C_LatencyTimer_OFFSET                             8
+#define D0F2x0C_LatencyTimer_WIDTH                              8
+#define D0F2x0C_LatencyTimer_MASK                               0xff00
+#define D0F2x0C_HeaderTypeReg_OFFSET                            16
+#define D0F2x0C_HeaderTypeReg_WIDTH                             8
+#define D0F2x0C_HeaderTypeReg_MASK                              0xff0000
+#define D0F2x0C_BIST_OFFSET                                     24
+#define D0F2x0C_BIST_WIDTH                                      8
+#define D0F2x0C_BIST_MASK                                       0xff000000
+
+/// D0F2x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x0C_STRUCT;
+
+// **** D0F2x2C Register Definition ****
+// Address
+#define D0F2x2C_ADDRESS                                         0x2c
+
+// Type
+#define D0F2x2C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x2C_SubsystemVendorId_OFFSET                        0
+#define D0F2x2C_SubsystemVendorId_WIDTH                         16
+#define D0F2x2C_SubsystemVendorId_MASK                          0xffff
+#define D0F2x2C_SubsystemId_OFFSET                              16
+#define D0F2x2C_SubsystemId_WIDTH                               16
+#define D0F2x2C_SubsystemId_MASK                                0xffff0000
+
+/// D0F2x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorId:16; ///<
+    UINT32                                              SubsystemId:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x2C_STRUCT;
+
+// **** D0F2x34 Register Definition ****
+// Address
+#define D0F2x34_ADDRESS                                         0x34
+
+// Type
+#define D0F2x34_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x34_CapPtr_OFFSET                                   0
+#define D0F2x34_CapPtr_WIDTH                                    8
+#define D0F2x34_CapPtr_MASK                                     0xff
+#define D0F2x34_Reserved_31_8_OFFSET                            8
+#define D0F2x34_Reserved_31_8_WIDTH                             24
+#define D0F2x34_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F2x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x34_STRUCT;
+
+// **** D0F2x3C Register Definition ****
+// Address
+#define D0F2x3C_ADDRESS                                         0x3c
+
+// Type
+#define D0F2x3C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x3C_InterruptLine_OFFSET                            0
+#define D0F2x3C_InterruptLine_WIDTH                             8
+#define D0F2x3C_InterruptLine_MASK                              0xff
+#define D0F2x3C_InterruptPin_OFFSET                             8
+#define D0F2x3C_InterruptPin_WIDTH                              8
+#define D0F2x3C_InterruptPin_MASK                               0xff00
+#define D0F2x3C_Reserved_31_16_OFFSET                           16
+#define D0F2x3C_Reserved_31_16_WIDTH                            16
+#define D0F2x3C_Reserved_31_16_MASK                             0xffff0000
+
+/// D0F2x3C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            InterruptLine:8 ; ///<
+    UINT32                                             InterruptPin:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x3C_STRUCT;
+
+// **** D0F2x40 Register Definition ****
+// Address
+#define D0F2x40_ADDRESS                                         0x40
+
+// Type
+#define D0F2x40_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x40_IommuCapId_OFFSET                               0
+#define D0F2x40_IommuCapId_WIDTH                                8
+#define D0F2x40_IommuCapId_MASK                                 0xff
+#define D0F2x40_IommuCapPtr_OFFSET                              8
+#define D0F2x40_IommuCapPtr_WIDTH                               8
+#define D0F2x40_IommuCapPtr_MASK                                0xff00
+#define D0F2x40_IommuCapType_OFFSET                             16
+#define D0F2x40_IommuCapType_WIDTH                              3
+#define D0F2x40_IommuCapType_MASK                               0x70000
+#define D0F2x40_IommuCapRev_OFFSET                              19
+#define D0F2x40_IommuCapRev_WIDTH                               5
+#define D0F2x40_IommuCapRev_MASK                                0xf80000
+#define D0F2x40_IommuIoTlbsup_OFFSET                            24
+#define D0F2x40_IommuIoTlbsup_WIDTH                             1
+#define D0F2x40_IommuIoTlbsup_MASK                              0x1000000
+#define D0F2x40_IommuHtTunnelSup_OFFSET                         25
+#define D0F2x40_IommuHtTunnelSup_WIDTH                          1
+#define D0F2x40_IommuHtTunnelSup_MASK                           0x2000000
+#define D0F2x40_IommuNpCache_OFFSET                             26
+#define D0F2x40_IommuNpCache_WIDTH                              1
+#define D0F2x40_IommuNpCache_MASK                               0x4000000
+#define D0F2x40_IommuEfrSup_OFFSET                              27
+#define D0F2x40_IommuEfrSup_WIDTH                               1
+#define D0F2x40_IommuEfrSup_MASK                                0x8000000
+#define D0F2x40_Reserved_31_28_OFFSET                           28
+#define D0F2x40_Reserved_31_28_WIDTH                            4
+#define D0F2x40_Reserved_31_28_MASK                             0xf0000000
+
+/// D0F2x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IommuCapId:8 ; ///<
+    UINT32                                              IommuCapPtr:8 ; ///<
+    UINT32                                             IommuCapType:3 ; ///<
+    UINT32                                              IommuCapRev:5 ; ///<
+    UINT32                                            IommuIoTlbsup:1 ; ///<
+    UINT32                                         IommuHtTunnelSup:1 ; ///<
+    UINT32                                             IommuNpCache:1 ; ///<
+    UINT32                                              IommuEfrSup:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x40_STRUCT;
+
+// **** D0F2x44 Register Definition ****
+// Address
+#define D0F2x44_ADDRESS                                         0x44
+
+// Type
+#define D0F2x44_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x44_IommuEnable_OFFSET                              0
+#define D0F2x44_IommuEnable_WIDTH                               1
+#define D0F2x44_IommuEnable_MASK                                0x1
+#define D0F2x44_Reserved_13_1_OFFSET                            1
+#define D0F2x44_Reserved_13_1_WIDTH                             13
+#define D0F2x44_Reserved_13_1_MASK                              0x3ffe
+#define D0F2x44_IommuBaseAddr_31_14__OFFSET                     14
+#define D0F2x44_IommuBaseAddr_31_14__WIDTH                      18
+#define D0F2x44_IommuBaseAddr_31_14__MASK                       0xffffc000
+
+/// D0F2x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IommuEnable:1 ; ///<
+    UINT32                                            Reserved_13_1:13; ///<
+    UINT32                                     IommuBaseAddr_31_14_:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x44_STRUCT;
+
+// **** D0F2x48 Register Definition ****
+// Address
+#define D0F2x48_ADDRESS                                         0x48
+
+// Type
+#define D0F2x48_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x48_IommuBaseAddr_63_32__OFFSET                     0
+#define D0F2x48_IommuBaseAddr_63_32__WIDTH                      32
+#define D0F2x48_IommuBaseAddr_63_32__MASK                       0xffffffff
+
+/// D0F2x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     IommuBaseAddr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x48_STRUCT;
+
+// **** D0F2x4C Register Definition ****
+// Address
+#define D0F2x4C_ADDRESS                                         0x4c
+
+// Type
+#define D0F2x4C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x4C_IommuUnitId_OFFSET                              0
+#define D0F2x4C_IommuUnitId_WIDTH                               5
+#define D0F2x4C_IommuUnitId_MASK                                0x1f
+#define D0F2x4C_Reserved_6_5_OFFSET                             5
+#define D0F2x4C_Reserved_6_5_WIDTH                              2
+#define D0F2x4C_Reserved_6_5_MASK                               0x60
+#define D0F2x4C_IommuRngValid_OFFSET                            7
+#define D0F2x4C_IommuRngValid_WIDTH                             1
+#define D0F2x4C_IommuRngValid_MASK                              0x80
+#define D0F2x4C_IommuBusNumber_OFFSET                           8
+#define D0F2x4C_IommuBusNumber_WIDTH                            8
+#define D0F2x4C_IommuBusNumber_MASK                             0xff00
+#define D0F2x4C_IommuFirstDevice_OFFSET                         16
+#define D0F2x4C_IommuFirstDevice_WIDTH                          8
+#define D0F2x4C_IommuFirstDevice_MASK                           0xff0000
+#define D0F2x4C_IommuLastDevice_OFFSET                          24
+#define D0F2x4C_IommuLastDevice_WIDTH                           8
+#define D0F2x4C_IommuLastDevice_MASK                            0xff000000
+
+/// D0F2x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IommuUnitId:5 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                            IommuRngValid:1 ; ///<
+    UINT32                                           IommuBusNumber:8 ; ///<
+    UINT32                                         IommuFirstDevice:8 ; ///<
+    UINT32                                          IommuLastDevice:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x4C_STRUCT;
+
+// **** D0F2x50 Register Definition ****
+// Address
+#define D0F2x50_ADDRESS                                         0x50
+
+// Type
+#define D0F2x50_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x50_IommuMsiNum_OFFSET                              0
+#define D0F2x50_IommuMsiNum_WIDTH                               5
+#define D0F2x50_IommuMsiNum_MASK                                0x1f
+#define D0F2x50_IommuGvaSize_OFFSET                             5
+#define D0F2x50_IommuGvaSize_WIDTH                              3
+#define D0F2x50_IommuGvaSize_MASK                               0xe0
+#define D0F2x50_IommuPaSize_OFFSET                              8
+#define D0F2x50_IommuPaSize_WIDTH                               7
+#define D0F2x50_IommuPaSize_MASK                                0x7f00
+#define D0F2x50_IommuVaSize_OFFSET                              15
+#define D0F2x50_IommuVaSize_WIDTH                               7
+#define D0F2x50_IommuVaSize_MASK                                0x3f8000
+#define D0F2x50_IommuHtAtsResv_OFFSET                           22
+#define D0F2x50_IommuHtAtsResv_WIDTH                            1
+#define D0F2x50_IommuHtAtsResv_MASK                             0x400000
+#define D0F2x50_Reserved_26_23_OFFSET                           23
+#define D0F2x50_Reserved_26_23_WIDTH                            4
+#define D0F2x50_Reserved_26_23_MASK                             0x7800000
+#define D0F2x50_IommuMsiNumPpr_OFFSET                           27
+#define D0F2x50_IommuMsiNumPpr_WIDTH                            5
+#define D0F2x50_IommuMsiNumPpr_MASK                             0xf8000000
+
+/// D0F2x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IommuMsiNum:5 ; ///<
+    UINT32                                             IommuGvaSize:3 ; ///<
+    UINT32                                              IommuPaSize:7 ; ///<
+    UINT32                                              IommuVaSize:7 ; ///<
+    UINT32                                           IommuHtAtsResv:1 ; ///<
+    UINT32                                           Reserved_26_23:4 ; ///<
+    UINT32                                           IommuMsiNumPpr:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x50_STRUCT;
+
+// **** D0F2x54 Register Definition ****
+// Address
+#define D0F2x54_ADDRESS                                         0x54
+
+// Type
+#define D0F2x54_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x54_MsiCapId_OFFSET                                 0
+#define D0F2x54_MsiCapId_WIDTH                                  8
+#define D0F2x54_MsiCapId_MASK                                   0xff
+#define D0F2x54_MsiCapPtr_OFFSET                                8
+#define D0F2x54_MsiCapPtr_WIDTH                                 8
+#define D0F2x54_MsiCapPtr_MASK                                  0xff00
+#define D0F2x54_MsiEn_OFFSET                                    16
+#define D0F2x54_MsiEn_WIDTH                                     1
+#define D0F2x54_MsiEn_MASK                                      0x10000
+#define D0F2x54_MsiMultMessCap_OFFSET                           17
+#define D0F2x54_MsiMultMessCap_WIDTH                            3
+#define D0F2x54_MsiMultMessCap_MASK                             0xe0000
+#define D0F2x54_MsiMultMessEn_OFFSET                            20
+#define D0F2x54_MsiMultMessEn_WIDTH                             3
+#define D0F2x54_MsiMultMessEn_MASK                              0x700000
+#define D0F2x54_Msi64En_OFFSET                                  23
+#define D0F2x54_Msi64En_WIDTH                                   1
+#define D0F2x54_Msi64En_MASK                                    0x800000
+#define D0F2x54_Reserved_31_24_OFFSET                           24
+#define D0F2x54_Reserved_31_24_WIDTH                            8
+#define D0F2x54_Reserved_31_24_MASK                             0xff000000
+
+/// D0F2x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 MsiCapId:8 ; ///<
+    UINT32                                                MsiCapPtr:8 ; ///<
+    UINT32                                                    MsiEn:1 ; ///<
+    UINT32                                           MsiMultMessCap:3 ; ///<
+    UINT32                                            MsiMultMessEn:3 ; ///<
+    UINT32                                                  Msi64En:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x54_STRUCT;
+
+// **** D0F2x58 Register Definition ****
+// Address
+#define D0F2x58_ADDRESS                                         0x58
+
+// Type
+#define D0F2x58_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x58_Reserved_1_0_OFFSET                             0
+#define D0F2x58_Reserved_1_0_WIDTH                              2
+#define D0F2x58_Reserved_1_0_MASK                               0x3
+#define D0F2x58_MsiAddr_31_2__OFFSET                            2
+#define D0F2x58_MsiAddr_31_2__WIDTH                             30
+#define D0F2x58_MsiAddr_31_2__MASK                              0xfffffffc
+
+/// D0F2x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            MsiAddr_31_2_:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x58_STRUCT;
+
+// **** D0F2x5C Register Definition ****
+// Address
+#define D0F2x5C_ADDRESS                                         0x5c
+
+// Type
+#define D0F2x5C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x5C_MsiAddr_63_32__OFFSET                           0
+#define D0F2x5C_MsiAddr_63_32__WIDTH                            32
+#define D0F2x5C_MsiAddr_63_32__MASK                             0xffffffff
+
+/// D0F2x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MsiAddr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x5C_STRUCT;
+
+// **** D0F2x60 Register Definition ****
+// Address
+#define D0F2x60_ADDRESS                                         0x60
+
+// Type
+#define D0F2x60_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x60_MsiData_OFFSET                                  0
+#define D0F2x60_MsiData_WIDTH                                   16
+#define D0F2x60_MsiData_MASK                                    0xffff
+#define D0F2x60_Reserved_31_16_OFFSET                           16
+#define D0F2x60_Reserved_31_16_WIDTH                            16
+#define D0F2x60_Reserved_31_16_MASK                             0xffff0000
+
+/// D0F2x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  MsiData:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x60_STRUCT;
+
+// **** D0F2x64 Register Definition ****
+// Address
+#define D0F2x64_ADDRESS                                         0x64
+
+// Type
+#define D0F2x64_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x64_MsiMapCapId_OFFSET                              0
+#define D0F2x64_MsiMapCapId_WIDTH                               8
+#define D0F2x64_MsiMapCapId_MASK                                0xff
+#define D0F2x64_MsiMapCapPtr_OFFSET                             8
+#define D0F2x64_MsiMapCapPtr_WIDTH                              8
+#define D0F2x64_MsiMapCapPtr_MASK                               0xff00
+#define D0F2x64_MsiMapEn_OFFSET                                 16
+#define D0F2x64_MsiMapEn_WIDTH                                  1
+#define D0F2x64_MsiMapEn_MASK                                   0x10000
+#define D0F2x64_MsiMapFixd_OFFSET                               17
+#define D0F2x64_MsiMapFixd_WIDTH                                1
+#define D0F2x64_MsiMapFixd_MASK                                 0x20000
+#define D0F2x64_Reserved_26_18_OFFSET                           18
+#define D0F2x64_Reserved_26_18_WIDTH                            9
+#define D0F2x64_Reserved_26_18_MASK                             0x7fc0000
+#define D0F2x64_MsiMapCapType_OFFSET                            27
+#define D0F2x64_MsiMapCapType_WIDTH                             5
+#define D0F2x64_MsiMapCapType_MASK                              0xf8000000
+
+/// D0F2x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MsiMapCapId:8 ; ///<
+    UINT32                                             MsiMapCapPtr:8 ; ///<
+    UINT32                                                 MsiMapEn:1 ; ///<
+    UINT32                                               MsiMapFixd:1 ; ///<
+    UINT32                                           Reserved_26_18:9 ; ///<
+    UINT32                                            MsiMapCapType:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x64_STRUCT;
+
+// **** D0F2x6C Register Definition ****
+// Address
+#define D0F2x6C_ADDRESS                                         0x6c
+
+// Type
+#define D0F2x6C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x6C_InterruptPinW_OFFSET                            0
+#define D0F2x6C_InterruptPinW_WIDTH                             3
+#define D0F2x6C_InterruptPinW_MASK                              0x7
+#define D0F2x6C_Reserved_3_3_OFFSET                             3
+#define D0F2x6C_Reserved_3_3_WIDTH                              1
+#define D0F2x6C_Reserved_3_3_MASK                               0x8
+#define D0F2x6C_MinorRevIdW_OFFSET                              4
+#define D0F2x6C_MinorRevIdW_WIDTH                               4
+#define D0F2x6C_MinorRevIdW_MASK                                0xf0
+#define D0F2x6C_IoTlbsupW_OFFSET                                8
+#define D0F2x6C_IoTlbsupW_WIDTH                                 1
+#define D0F2x6C_IoTlbsupW_MASK                                  0x100
+#define D0F2x6C_EfrSupW_OFFSET                                  9
+#define D0F2x6C_EfrSupW_WIDTH                                   1
+#define D0F2x6C_EfrSupW_MASK                                    0x200
+#define D0F2x6C_Reserved_31_10_OFFSET                           10
+#define D0F2x6C_Reserved_31_10_WIDTH                            22
+#define D0F2x6C_Reserved_31_10_MASK                             0xfffffc00
+
+/// D0F2x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            InterruptPinW:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                              MinorRevIdW:4 ; ///<
+    UINT32                                                IoTlbsupW:1 ; ///<
+    UINT32                                                  EfrSupW:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x6C_STRUCT;
+
+// **** D0F2x70 Register Definition ****
+// Address
+#define D0F2x70_ADDRESS                                         0x70
+
+// Type
+#define D0F2x70_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x70_PrefSupW_OFFSET                                 0
+#define D0F2x70_PrefSupW_WIDTH                                  1
+#define D0F2x70_PrefSupW_MASK                                   0x1
+#define D0F2x70_PprSupW_OFFSET                                  1
+#define D0F2x70_PprSupW_WIDTH                                   1
+#define D0F2x70_PprSupW_MASK                                    0x2
+#define D0F2x70_Reserved_2_2_OFFSET                             2
+#define D0F2x70_Reserved_2_2_WIDTH                              1
+#define D0F2x70_Reserved_2_2_MASK                               0x4
+#define D0F2x70_NxSupW_OFFSET                                   3
+#define D0F2x70_NxSupW_WIDTH                                    1
+#define D0F2x70_NxSupW_MASK                                     0x8
+#define D0F2x70_GtSupW_OFFSET                                   4
+#define D0F2x70_GtSupW_WIDTH                                    1
+#define D0F2x70_GtSupW_MASK                                     0x10
+#define D0F2x70_Reserved_5_5_OFFSET                             5
+#define D0F2x70_Reserved_5_5_WIDTH                              1
+#define D0F2x70_Reserved_5_5_MASK                               0x20
+#define D0F2x70_IaSupW_OFFSET                                   6
+#define D0F2x70_IaSupW_WIDTH                                    1
+#define D0F2x70_IaSupW_MASK                                     0x40
+#define D0F2x70_Reserved_7_7_OFFSET                             7
+#define D0F2x70_Reserved_7_7_WIDTH                              1
+#define D0F2x70_Reserved_7_7_MASK                               0x80
+#define D0F2x70_Reserved_8_8_OFFSET                             8
+#define D0F2x70_Reserved_8_8_WIDTH                              1
+#define D0F2x70_Reserved_8_8_MASK                               0x100
+#define D0F2x70_PcSupW_OFFSET                                   9
+#define D0F2x70_PcSupW_WIDTH                                    1
+#define D0F2x70_PcSupW_MASK                                     0x200
+#define D0F2x70_HatsW_OFFSET                                    10
+#define D0F2x70_HatsW_WIDTH                                     2
+#define D0F2x70_HatsW_MASK                                      0xc00
+#define D0F2x70_Reserved_31_12_OFFSET                           12
+#define D0F2x70_Reserved_31_12_WIDTH                            20
+#define D0F2x70_Reserved_31_12_MASK                             0xfffff000
+
+/// D0F2x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 PrefSupW:1 ; ///<
+    UINT32                                                  PprSupW:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                   NxSupW:1 ; ///<
+    UINT32                                                   GtSupW:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                                   IaSupW:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                                   PcSupW:1 ; ///<
+    UINT32                                                    HatsW:2 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x70_STRUCT;
+
+// **** D0F2x74 Register Definition ****
+// Address
+#define D0F2x74_ADDRESS                                         0x74
+
+// Type
+#define D0F2x74_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x74_PasMaxW_OFFSET                                  0
+#define D0F2x74_PasMaxW_WIDTH                                   4
+#define D0F2x74_PasMaxW_MASK                                    0xf
+#define D0F2x74_Reserved_31_4_OFFSET                            4
+#define D0F2x74_Reserved_31_4_WIDTH                             28
+#define D0F2x74_Reserved_31_4_MASK                              0xfffffff0
+
+/// D0F2x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  PasMaxW:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x74_STRUCT;
+
+// **** D0F2x78 Register Definition ****
+// Address
+#define D0F2x78_ADDRESS                                         0x78
+
+// Type
+#define D0F2x78_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x78_Reserved_6_0_OFFSET                             0
+#define D0F2x78_Reserved_6_0_WIDTH                              7
+#define D0F2x78_Reserved_6_0_MASK                               0x7f
+#define D0F2x78_RngValidW_OFFSET                                7
+#define D0F2x78_RngValidW_WIDTH                                 1
+#define D0F2x78_RngValidW_MASK                                  0x80
+#define D0F2x78_BusNumberW_OFFSET                               8
+#define D0F2x78_BusNumberW_WIDTH                                8
+#define D0F2x78_BusNumberW_MASK                                 0xff00
+#define D0F2x78_FirstDeviceW_OFFSET                             16
+#define D0F2x78_FirstDeviceW_WIDTH                              8
+#define D0F2x78_FirstDeviceW_MASK                               0xff0000
+#define D0F2x78_LastDeviceW_OFFSET                              24
+#define D0F2x78_LastDeviceW_WIDTH                               8
+#define D0F2x78_LastDeviceW_MASK                                0xff000000
+
+/// D0F2x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_6_0:7 ; ///<
+    UINT32                                                RngValidW:1 ; ///<
+    UINT32                                               BusNumberW:8 ; ///<
+    UINT32                                             FirstDeviceW:8 ; ///<
+    UINT32                                              LastDeviceW:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x78_STRUCT;
+
+// **** D0F2xF0 Register Definition ****
+// Address
+#define D0F2xF0_ADDRESS                                         0xf0
+
+// Type
+#define D0F2xF0_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xF0_L2cfgIndex_OFFSET                               0
+#define D0F2xF0_L2cfgIndex_WIDTH                                8
+#define D0F2xF0_L2cfgIndex_MASK                                 0xff
+#define D0F2xF0_L2cfgWrEn_OFFSET                                8
+#define D0F2xF0_L2cfgWrEn_WIDTH                                 1
+#define D0F2xF0_L2cfgWrEn_MASK                                  0x100
+#define D0F2xF0_Reserved_31_9_OFFSET                            9
+#define D0F2xF0_Reserved_31_9_WIDTH                             23
+#define D0F2xF0_Reserved_31_9_MASK                              0xfffffe00
+
+/// D0F2xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               L2cfgIndex:8 ; ///<
+    UINT32                                                L2cfgWrEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF0_STRUCT;
+
+// **** D0F2xF4 Register Definition ****
+// Address
+#define D0F2xF4_ADDRESS                                         0xf4
+
+// Type
+#define D0F2xF4_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xF4_L2cfgData_OFFSET                                0
+#define D0F2xF4_L2cfgData_WIDTH                                 32
+#define D0F2xF4_L2cfgData_MASK                                  0xffffffff
+
+/// D0F2xF4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L2cfgData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_STRUCT;
+
+// **** D0F2xF8 Register Definition ****
+// Address
+#define D0F2xF8_ADDRESS                                         0xf8
+
+// Type
+#define D0F2xF8_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xF8_L1cfgIndex_OFFSET                               0
+#define D0F2xF8_L1cfgIndex_WIDTH                                16
+#define D0F2xF8_L1cfgIndex_MASK                                 0xffff
+#define D0F2xF8_L1cfgSel_OFFSET                                 16
+#define D0F2xF8_L1cfgSel_WIDTH                                  4
+#define D0F2xF8_L1cfgSel_MASK                                   0xf0000
+#define D0F2xF8_Reserved_30_20_OFFSET                           20
+#define D0F2xF8_Reserved_30_20_WIDTH                            11
+#define D0F2xF8_Reserved_30_20_MASK                             0x7ff00000
+#define D0F2xF8_L1cfgEn_OFFSET                                  31
+#define D0F2xF8_L1cfgEn_WIDTH                                   1
+#define D0F2xF8_L1cfgEn_MASK                                    0x80000000
+
+/// D0F2xF8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               L1cfgIndex:16; ///<
+    UINT32                                                 L1cfgSel:4 ; ///<
+    UINT32                                           Reserved_30_20:11; ///<
+    UINT32                                                  L1cfgEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF8_STRUCT;
+
+// **** D0F2xFC Register Definition ****
+// Address
+#define D0F2xFC_ADDRESS                                         0xfc
+
+// Type
+#define D0F2xFC_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xFC_L1cfgData_OFFSET                                0
+#define D0F2xFC_L1cfgData_WIDTH                                 32
+#define D0F2xFC_L1cfgData_MASK                                  0xffffffff
+
+/// D0F2xFC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L1cfgData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_STRUCT;
+
+// **** D18F0x00 Register Definition ****
+// Address
+#define D18F0x00_ADDRESS                                        0x0
+
+// Type
+#define D18F0x00_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x00_VendorID_OFFSET                                0
+#define D18F0x00_VendorID_WIDTH                                 16
+#define D18F0x00_VendorID_MASK                                  0xffff
+#define D18F0x00_DeviceID_OFFSET                                16
+#define D18F0x00_DeviceID_WIDTH                                 16
+#define D18F0x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x00_STRUCT;
+
+// **** D18F0x04 Register Definition ****
+// Address
+#define D18F0x04_ADDRESS                                        0x4
+
+// Type
+#define D18F0x04_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x04_Command_OFFSET                                 0
+#define D18F0x04_Command_WIDTH                                  16
+#define D18F0x04_Command_MASK                                   0xffff
+#define D18F0x04_Status_OFFSET                                  16
+#define D18F0x04_Status_WIDTH                                   16
+#define D18F0x04_Status_MASK                                    0xffff0000
+
+/// D18F0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x04_STRUCT;
+
+// **** D18F0x08 Register Definition ****
+// Address
+#define D18F0x08_ADDRESS                                        0x8
+
+// Type
+#define D18F0x08_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x08_RevID_OFFSET                                   0
+#define D18F0x08_RevID_WIDTH                                    8
+#define D18F0x08_RevID_MASK                                     0xff
+#define D18F0x08_ClassCode_OFFSET                               8
+#define D18F0x08_ClassCode_WIDTH                                24
+#define D18F0x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x08_STRUCT;
+
+// **** D18F0x0C Register Definition ****
+// Address
+#define D18F0x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F0x0C_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x0C_HeaderTypeReg_OFFSET                           0
+#define D18F0x0C_HeaderTypeReg_WIDTH                            32
+#define D18F0x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x0C_STRUCT;
+
+// **** D18F0x34 Register Definition ****
+// Address
+#define D18F0x34_ADDRESS                                        0x34
+
+// Type
+#define D18F0x34_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x34_CapPtr_OFFSET                                  0
+#define D18F0x34_CapPtr_WIDTH                                   8
+#define D18F0x34_CapPtr_MASK                                    0xff
+#define D18F0x34_Reserved_31_8_OFFSET                           8
+#define D18F0x34_Reserved_31_8_WIDTH                            24
+#define D18F0x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x34_STRUCT;
+
+// **** D18F0x40 Register Definition ****
+// Address
+#define D18F0x40_ADDRESS                                        0x40
+
+// Type
+#define D18F0x40_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x40_Reserved_31_0_OFFSET                           0
+#define D18F0x40_Reserved_31_0_WIDTH                            32
+#define D18F0x40_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F0x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x40_STRUCT;
+
+// **** D18F0x60 Register Definition ****
+// Address
+#define D18F0x60_ADDRESS                                        0x60
+
+// Type
+#define D18F0x60_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x60_Reserved_15_0_OFFSET                           0
+#define D18F0x60_Reserved_15_0_WIDTH                            16
+#define D18F0x60_Reserved_15_0_MASK                             0xffff
+#define D18F0x60_CpuCnt_4_0__OFFSET                             16
+#define D18F0x60_CpuCnt_4_0__WIDTH                              5
+#define D18F0x60_CpuCnt_4_0__MASK                               0x1f0000
+#define D18F0x60_Reserved_31_21_OFFSET                          21
+#define D18F0x60_Reserved_31_21_WIDTH                           11
+#define D18F0x60_Reserved_31_21_MASK                            0xffe00000
+
+/// D18F0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                              CpuCnt_4_0_:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x60_STRUCT;
+
+// **** D18F0x64 Register Definition ****
+// Address
+#define D18F0x64_ADDRESS                                        0x64
+
+// Type
+#define D18F0x64_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x64_MctUnit_OFFSET                                 4
+#define D18F0x64_MctUnit_WIDTH                                  2
+#define D18F0x64_MctUnit_MASK                                   0x30
+#define D18F0x64_HbUnit_OFFSET                                  6
+#define D18F0x64_HbUnit_WIDTH                                   2
+#define D18F0x64_HbUnit_MASK                                    0xc0
+#define D18F0x64_Reserved_31_8_OFFSET                           8
+#define D18F0x64_Reserved_31_8_WIDTH                            24
+#define D18F0x64_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  CpuUnit:2 ; ///<
+    UINT32                                               ExtCpuUnit:2 ; ///<
+    UINT32                                                  MctUnit:2 ; ///<
+    UINT32                                                   HbUnit:2 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x64_STRUCT;
+
+// **** D18F0x68 Register Definition ****
+// Address
+#define D18F0x68_ADDRESS                                        0x68
+
+// Type
+#define D18F0x68_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x68_Reserved_3_0_OFFSET                            0
+#define D18F0x68_Reserved_3_0_WIDTH                             4
+#define D18F0x68_Reserved_3_0_MASK                              0xf
+#define D18F0x68_DisMTS_OFFSET                                  4
+#define D18F0x68_DisMTS_WIDTH                                   1
+#define D18F0x68_DisMTS_MASK                                    0x10
+#define D18F0x68_Reserved_5_5_OFFSET                            5
+#define D18F0x68_Reserved_5_5_WIDTH                             1
+#define D18F0x68_Reserved_5_5_MASK                              0x20
+#define D18F0x68_CPUReqPassPW_OFFSET                            6
+#define D18F0x68_CPUReqPassPW_WIDTH                             1
+#define D18F0x68_CPUReqPassPW_MASK                              0x40
+#define D18F0x68_CPURdRspPassPW_OFFSET                          7
+#define D18F0x68_CPURdRspPassPW_WIDTH                           1
+#define D18F0x68_CPURdRspPassPW_MASK                            0x80
+#define D18F0x68_DisPMemC_OFFSET                                8
+#define D18F0x68_DisPMemC_WIDTH                                 1
+#define D18F0x68_DisPMemC_MASK                                  0x100
+#define D18F0x68_DisRmtPMemC_OFFSET                             9
+#define D18F0x68_DisRmtPMemC_WIDTH                              1
+#define D18F0x68_DisRmtPMemC_MASK                               0x200
+#define D18F0x68_DisFillP_OFFSET                                10
+#define D18F0x68_DisFillP_WIDTH                                 1
+#define D18F0x68_DisFillP_MASK                                  0x400
+#define D18F0x68_RespPassPW_OFFSET                              11
+#define D18F0x68_RespPassPW_WIDTH                               1
+#define D18F0x68_RespPassPW_MASK                                0x800
+#define D18F0x68_Reserved_14_12_OFFSET                          12
+#define D18F0x68_Reserved_14_12_WIDTH                           3
+#define D18F0x68_Reserved_14_12_MASK                            0x7000
+#define D18F0x68_LimitCldtCfg_OFFSET                            15
+#define D18F0x68_LimitCldtCfg_WIDTH                             1
+#define D18F0x68_LimitCldtCfg_MASK                              0x8000
+#define D18F0x68_LintEn_OFFSET                                  16
+#define D18F0x68_LintEn_WIDTH                                   1
+#define D18F0x68_LintEn_MASK                                    0x10000
+#define D18F0x68_ApicExtBrdCst_OFFSET                           17
+#define D18F0x68_ApicExtBrdCst_WIDTH                            1
+#define D18F0x68_ApicExtBrdCst_MASK                             0x20000
+#define D18F0x68_ApicExtId_OFFSET                               18
+#define D18F0x68_ApicExtId_WIDTH                                1
+#define D18F0x68_ApicExtId_MASK                                 0x40000
+#define D18F0x68_ApicExtSpur_OFFSET                             19
+#define D18F0x68_ApicExtSpur_WIDTH                              1
+#define D18F0x68_ApicExtSpur_MASK                               0x80000
+#define D18F0x68_SeqIdSrcNodeEn_OFFSET                          20
+#define D18F0x68_SeqIdSrcNodeEn_WIDTH                           1
+#define D18F0x68_SeqIdSrcNodeEn_MASK                            0x100000
+#define D18F0x68_DsNpReqLmt_OFFSET                              21
+#define D18F0x68_DsNpReqLmt_WIDTH                               2
+#define D18F0x68_DsNpReqLmt_MASK                                0x600000
+#define D18F0x68_Reserved_31_23_OFFSET                          23
+#define D18F0x68_Reserved_31_23_WIDTH                           9
+#define D18F0x68_Reserved_31_23_MASK                            0xff800000
+
+/// D18F0x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                   DisMTS:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                             CPUReqPassPW:1 ; ///<
+    UINT32                                           CPURdRspPassPW:1 ; ///<
+    UINT32                                                 DisPMemC:1 ; ///<
+    UINT32                                              DisRmtPMemC:1 ; ///<
+    UINT32                                                 DisFillP:1 ; ///<
+    UINT32                                               RespPassPW:1 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                             LimitCldtCfg:1 ; ///<
+    UINT32                                                   LintEn:1 ; ///<
+    UINT32                                            ApicExtBrdCst:1 ; ///<
+    UINT32                                                ApicExtId:1 ; ///<
+    UINT32                                              ApicExtSpur:1 ; ///<
+    UINT32                                           SeqIdSrcNodeEn:1 ; ///<
+    UINT32                                               DsNpReqLmt:2 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x68_STRUCT;
+
+// **** D18F0x6C Register Definition ****
+// Address
+#define D18F0x6C_ADDRESS                                        0x6c
+
+// Type
+#define D18F0x6C_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x6C_RouteTblDis_OFFSET                             0
+#define D18F0x6C_RouteTblDis_WIDTH                              1
+#define D18F0x6C_RouteTblDis_MASK                               0x1
+#define D18F0x6C_Reserved_3_1_OFFSET                            1
+#define D18F0x6C_Reserved_3_1_WIDTH                             3
+#define D18F0x6C_Reserved_3_1_MASK                              0xe
+#define D18F0x6C_ColdRstDet_OFFSET                              4
+#define D18F0x6C_ColdRstDet_WIDTH                               1
+#define D18F0x6C_ColdRstDet_MASK                                0x10
+#define D18F0x6C_BiosRstDet_0__OFFSET                           5
+#define D18F0x6C_BiosRstDet_0__WIDTH                            1
+#define D18F0x6C_BiosRstDet_0__MASK                             0x20
+#define D18F0x6C_InitDet_OFFSET                                 6
+#define D18F0x6C_InitDet_WIDTH                                  1
+#define D18F0x6C_InitDet_MASK                                   0x40
+#define D18F0x6C_Reserved_8_7_OFFSET                            7
+#define D18F0x6C_Reserved_8_7_WIDTH                             2
+#define D18F0x6C_Reserved_8_7_MASK                              0x180
+#define D18F0x6C_BiosRstDet_2_1__OFFSET                         9
+#define D18F0x6C_BiosRstDet_2_1__WIDTH                          2
+#define D18F0x6C_BiosRstDet_2_1__MASK                           0x600
+#define D18F0x6C_Reserved_26_11_OFFSET                          11
+#define D18F0x6C_Reserved_26_11_WIDTH                           16
+#define D18F0x6C_Reserved_26_11_MASK                            0x7fff800
+#define D18F0x6C_ApplyIsocModeEnNow_OFFSET                      27
+#define D18F0x6C_ApplyIsocModeEnNow_WIDTH                       1
+#define D18F0x6C_ApplyIsocModeEnNow_MASK                        0x8000000
+#define D18F0x6C_RlsIntFullTokCntImm_OFFSET                     28
+#define D18F0x6C_RlsIntFullTokCntImm_WIDTH                      1
+#define D18F0x6C_RlsIntFullTokCntImm_MASK                       0x10000000
+#define D18F0x6C_Reserved_29_29_OFFSET                          29
+#define D18F0x6C_Reserved_29_29_WIDTH                           1
+#define D18F0x6C_Reserved_29_29_MASK                            0x20000000
+#define D18F0x6C_RlsLnkFullTokCntImm_OFFSET                     30
+#define D18F0x6C_RlsLnkFullTokCntImm_WIDTH                      1
+#define D18F0x6C_RlsLnkFullTokCntImm_MASK                       0x40000000
+#define D18F0x6C_Reserved_31_31_OFFSET                          31
+#define D18F0x6C_Reserved_31_31_WIDTH                           1
+#define D18F0x6C_Reserved_31_31_MASK                            0x80000000
+
+/// D18F0x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              RouteTblDis:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                               ColdRstDet:1 ; ///<
+    UINT32                                            BiosRstDet_0_:1 ; ///<
+    UINT32                                                  InitDet:1 ; ///<
+    UINT32                                             Reserved_8_7:2 ; ///<
+    UINT32                                          BiosRstDet_2_1_:2 ; ///<
+    UINT32                                           Reserved_26_11:16; ///<
+    UINT32                                       ApplyIsocModeEnNow:1 ; ///<
+    UINT32                                      RlsIntFullTokCntImm:1 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                      RlsLnkFullTokCntImm:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x6C_STRUCT;
+
+// **** D18F0x84 Register Definition ****
+// Address
+#define D18F0x84_ADDRESS                                        0x84
+
+// Type
+#define D18F0x84_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x84_Reserved_3_0_OFFSET                            0
+#define D18F0x84_Reserved_3_0_WIDTH                             4
+#define D18F0x84_Reserved_3_0_MASK                              0xf
+#define D18F0x84_LinkFail_OFFSET                                4
+#define D18F0x84_LinkFail_WIDTH                                 1
+#define D18F0x84_LinkFail_MASK                                  0x10
+#define D18F0x84_Reserved_5_5_OFFSET                            5
+#define D18F0x84_Reserved_5_5_WIDTH                             1
+#define D18F0x84_Reserved_5_5_MASK                              0x20
+#define D18F0x84_Reserved_11_6_OFFSET                           6
+#define D18F0x84_Reserved_11_6_WIDTH                            6
+#define D18F0x84_Reserved_11_6_MASK                             0xfc0
+#define D18F0x84_IsocEn_OFFSET                                  12
+#define D18F0x84_IsocEn_WIDTH                                   1
+#define D18F0x84_IsocEn_MASK                                    0x1000
+#define D18F0x84_Reserved_31_13_OFFSET                          13
+#define D18F0x84_Reserved_31_13_WIDTH                           19
+#define D18F0x84_Reserved_31_13_MASK                            0xffffe000
+
+/// D18F0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                 LinkFail:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                                   IsocEn:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x84_STRUCT;
+
+// **** D18F0x90 Register Definition ****
+// Address
+#define D18F0x90_ADDRESS                                        0x90
+
+// Type
+#define D18F0x90_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x90_NpReqCmd_OFFSET                                0
+#define D18F0x90_NpReqCmd_WIDTH                                 5
+#define D18F0x90_NpReqCmd_MASK                                  0x1f
+#define D18F0x90_PReq_OFFSET                                    5
+#define D18F0x90_PReq_WIDTH                                     3
+#define D18F0x90_PReq_MASK                                      0xe0
+#define D18F0x90_RspCmd_OFFSET                                  8
+#define D18F0x90_RspCmd_WIDTH                                   4
+#define D18F0x90_RspCmd_MASK                                    0xf00
+#define D18F0x90_ProbeCmd_OFFSET                                12
+#define D18F0x90_ProbeCmd_WIDTH                                 4
+#define D18F0x90_ProbeCmd_MASK                                  0xf000
+#define D18F0x90_NpReqData_OFFSET                               16
+#define D18F0x90_NpReqData_WIDTH                                2
+#define D18F0x90_NpReqData_MASK                                 0x30000
+#define D18F0x90_RspData_OFFSET                                 18
+#define D18F0x90_RspData_WIDTH                                  2
+#define D18F0x90_RspData_MASK                                   0xc0000
+#define D18F0x90_FreeCmd_OFFSET                                 20
+#define D18F0x90_FreeCmd_WIDTH                                  5
+#define D18F0x90_FreeCmd_MASK                                   0x1f00000
+#define D18F0x90_FreeData_OFFSET                                25
+#define D18F0x90_FreeData_WIDTH                                 3
+#define D18F0x90_FreeData_MASK                                  0xe000000
+#define D18F0x90_Reserved_30_28_OFFSET                          28
+#define D18F0x90_Reserved_30_28_WIDTH                           3
+#define D18F0x90_Reserved_30_28_MASK                            0x70000000
+#define D18F0x90_LockBc_OFFSET                                  31
+#define D18F0x90_LockBc_WIDTH                                   1
+#define D18F0x90_LockBc_MASK                                    0x80000000
+
+/// D18F0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 NpReqCmd:5 ; ///<
+    UINT32                                                     PReq:3 ; ///<
+    UINT32                                                   RspCmd:4 ; ///<
+    UINT32                                                 ProbeCmd:4 ; ///<
+    UINT32                                                NpReqData:2 ; ///<
+    UINT32                                                  RspData:2 ; ///<
+    UINT32                                                  FreeCmd:5 ; ///<
+    UINT32                                                 FreeData:3 ; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                                   LockBc:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x90_STRUCT;
+
+// **** D18F0x94 Register Definition ****
+// Address
+#define D18F0x94_ADDRESS                                        0x94
+
+// Type
+#define D18F0x94_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x94_Reserved_7_0_OFFSET                            0
+#define D18F0x94_Reserved_7_0_WIDTH                             8
+#define D18F0x94_Reserved_7_0_MASK                              0xff
+#define D18F0x94_SecBusNum_OFFSET                               8
+#define D18F0x94_SecBusNum_WIDTH                                8
+#define D18F0x94_SecBusNum_MASK                                 0xff00
+#define D18F0x94_IsocNpReqCmd_OFFSET                            16
+#define D18F0x94_IsocNpReqCmd_WIDTH                             3
+#define D18F0x94_IsocNpReqCmd_MASK                              0x70000
+#define D18F0x94_IsocPReq_OFFSET                                19
+#define D18F0x94_IsocPReq_WIDTH                                 3
+#define D18F0x94_IsocPReq_MASK                                  0x380000
+#define D18F0x94_IsocRspCmd_OFFSET                              22
+#define D18F0x94_IsocRspCmd_WIDTH                               3
+#define D18F0x94_IsocRspCmd_MASK                                0x1c00000
+#define D18F0x94_IsocNpReqData_OFFSET                           25
+#define D18F0x94_IsocNpReqData_WIDTH                            2
+#define D18F0x94_IsocNpReqData_MASK                             0x6000000
+#define D18F0x94_IsocRspData_OFFSET                             27
+#define D18F0x94_IsocRspData_WIDTH                              2
+#define D18F0x94_IsocRspData_MASK                               0x18000000
+#define D18F0x94_Reserved_31_29_OFFSET                          29
+#define D18F0x94_Reserved_31_29_WIDTH                           3
+#define D18F0x94_Reserved_31_29_MASK                            0xe0000000
+
+/// D18F0x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                SecBusNum:8 ; ///<
+    UINT32                                             IsocNpReqCmd:3 ; ///<
+    UINT32                                                 IsocPReq:3 ; ///<
+    UINT32                                               IsocRspCmd:3 ; ///<
+    UINT32                                            IsocNpReqData:2 ; ///<
+    UINT32                                              IsocRspData:2 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x94_STRUCT;
+
+// **** D18F0x98 Register Definition ****
+// Address
+#define D18F0x98_ADDRESS                                        0x98
+
+// Type
+#define D18F0x98_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x98_Reserved_0_0_OFFSET                            0
+#define D18F0x98_Reserved_0_0_WIDTH                             1
+#define D18F0x98_Reserved_0_0_MASK                              0x1
+#define D18F0x98_Reserved_1_1_OFFSET                            1
+#define D18F0x98_Reserved_1_1_WIDTH                             1
+#define D18F0x98_Reserved_1_1_MASK                              0x2
+#define D18F0x98_Reserved_2_2_OFFSET                            2
+#define D18F0x98_Reserved_2_2_WIDTH                             1
+#define D18F0x98_Reserved_2_2_MASK                              0x4
+#define D18F0x98_Reserved_4_3_OFFSET                            3
+#define D18F0x98_Reserved_4_3_WIDTH                             2
+#define D18F0x98_Reserved_4_3_MASK                              0x18
+#define D18F0x98_PciEligible_OFFSET                             5
+#define D18F0x98_PciEligible_WIDTH                              1
+#define D18F0x98_PciEligible_MASK                               0x20
+#define D18F0x98_Reserved_31_6_OFFSET                           6
+#define D18F0x98_Reserved_31_6_WIDTH                            26
+#define D18F0x98_Reserved_31_6_MASK                             0xffffffc0
+
+/// D18F0x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                              PciEligible:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x98_STRUCT;
+
+// **** D18F0x9C Register Definition ****
+// Address
+#define D18F0x9C_ADDRESS                                        0x9c
+
+// Type
+#define D18F0x9C_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x9C_Reserved_0_0_OFFSET                            0
+#define D18F0x9C_Reserved_0_0_WIDTH                             1
+#define D18F0x9C_Reserved_0_0_MASK                              0x1
+#define D18F0x9C_Reserved_15_1_OFFSET                           1
+#define D18F0x9C_Reserved_15_1_WIDTH                            15
+#define D18F0x9C_Reserved_15_1_MASK                             0xfffe
+#define D18F0x9C_Reserved_31_16_OFFSET                          16
+#define D18F0x9C_Reserved_31_16_WIDTH                           16
+#define D18F0x9C_Reserved_31_16_MASK                            0xffff0000
+
+/// D18F0x9C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                            Reserved_15_1:15; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x9C_STRUCT;
+
+// **** D18F0x110 Register Definition ****
+// Address
+#define D18F0x110_ADDRESS                                       0x110
+
+// Type
+#define D18F0x110_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x110_Reserved_0_0_OFFSET                           0
+#define D18F0x110_Reserved_0_0_WIDTH                            1
+#define D18F0x110_Reserved_0_0_MASK                             0x1
+#define D18F0x110_Reserved_1_1_OFFSET                           1
+#define D18F0x110_Reserved_1_1_WIDTH                            1
+#define D18F0x110_Reserved_1_1_MASK                             0x2
+#define D18F0x110_ClumpEn_OFFSET                                2
+#define D18F0x110_ClumpEn_WIDTH                                 30
+#define D18F0x110_ClumpEn_MASK                                  0xfffffffc
+
+/// D18F0x110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                  ClumpEn:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x110_STRUCT;
+
+// **** D18F0x16C Register Definition ****
+// Address
+#define D18F0x16C_ADDRESS                                       0x16c
+
+// Type
+#define D18F0x16C_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x16C_Reserved_31_0_OFFSET                          0
+#define D18F0x16C_Reserved_31_0_WIDTH                           32
+#define D18F0x16C_Reserved_31_0_MASK                            0xffffffff
+
+/// D18F0x16C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x16C_STRUCT;
+
+// **** D18F0x170 Register Definition ****
+// Address
+#define D18F0x170_ADDRESS                                       0x170
+
+// Type
+#define D18F0x170_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x170_Reserved_31_0_OFFSET                          0
+#define D18F0x170_Reserved_31_0_WIDTH                           32
+#define D18F0x170_Reserved_31_0_MASK                            0xffffffff
+
+/// D18F0x170
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x170_STRUCT;
+
+// **** D18F0x1A0 Register Definition ****
+// Address
+#define D18F0x1A0_ADDRESS                                       0x1a0
+
+// Type
+#define D18F0x1A0_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x1A0_InitComplete_OFFSET                           0
+#define D18F0x1A0_InitComplete_WIDTH                            2
+#define D18F0x1A0_InitComplete_MASK                             0x3
+#define D18F0x1A0_Reserved_30_2_OFFSET                          2
+#define D18F0x1A0_Reserved_30_2_WIDTH                           29
+#define D18F0x1A0_Reserved_30_2_MASK                            0x7ffffffc
+#define D18F0x1A0_InitStatusValid_OFFSET                        31
+#define D18F0x1A0_InitStatusValid_WIDTH                         1
+#define D18F0x1A0_InitStatusValid_MASK                          0x80000000
+
+/// D18F0x1A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             InitComplete:2 ; ///<
+    UINT32                                            Reserved_30_2:29; ///<
+    UINT32                                          InitStatusValid:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x1A0_STRUCT;
+
+// **** D18F0x1DC Register Definition ****
+// Address
+#define D18F0x1DC_ADDRESS                                       0x1dc
+
+// Type
+#define D18F0x1DC_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x1DC_Reserved_0_0_OFFSET                           0
+#define D18F0x1DC_Reserved_0_0_WIDTH                            1
+#define D18F0x1DC_Reserved_0_0_MASK                             0x1
+#define D18F0x1DC_CpuEn_OFFSET                                  1
+#define D18F0x1DC_CpuEn_WIDTH                                   7
+#define D18F0x1DC_CpuEn_MASK                                    0xfe
+#define D18F0x1DC_Reserved_31_8_OFFSET                          8
+#define D18F0x1DC_Reserved_31_8_WIDTH                           24
+#define D18F0x1DC_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F0x1DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                    CpuEn:7 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x1DC_STRUCT;
+
+// **** D18F1x00 Register Definition ****
+// Address
+#define D18F1x00_ADDRESS                                        0x0
+
+// Type
+#define D18F1x00_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x00_VendorID_OFFSET                                0
+#define D18F1x00_VendorID_WIDTH                                 16
+#define D18F1x00_VendorID_MASK                                  0xffff
+#define D18F1x00_DeviceID_OFFSET                                16
+#define D18F1x00_DeviceID_WIDTH                                 16
+#define D18F1x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F1x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x00_STRUCT;
+
+// **** D18F1x08 Register Definition ****
+// Address
+#define D18F1x08_ADDRESS                                        0x8
+
+// Type
+#define D18F1x08_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x08_RevID_OFFSET                                   0
+#define D18F1x08_RevID_WIDTH                                    8
+#define D18F1x08_RevID_MASK                                     0xff
+#define D18F1x08_ClassCode_OFFSET                               8
+#define D18F1x08_ClassCode_WIDTH                                24
+#define D18F1x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F1x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x08_STRUCT;
+
+// **** D18F1x0C Register Definition ****
+// Address
+#define D18F1x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F1x0C_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x0C_HeaderTypeReg_OFFSET                           0
+#define D18F1x0C_HeaderTypeReg_WIDTH                            32
+#define D18F1x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F1x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x0C_STRUCT;
+
+// **** D18F1x40 Register Definition ****
+// Address
+#define D18F1x40_ADDRESS                                        0x40
+
+// Type
+#define D18F1x40_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x40_RE_OFFSET                                      0
+#define D18F1x40_RE_WIDTH                                       1
+#define D18F1x40_RE_MASK                                        0x1
+#define D18F1x40_WE_OFFSET                                      1
+#define D18F1x40_WE_WIDTH                                       1
+#define D18F1x40_WE_MASK                                        0x2
+#define D18F1x40_Reserved_15_2_OFFSET                           2
+#define D18F1x40_Reserved_15_2_WIDTH                            14
+#define D18F1x40_Reserved_15_2_MASK                             0xfffc
+#define D18F1x40_DramBase_39_24__OFFSET                         16
+#define D18F1x40_DramBase_39_24__WIDTH                          16
+#define D18F1x40_DramBase_39_24__MASK                           0xffff0000
+
+/// D18F1x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                            Reserved_15_2:14; ///<
+    UINT32                                          DramBase_39_24_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x40_STRUCT;
+
+// **** D18F1x44 Register Definition ****
+// Address
+#define D18F1x44_ADDRESS                                        0x44
+
+// Type
+#define D18F1x44_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x44_DstNode_OFFSET                                 0
+#define D18F1x44_DstNode_WIDTH                                  3
+#define D18F1x44_DstNode_MASK                                   0x7
+#define D18F1x44_Reserved_7_3_OFFSET                            3
+#define D18F1x44_Reserved_7_3_WIDTH                             5
+#define D18F1x44_Reserved_7_3_MASK                              0xf8
+#define D18F1x44_Reserved_10_8_OFFSET                           8
+#define D18F1x44_Reserved_10_8_WIDTH                            3
+#define D18F1x44_Reserved_10_8_MASK                             0x700
+#define D18F1x44_Reserved_15_11_OFFSET                          11
+#define D18F1x44_Reserved_15_11_WIDTH                           5
+#define D18F1x44_Reserved_15_11_MASK                            0xf800
+#define D18F1x44_DramLimit_39_24__OFFSET                        16
+#define D18F1x44_DramLimit_39_24__WIDTH                         16
+#define D18F1x44_DramLimit_39_24__MASK                          0xffff0000
+
+/// D18F1x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                            Reserved_10_8:3 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                         DramLimit_39_24_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x44_STRUCT;
+
+// **** D18F1x80 Register Definition ****
+// Address
+#define D18F1x80_ADDRESS                                        0x80
+
+// Type
+#define D18F1x80_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x80_RE_OFFSET                                      0
+#define D18F1x80_RE_WIDTH                                       1
+#define D18F1x80_RE_MASK                                        0x1
+#define D18F1x80_WE_OFFSET                                      1
+#define D18F1x80_WE_WIDTH                                       1
+#define D18F1x80_WE_MASK                                        0x2
+#define D18F1x80_Reserved_2_2_OFFSET                            2
+#define D18F1x80_Reserved_2_2_WIDTH                             1
+#define D18F1x80_Reserved_2_2_MASK                              0x4
+#define D18F1x80_Lock_OFFSET                                    3
+#define D18F1x80_Lock_WIDTH                                     1
+#define D18F1x80_Lock_MASK                                      0x8
+#define D18F1x80_Reserved_7_4_OFFSET                            4
+#define D18F1x80_Reserved_7_4_WIDTH                             4
+#define D18F1x80_Reserved_7_4_MASK                              0xf0
+#define D18F1x80_MMIOBase_39_16__OFFSET                         8
+#define D18F1x80_MMIOBase_39_16__WIDTH                          24
+#define D18F1x80_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x80_STRUCT;
+
+// **** D18F1x84 Register Definition ****
+// Address
+#define D18F1x84_ADDRESS                                        0x84
+
+// Type
+#define D18F1x84_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x84_DstNode_OFFSET                                 0
+#define D18F1x84_DstNode_WIDTH                                  3
+#define D18F1x84_DstNode_MASK                                   0x7
+#define D18F1x84_Reserved_3_3_OFFSET                            3
+#define D18F1x84_Reserved_3_3_WIDTH                             1
+#define D18F1x84_Reserved_3_3_MASK                              0x8
+#define D18F1x84_DstLink_OFFSET                                 4
+#define D18F1x84_DstLink_WIDTH                                  2
+#define D18F1x84_DstLink_MASK                                   0x30
+#define D18F1x84_DstSubLink_OFFSET                              6
+#define D18F1x84_DstSubLink_WIDTH                               1
+#define D18F1x84_DstSubLink_MASK                                0x40
+#define D18F1x84_NP_OFFSET                                      7
+#define D18F1x84_NP_WIDTH                                       1
+#define D18F1x84_NP_MASK                                        0x80
+#define D18F1x84_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x84_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x84_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x84_STRUCT;
+
+// **** D18F1x88 Register Definition ****
+// Address
+#define D18F1x88_ADDRESS                                        0x88
+
+// Type
+#define D18F1x88_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x88_RE_OFFSET                                      0
+#define D18F1x88_RE_WIDTH                                       1
+#define D18F1x88_RE_MASK                                        0x1
+#define D18F1x88_WE_OFFSET                                      1
+#define D18F1x88_WE_WIDTH                                       1
+#define D18F1x88_WE_MASK                                        0x2
+#define D18F1x88_Reserved_2_2_OFFSET                            2
+#define D18F1x88_Reserved_2_2_WIDTH                             1
+#define D18F1x88_Reserved_2_2_MASK                              0x4
+#define D18F1x88_Lock_OFFSET                                    3
+#define D18F1x88_Lock_WIDTH                                     1
+#define D18F1x88_Lock_MASK                                      0x8
+#define D18F1x88_Reserved_7_4_OFFSET                            4
+#define D18F1x88_Reserved_7_4_WIDTH                             4
+#define D18F1x88_Reserved_7_4_MASK                              0xf0
+#define D18F1x88_MMIOBase_39_16__OFFSET                         8
+#define D18F1x88_MMIOBase_39_16__WIDTH                          24
+#define D18F1x88_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x88_STRUCT;
+
+// **** D18F1x8C Register Definition ****
+// Address
+#define D18F1x8C_ADDRESS                                        0x8c
+
+// Type
+#define D18F1x8C_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x8C_DstNode_OFFSET                                 0
+#define D18F1x8C_DstNode_WIDTH                                  3
+#define D18F1x8C_DstNode_MASK                                   0x7
+#define D18F1x8C_Reserved_3_3_OFFSET                            3
+#define D18F1x8C_Reserved_3_3_WIDTH                             1
+#define D18F1x8C_Reserved_3_3_MASK                              0x8
+#define D18F1x8C_DstLink_OFFSET                                 4
+#define D18F1x8C_DstLink_WIDTH                                  2
+#define D18F1x8C_DstLink_MASK                                   0x30
+#define D18F1x8C_DstSubLink_OFFSET                              6
+#define D18F1x8C_DstSubLink_WIDTH                               1
+#define D18F1x8C_DstSubLink_MASK                                0x40
+#define D18F1x8C_NP_OFFSET                                      7
+#define D18F1x8C_NP_WIDTH                                       1
+#define D18F1x8C_NP_MASK                                        0x80
+#define D18F1x8C_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x8C_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x8C_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x8C_STRUCT;
+
+// **** D18F1x90 Register Definition ****
+// Address
+#define D18F1x90_ADDRESS                                        0x90
+
+// Type
+#define D18F1x90_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x90_RE_OFFSET                                      0
+#define D18F1x90_RE_WIDTH                                       1
+#define D18F1x90_RE_MASK                                        0x1
+#define D18F1x90_WE_OFFSET                                      1
+#define D18F1x90_WE_WIDTH                                       1
+#define D18F1x90_WE_MASK                                        0x2
+#define D18F1x90_Reserved_2_2_OFFSET                            2
+#define D18F1x90_Reserved_2_2_WIDTH                             1
+#define D18F1x90_Reserved_2_2_MASK                              0x4
+#define D18F1x90_Lock_OFFSET                                    3
+#define D18F1x90_Lock_WIDTH                                     1
+#define D18F1x90_Lock_MASK                                      0x8
+#define D18F1x90_Reserved_7_4_OFFSET                            4
+#define D18F1x90_Reserved_7_4_WIDTH                             4
+#define D18F1x90_Reserved_7_4_MASK                              0xf0
+#define D18F1x90_MMIOBase_39_16__OFFSET                         8
+#define D18F1x90_MMIOBase_39_16__WIDTH                          24
+#define D18F1x90_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x90_STRUCT;
+
+// **** D18F1x94 Register Definition ****
+// Address
+#define D18F1x94_ADDRESS                                        0x94
+
+// Type
+#define D18F1x94_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x94_DstNode_OFFSET                                 0
+#define D18F1x94_DstNode_WIDTH                                  3
+#define D18F1x94_DstNode_MASK                                   0x7
+#define D18F1x94_Reserved_3_3_OFFSET                            3
+#define D18F1x94_Reserved_3_3_WIDTH                             1
+#define D18F1x94_Reserved_3_3_MASK                              0x8
+#define D18F1x94_DstLink_OFFSET                                 4
+#define D18F1x94_DstLink_WIDTH                                  2
+#define D18F1x94_DstLink_MASK                                   0x30
+#define D18F1x94_DstSubLink_OFFSET                              6
+#define D18F1x94_DstSubLink_WIDTH                               1
+#define D18F1x94_DstSubLink_MASK                                0x40
+#define D18F1x94_NP_OFFSET                                      7
+#define D18F1x94_NP_WIDTH                                       1
+#define D18F1x94_NP_MASK                                        0x80
+#define D18F1x94_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x94_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x94_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x94_STRUCT;
+
+// **** D18F1x98 Register Definition ****
+// Address
+#define D18F1x98_ADDRESS                                        0x98
+
+// Type
+#define D18F1x98_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x98_RE_OFFSET                                      0
+#define D18F1x98_RE_WIDTH                                       1
+#define D18F1x98_RE_MASK                                        0x1
+#define D18F1x98_WE_OFFSET                                      1
+#define D18F1x98_WE_WIDTH                                       1
+#define D18F1x98_WE_MASK                                        0x2
+#define D18F1x98_Reserved_2_2_OFFSET                            2
+#define D18F1x98_Reserved_2_2_WIDTH                             1
+#define D18F1x98_Reserved_2_2_MASK                              0x4
+#define D18F1x98_Lock_OFFSET                                    3
+#define D18F1x98_Lock_WIDTH                                     1
+#define D18F1x98_Lock_MASK                                      0x8
+#define D18F1x98_Reserved_7_4_OFFSET                            4
+#define D18F1x98_Reserved_7_4_WIDTH                             4
+#define D18F1x98_Reserved_7_4_MASK                              0xf0
+#define D18F1x98_MMIOBase_39_16__OFFSET                         8
+#define D18F1x98_MMIOBase_39_16__WIDTH                          24
+#define D18F1x98_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x98_STRUCT;
+
+// **** D18F1x9C Register Definition ****
+// Address
+#define D18F1x9C_ADDRESS                                        0x9c
+
+// Type
+#define D18F1x9C_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x9C_DstNode_OFFSET                                 0
+#define D18F1x9C_DstNode_WIDTH                                  3
+#define D18F1x9C_DstNode_MASK                                   0x7
+#define D18F1x9C_Reserved_3_3_OFFSET                            3
+#define D18F1x9C_Reserved_3_3_WIDTH                             1
+#define D18F1x9C_Reserved_3_3_MASK                              0x8
+#define D18F1x9C_DstLink_OFFSET                                 4
+#define D18F1x9C_DstLink_WIDTH                                  2
+#define D18F1x9C_DstLink_MASK                                   0x30
+#define D18F1x9C_DstSubLink_OFFSET                              6
+#define D18F1x9C_DstSubLink_WIDTH                               1
+#define D18F1x9C_DstSubLink_MASK                                0x40
+#define D18F1x9C_NP_OFFSET                                      7
+#define D18F1x9C_NP_WIDTH                                       1
+#define D18F1x9C_NP_MASK                                        0x80
+#define D18F1x9C_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x9C_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x9C_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x9C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x9C_STRUCT;
+
+// **** D18F1xA0 Register Definition ****
+// Address
+#define D18F1xA0_ADDRESS                                        0xa0
+
+// Type
+#define D18F1xA0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xA0_RE_OFFSET                                      0
+#define D18F1xA0_RE_WIDTH                                       1
+#define D18F1xA0_RE_MASK                                        0x1
+#define D18F1xA0_WE_OFFSET                                      1
+#define D18F1xA0_WE_WIDTH                                       1
+#define D18F1xA0_WE_MASK                                        0x2
+#define D18F1xA0_Reserved_2_2_OFFSET                            2
+#define D18F1xA0_Reserved_2_2_WIDTH                             1
+#define D18F1xA0_Reserved_2_2_MASK                              0x4
+#define D18F1xA0_Lock_OFFSET                                    3
+#define D18F1xA0_Lock_WIDTH                                     1
+#define D18F1xA0_Lock_MASK                                      0x8
+#define D18F1xA0_Reserved_7_4_OFFSET                            4
+#define D18F1xA0_Reserved_7_4_WIDTH                             4
+#define D18F1xA0_Reserved_7_4_MASK                              0xf0
+#define D18F1xA0_MMIOBase_39_16__OFFSET                         8
+#define D18F1xA0_MMIOBase_39_16__WIDTH                          24
+#define D18F1xA0_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xA0_STRUCT;
+
+// **** D18F1xA4 Register Definition ****
+// Address
+#define D18F1xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F1xA4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xA4_DstNode_OFFSET                                 0
+#define D18F1xA4_DstNode_WIDTH                                  3
+#define D18F1xA4_DstNode_MASK                                   0x7
+#define D18F1xA4_Reserved_3_3_OFFSET                            3
+#define D18F1xA4_Reserved_3_3_WIDTH                             1
+#define D18F1xA4_Reserved_3_3_MASK                              0x8
+#define D18F1xA4_DstLink_OFFSET                                 4
+#define D18F1xA4_DstLink_WIDTH                                  2
+#define D18F1xA4_DstLink_MASK                                   0x30
+#define D18F1xA4_DstSubLink_OFFSET                              6
+#define D18F1xA4_DstSubLink_WIDTH                               1
+#define D18F1xA4_DstSubLink_MASK                                0x40
+#define D18F1xA4_NP_OFFSET                                      7
+#define D18F1xA4_NP_WIDTH                                       1
+#define D18F1xA4_NP_MASK                                        0x80
+#define D18F1xA4_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xA4_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xA4_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xA4_STRUCT;
+
+// **** D18F1xA8 Register Definition ****
+// Address
+#define D18F1xA8_ADDRESS                                        0xa8
+
+// Type
+#define D18F1xA8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xA8_RE_OFFSET                                      0
+#define D18F1xA8_RE_WIDTH                                       1
+#define D18F1xA8_RE_MASK                                        0x1
+#define D18F1xA8_WE_OFFSET                                      1
+#define D18F1xA8_WE_WIDTH                                       1
+#define D18F1xA8_WE_MASK                                        0x2
+#define D18F1xA8_Reserved_2_2_OFFSET                            2
+#define D18F1xA8_Reserved_2_2_WIDTH                             1
+#define D18F1xA8_Reserved_2_2_MASK                              0x4
+#define D18F1xA8_Lock_OFFSET                                    3
+#define D18F1xA8_Lock_WIDTH                                     1
+#define D18F1xA8_Lock_MASK                                      0x8
+#define D18F1xA8_Reserved_7_4_OFFSET                            4
+#define D18F1xA8_Reserved_7_4_WIDTH                             4
+#define D18F1xA8_Reserved_7_4_MASK                              0xf0
+#define D18F1xA8_MMIOBase_39_16__OFFSET                         8
+#define D18F1xA8_MMIOBase_39_16__WIDTH                          24
+#define D18F1xA8_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xA8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xA8_STRUCT;
+
+// **** D18F1xAC Register Definition ****
+// Address
+#define D18F1xAC_ADDRESS                                        0xac
+
+// Type
+#define D18F1xAC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xAC_DstNode_OFFSET                                 0
+#define D18F1xAC_DstNode_WIDTH                                  3
+#define D18F1xAC_DstNode_MASK                                   0x7
+#define D18F1xAC_Reserved_3_3_OFFSET                            3
+#define D18F1xAC_Reserved_3_3_WIDTH                             1
+#define D18F1xAC_Reserved_3_3_MASK                              0x8
+#define D18F1xAC_DstLink_OFFSET                                 4
+#define D18F1xAC_DstLink_WIDTH                                  2
+#define D18F1xAC_DstLink_MASK                                   0x30
+#define D18F1xAC_DstSubLink_OFFSET                              6
+#define D18F1xAC_DstSubLink_WIDTH                               1
+#define D18F1xAC_DstSubLink_MASK                                0x40
+#define D18F1xAC_NP_OFFSET                                      7
+#define D18F1xAC_NP_WIDTH                                       1
+#define D18F1xAC_NP_MASK                                        0x80
+#define D18F1xAC_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xAC_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xAC_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xAC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xAC_STRUCT;
+
+// **** D18F1xB0 Register Definition ****
+// Address
+#define D18F1xB0_ADDRESS                                        0xb0
+
+// Type
+#define D18F1xB0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xB0_RE_OFFSET                                      0
+#define D18F1xB0_RE_WIDTH                                       1
+#define D18F1xB0_RE_MASK                                        0x1
+#define D18F1xB0_WE_OFFSET                                      1
+#define D18F1xB0_WE_WIDTH                                       1
+#define D18F1xB0_WE_MASK                                        0x2
+#define D18F1xB0_Reserved_2_2_OFFSET                            2
+#define D18F1xB0_Reserved_2_2_WIDTH                             1
+#define D18F1xB0_Reserved_2_2_MASK                              0x4
+#define D18F1xB0_Lock_OFFSET                                    3
+#define D18F1xB0_Lock_WIDTH                                     1
+#define D18F1xB0_Lock_MASK                                      0x8
+#define D18F1xB0_Reserved_7_4_OFFSET                            4
+#define D18F1xB0_Reserved_7_4_WIDTH                             4
+#define D18F1xB0_Reserved_7_4_MASK                              0xf0
+#define D18F1xB0_MMIOBase_39_16__OFFSET                         8
+#define D18F1xB0_MMIOBase_39_16__WIDTH                          24
+#define D18F1xB0_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xB0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xB0_STRUCT;
+
+// **** D18F1xB4 Register Definition ****
+// Address
+#define D18F1xB4_ADDRESS                                        0xb4
+
+// Type
+#define D18F1xB4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xB4_DstNode_OFFSET                                 0
+#define D18F1xB4_DstNode_WIDTH                                  3
+#define D18F1xB4_DstNode_MASK                                   0x7
+#define D18F1xB4_Reserved_3_3_OFFSET                            3
+#define D18F1xB4_Reserved_3_3_WIDTH                             1
+#define D18F1xB4_Reserved_3_3_MASK                              0x8
+#define D18F1xB4_DstLink_OFFSET                                 4
+#define D18F1xB4_DstLink_WIDTH                                  2
+#define D18F1xB4_DstLink_MASK                                   0x30
+#define D18F1xB4_DstSubLink_OFFSET                              6
+#define D18F1xB4_DstSubLink_WIDTH                               1
+#define D18F1xB4_DstSubLink_MASK                                0x40
+#define D18F1xB4_NP_OFFSET                                      7
+#define D18F1xB4_NP_WIDTH                                       1
+#define D18F1xB4_NP_MASK                                        0x80
+#define D18F1xB4_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xB4_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xB4_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xB4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xB4_STRUCT;
+
+// **** D18F1xB8 Register Definition ****
+// Address
+#define D18F1xB8_ADDRESS                                        0xb8
+
+// Type
+#define D18F1xB8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xB8_RE_OFFSET                                      0
+#define D18F1xB8_RE_WIDTH                                       1
+#define D18F1xB8_RE_MASK                                        0x1
+#define D18F1xB8_WE_OFFSET                                      1
+#define D18F1xB8_WE_WIDTH                                       1
+#define D18F1xB8_WE_MASK                                        0x2
+#define D18F1xB8_Reserved_2_2_OFFSET                            2
+#define D18F1xB8_Reserved_2_2_WIDTH                             1
+#define D18F1xB8_Reserved_2_2_MASK                              0x4
+#define D18F1xB8_Lock_OFFSET                                    3
+#define D18F1xB8_Lock_WIDTH                                     1
+#define D18F1xB8_Lock_MASK                                      0x8
+#define D18F1xB8_Reserved_7_4_OFFSET                            4
+#define D18F1xB8_Reserved_7_4_WIDTH                             4
+#define D18F1xB8_Reserved_7_4_MASK                              0xf0
+#define D18F1xB8_MMIOBase_39_16__OFFSET                         8
+#define D18F1xB8_MMIOBase_39_16__WIDTH                          24
+#define D18F1xB8_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xB8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xB8_STRUCT;
+
+// **** D18F1xBC Register Definition ****
+// Address
+#define D18F1xBC_ADDRESS                                        0xbc
+
+// Type
+#define D18F1xBC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xBC_DstNode_OFFSET                                 0
+#define D18F1xBC_DstNode_WIDTH                                  3
+#define D18F1xBC_DstNode_MASK                                   0x7
+#define D18F1xBC_Reserved_3_3_OFFSET                            3
+#define D18F1xBC_Reserved_3_3_WIDTH                             1
+#define D18F1xBC_Reserved_3_3_MASK                              0x8
+#define D18F1xBC_DstLink_OFFSET                                 4
+#define D18F1xBC_DstLink_WIDTH                                  2
+#define D18F1xBC_DstLink_MASK                                   0x30
+#define D18F1xBC_DstSubLink_OFFSET                              6
+#define D18F1xBC_DstSubLink_WIDTH                               1
+#define D18F1xBC_DstSubLink_MASK                                0x40
+#define D18F1xBC_NP_OFFSET                                      7
+#define D18F1xBC_NP_WIDTH                                       1
+#define D18F1xBC_NP_MASK                                        0x80
+#define D18F1xBC_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xBC_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xBC_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xBC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xBC_STRUCT;
+
+// **** D18F1xC0 Register Definition ****
+// Address
+#define D18F1xC0_ADDRESS                                        0xc0
+
+// Type
+#define D18F1xC0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xC0_RE_OFFSET                                      0
+#define D18F1xC0_RE_WIDTH                                       1
+#define D18F1xC0_RE_MASK                                        0x1
+#define D18F1xC0_WE_OFFSET                                      1
+#define D18F1xC0_WE_WIDTH                                       1
+#define D18F1xC0_WE_MASK                                        0x2
+#define D18F1xC0_Reserved_3_2_OFFSET                            2
+#define D18F1xC0_Reserved_3_2_WIDTH                             2
+#define D18F1xC0_Reserved_3_2_MASK                              0xc
+#define D18F1xC0_VE_OFFSET                                      4
+#define D18F1xC0_VE_WIDTH                                       1
+#define D18F1xC0_VE_MASK                                        0x10
+#define D18F1xC0_IE_OFFSET                                      5
+#define D18F1xC0_IE_WIDTH                                       1
+#define D18F1xC0_IE_MASK                                        0x20
+#define D18F1xC0_Reserved_11_6_OFFSET                           6
+#define D18F1xC0_Reserved_11_6_WIDTH                            6
+#define D18F1xC0_Reserved_11_6_MASK                             0xfc0
+#define D18F1xC0_IOBase_24_12__OFFSET                           12
+#define D18F1xC0_IOBase_24_12__WIDTH                            13
+#define D18F1xC0_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xC0_Reserved_31_25_OFFSET                          25
+#define D18F1xC0_Reserved_31_25_WIDTH                           7
+#define D18F1xC0_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xC0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xC0_STRUCT;
+
+// **** D18F1xC4 Register Definition ****
+// Address
+#define D18F1xC4_ADDRESS                                        0xc4
+
+// Type
+#define D18F1xC4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xC4_DstNode_OFFSET                                 0
+#define D18F1xC4_DstNode_WIDTH                                  3
+#define D18F1xC4_DstNode_MASK                                   0x7
+#define D18F1xC4_Reserved_3_3_OFFSET                            3
+#define D18F1xC4_Reserved_3_3_WIDTH                             1
+#define D18F1xC4_Reserved_3_3_MASK                              0x8
+#define D18F1xC4_DstLink_OFFSET                                 4
+#define D18F1xC4_DstLink_WIDTH                                  2
+#define D18F1xC4_DstLink_MASK                                   0x30
+#define D18F1xC4_DstSubLink_OFFSET                              6
+#define D18F1xC4_DstSubLink_WIDTH                               1
+#define D18F1xC4_DstSubLink_MASK                                0x40
+#define D18F1xC4_Reserved_11_7_OFFSET                           7
+#define D18F1xC4_Reserved_11_7_WIDTH                            5
+#define D18F1xC4_Reserved_11_7_MASK                             0xf80
+#define D18F1xC4_IOLimit_24_12__OFFSET                          12
+#define D18F1xC4_IOLimit_24_12__WIDTH                           13
+#define D18F1xC4_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xC4_Reserved_31_25_OFFSET                          25
+#define D18F1xC4_Reserved_31_25_WIDTH                           7
+#define D18F1xC4_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xC4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xC4_STRUCT;
+
+// **** D18F1xC8 Register Definition ****
+// Address
+#define D18F1xC8_ADDRESS                                        0xc8
+
+// Type
+#define D18F1xC8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xC8_RE_OFFSET                                      0
+#define D18F1xC8_RE_WIDTH                                       1
+#define D18F1xC8_RE_MASK                                        0x1
+#define D18F1xC8_WE_OFFSET                                      1
+#define D18F1xC8_WE_WIDTH                                       1
+#define D18F1xC8_WE_MASK                                        0x2
+#define D18F1xC8_Reserved_3_2_OFFSET                            2
+#define D18F1xC8_Reserved_3_2_WIDTH                             2
+#define D18F1xC8_Reserved_3_2_MASK                              0xc
+#define D18F1xC8_VE_OFFSET                                      4
+#define D18F1xC8_VE_WIDTH                                       1
+#define D18F1xC8_VE_MASK                                        0x10
+#define D18F1xC8_IE_OFFSET                                      5
+#define D18F1xC8_IE_WIDTH                                       1
+#define D18F1xC8_IE_MASK                                        0x20
+#define D18F1xC8_Reserved_11_6_OFFSET                           6
+#define D18F1xC8_Reserved_11_6_WIDTH                            6
+#define D18F1xC8_Reserved_11_6_MASK                             0xfc0
+#define D18F1xC8_IOBase_24_12__OFFSET                           12
+#define D18F1xC8_IOBase_24_12__WIDTH                            13
+#define D18F1xC8_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xC8_Reserved_31_25_OFFSET                          25
+#define D18F1xC8_Reserved_31_25_WIDTH                           7
+#define D18F1xC8_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xC8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xC8_STRUCT;
+
+// **** D18F1xCC Register Definition ****
+// Address
+#define D18F1xCC_ADDRESS                                        0xcc
+
+// Type
+#define D18F1xCC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xCC_DstNode_OFFSET                                 0
+#define D18F1xCC_DstNode_WIDTH                                  3
+#define D18F1xCC_DstNode_MASK                                   0x7
+#define D18F1xCC_Reserved_3_3_OFFSET                            3
+#define D18F1xCC_Reserved_3_3_WIDTH                             1
+#define D18F1xCC_Reserved_3_3_MASK                              0x8
+#define D18F1xCC_DstLink_OFFSET                                 4
+#define D18F1xCC_DstLink_WIDTH                                  2
+#define D18F1xCC_DstLink_MASK                                   0x30
+#define D18F1xCC_DstSubLink_OFFSET                              6
+#define D18F1xCC_DstSubLink_WIDTH                               1
+#define D18F1xCC_DstSubLink_MASK                                0x40
+#define D18F1xCC_Reserved_11_7_OFFSET                           7
+#define D18F1xCC_Reserved_11_7_WIDTH                            5
+#define D18F1xCC_Reserved_11_7_MASK                             0xf80
+#define D18F1xCC_IOLimit_24_12__OFFSET                          12
+#define D18F1xCC_IOLimit_24_12__WIDTH                           13
+#define D18F1xCC_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xCC_Reserved_31_25_OFFSET                          25
+#define D18F1xCC_Reserved_31_25_WIDTH                           7
+#define D18F1xCC_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xCC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xCC_STRUCT;
+
+// **** D18F1xD0 Register Definition ****
+// Address
+#define D18F1xD0_ADDRESS                                        0xd0
+
+// Type
+#define D18F1xD0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xD0_RE_OFFSET                                      0
+#define D18F1xD0_RE_WIDTH                                       1
+#define D18F1xD0_RE_MASK                                        0x1
+#define D18F1xD0_WE_OFFSET                                      1
+#define D18F1xD0_WE_WIDTH                                       1
+#define D18F1xD0_WE_MASK                                        0x2
+#define D18F1xD0_Reserved_3_2_OFFSET                            2
+#define D18F1xD0_Reserved_3_2_WIDTH                             2
+#define D18F1xD0_Reserved_3_2_MASK                              0xc
+#define D18F1xD0_VE_OFFSET                                      4
+#define D18F1xD0_VE_WIDTH                                       1
+#define D18F1xD0_VE_MASK                                        0x10
+#define D18F1xD0_IE_OFFSET                                      5
+#define D18F1xD0_IE_WIDTH                                       1
+#define D18F1xD0_IE_MASK                                        0x20
+#define D18F1xD0_Reserved_11_6_OFFSET                           6
+#define D18F1xD0_Reserved_11_6_WIDTH                            6
+#define D18F1xD0_Reserved_11_6_MASK                             0xfc0
+#define D18F1xD0_IOBase_24_12__OFFSET                           12
+#define D18F1xD0_IOBase_24_12__WIDTH                            13
+#define D18F1xD0_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xD0_Reserved_31_25_OFFSET                          25
+#define D18F1xD0_Reserved_31_25_WIDTH                           7
+#define D18F1xD0_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xD0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xD0_STRUCT;
+
+// **** D18F1xD4 Register Definition ****
+// Address
+#define D18F1xD4_ADDRESS                                        0xd4
+
+// Type
+#define D18F1xD4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xD4_DstNode_OFFSET                                 0
+#define D18F1xD4_DstNode_WIDTH                                  3
+#define D18F1xD4_DstNode_MASK                                   0x7
+#define D18F1xD4_Reserved_3_3_OFFSET                            3
+#define D18F1xD4_Reserved_3_3_WIDTH                             1
+#define D18F1xD4_Reserved_3_3_MASK                              0x8
+#define D18F1xD4_DstLink_OFFSET                                 4
+#define D18F1xD4_DstLink_WIDTH                                  2
+#define D18F1xD4_DstLink_MASK                                   0x30
+#define D18F1xD4_DstSubLink_OFFSET                              6
+#define D18F1xD4_DstSubLink_WIDTH                               1
+#define D18F1xD4_DstSubLink_MASK                                0x40
+#define D18F1xD4_Reserved_11_7_OFFSET                           7
+#define D18F1xD4_Reserved_11_7_WIDTH                            5
+#define D18F1xD4_Reserved_11_7_MASK                             0xf80
+#define D18F1xD4_IOLimit_24_12__OFFSET                          12
+#define D18F1xD4_IOLimit_24_12__WIDTH                           13
+#define D18F1xD4_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xD4_Reserved_31_25_OFFSET                          25
+#define D18F1xD4_Reserved_31_25_WIDTH                           7
+#define D18F1xD4_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xD4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xD4_STRUCT;
+
+// **** D18F1xD8 Register Definition ****
+// Address
+#define D18F1xD8_ADDRESS                                        0xd8
+
+// Type
+#define D18F1xD8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xD8_RE_OFFSET                                      0
+#define D18F1xD8_RE_WIDTH                                       1
+#define D18F1xD8_RE_MASK                                        0x1
+#define D18F1xD8_WE_OFFSET                                      1
+#define D18F1xD8_WE_WIDTH                                       1
+#define D18F1xD8_WE_MASK                                        0x2
+#define D18F1xD8_Reserved_3_2_OFFSET                            2
+#define D18F1xD8_Reserved_3_2_WIDTH                             2
+#define D18F1xD8_Reserved_3_2_MASK                              0xc
+#define D18F1xD8_VE_OFFSET                                      4
+#define D18F1xD8_VE_WIDTH                                       1
+#define D18F1xD8_VE_MASK                                        0x10
+#define D18F1xD8_IE_OFFSET                                      5
+#define D18F1xD8_IE_WIDTH                                       1
+#define D18F1xD8_IE_MASK                                        0x20
+#define D18F1xD8_Reserved_11_6_OFFSET                           6
+#define D18F1xD8_Reserved_11_6_WIDTH                            6
+#define D18F1xD8_Reserved_11_6_MASK                             0xfc0
+#define D18F1xD8_IOBase_24_12__OFFSET                           12
+#define D18F1xD8_IOBase_24_12__WIDTH                            13
+#define D18F1xD8_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xD8_Reserved_31_25_OFFSET                          25
+#define D18F1xD8_Reserved_31_25_WIDTH                           7
+#define D18F1xD8_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xD8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xD8_STRUCT;
+
+// **** D18F1xDC Register Definition ****
+// Address
+#define D18F1xDC_ADDRESS                                        0xdc
+
+// Type
+#define D18F1xDC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xDC_DstNode_OFFSET                                 0
+#define D18F1xDC_DstNode_WIDTH                                  3
+#define D18F1xDC_DstNode_MASK                                   0x7
+#define D18F1xDC_Reserved_3_3_OFFSET                            3
+#define D18F1xDC_Reserved_3_3_WIDTH                             1
+#define D18F1xDC_Reserved_3_3_MASK                              0x8
+#define D18F1xDC_DstLink_OFFSET                                 4
+#define D18F1xDC_DstLink_WIDTH                                  2
+#define D18F1xDC_DstLink_MASK                                   0x30
+#define D18F1xDC_DstSubLink_OFFSET                              6
+#define D18F1xDC_DstSubLink_WIDTH                               1
+#define D18F1xDC_DstSubLink_MASK                                0x40
+#define D18F1xDC_Reserved_11_7_OFFSET                           7
+#define D18F1xDC_Reserved_11_7_WIDTH                            5
+#define D18F1xDC_Reserved_11_7_MASK                             0xf80
+#define D18F1xDC_IOLimit_24_12__OFFSET                          12
+#define D18F1xDC_IOLimit_24_12__WIDTH                           13
+#define D18F1xDC_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xDC_Reserved_31_25_OFFSET                          25
+#define D18F1xDC_Reserved_31_25_WIDTH                           7
+#define D18F1xDC_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xDC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xDC_STRUCT;
+
+// **** D18F1xE0 Register Definition ****
+// Address
+#define D18F1xE0_ADDRESS                                        0xe0
+
+// Type
+#define D18F1xE0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xE0_RE_OFFSET                                      0
+#define D18F1xE0_RE_WIDTH                                       1
+#define D18F1xE0_RE_MASK                                        0x1
+#define D18F1xE0_WE_OFFSET                                      1
+#define D18F1xE0_WE_WIDTH                                       1
+#define D18F1xE0_WE_MASK                                        0x2
+#define D18F1xE0_DevCmpEn_OFFSET                                2
+#define D18F1xE0_DevCmpEn_WIDTH                                 1
+#define D18F1xE0_DevCmpEn_MASK                                  0x4
+#define D18F1xE0_Reserved_15_3_OFFSET                           3
+#define D18F1xE0_Reserved_15_3_WIDTH                            13
+#define D18F1xE0_Reserved_15_3_MASK                             0xfff8
+#define D18F1xE0_BusNumBase_7_0__OFFSET                         16
+#define D18F1xE0_BusNumBase_7_0__WIDTH                          8
+#define D18F1xE0_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xE0_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xE0_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xE0_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xE0_STRUCT;
+
+// **** D18F1xE4 Register Definition ****
+// Address
+#define D18F1xE4_ADDRESS                                        0xe4
+
+// Type
+#define D18F1xE4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xE4_RE_OFFSET                                      0
+#define D18F1xE4_RE_WIDTH                                       1
+#define D18F1xE4_RE_MASK                                        0x1
+#define D18F1xE4_WE_OFFSET                                      1
+#define D18F1xE4_WE_WIDTH                                       1
+#define D18F1xE4_WE_MASK                                        0x2
+#define D18F1xE4_DevCmpEn_OFFSET                                2
+#define D18F1xE4_DevCmpEn_WIDTH                                 1
+#define D18F1xE4_DevCmpEn_MASK                                  0x4
+#define D18F1xE4_Reserved_15_3_OFFSET                           3
+#define D18F1xE4_Reserved_15_3_WIDTH                            13
+#define D18F1xE4_Reserved_15_3_MASK                             0xfff8
+#define D18F1xE4_BusNumBase_7_0__OFFSET                         16
+#define D18F1xE4_BusNumBase_7_0__WIDTH                          8
+#define D18F1xE4_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xE4_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xE4_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xE4_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xE4_STRUCT;
+
+// **** D18F1xE8 Register Definition ****
+// Address
+#define D18F1xE8_ADDRESS                                        0xe8
+
+// Type
+#define D18F1xE8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xE8_RE_OFFSET                                      0
+#define D18F1xE8_RE_WIDTH                                       1
+#define D18F1xE8_RE_MASK                                        0x1
+#define D18F1xE8_WE_OFFSET                                      1
+#define D18F1xE8_WE_WIDTH                                       1
+#define D18F1xE8_WE_MASK                                        0x2
+#define D18F1xE8_DevCmpEn_OFFSET                                2
+#define D18F1xE8_DevCmpEn_WIDTH                                 1
+#define D18F1xE8_DevCmpEn_MASK                                  0x4
+#define D18F1xE8_Reserved_15_3_OFFSET                           3
+#define D18F1xE8_Reserved_15_3_WIDTH                            13
+#define D18F1xE8_Reserved_15_3_MASK                             0xfff8
+#define D18F1xE8_BusNumBase_7_0__OFFSET                         16
+#define D18F1xE8_BusNumBase_7_0__WIDTH                          8
+#define D18F1xE8_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xE8_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xE8_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xE8_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xE8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xE8_STRUCT;
+
+// **** D18F1xEC Register Definition ****
+// Address
+#define D18F1xEC_ADDRESS                                        0xec
+
+// Type
+#define D18F1xEC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xEC_RE_OFFSET                                      0
+#define D18F1xEC_RE_WIDTH                                       1
+#define D18F1xEC_RE_MASK                                        0x1
+#define D18F1xEC_WE_OFFSET                                      1
+#define D18F1xEC_WE_WIDTH                                       1
+#define D18F1xEC_WE_MASK                                        0x2
+#define D18F1xEC_DevCmpEn_OFFSET                                2
+#define D18F1xEC_DevCmpEn_WIDTH                                 1
+#define D18F1xEC_DevCmpEn_MASK                                  0x4
+#define D18F1xEC_Reserved_15_3_OFFSET                           3
+#define D18F1xEC_Reserved_15_3_WIDTH                            13
+#define D18F1xEC_Reserved_15_3_MASK                             0xfff8
+#define D18F1xEC_BusNumBase_7_0__OFFSET                         16
+#define D18F1xEC_BusNumBase_7_0__WIDTH                          8
+#define D18F1xEC_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xEC_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xEC_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xEC_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xEC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xEC_STRUCT;
+
+// **** D18F1xF0 Register Definition ****
+// Address
+#define D18F1xF0_ADDRESS                                        0xf0
+
+// Type
+#define D18F1xF0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xF0_DramHoleValid_OFFSET                           0
+#define D18F1xF0_DramHoleValid_WIDTH                            1
+#define D18F1xF0_DramHoleValid_MASK                             0x1
+#define D18F1xF0_DramMemHoistValid_OFFSET                       1
+#define D18F1xF0_DramMemHoistValid_WIDTH                        1
+#define D18F1xF0_DramMemHoistValid_MASK                         0x2
+#define D18F1xF0_Reserved_2_2_OFFSET                            2
+#define D18F1xF0_Reserved_2_2_WIDTH                             1
+#define D18F1xF0_Reserved_2_2_MASK                              0x4
+#define D18F1xF0_Reserved_6_3_OFFSET                            3
+#define D18F1xF0_Reserved_6_3_WIDTH                             4
+#define D18F1xF0_Reserved_6_3_MASK                              0x78
+#define D18F1xF0_DramHoleOffset_31_23__OFFSET                   7
+#define D18F1xF0_DramHoleOffset_31_23__WIDTH                    9
+#define D18F1xF0_DramHoleOffset_31_23__MASK                     0xff80
+#define D18F1xF0_Reserved_23_16_OFFSET                          16
+#define D18F1xF0_Reserved_23_16_WIDTH                           8
+#define D18F1xF0_Reserved_23_16_MASK                            0xff0000
+#define D18F1xF0_DramHoleBase_31_24__OFFSET                     24
+#define D18F1xF0_DramHoleBase_31_24__WIDTH                      8
+#define D18F1xF0_DramHoleBase_31_24__MASK                       0xff000000
+
+/// D18F1xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DramHoleValid:1 ; ///<
+    UINT32                                        DramMemHoistValid:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             Reserved_6_3:4 ; ///<
+    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
+    UINT32                                           Reserved_23_16:8 ; ///<
+    UINT32                                      DramHoleBase_31_24_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xF0_STRUCT;
+
+// **** D18F1xF4 Register Definition ****
+// Address
+#define D18F1xF4_ADDRESS                                        0xf4
+
+// Type
+#define D18F1xF4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xF4_VE_OFFSET                                      0
+#define D18F1xF4_VE_WIDTH                                       1
+#define D18F1xF4_VE_MASK                                        0x1
+#define D18F1xF4_NP_OFFSET                                      1
+#define D18F1xF4_NP_WIDTH                                       1
+#define D18F1xF4_NP_MASK                                        0x2
+#define D18F1xF4_Reserved_2_2_OFFSET                            2
+#define D18F1xF4_Reserved_2_2_WIDTH                             1
+#define D18F1xF4_Reserved_2_2_MASK                              0x4
+#define D18F1xF4_Lock_OFFSET                                    3
+#define D18F1xF4_Lock_WIDTH                                     1
+#define D18F1xF4_Lock_MASK                                      0x8
+#define D18F1xF4_DstNode_OFFSET                                 4
+#define D18F1xF4_DstNode_WIDTH                                  3
+#define D18F1xF4_DstNode_MASK                                   0x70
+#define D18F1xF4_Reserved_11_7_OFFSET                           7
+#define D18F1xF4_Reserved_11_7_WIDTH                            5
+#define D18F1xF4_Reserved_11_7_MASK                             0xf80
+#define D18F1xF4_DstLink_OFFSET                                 12
+#define D18F1xF4_DstLink_WIDTH                                  2
+#define D18F1xF4_DstLink_MASK                                   0x3000
+#define D18F1xF4_DstSubLink_OFFSET                              14
+#define D18F1xF4_DstSubLink_WIDTH                               1
+#define D18F1xF4_DstSubLink_MASK                                0x4000
+#define D18F1xF4_Reserved_31_15_OFFSET                          15
+#define D18F1xF4_Reserved_31_15_WIDTH                           17
+#define D18F1xF4_Reserved_31_15_MASK                            0xffff8000
+
+/// D18F1xF4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xF4_STRUCT;
+
+// **** D18F1x10C Register Definition ****
+// Address
+#define D18F1x10C_ADDRESS                                       0x10c
+
+// Type
+#define D18F1x10C_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x10C_DctCfgSel_OFFSET                              0
+#define D18F1x10C_DctCfgSel_WIDTH                               1
+#define D18F1x10C_DctCfgSel_MASK                                0x1
+#define D18F1x10C_Reserved_2_1_OFFSET                           1
+#define D18F1x10C_Reserved_2_1_WIDTH                            2
+#define D18F1x10C_Reserved_2_1_MASK                             0x6
+#define D18F1x10C_MemPsSel_OFFSET                               3
+#define D18F1x10C_MemPsSel_WIDTH                                1
+#define D18F1x10C_MemPsSel_MASK                                 0x8
+#define D18F1x10C_NbPsSel_OFFSET                                4
+#define D18F1x10C_NbPsSel_WIDTH                                 2
+#define D18F1x10C_NbPsSel_MASK                                  0x30
+#define D18F1x10C_Unused_31_6_OFFSET                            6
+#define D18F1x10C_Unused_31_6_WIDTH                             26
+#define D18F1x10C_Unused_31_6_MASK                              0xffffffc0
+
+/// D18F1x10C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctCfgSel:1 ; ///<
+    UINT32                                             Reserved_2_1:2 ; ///<
+    UINT32                                                 MemPsSel:1 ; ///<
+    UINT32                                                  NbPsSel:2 ; ///<
+    UINT32                                              Unused_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x10C_STRUCT;
+
+// **** D18F1x120 Register Definition ****
+// Address
+#define D18F1x120_ADDRESS                                       0x120
+
+// Type
+#define D18F1x120_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x120_DramBaseAddr_47_27__OFFSET                    0
+#define D18F1x120_DramBaseAddr_47_27__WIDTH                     21
+#define D18F1x120_DramBaseAddr_47_27__MASK                      0x1fffff
+#define D18F1x120_Reserved_31_21_OFFSET                         21
+#define D18F1x120_Reserved_31_21_WIDTH                          11
+#define D18F1x120_Reserved_31_21_MASK                           0xffe00000
+
+/// D18F1x120
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      DramBaseAddr_47_27_:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x120_STRUCT;
+
+// **** D18F1x124 Register Definition ****
+// Address
+#define D18F1x124_ADDRESS                                       0x124
+
+// Type
+#define D18F1x124_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x124_DramLimitAddr_47_27__OFFSET                   0
+#define D18F1x124_DramLimitAddr_47_27__WIDTH                    21
+#define D18F1x124_DramLimitAddr_47_27__MASK                     0x1fffff
+#define D18F1x124_Reserved_31_21_OFFSET                         21
+#define D18F1x124_Reserved_31_21_WIDTH                          11
+#define D18F1x124_Reserved_31_21_MASK                           0xffe00000
+
+/// D18F1x124
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     DramLimitAddr_47_27_:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x124_STRUCT;
+
+// **** D18F1x140 Register Definition ****
+// Address
+#define D18F1x140_ADDRESS                                       0x140
+
+// Type
+#define D18F1x140_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x140_DramBase_47_40__OFFSET                        0
+#define D18F1x140_DramBase_47_40__WIDTH                         8
+#define D18F1x140_DramBase_47_40__MASK                          0xff
+#define D18F1x140_Reserved_31_8_OFFSET                          8
+#define D18F1x140_Reserved_31_8_WIDTH                           24
+#define D18F1x140_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F1x140
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          DramBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x140_STRUCT;
+
+// **** D18F1x144 Register Definition ****
+// Address
+#define D18F1x144_ADDRESS                                       0x144
+
+// Type
+#define D18F1x144_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x144_DramLimit_47_40__OFFSET                       0
+#define D18F1x144_DramLimit_47_40__WIDTH                        8
+#define D18F1x144_DramLimit_47_40__MASK                         0xff
+#define D18F1x144_Reserved_31_8_OFFSET                          8
+#define D18F1x144_Reserved_31_8_WIDTH                           24
+#define D18F1x144_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F1x144
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         DramLimit_47_40_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x144_STRUCT;
+
+// **** D18F1x180 Register Definition ****
+// Address
+#define D18F1x180_ADDRESS                                       0x180
+
+// Type
+#define D18F1x180_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x180_MMIOBase_47_40__OFFSET                        0
+#define D18F1x180_MMIOBase_47_40__WIDTH                         8
+#define D18F1x180_MMIOBase_47_40__MASK                          0xff
+#define D18F1x180_Reserved_15_8_OFFSET                          8
+#define D18F1x180_Reserved_15_8_WIDTH                           8
+#define D18F1x180_Reserved_15_8_MASK                            0xff00
+#define D18F1x180_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x180_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x180_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x180_Reserved_31_24_OFFSET                         24
+#define D18F1x180_Reserved_31_24_WIDTH                          8
+#define D18F1x180_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x180
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x180_STRUCT;
+
+// **** D18F1x184 Register Definition ****
+// Address
+#define D18F1x184_ADDRESS                                       0x184
+
+// Type
+#define D18F1x184_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x184_MMIOBase_47_40__OFFSET                        0
+#define D18F1x184_MMIOBase_47_40__WIDTH                         8
+#define D18F1x184_MMIOBase_47_40__MASK                          0xff
+#define D18F1x184_Reserved_15_8_OFFSET                          8
+#define D18F1x184_Reserved_15_8_WIDTH                           8
+#define D18F1x184_Reserved_15_8_MASK                            0xff00
+#define D18F1x184_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x184_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x184_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x184_Reserved_31_24_OFFSET                         24
+#define D18F1x184_Reserved_31_24_WIDTH                          8
+#define D18F1x184_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x184
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x184_STRUCT;
+
+// **** D18F1x188 Register Definition ****
+// Address
+#define D18F1x188_ADDRESS                                       0x188
+
+// Type
+#define D18F1x188_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x188_MMIOBase_47_40__OFFSET                        0
+#define D18F1x188_MMIOBase_47_40__WIDTH                         8
+#define D18F1x188_MMIOBase_47_40__MASK                          0xff
+#define D18F1x188_Reserved_15_8_OFFSET                          8
+#define D18F1x188_Reserved_15_8_WIDTH                           8
+#define D18F1x188_Reserved_15_8_MASK                            0xff00
+#define D18F1x188_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x188_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x188_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x188_Reserved_31_24_OFFSET                         24
+#define D18F1x188_Reserved_31_24_WIDTH                          8
+#define D18F1x188_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x188_STRUCT;
+
+// **** D18F1x18C Register Definition ****
+// Address
+#define D18F1x18C_ADDRESS                                       0x18c
+
+// Type
+#define D18F1x18C_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x18C_MMIOBase_47_40__OFFSET                        0
+#define D18F1x18C_MMIOBase_47_40__WIDTH                         8
+#define D18F1x18C_MMIOBase_47_40__MASK                          0xff
+#define D18F1x18C_Reserved_15_8_OFFSET                          8
+#define D18F1x18C_Reserved_15_8_WIDTH                           8
+#define D18F1x18C_Reserved_15_8_MASK                            0xff00
+#define D18F1x18C_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x18C_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x18C_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x18C_Reserved_31_24_OFFSET                         24
+#define D18F1x18C_Reserved_31_24_WIDTH                          8
+#define D18F1x18C_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x18C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x18C_STRUCT;
+
+// **** D18F1x190 Register Definition ****
+// Address
+#define D18F1x190_ADDRESS                                       0x190
+
+// Type
+#define D18F1x190_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x190_MMIOBase_47_40__OFFSET                        0
+#define D18F1x190_MMIOBase_47_40__WIDTH                         8
+#define D18F1x190_MMIOBase_47_40__MASK                          0xff
+#define D18F1x190_Reserved_15_8_OFFSET                          8
+#define D18F1x190_Reserved_15_8_WIDTH                           8
+#define D18F1x190_Reserved_15_8_MASK                            0xff00
+#define D18F1x190_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x190_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x190_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x190_Reserved_31_24_OFFSET                         24
+#define D18F1x190_Reserved_31_24_WIDTH                          8
+#define D18F1x190_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x190
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x190_STRUCT;
+
+// **** D18F1x194 Register Definition ****
+// Address
+#define D18F1x194_ADDRESS                                       0x194
+
+// Type
+#define D18F1x194_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x194_MMIOBase_47_40__OFFSET                        0
+#define D18F1x194_MMIOBase_47_40__WIDTH                         8
+#define D18F1x194_MMIOBase_47_40__MASK                          0xff
+#define D18F1x194_Reserved_15_8_OFFSET                          8
+#define D18F1x194_Reserved_15_8_WIDTH                           8
+#define D18F1x194_Reserved_15_8_MASK                            0xff00
+#define D18F1x194_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x194_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x194_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x194_Reserved_31_24_OFFSET                         24
+#define D18F1x194_Reserved_31_24_WIDTH                          8
+#define D18F1x194_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x194
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x194_STRUCT;
+
+// **** D18F1x198 Register Definition ****
+// Address
+#define D18F1x198_ADDRESS                                       0x198
+
+// Type
+#define D18F1x198_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x198_MMIOBase_47_40__OFFSET                        0
+#define D18F1x198_MMIOBase_47_40__WIDTH                         8
+#define D18F1x198_MMIOBase_47_40__MASK                          0xff
+#define D18F1x198_Reserved_15_8_OFFSET                          8
+#define D18F1x198_Reserved_15_8_WIDTH                           8
+#define D18F1x198_Reserved_15_8_MASK                            0xff00
+#define D18F1x198_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x198_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x198_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x198_Reserved_31_24_OFFSET                         24
+#define D18F1x198_Reserved_31_24_WIDTH                          8
+#define D18F1x198_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x198
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x198_STRUCT;
+
+// **** D18F1x19C Register Definition ****
+// Address
+#define D18F1x19C_ADDRESS                                       0x19c
+
+// Type
+#define D18F1x19C_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x19C_MMIOBase_47_40__OFFSET                        0
+#define D18F1x19C_MMIOBase_47_40__WIDTH                         8
+#define D18F1x19C_MMIOBase_47_40__MASK                          0xff
+#define D18F1x19C_Reserved_15_8_OFFSET                          8
+#define D18F1x19C_Reserved_15_8_WIDTH                           8
+#define D18F1x19C_Reserved_15_8_MASK                            0xff00
+#define D18F1x19C_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x19C_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x19C_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x19C_Reserved_31_24_OFFSET                         24
+#define D18F1x19C_Reserved_31_24_WIDTH                          8
+#define D18F1x19C_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x19C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x19C_STRUCT;
+
+// **** D18F1x1A0 Register Definition ****
+// Address
+#define D18F1x1A0_ADDRESS                                       0x1a0
+
+// Type
+#define D18F1x1A0_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1A0_RE_OFFSET                                     0
+#define D18F1x1A0_RE_WIDTH                                      1
+#define D18F1x1A0_RE_MASK                                       0x1
+#define D18F1x1A0_WE_OFFSET                                     1
+#define D18F1x1A0_WE_WIDTH                                      1
+#define D18F1x1A0_WE_MASK                                       0x2
+#define D18F1x1A0_Reserved_2_2_OFFSET                           2
+#define D18F1x1A0_Reserved_2_2_WIDTH                            1
+#define D18F1x1A0_Reserved_2_2_MASK                             0x4
+#define D18F1x1A0_Lock_OFFSET                                   3
+#define D18F1x1A0_Lock_WIDTH                                    1
+#define D18F1x1A0_Lock_MASK                                     0x8
+#define D18F1x1A0_Reserved_7_4_OFFSET                           4
+#define D18F1x1A0_Reserved_7_4_WIDTH                            4
+#define D18F1x1A0_Reserved_7_4_MASK                             0xf0
+#define D18F1x1A0_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1A0_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1A0_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1A0_STRUCT;
+
+// **** D18F1x1A4 Register Definition ****
+// Address
+#define D18F1x1A4_ADDRESS                                       0x1a4
+
+// Type
+#define D18F1x1A4_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1A4_DstNode_OFFSET                                0
+#define D18F1x1A4_DstNode_WIDTH                                 3
+#define D18F1x1A4_DstNode_MASK                                  0x7
+#define D18F1x1A4_Reserved_3_3_OFFSET                           3
+#define D18F1x1A4_Reserved_3_3_WIDTH                            1
+#define D18F1x1A4_Reserved_3_3_MASK                             0x8
+#define D18F1x1A4_DstLink_OFFSET                                4
+#define D18F1x1A4_DstLink_WIDTH                                 2
+#define D18F1x1A4_DstLink_MASK                                  0x30
+#define D18F1x1A4_DstSubLink_OFFSET                             6
+#define D18F1x1A4_DstSubLink_WIDTH                              1
+#define D18F1x1A4_DstSubLink_MASK                               0x40
+#define D18F1x1A4_NP_OFFSET                                     7
+#define D18F1x1A4_NP_WIDTH                                      1
+#define D18F1x1A4_NP_MASK                                       0x80
+#define D18F1x1A4_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1A4_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1A4_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1A4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1A4_STRUCT;
+
+// **** D18F1x1A8 Register Definition ****
+// Address
+#define D18F1x1A8_ADDRESS                                       0x1a8
+
+// Type
+#define D18F1x1A8_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1A8_RE_OFFSET                                     0
+#define D18F1x1A8_RE_WIDTH                                      1
+#define D18F1x1A8_RE_MASK                                       0x1
+#define D18F1x1A8_WE_OFFSET                                     1
+#define D18F1x1A8_WE_WIDTH                                      1
+#define D18F1x1A8_WE_MASK                                       0x2
+#define D18F1x1A8_Reserved_2_2_OFFSET                           2
+#define D18F1x1A8_Reserved_2_2_WIDTH                            1
+#define D18F1x1A8_Reserved_2_2_MASK                             0x4
+#define D18F1x1A8_Lock_OFFSET                                   3
+#define D18F1x1A8_Lock_WIDTH                                    1
+#define D18F1x1A8_Lock_MASK                                     0x8
+#define D18F1x1A8_Reserved_7_4_OFFSET                           4
+#define D18F1x1A8_Reserved_7_4_WIDTH                            4
+#define D18F1x1A8_Reserved_7_4_MASK                             0xf0
+#define D18F1x1A8_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1A8_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1A8_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1A8_STRUCT;
+
+// **** D18F1x1AC Register Definition ****
+// Address
+#define D18F1x1AC_ADDRESS                                       0x1ac
+
+// Type
+#define D18F1x1AC_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1AC_DstNode_OFFSET                                0
+#define D18F1x1AC_DstNode_WIDTH                                 3
+#define D18F1x1AC_DstNode_MASK                                  0x7
+#define D18F1x1AC_Reserved_3_3_OFFSET                           3
+#define D18F1x1AC_Reserved_3_3_WIDTH                            1
+#define D18F1x1AC_Reserved_3_3_MASK                             0x8
+#define D18F1x1AC_DstLink_OFFSET                                4
+#define D18F1x1AC_DstLink_WIDTH                                 2
+#define D18F1x1AC_DstLink_MASK                                  0x30
+#define D18F1x1AC_DstSubLink_OFFSET                             6
+#define D18F1x1AC_DstSubLink_WIDTH                              1
+#define D18F1x1AC_DstSubLink_MASK                               0x40
+#define D18F1x1AC_NP_OFFSET                                     7
+#define D18F1x1AC_NP_WIDTH                                      1
+#define D18F1x1AC_NP_MASK                                       0x80
+#define D18F1x1AC_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1AC_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1AC_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1AC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1AC_STRUCT;
+
+// **** D18F1x1B0 Register Definition ****
+// Address
+#define D18F1x1B0_ADDRESS                                       0x1b0
+
+// Type
+#define D18F1x1B0_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1B0_RE_OFFSET                                     0
+#define D18F1x1B0_RE_WIDTH                                      1
+#define D18F1x1B0_RE_MASK                                       0x1
+#define D18F1x1B0_WE_OFFSET                                     1
+#define D18F1x1B0_WE_WIDTH                                      1
+#define D18F1x1B0_WE_MASK                                       0x2
+#define D18F1x1B0_Reserved_2_2_OFFSET                           2
+#define D18F1x1B0_Reserved_2_2_WIDTH                            1
+#define D18F1x1B0_Reserved_2_2_MASK                             0x4
+#define D18F1x1B0_Lock_OFFSET                                   3
+#define D18F1x1B0_Lock_WIDTH                                    1
+#define D18F1x1B0_Lock_MASK                                     0x8
+#define D18F1x1B0_Reserved_7_4_OFFSET                           4
+#define D18F1x1B0_Reserved_7_4_WIDTH                            4
+#define D18F1x1B0_Reserved_7_4_MASK                             0xf0
+#define D18F1x1B0_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1B0_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1B0_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1B0_STRUCT;
+
+// **** D18F1x1B4 Register Definition ****
+// Address
+#define D18F1x1B4_ADDRESS                                       0x1b4
+
+// Type
+#define D18F1x1B4_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1B4_DstNode_OFFSET                                0
+#define D18F1x1B4_DstNode_WIDTH                                 3
+#define D18F1x1B4_DstNode_MASK                                  0x7
+#define D18F1x1B4_Reserved_3_3_OFFSET                           3
+#define D18F1x1B4_Reserved_3_3_WIDTH                            1
+#define D18F1x1B4_Reserved_3_3_MASK                             0x8
+#define D18F1x1B4_DstLink_OFFSET                                4
+#define D18F1x1B4_DstLink_WIDTH                                 2
+#define D18F1x1B4_DstLink_MASK                                  0x30
+#define D18F1x1B4_DstSubLink_OFFSET                             6
+#define D18F1x1B4_DstSubLink_WIDTH                              1
+#define D18F1x1B4_DstSubLink_MASK                               0x40
+#define D18F1x1B4_NP_OFFSET                                     7
+#define D18F1x1B4_NP_WIDTH                                      1
+#define D18F1x1B4_NP_MASK                                       0x80
+#define D18F1x1B4_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1B4_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1B4_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1B4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1B4_STRUCT;
+
+// **** D18F1x1B8 Register Definition ****
+// Address
+#define D18F1x1B8_ADDRESS                                       0x1b8
+
+// Type
+#define D18F1x1B8_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1B8_RE_OFFSET                                     0
+#define D18F1x1B8_RE_WIDTH                                      1
+#define D18F1x1B8_RE_MASK                                       0x1
+#define D18F1x1B8_WE_OFFSET                                     1
+#define D18F1x1B8_WE_WIDTH                                      1
+#define D18F1x1B8_WE_MASK                                       0x2
+#define D18F1x1B8_Reserved_2_2_OFFSET                           2
+#define D18F1x1B8_Reserved_2_2_WIDTH                            1
+#define D18F1x1B8_Reserved_2_2_MASK                             0x4
+#define D18F1x1B8_Lock_OFFSET                                   3
+#define D18F1x1B8_Lock_WIDTH                                    1
+#define D18F1x1B8_Lock_MASK                                     0x8
+#define D18F1x1B8_Reserved_7_4_OFFSET                           4
+#define D18F1x1B8_Reserved_7_4_WIDTH                            4
+#define D18F1x1B8_Reserved_7_4_MASK                             0xf0
+#define D18F1x1B8_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1B8_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1B8_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1B8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1B8_STRUCT;
+
+// **** D18F1x1BC Register Definition ****
+// Address
+#define D18F1x1BC_ADDRESS                                       0x1bc
+
+// Type
+#define D18F1x1BC_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1BC_DstNode_OFFSET                                0
+#define D18F1x1BC_DstNode_WIDTH                                 3
+#define D18F1x1BC_DstNode_MASK                                  0x7
+#define D18F1x1BC_Reserved_3_3_OFFSET                           3
+#define D18F1x1BC_Reserved_3_3_WIDTH                            1
+#define D18F1x1BC_Reserved_3_3_MASK                             0x8
+#define D18F1x1BC_DstLink_OFFSET                                4
+#define D18F1x1BC_DstLink_WIDTH                                 2
+#define D18F1x1BC_DstLink_MASK                                  0x30
+#define D18F1x1BC_DstSubLink_OFFSET                             6
+#define D18F1x1BC_DstSubLink_WIDTH                              1
+#define D18F1x1BC_DstSubLink_MASK                               0x40
+#define D18F1x1BC_NP_OFFSET                                     7
+#define D18F1x1BC_NP_WIDTH                                      1
+#define D18F1x1BC_NP_MASK                                       0x80
+#define D18F1x1BC_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1BC_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1BC_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1BC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1BC_STRUCT;
+
+// **** D18F1x1C0 Register Definition ****
+// Address
+#define D18F1x1C0_ADDRESS                                       0x1c0
+
+// Type
+#define D18F1x1C0_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1C0_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1C0_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1C0_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1C0_Reserved_15_8_OFFSET                          8
+#define D18F1x1C0_Reserved_15_8_WIDTH                           8
+#define D18F1x1C0_Reserved_15_8_MASK                            0xff00
+#define D18F1x1C0_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1C0_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1C0_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1C0_Reserved_31_24_OFFSET                         24
+#define D18F1x1C0_Reserved_31_24_WIDTH                          8
+#define D18F1x1C0_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1C0_STRUCT;
+
+// **** D18F1x1C4 Register Definition ****
+// Address
+#define D18F1x1C4_ADDRESS                                       0x1c4
+
+// Type
+#define D18F1x1C4_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1C4_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1C4_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1C4_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1C4_Reserved_15_8_OFFSET                          8
+#define D18F1x1C4_Reserved_15_8_WIDTH                           8
+#define D18F1x1C4_Reserved_15_8_MASK                            0xff00
+#define D18F1x1C4_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1C4_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1C4_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1C4_Reserved_31_24_OFFSET                         24
+#define D18F1x1C4_Reserved_31_24_WIDTH                          8
+#define D18F1x1C4_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1C4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1C4_STRUCT;
+
+// **** D18F1x1C8 Register Definition ****
+// Address
+#define D18F1x1C8_ADDRESS                                       0x1c8
+
+// Type
+#define D18F1x1C8_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1C8_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1C8_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1C8_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1C8_Reserved_15_8_OFFSET                          8
+#define D18F1x1C8_Reserved_15_8_WIDTH                           8
+#define D18F1x1C8_Reserved_15_8_MASK                            0xff00
+#define D18F1x1C8_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1C8_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1C8_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1C8_Reserved_31_24_OFFSET                         24
+#define D18F1x1C8_Reserved_31_24_WIDTH                          8
+#define D18F1x1C8_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1C8_STRUCT;
+
+// **** D18F1x1CC Register Definition ****
+// Address
+#define D18F1x1CC_ADDRESS                                       0x1cc
+
+// Type
+#define D18F1x1CC_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1CC_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1CC_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1CC_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1CC_Reserved_15_8_OFFSET                          8
+#define D18F1x1CC_Reserved_15_8_WIDTH                           8
+#define D18F1x1CC_Reserved_15_8_MASK                            0xff00
+#define D18F1x1CC_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1CC_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1CC_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1CC_Reserved_31_24_OFFSET                         24
+#define D18F1x1CC_Reserved_31_24_WIDTH                          8
+#define D18F1x1CC_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1CC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1CC_STRUCT;
+
+// **** D18F2x00 Register Definition ****
+// Address
+#define D18F2x00_ADDRESS                                        0x0
+
+// Type
+#define D18F2x00_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x00_VendorID_OFFSET                                0
+#define D18F2x00_VendorID_WIDTH                                 16
+#define D18F2x00_VendorID_MASK                                  0xffff
+#define D18F2x00_DeviceID_OFFSET                                16
+#define D18F2x00_DeviceID_WIDTH                                 16
+#define D18F2x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F2x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x00_STRUCT;
+
+// **** D18F2x08 Register Definition ****
+// Address
+#define D18F2x08_ADDRESS                                        0x8
+
+// Type
+#define D18F2x08_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x08_RevID_OFFSET                                   0
+#define D18F2x08_RevID_WIDTH                                    8
+#define D18F2x08_RevID_MASK                                     0xff
+#define D18F2x08_ClassCode_OFFSET                               8
+#define D18F2x08_ClassCode_WIDTH                                24
+#define D18F2x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F2x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x08_STRUCT;
+
+// **** D18F2x0C Register Definition ****
+// Address
+#define D18F2x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F2x0C_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x0C_HeaderTypeReg_OFFSET                           0
+#define D18F2x0C_HeaderTypeReg_WIDTH                            32
+#define D18F2x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F2x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x0C_STRUCT;
+
+// **** D18F2x40_dct1 Register Definition ****
+// Address
+#define D18F2x40_dct1_ADDRESS                                   0x40
+
+// Type
+#define D18F2x40_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x40_dct1_CSEnable_OFFSET                           0
+#define D18F2x40_dct1_CSEnable_WIDTH                            1
+#define D18F2x40_dct1_CSEnable_MASK                             0x1
+#define D18F2x40_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x40_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x40_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x40_dct1_TestFail_OFFSET                           2
+#define D18F2x40_dct1_TestFail_WIDTH                            1
+#define D18F2x40_dct1_TestFail_MASK                             0x4
+#define D18F2x40_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x40_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x40_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x40_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x40_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x40_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x40_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x40_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x40_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x40_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x40_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x40_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x40_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x40_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x40_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x40_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x40_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x40_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x40_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x40_dct1_STRUCT;
+
+// **** D18F2x40_dct0 Register Definition ****
+// Address
+#define D18F2x40_dct0_ADDRESS                                   0x40
+
+// Type
+#define D18F2x40_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x40_dct0_CSEnable_OFFSET                           0
+#define D18F2x40_dct0_CSEnable_WIDTH                            1
+#define D18F2x40_dct0_CSEnable_MASK                             0x1
+#define D18F2x40_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x40_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x40_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x40_dct0_TestFail_OFFSET                           2
+#define D18F2x40_dct0_TestFail_WIDTH                            1
+#define D18F2x40_dct0_TestFail_MASK                             0x4
+#define D18F2x40_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x40_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x40_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x40_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x40_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x40_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x40_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x40_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x40_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x40_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x40_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x40_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x40_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x40_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x40_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x40_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x40_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x40_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x40_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x40_dct0_STRUCT;
+
+// **** D18F2x44_dct1 Register Definition ****
+// Address
+#define D18F2x44_dct1_ADDRESS                                   0x44
+
+// Type
+#define D18F2x44_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x44_dct1_CSEnable_OFFSET                           0
+#define D18F2x44_dct1_CSEnable_WIDTH                            1
+#define D18F2x44_dct1_CSEnable_MASK                             0x1
+#define D18F2x44_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x44_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x44_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x44_dct1_TestFail_OFFSET                           2
+#define D18F2x44_dct1_TestFail_WIDTH                            1
+#define D18F2x44_dct1_TestFail_MASK                             0x4
+#define D18F2x44_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x44_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x44_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x44_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x44_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x44_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x44_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x44_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x44_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x44_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x44_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x44_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x44_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x44_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x44_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x44_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x44_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x44_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x44_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x44_dct1_STRUCT;
+
+// **** D18F2x44_dct0 Register Definition ****
+// Address
+#define D18F2x44_dct0_ADDRESS                                   0x44
+
+// Type
+#define D18F2x44_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x44_dct0_CSEnable_OFFSET                           0
+#define D18F2x44_dct0_CSEnable_WIDTH                            1
+#define D18F2x44_dct0_CSEnable_MASK                             0x1
+#define D18F2x44_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x44_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x44_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x44_dct0_TestFail_OFFSET                           2
+#define D18F2x44_dct0_TestFail_WIDTH                            1
+#define D18F2x44_dct0_TestFail_MASK                             0x4
+#define D18F2x44_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x44_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x44_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x44_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x44_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x44_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x44_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x44_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x44_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x44_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x44_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x44_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x44_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x44_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x44_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x44_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x44_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x44_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x44_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x44_dct0_STRUCT;
+
+// **** D18F2x48_dct1 Register Definition ****
+// Address
+#define D18F2x48_dct1_ADDRESS                                   0x48
+
+// Type
+#define D18F2x48_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x48_dct1_CSEnable_OFFSET                           0
+#define D18F2x48_dct1_CSEnable_WIDTH                            1
+#define D18F2x48_dct1_CSEnable_MASK                             0x1
+#define D18F2x48_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x48_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x48_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x48_dct1_TestFail_OFFSET                           2
+#define D18F2x48_dct1_TestFail_WIDTH                            1
+#define D18F2x48_dct1_TestFail_MASK                             0x4
+#define D18F2x48_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x48_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x48_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x48_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x48_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x48_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x48_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x48_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x48_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x48_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x48_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x48_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x48_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x48_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x48_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x48_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x48_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x48_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x48_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x48_dct1_STRUCT;
+
+// **** D18F2x48_dct0 Register Definition ****
+// Address
+#define D18F2x48_dct0_ADDRESS                                   0x48
+
+// Type
+#define D18F2x48_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x48_dct0_CSEnable_OFFSET                           0
+#define D18F2x48_dct0_CSEnable_WIDTH                            1
+#define D18F2x48_dct0_CSEnable_MASK                             0x1
+#define D18F2x48_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x48_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x48_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x48_dct0_TestFail_OFFSET                           2
+#define D18F2x48_dct0_TestFail_WIDTH                            1
+#define D18F2x48_dct0_TestFail_MASK                             0x4
+#define D18F2x48_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x48_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x48_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x48_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x48_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x48_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x48_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x48_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x48_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x48_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x48_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x48_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x48_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x48_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x48_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x48_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x48_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x48_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x48_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x48_dct0_STRUCT;
+
+// **** D18F2x4C_dct1 Register Definition ****
+// Address
+#define D18F2x4C_dct1_ADDRESS                                   0x4c
+
+// Type
+#define D18F2x4C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x4C_dct1_CSEnable_OFFSET                           0
+#define D18F2x4C_dct1_CSEnable_WIDTH                            1
+#define D18F2x4C_dct1_CSEnable_MASK                             0x1
+#define D18F2x4C_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x4C_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x4C_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x4C_dct1_TestFail_OFFSET                           2
+#define D18F2x4C_dct1_TestFail_WIDTH                            1
+#define D18F2x4C_dct1_TestFail_MASK                             0x4
+#define D18F2x4C_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x4C_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x4C_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x4C_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x4C_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x4C_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x4C_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x4C_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x4C_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x4C_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x4C_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x4C_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x4C_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x4C_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x4C_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x4C_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x4C_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x4C_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x4C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x4C_dct1_STRUCT;
+
+// **** D18F2x4C_dct0 Register Definition ****
+// Address
+#define D18F2x4C_dct0_ADDRESS                                   0x4c
+
+// Type
+#define D18F2x4C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x4C_dct0_CSEnable_OFFSET                           0
+#define D18F2x4C_dct0_CSEnable_WIDTH                            1
+#define D18F2x4C_dct0_CSEnable_MASK                             0x1
+#define D18F2x4C_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x4C_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x4C_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x4C_dct0_TestFail_OFFSET                           2
+#define D18F2x4C_dct0_TestFail_WIDTH                            1
+#define D18F2x4C_dct0_TestFail_MASK                             0x4
+#define D18F2x4C_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x4C_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x4C_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x4C_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x4C_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x4C_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x4C_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x4C_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x4C_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x4C_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x4C_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x4C_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x4C_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x4C_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x4C_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x4C_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x4C_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x4C_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x4C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x4C_dct0_STRUCT;
+
+// **** D18F2x50_dct1 Register Definition ****
+// Address
+#define D18F2x50_dct1_ADDRESS                                   0x50
+
+// Type
+#define D18F2x50_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x50_dct1_CSEnable_OFFSET                           0
+#define D18F2x50_dct1_CSEnable_WIDTH                            1
+#define D18F2x50_dct1_CSEnable_MASK                             0x1
+#define D18F2x50_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x50_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x50_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x50_dct1_TestFail_OFFSET                           2
+#define D18F2x50_dct1_TestFail_WIDTH                            1
+#define D18F2x50_dct1_TestFail_MASK                             0x4
+#define D18F2x50_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x50_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x50_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x50_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x50_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x50_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x50_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x50_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x50_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x50_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x50_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x50_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x50_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x50_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x50_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x50_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x50_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x50_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x50_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x50_dct1_STRUCT;
+
+// **** D18F2x50_dct0 Register Definition ****
+// Address
+#define D18F2x50_dct0_ADDRESS                                   0x50
+
+// Type
+#define D18F2x50_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x50_dct0_CSEnable_OFFSET                           0
+#define D18F2x50_dct0_CSEnable_WIDTH                            1
+#define D18F2x50_dct0_CSEnable_MASK                             0x1
+#define D18F2x50_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x50_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x50_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x50_dct0_TestFail_OFFSET                           2
+#define D18F2x50_dct0_TestFail_WIDTH                            1
+#define D18F2x50_dct0_TestFail_MASK                             0x4
+#define D18F2x50_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x50_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x50_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x50_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x50_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x50_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x50_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x50_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x50_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x50_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x50_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x50_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x50_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x50_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x50_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x50_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x50_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x50_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x50_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x50_dct0_STRUCT;
+
+// **** D18F2x54_dct0 Register Definition ****
+// Address
+#define D18F2x54_dct0_ADDRESS                                   0x54
+
+// Type
+#define D18F2x54_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x54_dct0_CSEnable_OFFSET                           0
+#define D18F2x54_dct0_CSEnable_WIDTH                            1
+#define D18F2x54_dct0_CSEnable_MASK                             0x1
+#define D18F2x54_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x54_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x54_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x54_dct0_TestFail_OFFSET                           2
+#define D18F2x54_dct0_TestFail_WIDTH                            1
+#define D18F2x54_dct0_TestFail_MASK                             0x4
+#define D18F2x54_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x54_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x54_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x54_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x54_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x54_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x54_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x54_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x54_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x54_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x54_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x54_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x54_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x54_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x54_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x54_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x54_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x54_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x54_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x54_dct0_STRUCT;
+
+// **** D18F2x54_dct1 Register Definition ****
+// Address
+#define D18F2x54_dct1_ADDRESS                                   0x54
+
+// Type
+#define D18F2x54_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x54_dct1_CSEnable_OFFSET                           0
+#define D18F2x54_dct1_CSEnable_WIDTH                            1
+#define D18F2x54_dct1_CSEnable_MASK                             0x1
+#define D18F2x54_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x54_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x54_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x54_dct1_TestFail_OFFSET                           2
+#define D18F2x54_dct1_TestFail_WIDTH                            1
+#define D18F2x54_dct1_TestFail_MASK                             0x4
+#define D18F2x54_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x54_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x54_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x54_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x54_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x54_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x54_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x54_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x54_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x54_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x54_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x54_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x54_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x54_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x54_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x54_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x54_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x54_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x54_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x54_dct1_STRUCT;
+
+// **** D18F2x58_dct1 Register Definition ****
+// Address
+#define D18F2x58_dct1_ADDRESS                                   0x58
+
+// Type
+#define D18F2x58_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x58_dct1_CSEnable_OFFSET                           0
+#define D18F2x58_dct1_CSEnable_WIDTH                            1
+#define D18F2x58_dct1_CSEnable_MASK                             0x1
+#define D18F2x58_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x58_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x58_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x58_dct1_TestFail_OFFSET                           2
+#define D18F2x58_dct1_TestFail_WIDTH                            1
+#define D18F2x58_dct1_TestFail_MASK                             0x4
+#define D18F2x58_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x58_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x58_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x58_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x58_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x58_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x58_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x58_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x58_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x58_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x58_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x58_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x58_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x58_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x58_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x58_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x58_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x58_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x58_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x58_dct1_STRUCT;
+
+// **** D18F2x58_dct0 Register Definition ****
+// Address
+#define D18F2x58_dct0_ADDRESS                                   0x58
+
+// Type
+#define D18F2x58_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x58_dct0_CSEnable_OFFSET                           0
+#define D18F2x58_dct0_CSEnable_WIDTH                            1
+#define D18F2x58_dct0_CSEnable_MASK                             0x1
+#define D18F2x58_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x58_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x58_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x58_dct0_TestFail_OFFSET                           2
+#define D18F2x58_dct0_TestFail_WIDTH                            1
+#define D18F2x58_dct0_TestFail_MASK                             0x4
+#define D18F2x58_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x58_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x58_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x58_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x58_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x58_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x58_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x58_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x58_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x58_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x58_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x58_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x58_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x58_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x58_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x58_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x58_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x58_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x58_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x58_dct0_STRUCT;
+
+// **** D18F2x5C_dct1 Register Definition ****
+// Address
+#define D18F2x5C_dct1_ADDRESS                                   0x5c
+
+// Type
+#define D18F2x5C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x5C_dct1_CSEnable_OFFSET                           0
+#define D18F2x5C_dct1_CSEnable_WIDTH                            1
+#define D18F2x5C_dct1_CSEnable_MASK                             0x1
+#define D18F2x5C_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x5C_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x5C_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x5C_dct1_TestFail_OFFSET                           2
+#define D18F2x5C_dct1_TestFail_WIDTH                            1
+#define D18F2x5C_dct1_TestFail_MASK                             0x4
+#define D18F2x5C_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x5C_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x5C_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x5C_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x5C_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x5C_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x5C_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x5C_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x5C_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x5C_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x5C_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x5C_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x5C_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x5C_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x5C_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x5C_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x5C_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x5C_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x5C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x5C_dct1_STRUCT;
+
+// **** D18F2x5C_dct0 Register Definition ****
+// Address
+#define D18F2x5C_dct0_ADDRESS                                   0x5c
+
+// Type
+#define D18F2x5C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x5C_dct0_CSEnable_OFFSET                           0
+#define D18F2x5C_dct0_CSEnable_WIDTH                            1
+#define D18F2x5C_dct0_CSEnable_MASK                             0x1
+#define D18F2x5C_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x5C_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x5C_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x5C_dct0_TestFail_OFFSET                           2
+#define D18F2x5C_dct0_TestFail_WIDTH                            1
+#define D18F2x5C_dct0_TestFail_MASK                             0x4
+#define D18F2x5C_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x5C_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x5C_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x5C_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x5C_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x5C_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x5C_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x5C_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x5C_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x5C_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x5C_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x5C_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x5C_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x5C_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x5C_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x5C_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x5C_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x5C_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x5C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x5C_dct0_STRUCT;
+
+// **** D18F2x60_dct1 Register Definition ****
+// Address
+#define D18F2x60_dct1_ADDRESS                                   0x60
+
+// Type
+#define D18F2x60_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x60_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x60_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x60_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x60_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x60_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x60_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x60_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x60_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x60_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x60_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x60_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x60_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x60_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x60_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x60_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x60_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x60_dct1_STRUCT;
+
+// **** D18F2x60_dct0 Register Definition ****
+// Address
+#define D18F2x60_dct0_ADDRESS                                   0x60
+
+// Type
+#define D18F2x60_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x60_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x60_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x60_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x60_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x60_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x60_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x60_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x60_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x60_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x60_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x60_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x60_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x60_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x60_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x60_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x60_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x60_dct0_STRUCT;
+
+// **** D18F2x64_dct0 Register Definition ****
+// Address
+#define D18F2x64_dct0_ADDRESS                                   0x64
+
+// Type
+#define D18F2x64_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x64_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x64_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x64_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x64_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x64_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x64_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x64_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x64_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x64_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x64_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x64_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x64_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x64_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x64_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x64_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x64_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x64_dct0_STRUCT;
+
+// **** D18F2x64_dct1 Register Definition ****
+// Address
+#define D18F2x64_dct1_ADDRESS                                   0x64
+
+// Type
+#define D18F2x64_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x64_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x64_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x64_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x64_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x64_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x64_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x64_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x64_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x64_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x64_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x64_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x64_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x64_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x64_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x64_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x64_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x64_dct1_STRUCT;
+
+// **** D18F2x68_dct1 Register Definition ****
+// Address
+#define D18F2x68_dct1_ADDRESS                                   0x68
+
+// Type
+#define D18F2x68_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x68_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x68_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x68_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x68_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x68_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x68_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x68_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x68_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x68_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x68_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x68_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x68_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x68_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x68_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x68_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x68_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x68_dct1_STRUCT;
+
+// **** D18F2x68_dct0 Register Definition ****
+// Address
+#define D18F2x68_dct0_ADDRESS                                   0x68
+
+// Type
+#define D18F2x68_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x68_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x68_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x68_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x68_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x68_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x68_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x68_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x68_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x68_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x68_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x68_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x68_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x68_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x68_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x68_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x68_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x68_dct0_STRUCT;
+
+// **** D18F2x6C_dct1 Register Definition ****
+// Address
+#define D18F2x6C_dct1_ADDRESS                                   0x6c
+
+// Type
+#define D18F2x6C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x6C_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x6C_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x6C_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x6C_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x6C_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x6C_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x6C_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x6C_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x6C_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x6C_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x6C_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x6C_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x6C_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x6C_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x6C_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x6C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x6C_dct1_STRUCT;
+
+// **** D18F2x6C_dct0 Register Definition ****
+// Address
+#define D18F2x6C_dct0_ADDRESS                                   0x6c
+
+// Type
+#define D18F2x6C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x6C_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x6C_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x6C_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x6C_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x6C_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x6C_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x6C_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x6C_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x6C_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x6C_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x6C_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x6C_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x6C_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x6C_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x6C_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x6C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x6C_dct0_STRUCT;
+
+// **** D18F2x78_dct0 Register Definition ****
+// Address
+#define D18F2x78_dct0_ADDRESS                                   0x78
+
+// Type
+#define D18F2x78_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x78_dct0_Reserved_16_0_OFFSET                      0
+#define D18F2x78_dct0_Reserved_16_0_WIDTH                       17
+#define D18F2x78_dct0_Reserved_16_0_MASK                        0x1ffff
+#define D18F2x78_dct0_AddrCmdTriEn_OFFSET                       17
+#define D18F2x78_dct0_AddrCmdTriEn_WIDTH                        1
+#define D18F2x78_dct0_AddrCmdTriEn_MASK                         0x20000
+#define D18F2x78_dct0_Reserved_31_18_OFFSET                     18
+#define D18F2x78_dct0_Reserved_31_18_WIDTH                      14
+#define D18F2x78_dct0_Reserved_31_18_MASK                       0xfffc0000
+
+/// D18F2x78_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_16_0:17; ///<
+    UINT32                                             AddrCmdTriEn:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x78_dct0_STRUCT;
+
+// **** D18F2x78_dct1 Register Definition ****
+// Address
+#define D18F2x78_dct1_ADDRESS                                   0x78
+
+// Type
+#define D18F2x78_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x78_dct1_Reserved_16_0_OFFSET                      0
+#define D18F2x78_dct1_Reserved_16_0_WIDTH                       17
+#define D18F2x78_dct1_Reserved_16_0_MASK                        0x1ffff
+#define D18F2x78_dct1_AddrCmdTriEn_OFFSET                       17
+#define D18F2x78_dct1_AddrCmdTriEn_WIDTH                        1
+#define D18F2x78_dct1_AddrCmdTriEn_MASK                         0x20000
+#define D18F2x78_dct1_Reserved_31_18_OFFSET                     18
+#define D18F2x78_dct1_Reserved_31_18_WIDTH                      14
+#define D18F2x78_dct1_Reserved_31_18_MASK                       0xfffc0000
+
+/// D18F2x78_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_16_0:17; ///<
+    UINT32                                             AddrCmdTriEn:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x78_dct1_STRUCT;
+
+// **** D18F2x7C_dct1 Register Definition ****
+// Address
+#define D18F2x7C_dct1_ADDRESS                                   0x7c
+
+// Type
+#define D18F2x7C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x7C_dct1_MrsAddress_17_0__OFFSET                   0
+#define D18F2x7C_dct1_MrsAddress_17_0__WIDTH                    18
+#define D18F2x7C_dct1_MrsAddress_17_0__MASK                     0x3ffff
+#define D18F2x7C_dct1_MrsBank_2_0__OFFSET                       18
+#define D18F2x7C_dct1_MrsBank_2_0__WIDTH                        3
+#define D18F2x7C_dct1_MrsBank_2_0__MASK                         0x1c0000
+#define D18F2x7C_dct1_MrsChipSel_OFFSET                         21
+#define D18F2x7C_dct1_MrsChipSel_WIDTH                          3
+#define D18F2x7C_dct1_MrsChipSel_MASK                           0xe00000
+#define D18F2x7C_dct1_Reserved_24_24_OFFSET                     24
+#define D18F2x7C_dct1_Reserved_24_24_WIDTH                      1
+#define D18F2x7C_dct1_Reserved_24_24_MASK                       0x1000000
+#define D18F2x7C_dct1_SendAutoRefresh_OFFSET                    25
+#define D18F2x7C_dct1_SendAutoRefresh_WIDTH                     1
+#define D18F2x7C_dct1_SendAutoRefresh_MASK                      0x2000000
+#define D18F2x7C_dct1_SendMrsCmd_OFFSET                         26
+#define D18F2x7C_dct1_SendMrsCmd_WIDTH                          1
+#define D18F2x7C_dct1_SendMrsCmd_MASK                           0x4000000
+#define D18F2x7C_dct1_DeassertMemRstX_OFFSET                    27
+#define D18F2x7C_dct1_DeassertMemRstX_WIDTH                     1
+#define D18F2x7C_dct1_DeassertMemRstX_MASK                      0x8000000
+#define D18F2x7C_dct1_AssertCke_OFFSET                          28
+#define D18F2x7C_dct1_AssertCke_WIDTH                           1
+#define D18F2x7C_dct1_AssertCke_MASK                            0x10000000
+#define D18F2x7C_dct1_SendZQCmd_OFFSET                          29
+#define D18F2x7C_dct1_SendZQCmd_WIDTH                           1
+#define D18F2x7C_dct1_SendZQCmd_MASK                            0x20000000
+#define D18F2x7C_dct1_SendControlWord_OFFSET                    30
+#define D18F2x7C_dct1_SendControlWord_WIDTH                     1
+#define D18F2x7C_dct1_SendControlWord_MASK                      0x40000000
+#define D18F2x7C_dct1_EnDramInit_OFFSET                         31
+#define D18F2x7C_dct1_EnDramInit_WIDTH                          1
+#define D18F2x7C_dct1_EnDramInit_MASK                           0x80000000
+
+/// D18F2x7C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         MrsAddress_17_0_:18; ///<
+    UINT32                                             MrsBank_2_0_:3 ; ///<
+    UINT32                                               MrsChipSel:3 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                          SendAutoRefresh:1 ; ///<
+    UINT32                                               SendMrsCmd:1 ; ///<
+    UINT32                                          DeassertMemRstX:1 ; ///<
+    UINT32                                                AssertCke:1 ; ///<
+    UINT32                                                SendZQCmd:1 ; ///<
+    UINT32                                          SendControlWord:1 ; ///<
+    UINT32                                               EnDramInit:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x7C_dct1_STRUCT;
+
+// **** D18F2x7C_dct0 Register Definition ****
+// Address
+#define D18F2x7C_dct0_ADDRESS                                   0x7c
+
+// Type
+#define D18F2x7C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x7C_dct0_MrsAddress_17_0__OFFSET                   0
+#define D18F2x7C_dct0_MrsAddress_17_0__WIDTH                    18
+#define D18F2x7C_dct0_MrsAddress_17_0__MASK                     0x3ffff
+#define D18F2x7C_dct0_MrsBank_2_0__OFFSET                       18
+#define D18F2x7C_dct0_MrsBank_2_0__WIDTH                        3
+#define D18F2x7C_dct0_MrsBank_2_0__MASK                         0x1c0000
+#define D18F2x7C_dct0_MrsChipSel_OFFSET                         21
+#define D18F2x7C_dct0_MrsChipSel_WIDTH                          3
+#define D18F2x7C_dct0_MrsChipSel_MASK                           0xe00000
+#define D18F2x7C_dct0_Reserved_24_24_OFFSET                     24
+#define D18F2x7C_dct0_Reserved_24_24_WIDTH                      1
+#define D18F2x7C_dct0_Reserved_24_24_MASK                       0x1000000
+#define D18F2x7C_dct0_SendAutoRefresh_OFFSET                    25
+#define D18F2x7C_dct0_SendAutoRefresh_WIDTH                     1
+#define D18F2x7C_dct0_SendAutoRefresh_MASK                      0x2000000
+#define D18F2x7C_dct0_SendMrsCmd_OFFSET                         26
+#define D18F2x7C_dct0_SendMrsCmd_WIDTH                          1
+#define D18F2x7C_dct0_SendMrsCmd_MASK                           0x4000000
+#define D18F2x7C_dct0_DeassertMemRstX_OFFSET                    27
+#define D18F2x7C_dct0_DeassertMemRstX_WIDTH                     1
+#define D18F2x7C_dct0_DeassertMemRstX_MASK                      0x8000000
+#define D18F2x7C_dct0_AssertCke_OFFSET                          28
+#define D18F2x7C_dct0_AssertCke_WIDTH                           1
+#define D18F2x7C_dct0_AssertCke_MASK                            0x10000000
+#define D18F2x7C_dct0_SendZQCmd_OFFSET                          29
+#define D18F2x7C_dct0_SendZQCmd_WIDTH                           1
+#define D18F2x7C_dct0_SendZQCmd_MASK                            0x20000000
+#define D18F2x7C_dct0_SendControlWord_OFFSET                    30
+#define D18F2x7C_dct0_SendControlWord_WIDTH                     1
+#define D18F2x7C_dct0_SendControlWord_MASK                      0x40000000
+#define D18F2x7C_dct0_EnDramInit_OFFSET                         31
+#define D18F2x7C_dct0_EnDramInit_WIDTH                          1
+#define D18F2x7C_dct0_EnDramInit_MASK                           0x80000000
+
+/// D18F2x7C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         MrsAddress_17_0_:18; ///<
+    UINT32                                             MrsBank_2_0_:3 ; ///<
+    UINT32                                               MrsChipSel:3 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                          SendAutoRefresh:1 ; ///<
+    UINT32                                               SendMrsCmd:1 ; ///<
+    UINT32                                          DeassertMemRstX:1 ; ///<
+    UINT32                                                AssertCke:1 ; ///<
+    UINT32                                                SendZQCmd:1 ; ///<
+    UINT32                                          SendControlWord:1 ; ///<
+    UINT32                                               EnDramInit:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x7C_dct0_STRUCT;
+
+// **** D18F2x80_dct1 Register Definition ****
+// Address
+#define D18F2x80_dct1_ADDRESS                                   0x80
+
+// Type
+#define D18F2x80_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x80_dct1_DimmAddrMap0_OFFSET                       0
+#define D18F2x80_dct1_DimmAddrMap0_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap0_MASK                         0xf
+#define D18F2x80_dct1_DimmAddrMap1_OFFSET                       4
+#define D18F2x80_dct1_DimmAddrMap1_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap1_MASK                         0xf0
+#define D18F2x80_dct1_DimmAddrMap2_OFFSET                       8
+#define D18F2x80_dct1_DimmAddrMap2_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap2_MASK                         0xf00
+#define D18F2x80_dct1_DimmAddrMap3_OFFSET                       12
+#define D18F2x80_dct1_DimmAddrMap3_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap3_MASK                         0xf000
+#define D18F2x80_dct1_Reserved_31_16_OFFSET                     16
+#define D18F2x80_dct1_Reserved_31_16_WIDTH                      16
+#define D18F2x80_dct1_Reserved_31_16_MASK                       0xffff0000
+
+/// D18F2x80_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DimmAddrMap0:4 ; ///<
+    UINT32                                             DimmAddrMap1:4 ; ///<
+    UINT32                                             DimmAddrMap2:4 ; ///<
+    UINT32                                             DimmAddrMap3:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x80_dct1_STRUCT;
+
+// **** D18F2x80_dct0 Register Definition ****
+// Address
+#define D18F2x80_dct0_ADDRESS                                   0x80
+
+// Type
+#define D18F2x80_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x80_dct0_DimmAddrMap0_OFFSET                       0
+#define D18F2x80_dct0_DimmAddrMap0_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap0_MASK                         0xf
+#define D18F2x80_dct0_DimmAddrMap1_OFFSET                       4
+#define D18F2x80_dct0_DimmAddrMap1_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap1_MASK                         0xf0
+#define D18F2x80_dct0_DimmAddrMap2_OFFSET                       8
+#define D18F2x80_dct0_DimmAddrMap2_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap2_MASK                         0xf00
+#define D18F2x80_dct0_DimmAddrMap3_OFFSET                       12
+#define D18F2x80_dct0_DimmAddrMap3_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap3_MASK                         0xf000
+#define D18F2x80_dct0_Reserved_31_16_OFFSET                     16
+#define D18F2x80_dct0_Reserved_31_16_WIDTH                      16
+#define D18F2x80_dct0_Reserved_31_16_MASK                       0xffff0000
+
+/// D18F2x80_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DimmAddrMap0:4 ; ///<
+    UINT32                                             DimmAddrMap1:4 ; ///<
+    UINT32                                             DimmAddrMap2:4 ; ///<
+    UINT32                                             DimmAddrMap3:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x80_dct0_STRUCT;
+
+// **** D18F2x84_dct1 Register Definition ****
+// Address
+#define D18F2x84_dct1_ADDRESS                                   0x84
+
+// Type
+#define D18F2x84_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x84_dct1_BurstCtrl_OFFSET                          0
+#define D18F2x84_dct1_BurstCtrl_WIDTH                           2
+#define D18F2x84_dct1_BurstCtrl_MASK                            0x3
+#define D18F2x84_dct1_Reserved_22_2_OFFSET                      2
+#define D18F2x84_dct1_Reserved_22_2_WIDTH                       21
+#define D18F2x84_dct1_Reserved_22_2_MASK                        0x7ffffc
+#define D18F2x84_dct1_PchgPDModeSel_OFFSET                      23
+#define D18F2x84_dct1_PchgPDModeSel_WIDTH                       1
+#define D18F2x84_dct1_PchgPDModeSel_MASK                        0x800000
+#define D18F2x84_dct1_Reserved_31_24_OFFSET                     24
+#define D18F2x84_dct1_Reserved_31_24_WIDTH                      8
+#define D18F2x84_dct1_Reserved_31_24_MASK                       0xff000000
+
+/// D18F2x84_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                BurstCtrl:2 ; ///<
+    UINT32                                            Reserved_22_2:21; ///<
+    UINT32                                            PchgPDModeSel:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x84_dct1_STRUCT;
+
+// **** D18F2x84_dct0 Register Definition ****
+// Address
+#define D18F2x84_dct0_ADDRESS                                   0x84
+
+// Type
+#define D18F2x84_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x84_dct0_BurstCtrl_OFFSET                          0
+#define D18F2x84_dct0_BurstCtrl_WIDTH                           2
+#define D18F2x84_dct0_BurstCtrl_MASK                            0x3
+#define D18F2x84_dct0_Reserved_22_2_OFFSET                      2
+#define D18F2x84_dct0_Reserved_22_2_WIDTH                       21
+#define D18F2x84_dct0_Reserved_22_2_MASK                        0x7ffffc
+#define D18F2x84_dct0_PchgPDModeSel_OFFSET                      23
+#define D18F2x84_dct0_PchgPDModeSel_WIDTH                       1
+#define D18F2x84_dct0_PchgPDModeSel_MASK                        0x800000
+#define D18F2x84_dct0_Reserved_31_24_OFFSET                     24
+#define D18F2x84_dct0_Reserved_31_24_WIDTH                      8
+#define D18F2x84_dct0_Reserved_31_24_MASK                       0xff000000
+
+/// D18F2x84_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                BurstCtrl:2 ; ///<
+    UINT32                                            Reserved_22_2:21; ///<
+    UINT32                                            PchgPDModeSel:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x84_dct0_STRUCT;
+
+// **** D18F2x88_dct1 Register Definition ****
+// Address
+#define D18F2x88_dct1_ADDRESS                                   0x88
+
+// Type
+#define D18F2x88_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x88_dct1_Reserved_23_0_OFFSET                      0
+#define D18F2x88_dct1_Reserved_23_0_WIDTH                       24
+#define D18F2x88_dct1_Reserved_23_0_MASK                        0xffffff
+#define D18F2x88_dct1_MemClkDis_OFFSET                          24
+#define D18F2x88_dct1_MemClkDis_WIDTH                           6
+#define D18F2x88_dct1_MemClkDis_MASK                            0x3f000000
+#define D18F2x88_dct1_Reserved_31_30_OFFSET                     30
+#define D18F2x88_dct1_Reserved_31_30_WIDTH                      2
+#define D18F2x88_dct1_Reserved_31_30_MASK                       0xc0000000
+
+/// D18F2x88_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                MemClkDis:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x88_dct1_STRUCT;
+
+// **** D18F2x88_dct0 Register Definition ****
+// Address
+#define D18F2x88_dct0_ADDRESS                                   0x88
+
+// Type
+#define D18F2x88_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x88_dct0_Reserved_23_0_OFFSET                      0
+#define D18F2x88_dct0_Reserved_23_0_WIDTH                       24
+#define D18F2x88_dct0_Reserved_23_0_MASK                        0xffffff
+#define D18F2x88_dct0_MemClkDis_OFFSET                          24
+#define D18F2x88_dct0_MemClkDis_WIDTH                           6
+#define D18F2x88_dct0_MemClkDis_MASK                            0x3f000000
+#define D18F2x88_dct0_Reserved_31_30_OFFSET                     30
+#define D18F2x88_dct0_Reserved_31_30_WIDTH                      2
+#define D18F2x88_dct0_Reserved_31_30_MASK                       0xc0000000
+
+/// D18F2x88_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                MemClkDis:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x88_dct0_STRUCT;
+
+// **** D18F2x8C_dct1 Register Definition ****
+// Address
+#define D18F2x8C_dct1_ADDRESS                                   0x8c
+
+// Type
+#define D18F2x8C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x8C_dct1_Reserved_15_0_OFFSET                      0
+#define D18F2x8C_dct1_Reserved_15_0_WIDTH                       16
+#define D18F2x8C_dct1_Reserved_15_0_MASK                        0xffff
+#define D18F2x8C_dct1_Tref_OFFSET                               16
+#define D18F2x8C_dct1_Tref_WIDTH                                2
+#define D18F2x8C_dct1_Tref_MASK                                 0x30000
+#define D18F2x8C_dct1_DisAutoRefresh_OFFSET                     18
+#define D18F2x8C_dct1_DisAutoRefresh_WIDTH                      1
+#define D18F2x8C_dct1_DisAutoRefresh_MASK                       0x40000
+#define D18F2x8C_dct1_Reserved_31_19_OFFSET                     19
+#define D18F2x8C_dct1_Reserved_31_19_WIDTH                      13
+#define D18F2x8C_dct1_Reserved_31_19_MASK                       0xfff80000
+
+/// D18F2x8C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                                     Tref:2 ; ///<
+    UINT32                                           DisAutoRefresh:1 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x8C_dct1_STRUCT;
+
+// **** D18F2x8C_dct0 Register Definition ****
+// Address
+#define D18F2x8C_dct0_ADDRESS                                   0x8c
+
+// Type
+#define D18F2x8C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x8C_dct0_Reserved_15_0_OFFSET                      0
+#define D18F2x8C_dct0_Reserved_15_0_WIDTH                       16
+#define D18F2x8C_dct0_Reserved_15_0_MASK                        0xffff
+#define D18F2x8C_dct0_Tref_OFFSET                               16
+#define D18F2x8C_dct0_Tref_WIDTH                                2
+#define D18F2x8C_dct0_Tref_MASK                                 0x30000
+#define D18F2x8C_dct0_DisAutoRefresh_OFFSET                     18
+#define D18F2x8C_dct0_DisAutoRefresh_WIDTH                      1
+#define D18F2x8C_dct0_DisAutoRefresh_MASK                       0x40000
+#define D18F2x8C_dct0_Reserved_31_19_OFFSET                     19
+#define D18F2x8C_dct0_Reserved_31_19_WIDTH                      13
+#define D18F2x8C_dct0_Reserved_31_19_MASK                       0xfff80000
+
+/// D18F2x8C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                                     Tref:2 ; ///<
+    UINT32                                           DisAutoRefresh:1 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x8C_dct0_STRUCT;
+
+// **** D18F2x90_dct0 Register Definition ****
+// Address
+#define D18F2x90_dct0_ADDRESS                                   0x90
+
+// Type
+#define D18F2x90_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x90_dct0_Reserved_0_0_OFFSET                       0
+#define D18F2x90_dct0_Reserved_0_0_WIDTH                        1
+#define D18F2x90_dct0_Reserved_0_0_MASK                         0x1
+#define D18F2x90_dct0_ExitSelfRef_OFFSET                        1
+#define D18F2x90_dct0_ExitSelfRef_WIDTH                         1
+#define D18F2x90_dct0_ExitSelfRef_MASK                          0x2
+#define D18F2x90_dct0_Reserved_7_2_OFFSET                       2
+#define D18F2x90_dct0_Reserved_7_2_WIDTH                        6
+#define D18F2x90_dct0_Reserved_7_2_MASK                         0xfc
+#define D18F2x90_dct0_Reserved_8_8_OFFSET                       8
+#define D18F2x90_dct0_Reserved_8_8_WIDTH                        1
+#define D18F2x90_dct0_Reserved_8_8_MASK                         0x100
+#define D18F2x90_dct0_Reserved_11_9_OFFSET                      9
+#define D18F2x90_dct0_Reserved_11_9_WIDTH                       3
+#define D18F2x90_dct0_Reserved_11_9_MASK                        0xe00
+#define D18F2x90_dct0_Reserved_15_12_OFFSET                     12
+#define D18F2x90_dct0_Reserved_15_12_WIDTH                      4
+#define D18F2x90_dct0_Reserved_15_12_MASK                       0xf000
+#define D18F2x90_dct0_UnbuffDimm_OFFSET                         16
+#define D18F2x90_dct0_UnbuffDimm_WIDTH                          1
+#define D18F2x90_dct0_UnbuffDimm_MASK                           0x10000
+#define D18F2x90_dct0_EnterSelfRef_OFFSET                       17
+#define D18F2x90_dct0_EnterSelfRef_WIDTH                        1
+#define D18F2x90_dct0_EnterSelfRef_MASK                         0x20000
+#define D18F2x90_dct0_PendRefPayback_OFFSET                     18
+#define D18F2x90_dct0_PendRefPayback_WIDTH                      1
+#define D18F2x90_dct0_PendRefPayback_MASK                       0x40000
+#define D18F2x90_dct0_Reserved_19_19_OFFSET                     19
+#define D18F2x90_dct0_Reserved_19_19_WIDTH                      1
+#define D18F2x90_dct0_Reserved_19_19_MASK                       0x80000
+#define D18F2x90_dct0_DynPageCloseEn_OFFSET                     20
+#define D18F2x90_dct0_DynPageCloseEn_WIDTH                      1
+#define D18F2x90_dct0_DynPageCloseEn_MASK                       0x100000
+#define D18F2x90_dct0_IdleCycLowLimit_OFFSET                    21
+#define D18F2x90_dct0_IdleCycLowLimit_WIDTH                     2
+#define D18F2x90_dct0_IdleCycLowLimit_MASK                      0x600000
+#define D18F2x90_dct0_ForceAutoPchg_OFFSET                      23
+#define D18F2x90_dct0_ForceAutoPchg_WIDTH                       1
+#define D18F2x90_dct0_ForceAutoPchg_MASK                        0x800000
+#define D18F2x90_dct0_StagRefEn_OFFSET                          24
+#define D18F2x90_dct0_StagRefEn_WIDTH                           1
+#define D18F2x90_dct0_StagRefEn_MASK                            0x1000000
+#define D18F2x90_dct0_PendRefPaybackS3En_OFFSET                 25
+#define D18F2x90_dct0_PendRefPaybackS3En_WIDTH                  1
+#define D18F2x90_dct0_PendRefPaybackS3En_MASK                   0x2000000
+#define D18F2x90_dct0_Reserved_26_26_OFFSET                     26
+#define D18F2x90_dct0_Reserved_26_26_WIDTH                      1
+#define D18F2x90_dct0_Reserved_26_26_MASK                       0x4000000
+#define D18F2x90_dct0_DisDllShutdownSR_OFFSET                   27
+#define D18F2x90_dct0_DisDllShutdownSR_WIDTH                    1
+#define D18F2x90_dct0_DisDllShutdownSR_MASK                     0x8000000
+#define D18F2x90_dct0_Reserved_31_28_OFFSET                     28
+#define D18F2x90_dct0_Reserved_31_28_WIDTH                      4
+#define D18F2x90_dct0_Reserved_31_28_MASK                       0xf0000000
+
+/// D18F2x90_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                              ExitSelfRef:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                            Reserved_11_9:3 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                               UnbuffDimm:1 ; ///<
+    UINT32                                             EnterSelfRef:1 ; ///<
+    UINT32                                           PendRefPayback:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                           DynPageCloseEn:1 ; ///<
+    UINT32                                          IdleCycLowLimit:2 ; ///<
+    UINT32                                            ForceAutoPchg:1 ; ///<
+    UINT32                                                StagRefEn:1 ; ///<
+    UINT32                                       PendRefPaybackS3En:1 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                         DisDllShutdownSR:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x90_dct0_STRUCT;
+
+// **** D18F2x90_dct1 Register Definition ****
+// Address
+#define D18F2x90_dct1_ADDRESS                                   0x90
+
+// Type
+#define D18F2x90_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x90_dct1_Reserved_0_0_OFFSET                       0
+#define D18F2x90_dct1_Reserved_0_0_WIDTH                        1
+#define D18F2x90_dct1_Reserved_0_0_MASK                         0x1
+#define D18F2x90_dct1_ExitSelfRef_OFFSET                        1
+#define D18F2x90_dct1_ExitSelfRef_WIDTH                         1
+#define D18F2x90_dct1_ExitSelfRef_MASK                          0x2
+#define D18F2x90_dct1_Reserved_7_2_OFFSET                       2
+#define D18F2x90_dct1_Reserved_7_2_WIDTH                        6
+#define D18F2x90_dct1_Reserved_7_2_MASK                         0xfc
+#define D18F2x90_dct1_Reserved_8_8_OFFSET                       8
+#define D18F2x90_dct1_Reserved_8_8_WIDTH                        1
+#define D18F2x90_dct1_Reserved_8_8_MASK                         0x100
+#define D18F2x90_dct1_Reserved_11_9_OFFSET                      9
+#define D18F2x90_dct1_Reserved_11_9_WIDTH                       3
+#define D18F2x90_dct1_Reserved_11_9_MASK                        0xe00
+#define D18F2x90_dct1_Reserved_15_12_OFFSET                     12
+#define D18F2x90_dct1_Reserved_15_12_WIDTH                      4
+#define D18F2x90_dct1_Reserved_15_12_MASK                       0xf000
+#define D18F2x90_dct1_UnbuffDimm_OFFSET                         16
+#define D18F2x90_dct1_UnbuffDimm_WIDTH                          1
+#define D18F2x90_dct1_UnbuffDimm_MASK                           0x10000
+#define D18F2x90_dct1_EnterSelfRef_OFFSET                       17
+#define D18F2x90_dct1_EnterSelfRef_WIDTH                        1
+#define D18F2x90_dct1_EnterSelfRef_MASK                         0x20000
+#define D18F2x90_dct1_PendRefPayback_OFFSET                     18
+#define D18F2x90_dct1_PendRefPayback_WIDTH                      1
+#define D18F2x90_dct1_PendRefPayback_MASK                       0x40000
+#define D18F2x90_dct1_Reserved_19_19_OFFSET                     19
+#define D18F2x90_dct1_Reserved_19_19_WIDTH                      1
+#define D18F2x90_dct1_Reserved_19_19_MASK                       0x80000
+#define D18F2x90_dct1_DynPageCloseEn_OFFSET                     20
+#define D18F2x90_dct1_DynPageCloseEn_WIDTH                      1
+#define D18F2x90_dct1_DynPageCloseEn_MASK                       0x100000
+#define D18F2x90_dct1_IdleCycLowLimit_OFFSET                    21
+#define D18F2x90_dct1_IdleCycLowLimit_WIDTH                     2
+#define D18F2x90_dct1_IdleCycLowLimit_MASK                      0x600000
+#define D18F2x90_dct1_ForceAutoPchg_OFFSET                      23
+#define D18F2x90_dct1_ForceAutoPchg_WIDTH                       1
+#define D18F2x90_dct1_ForceAutoPchg_MASK                        0x800000
+#define D18F2x90_dct1_StagRefEn_OFFSET                          24
+#define D18F2x90_dct1_StagRefEn_WIDTH                           1
+#define D18F2x90_dct1_StagRefEn_MASK                            0x1000000
+#define D18F2x90_dct1_PendRefPaybackS3En_OFFSET                 25
+#define D18F2x90_dct1_PendRefPaybackS3En_WIDTH                  1
+#define D18F2x90_dct1_PendRefPaybackS3En_MASK                   0x2000000
+#define D18F2x90_dct1_Reserved_26_26_OFFSET                     26
+#define D18F2x90_dct1_Reserved_26_26_WIDTH                      1
+#define D18F2x90_dct1_Reserved_26_26_MASK                       0x4000000
+#define D18F2x90_dct1_DisDllShutdownSR_OFFSET                   27
+#define D18F2x90_dct1_DisDllShutdownSR_WIDTH                    1
+#define D18F2x90_dct1_DisDllShutdownSR_MASK                     0x8000000
+#define D18F2x90_dct1_Reserved_31_28_OFFSET                     28
+#define D18F2x90_dct1_Reserved_31_28_WIDTH                      4
+#define D18F2x90_dct1_Reserved_31_28_MASK                       0xf0000000
+
+/// D18F2x90_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                              ExitSelfRef:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                            Reserved_11_9:3 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                               UnbuffDimm:1 ; ///<
+    UINT32                                             EnterSelfRef:1 ; ///<
+    UINT32                                           PendRefPayback:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                           DynPageCloseEn:1 ; ///<
+    UINT32                                          IdleCycLowLimit:2 ; ///<
+    UINT32                                            ForceAutoPchg:1 ; ///<
+    UINT32                                                StagRefEn:1 ; ///<
+    UINT32                                       PendRefPaybackS3En:1 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                         DisDllShutdownSR:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x90_dct1_STRUCT;
+
+// **** D18F2x94_dct1 Register Definition ****
+// Address
+#define D18F2x94_dct1_ADDRESS                                   0x94
+
+// Type
+#define D18F2x94_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x94_dct1_MemClkFreq_OFFSET                         0
+#define D18F2x94_dct1_MemClkFreq_WIDTH                          5
+#define D18F2x94_dct1_MemClkFreq_MASK                           0x1f
+#define D18F2x94_dct1_Reserved_6_5_OFFSET                       5
+#define D18F2x94_dct1_Reserved_6_5_WIDTH                        2
+#define D18F2x94_dct1_Reserved_6_5_MASK                         0x60
+#define D18F2x94_dct1_MemClkFreqVal_OFFSET                      7
+#define D18F2x94_dct1_MemClkFreqVal_WIDTH                       1
+#define D18F2x94_dct1_MemClkFreqVal_MASK                        0x80
+#define D18F2x94_dct1_Reserved_9_8_OFFSET                       8
+#define D18F2x94_dct1_Reserved_9_8_WIDTH                        2
+#define D18F2x94_dct1_Reserved_9_8_MASK                         0x300
+#define D18F2x94_dct1_ZqcsInterval_OFFSET                       10
+#define D18F2x94_dct1_ZqcsInterval_WIDTH                        2
+#define D18F2x94_dct1_ZqcsInterval_MASK                         0xc00
+#define D18F2x94_dct1_Reserved_12_12_OFFSET                     12
+#define D18F2x94_dct1_Reserved_12_12_WIDTH                      1
+#define D18F2x94_dct1_Reserved_12_12_MASK                       0x1000
+#define D18F2x94_dct1_Reserved_13_13_OFFSET                     13
+#define D18F2x94_dct1_Reserved_13_13_WIDTH                      1
+#define D18F2x94_dct1_Reserved_13_13_MASK                       0x2000
+#define D18F2x94_dct1_DisDramInterface_OFFSET                   14
+#define D18F2x94_dct1_DisDramInterface_WIDTH                    1
+#define D18F2x94_dct1_DisDramInterface_MASK                     0x4000
+#define D18F2x94_dct1_PowerDownEn_OFFSET                        15
+#define D18F2x94_dct1_PowerDownEn_WIDTH                         1
+#define D18F2x94_dct1_PowerDownEn_MASK                          0x8000
+#define D18F2x94_dct1_PowerDownMode_OFFSET                      16
+#define D18F2x94_dct1_PowerDownMode_WIDTH                       1
+#define D18F2x94_dct1_PowerDownMode_MASK                        0x10000
+#define D18F2x94_dct1_Reserved_18_17_OFFSET                     17
+#define D18F2x94_dct1_Reserved_18_17_WIDTH                      2
+#define D18F2x94_dct1_Reserved_18_17_MASK                       0x60000
+#define D18F2x94_dct1_SlowAccessMode_OFFSET                     20
+#define D18F2x94_dct1_SlowAccessMode_WIDTH                      1
+#define D18F2x94_dct1_SlowAccessMode_MASK                       0x100000
+#define D18F2x94_dct1_FreqChgInProg_OFFSET                      21
+#define D18F2x94_dct1_FreqChgInProg_WIDTH                       1
+#define D18F2x94_dct1_FreqChgInProg_MASK                        0x200000
+#define D18F2x94_dct1_BankSwizzleMode_OFFSET                    22
+#define D18F2x94_dct1_BankSwizzleMode_WIDTH                     1
+#define D18F2x94_dct1_BankSwizzleMode_MASK                      0x400000
+#define D18F2x94_dct1_ProcOdtDis_OFFSET                         23
+#define D18F2x94_dct1_ProcOdtDis_WIDTH                          1
+#define D18F2x94_dct1_ProcOdtDis_MASK                           0x800000
+#define D18F2x94_dct1_DcqBypassMax_OFFSET                       24
+#define D18F2x94_dct1_DcqBypassMax_WIDTH                        5
+#define D18F2x94_dct1_DcqBypassMax_MASK                         0x1f000000
+#define D18F2x94_dct1_Reserved_30_29_OFFSET                     29
+#define D18F2x94_dct1_Reserved_30_29_WIDTH                      2
+#define D18F2x94_dct1_Reserved_30_29_MASK                       0x60000000
+#define D18F2x94_dct1_DphyMemPsSelEn_OFFSET                     31
+#define D18F2x94_dct1_DphyMemPsSelEn_WIDTH                      1
+#define D18F2x94_dct1_DphyMemPsSelEn_MASK                       0x80000000
+
+/// D18F2x94_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               MemClkFreq:5 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                            MemClkFreqVal:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                             ZqcsInterval:2 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                         DisDramInterface:1 ; ///<
+    UINT32                                              PowerDownEn:1 ; ///<
+    UINT32                                            PowerDownMode:1 ; ///<
+    UINT32                                           Reserved_18_17:2 ; ///<
+    UINT32                                           DcqArbBypassEn:1 ; ///<
+    UINT32                                           SlowAccessMode:1 ; ///<
+    UINT32                                            FreqChgInProg:1 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                               ProcOdtDis:1 ; ///<
+    UINT32                                             DcqBypassMax:5 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                           DphyMemPsSelEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x94_dct1_STRUCT;
+
+// **** D18F2x94_dct0 Register Definition ****
+// Address
+#define D18F2x94_dct0_ADDRESS                                   0x94
+
+// Type
+#define D18F2x94_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x94_dct0_MemClkFreq_OFFSET                         0
+#define D18F2x94_dct0_MemClkFreq_WIDTH                          5
+#define D18F2x94_dct0_MemClkFreq_MASK                           0x1f
+#define D18F2x94_dct0_Reserved_6_5_OFFSET                       5
+#define D18F2x94_dct0_Reserved_6_5_WIDTH                        2
+#define D18F2x94_dct0_Reserved_6_5_MASK                         0x60
+#define D18F2x94_dct0_MemClkFreqVal_OFFSET                      7
+#define D18F2x94_dct0_MemClkFreqVal_WIDTH                       1
+#define D18F2x94_dct0_MemClkFreqVal_MASK                        0x80
+#define D18F2x94_dct0_Reserved_9_8_OFFSET                       8
+#define D18F2x94_dct0_Reserved_9_8_WIDTH                        2
+#define D18F2x94_dct0_Reserved_9_8_MASK                         0x300
+#define D18F2x94_dct0_ZqcsInterval_OFFSET                       10
+#define D18F2x94_dct0_ZqcsInterval_WIDTH                        2
+#define D18F2x94_dct0_ZqcsInterval_MASK                         0xc00
+#define D18F2x94_dct0_Reserved_12_12_OFFSET                     12
+#define D18F2x94_dct0_Reserved_12_12_WIDTH                      1
+#define D18F2x94_dct0_Reserved_12_12_MASK                       0x1000
+#define D18F2x94_dct0_Reserved_13_13_OFFSET                     13
+#define D18F2x94_dct0_Reserved_13_13_WIDTH                      1
+#define D18F2x94_dct0_Reserved_13_13_MASK                       0x2000
+#define D18F2x94_dct0_DisDramInterface_OFFSET                   14
+#define D18F2x94_dct0_DisDramInterface_WIDTH                    1
+#define D18F2x94_dct0_DisDramInterface_MASK                     0x4000
+#define D18F2x94_dct0_PowerDownEn_OFFSET                        15
+#define D18F2x94_dct0_PowerDownEn_WIDTH                         1
+#define D18F2x94_dct0_PowerDownEn_MASK                          0x8000
+#define D18F2x94_dct0_PowerDownMode_OFFSET                      16
+#define D18F2x94_dct0_PowerDownMode_WIDTH                       1
+#define D18F2x94_dct0_PowerDownMode_MASK                        0x10000
+#define D18F2x94_dct0_Reserved_18_17_OFFSET                     17
+#define D18F2x94_dct0_Reserved_18_17_WIDTH                      2
+#define D18F2x94_dct0_Reserved_18_17_MASK                       0x60000
+#define D18F2x94_dct0_SlowAccessMode_OFFSET                     20
+#define D18F2x94_dct0_SlowAccessMode_WIDTH                      1
+#define D18F2x94_dct0_SlowAccessMode_MASK                       0x100000
+#define D18F2x94_dct0_FreqChgInProg_OFFSET                      21
+#define D18F2x94_dct0_FreqChgInProg_WIDTH                       1
+#define D18F2x94_dct0_FreqChgInProg_MASK                        0x200000
+#define D18F2x94_dct0_BankSwizzleMode_OFFSET                    22
+#define D18F2x94_dct0_BankSwizzleMode_WIDTH                     1
+#define D18F2x94_dct0_BankSwizzleMode_MASK                      0x400000
+#define D18F2x94_dct0_ProcOdtDis_OFFSET                         23
+#define D18F2x94_dct0_ProcOdtDis_WIDTH                          1
+#define D18F2x94_dct0_ProcOdtDis_MASK                           0x800000
+#define D18F2x94_dct0_DcqBypassMax_OFFSET                       24
+#define D18F2x94_dct0_DcqBypassMax_WIDTH                        5
+#define D18F2x94_dct0_DcqBypassMax_MASK                         0x1f000000
+#define D18F2x94_dct0_Reserved_30_29_OFFSET                     29
+#define D18F2x94_dct0_Reserved_30_29_WIDTH                      2
+#define D18F2x94_dct0_Reserved_30_29_MASK                       0x60000000
+#define D18F2x94_dct0_DphyMemPsSelEn_OFFSET                     31
+#define D18F2x94_dct0_DphyMemPsSelEn_WIDTH                      1
+#define D18F2x94_dct0_DphyMemPsSelEn_MASK                       0x80000000
+
+/// D18F2x94_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               MemClkFreq:5 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                            MemClkFreqVal:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                             ZqcsInterval:2 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                         DisDramInterface:1 ; ///<
+    UINT32                                              PowerDownEn:1 ; ///<
+    UINT32                                            PowerDownMode:1 ; ///<
+    UINT32                                           Reserved_18_17:2 ; ///<
+    UINT32                                           DcqArbBypassEn:1 ; ///<
+    UINT32                                           SlowAccessMode:1 ; ///<
+    UINT32                                            FreqChgInProg:1 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                               ProcOdtDis:1 ; ///<
+    UINT32                                             DcqBypassMax:5 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                           DphyMemPsSelEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x94_dct0_STRUCT;
+
+// **** D18F2x98_dct0 Register Definition ****
+// Address
+#define D18F2x98_dct0_ADDRESS                                   0x98
+
+// Type
+#define D18F2x98_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x98_dct0_DctOffset_OFFSET                          0
+#define D18F2x98_dct0_DctOffset_WIDTH                           30
+#define D18F2x98_dct0_DctOffset_MASK                            0x3fffffff
+#define D18F2x98_dct0_DctAccessWrite_OFFSET                     30
+#define D18F2x98_dct0_DctAccessWrite_WIDTH                      1
+#define D18F2x98_dct0_DctAccessWrite_MASK                       0x40000000
+#define D18F2x98_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x98_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x98_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x98_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctOffset:30; ///<
+    UINT32                                           DctAccessWrite:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x98_dct0_STRUCT;
+
+// **** D18F2x98_dct1 Register Definition ****
+// Address
+#define D18F2x98_dct1_ADDRESS                                   0x98
+
+// Type
+#define D18F2x98_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x98_dct1_DctOffset_OFFSET                          0
+#define D18F2x98_dct1_DctOffset_WIDTH                           30
+#define D18F2x98_dct1_DctOffset_MASK                            0x3fffffff
+#define D18F2x98_dct1_DctAccessWrite_OFFSET                     30
+#define D18F2x98_dct1_DctAccessWrite_WIDTH                      1
+#define D18F2x98_dct1_DctAccessWrite_MASK                       0x40000000
+#define D18F2x98_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x98_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x98_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x98_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctOffset:30; ///<
+    UINT32                                           DctAccessWrite:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x98_dct1_STRUCT;
+
+// **** D18F2x9C_dct1 Register Definition ****
+// Address
+#define D18F2x9C_dct1_ADDRESS                                   0x9c
+
+// Type
+#define D18F2x9C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x9C_dct1_Data_OFFSET                               0
+#define D18F2x9C_dct1_Data_WIDTH                                32
+#define D18F2x9C_dct1_Data_MASK                                 0xffffffff
+
+/// D18F2x9C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_dct1_STRUCT;
+
+// **** D18F2x9C_dct0 Register Definition ****
+// Address
+#define D18F2x9C_dct0_ADDRESS                                   0x9c
+
+// Type
+#define D18F2x9C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x9C_dct0_Data_OFFSET                               0
+#define D18F2x9C_dct0_Data_WIDTH                                32
+#define D18F2x9C_dct0_Data_MASK                                 0xffffffff
+
+/// D18F2x9C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_dct0_STRUCT;
+
+// **** D18F2xA4 Register Definition ****
+// Address
+#define D18F2xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F2xA4_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xA4_Reserved_7_0_OFFSET                            0
+#define D18F2xA4_Reserved_7_0_WIDTH                             8
+#define D18F2xA4_Reserved_7_0_MASK                              0xff
+#define D18F2xA4_ODTSEn_OFFSET                                  8
+#define D18F2xA4_ODTSEn_WIDTH                                   1
+#define D18F2xA4_ODTSEn_MASK                                    0x100
+#define D18F2xA4_Reserved_10_9_OFFSET                           9
+#define D18F2xA4_Reserved_10_9_WIDTH                            2
+#define D18F2xA4_Reserved_10_9_MASK                             0x600
+#define D18F2xA4_BwCapEn_OFFSET                                 11
+#define D18F2xA4_BwCapEn_WIDTH                                  1
+#define D18F2xA4_BwCapEn_MASK                                   0x800
+#define D18F2xA4_CmdThrottleMode_OFFSET                         12
+#define D18F2xA4_CmdThrottleMode_WIDTH                          3
+#define D18F2xA4_CmdThrottleMode_MASK                           0x7000
+#define D18F2xA4_Reserved_19_15_OFFSET                          15
+#define D18F2xA4_Reserved_19_15_WIDTH                           5
+#define D18F2xA4_Reserved_19_15_MASK                            0xf8000
+#define D18F2xA4_BwCapCmdThrottleMode_OFFSET                    20
+#define D18F2xA4_BwCapCmdThrottleMode_WIDTH                     4
+#define D18F2xA4_BwCapCmdThrottleMode_MASK                      0xf00000
+#define D18F2xA4_Reserved_31_24_OFFSET                          24
+#define D18F2xA4_Reserved_31_24_WIDTH                           8
+#define D18F2xA4_Reserved_31_24_MASK                            0xff000000
+
+/// D18F2xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   ODTSEn:1 ; ///<
+    UINT32                                            Reserved_10_9:2 ; ///<
+    UINT32                                                  BwCapEn:1 ; ///<
+    UINT32                                          CmdThrottleMode:3 ; ///<
+    UINT32                                           Reserved_19_15:5 ; ///<
+    UINT32                                     BwCapCmdThrottleMode:4 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xA4_STRUCT;
+
+// **** D18F2xA8_dct0 Register Definition ****
+// Address
+#define D18F2xA8_dct0_ADDRESS                                   0xa8
+
+// Type
+#define D18F2xA8_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2xA8_dct0_Reserved_1_0_OFFSET                       0
+#define D18F2xA8_dct0_Reserved_1_0_WIDTH                        2
+#define D18F2xA8_dct0_Reserved_1_0_MASK                         0x3
+#define D18F2xA8_dct0_CSTimingMux67_OFFSET                      2
+#define D18F2xA8_dct0_CSTimingMux67_WIDTH                       1
+#define D18F2xA8_dct0_CSTimingMux67_MASK                        0x4
+#define D18F2xA8_dct0_Reserved_3_3_OFFSET                       3
+#define D18F2xA8_dct0_Reserved_3_3_WIDTH                        1
+#define D18F2xA8_dct0_Reserved_3_3_MASK                         0x8
+#define D18F2xA8_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2xA8_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2xA8_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2xA8_dct0_SubMemclkRegDly_OFFSET                    5
+#define D18F2xA8_dct0_SubMemclkRegDly_WIDTH                     1
+#define D18F2xA8_dct0_SubMemclkRegDly_MASK                      0x20
+#define D18F2xA8_dct0_Reserved_7_6_OFFSET                       6
+#define D18F2xA8_dct0_Reserved_7_6_WIDTH                        2
+#define D18F2xA8_dct0_Reserved_7_6_MASK                         0xc0
+#define D18F2xA8_dct0_CtrlWordCS_7_0__OFFSET                    8
+#define D18F2xA8_dct0_CtrlWordCS_7_0__WIDTH                     8
+#define D18F2xA8_dct0_CtrlWordCS_7_0__MASK                      0xff00
+#define D18F2xA8_dct0_MemPhyPllPdMode_OFFSET                    16
+#define D18F2xA8_dct0_MemPhyPllPdMode_WIDTH                     2
+#define D18F2xA8_dct0_MemPhyPllPdMode_MASK                      0x30000
+#define D18F2xA8_dct0_Reserved_19_18_OFFSET                     18
+#define D18F2xA8_dct0_Reserved_19_18_WIDTH                      2
+#define D18F2xA8_dct0_Reserved_19_18_MASK                       0xc0000
+#define D18F2xA8_dct0_BankSwap_OFFSET                           20
+#define D18F2xA8_dct0_BankSwap_WIDTH                            1
+#define D18F2xA8_dct0_BankSwap_MASK                             0x100000
+#define D18F2xA8_dct0_AggrPDEn_OFFSET                           21
+#define D18F2xA8_dct0_AggrPDEn_WIDTH                            1
+#define D18F2xA8_dct0_AggrPDEn_MASK                             0x200000
+#define D18F2xA8_dct0_PrtlChPDEnhEn_OFFSET                      22
+#define D18F2xA8_dct0_PrtlChPDEnhEn_WIDTH                       1
+#define D18F2xA8_dct0_PrtlChPDEnhEn_MASK                        0x400000
+#define D18F2xA8_dct0_Reserved_23_23_OFFSET                     23
+#define D18F2xA8_dct0_Reserved_23_23_WIDTH                      1
+#define D18F2xA8_dct0_Reserved_23_23_MASK                       0x800000
+#define D18F2xA8_dct0_Reserved_25_24_OFFSET                     24
+#define D18F2xA8_dct0_Reserved_25_24_WIDTH                      2
+#define D18F2xA8_dct0_Reserved_25_24_MASK                       0x3000000
+#define D18F2xA8_dct0_CsMux45_OFFSET                            26
+#define D18F2xA8_dct0_CsMux45_WIDTH                             1
+#define D18F2xA8_dct0_CsMux45_MASK                              0x4000000
+#define D18F2xA8_dct0_CsMux67_OFFSET                            27
+#define D18F2xA8_dct0_CsMux67_WIDTH                             1
+#define D18F2xA8_dct0_CsMux67_MASK                              0x8000000
+#define D18F2xA8_dct0_FastSelfRefEntryDis_OFFSET                28
+#define D18F2xA8_dct0_FastSelfRefEntryDis_WIDTH                 1
+#define D18F2xA8_dct0_FastSelfRefEntryDis_MASK                  0x10000000
+#define D18F2xA8_dct0_RefChCmdMgtDis_OFFSET                     29
+#define D18F2xA8_dct0_RefChCmdMgtDis_WIDTH                      1
+#define D18F2xA8_dct0_RefChCmdMgtDis_MASK                       0x20000000
+#define D18F2xA8_dct0_Reserved_30_30_OFFSET                     30
+#define D18F2xA8_dct0_Reserved_30_30_WIDTH                      1
+#define D18F2xA8_dct0_Reserved_30_30_MASK                       0x40000000
+#define D18F2xA8_dct0_PerRankTimingEn_OFFSET                    31
+#define D18F2xA8_dct0_PerRankTimingEn_WIDTH                     1
+#define D18F2xA8_dct0_PerRankTimingEn_MASK                      0x80000000
+
+/// D18F2xA8_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CSTimingMux67:1 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          SubMemclkRegDly:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                          CtrlWordCS_7_0_:8 ; ///<
+    UINT32                                          MemPhyPllPdMode:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                                 AggrPDEn:1 ; ///<
+    UINT32                                            PrtlChPDEnhEn:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                  CsMux45:1 ; ///<
+    UINT32                                                  CsMux67:1 ; ///<
+    UINT32                                      FastSelfRefEntryDis:1 ; ///<
+    UINT32                                           RefChCmdMgtDis:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                          PerRankTimingEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xA8_dct0_STRUCT;
+
+// **** D18F2xA8_dct1 Register Definition ****
+// Address
+#define D18F2xA8_dct1_ADDRESS                                   0xa8
+
+// Type
+#define D18F2xA8_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2xA8_dct1_Reserved_1_0_OFFSET                       0
+#define D18F2xA8_dct1_Reserved_1_0_WIDTH                        2
+#define D18F2xA8_dct1_Reserved_1_0_MASK                         0x3
+#define D18F2xA8_dct1_CSTimingMux67_OFFSET                      2
+#define D18F2xA8_dct1_CSTimingMux67_WIDTH                       1
+#define D18F2xA8_dct1_CSTimingMux67_MASK                        0x4
+#define D18F2xA8_dct1_Reserved_3_3_OFFSET                       3
+#define D18F2xA8_dct1_Reserved_3_3_WIDTH                        1
+#define D18F2xA8_dct1_Reserved_3_3_MASK                         0x8
+#define D18F2xA8_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2xA8_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2xA8_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2xA8_dct1_SubMemclkRegDly_OFFSET                    5
+#define D18F2xA8_dct1_SubMemclkRegDly_WIDTH                     1
+#define D18F2xA8_dct1_SubMemclkRegDly_MASK                      0x20
+#define D18F2xA8_dct1_Reserved_7_6_OFFSET                       6
+#define D18F2xA8_dct1_Reserved_7_6_WIDTH                        2
+#define D18F2xA8_dct1_Reserved_7_6_MASK                         0xc0
+#define D18F2xA8_dct1_CtrlWordCS_7_0__OFFSET                    8
+#define D18F2xA8_dct1_CtrlWordCS_7_0__WIDTH                     8
+#define D18F2xA8_dct1_CtrlWordCS_7_0__MASK                      0xff00
+#define D18F2xA8_dct1_MemPhyPllPdMode_OFFSET                    16
+#define D18F2xA8_dct1_MemPhyPllPdMode_WIDTH                     2
+#define D18F2xA8_dct1_MemPhyPllPdMode_MASK                      0x30000
+#define D18F2xA8_dct1_Reserved_19_18_OFFSET                     18
+#define D18F2xA8_dct1_Reserved_19_18_WIDTH                      2
+#define D18F2xA8_dct1_Reserved_19_18_MASK                       0xc0000
+#define D18F2xA8_dct1_BankSwap_OFFSET                           20
+#define D18F2xA8_dct1_BankSwap_WIDTH                            1
+#define D18F2xA8_dct1_BankSwap_MASK                             0x100000
+#define D18F2xA8_dct1_AggrPDEn_OFFSET                           21
+#define D18F2xA8_dct1_AggrPDEn_WIDTH                            1
+#define D18F2xA8_dct1_AggrPDEn_MASK                             0x200000
+#define D18F2xA8_dct1_PrtlChPDEnhEn_OFFSET                      22
+#define D18F2xA8_dct1_PrtlChPDEnhEn_WIDTH                       1
+#define D18F2xA8_dct1_PrtlChPDEnhEn_MASK                        0x400000
+#define D18F2xA8_dct1_Reserved_23_23_OFFSET                     23
+#define D18F2xA8_dct1_Reserved_23_23_WIDTH                      1
+#define D18F2xA8_dct1_Reserved_23_23_MASK                       0x800000
+#define D18F2xA8_dct1_Reserved_25_24_OFFSET                     24
+#define D18F2xA8_dct1_Reserved_25_24_WIDTH                      2
+#define D18F2xA8_dct1_Reserved_25_24_MASK                       0x3000000
+#define D18F2xA8_dct1_CsMux45_OFFSET                            26
+#define D18F2xA8_dct1_CsMux45_WIDTH                             1
+#define D18F2xA8_dct1_CsMux45_MASK                              0x4000000
+#define D18F2xA8_dct1_CsMux67_OFFSET                            27
+#define D18F2xA8_dct1_CsMux67_WIDTH                             1
+#define D18F2xA8_dct1_CsMux67_MASK                              0x8000000
+#define D18F2xA8_dct1_FastSelfRefEntryDis_OFFSET                28
+#define D18F2xA8_dct1_FastSelfRefEntryDis_WIDTH                 1
+#define D18F2xA8_dct1_FastSelfRefEntryDis_MASK                  0x10000000
+#define D18F2xA8_dct1_RefChCmdMgtDis_OFFSET                     29
+#define D18F2xA8_dct1_RefChCmdMgtDis_WIDTH                      1
+#define D18F2xA8_dct1_RefChCmdMgtDis_MASK                       0x20000000
+#define D18F2xA8_dct1_Reserved_30_30_OFFSET                     30
+#define D18F2xA8_dct1_Reserved_30_30_WIDTH                      1
+#define D18F2xA8_dct1_Reserved_30_30_MASK                       0x40000000
+#define D18F2xA8_dct1_PerRankTimingEn_OFFSET                    31
+#define D18F2xA8_dct1_PerRankTimingEn_WIDTH                     1
+#define D18F2xA8_dct1_PerRankTimingEn_MASK                      0x80000000
+
+/// D18F2xA8_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CSTimingMux67:1 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          SubMemclkRegDly:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                          CtrlWordCS_7_0_:8 ; ///<
+    UINT32                                          MemPhyPllPdMode:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                                 AggrPDEn:1 ; ///<
+    UINT32                                            PrtlChPDEnhEn:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                  CsMux45:1 ; ///<
+    UINT32                                                  CsMux67:1 ; ///<
+    UINT32                                      FastSelfRefEntryDis:1 ; ///<
+    UINT32                                           RefChCmdMgtDis:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                          PerRankTimingEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xA8_dct1_STRUCT;
+
+// **** D18F2xAC Register Definition ****
+// Address
+#define D18F2xAC_ADDRESS                                        0xac
+
+// Type
+#define D18F2xAC_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xAC_MemTempHot0_OFFSET                             0
+#define D18F2xAC_MemTempHot0_WIDTH                              1
+#define D18F2xAC_MemTempHot0_MASK                               0x1
+#define D18F2xAC_Reserved_1_1_OFFSET                            1
+#define D18F2xAC_Reserved_1_1_WIDTH                             1
+#define D18F2xAC_Reserved_1_1_MASK                              0x2
+#define D18F2xAC_MemTempHot1_OFFSET                             2
+#define D18F2xAC_MemTempHot1_WIDTH                              1
+#define D18F2xAC_MemTempHot1_MASK                               0x4
+#define D18F2xAC_Reserved_31_3_OFFSET                           3
+#define D18F2xAC_Reserved_31_3_WIDTH                            29
+#define D18F2xAC_Reserved_31_3_MASK                             0xfffffff8
+
+/// D18F2xAC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MemTempHot0:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              MemTempHot1:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xAC_STRUCT;
+
+
+
+// **** D18F2xC4 Register Definition ****
+// Address
+
+
+
+
+
+
+
+
+
+
+
+// **** D18F2xF8 Register Definition ****
+// Address
+#define D18F2xF8_ADDRESS                                        0xf8
+
+// Type
+#define D18F2xF8_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xF8_PwrValue0_OFFSET                               0
+#define D18F2xF8_PwrValue0_WIDTH                                8
+#define D18F2xF8_PwrValue0_MASK                                 0xff
+#define D18F2xF8_PwrValue1_OFFSET                               8
+#define D18F2xF8_PwrValue1_WIDTH                                8
+#define D18F2xF8_PwrValue1_MASK                                 0xff00
+#define D18F2xF8_PwrValue2_OFFSET                               16
+#define D18F2xF8_PwrValue2_WIDTH                                8
+#define D18F2xF8_PwrValue2_MASK                                 0xff0000
+#define D18F2xF8_PwrValue3_OFFSET                               24
+#define D18F2xF8_PwrValue3_WIDTH                                8
+#define D18F2xF8_PwrValue3_MASK                                 0xff000000
+
+/// D18F2xF8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PwrValue0:8 ; ///<
+    UINT32                                                PwrValue1:8 ; ///<
+    UINT32                                                PwrValue2:8 ; ///<
+    UINT32                                                PwrValue3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xF8_STRUCT;
+
+
+// **** D18F2x104 Register Definition ****
+// Address
+#define D18F2x104_ADDRESS                                       0x104
+
+// Type
+#define D18F2x104_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x104_PwrValue5_OFFSET                              0
+#define D18F2x104_PwrValue5_WIDTH                               8
+#define D18F2x104_PwrValue5_MASK                                0xff
+#define D18F2x104_PwrValue6_OFFSET                              8
+#define D18F2x104_PwrValue6_WIDTH                               8
+#define D18F2x104_PwrValue6_MASK                                0xff00
+#define D18F2x104_PwrValue7_OFFSET                              16
+#define D18F2x104_PwrValue7_WIDTH                               8
+#define D18F2x104_PwrValue7_MASK                                0xff0000
+#define D18F2x104_Reserved_31_24_OFFSET                         24
+#define D18F2x104_Reserved_31_24_WIDTH                          8
+#define D18F2x104_Reserved_31_24_MASK                           0xff000000
+
+/// D18F2x104
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PwrValue5:8 ; ///<
+    UINT32                                                PwrValue6:8 ; ///<
+    UINT32                                                PwrValue7:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x104_STRUCT;
+
+// **** D18F2x10C Register Definition ****
+// Address
+#define D18F2x10C_ADDRESS                                       0x10c
+
+// Type
+#define D18F2x10C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x10C_IntLvRgnSwapEn_OFFSET                         0
+#define D18F2x10C_IntLvRgnSwapEn_WIDTH                          1
+#define D18F2x10C_IntLvRgnSwapEn_MASK                           0x1
+#define D18F2x10C_Reserved_2_1_OFFSET                           1
+#define D18F2x10C_Reserved_2_1_WIDTH                            2
+#define D18F2x10C_Reserved_2_1_MASK                             0x6
+#define D18F2x10C_IntLvRgnBaseAddr_33_27__OFFSET                3
+#define D18F2x10C_IntLvRgnBaseAddr_33_27__WIDTH                 7
+#define D18F2x10C_IntLvRgnBaseAddr_33_27__MASK                  0x3f8
+#define D18F2x10C_Reserved_10_10_OFFSET                         10
+#define D18F2x10C_Reserved_10_10_WIDTH                          1
+#define D18F2x10C_Reserved_10_10_MASK                           0x400
+#define D18F2x10C_IntLvRgnLmtAddr_33_27__OFFSET                 11
+#define D18F2x10C_IntLvRgnLmtAddr_33_27__WIDTH                  7
+#define D18F2x10C_IntLvRgnLmtAddr_33_27__MASK                   0x3f800
+#define D18F2x10C_Reserved_19_18_OFFSET                         18
+#define D18F2x10C_Reserved_19_18_WIDTH                          2
+#define D18F2x10C_Reserved_19_18_MASK                           0xc0000
+#define D18F2x10C_IntLvRgnSize_33_27__OFFSET                    20
+#define D18F2x10C_IntLvRgnSize_33_27__WIDTH                     7
+#define D18F2x10C_IntLvRgnSize_33_27__MASK                      0x7f00000
+#define D18F2x10C_Reserved_31_27_OFFSET                         27
+#define D18F2x10C_Reserved_31_27_WIDTH                          5
+#define D18F2x10C_Reserved_31_27_MASK                           0xf8000000
+
+/// D18F2x10C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           IntLvRgnSwapEn:1 ; ///<
+    UINT32                                             Reserved_2_1:2 ; ///<
+    UINT32                                  IntLvRgnBaseAddr_33_27_:7 ; ///<
+    UINT32                                           Reserved_10_10:1 ; ///<
+    UINT32                                   IntLvRgnLmtAddr_33_27_:7 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                      IntLvRgnSize_33_27_:7 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x10C_STRUCT;
+
+// **** D18F2x110 Register Definition ****
+// Address
+#define D18F2x110_ADDRESS                                       0x110
+
+// Type
+#define D18F2x110_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x110_DctSelHiRngEn_OFFSET                          0
+#define D18F2x110_DctSelHiRngEn_WIDTH                           1
+#define D18F2x110_DctSelHiRngEn_MASK                            0x1
+#define D18F2x110_DctSelHi_OFFSET                               1
+#define D18F2x110_DctSelHi_WIDTH                                1
+#define D18F2x110_DctSelHi_MASK                                 0x2
+#define D18F2x110_DctSelIntLvEn_OFFSET                          2
+#define D18F2x110_DctSelIntLvEn_WIDTH                           1
+#define D18F2x110_DctSelIntLvEn_MASK                            0x4
+#define D18F2x110_MemClrInit_OFFSET                             3
+#define D18F2x110_MemClrInit_WIDTH                              1
+#define D18F2x110_MemClrInit_MASK                               0x8
+#define D18F2x110_Reserved_4_4_OFFSET                           4
+#define D18F2x110_Reserved_4_4_WIDTH                            1
+#define D18F2x110_Reserved_4_4_MASK                             0x10
+#define D18F2x110_DctDatIntLv_OFFSET                            5
+#define D18F2x110_DctDatIntLv_WIDTH                             1
+#define D18F2x110_DctDatIntLv_MASK                              0x20
+#define D18F2x110_DctSelIntLvAddr_1_0__OFFSET                   6
+#define D18F2x110_DctSelIntLvAddr_1_0__WIDTH                    2
+#define D18F2x110_DctSelIntLvAddr_1_0__MASK                     0xc0
+#define D18F2x110_DramEnable_OFFSET                             8
+#define D18F2x110_DramEnable_WIDTH                              1
+#define D18F2x110_DramEnable_MASK                               0x100
+#define D18F2x110_MemClrBusy_OFFSET                             9
+#define D18F2x110_MemClrBusy_WIDTH                              1
+#define D18F2x110_MemClrBusy_MASK                               0x200
+#define D18F2x110_MemCleared_OFFSET                             10
+#define D18F2x110_MemCleared_WIDTH                              1
+#define D18F2x110_MemCleared_MASK                               0x400
+#define D18F2x110_DctSelBaseAddr_47_27__OFFSET                  11
+#define D18F2x110_DctSelBaseAddr_47_27__WIDTH                   21
+#define D18F2x110_DctSelBaseAddr_47_27__MASK                    0xfffff800
+
+/// D18F2x110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DctSelHiRngEn:1 ; ///<
+    UINT32                                                 DctSelHi:1 ; ///<
+    UINT32                                            DctSelIntLvEn:1 ; ///<
+    UINT32                                               MemClrInit:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                              DctDatIntLv:1 ; ///<
+    UINT32                                     DctSelIntLvAddr_1_0_:2 ; ///<
+    UINT32                                               DramEnable:1 ; ///<
+    UINT32                                               MemClrBusy:1 ; ///<
+    UINT32                                               MemCleared:1 ; ///<
+    UINT32                                    DctSelBaseAddr_47_27_:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x110_STRUCT;
+
+// **** D18F2x114 Register Definition ****
+// Address
+#define D18F2x114_ADDRESS                                       0x114
+
+// Type
+#define D18F2x114_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x114_Reserved_8_0_OFFSET                           0
+#define D18F2x114_Reserved_8_0_WIDTH                            9
+#define D18F2x114_Reserved_8_0_MASK                             0x1ff
+#define D18F2x114_DctSelIntLvAddr_2__OFFSET                     9
+#define D18F2x114_DctSelIntLvAddr_2__WIDTH                      1
+#define D18F2x114_DctSelIntLvAddr_2__MASK                       0x200
+#define D18F2x114_DctSelBaseOffset_47_26__OFFSET                10
+#define D18F2x114_DctSelBaseOffset_47_26__WIDTH                 22
+#define D18F2x114_DctSelBaseOffset_47_26__MASK                  0xfffffc00
+
+/// D18F2x114
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
+    UINT32                                  DctSelBaseOffset_47_26_:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x114_STRUCT;
+
+// **** D18F2x118 Register Definition ****
+// Address
+#define D18F2x118_ADDRESS                                       0x118
+
+// Type
+#define D18F2x118_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x118_MctPriCpuRd_OFFSET                            0
+#define D18F2x118_MctPriCpuRd_WIDTH                             2
+#define D18F2x118_MctPriCpuRd_MASK                              0x3
+#define D18F2x118_MctPriCpuWr_OFFSET                            2
+#define D18F2x118_MctPriCpuWr_WIDTH                             2
+#define D18F2x118_MctPriCpuWr_MASK                              0xc
+#define D18F2x118_MctPriIsocRd_OFFSET                           4
+#define D18F2x118_MctPriIsocRd_WIDTH                            2
+#define D18F2x118_MctPriIsocRd_MASK                             0x30
+#define D18F2x118_MctPriIsocWr_OFFSET                           6
+#define D18F2x118_MctPriIsocWr_WIDTH                            2
+#define D18F2x118_MctPriIsocWr_MASK                             0xc0
+#define D18F2x118_MctPriDefault_OFFSET                          8
+#define D18F2x118_MctPriDefault_WIDTH                           2
+#define D18F2x118_MctPriDefault_MASK                            0x300
+#define D18F2x118_MctPriWr_OFFSET                               10
+#define D18F2x118_MctPriWr_WIDTH                                2
+#define D18F2x118_MctPriWr_MASK                                 0xc00
+#define D18F2x118_MctPriIsoc_OFFSET                             12
+#define D18F2x118_MctPriIsoc_WIDTH                              2
+#define D18F2x118_MctPriIsoc_MASK                               0x3000
+#define D18F2x118_MctPriTrace_OFFSET                            14
+#define D18F2x118_MctPriTrace_WIDTH                             2
+#define D18F2x118_MctPriTrace_MASK                              0xc000
+#define D18F2x118_MctPriScrub_OFFSET                            16
+#define D18F2x118_MctPriScrub_WIDTH                             2
+#define D18F2x118_MctPriScrub_MASK                              0x30000
+#define D18F2x118_CC6SaveEn_OFFSET                              18
+#define D18F2x118_CC6SaveEn_WIDTH                               1
+#define D18F2x118_CC6SaveEn_MASK                                0x40000
+#define D18F2x118_LockDramCfg_OFFSET                            19
+#define D18F2x118_LockDramCfg_WIDTH                             1
+#define D18F2x118_LockDramCfg_MASK                              0x80000
+#define D18F2x118_McqMedPriByPassMax_OFFSET                     20
+#define D18F2x118_McqMedPriByPassMax_WIDTH                      3
+#define D18F2x118_McqMedPriByPassMax_MASK                       0x700000
+#define D18F2x118_Reserved_23_23_OFFSET                         23
+#define D18F2x118_Reserved_23_23_WIDTH                          1
+#define D18F2x118_Reserved_23_23_MASK                           0x800000
+#define D18F2x118_McqHiPriByPassMax_OFFSET                      24
+#define D18F2x118_McqHiPriByPassMax_WIDTH                       3
+#define D18F2x118_McqHiPriByPassMax_MASK                        0x7000000
+#define D18F2x118_MctEccDisLatOptEn_OFFSET                      27
+#define D18F2x118_MctEccDisLatOptEn_WIDTH                       1
+#define D18F2x118_MctEccDisLatOptEn_MASK                        0x8000000
+#define D18F2x118_MctVarPriCntLmt_OFFSET                        28
+#define D18F2x118_MctVarPriCntLmt_WIDTH                         4
+#define D18F2x118_MctVarPriCntLmt_MASK                          0xf0000000
+
+/// D18F2x118
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MctPriCpuRd:2 ; ///<
+    UINT32                                              MctPriCpuWr:2 ; ///<
+    UINT32                                             MctPriIsocRd:2 ; ///<
+    UINT32                                             MctPriIsocWr:2 ; ///<
+    UINT32                                            MctPriDefault:2 ; ///<
+    UINT32                                                 MctPriWr:2 ; ///<
+    UINT32                                               MctPriIsoc:2 ; ///<
+    UINT32                                              MctPriTrace:2 ; ///<
+    UINT32                                              MctPriScrub:2 ; ///<
+    UINT32                                                CC6SaveEn:1 ; ///<
+    UINT32                                              LockDramCfg:1 ; ///<
+    UINT32                                       McqMedPriByPassMax:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        McqHiPriByPassMax:3 ; ///<
+    UINT32                                        MctEccDisLatOptEn:1 ; ///<
+    UINT32                                          MctVarPriCntLmt:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x118_STRUCT;
+
+// **** D18F2x11C Register Definition ****
+// Address
+#define D18F2x11C_ADDRESS                                       0x11c
+
+// Type
+#define D18F2x11C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x11C_DctWrLimit_OFFSET                             0
+#define D18F2x11C_DctWrLimit_WIDTH                              2
+#define D18F2x11C_DctWrLimit_MASK                               0x3
+#define D18F2x11C_MctWrLimit_OFFSET                             2
+#define D18F2x11C_MctWrLimit_WIDTH                              5
+#define D18F2x11C_MctWrLimit_MASK                               0x7c
+#define D18F2x11C_MctPrefReqLimit_OFFSET                        7
+#define D18F2x11C_MctPrefReqLimit_WIDTH                         5
+#define D18F2x11C_MctPrefReqLimit_MASK                          0xf80
+#define D18F2x11C_PrefCpuDis_OFFSET                             12
+#define D18F2x11C_PrefCpuDis_WIDTH                              1
+#define D18F2x11C_PrefCpuDis_MASK                               0x1000
+#define D18F2x11C_PrefIoDis_OFFSET                              13
+#define D18F2x11C_PrefIoDis_WIDTH                               1
+#define D18F2x11C_PrefIoDis_MASK                                0x2000
+#define D18F2x11C_PrefIoFixStrideEn_OFFSET                      14
+#define D18F2x11C_PrefIoFixStrideEn_WIDTH                       1
+#define D18F2x11C_PrefIoFixStrideEn_MASK                        0x4000
+#define D18F2x11C_PrefFixStrideEn_OFFSET                        15
+#define D18F2x11C_PrefFixStrideEn_WIDTH                         1
+#define D18F2x11C_PrefFixStrideEn_MASK                          0x8000
+#define D18F2x11C_PrefFixDist_OFFSET                            16
+#define D18F2x11C_PrefFixDist_WIDTH                             2
+#define D18F2x11C_PrefFixDist_MASK                              0x30000
+#define D18F2x11C_PrefConfSat_OFFSET                            18
+#define D18F2x11C_PrefConfSat_WIDTH                             2
+#define D18F2x11C_PrefConfSat_MASK                              0xc0000
+#define D18F2x11C_PrefOneConf_OFFSET                            20
+#define D18F2x11C_PrefOneConf_WIDTH                             2
+#define D18F2x11C_PrefOneConf_MASK                              0x300000
+#define D18F2x11C_PrefTwoConf_OFFSET                            22
+#define D18F2x11C_PrefTwoConf_WIDTH                             3
+#define D18F2x11C_PrefTwoConf_MASK                              0x1c00000
+#define D18F2x11C_PrefThreeConf_OFFSET                          25
+#define D18F2x11C_PrefThreeConf_WIDTH                           3
+#define D18F2x11C_PrefThreeConf_MASK                            0xe000000
+#define D18F2x11C_PrefDramTrainMode_OFFSET                      28
+#define D18F2x11C_PrefDramTrainMode_WIDTH                       1
+#define D18F2x11C_PrefDramTrainMode_MASK                        0x10000000
+#define D18F2x11C_FlushWrOnStpGnt_OFFSET                        29
+#define D18F2x11C_FlushWrOnStpGnt_WIDTH                         1
+#define D18F2x11C_FlushWrOnStpGnt_MASK                          0x20000000
+#define D18F2x11C_FlushWr_OFFSET                                30
+#define D18F2x11C_FlushWr_WIDTH                                 1
+#define D18F2x11C_FlushWr_MASK                                  0x40000000
+#define D18F2x11C_Reserved_31_31_OFFSET                         31
+#define D18F2x11C_Reserved_31_31_WIDTH                          1
+#define D18F2x11C_Reserved_31_31_MASK                           0x80000000
+
+/// D18F2x11C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               DctWrLimit:2 ; ///<
+    UINT32                                               MctWrLimit:5 ; ///<
+    UINT32                                          MctPrefReqLimit:5 ; ///<
+    UINT32                                               PrefCpuDis:1 ; ///<
+    UINT32                                                PrefIoDis:1 ; ///<
+    UINT32                                        PrefIoFixStrideEn:1 ; ///<
+    UINT32                                          PrefFixStrideEn:1 ; ///<
+    UINT32                                              PrefFixDist:2 ; ///<
+    UINT32                                              PrefConfSat:2 ; ///<
+    UINT32                                              PrefOneConf:2 ; ///<
+    UINT32                                              PrefTwoConf:3 ; ///<
+    UINT32                                            PrefThreeConf:3 ; ///<
+    UINT32                                        PrefDramTrainMode:1 ; ///<
+    UINT32                                          FlushWrOnStpGnt:1 ; ///<
+    UINT32                                                  FlushWr:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x11C_STRUCT;
+
+
+
+
+
+
+// **** D18F2x1B0 Register Definition ****
+// Address
+#define D18F2x1B0_ADDRESS                                       0x1b0
+
+// Type
+#define D18F2x1B0_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x1B0_AdapPrefMissRatio_OFFSET                      0
+#define D18F2x1B0_AdapPrefMissRatio_WIDTH                       2
+#define D18F2x1B0_AdapPrefMissRatio_MASK                        0x3
+#define D18F2x1B0_AdapPrefPositiveStep_OFFSET                   2
+#define D18F2x1B0_AdapPrefPositiveStep_WIDTH                    2
+#define D18F2x1B0_AdapPrefPositiveStep_MASK                     0xc
+#define D18F2x1B0_AdapPrefNegativeStep_OFFSET                   4
+#define D18F2x1B0_AdapPrefNegativeStep_WIDTH                    2
+#define D18F2x1B0_AdapPrefNegativeStep_MASK                     0x30
+#define D18F2x1B0_Reserved_7_6_OFFSET                           6
+#define D18F2x1B0_Reserved_7_6_WIDTH                            2
+#define D18F2x1B0_Reserved_7_6_MASK                             0xc0
+#define D18F2x1B0_CohPrefPrbLmt_OFFSET                          8
+#define D18F2x1B0_CohPrefPrbLmt_WIDTH                           3
+#define D18F2x1B0_CohPrefPrbLmt_MASK                            0x700
+#define D18F2x1B0_DisIoCohPref_OFFSET                           11
+#define D18F2x1B0_DisIoCohPref_WIDTH                            1
+#define D18F2x1B0_DisIoCohPref_MASK                             0x800
+#define D18F2x1B0_EnSplitDctLimits_OFFSET                       12
+#define D18F2x1B0_EnSplitDctLimits_WIDTH                        1
+#define D18F2x1B0_EnSplitDctLimits_MASK                         0x1000
+#define D18F2x1B0_Reserved_17_13_OFFSET                         13
+#define D18F2x1B0_Reserved_17_13_WIDTH                          5
+#define D18F2x1B0_Reserved_17_13_MASK                           0x3e000
+#define D18F2x1B0_Reserved_19_18_OFFSET                         18
+#define D18F2x1B0_Reserved_19_18_WIDTH                          2
+#define D18F2x1B0_Reserved_19_18_MASK                           0xc0000
+#define D18F2x1B0_DblPrefEn_OFFSET                              20
+#define D18F2x1B0_DblPrefEn_WIDTH                               1
+#define D18F2x1B0_DblPrefEn_MASK                                0x100000
+#define D18F2x1B0_Reserved_21_21_OFFSET                         21
+#define D18F2x1B0_Reserved_21_21_WIDTH                          1
+#define D18F2x1B0_Reserved_21_21_MASK                           0x200000
+#define D18F2x1B0_PrefFourConf_OFFSET                           22
+#define D18F2x1B0_PrefFourConf_WIDTH                            3
+#define D18F2x1B0_PrefFourConf_MASK                             0x1c00000
+#define D18F2x1B0_PrefFiveConf_OFFSET                           25
+#define D18F2x1B0_PrefFiveConf_WIDTH                            3
+#define D18F2x1B0_PrefFiveConf_MASK                             0xe000000
+#define D18F2x1B0_DcqBwThrotWm_OFFSET                           28
+#define D18F2x1B0_DcqBwThrotWm_WIDTH                            4
+#define D18F2x1B0_DcqBwThrotWm_MASK                             0xf0000000
+
+/// D18F2x1B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AdapPrefMissRatio:2 ; ///<
+    UINT32                                     AdapPrefPositiveStep:2 ; ///<
+    UINT32                                     AdapPrefNegativeStep:2 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                            CohPrefPrbLmt:3 ; ///<
+    UINT32                                             DisIoCohPref:1 ; ///<
+    UINT32                                         EnSplitDctLimits:1 ; ///<
+    UINT32                                           Reserved_17_13:5 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                DblPrefEn:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                             PrefFourConf:3 ; ///<
+    UINT32                                             PrefFiveConf:3 ; ///<
+    UINT32                                             DcqBwThrotWm:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x1B0_STRUCT;
+
+// **** D18F2x1B4 Register Definition ****
+// Address
+#define D18F2x1B4_ADDRESS                                       0x1b4
+
+// Type
+#define D18F2x1B4_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x1B4_DcqBwThrotWm1_OFFSET                          0
+#define D18F2x1B4_DcqBwThrotWm1_WIDTH                           5
+#define D18F2x1B4_DcqBwThrotWm1_MASK                            0x1f
+#define D18F2x1B4_DcqBwThrotWm2_OFFSET                          5
+#define D18F2x1B4_DcqBwThrotWm2_WIDTH                           5
+#define D18F2x1B4_DcqBwThrotWm2_MASK                            0x3e0
+#define D18F2x1B4_DemandPropWm1_OFFSET                          10
+#define D18F2x1B4_DemandPropWm1_WIDTH                           1
+#define D18F2x1B4_DemandPropWm1_MASK                            0x400
+#define D18F2x1B4_DemandAlloWm1_OFFSET                          11
+#define D18F2x1B4_DemandAlloWm1_WIDTH                           1
+#define D18F2x1B4_DemandAlloWm1_MASK                            0x800
+#define D18F2x1B4_StridePropWm1_OFFSET                          12
+#define D18F2x1B4_StridePropWm1_WIDTH                           1
+#define D18F2x1B4_StridePropWm1_MASK                            0x1000
+#define D18F2x1B4_StrideAlloWm1_OFFSET                          13
+#define D18F2x1B4_StrideAlloWm1_WIDTH                           1
+#define D18F2x1B4_StrideAlloWm1_MASK                            0x2000
+#define D18F2x1B4_RegionPropWm1_OFFSET                          14
+#define D18F2x1B4_RegionPropWm1_WIDTH                           1
+#define D18F2x1B4_RegionPropWm1_MASK                            0x4000
+#define D18F2x1B4_RegionAlloWm1_OFFSET                          15
+#define D18F2x1B4_RegionAlloWm1_WIDTH                           1
+#define D18F2x1B4_RegionAlloWm1_MASK                            0x8000
+#define D18F2x1B4_DemandPropWm2_OFFSET                          16
+#define D18F2x1B4_DemandPropWm2_WIDTH                           1
+#define D18F2x1B4_DemandPropWm2_MASK                            0x10000
+#define D18F2x1B4_DemandAlloWm2_OFFSET                          17
+#define D18F2x1B4_DemandAlloWm2_WIDTH                           1
+#define D18F2x1B4_DemandAlloWm2_MASK                            0x20000
+#define D18F2x1B4_StridePropWm2_OFFSET                          18
+#define D18F2x1B4_StridePropWm2_WIDTH                           1
+#define D18F2x1B4_StridePropWm2_MASK                            0x40000
+#define D18F2x1B4_StrideAlloWm2_OFFSET                          19
+#define D18F2x1B4_StrideAlloWm2_WIDTH                           1
+#define D18F2x1B4_StrideAlloWm2_MASK                            0x80000
+#define D18F2x1B4_RegionPropWm2_OFFSET                          20
+#define D18F2x1B4_RegionPropWm2_WIDTH                           1
+#define D18F2x1B4_RegionPropWm2_MASK                            0x100000
+#define D18F2x1B4_RegionAlloWm2_OFFSET                          21
+#define D18F2x1B4_RegionAlloWm2_WIDTH                           1
+#define D18F2x1B4_RegionAlloWm2_MASK                            0x200000
+#define D18F2x1B4_SpecPrefDisWm1_OFFSET                         22
+#define D18F2x1B4_SpecPrefDisWm1_WIDTH                          1
+#define D18F2x1B4_SpecPrefDisWm1_MASK                           0x400000
+#define D18F2x1B4_Reserved_25_23_OFFSET                         23
+#define D18F2x1B4_Reserved_25_23_WIDTH                          3
+#define D18F2x1B4_Reserved_25_23_MASK                           0x3800000
+#define D18F2x1B4_EnSplitMctDatBuffers_OFFSET                   26
+#define D18F2x1B4_EnSplitMctDatBuffers_WIDTH                    1
+#define D18F2x1B4_EnSplitMctDatBuffers_MASK                     0x4000000
+#define D18F2x1B4_FlushWrOnS3StpGnt_OFFSET                      27
+#define D18F2x1B4_FlushWrOnS3StpGnt_WIDTH                       1
+#define D18F2x1B4_FlushWrOnS3StpGnt_MASK                        0x8000000
+#define D18F2x1B4_S3SmafId_OFFSET                               28
+#define D18F2x1B4_S3SmafId_WIDTH                                3
+#define D18F2x1B4_S3SmafId_MASK                                 0x70000000
+#define D18F2x1B4_FlushOnMmioWrEn_OFFSET                        31
+#define D18F2x1B4_FlushOnMmioWrEn_WIDTH                         1
+#define D18F2x1B4_FlushOnMmioWrEn_MASK                          0x80000000
+
+/// D18F2x1B4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DcqBwThrotWm1:5 ; ///<
+    UINT32                                            DcqBwThrotWm2:5 ; ///<
+    UINT32                                            DemandPropWm1:1 ; ///<
+    UINT32                                            DemandAlloWm1:1 ; ///<
+    UINT32                                            StridePropWm1:1 ; ///<
+    UINT32                                            StrideAlloWm1:1 ; ///<
+    UINT32                                            RegionPropWm1:1 ; ///<
+    UINT32                                            RegionAlloWm1:1 ; ///<
+    UINT32                                            DemandPropWm2:1 ; ///<
+    UINT32                                            DemandAlloWm2:1 ; ///<
+    UINT32                                            StridePropWm2:1 ; ///<
+    UINT32                                            StrideAlloWm2:1 ; ///<
+    UINT32                                            RegionPropWm2:1 ; ///<
+    UINT32                                            RegionAlloWm2:1 ; ///<
+    UINT32                                           SpecPrefDisWm1:1 ; ///<
+    UINT32                                           Reserved_25_23:3 ; ///<
+    UINT32                                     EnSplitMctDatBuffers:1 ; ///<
+    UINT32                                        FlushWrOnS3StpGnt:1 ; ///<
+    UINT32                                                 S3SmafId:3 ; ///<
+    UINT32                                          FlushOnMmioWrEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x1B4_STRUCT;
+
+// **** D18F2x200_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x200_dct0_mp1_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x200_dct0_mp1_Tcl_OFFSET                           0
+#define D18F2x200_dct0_mp1_Tcl_WIDTH                            5
+#define D18F2x200_dct0_mp1_Tcl_MASK                             0x1f
+#define D18F2x200_dct0_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct0_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct0_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct0_mp1_Trcd_OFFSET                          8
+#define D18F2x200_dct0_mp1_Trcd_WIDTH                           5
+#define D18F2x200_dct0_mp1_Trcd_MASK                            0x1f00
+#define D18F2x200_dct0_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct0_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct0_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct0_mp1_Trp_OFFSET                           16
+#define D18F2x200_dct0_mp1_Trp_WIDTH                            5
+#define D18F2x200_dct0_mp1_Trp_MASK                             0x1f0000
+#define D18F2x200_dct0_mp1_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct0_mp1_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct0_mp1_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct0_mp1_Tras_OFFSET                          24
+#define D18F2x200_dct0_mp1_Tras_WIDTH                           6
+#define D18F2x200_dct0_mp1_Tras_MASK                            0x3f000000
+#define D18F2x200_dct0_mp1_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct0_mp1_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct0_mp1_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct0_mp1_STRUCT;
+
+// **** D18F2x200_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x200_dct0_mp0_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x200_dct0_mp0_Tcl_OFFSET                           0
+#define D18F2x200_dct0_mp0_Tcl_WIDTH                            5
+#define D18F2x200_dct0_mp0_Tcl_MASK                             0x1f
+#define D18F2x200_dct0_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct0_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct0_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct0_mp0_Trcd_OFFSET                          8
+#define D18F2x200_dct0_mp0_Trcd_WIDTH                           5
+#define D18F2x200_dct0_mp0_Trcd_MASK                            0x1f00
+#define D18F2x200_dct0_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct0_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct0_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct0_mp0_Trp_OFFSET                           16
+#define D18F2x200_dct0_mp0_Trp_WIDTH                            5
+#define D18F2x200_dct0_mp0_Trp_MASK                             0x1f0000
+#define D18F2x200_dct0_mp0_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct0_mp0_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct0_mp0_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct0_mp0_Tras_OFFSET                          24
+#define D18F2x200_dct0_mp0_Tras_WIDTH                           6
+#define D18F2x200_dct0_mp0_Tras_MASK                            0x3f000000
+#define D18F2x200_dct0_mp0_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct0_mp0_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct0_mp0_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct0_mp0_STRUCT;
+
+// **** D18F2x200_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x200_dct1_mp1_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x200_dct1_mp1_Tcl_OFFSET                           0
+#define D18F2x200_dct1_mp1_Tcl_WIDTH                            5
+#define D18F2x200_dct1_mp1_Tcl_MASK                             0x1f
+#define D18F2x200_dct1_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct1_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct1_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct1_mp1_Trcd_OFFSET                          8
+#define D18F2x200_dct1_mp1_Trcd_WIDTH                           5
+#define D18F2x200_dct1_mp1_Trcd_MASK                            0x1f00
+#define D18F2x200_dct1_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct1_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct1_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct1_mp1_Trp_OFFSET                           16
+#define D18F2x200_dct1_mp1_Trp_WIDTH                            5
+#define D18F2x200_dct1_mp1_Trp_MASK                             0x1f0000
+#define D18F2x200_dct1_mp1_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct1_mp1_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct1_mp1_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct1_mp1_Tras_OFFSET                          24
+#define D18F2x200_dct1_mp1_Tras_WIDTH                           6
+#define D18F2x200_dct1_mp1_Tras_MASK                            0x3f000000
+#define D18F2x200_dct1_mp1_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct1_mp1_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct1_mp1_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct1_mp1_STRUCT;
+
+// **** D18F2x200_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x200_dct1_mp0_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x200_dct1_mp0_Tcl_OFFSET                           0
+#define D18F2x200_dct1_mp0_Tcl_WIDTH                            5
+#define D18F2x200_dct1_mp0_Tcl_MASK                             0x1f
+#define D18F2x200_dct1_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct1_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct1_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct1_mp0_Trcd_OFFSET                          8
+#define D18F2x200_dct1_mp0_Trcd_WIDTH                           5
+#define D18F2x200_dct1_mp0_Trcd_MASK                            0x1f00
+#define D18F2x200_dct1_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct1_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct1_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct1_mp0_Trp_OFFSET                           16
+#define D18F2x200_dct1_mp0_Trp_WIDTH                            5
+#define D18F2x200_dct1_mp0_Trp_MASK                             0x1f0000
+#define D18F2x200_dct1_mp0_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct1_mp0_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct1_mp0_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct1_mp0_Tras_OFFSET                          24
+#define D18F2x200_dct1_mp0_Tras_WIDTH                           6
+#define D18F2x200_dct1_mp0_Tras_MASK                            0x3f000000
+#define D18F2x200_dct1_mp0_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct1_mp0_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct1_mp0_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct1_mp0_STRUCT;
+
+// **** D18F2x204_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x204_dct0_mp0_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x204_dct0_mp0_Trc_OFFSET                           0
+#define D18F2x204_dct0_mp0_Trc_WIDTH                            6
+#define D18F2x204_dct0_mp0_Trc_MASK                             0x3f
+#define D18F2x204_dct0_mp0_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct0_mp0_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct0_mp0_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct0_mp0_Trrd_OFFSET                          8
+#define D18F2x204_dct0_mp0_Trrd_WIDTH                           4
+#define D18F2x204_dct0_mp0_Trrd_MASK                            0xf00
+#define D18F2x204_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct0_mp0_FourActWindow_OFFSET                 16
+#define D18F2x204_dct0_mp0_FourActWindow_WIDTH                  6
+#define D18F2x204_dct0_mp0_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct0_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct0_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct0_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct0_mp0_Trtp_OFFSET                          24
+#define D18F2x204_dct0_mp0_Trtp_WIDTH                           4
+#define D18F2x204_dct0_mp0_Trtp_MASK                            0xf000000
+#define D18F2x204_dct0_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct0_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct0_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct0_mp0_STRUCT;
+
+// **** D18F2x204_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x204_dct1_mp0_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x204_dct1_mp0_Trc_OFFSET                           0
+#define D18F2x204_dct1_mp0_Trc_WIDTH                            6
+#define D18F2x204_dct1_mp0_Trc_MASK                             0x3f
+#define D18F2x204_dct1_mp0_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct1_mp0_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct1_mp0_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct1_mp0_Trrd_OFFSET                          8
+#define D18F2x204_dct1_mp0_Trrd_WIDTH                           4
+#define D18F2x204_dct1_mp0_Trrd_MASK                            0xf00
+#define D18F2x204_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct1_mp0_FourActWindow_OFFSET                 16
+#define D18F2x204_dct1_mp0_FourActWindow_WIDTH                  6
+#define D18F2x204_dct1_mp0_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct1_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct1_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct1_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct1_mp0_Trtp_OFFSET                          24
+#define D18F2x204_dct1_mp0_Trtp_WIDTH                           4
+#define D18F2x204_dct1_mp0_Trtp_MASK                            0xf000000
+#define D18F2x204_dct1_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct1_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct1_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct1_mp0_STRUCT;
+
+// **** D18F2x204_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x204_dct0_mp1_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x204_dct0_mp1_Trc_OFFSET                           0
+#define D18F2x204_dct0_mp1_Trc_WIDTH                            6
+#define D18F2x204_dct0_mp1_Trc_MASK                             0x3f
+#define D18F2x204_dct0_mp1_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct0_mp1_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct0_mp1_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct0_mp1_Trrd_OFFSET                          8
+#define D18F2x204_dct0_mp1_Trrd_WIDTH                           4
+#define D18F2x204_dct0_mp1_Trrd_MASK                            0xf00
+#define D18F2x204_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct0_mp1_FourActWindow_OFFSET                 16
+#define D18F2x204_dct0_mp1_FourActWindow_WIDTH                  6
+#define D18F2x204_dct0_mp1_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct0_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct0_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct0_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct0_mp1_Trtp_OFFSET                          24
+#define D18F2x204_dct0_mp1_Trtp_WIDTH                           4
+#define D18F2x204_dct0_mp1_Trtp_MASK                            0xf000000
+#define D18F2x204_dct0_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct0_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct0_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct0_mp1_STRUCT;
+
+// **** D18F2x204_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x204_dct1_mp1_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x204_dct1_mp1_Trc_OFFSET                           0
+#define D18F2x204_dct1_mp1_Trc_WIDTH                            6
+#define D18F2x204_dct1_mp1_Trc_MASK                             0x3f
+#define D18F2x204_dct1_mp1_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct1_mp1_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct1_mp1_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct1_mp1_Trrd_OFFSET                          8
+#define D18F2x204_dct1_mp1_Trrd_WIDTH                           4
+#define D18F2x204_dct1_mp1_Trrd_MASK                            0xf00
+#define D18F2x204_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct1_mp1_FourActWindow_OFFSET                 16
+#define D18F2x204_dct1_mp1_FourActWindow_WIDTH                  6
+#define D18F2x204_dct1_mp1_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct1_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct1_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct1_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct1_mp1_Trtp_OFFSET                          24
+#define D18F2x204_dct1_mp1_Trtp_WIDTH                           4
+#define D18F2x204_dct1_mp1_Trtp_MASK                            0xf000000
+#define D18F2x204_dct1_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct1_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct1_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct1_mp1_STRUCT;
+
+// **** D18F2x208_dct0 Register Definition ****
+// Address
+#define D18F2x208_dct0_ADDRESS                                  0x208
+
+// Type
+#define D18F2x208_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x208_dct0_Trfc0_OFFSET                             0
+#define D18F2x208_dct0_Trfc0_WIDTH                              3
+#define D18F2x208_dct0_Trfc0_MASK                               0x7
+#define D18F2x208_dct0_Reserved_7_3_OFFSET                      3
+#define D18F2x208_dct0_Reserved_7_3_WIDTH                       5
+#define D18F2x208_dct0_Reserved_7_3_MASK                        0xf8
+#define D18F2x208_dct0_Trfc1_OFFSET                             8
+#define D18F2x208_dct0_Trfc1_WIDTH                              3
+#define D18F2x208_dct0_Trfc1_MASK                               0x700
+#define D18F2x208_dct0_Reserved_15_11_OFFSET                    11
+#define D18F2x208_dct0_Reserved_15_11_WIDTH                     5
+#define D18F2x208_dct0_Reserved_15_11_MASK                      0xf800
+#define D18F2x208_dct0_Trfc2_OFFSET                             16
+#define D18F2x208_dct0_Trfc2_WIDTH                              3
+#define D18F2x208_dct0_Trfc2_MASK                               0x70000
+#define D18F2x208_dct0_Reserved_23_19_OFFSET                    19
+#define D18F2x208_dct0_Reserved_23_19_WIDTH                     5
+#define D18F2x208_dct0_Reserved_23_19_MASK                      0xf80000
+#define D18F2x208_dct0_Trfc3_OFFSET                             24
+#define D18F2x208_dct0_Trfc3_WIDTH                              3
+#define D18F2x208_dct0_Trfc3_MASK                               0x7000000
+#define D18F2x208_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x208_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x208_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x208_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Trfc0:3 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                                    Trfc1:3 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                                    Trfc2:3 ; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                                    Trfc3:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x208_dct0_STRUCT;
+
+// **** D18F2x208_dct1 Register Definition ****
+// Address
+#define D18F2x208_dct1_ADDRESS                                  0x208
+
+// Type
+#define D18F2x208_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x208_dct1_Trfc0_OFFSET                             0
+#define D18F2x208_dct1_Trfc0_WIDTH                              3
+#define D18F2x208_dct1_Trfc0_MASK                               0x7
+#define D18F2x208_dct1_Reserved_7_3_OFFSET                      3
+#define D18F2x208_dct1_Reserved_7_3_WIDTH                       5
+#define D18F2x208_dct1_Reserved_7_3_MASK                        0xf8
+#define D18F2x208_dct1_Trfc1_OFFSET                             8
+#define D18F2x208_dct1_Trfc1_WIDTH                              3
+#define D18F2x208_dct1_Trfc1_MASK                               0x700
+#define D18F2x208_dct1_Reserved_15_11_OFFSET                    11
+#define D18F2x208_dct1_Reserved_15_11_WIDTH                     5
+#define D18F2x208_dct1_Reserved_15_11_MASK                      0xf800
+#define D18F2x208_dct1_Trfc2_OFFSET                             16
+#define D18F2x208_dct1_Trfc2_WIDTH                              3
+#define D18F2x208_dct1_Trfc2_MASK                               0x70000
+#define D18F2x208_dct1_Reserved_23_19_OFFSET                    19
+#define D18F2x208_dct1_Reserved_23_19_WIDTH                     5
+#define D18F2x208_dct1_Reserved_23_19_MASK                      0xf80000
+#define D18F2x208_dct1_Trfc3_OFFSET                             24
+#define D18F2x208_dct1_Trfc3_WIDTH                              3
+#define D18F2x208_dct1_Trfc3_MASK                               0x7000000
+#define D18F2x208_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x208_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x208_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x208_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Trfc0:3 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                                    Trfc1:3 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                                    Trfc2:3 ; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                                    Trfc3:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x208_dct1_STRUCT;
+
+// **** D18F2x20C_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x20C_dct0_mp1_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x20C_dct0_mp1_Tcwl_OFFSET                          0
+#define D18F2x20C_dct0_mp1_Tcwl_WIDTH                           5
+#define D18F2x20C_dct0_mp1_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct0_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct0_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct0_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct0_mp1_Twtr_OFFSET                          8
+#define D18F2x20C_dct0_mp1_Twtr_WIDTH                           4
+#define D18F2x20C_dct0_mp1_Twtr_MASK                            0xf00
+#define D18F2x20C_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct0_mp1_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct0_mp1_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct0_mp1_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct0_mp1_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct0_mp1_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct0_mp1_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct0_mp1_STRUCT;
+
+// **** D18F2x20C_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x20C_dct1_mp1_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x20C_dct1_mp1_Tcwl_OFFSET                          0
+#define D18F2x20C_dct1_mp1_Tcwl_WIDTH                           5
+#define D18F2x20C_dct1_mp1_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct1_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct1_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct1_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct1_mp1_Twtr_OFFSET                          8
+#define D18F2x20C_dct1_mp1_Twtr_WIDTH                           4
+#define D18F2x20C_dct1_mp1_Twtr_MASK                            0xf00
+#define D18F2x20C_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct1_mp1_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct1_mp1_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct1_mp1_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct1_mp1_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct1_mp1_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct1_mp1_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct1_mp1_STRUCT;
+
+// **** D18F2x20C_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x20C_dct1_mp0_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x20C_dct1_mp0_Tcwl_OFFSET                          0
+#define D18F2x20C_dct1_mp0_Tcwl_WIDTH                           5
+#define D18F2x20C_dct1_mp0_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct1_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct1_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct1_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct1_mp0_Twtr_OFFSET                          8
+#define D18F2x20C_dct1_mp0_Twtr_WIDTH                           4
+#define D18F2x20C_dct1_mp0_Twtr_MASK                            0xf00
+#define D18F2x20C_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct1_mp0_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct1_mp0_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct1_mp0_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct1_mp0_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct1_mp0_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct1_mp0_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct1_mp0_STRUCT;
+
+// **** D18F2x20C_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x20C_dct0_mp0_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x20C_dct0_mp0_Tcwl_OFFSET                          0
+#define D18F2x20C_dct0_mp0_Tcwl_WIDTH                           5
+#define D18F2x20C_dct0_mp0_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct0_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct0_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct0_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct0_mp0_Twtr_OFFSET                          8
+#define D18F2x20C_dct0_mp0_Twtr_WIDTH                           4
+#define D18F2x20C_dct0_mp0_Twtr_MASK                            0xf00
+#define D18F2x20C_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct0_mp0_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct0_mp0_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct0_mp0_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct0_mp0_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct0_mp0_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct0_mp0_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct0_mp0_STRUCT;
+
+// **** D18F2x210_dct1_nbp0 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp0_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp0_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp0_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp0_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp0_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp0_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp0_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp0_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp0_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp0_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp0_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp0_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp0_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp0_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp0_STRUCT;
+
+// **** D18F2x210_dct0_nbp2 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp2_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp2_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp2_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp2_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp2_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp2_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp2_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp2_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp2_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp2_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp2_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp2_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp2_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp2_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp2_STRUCT;
+
+// **** D18F2x210_dct1_nbp1 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp1_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp1_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp1_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp1_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp1_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp1_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp1_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp1_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp1_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp1_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp1_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp1_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp1_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp1_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp1_STRUCT;
+
+// **** D18F2x210_dct1_nbp3 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp3_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp3_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp3_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp3_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp3_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp3_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp3_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp3_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp3_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp3_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp3_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp3_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp3_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp3_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp3_STRUCT;
+
+// **** D18F2x210_dct0_nbp0 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp0_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp0_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp0_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp0_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp0_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp0_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp0_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp0_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp0_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp0_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp0_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp0_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp0_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp0_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp0_STRUCT;
+
+// **** D18F2x210_dct0_nbp3 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp3_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp3_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp3_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp3_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp3_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp3_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp3_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp3_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp3_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp3_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp3_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp3_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp3_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp3_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp3_STRUCT;
+
+// **** D18F2x210_dct1_nbp2 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp2_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp2_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp2_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp2_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp2_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp2_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp2_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp2_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp2_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp2_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp2_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp2_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp2_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp2_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp2_STRUCT;
+
+// **** D18F2x210_dct0_nbp1 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp1_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp1_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp1_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp1_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp1_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp1_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp1_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp1_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp1_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp1_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp1_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp1_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp1_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp1_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp1_STRUCT;
+
+// **** D18F2x214_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x214_dct1_mp1_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x214_dct1_mp1_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct1_mp1_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct1_mp1_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct1_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct1_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct1_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct1_mp1_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct1_mp1_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct1_mp1_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct1_mp1_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct1_mp1_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct1_mp1_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct1_mp1_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct1_mp1_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct1_mp1_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct1_mp1_STRUCT;
+
+// **** D18F2x214_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x214_dct0_mp0_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x214_dct0_mp0_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct0_mp0_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct0_mp0_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct0_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct0_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct0_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct0_mp0_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct0_mp0_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct0_mp0_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct0_mp0_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct0_mp0_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct0_mp0_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct0_mp0_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct0_mp0_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct0_mp0_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct0_mp0_STRUCT;
+
+// **** D18F2x214_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x214_dct1_mp0_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x214_dct1_mp0_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct1_mp0_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct1_mp0_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct1_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct1_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct1_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct1_mp0_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct1_mp0_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct1_mp0_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct1_mp0_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct1_mp0_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct1_mp0_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct1_mp0_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct1_mp0_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct1_mp0_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct1_mp0_STRUCT;
+
+// **** D18F2x214_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x214_dct0_mp1_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x214_dct0_mp1_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct0_mp1_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct0_mp1_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct0_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct0_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct0_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct0_mp1_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct0_mp1_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct0_mp1_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct0_mp1_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct0_mp1_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct0_mp1_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct0_mp1_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct0_mp1_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct0_mp1_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct0_mp1_STRUCT;
+
+// **** D18F2x218_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x218_dct0_mp1_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x218_dct0_mp1_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct0_mp1_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct0_mp1_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct0_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct0_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct0_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct0_mp1_Twrrd_OFFSET                         8
+#define D18F2x218_dct0_mp1_Twrrd_WIDTH                          4
+#define D18F2x218_dct0_mp1_Twrrd_MASK                           0xf00
+#define D18F2x218_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct0_mp1_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct0_mp1_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct0_mp1_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct0_mp1_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct0_mp1_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct0_mp1_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct0_mp1_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct0_mp1_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct0_mp1_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct0_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct0_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct0_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct0_mp1_STRUCT;
+
+// **** D18F2x218_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x218_dct1_mp1_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x218_dct1_mp1_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct1_mp1_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct1_mp1_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct1_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct1_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct1_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct1_mp1_Twrrd_OFFSET                         8
+#define D18F2x218_dct1_mp1_Twrrd_WIDTH                          4
+#define D18F2x218_dct1_mp1_Twrrd_MASK                           0xf00
+#define D18F2x218_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct1_mp1_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct1_mp1_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct1_mp1_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct1_mp1_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct1_mp1_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct1_mp1_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct1_mp1_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct1_mp1_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct1_mp1_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct1_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct1_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct1_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct1_mp1_STRUCT;
+
+// **** D18F2x218_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x218_dct0_mp0_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x218_dct0_mp0_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct0_mp0_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct0_mp0_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct0_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct0_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct0_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct0_mp0_Twrrd_OFFSET                         8
+#define D18F2x218_dct0_mp0_Twrrd_WIDTH                          4
+#define D18F2x218_dct0_mp0_Twrrd_MASK                           0xf00
+#define D18F2x218_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct0_mp0_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct0_mp0_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct0_mp0_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct0_mp0_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct0_mp0_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct0_mp0_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct0_mp0_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct0_mp0_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct0_mp0_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct0_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct0_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct0_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct0_mp0_STRUCT;
+
+// **** D18F2x218_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x218_dct1_mp0_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x218_dct1_mp0_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct1_mp0_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct1_mp0_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct1_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct1_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct1_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct1_mp0_Twrrd_OFFSET                         8
+#define D18F2x218_dct1_mp0_Twrrd_WIDTH                          4
+#define D18F2x218_dct1_mp0_Twrrd_MASK                           0xf00
+#define D18F2x218_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct1_mp0_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct1_mp0_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct1_mp0_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct1_mp0_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct1_mp0_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct1_mp0_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct1_mp0_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct1_mp0_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct1_mp0_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct1_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct1_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct1_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct1_mp0_STRUCT;
+
+// **** D18F2x21C_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x21C_dct1_mp1_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x21C_dct1_mp1_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct1_mp1_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct1_mp1_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct1_mp1_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct1_mp1_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct1_mp1_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct1_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct1_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct1_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct1_mp1_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct1_mp1_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct1_mp1_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct1_mp1_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct1_mp1_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct1_mp1_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct1_mp1_STRUCT;
+
+// **** D18F2x21C_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x21C_dct1_mp0_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x21C_dct1_mp0_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct1_mp0_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct1_mp0_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct1_mp0_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct1_mp0_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct1_mp0_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct1_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct1_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct1_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct1_mp0_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct1_mp0_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct1_mp0_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct1_mp0_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct1_mp0_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct1_mp0_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct1_mp0_STRUCT;
+
+// **** D18F2x21C_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x21C_dct0_mp0_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x21C_dct0_mp0_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct0_mp0_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct0_mp0_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct0_mp0_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct0_mp0_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct0_mp0_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct0_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct0_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct0_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct0_mp0_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct0_mp0_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct0_mp0_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct0_mp0_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct0_mp0_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct0_mp0_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct0_mp0_STRUCT;
+
+// **** D18F2x21C_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x21C_dct0_mp1_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x21C_dct0_mp1_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct0_mp1_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct0_mp1_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct0_mp1_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct0_mp1_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct0_mp1_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct0_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct0_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct0_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct0_mp1_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct0_mp1_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct0_mp1_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct0_mp1_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct0_mp1_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct0_mp1_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct0_mp1_STRUCT;
+
+// **** D18F2x220_dct1 Register Definition ****
+// Address
+#define D18F2x220_dct1_ADDRESS                                  0x220
+
+// Type
+#define D18F2x220_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x220_dct1_Tmrd_OFFSET                              0
+#define D18F2x220_dct1_Tmrd_WIDTH                               4
+#define D18F2x220_dct1_Tmrd_MASK                                0xf
+#define D18F2x220_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x220_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x220_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x220_dct1_Tmod_OFFSET                              8
+#define D18F2x220_dct1_Tmod_WIDTH                               5
+#define D18F2x220_dct1_Tmod_MASK                                0x1f00
+#define D18F2x220_dct1_Reserved_31_13_OFFSET                    13
+#define D18F2x220_dct1_Reserved_31_13_WIDTH                     19
+#define D18F2x220_dct1_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x220_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tmrd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                     Tmod:5 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x220_dct1_STRUCT;
+
+// **** D18F2x220_dct0 Register Definition ****
+// Address
+#define D18F2x220_dct0_ADDRESS                                  0x220
+
+// Type
+#define D18F2x220_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x220_dct0_Tmrd_OFFSET                              0
+#define D18F2x220_dct0_Tmrd_WIDTH                               4
+#define D18F2x220_dct0_Tmrd_MASK                                0xf
+#define D18F2x220_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x220_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x220_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x220_dct0_Tmod_OFFSET                              8
+#define D18F2x220_dct0_Tmod_WIDTH                               5
+#define D18F2x220_dct0_Tmod_MASK                                0x1f00
+#define D18F2x220_dct0_Reserved_31_13_OFFSET                    13
+#define D18F2x220_dct0_Reserved_31_13_WIDTH                     19
+#define D18F2x220_dct0_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x220_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tmrd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                     Tmod:5 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x220_dct0_STRUCT;
+
+// **** D18F2x224_dct0 Register Definition ****
+// Address
+#define D18F2x224_dct0_ADDRESS                                  0x224
+
+// Type
+#define D18F2x224_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x224_dct0_Tzqoper_OFFSET                           0
+#define D18F2x224_dct0_Tzqoper_WIDTH                            4
+#define D18F2x224_dct0_Tzqoper_MASK                             0xf
+#define D18F2x224_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x224_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x224_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x224_dct0_Tzqcs_OFFSET                             8
+#define D18F2x224_dct0_Tzqcs_WIDTH                              3
+#define D18F2x224_dct0_Tzqcs_MASK                               0x700
+#define D18F2x224_dct0_Reserved_31_11_OFFSET                    11
+#define D18F2x224_dct0_Reserved_31_11_WIDTH                     21
+#define D18F2x224_dct0_Reserved_31_11_MASK                      0xfffff800
+
+/// D18F2x224_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Tzqoper:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Tzqcs:3 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x224_dct0_STRUCT;
+
+// **** D18F2x224_dct1 Register Definition ****
+// Address
+#define D18F2x224_dct1_ADDRESS                                  0x224
+
+// Type
+#define D18F2x224_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x224_dct1_Tzqoper_OFFSET                           0
+#define D18F2x224_dct1_Tzqoper_WIDTH                            4
+#define D18F2x224_dct1_Tzqoper_MASK                             0xf
+#define D18F2x224_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x224_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x224_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x224_dct1_Tzqcs_OFFSET                             8
+#define D18F2x224_dct1_Tzqcs_WIDTH                              3
+#define D18F2x224_dct1_Tzqcs_MASK                               0x700
+#define D18F2x224_dct1_Reserved_31_11_OFFSET                    11
+#define D18F2x224_dct1_Reserved_31_11_WIDTH                     21
+#define D18F2x224_dct1_Reserved_31_11_MASK                      0xfffff800
+
+/// D18F2x224_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Tzqoper:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Tzqcs:3 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x224_dct1_STRUCT;
+
+// **** D18F2x228_dct1 Register Definition ****
+// Address
+#define D18F2x228_dct1_ADDRESS                                  0x228
+
+// Type
+#define D18F2x228_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x228_dct1_Tstag0_OFFSET                            0
+#define D18F2x228_dct1_Tstag0_WIDTH                             8
+#define D18F2x228_dct1_Tstag0_MASK                              0xff
+#define D18F2x228_dct1_Tstag1_OFFSET                            8
+#define D18F2x228_dct1_Tstag1_WIDTH                             8
+#define D18F2x228_dct1_Tstag1_MASK                              0xff00
+#define D18F2x228_dct1_Tstag2_OFFSET                            16
+#define D18F2x228_dct1_Tstag2_WIDTH                             8
+#define D18F2x228_dct1_Tstag2_MASK                              0xff0000
+#define D18F2x228_dct1_Tstag3_OFFSET                            24
+#define D18F2x228_dct1_Tstag3_WIDTH                             8
+#define D18F2x228_dct1_Tstag3_MASK                              0xff000000
+
+/// D18F2x228_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   Tstag0:8 ; ///<
+    UINT32                                                   Tstag1:8 ; ///<
+    UINT32                                                   Tstag2:8 ; ///<
+    UINT32                                                   Tstag3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x228_dct1_STRUCT;
+
+// **** D18F2x228_dct0 Register Definition ****
+// Address
+#define D18F2x228_dct0_ADDRESS                                  0x228
+
+// Type
+#define D18F2x228_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x228_dct0_Tstag0_OFFSET                            0
+#define D18F2x228_dct0_Tstag0_WIDTH                             8
+#define D18F2x228_dct0_Tstag0_MASK                              0xff
+#define D18F2x228_dct0_Tstag1_OFFSET                            8
+#define D18F2x228_dct0_Tstag1_WIDTH                             8
+#define D18F2x228_dct0_Tstag1_MASK                              0xff00
+#define D18F2x228_dct0_Tstag2_OFFSET                            16
+#define D18F2x228_dct0_Tstag2_WIDTH                             8
+#define D18F2x228_dct0_Tstag2_MASK                              0xff0000
+#define D18F2x228_dct0_Tstag3_OFFSET                            24
+#define D18F2x228_dct0_Tstag3_WIDTH                             8
+#define D18F2x228_dct0_Tstag3_MASK                              0xff000000
+
+/// D18F2x228_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   Tstag0:8 ; ///<
+    UINT32                                                   Tstag1:8 ; ///<
+    UINT32                                                   Tstag2:8 ; ///<
+    UINT32                                                   Tstag3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x228_dct0_STRUCT;
+
+// **** D18F2x22C_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x22C_dct1_mp1_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x22C_dct1_mp1_Twr_OFFSET                           0
+#define D18F2x22C_dct1_mp1_Twr_WIDTH                            5
+#define D18F2x22C_dct1_mp1_Twr_MASK                             0x1f
+#define D18F2x22C_dct1_mp1_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct1_mp1_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct1_mp1_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct1_mp1_STRUCT;
+
+// **** D18F2x22C_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x22C_dct1_mp0_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x22C_dct1_mp0_Twr_OFFSET                           0
+#define D18F2x22C_dct1_mp0_Twr_WIDTH                            5
+#define D18F2x22C_dct1_mp0_Twr_MASK                             0x1f
+#define D18F2x22C_dct1_mp0_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct1_mp0_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct1_mp0_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct1_mp0_STRUCT;
+
+// **** D18F2x22C_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x22C_dct0_mp0_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x22C_dct0_mp0_Twr_OFFSET                           0
+#define D18F2x22C_dct0_mp0_Twr_WIDTH                            5
+#define D18F2x22C_dct0_mp0_Twr_MASK                             0x1f
+#define D18F2x22C_dct0_mp0_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct0_mp0_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct0_mp0_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct0_mp0_STRUCT;
+
+// **** D18F2x22C_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x22C_dct0_mp1_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x22C_dct0_mp1_Twr_OFFSET                           0
+#define D18F2x22C_dct0_mp1_Twr_WIDTH                            5
+#define D18F2x22C_dct0_mp1_Twr_MASK                             0x1f
+#define D18F2x22C_dct0_mp1_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct0_mp1_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct0_mp1_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct0_mp1_STRUCT;
+
+// **** D18F2x230_dct0 Register Definition ****
+// Address
+#define D18F2x230_dct0_ADDRESS                                  0x230
+
+// Type
+#define D18F2x230_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x230_dct0_RdOdtPatCs40_OFFSET                      0
+#define D18F2x230_dct0_RdOdtPatCs40_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs40_MASK                        0xf
+#define D18F2x230_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x230_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x230_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x230_dct0_RdOdtPatCs51_OFFSET                      8
+#define D18F2x230_dct0_RdOdtPatCs51_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x230_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x230_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x230_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x230_dct0_RdOdtPatCs62_OFFSET                      16
+#define D18F2x230_dct0_RdOdtPatCs62_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x230_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x230_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x230_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x230_dct0_RdOdtPatCs73_OFFSET                      24
+#define D18F2x230_dct0_RdOdtPatCs73_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x230_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x230_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x230_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x230_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x230_dct0_STRUCT;
+
+// **** D18F2x230_dct1 Register Definition ****
+// Address
+#define D18F2x230_dct1_ADDRESS                                  0x230
+
+// Type
+#define D18F2x230_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x230_dct1_RdOdtPatCs40_OFFSET                      0
+#define D18F2x230_dct1_RdOdtPatCs40_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs40_MASK                        0xf
+#define D18F2x230_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x230_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x230_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x230_dct1_RdOdtPatCs51_OFFSET                      8
+#define D18F2x230_dct1_RdOdtPatCs51_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x230_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x230_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x230_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x230_dct1_RdOdtPatCs62_OFFSET                      16
+#define D18F2x230_dct1_RdOdtPatCs62_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x230_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x230_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x230_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x230_dct1_RdOdtPatCs73_OFFSET                      24
+#define D18F2x230_dct1_RdOdtPatCs73_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x230_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x230_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x230_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x230_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x230_dct1_STRUCT;
+
+// **** D18F2x234_dct1 Register Definition ****
+// Address
+#define D18F2x234_dct1_ADDRESS                                  0x234
+
+// Type
+#define D18F2x234_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x234_dct1_RdOdtPatCs40_OFFSET                      0
+#define D18F2x234_dct1_RdOdtPatCs40_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs40_MASK                        0xf
+#define D18F2x234_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x234_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x234_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x234_dct1_RdOdtPatCs51_OFFSET                      8
+#define D18F2x234_dct1_RdOdtPatCs51_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x234_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x234_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x234_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x234_dct1_RdOdtPatCs62_OFFSET                      16
+#define D18F2x234_dct1_RdOdtPatCs62_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x234_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x234_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x234_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x234_dct1_RdOdtPatCs73_OFFSET                      24
+#define D18F2x234_dct1_RdOdtPatCs73_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x234_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x234_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x234_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x234_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x234_dct1_STRUCT;
+
+// **** D18F2x234_dct0 Register Definition ****
+// Address
+#define D18F2x234_dct0_ADDRESS                                  0x234
+
+// Type
+#define D18F2x234_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x234_dct0_RdOdtPatCs40_OFFSET                      0
+#define D18F2x234_dct0_RdOdtPatCs40_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs40_MASK                        0xf
+#define D18F2x234_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x234_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x234_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x234_dct0_RdOdtPatCs51_OFFSET                      8
+#define D18F2x234_dct0_RdOdtPatCs51_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x234_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x234_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x234_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x234_dct0_RdOdtPatCs62_OFFSET                      16
+#define D18F2x234_dct0_RdOdtPatCs62_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x234_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x234_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x234_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x234_dct0_RdOdtPatCs73_OFFSET                      24
+#define D18F2x234_dct0_RdOdtPatCs73_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x234_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x234_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x234_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x234_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x234_dct0_STRUCT;
+
+// **** D18F2x238_dct1 Register Definition ****
+// Address
+#define D18F2x238_dct1_ADDRESS                                  0x238
+
+// Type
+#define D18F2x238_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x238_dct1_WrOdtPatCs40_OFFSET                      0
+#define D18F2x238_dct1_WrOdtPatCs40_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs40_MASK                        0xf
+#define D18F2x238_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x238_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x238_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x238_dct1_WrOdtPatCs51_OFFSET                      8
+#define D18F2x238_dct1_WrOdtPatCs51_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x238_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x238_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x238_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x238_dct1_WrOdtPatCs62_OFFSET                      16
+#define D18F2x238_dct1_WrOdtPatCs62_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x238_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x238_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x238_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x238_dct1_WrOdtPatCs73_OFFSET                      24
+#define D18F2x238_dct1_WrOdtPatCs73_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x238_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x238_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x238_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x238_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x238_dct1_STRUCT;
+
+// **** D18F2x238_dct0 Register Definition ****
+// Address
+#define D18F2x238_dct0_ADDRESS                                  0x238
+
+// Type
+#define D18F2x238_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x238_dct0_WrOdtPatCs40_OFFSET                      0
+#define D18F2x238_dct0_WrOdtPatCs40_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs40_MASK                        0xf
+#define D18F2x238_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x238_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x238_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x238_dct0_WrOdtPatCs51_OFFSET                      8
+#define D18F2x238_dct0_WrOdtPatCs51_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x238_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x238_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x238_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x238_dct0_WrOdtPatCs62_OFFSET                      16
+#define D18F2x238_dct0_WrOdtPatCs62_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x238_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x238_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x238_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x238_dct0_WrOdtPatCs73_OFFSET                      24
+#define D18F2x238_dct0_WrOdtPatCs73_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x238_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x238_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x238_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x238_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x238_dct0_STRUCT;
+
+// **** D18F2x23C_dct0 Register Definition ****
+// Address
+#define D18F2x23C_dct0_ADDRESS                                  0x23c
+
+// Type
+#define D18F2x23C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x23C_dct0_WrOdtPatCs40_OFFSET                      0
+#define D18F2x23C_dct0_WrOdtPatCs40_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs40_MASK                        0xf
+#define D18F2x23C_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x23C_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x23C_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x23C_dct0_WrOdtPatCs51_OFFSET                      8
+#define D18F2x23C_dct0_WrOdtPatCs51_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x23C_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x23C_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x23C_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x23C_dct0_WrOdtPatCs62_OFFSET                      16
+#define D18F2x23C_dct0_WrOdtPatCs62_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x23C_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x23C_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x23C_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x23C_dct0_WrOdtPatCs73_OFFSET                      24
+#define D18F2x23C_dct0_WrOdtPatCs73_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x23C_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x23C_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x23C_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x23C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x23C_dct0_STRUCT;
+
+// **** D18F2x23C_dct1 Register Definition ****
+// Address
+#define D18F2x23C_dct1_ADDRESS                                  0x23c
+
+// Type
+#define D18F2x23C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x23C_dct1_WrOdtPatCs40_OFFSET                      0
+#define D18F2x23C_dct1_WrOdtPatCs40_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs40_MASK                        0xf
+#define D18F2x23C_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x23C_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x23C_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x23C_dct1_WrOdtPatCs51_OFFSET                      8
+#define D18F2x23C_dct1_WrOdtPatCs51_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x23C_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x23C_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x23C_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x23C_dct1_WrOdtPatCs62_OFFSET                      16
+#define D18F2x23C_dct1_WrOdtPatCs62_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x23C_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x23C_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x23C_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x23C_dct1_WrOdtPatCs73_OFFSET                      24
+#define D18F2x23C_dct1_WrOdtPatCs73_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x23C_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x23C_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x23C_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x23C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x23C_dct1_STRUCT;
+
+// **** D18F2x240_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x240_dct0_mp1_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct0_mp1_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct0_mp1_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp1_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct0_mp1_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct0_mp1_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct0_mp1_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct0_mp1_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct0_mp1_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct0_mp1_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct0_mp1_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct0_mp1_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp1_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct0_mp1_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct0_mp1_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct0_mp1_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct0_mp1_STRUCT;
+
+// **** D18F2x240_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x240_dct1_mp0_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct1_mp0_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct1_mp0_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp0_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct1_mp0_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct1_mp0_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct1_mp0_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct1_mp0_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct1_mp0_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct1_mp0_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct1_mp0_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct1_mp0_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp0_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct1_mp0_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct1_mp0_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct1_mp0_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct1_mp0_STRUCT;
+
+// **** D18F2x240_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x240_dct0_mp0_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct0_mp0_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct0_mp0_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp0_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct0_mp0_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct0_mp0_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct0_mp0_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct0_mp0_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct0_mp0_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct0_mp0_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct0_mp0_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct0_mp0_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp0_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct0_mp0_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct0_mp0_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct0_mp0_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct0_mp0_STRUCT;
+
+// **** D18F2x240_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x240_dct1_mp1_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct1_mp1_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct1_mp1_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp1_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct1_mp1_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct1_mp1_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct1_mp1_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct1_mp1_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct1_mp1_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct1_mp1_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct1_mp1_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct1_mp1_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp1_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct1_mp1_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct1_mp1_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct1_mp1_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct1_mp1_STRUCT;
+
+// **** D18F2x244_dct1 Register Definition ****
+// Address
+#define D18F2x244_dct1_ADDRESS                                  0x244
+
+// Type
+#define D18F2x244_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x244_dct1_PrtlChPDDynDly_OFFSET                    0
+#define D18F2x244_dct1_PrtlChPDDynDly_WIDTH                     4
+#define D18F2x244_dct1_PrtlChPDDynDly_MASK                      0xf
+#define D18F2x244_dct1_Reserved_31_4_OFFSET                     4
+#define D18F2x244_dct1_Reserved_31_4_WIDTH                      28
+#define D18F2x244_dct1_Reserved_31_4_MASK                       0xfffffff0
+
+/// D18F2x244_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PrtlChPDDynDly:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x244_dct1_STRUCT;
+
+// **** D18F2x244_dct0 Register Definition ****
+// Address
+#define D18F2x244_dct0_ADDRESS                                  0x244
+
+// Type
+#define D18F2x244_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x244_dct0_PrtlChPDDynDly_OFFSET                    0
+#define D18F2x244_dct0_PrtlChPDDynDly_WIDTH                     4
+#define D18F2x244_dct0_PrtlChPDDynDly_MASK                      0xf
+#define D18F2x244_dct0_Reserved_31_4_OFFSET                     4
+#define D18F2x244_dct0_Reserved_31_4_WIDTH                      28
+#define D18F2x244_dct0_Reserved_31_4_MASK                       0xfffffff0
+
+/// D18F2x244_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PrtlChPDDynDly:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x244_dct0_STRUCT;
+
+// **** D18F2x248_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x248_dct1_mp1_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x248_dct1_mp1_Txp_OFFSET                           0
+#define D18F2x248_dct1_mp1_Txp_WIDTH                            4
+#define D18F2x248_dct1_mp1_Txp_MASK                             0xf
+#define D18F2x248_dct1_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct1_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct1_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct1_mp1_Txpdll_OFFSET                        8
+#define D18F2x248_dct1_mp1_Txpdll_WIDTH                         5
+#define D18F2x248_dct1_mp1_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct1_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct1_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct1_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct1_mp1_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct1_mp1_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct1_mp1_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct1_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct1_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct1_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct1_mp1_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct1_mp1_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct1_mp1_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct1_mp1_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct1_mp1_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct1_mp1_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct1_mp1_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct1_mp1_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct1_mp1_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct1_mp1_STRUCT;
+
+// **** D18F2x248_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x248_dct0_mp1_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x248_dct0_mp1_Txp_OFFSET                           0
+#define D18F2x248_dct0_mp1_Txp_WIDTH                            4
+#define D18F2x248_dct0_mp1_Txp_MASK                             0xf
+#define D18F2x248_dct0_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct0_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct0_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct0_mp1_Txpdll_OFFSET                        8
+#define D18F2x248_dct0_mp1_Txpdll_WIDTH                         5
+#define D18F2x248_dct0_mp1_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct0_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct0_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct0_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct0_mp1_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct0_mp1_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct0_mp1_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct0_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct0_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct0_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct0_mp1_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct0_mp1_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct0_mp1_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct0_mp1_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct0_mp1_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct0_mp1_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct0_mp1_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct0_mp1_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct0_mp1_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct0_mp1_STRUCT;
+
+// **** D18F2x248_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x248_dct1_mp0_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x248_dct1_mp0_Txp_OFFSET                           0
+#define D18F2x248_dct1_mp0_Txp_WIDTH                            4
+#define D18F2x248_dct1_mp0_Txp_MASK                             0xf
+#define D18F2x248_dct1_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct1_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct1_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct1_mp0_Txpdll_OFFSET                        8
+#define D18F2x248_dct1_mp0_Txpdll_WIDTH                         5
+#define D18F2x248_dct1_mp0_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct1_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct1_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct1_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct1_mp0_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct1_mp0_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct1_mp0_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct1_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct1_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct1_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct1_mp0_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct1_mp0_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct1_mp0_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct1_mp0_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct1_mp0_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct1_mp0_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct1_mp0_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct1_mp0_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct1_mp0_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct1_mp0_STRUCT;
+
+// **** D18F2x248_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x248_dct0_mp0_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x248_dct0_mp0_Txp_OFFSET                           0
+#define D18F2x248_dct0_mp0_Txp_WIDTH                            4
+#define D18F2x248_dct0_mp0_Txp_MASK                             0xf
+#define D18F2x248_dct0_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct0_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct0_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct0_mp0_Txpdll_OFFSET                        8
+#define D18F2x248_dct0_mp0_Txpdll_WIDTH                         5
+#define D18F2x248_dct0_mp0_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct0_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct0_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct0_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct0_mp0_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct0_mp0_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct0_mp0_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct0_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct0_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct0_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct0_mp0_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct0_mp0_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct0_mp0_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct0_mp0_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct0_mp0_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct0_mp0_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct0_mp0_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct0_mp0_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct0_mp0_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct0_mp0_STRUCT;
+
+// **** D18F2x24C_dct0 Register Definition ****
+// Address
+#define D18F2x24C_dct0_ADDRESS                                  0x24c
+
+// Type
+#define D18F2x24C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x24C_dct0_Tpd_OFFSET                               0
+#define D18F2x24C_dct0_Tpd_WIDTH                                4
+#define D18F2x24C_dct0_Tpd_MASK                                 0xf
+#define D18F2x24C_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x24C_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x24C_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x24C_dct0_Tckesr_OFFSET                            8
+#define D18F2x24C_dct0_Tckesr_WIDTH                             6
+#define D18F2x24C_dct0_Tckesr_MASK                              0x3f00
+#define D18F2x24C_dct0_Reserved_15_14_OFFSET                    14
+#define D18F2x24C_dct0_Reserved_15_14_WIDTH                     2
+#define D18F2x24C_dct0_Reserved_15_14_MASK                      0xc000
+#define D18F2x24C_dct0_Tcksre_OFFSET                            16
+#define D18F2x24C_dct0_Tcksre_WIDTH                             6
+#define D18F2x24C_dct0_Tcksre_MASK                              0x3f0000
+#define D18F2x24C_dct0_Reserved_23_22_OFFSET                    22
+#define D18F2x24C_dct0_Reserved_23_22_WIDTH                     2
+#define D18F2x24C_dct0_Reserved_23_22_MASK                      0xc00000
+#define D18F2x24C_dct0_Tcksrx_OFFSET                            24
+#define D18F2x24C_dct0_Tcksrx_WIDTH                             6
+#define D18F2x24C_dct0_Tcksrx_MASK                              0x3f000000
+#define D18F2x24C_dct0_Reserved_31_30_OFFSET                    30
+#define D18F2x24C_dct0_Reserved_31_30_WIDTH                     2
+#define D18F2x24C_dct0_Reserved_31_30_MASK                      0xc0000000
+
+/// D18F2x24C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tpd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Tckesr:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                                   Tcksre:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                   Tcksrx:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x24C_dct0_STRUCT;
+
+// **** D18F2x24C_dct1 Register Definition ****
+// Address
+#define D18F2x24C_dct1_ADDRESS                                  0x24c
+
+// Type
+#define D18F2x24C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x24C_dct1_Tpd_OFFSET                               0
+#define D18F2x24C_dct1_Tpd_WIDTH                                4
+#define D18F2x24C_dct1_Tpd_MASK                                 0xf
+#define D18F2x24C_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x24C_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x24C_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x24C_dct1_Tckesr_OFFSET                            8
+#define D18F2x24C_dct1_Tckesr_WIDTH                             6
+#define D18F2x24C_dct1_Tckesr_MASK                              0x3f00
+#define D18F2x24C_dct1_Reserved_15_14_OFFSET                    14
+#define D18F2x24C_dct1_Reserved_15_14_WIDTH                     2
+#define D18F2x24C_dct1_Reserved_15_14_MASK                      0xc000
+#define D18F2x24C_dct1_Tcksre_OFFSET                            16
+#define D18F2x24C_dct1_Tcksre_WIDTH                             6
+#define D18F2x24C_dct1_Tcksre_MASK                              0x3f0000
+#define D18F2x24C_dct1_Reserved_23_22_OFFSET                    22
+#define D18F2x24C_dct1_Reserved_23_22_WIDTH                     2
+#define D18F2x24C_dct1_Reserved_23_22_MASK                      0xc00000
+#define D18F2x24C_dct1_Tcksrx_OFFSET                            24
+#define D18F2x24C_dct1_Tcksrx_WIDTH                             6
+#define D18F2x24C_dct1_Tcksrx_MASK                              0x3f000000
+#define D18F2x24C_dct1_Reserved_31_30_OFFSET                    30
+#define D18F2x24C_dct1_Reserved_31_30_WIDTH                     2
+#define D18F2x24C_dct1_Reserved_31_30_MASK                      0xc0000000
+
+/// D18F2x24C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tpd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Tckesr:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                                   Tcksre:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                   Tcksrx:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x24C_dct1_STRUCT;
+
+// **** D18F2x250_dct0 Register Definition ****
+// Address
+#define D18F2x250_dct0_ADDRESS                                  0x250
+
+// Type
+#define D18F2x250_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x250_dct0_Reserved_1_0_OFFSET                      0
+#define D18F2x250_dct0_Reserved_1_0_WIDTH                       2
+#define D18F2x250_dct0_Reserved_1_0_MASK                        0x3
+#define D18F2x250_dct0_CmdTestEnable_OFFSET                     2
+#define D18F2x250_dct0_CmdTestEnable_WIDTH                      1
+#define D18F2x250_dct0_CmdTestEnable_MASK                       0x4
+#define D18F2x250_dct0_ResetAllErr_OFFSET                       3
+#define D18F2x250_dct0_ResetAllErr_WIDTH                        1
+#define D18F2x250_dct0_ResetAllErr_MASK                         0x8
+#define D18F2x250_dct0_StopOnErr_OFFSET                         4
+#define D18F2x250_dct0_StopOnErr_WIDTH                          1
+#define D18F2x250_dct0_StopOnErr_MASK                           0x10
+#define D18F2x250_dct0_CmdType_OFFSET                           5
+#define D18F2x250_dct0_CmdType_WIDTH                            3
+#define D18F2x250_dct0_CmdType_MASK                             0xe0
+#define D18F2x250_dct0_CmdTgt_OFFSET                            8
+#define D18F2x250_dct0_CmdTgt_WIDTH                             2
+#define D18F2x250_dct0_CmdTgt_MASK                              0x300
+#define D18F2x250_dct0_TestStatus_OFFSET                        10
+#define D18F2x250_dct0_TestStatus_WIDTH                         1
+#define D18F2x250_dct0_TestStatus_MASK                          0x400
+#define D18F2x250_dct0_SendCmd_OFFSET                           11
+#define D18F2x250_dct0_SendCmd_WIDTH                            1
+#define D18F2x250_dct0_SendCmd_MASK                             0x800
+#define D18F2x250_dct0_CmdSendInProg_OFFSET                     12
+#define D18F2x250_dct0_CmdSendInProg_WIDTH                      1
+#define D18F2x250_dct0_CmdSendInProg_MASK                       0x1000
+#define D18F2x250_dct0_Reserved_31_13_OFFSET                    13
+#define D18F2x250_dct0_Reserved_31_13_WIDTH                     19
+#define D18F2x250_dct0_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x250_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CmdTestEnable:1 ; ///<
+    UINT32                                              ResetAllErr:1 ; ///<
+    UINT32                                                StopOnErr:1 ; ///<
+    UINT32                                                  CmdType:3 ; ///<
+    UINT32                                                   CmdTgt:2 ; ///<
+    UINT32                                               TestStatus:1 ; ///<
+    UINT32                                                  SendCmd:1 ; ///<
+    UINT32                                            CmdSendInProg:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x250_dct0_STRUCT;
+
+// **** D18F2x250_dct1 Register Definition ****
+// Address
+#define D18F2x250_dct1_ADDRESS                                  0x250
+
+// Type
+#define D18F2x250_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x250_dct1_Reserved_1_0_OFFSET                      0
+#define D18F2x250_dct1_Reserved_1_0_WIDTH                       2
+#define D18F2x250_dct1_Reserved_1_0_MASK                        0x3
+#define D18F2x250_dct1_CmdTestEnable_OFFSET                     2
+#define D18F2x250_dct1_CmdTestEnable_WIDTH                      1
+#define D18F2x250_dct1_CmdTestEnable_MASK                       0x4
+#define D18F2x250_dct1_ResetAllErr_OFFSET                       3
+#define D18F2x250_dct1_ResetAllErr_WIDTH                        1
+#define D18F2x250_dct1_ResetAllErr_MASK                         0x8
+#define D18F2x250_dct1_StopOnErr_OFFSET                         4
+#define D18F2x250_dct1_StopOnErr_WIDTH                          1
+#define D18F2x250_dct1_StopOnErr_MASK                           0x10
+#define D18F2x250_dct1_CmdType_OFFSET                           5
+#define D18F2x250_dct1_CmdType_WIDTH                            3
+#define D18F2x250_dct1_CmdType_MASK                             0xe0
+#define D18F2x250_dct1_CmdTgt_OFFSET                            8
+#define D18F2x250_dct1_CmdTgt_WIDTH                             2
+#define D18F2x250_dct1_CmdTgt_MASK                              0x300
+#define D18F2x250_dct1_TestStatus_OFFSET                        10
+#define D18F2x250_dct1_TestStatus_WIDTH                         1
+#define D18F2x250_dct1_TestStatus_MASK                          0x400
+#define D18F2x250_dct1_SendCmd_OFFSET                           11
+#define D18F2x250_dct1_SendCmd_WIDTH                            1
+#define D18F2x250_dct1_SendCmd_MASK                             0x800
+#define D18F2x250_dct1_CmdSendInProg_OFFSET                     12
+#define D18F2x250_dct1_CmdSendInProg_WIDTH                      1
+#define D18F2x250_dct1_CmdSendInProg_MASK                       0x1000
+#define D18F2x250_dct1_Reserved_31_13_OFFSET                    13
+#define D18F2x250_dct1_Reserved_31_13_WIDTH                     19
+#define D18F2x250_dct1_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x250_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CmdTestEnable:1 ; ///<
+    UINT32                                              ResetAllErr:1 ; ///<
+    UINT32                                                StopOnErr:1 ; ///<
+    UINT32                                                  CmdType:3 ; ///<
+    UINT32                                                   CmdTgt:2 ; ///<
+    UINT32                                               TestStatus:1 ; ///<
+    UINT32                                                  SendCmd:1 ; ///<
+    UINT32                                            CmdSendInProg:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x250_dct1_STRUCT;
+
+// **** D18F2x254_dct0 Register Definition ****
+// Address
+#define D18F2x254_dct0_ADDRESS                                  0x254
+
+// Type
+#define D18F2x254_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x254_dct0_TgtAddress_9_0__OFFSET                   0
+#define D18F2x254_dct0_TgtAddress_9_0__WIDTH                    10
+#define D18F2x254_dct0_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x254_dct0_Reserved_20_10_OFFSET                    10
+#define D18F2x254_dct0_Reserved_20_10_WIDTH                     11
+#define D18F2x254_dct0_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x254_dct0_TgtBank_OFFSET                           21
+#define D18F2x254_dct0_TgtBank_WIDTH                            3
+#define D18F2x254_dct0_TgtBank_MASK                             0xe00000
+#define D18F2x254_dct0_TgtChipSelect_OFFSET                     24
+#define D18F2x254_dct0_TgtChipSelect_WIDTH                      3
+#define D18F2x254_dct0_TgtChipSelect_MASK                       0x7000000
+#define D18F2x254_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x254_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x254_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x254_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x254_dct0_STRUCT;
+
+// **** D18F2x254_dct1 Register Definition ****
+// Address
+#define D18F2x254_dct1_ADDRESS                                  0x254
+
+// Type
+#define D18F2x254_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x254_dct1_TgtAddress_9_0__OFFSET                   0
+#define D18F2x254_dct1_TgtAddress_9_0__WIDTH                    10
+#define D18F2x254_dct1_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x254_dct1_Reserved_20_10_OFFSET                    10
+#define D18F2x254_dct1_Reserved_20_10_WIDTH                     11
+#define D18F2x254_dct1_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x254_dct1_TgtBank_OFFSET                           21
+#define D18F2x254_dct1_TgtBank_WIDTH                            3
+#define D18F2x254_dct1_TgtBank_MASK                             0xe00000
+#define D18F2x254_dct1_TgtChipSelect_OFFSET                     24
+#define D18F2x254_dct1_TgtChipSelect_WIDTH                      3
+#define D18F2x254_dct1_TgtChipSelect_MASK                       0x7000000
+#define D18F2x254_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x254_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x254_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x254_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x254_dct1_STRUCT;
+
+// **** D18F2x258_dct0 Register Definition ****
+// Address
+#define D18F2x258_dct0_ADDRESS                                  0x258
+
+// Type
+#define D18F2x258_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x258_dct0_TgtAddress_9_0__OFFSET                   0
+#define D18F2x258_dct0_TgtAddress_9_0__WIDTH                    10
+#define D18F2x258_dct0_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x258_dct0_Reserved_20_10_OFFSET                    10
+#define D18F2x258_dct0_Reserved_20_10_WIDTH                     11
+#define D18F2x258_dct0_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x258_dct0_TgtBank_OFFSET                           21
+#define D18F2x258_dct0_TgtBank_WIDTH                            3
+#define D18F2x258_dct0_TgtBank_MASK                             0xe00000
+#define D18F2x258_dct0_TgtChipSelect_OFFSET                     24
+#define D18F2x258_dct0_TgtChipSelect_WIDTH                      3
+#define D18F2x258_dct0_TgtChipSelect_MASK                       0x7000000
+#define D18F2x258_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x258_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x258_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x258_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x258_dct0_STRUCT;
+
+// **** D18F2x258_dct1 Register Definition ****
+// Address
+#define D18F2x258_dct1_ADDRESS                                  0x258
+
+// Type
+#define D18F2x258_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x258_dct1_TgtAddress_9_0__OFFSET                   0
+#define D18F2x258_dct1_TgtAddress_9_0__WIDTH                    10
+#define D18F2x258_dct1_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x258_dct1_Reserved_20_10_OFFSET                    10
+#define D18F2x258_dct1_Reserved_20_10_WIDTH                     11
+#define D18F2x258_dct1_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x258_dct1_TgtBank_OFFSET                           21
+#define D18F2x258_dct1_TgtBank_WIDTH                            3
+#define D18F2x258_dct1_TgtBank_MASK                             0xe00000
+#define D18F2x258_dct1_TgtChipSelect_OFFSET                     24
+#define D18F2x258_dct1_TgtChipSelect_WIDTH                      3
+#define D18F2x258_dct1_TgtChipSelect_MASK                       0x7000000
+#define D18F2x258_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x258_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x258_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x258_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x258_dct1_STRUCT;
+
+
+// **** D18F2x260_dct1 Register Definition ****
+// Address
+#define D18F2x260_dct1_ADDRESS                                  0x260
+
+// Type
+#define D18F2x260_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x260_dct1_CmdCount_OFFSET                          0
+#define D18F2x260_dct1_CmdCount_WIDTH                           21
+#define D18F2x260_dct1_CmdCount_MASK                            0x1fffff
+#define D18F2x260_dct1_Reserved_31_21_OFFSET                    21
+#define D18F2x260_dct1_Reserved_31_21_WIDTH                     11
+#define D18F2x260_dct1_Reserved_31_21_MASK                      0xffe00000
+
+/// D18F2x260_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CmdCount:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x260_dct1_STRUCT;
+
+// **** D18F2x260_dct0 Register Definition ****
+// Address
+#define D18F2x260_dct0_ADDRESS                                  0x260
+
+// Type
+#define D18F2x260_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x260_dct0_CmdCount_OFFSET                          0
+#define D18F2x260_dct0_CmdCount_WIDTH                           21
+#define D18F2x260_dct0_CmdCount_MASK                            0x1fffff
+#define D18F2x260_dct0_Reserved_31_21_OFFSET                    21
+#define D18F2x260_dct0_Reserved_31_21_WIDTH                     11
+#define D18F2x260_dct0_Reserved_31_21_MASK                      0xffe00000
+
+/// D18F2x260_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CmdCount:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x260_dct0_STRUCT;
+
+// **** D18F2x264_dct1 Register Definition ****
+// Address
+#define D18F2x264_dct1_ADDRESS                                  0x264
+
+// Type
+#define D18F2x264_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x264_dct1_ErrCnt_OFFSET                            0
+#define D18F2x264_dct1_ErrCnt_WIDTH                             25
+#define D18F2x264_dct1_ErrCnt_MASK                              0x1ffffff
+#define D18F2x264_dct1_ErrDqNum_OFFSET                          25
+#define D18F2x264_dct1_ErrDqNum_WIDTH                           7
+#define D18F2x264_dct1_ErrDqNum_MASK                            0xfe000000
+
+/// D18F2x264_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   ErrCnt:25; ///<
+    UINT32                                                 ErrDqNum:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x264_dct1_STRUCT;
+
+// **** D18F2x264_dct0 Register Definition ****
+// Address
+#define D18F2x264_dct0_ADDRESS                                  0x264
+
+// Type
+#define D18F2x264_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x264_dct0_ErrCnt_OFFSET                            0
+#define D18F2x264_dct0_ErrCnt_WIDTH                             25
+#define D18F2x264_dct0_ErrCnt_MASK                              0x1ffffff
+#define D18F2x264_dct0_ErrDqNum_OFFSET                          25
+#define D18F2x264_dct0_ErrDqNum_WIDTH                           7
+#define D18F2x264_dct0_ErrDqNum_MASK                            0xfe000000
+
+/// D18F2x264_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   ErrCnt:25; ///<
+    UINT32                                                 ErrDqNum:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x264_dct0_STRUCT;
+
+// **** D18F2x268_dct1 Register Definition ****
+// Address
+#define D18F2x268_dct1_ADDRESS                                  0x268
+
+// Type
+#define D18F2x268_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x268_dct1_NibbleErrSts_OFFSET                      0
+#define D18F2x268_dct1_NibbleErrSts_WIDTH                       18
+#define D18F2x268_dct1_NibbleErrSts_MASK                        0x3ffff
+#define D18F2x268_dct1_Reserved_31_18_OFFSET                    18
+#define D18F2x268_dct1_Reserved_31_18_WIDTH                     14
+#define D18F2x268_dct1_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x268_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NibbleErrSts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x268_dct1_STRUCT;
+
+// **** D18F2x268_dct0 Register Definition ****
+// Address
+#define D18F2x268_dct0_ADDRESS                                  0x268
+
+// Type
+#define D18F2x268_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x268_dct0_NibbleErrSts_OFFSET                      0
+#define D18F2x268_dct0_NibbleErrSts_WIDTH                       18
+#define D18F2x268_dct0_NibbleErrSts_MASK                        0x3ffff
+#define D18F2x268_dct0_Reserved_31_18_OFFSET                    18
+#define D18F2x268_dct0_Reserved_31_18_WIDTH                     14
+#define D18F2x268_dct0_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x268_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NibbleErrSts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x268_dct0_STRUCT;
+
+// **** D18F2x26C_dct1 Register Definition ****
+// Address
+#define D18F2x26C_dct1_ADDRESS                                  0x26c
+
+// Type
+#define D18F2x26C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x26C_dct1_NibbleErr180Sts_OFFSET                   0
+#define D18F2x26C_dct1_NibbleErr180Sts_WIDTH                    18
+#define D18F2x26C_dct1_NibbleErr180Sts_MASK                     0x3ffff
+#define D18F2x26C_dct1_Reserved_31_18_OFFSET                    18
+#define D18F2x26C_dct1_Reserved_31_18_WIDTH                     14
+#define D18F2x26C_dct1_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x26C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          NibbleErr180Sts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x26C_dct1_STRUCT;
+
+// **** D18F2x26C_dct0 Register Definition ****
+// Address
+#define D18F2x26C_dct0_ADDRESS                                  0x26c
+
+// Type
+#define D18F2x26C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x26C_dct0_NibbleErr180Sts_OFFSET                   0
+#define D18F2x26C_dct0_NibbleErr180Sts_WIDTH                    18
+#define D18F2x26C_dct0_NibbleErr180Sts_MASK                     0x3ffff
+#define D18F2x26C_dct0_Reserved_31_18_OFFSET                    18
+#define D18F2x26C_dct0_Reserved_31_18_WIDTH                     14
+#define D18F2x26C_dct0_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x26C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          NibbleErr180Sts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x26C_dct0_STRUCT;
+
+// **** D18F2x270_dct0 Register Definition ****
+// Address
+#define D18F2x270_dct0_ADDRESS                                  0x270
+
+// Type
+#define D18F2x270_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x270_dct0_DataPrbsSeed_OFFSET                      0
+#define D18F2x270_dct0_DataPrbsSeed_WIDTH                       19
+#define D18F2x270_dct0_DataPrbsSeed_MASK                        0x7ffff
+#define D18F2x270_dct0_Reserved_23_19_OFFSET                    19
+#define D18F2x270_dct0_Reserved_23_19_WIDTH                     5
+#define D18F2x270_dct0_Reserved_23_19_MASK                      0xf80000
+#define D18F2x270_dct0_Reserved_30_24_OFFSET                    24
+#define D18F2x270_dct0_Reserved_30_24_WIDTH                     7
+#define D18F2x270_dct0_Reserved_30_24_MASK                      0x7f000000
+#define D18F2x270_dct0_Reserved_31_31_OFFSET                    31
+#define D18F2x270_dct0_Reserved_31_31_WIDTH                     1
+#define D18F2x270_dct0_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x270_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DataPrbsSeed:19; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                           Reserved_30_24:7 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x270_dct0_STRUCT;
+
+// **** D18F2x270_dct1 Register Definition ****
+// Address
+#define D18F2x270_dct1_ADDRESS                                  0x270
+
+// Type
+#define D18F2x270_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x270_dct1_DataPrbsSeed_OFFSET                      0
+#define D18F2x270_dct1_DataPrbsSeed_WIDTH                       19
+#define D18F2x270_dct1_DataPrbsSeed_MASK                        0x7ffff
+#define D18F2x270_dct1_Reserved_23_19_OFFSET                    19
+#define D18F2x270_dct1_Reserved_23_19_WIDTH                     5
+#define D18F2x270_dct1_Reserved_23_19_MASK                      0xf80000
+#define D18F2x270_dct1_Reserved_30_24_OFFSET                    24
+#define D18F2x270_dct1_Reserved_30_24_WIDTH                     7
+#define D18F2x270_dct1_Reserved_30_24_MASK                      0x7f000000
+#define D18F2x270_dct1_Reserved_31_31_OFFSET                    31
+#define D18F2x270_dct1_Reserved_31_31_WIDTH                     1
+#define D18F2x270_dct1_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x270_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DataPrbsSeed:19; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                           Reserved_30_24:7 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x270_dct1_STRUCT;
+
+// **** D18F2x274_dct0 Register Definition ****
+// Address
+#define D18F2x274_dct0_ADDRESS                                  0x274
+
+// Type
+#define D18F2x274_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x274_dct0_DQMask_31_0__OFFSET                      0
+#define D18F2x274_dct0_DQMask_31_0__WIDTH                       32
+#define D18F2x274_dct0_DQMask_31_0__MASK                        0xffffffff
+
+/// D18F2x274_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQMask_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x274_dct0_STRUCT;
+
+// **** D18F2x274_dct1 Register Definition ****
+// Address
+#define D18F2x274_dct1_ADDRESS                                  0x274
+
+// Type
+#define D18F2x274_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x274_dct1_DQMask_31_0__OFFSET                      0
+#define D18F2x274_dct1_DQMask_31_0__WIDTH                       32
+#define D18F2x274_dct1_DQMask_31_0__MASK                        0xffffffff
+
+/// D18F2x274_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQMask_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x274_dct1_STRUCT;
+
+// **** D18F2x278_dct0 Register Definition ****
+// Address
+#define D18F2x278_dct0_ADDRESS                                  0x278
+
+// Type
+#define D18F2x278_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x278_dct0_DQMask_63_32__OFFSET                     0
+#define D18F2x278_dct0_DQMask_63_32__WIDTH                      32
+#define D18F2x278_dct0_DQMask_63_32__MASK                       0xffffffff
+
+/// D18F2x278_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DQMask_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x278_dct0_STRUCT;
+
+// **** D18F2x278_dct1 Register Definition ****
+// Address
+#define D18F2x278_dct1_ADDRESS                                  0x278
+
+// Type
+#define D18F2x278_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x278_dct1_DQMask_63_32__OFFSET                     0
+#define D18F2x278_dct1_DQMask_63_32__WIDTH                      32
+#define D18F2x278_dct1_DQMask_63_32__MASK                       0xffffffff
+
+/// D18F2x278_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DQMask_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x278_dct1_STRUCT;
+
+// **** D18F2x28C_dct0 Register Definition ****
+// Address
+#define D18F2x28C_dct0_ADDRESS                                  0x28c
+
+// Type
+#define D18F2x28C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x28C_dct0_CmdAddress_17_0__OFFSET                  0
+#define D18F2x28C_dct0_CmdAddress_17_0__WIDTH                   18
+#define D18F2x28C_dct0_CmdAddress_17_0__MASK                    0x3ffff
+#define D18F2x28C_dct0_Reserved_18_18_OFFSET                    18
+#define D18F2x28C_dct0_Reserved_18_18_WIDTH                     1
+#define D18F2x28C_dct0_Reserved_18_18_MASK                      0x40000
+#define D18F2x28C_dct0_CmdBank_2_0__OFFSET                      19
+#define D18F2x28C_dct0_CmdBank_2_0__WIDTH                       3
+#define D18F2x28C_dct0_CmdBank_2_0__MASK                        0x380000
+#define D18F2x28C_dct0_CmdChipSelect_OFFSET                     22
+#define D18F2x28C_dct0_CmdChipSelect_WIDTH                      8
+#define D18F2x28C_dct0_CmdChipSelect_MASK                       0x3fc00000
+#define D18F2x28C_dct0_SendPchgCmd_OFFSET                       30
+#define D18F2x28C_dct0_SendPchgCmd_WIDTH                        1
+#define D18F2x28C_dct0_SendPchgCmd_MASK                         0x40000000
+#define D18F2x28C_dct0_SendActCmd_OFFSET                        31
+#define D18F2x28C_dct0_SendActCmd_WIDTH                         1
+#define D18F2x28C_dct0_SendActCmd_MASK                          0x80000000
+
+/// D18F2x28C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CmdAddress_17_0_:18; ///<
+    UINT32                                           Reserved_18_18:1 ; ///<
+    UINT32                                             CmdBank_2_0_:3 ; ///<
+    UINT32                                            CmdChipSelect:8 ; ///<
+    UINT32                                              SendPchgCmd:1 ; ///<
+    UINT32                                               SendActCmd:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x28C_dct0_STRUCT;
+
+// **** D18F2x28C_dct1 Register Definition ****
+// Address
+#define D18F2x28C_dct1_ADDRESS                                  0x28c
+
+// Type
+#define D18F2x28C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x28C_dct1_CmdAddress_17_0__OFFSET                  0
+#define D18F2x28C_dct1_CmdAddress_17_0__WIDTH                   18
+#define D18F2x28C_dct1_CmdAddress_17_0__MASK                    0x3ffff
+#define D18F2x28C_dct1_Reserved_18_18_OFFSET                    18
+#define D18F2x28C_dct1_Reserved_18_18_WIDTH                     1
+#define D18F2x28C_dct1_Reserved_18_18_MASK                      0x40000
+#define D18F2x28C_dct1_CmdBank_2_0__OFFSET                      19
+#define D18F2x28C_dct1_CmdBank_2_0__WIDTH                       3
+#define D18F2x28C_dct1_CmdBank_2_0__MASK                        0x380000
+#define D18F2x28C_dct1_CmdChipSelect_OFFSET                     22
+#define D18F2x28C_dct1_CmdChipSelect_WIDTH                      8
+#define D18F2x28C_dct1_CmdChipSelect_MASK                       0x3fc00000
+#define D18F2x28C_dct1_SendPchgCmd_OFFSET                       30
+#define D18F2x28C_dct1_SendPchgCmd_WIDTH                        1
+#define D18F2x28C_dct1_SendPchgCmd_MASK                         0x40000000
+#define D18F2x28C_dct1_SendActCmd_OFFSET                        31
+#define D18F2x28C_dct1_SendActCmd_WIDTH                         1
+#define D18F2x28C_dct1_SendActCmd_MASK                          0x80000000
+
+/// D18F2x28C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CmdAddress_17_0_:18; ///<
+    UINT32                                           Reserved_18_18:1 ; ///<
+    UINT32                                             CmdBank_2_0_:3 ; ///<
+    UINT32                                            CmdChipSelect:8 ; ///<
+    UINT32                                              SendPchgCmd:1 ; ///<
+    UINT32                                               SendActCmd:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x28C_dct1_STRUCT;
+
+// **** D18F2x290_dct1 Register Definition ****
+// Address
+#define D18F2x290_dct1_ADDRESS                                  0x290
+
+// Type
+#define D18F2x290_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x290_dct1_ErrCmdNum_OFFSET                         0
+#define D18F2x290_dct1_ErrCmdNum_WIDTH                          21
+#define D18F2x290_dct1_ErrCmdNum_MASK                           0x1fffff
+#define D18F2x290_dct1_Reserved_23_21_OFFSET                    21
+#define D18F2x290_dct1_Reserved_23_21_WIDTH                     3
+#define D18F2x290_dct1_Reserved_23_21_MASK                      0xe00000
+#define D18F2x290_dct1_ErrBeatNum_OFFSET                        24
+#define D18F2x290_dct1_ErrBeatNum_WIDTH                         3
+#define D18F2x290_dct1_ErrBeatNum_MASK                          0x7000000
+#define D18F2x290_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x290_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x290_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x290_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrCmdNum:21; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                               ErrBeatNum:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x290_dct1_STRUCT;
+
+// **** D18F2x290_dct0 Register Definition ****
+// Address
+#define D18F2x290_dct0_ADDRESS                                  0x290
+
+// Type
+#define D18F2x290_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x290_dct0_ErrCmdNum_OFFSET                         0
+#define D18F2x290_dct0_ErrCmdNum_WIDTH                          21
+#define D18F2x290_dct0_ErrCmdNum_MASK                           0x1fffff
+#define D18F2x290_dct0_Reserved_23_21_OFFSET                    21
+#define D18F2x290_dct0_Reserved_23_21_WIDTH                     3
+#define D18F2x290_dct0_Reserved_23_21_MASK                      0xe00000
+#define D18F2x290_dct0_ErrBeatNum_OFFSET                        24
+#define D18F2x290_dct0_ErrBeatNum_WIDTH                         3
+#define D18F2x290_dct0_ErrBeatNum_MASK                          0x7000000
+#define D18F2x290_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x290_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x290_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x290_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrCmdNum:21; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                               ErrBeatNum:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x290_dct0_STRUCT;
+
+// **** D18F2x294_dct1 Register Definition ****
+// Address
+#define D18F2x294_dct1_ADDRESS                                  0x294
+
+// Type
+#define D18F2x294_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x294_dct1_DQErr_31_0__OFFSET                       0
+#define D18F2x294_dct1_DQErr_31_0__WIDTH                        32
+#define D18F2x294_dct1_DQErr_31_0__MASK                         0xffffffff
+
+/// D18F2x294_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DQErr_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x294_dct1_STRUCT;
+
+// **** D18F2x294_dct0 Register Definition ****
+// Address
+#define D18F2x294_dct0_ADDRESS                                  0x294
+
+// Type
+#define D18F2x294_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x294_dct0_DQErr_31_0__OFFSET                       0
+#define D18F2x294_dct0_DQErr_31_0__WIDTH                        32
+#define D18F2x294_dct0_DQErr_31_0__MASK                         0xffffffff
+
+/// D18F2x294_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DQErr_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x294_dct0_STRUCT;
+
+// **** D18F2x298_dct0 Register Definition ****
+// Address
+#define D18F2x298_dct0_ADDRESS                                  0x298
+
+// Type
+#define D18F2x298_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x298_dct0_DQErr_63_32__OFFSET                      0
+#define D18F2x298_dct0_DQErr_63_32__WIDTH                       32
+#define D18F2x298_dct0_DQErr_63_32__MASK                        0xffffffff
+
+/// D18F2x298_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQErr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x298_dct0_STRUCT;
+
+// **** D18F2x298_dct1 Register Definition ****
+// Address
+#define D18F2x298_dct1_ADDRESS                                  0x298
+
+// Type
+#define D18F2x298_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x298_dct1_DQErr_63_32__OFFSET                      0
+#define D18F2x298_dct1_DQErr_63_32__WIDTH                       32
+#define D18F2x298_dct1_DQErr_63_32__MASK                        0xffffffff
+
+/// D18F2x298_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQErr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x298_dct1_STRUCT;
+
+// **** D18F2x2E0_dct1 Register Definition ****
+// Address
+#define D18F2x2E0_dct1_ADDRESS                                  0x2e0
+
+// Type
+#define D18F2x2E0_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x2E0_dct1_CurMemPstate_OFFSET                      0
+#define D18F2x2E0_dct1_CurMemPstate_WIDTH                       1
+#define D18F2x2E0_dct1_CurMemPstate_MASK                        0x1
+#define D18F2x2E0_dct1_Reserved_19_1_OFFSET                     1
+#define D18F2x2E0_dct1_Reserved_19_1_WIDTH                      19
+#define D18F2x2E0_dct1_Reserved_19_1_MASK                       0xffffe
+#define D18F2x2E0_dct1_MxMrsEn_OFFSET                           20
+#define D18F2x2E0_dct1_MxMrsEn_WIDTH                            3
+#define D18F2x2E0_dct1_MxMrsEn_MASK                             0x700000
+#define D18F2x2E0_dct1_Reserved_23_23_OFFSET                    23
+#define D18F2x2E0_dct1_Reserved_23_23_WIDTH                     1
+#define D18F2x2E0_dct1_Reserved_23_23_MASK                      0x800000
+#define D18F2x2E0_dct1_M1MemClkFreq_OFFSET                      24
+#define D18F2x2E0_dct1_M1MemClkFreq_WIDTH                       5
+#define D18F2x2E0_dct1_M1MemClkFreq_MASK                        0x1f000000
+#define D18F2x2E0_dct1_Reserved_29_29_OFFSET                    29
+#define D18F2x2E0_dct1_Reserved_29_29_WIDTH                     1
+#define D18F2x2E0_dct1_Reserved_29_29_MASK                      0x20000000
+#define D18F2x2E0_dct1_FastMstateDis_OFFSET                     30
+#define D18F2x2E0_dct1_FastMstateDis_WIDTH                      1
+#define D18F2x2E0_dct1_FastMstateDis_MASK                       0x40000000
+#define D18F2x2E0_dct1_Reserved_31_31_OFFSET                    31
+#define D18F2x2E0_dct1_Reserved_31_31_WIDTH                     1
+#define D18F2x2E0_dct1_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x2E0_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CurMemPstate:1 ; ///<
+    UINT32                                            Reserved_19_1:19; ///<
+    UINT32                                                  MxMrsEn:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                             M1MemClkFreq:5 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                            FastMstateDis:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E0_dct1_STRUCT;
+
+// **** D18F2x2E0_dct0 Register Definition ****
+// Address
+#define D18F2x2E0_dct0_ADDRESS                                  0x2e0
+
+// Type
+#define D18F2x2E0_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x2E0_dct0_CurMemPstate_OFFSET                      0
+#define D18F2x2E0_dct0_CurMemPstate_WIDTH                       1
+#define D18F2x2E0_dct0_CurMemPstate_MASK                        0x1
+#define D18F2x2E0_dct0_Reserved_19_1_OFFSET                     1
+#define D18F2x2E0_dct0_Reserved_19_1_WIDTH                      19
+#define D18F2x2E0_dct0_Reserved_19_1_MASK                       0xffffe
+#define D18F2x2E0_dct0_MxMrsEn_OFFSET                           20
+#define D18F2x2E0_dct0_MxMrsEn_WIDTH                            3
+#define D18F2x2E0_dct0_MxMrsEn_MASK                             0x700000
+#define D18F2x2E0_dct0_Reserved_23_23_OFFSET                    23
+#define D18F2x2E0_dct0_Reserved_23_23_WIDTH                     1
+#define D18F2x2E0_dct0_Reserved_23_23_MASK                      0x800000
+#define D18F2x2E0_dct0_M1MemClkFreq_OFFSET                      24
+#define D18F2x2E0_dct0_M1MemClkFreq_WIDTH                       5
+#define D18F2x2E0_dct0_M1MemClkFreq_MASK                        0x1f000000
+#define D18F2x2E0_dct0_Reserved_29_29_OFFSET                    29
+#define D18F2x2E0_dct0_Reserved_29_29_WIDTH                     1
+#define D18F2x2E0_dct0_Reserved_29_29_MASK                      0x20000000
+#define D18F2x2E0_dct0_FastMstateDis_OFFSET                     30
+#define D18F2x2E0_dct0_FastMstateDis_WIDTH                      1
+#define D18F2x2E0_dct0_FastMstateDis_MASK                       0x40000000
+#define D18F2x2E0_dct0_Reserved_31_31_OFFSET                    31
+#define D18F2x2E0_dct0_Reserved_31_31_WIDTH                     1
+#define D18F2x2E0_dct0_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x2E0_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CurMemPstate:1 ; ///<
+    UINT32                                            Reserved_19_1:19; ///<
+    UINT32                                                  MxMrsEn:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                             M1MemClkFreq:5 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                            FastMstateDis:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E0_dct0_STRUCT;
+
+// **** D18F2x2E8_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x2E8_dct0_mp1_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x2E8_dct0_mp1_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct0_mp1_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct0_mp1_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct0_mp1_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct0_mp1_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct0_mp1_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct0_mp1_STRUCT;
+
+// **** D18F2x2E8_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x2E8_dct1_mp1_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x2E8_dct1_mp1_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct1_mp1_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct1_mp1_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct1_mp1_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct1_mp1_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct1_mp1_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct1_mp1_STRUCT;
+
+// **** D18F2x2E8_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x2E8_dct1_mp0_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x2E8_dct1_mp0_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct1_mp0_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct1_mp0_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct1_mp0_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct1_mp0_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct1_mp0_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct1_mp0_STRUCT;
+
+// **** D18F2x2E8_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x2E8_dct0_mp0_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x2E8_dct0_mp0_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct0_mp0_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct0_mp0_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct0_mp0_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct0_mp0_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct0_mp0_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct0_mp0_STRUCT;
+
+// **** D18F2x2EC_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x2EC_dct0_mp0_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x2EC_dct0_mp0_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct0_mp0_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct0_mp0_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct0_mp0_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct0_mp0_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct0_mp0_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct0_mp0_STRUCT;
+
+// **** D18F2x2EC_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x2EC_dct0_mp1_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x2EC_dct0_mp1_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct0_mp1_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct0_mp1_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct0_mp1_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct0_mp1_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct0_mp1_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct0_mp1_STRUCT;
+
+// **** D18F2x2EC_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x2EC_dct1_mp1_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x2EC_dct1_mp1_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct1_mp1_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct1_mp1_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct1_mp1_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct1_mp1_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct1_mp1_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct1_mp1_STRUCT;
+
+// **** D18F2x2EC_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x2EC_dct1_mp0_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x2EC_dct1_mp0_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct1_mp0_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct1_mp0_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct1_mp0_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct1_mp0_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct1_mp0_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct1_mp0_STRUCT;
+
+// **** D18F2x2F0_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x2F0_dct1_mp1_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x2F0_dct1_mp1_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct1_mp1_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct1_mp1_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct1_mp1_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct1_mp1_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct1_mp1_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct1_mp1_STRUCT;
+
+// **** D18F2x2F0_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x2F0_dct0_mp1_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x2F0_dct0_mp1_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct0_mp1_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct0_mp1_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct0_mp1_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct0_mp1_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct0_mp1_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct0_mp1_STRUCT;
+
+// **** D18F2x2F0_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x2F0_dct1_mp0_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x2F0_dct1_mp0_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct1_mp0_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct1_mp0_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct1_mp0_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct1_mp0_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct1_mp0_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct1_mp0_STRUCT;
+
+// **** D18F2x2F0_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x2F0_dct0_mp0_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x2F0_dct0_mp0_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct0_mp0_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct0_mp0_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct0_mp0_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct0_mp0_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct0_mp0_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct0_mp0_STRUCT;
+
+// **** D18F2x400_dct1 Register Definition ****
+// Address
+#define D18F2x400_dct1_ADDRESS                                  0x400
+
+// Type
+#define D18F2x400_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x400_dct1_MctTokenLimit_OFFSET                     0
+#define D18F2x400_dct1_MctTokenLimit_WIDTH                      4
+#define D18F2x400_dct1_MctTokenLimit_MASK                       0xf
+#define D18F2x400_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x400_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x400_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x400_dct1_GmcTokenLimit_OFFSET                     8
+#define D18F2x400_dct1_GmcTokenLimit_WIDTH                      4
+#define D18F2x400_dct1_GmcTokenLimit_MASK                       0xf00
+#define D18F2x400_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x400_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x400_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x400_dct1_Reserved_31_16_OFFSET                    16
+#define D18F2x400_dct1_Reserved_31_16_WIDTH                     16
+#define D18F2x400_dct1_Reserved_31_16_MASK                      0xffff0000
+
+/// D18F2x400_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            MctTokenLimit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                            GmcTokenLimit:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x400_dct1_STRUCT;
+
+// **** D18F2x400_dct0 Register Definition ****
+// Address
+#define D18F2x400_dct0_ADDRESS                                  0x400
+
+// Type
+#define D18F2x400_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x400_dct0_MctTokenLimit_OFFSET                     0
+#define D18F2x400_dct0_MctTokenLimit_WIDTH                      4
+#define D18F2x400_dct0_MctTokenLimit_MASK                       0xf
+#define D18F2x400_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x400_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x400_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x400_dct0_GmcTokenLimit_OFFSET                     8
+#define D18F2x400_dct0_GmcTokenLimit_WIDTH                      4
+#define D18F2x400_dct0_GmcTokenLimit_MASK                       0xf00
+#define D18F2x400_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x400_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x400_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x400_dct0_Reserved_31_16_OFFSET                    16
+#define D18F2x400_dct0_Reserved_31_16_WIDTH                     16
+#define D18F2x400_dct0_Reserved_31_16_MASK                      0xffff0000
+
+/// D18F2x400_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            MctTokenLimit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                            GmcTokenLimit:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x400_dct0_STRUCT;
+
+// **** D18F2x404_dct0 Register Definition ****
+// Address
+#define D18F2x404_dct0_ADDRESS                                  0x404
+
+// Type
+#define D18F2x404_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x404_dct0_UrMctTokenLimit_OFFSET                   0
+#define D18F2x404_dct0_UrMctTokenLimit_WIDTH                    4
+#define D18F2x404_dct0_UrMctTokenLimit_MASK                     0xf
+#define D18F2x404_dct0_UrMctMinTokens_OFFSET                    4
+#define D18F2x404_dct0_UrMctMinTokens_WIDTH                     4
+#define D18F2x404_dct0_UrMctMinTokens_MASK                      0xf0
+#define D18F2x404_dct0_UrGmcTokenLimit_OFFSET                   8
+#define D18F2x404_dct0_UrGmcTokenLimit_WIDTH                    4
+#define D18F2x404_dct0_UrGmcTokenLimit_MASK                     0xf00
+#define D18F2x404_dct0_UrGmcMinTokens_OFFSET                    12
+#define D18F2x404_dct0_UrGmcMinTokens_WIDTH                     4
+#define D18F2x404_dct0_UrGmcMinTokens_MASK                      0xf000
+#define D18F2x404_dct0_UrgentTknDis_OFFSET                      16
+#define D18F2x404_dct0_UrgentTknDis_WIDTH                       1
+#define D18F2x404_dct0_UrgentTknDis_MASK                        0x10000
+#define D18F2x404_dct0_Reserved_31_17_OFFSET                    17
+#define D18F2x404_dct0_Reserved_31_17_WIDTH                     15
+#define D18F2x404_dct0_Reserved_31_17_MASK                      0xfffe0000
+
+/// D18F2x404_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          UrMctTokenLimit:4 ; ///<
+    UINT32                                           UrMctMinTokens:4 ; ///<
+    UINT32                                          UrGmcTokenLimit:4 ; ///<
+    UINT32                                           UrGmcMinTokens:4 ; ///<
+    UINT32                                             UrgentTknDis:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x404_dct0_STRUCT;
+
+// **** D18F2x404_dct1 Register Definition ****
+// Address
+#define D18F2x404_dct1_ADDRESS                                  0x404
+
+// Type
+#define D18F2x404_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x404_dct1_UrMctTokenLimit_OFFSET                   0
+#define D18F2x404_dct1_UrMctTokenLimit_WIDTH                    4
+#define D18F2x404_dct1_UrMctTokenLimit_MASK                     0xf
+#define D18F2x404_dct1_UrMctMinTokens_OFFSET                    4
+#define D18F2x404_dct1_UrMctMinTokens_WIDTH                     4
+#define D18F2x404_dct1_UrMctMinTokens_MASK                      0xf0
+#define D18F2x404_dct1_UrGmcTokenLimit_OFFSET                   8
+#define D18F2x404_dct1_UrGmcTokenLimit_WIDTH                    4
+#define D18F2x404_dct1_UrGmcTokenLimit_MASK                     0xf00
+#define D18F2x404_dct1_UrGmcMinTokens_OFFSET                    12
+#define D18F2x404_dct1_UrGmcMinTokens_WIDTH                     4
+#define D18F2x404_dct1_UrGmcMinTokens_MASK                      0xf000
+#define D18F2x404_dct1_UrgentTknDis_OFFSET                      16
+#define D18F2x404_dct1_UrgentTknDis_WIDTH                       1
+#define D18F2x404_dct1_UrgentTknDis_MASK                        0x10000
+#define D18F2x404_dct1_Reserved_31_17_OFFSET                    17
+#define D18F2x404_dct1_Reserved_31_17_WIDTH                     15
+#define D18F2x404_dct1_Reserved_31_17_MASK                      0xfffe0000
+
+/// D18F2x404_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          UrMctTokenLimit:4 ; ///<
+    UINT32                                           UrMctMinTokens:4 ; ///<
+    UINT32                                          UrGmcTokenLimit:4 ; ///<
+    UINT32                                           UrGmcMinTokens:4 ; ///<
+    UINT32                                             UrgentTknDis:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x404_dct1_STRUCT;
+
+// **** D18F2x408_dct1 Register Definition ****
+// Address
+#define D18F2x408_dct1_ADDRESS                                  0x408
+
+// Type
+#define D18F2x408_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x408_dct1_CpuElevPrioDis_OFFSET                    0
+#define D18F2x408_dct1_CpuElevPrioDis_WIDTH                     1
+#define D18F2x408_dct1_CpuElevPrioDis_MASK                      0x1
+#define D18F2x408_dct1_TokenAllocSelect_OFFSET                  1
+#define D18F2x408_dct1_TokenAllocSelect_WIDTH                   1
+#define D18F2x408_dct1_TokenAllocSelect_MASK                    0x2
+#define D18F2x408_dct1_Reserved_30_2_OFFSET                     2
+#define D18F2x408_dct1_Reserved_30_2_WIDTH                      29
+#define D18F2x408_dct1_Reserved_30_2_MASK                       0x7ffffffc
+#define D18F2x408_dct1_DisHalfNclkPwrGate_OFFSET                31
+#define D18F2x408_dct1_DisHalfNclkPwrGate_WIDTH                 1
+#define D18F2x408_dct1_DisHalfNclkPwrGate_MASK                  0x80000000
+
+/// D18F2x408_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CpuElevPrioDis:1 ; ///<
+    UINT32                                         TokenAllocSelect:1 ; ///<
+    UINT32                                            Reserved_30_2:29; ///<
+    UINT32                                       DisHalfNclkPwrGate:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x408_dct1_STRUCT;
+
+// **** D18F2x408_dct0 Register Definition ****
+// Address
+#define D18F2x408_dct0_ADDRESS                                  0x408
+
+// Type
+#define D18F2x408_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x408_dct0_CpuElevPrioDis_OFFSET                    0
+#define D18F2x408_dct0_CpuElevPrioDis_WIDTH                     1
+#define D18F2x408_dct0_CpuElevPrioDis_MASK                      0x1
+#define D18F2x408_dct0_TokenAllocSelect_OFFSET                  1
+#define D18F2x408_dct0_TokenAllocSelect_WIDTH                   1
+#define D18F2x408_dct0_TokenAllocSelect_MASK                    0x2
+#define D18F2x408_dct0_Reserved_30_2_OFFSET                     2
+#define D18F2x408_dct0_Reserved_30_2_WIDTH                      29
+#define D18F2x408_dct0_Reserved_30_2_MASK                       0x7ffffffc
+#define D18F2x408_dct0_DisHalfNclkPwrGate_OFFSET                31
+#define D18F2x408_dct0_DisHalfNclkPwrGate_WIDTH                 1
+#define D18F2x408_dct0_DisHalfNclkPwrGate_MASK                  0x80000000
+
+/// D18F2x408_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CpuElevPrioDis:1 ; ///<
+    UINT32                                         TokenAllocSelect:1 ; ///<
+    UINT32                                            Reserved_30_2:29; ///<
+    UINT32                                       DisHalfNclkPwrGate:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x408_dct0_STRUCT;
+
+// **** D18F2x420_dct0 Register Definition ****
+// Address
+#define D18F2x420_dct0_ADDRESS                                  0x420
+
+// Type
+#define D18F2x420_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x420_dct0_CmdRdPtrInit_OFFSET                      0
+#define D18F2x420_dct0_CmdRdPtrInit_WIDTH                       4
+#define D18F2x420_dct0_CmdRdPtrInit_MASK                        0xf
+#define D18F2x420_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x420_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x420_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x420_dct0_SbRdPtrInit_OFFSET                       8
+#define D18F2x420_dct0_SbRdPtrInit_WIDTH                        4
+#define D18F2x420_dct0_SbRdPtrInit_MASK                         0xf00
+#define D18F2x420_dct0_Reserved_31_12_OFFSET                    12
+#define D18F2x420_dct0_Reserved_31_12_WIDTH                     20
+#define D18F2x420_dct0_Reserved_31_12_MASK                      0xfffff000
+
+/// D18F2x420_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CmdRdPtrInit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                              SbRdPtrInit:4 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x420_dct0_STRUCT;
+
+// **** D18F2x420_dct1 Register Definition ****
+// Address
+#define D18F2x420_dct1_ADDRESS                                  0x420
+
+// Type
+#define D18F2x420_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x420_dct1_CmdRdPtrInit_OFFSET                      0
+#define D18F2x420_dct1_CmdRdPtrInit_WIDTH                       4
+#define D18F2x420_dct1_CmdRdPtrInit_MASK                        0xf
+#define D18F2x420_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x420_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x420_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x420_dct1_SbRdPtrInit_OFFSET                       8
+#define D18F2x420_dct1_SbRdPtrInit_WIDTH                        4
+#define D18F2x420_dct1_SbRdPtrInit_MASK                         0xf00
+#define D18F2x420_dct1_Reserved_31_12_OFFSET                    12
+#define D18F2x420_dct1_Reserved_31_12_WIDTH                     20
+#define D18F2x420_dct1_Reserved_31_12_MASK                      0xfffff000
+
+/// D18F2x420_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CmdRdPtrInit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                              SbRdPtrInit:4 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x420_dct1_STRUCT;
+
+// **** D18F3x00 Register Definition ****
+// Address
+#define D18F3x00_ADDRESS                                        0x0
+
+// Type
+#define D18F3x00_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x00_VendorID_OFFSET                                0
+#define D18F3x00_VendorID_WIDTH                                 16
+#define D18F3x00_VendorID_MASK                                  0xffff
+#define D18F3x00_DeviceID_OFFSET                                16
+#define D18F3x00_DeviceID_WIDTH                                 16
+#define D18F3x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F3x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x00_STRUCT;
+
+// **** D18F3x04 Register Definition ****
+// Address
+#define D18F3x04_ADDRESS                                        0x4
+
+// Type
+#define D18F3x04_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x04_Command_OFFSET                                 0
+#define D18F3x04_Command_WIDTH                                  16
+#define D18F3x04_Command_MASK                                   0xffff
+#define D18F3x04_Status_OFFSET                                  16
+#define D18F3x04_Status_WIDTH                                   16
+#define D18F3x04_Status_MASK                                    0xffff0000
+
+/// D18F3x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x04_STRUCT;
+
+// **** D18F3x08 Register Definition ****
+// Address
+#define D18F3x08_ADDRESS                                        0x8
+
+// Type
+#define D18F3x08_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x08_RevID_OFFSET                                   0
+#define D18F3x08_RevID_WIDTH                                    8
+#define D18F3x08_RevID_MASK                                     0xff
+#define D18F3x08_ClassCode_OFFSET                               8
+#define D18F3x08_ClassCode_WIDTH                                24
+#define D18F3x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F3x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x08_STRUCT;
+
+// **** D18F3x0C Register Definition ****
+// Address
+#define D18F3x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F3x0C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x0C_HeaderTypeReg_OFFSET                           0
+#define D18F3x0C_HeaderTypeReg_WIDTH                            32
+#define D18F3x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F3x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x0C_STRUCT;
+
+// **** D18F3x34 Register Definition ****
+// Address
+#define D18F3x34_ADDRESS                                        0x34
+
+// Type
+#define D18F3x34_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x34_CapPtr_OFFSET                                  0
+#define D18F3x34_CapPtr_WIDTH                                   8
+#define D18F3x34_CapPtr_MASK                                    0xff
+#define D18F3x34_Reserved_31_8_OFFSET                           8
+#define D18F3x34_Reserved_31_8_WIDTH                            24
+#define D18F3x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F3x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x34_STRUCT;
+
+// **** D18F3x40 Register Definition ****
+// Address
+#define D18F3x40_ADDRESS                                        0x40
+
+// Type
+#define D18F3x40_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x40_Unused_4_0_OFFSET                              0
+#define D18F3x40_Unused_4_0_WIDTH                               5
+#define D18F3x40_Unused_4_0_MASK                                0x1f
+#define D18F3x40_SyncPktEn_OFFSET                               5
+#define D18F3x40_SyncPktEn_WIDTH                                1
+#define D18F3x40_SyncPktEn_MASK                                 0x20
+#define D18F3x40_Unused_7_6_OFFSET                              6
+#define D18F3x40_Unused_7_6_WIDTH                               2
+#define D18F3x40_Unused_7_6_MASK                                0xc0
+#define D18F3x40_MstrAbortEn_OFFSET                             8
+#define D18F3x40_MstrAbortEn_WIDTH                              1
+#define D18F3x40_MstrAbortEn_MASK                               0x100
+#define D18F3x40_TgtAbortEn_OFFSET                              9
+#define D18F3x40_TgtAbortEn_WIDTH                               1
+#define D18F3x40_TgtAbortEn_MASK                                0x200
+#define D18F3x40_Unused_10_10_OFFSET                            10
+#define D18F3x40_Unused_10_10_WIDTH                             1
+#define D18F3x40_Unused_10_10_MASK                              0x400
+#define D18F3x40_AtomicRMWEn_OFFSET                             11
+#define D18F3x40_AtomicRMWEn_WIDTH                              1
+#define D18F3x40_AtomicRMWEn_MASK                               0x800
+#define D18F3x40_WDTRptEn_OFFSET                                12
+#define D18F3x40_WDTRptEn_WIDTH                                 1
+#define D18F3x40_WDTRptEn_MASK                                  0x1000
+#define D18F3x40_Unused_15_13_OFFSET                            13
+#define D18F3x40_Unused_15_13_WIDTH                             3
+#define D18F3x40_Unused_15_13_MASK                              0xe000
+#define D18F3x40_NbIntProtEn_OFFSET                             16
+#define D18F3x40_NbIntProtEn_WIDTH                              1
+#define D18F3x40_NbIntProtEn_MASK                               0x10000
+#define D18F3x40_CpPktDatEn_OFFSET                              17
+#define D18F3x40_CpPktDatEn_WIDTH                               1
+#define D18F3x40_CpPktDatEn_MASK                                0x20000
+#define D18F3x40_Unused_24_18_OFFSET                            18
+#define D18F3x40_Unused_24_18_WIDTH                             7
+#define D18F3x40_Unused_24_18_MASK                              0x1fc0000
+#define D18F3x40_UsPwDatErrEn_OFFSET                            25
+#define D18F3x40_UsPwDatErrEn_WIDTH                             1
+#define D18F3x40_UsPwDatErrEn_MASK                              0x2000000
+#define D18F3x40_NbArrayParEn_OFFSET                            26
+#define D18F3x40_NbArrayParEn_WIDTH                             1
+#define D18F3x40_NbArrayParEn_MASK                              0x4000000
+#define D18F3x40_Unused_29_27_OFFSET                            27
+#define D18F3x40_Unused_29_27_WIDTH                             3
+#define D18F3x40_Unused_29_27_MASK                              0x38000000
+#define D18F3x40_Unused_30_30_OFFSET                            30
+#define D18F3x40_Unused_30_30_WIDTH                             1
+#define D18F3x40_Unused_30_30_MASK                              0x40000000
+#define D18F3x40_McaCpuDatErrEn_OFFSET                          31
+#define D18F3x40_McaCpuDatErrEn_WIDTH                           1
+#define D18F3x40_McaCpuDatErrEn_MASK                            0x80000000
+
+/// D18F3x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               Unused_4_0:5 ; ///<
+    UINT32                                                SyncPktEn:1 ; ///<
+    UINT32                                               Unused_7_6:2 ; ///<
+    UINT32                                              MstrAbortEn:1 ; ///<
+    UINT32                                               TgtAbortEn:1 ; ///<
+    UINT32                                             Unused_10_10:1 ; ///<
+    UINT32                                              AtomicRMWEn:1 ; ///<
+    UINT32                                                 WDTRptEn:1 ; ///<
+    UINT32                                             Unused_15_13:3 ; ///<
+    UINT32                                              NbIntProtEn:1 ; ///<
+    UINT32                                               CpPktDatEn:1 ; ///<
+    UINT32                                             Unused_24_18:7 ; ///<
+    UINT32                                             UsPwDatErrEn:1 ; ///<
+    UINT32                                             NbArrayParEn:1 ; ///<
+    UINT32                                             Unused_29_27:3 ; ///<
+    UINT32                                             Unused_30_30:1 ; ///<
+    UINT32                                           McaCpuDatErrEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x40_STRUCT;
+
+// **** D18F3x44 Register Definition ****
+// Address
+#define D18F3x44_ADDRESS                                        0x44
+
+// Type
+#define D18F3x44_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x44_Reserved_0_0_OFFSET                            0
+#define D18F3x44_Reserved_0_0_WIDTH                             1
+#define D18F3x44_Reserved_0_0_MASK                              0x1
+#define D18F3x44_CpuRdDatErrEn_OFFSET                           1
+#define D18F3x44_CpuRdDatErrEn_WIDTH                            1
+#define D18F3x44_CpuRdDatErrEn_MASK                             0x2
+#define D18F3x44_SyncPktGenDis_OFFSET                           3
+#define D18F3x44_SyncPktGenDis_WIDTH                            1
+#define D18F3x44_SyncPktGenDis_MASK                             0x8
+#define D18F3x44_SyncPktPropDis_OFFSET                          4
+#define D18F3x44_SyncPktPropDis_WIDTH                           1
+#define D18F3x44_SyncPktPropDis_MASK                            0x10
+#define D18F3x44_IoMstAbortDis_OFFSET                           5
+#define D18F3x44_IoMstAbortDis_WIDTH                            1
+#define D18F3x44_IoMstAbortDis_MASK                             0x20
+#define D18F3x44_CpuErrDis_OFFSET                               6
+#define D18F3x44_CpuErrDis_WIDTH                                1
+#define D18F3x44_CpuErrDis_MASK                                 0x40
+#define D18F3x44_IoErrDis_OFFSET                                7
+#define D18F3x44_IoErrDis_WIDTH                                 1
+#define D18F3x44_IoErrDis_MASK                                  0x80
+#define D18F3x44_WDTDis_OFFSET                                  8
+#define D18F3x44_WDTDis_WIDTH                                   1
+#define D18F3x44_WDTDis_MASK                                    0x100
+#define D18F3x44_WDTCntSel_2_0__OFFSET                          9
+#define D18F3x44_WDTCntSel_2_0__WIDTH                           3
+#define D18F3x44_WDTCntSel_2_0__MASK                            0xe00
+#define D18F3x44_WDTBaseSel_OFFSET                              12
+#define D18F3x44_WDTBaseSel_WIDTH                               2
+#define D18F3x44_WDTBaseSel_MASK                                0x3000
+#define D18F3x44_GenCrcErrByte0_OFFSET                          16
+#define D18F3x44_GenCrcErrByte0_WIDTH                           1
+#define D18F3x44_GenCrcErrByte0_MASK                            0x10000
+#define D18F3x44_GenCrcErrByte1_OFFSET                          17
+#define D18F3x44_GenCrcErrByte1_WIDTH                           1
+#define D18F3x44_GenCrcErrByte1_MASK                            0x20000
+#define D18F3x44_GenSubLinkSel_OFFSET                           18
+#define D18F3x44_GenSubLinkSel_WIDTH                            2
+#define D18F3x44_GenSubLinkSel_MASK                             0xc0000
+#define D18F3x44_Reserved_23_22_WIDTH                           2
+#define D18F3x44_Reserved_23_22_MASK                            0xc00000
+#define D18F3x44_IoRdDatErrEn_OFFSET                            24
+#define D18F3x44_IoRdDatErrEn_WIDTH                             1
+#define D18F3x44_IoRdDatErrEn_MASK                              0x1000000
+#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET                      25
+#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH                       1
+#define D18F3x44_DisPciCfgCpuErrRsp_MASK                        0x2000000
+#define D18F3x44_FlagMcaCorrErr_OFFSET                          26
+#define D18F3x44_FlagMcaCorrErr_WIDTH                           1
+#define D18F3x44_FlagMcaCorrErr_MASK                            0x4000000
+#define D18F3x44_NbMcaToMstCpuEn_OFFSET                         27
+#define D18F3x44_NbMcaToMstCpuEn_WIDTH                          1
+#define D18F3x44_NbMcaToMstCpuEn_MASK                           0x8000000
+#define D18F3x44_DisTgtAbortCpuErrRsp_OFFSET                    28
+#define D18F3x44_DisTgtAbortCpuErrRsp_WIDTH                     1
+#define D18F3x44_DisTgtAbortCpuErrRsp_MASK                      0x10000000
+#define D18F3x44_DisMstAbortCpuErrRsp_OFFSET                    29
+#define D18F3x44_DisMstAbortCpuErrRsp_WIDTH                     1
+#define D18F3x44_DisMstAbortCpuErrRsp_MASK                      0x20000000
+#define D18F3x44_SyncOnDramAdrParErrEn_OFFSET                   30
+#define D18F3x44_SyncOnDramAdrParErrEn_WIDTH                    1
+#define D18F3x44_SyncOnDramAdrParErrEn_MASK                     0x40000000
+#define D18F3x44_NbMcaLogEn_OFFSET                              31
+#define D18F3x44_NbMcaLogEn_WIDTH                               1
+#define D18F3x44_NbMcaLogEn_MASK                                0x80000000
+
+/// D18F3x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                            CpuRdDatErrEn:1 ; ///<
+    UINT32                                            SyncOnUcEccEn:1 ; ///<
+    UINT32                                            SyncPktGenDis:1 ; ///<
+    UINT32                                           SyncPktPropDis:1 ; ///<
+    UINT32                                            IoMstAbortDis:1 ; ///<
+    UINT32                                                CpuErrDis:1 ; ///<
+    UINT32                                                 IoErrDis:1 ; ///<
+    UINT32                                                   WDTDis:1 ; ///<
+    UINT32                                           WDTCntSel_2_0_:3 ; ///<
+    UINT32                                               WDTBaseSel:2 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                           GenCrcErrByte0:1 ; ///<
+    UINT32                                           GenCrcErrByte1:1 ; ///<
+    UINT32                                            GenSubLinkSel:2 ; ///<
+    UINT32                                              :1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                             IoRdDatErrEn:1 ; ///<
+    UINT32                                       DisPciCfgCpuErrRsp:1 ; ///<
+    UINT32                                           FlagMcaCorrErr:1 ; ///<
+    UINT32                                          NbMcaToMstCpuEn:1 ; ///<
+    UINT32                                     DisTgtAbortCpuErrRsp:1 ; ///<
+    UINT32                                     DisMstAbortCpuErrRsp:1 ; ///<
+    UINT32                                    SyncOnDramAdrParErrEn:1 ; ///<
+    UINT32                                               NbMcaLogEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x44_STRUCT;
+
+// **** D18F3x48 Register Definition ****
+// Address
+#define D18F3x48_ADDRESS                                        0x48
+
+// Type
+#define D18F3x48_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x48_ErrorCode_OFFSET                               0
+#define D18F3x48_ErrorCode_WIDTH                                16
+#define D18F3x48_ErrorCode_MASK                                 0xffff
+#define D18F3x48_ErrorCodeExt_OFFSET                            16
+#define D18F3x48_ErrorCodeExt_WIDTH                             5
+#define D18F3x48_ErrorCodeExt_MASK                              0x1f0000
+#define D18F3x48_Reserved_23_21_OFFSET                          21
+#define D18F3x48_Reserved_23_21_WIDTH                           3
+#define D18F3x48_Reserved_23_21_MASK                            0xe00000
+#define D18F3x48_Reserved_31_24_OFFSET                          24
+#define D18F3x48_Reserved_31_24_WIDTH                           8
+#define D18F3x48_Reserved_31_24_MASK                            0xff000000
+
+/// D18F3x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrorCode:16; ///<
+    UINT32                                             ErrorCodeExt:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x48_STRUCT;
+
+// **** D18F3x4C Register Definition ****
+// Address
+#define D18F3x4C_ADDRESS                                        0x4c
+
+// Type
+#define D18F3x4C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x4C_ErrCoreId_OFFSET                               0
+#define D18F3x4C_ErrCoreId_WIDTH                                4
+#define D18F3x4C_ErrCoreId_MASK                                 0xf
+#define D18F3x4C_Reserved_39_37_OFFSET                          5
+#define D18F3x4C_Reserved_39_37_WIDTH                           3
+#define D18F3x4C_Reserved_39_37_MASK                            0xe0
+#define D18F3x4C_Reserved_40_40_OFFSET                          8
+#define D18F3x4C_Reserved_40_40_WIDTH                           1
+#define D18F3x4C_Reserved_40_40_MASK                            0x100
+#define D18F3x4C_SubLink_OFFSET                                 9
+#define D18F3x4C_SubLink_WIDTH                                  1
+#define D18F3x4C_SubLink_MASK                                   0x200
+#define D18F3x4C_Reserved_43_42_OFFSET                          10
+#define D18F3x4C_Reserved_43_42_WIDTH                           2
+#define D18F3x4C_Reserved_43_42_MASK                            0xc00
+#define D18F3x4C_Reserved_54_45_OFFSET                          13
+#define D18F3x4C_Reserved_54_45_WIDTH                           10
+#define D18F3x4C_Reserved_54_45_MASK                            0x7fe000
+#define D18F3x4C_Reserved_55_55_OFFSET                          23
+#define D18F3x4C_Reserved_55_55_WIDTH                           1
+#define D18F3x4C_Reserved_55_55_MASK                            0x800000
+#define D18F3x4C_ErrCoreIdVal_OFFSET                            24
+#define D18F3x4C_ErrCoreIdVal_WIDTH                             1
+#define D18F3x4C_ErrCoreIdVal_MASK                              0x1000000
+#define D18F3x4C_PCC_OFFSET                                     25
+#define D18F3x4C_PCC_WIDTH                                      1
+#define D18F3x4C_PCC_MASK                                       0x2000000
+#define D18F3x4C_AddrV_OFFSET                                   26
+#define D18F3x4C_AddrV_WIDTH                                    1
+#define D18F3x4C_AddrV_MASK                                     0x4000000
+#define D18F3x4C_MiscV_OFFSET                                   27
+#define D18F3x4C_MiscV_WIDTH                                    1
+#define D18F3x4C_MiscV_MASK                                     0x8000000
+#define D18F3x4C_En_OFFSET                                      28
+#define D18F3x4C_En_WIDTH                                       1
+#define D18F3x4C_En_MASK                                        0x10000000
+#define D18F3x4C_UC_OFFSET                                      29
+#define D18F3x4C_UC_WIDTH                                       1
+#define D18F3x4C_UC_MASK                                        0x20000000
+#define D18F3x4C_Overflow_OFFSET                                30
+#define D18F3x4C_Overflow_WIDTH                                 1
+#define D18F3x4C_Overflow_MASK                                  0x40000000
+#define D18F3x4C_Val_OFFSET                                     31
+#define D18F3x4C_Val_WIDTH                                      1
+#define D18F3x4C_Val_MASK                                       0x80000000
+
+/// D18F3x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrCoreId:4 ; ///<
+    UINT32                                                     Link:1 ; ///<
+    UINT32                                           Reserved_39_37:3 ; ///<
+    UINT32                                           Reserved_40_40:1 ; ///<
+    UINT32                                                  SubLink:1 ; ///<
+    UINT32                                           Reserved_43_42:2 ; ///<
+    UINT32                                           Reserved_44_44:1 ; ///<
+    UINT32                                           Reserved_54_45:10; ///<
+    UINT32                                           Reserved_55_55:1 ; ///<
+    UINT32                                             ErrCoreIdVal:1 ; ///<
+    UINT32                                                      PCC:1 ; ///<
+    UINT32                                                    AddrV:1 ; ///<
+    UINT32                                                    MiscV:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                                       UC:1 ; ///<
+    UINT32                                                 Overflow:1 ; ///<
+    UINT32                                                      Val:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x4C_STRUCT;
+
+// **** D18F3x50 Register Definition ****
+// Address
+#define D18F3x50_ADDRESS                                        0x50
+
+// Type
+#define D18F3x50_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x50_Reserved_0_0_OFFSET                            0
+#define D18F3x50_Reserved_0_0_WIDTH                             1
+#define D18F3x50_Reserved_0_0_MASK                              0x1
+#define D18F3x50_ErrAddr_31_1__OFFSET                           1
+#define D18F3x50_ErrAddr_31_1__WIDTH                            31
+#define D18F3x50_ErrAddr_31_1__MASK                             0xfffffffe
+
+/// D18F3x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                            ErrAddr_31_1_:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x50_STRUCT;
+
+// **** D18F3x54 Register Definition ****
+// Address
+#define D18F3x54_ADDRESS                                        0x54
+
+// Type
+#define D18F3x54_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x54_ErrAddr_47_32__OFFSET                          0
+#define D18F3x54_ErrAddr_47_32__WIDTH                           16
+#define D18F3x54_ErrAddr_47_32__MASK                            0xffff
+#define D18F3x54_Reserved_63_48_OFFSET                          16
+#define D18F3x54_Reserved_63_48_WIDTH                           16
+#define D18F3x54_Reserved_63_48_MASK                            0xffff0000
+
+/// D18F3x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           ErrAddr_47_32_:16; ///<
+    UINT32                                           Reserved_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x54_STRUCT;
+
+// **** D18F3x64 Register Definition ****
+// Address
+#define D18F3x64_ADDRESS                                        0x64
+
+// Type
+#define D18F3x64_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x64_HtcEn_OFFSET                                   0
+#define D18F3x64_HtcEn_WIDTH                                    1
+#define D18F3x64_HtcEn_MASK                                     0x1
+#define D18F3x64_Reserved_3_1_OFFSET                            1
+#define D18F3x64_Reserved_3_1_WIDTH                             3
+#define D18F3x64_Reserved_3_1_MASK                              0xe
+#define D18F3x64_HtcAct_OFFSET                                  4
+#define D18F3x64_HtcAct_WIDTH                                   1
+#define D18F3x64_HtcAct_MASK                                    0x10
+#define D18F3x64_HtcActSts_OFFSET                               5
+#define D18F3x64_HtcActSts_WIDTH                                1
+#define D18F3x64_HtcActSts_MASK                                 0x20
+#define D18F3x64_PslApicHiEn_OFFSET                             6
+#define D18F3x64_PslApicHiEn_WIDTH                              1
+#define D18F3x64_PslApicHiEn_MASK                               0x40
+#define D18F3x64_PslApicLoEn_OFFSET                             7
+#define D18F3x64_PslApicLoEn_WIDTH                              1
+#define D18F3x64_PslApicLoEn_MASK                               0x80
+#define D18F3x64_Reserved_15_8_OFFSET                           8
+#define D18F3x64_Reserved_15_8_WIDTH                            8
+#define D18F3x64_Reserved_15_8_MASK                             0xff00
+#define D18F3x64_HtcTmpLmt_OFFSET                               16
+#define D18F3x64_HtcTmpLmt_WIDTH                                7
+#define D18F3x64_HtcTmpLmt_MASK                                 0x7f0000
+#define D18F3x64_HtcSlewSel_OFFSET                              23
+#define D18F3x64_HtcSlewSel_WIDTH                               1
+#define D18F3x64_HtcSlewSel_MASK                                0x800000
+#define D18F3x64_HtcHystLmt_OFFSET                              24
+#define D18F3x64_HtcHystLmt_WIDTH                               4
+#define D18F3x64_HtcHystLmt_MASK                                0xf000000
+#define D18F3x64_HtcPstateLimit_OFFSET                          28
+#define D18F3x64_HtcPstateLimit_WIDTH                           3
+#define D18F3x64_HtcPstateLimit_MASK                            0x70000000
+#define D18F3x64_Reserved_31_31_OFFSET                          31
+#define D18F3x64_Reserved_31_31_WIDTH                           1
+#define D18F3x64_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    HtcEn:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                                   HtcAct:1 ; ///<
+    UINT32                                                HtcActSts:1 ; ///<
+    UINT32                                              PslApicHiEn:1 ; ///<
+    UINT32                                              PslApicLoEn:1 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                                HtcTmpLmt:7 ; ///<
+    UINT32                                               HtcSlewSel:1 ; ///<
+    UINT32                                               HtcHystLmt:4 ; ///<
+    UINT32                                           HtcPstateLimit:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x64_STRUCT;
+
+// **** D18F3x68 Register Definition ****
+// Address
+#define D18F3x68_ADDRESS                                        0x68
+
+// Type
+#define D18F3x68_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x68_Reserved_4_0_OFFSET                            0
+#define D18F3x68_Reserved_4_0_WIDTH                             5
+#define D18F3x68_Reserved_4_0_MASK                              0x1f
+#define D18F3x68_SwPstateLimitEn_OFFSET                         5
+#define D18F3x68_SwPstateLimitEn_WIDTH                          1
+#define D18F3x68_SwPstateLimitEn_MASK                           0x20
+#define D18F3x68_Reserved_27_6_OFFSET                           6
+#define D18F3x68_Reserved_27_6_WIDTH                            22
+#define D18F3x68_Reserved_27_6_MASK                             0xfffffc0
+#define D18F3x68_SwPstateLimit_OFFSET                           28
+#define D18F3x68_SwPstateLimit_WIDTH                            3
+#define D18F3x68_SwPstateLimit_MASK                             0x70000000
+#define D18F3x68_Reserved_31_31_OFFSET                          31
+#define D18F3x68_Reserved_31_31_WIDTH                           1
+#define D18F3x68_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          SwPstateLimitEn:1 ; ///<
+    UINT32                                            Reserved_27_6:22; ///<
+    UINT32                                            SwPstateLimit:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x68_STRUCT;
+
+// **** D18F3x6C Register Definition ****
+// Address
+#define D18F3x6C_ADDRESS                                        0x6c
+
+// Type
+#define D18F3x6C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x6C_UpReqDBC_OFFSET                                0
+#define D18F3x6C_UpReqDBC_WIDTH                                 3
+#define D18F3x6C_UpReqDBC_MASK                                  0x7
+#define D18F3x6C_Reserved_3_3_OFFSET                            3
+#define D18F3x6C_Reserved_3_3_WIDTH                             1
+#define D18F3x6C_Reserved_3_3_MASK                              0x8
+#define D18F3x6C_DnReqDBC_OFFSET                                4
+#define D18F3x6C_DnReqDBC_WIDTH                                 2
+#define D18F3x6C_DnReqDBC_MASK                                  0x30
+#define D18F3x6C_DnRspDBC_OFFSET                                6
+#define D18F3x6C_DnRspDBC_WIDTH                                 2
+#define D18F3x6C_DnRspDBC_MASK                                  0xc0
+#define D18F3x6C_Reserved_15_8_OFFSET                           8
+#define D18F3x6C_Reserved_15_8_WIDTH                            8
+#define D18F3x6C_Reserved_15_8_MASK                             0xff00
+#define D18F3x6C_UpRspDBC_OFFSET                                16
+#define D18F3x6C_UpRspDBC_WIDTH                                 3
+#define D18F3x6C_UpRspDBC_MASK                                  0x70000
+#define D18F3x6C_Reserved_27_19_OFFSET                          19
+#define D18F3x6C_Reserved_27_19_WIDTH                           9
+#define D18F3x6C_Reserved_27_19_MASK                            0xff80000
+#define D18F3x6C_IsocRspDBC_OFFSET                              28
+#define D18F3x6C_IsocRspDBC_WIDTH                               3
+#define D18F3x6C_IsocRspDBC_MASK                                0x70000000
+#define D18F3x6C_Reserved_31_31_OFFSET                          31
+#define D18F3x6C_Reserved_31_31_WIDTH                           1
+#define D18F3x6C_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqDBC:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                 DnReqDBC:2 ; ///<
+    UINT32                                                 DnRspDBC:2 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                                 UpRspDBC:3 ; ///<
+    UINT32                                           Reserved_27_19:9 ; ///<
+    UINT32                                               IsocRspDBC:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x6C_STRUCT;
+
+// **** D18F3x70 Register Definition ****
+// Address
+#define D18F3x70_ADDRESS                                        0x70
+
+// Type
+#define D18F3x70_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x70_UpReqCBC_OFFSET                                0
+#define D18F3x70_UpReqCBC_WIDTH                                 3
+#define D18F3x70_UpReqCBC_MASK                                  0x7
+#define D18F3x70_Reserved_3_3_OFFSET                            3
+#define D18F3x70_Reserved_3_3_WIDTH                             1
+#define D18F3x70_Reserved_3_3_MASK                              0x8
+#define D18F3x70_DnReqCBC_OFFSET                                4
+#define D18F3x70_DnReqCBC_WIDTH                                 2
+#define D18F3x70_DnReqCBC_MASK                                  0x30
+#define D18F3x70_DnRspCBC_OFFSET                                6
+#define D18F3x70_DnRspCBC_WIDTH                                 2
+#define D18F3x70_DnRspCBC_MASK                                  0xc0
+#define D18F3x70_UpPreqCBC_OFFSET                               8
+#define D18F3x70_UpPreqCBC_WIDTH                                3
+#define D18F3x70_UpPreqCBC_MASK                                 0x700
+#define D18F3x70_Reserved_11_11_OFFSET                          11
+#define D18F3x70_Reserved_11_11_WIDTH                           1
+#define D18F3x70_Reserved_11_11_MASK                            0x800
+#define D18F3x70_DnPreqCBC_OFFSET                               12
+#define D18F3x70_DnPreqCBC_WIDTH                                3
+#define D18F3x70_DnPreqCBC_MASK                                 0x7000
+#define D18F3x70_Reserved_15_15_OFFSET                          15
+#define D18F3x70_Reserved_15_15_WIDTH                           1
+#define D18F3x70_Reserved_15_15_MASK                            0x8000
+#define D18F3x70_UpRspCBC_OFFSET                                16
+#define D18F3x70_UpRspCBC_WIDTH                                 3
+#define D18F3x70_UpRspCBC_MASK                                  0x70000
+#define D18F3x70_Reserved_19_19_OFFSET                          19
+#define D18F3x70_Reserved_19_19_WIDTH                           1
+#define D18F3x70_Reserved_19_19_MASK                            0x80000
+#define D18F3x70_IsocReqCBC_OFFSET                              20
+#define D18F3x70_IsocReqCBC_WIDTH                               3
+#define D18F3x70_IsocReqCBC_MASK                                0x700000
+#define D18F3x70_Reserved_23_23_OFFSET                          23
+#define D18F3x70_Reserved_23_23_WIDTH                           1
+#define D18F3x70_Reserved_23_23_MASK                            0x800000
+#define D18F3x70_IsocPreqCBC_OFFSET                             24
+#define D18F3x70_IsocPreqCBC_WIDTH                              3
+#define D18F3x70_IsocPreqCBC_MASK                               0x7000000
+#define D18F3x70_Reserved_27_27_OFFSET                          27
+#define D18F3x70_Reserved_27_27_WIDTH                           1
+#define D18F3x70_Reserved_27_27_MASK                            0x8000000
+#define D18F3x70_IsocRspCBC_OFFSET                              28
+#define D18F3x70_IsocRspCBC_WIDTH                               3
+#define D18F3x70_IsocRspCBC_MASK                                0x70000000
+#define D18F3x70_Reserved_31_31_OFFSET                          31
+#define D18F3x70_Reserved_31_31_WIDTH                           1
+#define D18F3x70_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqCBC:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                 DnReqCBC:2 ; ///<
+    UINT32                                                 DnRspCBC:2 ; ///<
+    UINT32                                                UpPreqCBC:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                                DnPreqCBC:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                 UpRspCBC:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                               IsocReqCBC:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                              IsocPreqCBC:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                               IsocRspCBC:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x70_STRUCT;
+
+// **** D18F3x74 Register Definition ****
+// Address
+#define D18F3x74_ADDRESS                                        0x74
+
+// Type
+#define D18F3x74_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x74_UpReqCBC_OFFSET                                0
+#define D18F3x74_UpReqCBC_WIDTH                                 3
+#define D18F3x74_UpReqCBC_MASK                                  0x7
+#define D18F3x74_Reserved_3_3_OFFSET                            3
+#define D18F3x74_Reserved_3_3_WIDTH                             1
+#define D18F3x74_Reserved_3_3_MASK                              0x8
+#define D18F3x74_DnReqCBC_OFFSET                                4
+#define D18F3x74_DnReqCBC_WIDTH                                 3
+#define D18F3x74_DnReqCBC_MASK                                  0x70
+#define D18F3x74_Reserved_7_7_OFFSET                            7
+#define D18F3x74_Reserved_7_7_WIDTH                             1
+#define D18F3x74_Reserved_7_7_MASK                              0x80
+#define D18F3x74_UpPreqCBC_OFFSET                               8
+#define D18F3x74_UpPreqCBC_WIDTH                                3
+#define D18F3x74_UpPreqCBC_MASK                                 0x700
+#define D18F3x74_Reserved_11_11_OFFSET                          11
+#define D18F3x74_Reserved_11_11_WIDTH                           1
+#define D18F3x74_Reserved_11_11_MASK                            0x800
+#define D18F3x74_DnPreqCBC_OFFSET                               12
+#define D18F3x74_DnPreqCBC_WIDTH                                3
+#define D18F3x74_DnPreqCBC_MASK                                 0x7000
+#define D18F3x74_Reserved_15_15_OFFSET                          15
+#define D18F3x74_Reserved_15_15_WIDTH                           1
+#define D18F3x74_Reserved_15_15_MASK                            0x8000
+#define D18F3x74_ProbeCBC_OFFSET                                16
+#define D18F3x74_ProbeCBC_WIDTH                                 4
+#define D18F3x74_ProbeCBC_MASK                                  0xf0000
+#define D18F3x74_IsocReqCBC_OFFSET                              20
+#define D18F3x74_IsocReqCBC_WIDTH                               4
+#define D18F3x74_IsocReqCBC_MASK                                0xf00000
+#define D18F3x74_IsocPreqCBC_OFFSET                             24
+#define D18F3x74_IsocPreqCBC_WIDTH                              3
+#define D18F3x74_IsocPreqCBC_MASK                               0x7000000
+#define D18F3x74_Reserved_27_27_OFFSET                          27
+#define D18F3x74_Reserved_27_27_WIDTH                           1
+#define D18F3x74_Reserved_27_27_MASK                            0x8000000
+#define D18F3x74_DRReqCBC_OFFSET                                28
+#define D18F3x74_DRReqCBC_WIDTH                                 4
+#define D18F3x74_DRReqCBC_MASK                                  0xf0000000
+
+/// D18F3x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqCBC:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                 DnReqCBC:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                UpPreqCBC:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                                DnPreqCBC:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                 ProbeCBC:4 ; ///<
+    UINT32                                               IsocReqCBC:4 ; ///<
+    UINT32                                              IsocPreqCBC:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                                 DRReqCBC:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x74_STRUCT;
+
+// **** D18F3x78 Register Definition ****
+// Address
+#define D18F3x78_ADDRESS                                        0x78
+
+// Type
+#define D18F3x78_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x78_RspCBC_OFFSET                                  0
+#define D18F3x78_RspCBC_WIDTH                                   5
+#define D18F3x78_RspCBC_MASK                                    0x1f
+#define D18F3x78_Reserved_7_5_OFFSET                            5
+#define D18F3x78_Reserved_7_5_WIDTH                             3
+#define D18F3x78_Reserved_7_5_MASK                              0xe0
+#define D18F3x78_ProbeCBC_OFFSET                                8
+#define D18F3x78_ProbeCBC_WIDTH                                 5
+#define D18F3x78_ProbeCBC_MASK                                  0x1f00
+#define D18F3x78_Reserved_15_13_OFFSET                          13
+#define D18F3x78_Reserved_15_13_WIDTH                           3
+#define D18F3x78_Reserved_15_13_MASK                            0xe000
+#define D18F3x78_RspDBC_OFFSET                                  16
+#define D18F3x78_RspDBC_WIDTH                                   6
+#define D18F3x78_RspDBC_MASK                                    0x3f0000
+#define D18F3x78_Reserved_31_22_OFFSET                          22
+#define D18F3x78_Reserved_31_22_WIDTH                           10
+#define D18F3x78_Reserved_31_22_MASK                            0xffc00000
+
+/// D18F3x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   RspCBC:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                 ProbeCBC:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   RspDBC:6 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x78_STRUCT;
+
+// **** D18F3x7C Register Definition ****
+// Address
+#define D18F3x7C_ADDRESS                                        0x7c
+
+// Type
+#define D18F3x7C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x7C_Xbar2SriFreeListCBC_OFFSET                     0
+#define D18F3x7C_Xbar2SriFreeListCBC_WIDTH                      5
+#define D18F3x7C_Xbar2SriFreeListCBC_MASK                       0x1f
+#define D18F3x7C_Reserved_7_5_OFFSET                            5
+#define D18F3x7C_Reserved_7_5_WIDTH                             3
+#define D18F3x7C_Reserved_7_5_MASK                              0xe0
+#define D18F3x7C_Sri2XbarFreeXreqCBC_OFFSET                     8
+#define D18F3x7C_Sri2XbarFreeXreqCBC_WIDTH                      4
+#define D18F3x7C_Sri2XbarFreeXreqCBC_MASK                       0xf00
+#define D18F3x7C_Sri2XbarFreeRspCBC_OFFSET                      12
+#define D18F3x7C_Sri2XbarFreeRspCBC_WIDTH                       4
+#define D18F3x7C_Sri2XbarFreeRspCBC_MASK                        0xf000
+#define D18F3x7C_Sri2XbarFreeXreqDBC_OFFSET                     16
+#define D18F3x7C_Sri2XbarFreeXreqDBC_WIDTH                      4
+#define D18F3x7C_Sri2XbarFreeXreqDBC_MASK                       0xf0000
+#define D18F3x7C_Sri2XbarFreeRspDBC_OFFSET                      20
+#define D18F3x7C_Sri2XbarFreeRspDBC_WIDTH                       3
+#define D18F3x7C_Sri2XbarFreeRspDBC_MASK                        0x700000
+#define D18F3x7C_ExtSrqFreeList_OFFSET                          23
+#define D18F3x7C_ExtSrqFreeList_WIDTH                           4
+#define D18F3x7C_ExtSrqFreeList_MASK                            0x7800000
+#define D18F3x7C_Reserved_27_27_OFFSET                          27
+#define D18F3x7C_Reserved_27_27_WIDTH                           1
+#define D18F3x7C_Reserved_27_27_MASK                            0x8000000
+#define D18F3x7C_Xbar2SriFreeListCBInc_OFFSET                   28
+#define D18F3x7C_Xbar2SriFreeListCBInc_WIDTH                    3
+#define D18F3x7C_Xbar2SriFreeListCBInc_MASK                     0x70000000
+#define D18F3x7C_Reserved_31_31_OFFSET                          31
+#define D18F3x7C_Reserved_31_31_WIDTH                           1
+#define D18F3x7C_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      Xbar2SriFreeListCBC:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                      Sri2XbarFreeXreqCBC:4 ; ///<
+    UINT32                                       Sri2XbarFreeRspCBC:4 ; ///<
+    UINT32                                      Sri2XbarFreeXreqDBC:4 ; ///<
+    UINT32                                       Sri2XbarFreeRspDBC:3 ; ///<
+    UINT32                                           ExtSrqFreeList:4 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                    Xbar2SriFreeListCBInc:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x7C_STRUCT;
+
+// **** D18F3x80 Register Definition ****
+// Address
+#define D18F3x80_ADDRESS                                        0x80
+
+// Type
+#define D18F3x80_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x80_CpuPrbEnSmafAct0_OFFSET                        0
+#define D18F3x80_CpuPrbEnSmafAct0_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct0_MASK                          0x1
+#define D18F3x80_NbLowPwrEnSmafAct0_OFFSET                      1
+#define D18F3x80_NbLowPwrEnSmafAct0_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct0_MASK                        0x2
+#define D18F3x80_NbGateEnSmafAct0_OFFSET                        2
+#define D18F3x80_NbGateEnSmafAct0_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct0_MASK                          0x4
+#define D18F3x80_Reserved_4_3_OFFSET                            3
+#define D18F3x80_Reserved_4_3_WIDTH                             2
+#define D18F3x80_Reserved_4_3_MASK                              0x18
+#define D18F3x80_ClkDivisorSmafAct0_OFFSET                      5
+#define D18F3x80_ClkDivisorSmafAct0_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct0_MASK                        0xe0
+#define D18F3x80_CpuPrbEnSmafAct1_OFFSET                        8
+#define D18F3x80_CpuPrbEnSmafAct1_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct1_MASK                          0x100
+#define D18F3x80_NbLowPwrEnSmafAct1_OFFSET                      9
+#define D18F3x80_NbLowPwrEnSmafAct1_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct1_MASK                        0x200
+#define D18F3x80_NbGateEnSmafAct1_OFFSET                        10
+#define D18F3x80_NbGateEnSmafAct1_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct1_MASK                          0x400
+#define D18F3x80_Reserved_12_11_OFFSET                          11
+#define D18F3x80_Reserved_12_11_WIDTH                           2
+#define D18F3x80_Reserved_12_11_MASK                            0x1800
+#define D18F3x80_ClkDivisorSmafAct1_OFFSET                      13
+#define D18F3x80_ClkDivisorSmafAct1_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct1_MASK                        0xe000
+#define D18F3x80_CpuPrbEnSmafAct2_OFFSET                        16
+#define D18F3x80_CpuPrbEnSmafAct2_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct2_MASK                          0x10000
+#define D18F3x80_NbLowPwrEnSmafAct2_OFFSET                      17
+#define D18F3x80_NbLowPwrEnSmafAct2_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct2_MASK                        0x20000
+#define D18F3x80_NbGateEnSmafAct2_OFFSET                        18
+#define D18F3x80_NbGateEnSmafAct2_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct2_MASK                          0x40000
+#define D18F3x80_Reserved_20_19_OFFSET                          19
+#define D18F3x80_Reserved_20_19_WIDTH                           2
+#define D18F3x80_Reserved_20_19_MASK                            0x180000
+#define D18F3x80_ClkDivisorSmafAct2_OFFSET                      21
+#define D18F3x80_ClkDivisorSmafAct2_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct2_MASK                        0xe00000
+#define D18F3x80_CpuPrbEnSmafAct3_OFFSET                        24
+#define D18F3x80_CpuPrbEnSmafAct3_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct3_MASK                          0x1000000
+#define D18F3x80_NbLowPwrEnSmafAct3_OFFSET                      25
+#define D18F3x80_NbLowPwrEnSmafAct3_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct3_MASK                        0x2000000
+#define D18F3x80_NbGateEnSmafAct3_OFFSET                        26
+#define D18F3x80_NbGateEnSmafAct3_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct3_MASK                          0x4000000
+#define D18F3x80_Reserved_28_27_OFFSET                          27
+#define D18F3x80_Reserved_28_27_WIDTH                           2
+#define D18F3x80_Reserved_28_27_MASK                            0x18000000
+#define D18F3x80_ClkDivisorSmafAct3_OFFSET                      29
+#define D18F3x80_ClkDivisorSmafAct3_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct3_MASK                        0xe0000000
+
+/// D18F3x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CpuPrbEnSmafAct0:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct0:1 ; ///<
+    UINT32                                         NbGateEnSmafAct0:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct0:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct1:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct1:1 ; ///<
+    UINT32                                         NbGateEnSmafAct1:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct1:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct2:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct2:1 ; ///<
+    UINT32                                         NbGateEnSmafAct2:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct2:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct3:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct3:1 ; ///<
+    UINT32                                         NbGateEnSmafAct3:1 ; ///<
+    UINT32                                           Reserved_28_27:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x80_STRUCT;
+
+// **** D18F3x84 Register Definition ****
+// Address
+#define D18F3x84_ADDRESS                                        0x84
+
+// Type
+#define D18F3x84_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x84_CpuPrbEnSmafAct4_OFFSET                        0
+#define D18F3x84_CpuPrbEnSmafAct4_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct4_MASK                          0x1
+#define D18F3x84_NbLowPwrEnSmafAct4_OFFSET                      1
+#define D18F3x84_NbLowPwrEnSmafAct4_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct4_MASK                        0x2
+#define D18F3x84_NbGateEnSmafAct4_OFFSET                        2
+#define D18F3x84_NbGateEnSmafAct4_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct4_MASK                          0x4
+#define D18F3x84_Reserved_4_3_OFFSET                            3
+#define D18F3x84_Reserved_4_3_WIDTH                             2
+#define D18F3x84_Reserved_4_3_MASK                              0x18
+#define D18F3x84_ClkDivisorSmafAct4_OFFSET                      5
+#define D18F3x84_ClkDivisorSmafAct4_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct4_MASK                        0xe0
+#define D18F3x84_CpuPrbEnSmafAct5_OFFSET                        8
+#define D18F3x84_CpuPrbEnSmafAct5_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct5_MASK                          0x100
+#define D18F3x84_NbLowPwrEnSmafAct5_OFFSET                      9
+#define D18F3x84_NbLowPwrEnSmafAct5_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct5_MASK                        0x200
+#define D18F3x84_NbGateEnSmafAct5_OFFSET                        10
+#define D18F3x84_NbGateEnSmafAct5_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct5_MASK                          0x400
+#define D18F3x84_Reserved_12_11_OFFSET                          11
+#define D18F3x84_Reserved_12_11_WIDTH                           2
+#define D18F3x84_Reserved_12_11_MASK                            0x1800
+#define D18F3x84_ClkDivisorSmafAct5_OFFSET                      13
+#define D18F3x84_ClkDivisorSmafAct5_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct5_MASK                        0xe000
+#define D18F3x84_CpuPrbEnSmafAct6_OFFSET                        16
+#define D18F3x84_CpuPrbEnSmafAct6_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct6_MASK                          0x10000
+#define D18F3x84_NbLowPwrEnSmafAct6_OFFSET                      17
+#define D18F3x84_NbLowPwrEnSmafAct6_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct6_MASK                        0x20000
+#define D18F3x84_NbGateEnSmafAct6_OFFSET                        18
+#define D18F3x84_NbGateEnSmafAct6_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct6_MASK                          0x40000
+#define D18F3x84_Reserved_20_19_OFFSET                          19
+#define D18F3x84_Reserved_20_19_WIDTH                           2
+#define D18F3x84_Reserved_20_19_MASK                            0x180000
+#define D18F3x84_ClkDivisorSmafAct6_OFFSET                      21
+#define D18F3x84_ClkDivisorSmafAct6_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct6_MASK                        0xe00000
+#define D18F3x84_CpuPrbEnSmafAct7_OFFSET                        24
+#define D18F3x84_CpuPrbEnSmafAct7_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct7_MASK                          0x1000000
+#define D18F3x84_NbLowPwrEnSmafAct7_OFFSET                      25
+#define D18F3x84_NbLowPwrEnSmafAct7_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct7_MASK                        0x2000000
+#define D18F3x84_NbGateEnSmafAct7_OFFSET                        26
+#define D18F3x84_NbGateEnSmafAct7_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct7_MASK                          0x4000000
+#define D18F3x84_Reserved_28_27_OFFSET                          27
+#define D18F3x84_Reserved_28_27_WIDTH                           2
+#define D18F3x84_Reserved_28_27_MASK                            0x18000000
+#define D18F3x84_ClkDivisorSmafAct7_OFFSET                      29
+#define D18F3x84_ClkDivisorSmafAct7_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct7_MASK                        0xe0000000
+
+/// D18F3x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CpuPrbEnSmafAct4:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct4:1 ; ///<
+    UINT32                                         NbGateEnSmafAct4:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct4:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct5:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct5:1 ; ///<
+    UINT32                                         NbGateEnSmafAct5:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct5:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct6:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct6:1 ; ///<
+    UINT32                                         NbGateEnSmafAct6:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct6:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct7:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct7:1 ; ///<
+    UINT32                                         NbGateEnSmafAct7:1 ; ///<
+    UINT32                                           Reserved_28_27:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct7:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x84_STRUCT;
+
+// **** D18F3x88 Register Definition ****
+// Address
+#define D18F3x88_ADDRESS                                        0x88
+
+// Type
+#define D18F3x88_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x88_Reserved_30_0_OFFSET                           0
+#define D18F3x88_Reserved_30_0_WIDTH                            31
+#define D18F3x88_Reserved_30_0_MASK                             0x7fffffff
+#define D18F3x88_DisCohLdtCfg_OFFSET                            31
+#define D18F3x88_DisCohLdtCfg_WIDTH                             1
+#define D18F3x88_DisCohLdtCfg_MASK                              0x80000000
+
+/// D18F3x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_30_0:31; ///<
+    UINT32                                             DisCohLdtCfg:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x88_STRUCT;
+
+// **** D18F3x8C Register Definition ****
+// Address
+#define D18F3x8C_ADDRESS                                        0x8c
+
+// Type
+#define D18F3x8C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x8C_Reserved_35_32_OFFSET                          0
+#define D18F3x8C_Reserved_35_32_WIDTH                           4
+#define D18F3x8C_Reserved_35_32_MASK                            0xf
+#define D18F3x8C_DisDatMsk_OFFSET                               4
+#define D18F3x8C_DisDatMsk_WIDTH                                1
+#define D18F3x8C_DisDatMsk_MASK                                 0x10
+#define D18F3x8C_Reserved_44_37_OFFSET                          5
+#define D18F3x8C_Reserved_44_37_WIDTH                           8
+#define D18F3x8C_Reserved_44_37_MASK                            0x1fe0
+#define D18F3x8C_DisUsSysMgtReqToNcHt_OFFSET                    13
+#define D18F3x8C_DisUsSysMgtReqToNcHt_WIDTH                     1
+#define D18F3x8C_DisUsSysMgtReqToNcHt_MASK                      0x2000
+#define D18F3x8C_EnableCf8ExtCfg_OFFSET                         14
+#define D18F3x8C_EnableCf8ExtCfg_WIDTH                          1
+#define D18F3x8C_EnableCf8ExtCfg_MASK                           0x4000
+#define D18F3x8C_Reserved_49_47_OFFSET                          15
+#define D18F3x8C_Reserved_49_47_WIDTH                           3
+#define D18F3x8C_Reserved_49_47_MASK                            0x38000
+#define D18F3x8C_DisOrderRdRsp_OFFSET                           18
+#define D18F3x8C_DisOrderRdRsp_WIDTH                            1
+#define D18F3x8C_DisOrderRdRsp_MASK                             0x40000
+#define D18F3x8C_Reserved_53_51_OFFSET                          19
+#define D18F3x8C_Reserved_53_51_WIDTH                           3
+#define D18F3x8C_Reserved_53_51_MASK                            0x380000
+#define D18F3x8C_InitApicIdCpuIdLo_OFFSET                       22
+#define D18F3x8C_InitApicIdCpuIdLo_WIDTH                        1
+#define D18F3x8C_InitApicIdCpuIdLo_MASK                         0x400000
+#define D18F3x8C_Reserved_63_55_OFFSET                          23
+#define D18F3x8C_Reserved_63_55_WIDTH                           9
+#define D18F3x8C_Reserved_63_55_MASK                            0xff800000
+
+/// D18F3x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           Reserved_35_32:4 ; ///<
+    UINT32                                                DisDatMsk:1 ; ///<
+    UINT32                                           Reserved_44_37:8 ; ///<
+    UINT32                                     DisUsSysMgtReqToNcHt:1 ; ///<
+    UINT32                                          EnableCf8ExtCfg:1 ; ///<
+    UINT32                                           Reserved_49_47:3 ; ///<
+    UINT32                                            DisOrderRdRsp:1 ; ///<
+    UINT32                                           Reserved_53_51:3 ; ///<
+    UINT32                                        InitApicIdCpuIdLo:1 ; ///<
+    UINT32                                           Reserved_63_55:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x8C_STRUCT;
+
+// **** D18F3xA0 Register Definition ****
+// Address
+#define D18F3xA0_ADDRESS                                        0xa0
+
+// Type
+#define D18F3xA0_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xA0_PsiVid_6_0__OFFSET                             0
+#define D18F3xA0_PsiVid_6_0__WIDTH                              7
+#define D18F3xA0_PsiVid_6_0__MASK                               0x7f
+#define D18F3xA0_PsiVidEn_OFFSET                                7
+#define D18F3xA0_PsiVidEn_WIDTH                                 1
+#define D18F3xA0_PsiVidEn_MASK                                  0x80
+#define D18F3xA0_PsiVid_7__OFFSET                               8
+#define D18F3xA0_PsiVid_7__WIDTH                                1
+#define D18F3xA0_PsiVid_7__MASK                                 0x100
+#define D18F3xA0_Reserved_10_9_OFFSET                           9
+#define D18F3xA0_Reserved_10_9_WIDTH                            2
+#define D18F3xA0_Reserved_10_9_MASK                             0x600
+#define D18F3xA0_PllLockTime_OFFSET                             11
+#define D18F3xA0_PllLockTime_WIDTH                              3
+#define D18F3xA0_PllLockTime_MASK                               0x3800
+#define D18F3xA0_Svi2HighFreqSel_OFFSET                         14
+#define D18F3xA0_Svi2HighFreqSel_WIDTH                          1
+#define D18F3xA0_Svi2HighFreqSel_MASK                           0x4000
+#define D18F3xA0_Reserved_15_15_OFFSET                          15
+#define D18F3xA0_Reserved_15_15_WIDTH                           1
+#define D18F3xA0_Reserved_15_15_MASK                            0x8000
+#define D18F3xA0_ConfigId_OFFSET                                16
+#define D18F3xA0_ConfigId_WIDTH                                 12
+#define D18F3xA0_ConfigId_MASK                                  0xfff0000
+#define D18F3xA0_Reserved_30_28_OFFSET                          28
+#define D18F3xA0_Reserved_30_28_WIDTH                           3
+#define D18F3xA0_Reserved_30_28_MASK                            0x70000000
+#define D18F3xA0_CofVidProg_OFFSET                              31
+#define D18F3xA0_CofVidProg_WIDTH                               1
+#define D18F3xA0_CofVidProg_MASK                                0x80000000
+
+/// D18F3xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              PsiVid_6_0_:7 ; ///<
+    UINT32                                                 PsiVidEn:1 ; ///<
+    UINT32                                                PsiVid_7_:1 ; ///<
+    UINT32                                            Reserved_10_9:2 ; ///<
+    UINT32                                              PllLockTime:3 ; ///<
+    UINT32                                          Svi2HighFreqSel:1 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                 ConfigId:12; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                               CofVidProg:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xA0_STRUCT;
+
+// **** D18F3xA4 Register Definition ****
+// Address
+#define D18F3xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F3xA4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xA4_PerStepTimeUp_OFFSET                           0
+#define D18F3xA4_PerStepTimeUp_WIDTH                            5
+#define D18F3xA4_PerStepTimeUp_MASK                             0x1f
+#define D18F3xA4_TmpMaxDiffUp_OFFSET                            5
+#define D18F3xA4_TmpMaxDiffUp_WIDTH                             2
+#define D18F3xA4_TmpMaxDiffUp_MASK                              0x60
+#define D18F3xA4_TmpSlewDnEn_OFFSET                             7
+#define D18F3xA4_TmpSlewDnEn_WIDTH                              1
+#define D18F3xA4_TmpSlewDnEn_MASK                               0x80
+#define D18F3xA4_PerStepTimeDn_OFFSET                           8
+#define D18F3xA4_PerStepTimeDn_WIDTH                            5
+#define D18F3xA4_PerStepTimeDn_MASK                             0x1f00
+#define D18F3xA4_Reserved_15_13_OFFSET                          13
+#define D18F3xA4_Reserved_15_13_WIDTH                           3
+#define D18F3xA4_Reserved_15_13_MASK                            0xe000
+#define D18F3xA4_CurTmpTjSel_OFFSET                             16
+#define D18F3xA4_CurTmpTjSel_WIDTH                              2
+#define D18F3xA4_CurTmpTjSel_MASK                               0x30000
+#define D18F3xA4_Reserved_19_18_OFFSET                          18
+#define D18F3xA4_Reserved_19_18_WIDTH                           2
+#define D18F3xA4_Reserved_19_18_MASK                            0xc0000
+#define D18F3xA4_TcenPwrDnCc6En_OFFSET                          20
+#define D18F3xA4_TcenPwrDnCc6En_WIDTH                           1
+#define D18F3xA4_TcenPwrDnCc6En_MASK                            0x100000
+#define D18F3xA4_CurTmp_OFFSET                                  21
+#define D18F3xA4_CurTmp_WIDTH                                   11
+#define D18F3xA4_CurTmp_MASK                                    0xffe00000
+
+/// D18F3xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PerStepTimeUp:5 ; ///<
+    UINT32                                             TmpMaxDiffUp:2 ; ///<
+    UINT32                                              TmpSlewDnEn:1 ; ///<
+    UINT32                                            PerStepTimeDn:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                              CurTmpTjSel:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                           TcenPwrDnCc6En:1 ; ///<
+    UINT32                                                   CurTmp:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xA4_STRUCT;
+
+// **** D18F3xA8 Register Definition ****
+// Address
+#define D18F3xA8_ADDRESS                                        0xa8
+
+// Type
+#define D18F3xA8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xA8_Reserved_28_0_OFFSET                           0
+#define D18F3xA8_Reserved_28_0_WIDTH                            29
+#define D18F3xA8_Reserved_28_0_MASK                             0x1fffffff
+#define D18F3xA8_PopDownPstate_OFFSET                           29
+#define D18F3xA8_PopDownPstate_WIDTH                            3
+#define D18F3xA8_PopDownPstate_MASK                             0xe0000000
+
+/// D18F3xA8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_28_0:29; ///<
+    UINT32                                            PopDownPstate:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xA8_STRUCT;
+
+
+// **** D18F3xD4 Register Definition ****
+// Address
+#define D18F3xD4_ADDRESS                                        0xd4
+
+// Type
+#define D18F3xD4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xD4_MaxSwPstateCpuCof_OFFSET                       0
+#define D18F3xD4_MaxSwPstateCpuCof_WIDTH                        6
+#define D18F3xD4_MaxSwPstateCpuCof_MASK                         0x3f
+#define D18F3xD4_Reserved_7_6_OFFSET                            6
+#define D18F3xD4_Reserved_7_6_WIDTH                             2
+#define D18F3xD4_Reserved_7_6_MASK                              0xc0
+#define D18F3xD4_ClkRampHystSel_OFFSET                          8
+#define D18F3xD4_ClkRampHystSel_WIDTH                           4
+#define D18F3xD4_ClkRampHystSel_MASK                            0xf00
+#define D18F3xD4_ClkRampHystCtl_OFFSET                          12
+#define D18F3xD4_ClkRampHystCtl_WIDTH                           1
+#define D18F3xD4_ClkRampHystCtl_MASK                            0x1000
+#define D18F3xD4_Reserved_13_13_OFFSET                          13
+#define D18F3xD4_Reserved_13_13_WIDTH                           1
+#define D18F3xD4_Reserved_13_13_MASK                            0x2000
+#define D18F3xD4_CacheFlushImmOnAllHalt_OFFSET                  14
+#define D18F3xD4_CacheFlushImmOnAllHalt_WIDTH                   1
+#define D18F3xD4_CacheFlushImmOnAllHalt_MASK                    0x4000
+#define D18F3xD4_Reserved_17_15_OFFSET                          15
+#define D18F3xD4_Reserved_17_15_WIDTH                           3
+#define D18F3xD4_Reserved_17_15_MASK                            0x38000
+#define D18F3xD4_Reserved_19_18_OFFSET                          18
+#define D18F3xD4_Reserved_19_18_WIDTH                           2
+#define D18F3xD4_Reserved_19_18_MASK                            0xc0000
+#define D18F3xD4_PowerStepDown_OFFSET                           20
+#define D18F3xD4_PowerStepDown_WIDTH                            4
+#define D18F3xD4_PowerStepDown_MASK                             0xf00000
+#define D18F3xD4_PowerStepUp_OFFSET                             24
+#define D18F3xD4_PowerStepUp_WIDTH                              4
+#define D18F3xD4_PowerStepUp_MASK                               0xf000000
+#define D18F3xD4_NbClkDiv_OFFSET                                28
+#define D18F3xD4_NbClkDiv_WIDTH                                 3
+#define D18F3xD4_NbClkDiv_MASK                                  0x70000000
+#define D18F3xD4_NbClkDivApplyAll_OFFSET                        31
+#define D18F3xD4_NbClkDivApplyAll_WIDTH                         1
+#define D18F3xD4_NbClkDivApplyAll_MASK                          0x80000000
+
+/// D18F3xD4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        MaxSwPstateCpuCof:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           ClkRampHystSel:4 ; ///<
+    UINT32                                           ClkRampHystCtl:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                   CacheFlushImmOnAllHalt:1 ; ///<
+    UINT32                                           Reserved_17_15:3 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                            PowerStepDown:4 ; ///<
+    UINT32                                              PowerStepUp:4 ; ///<
+    UINT32                                                 NbClkDiv:3 ; ///<
+    UINT32                                         NbClkDivApplyAll:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xD4_STRUCT;
+
+// **** D18F3xD8 Register Definition ****
+// Address
+#define D18F3xD8_ADDRESS                                        0xd8
+
+// Type
+#define D18F3xD8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xD8_Reserved_3_0_OFFSET                            0
+#define D18F3xD8_Reserved_3_0_WIDTH                             4
+#define D18F3xD8_Reserved_3_0_MASK                              0xf
+#define D18F3xD8_VSRampSlamTime_OFFSET                          4
+#define D18F3xD8_VSRampSlamTime_WIDTH                           3
+#define D18F3xD8_VSRampSlamTime_MASK                            0x70
+#define D18F3xD8_Reserved_31_7_OFFSET                           7
+#define D18F3xD8_Reserved_31_7_WIDTH                            25
+#define D18F3xD8_Reserved_31_7_MASK                             0xffffff80
+
+/// D18F3xD8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                           VSRampSlamTime:3 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xD8_STRUCT;
+
+// **** D18F3xDC Register Definition ****
+// Address
+#define D18F3xDC_ADDRESS                                        0xdc
+
+// Type
+#define D18F3xDC_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xDC_Reserved_7_0_OFFSET                            0
+#define D18F3xDC_Reserved_7_0_WIDTH                             8
+#define D18F3xDC_Reserved_7_0_MASK                              0xff
+#define D18F3xDC_PstateMaxVal_OFFSET                            8
+#define D18F3xDC_PstateMaxVal_WIDTH                             3
+#define D18F3xDC_PstateMaxVal_MASK                              0x700
+#define D18F3xDC_Reserved_11_11_OFFSET                          11
+#define D18F3xDC_Reserved_11_11_WIDTH                           1
+#define D18F3xDC_Reserved_11_11_MASK                            0x800
+#define D18F3xDC_NbsynPtrAdj_OFFSET                             12
+#define D18F3xDC_NbsynPtrAdj_WIDTH                              3
+#define D18F3xDC_NbsynPtrAdj_MASK                               0x7000
+#define D18F3xDC_Reserved_15_15_OFFSET                          15
+#define D18F3xDC_Reserved_15_15_WIDTH                           1
+#define D18F3xDC_Reserved_15_15_MASK                            0x8000
+#define D18F3xDC_CacheFlushOnHaltCtl_OFFSET                     16
+#define D18F3xDC_CacheFlushOnHaltCtl_WIDTH                      3
+#define D18F3xDC_CacheFlushOnHaltCtl_MASK                       0x70000
+#define D18F3xDC_CacheFlushOnHaltTmr_OFFSET                     19
+#define D18F3xDC_CacheFlushOnHaltTmr_WIDTH                      7
+#define D18F3xDC_CacheFlushOnHaltTmr_MASK                       0x3f80000
+#define D18F3xDC_IgnCpuPrbEn_OFFSET                             26
+#define D18F3xDC_IgnCpuPrbEn_WIDTH                              1
+#define D18F3xDC_IgnCpuPrbEn_MASK                               0x4000000
+#define D18F3xDC_Reserved_31_27_OFFSET                          27
+#define D18F3xDC_Reserved_31_27_WIDTH                           5
+#define D18F3xDC_Reserved_31_27_MASK                            0xf8000000
+
+/// D18F3xDC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                             PstateMaxVal:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              NbsynPtrAdj:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                      CacheFlushOnHaltCtl:3 ; ///<
+    UINT32                                      CacheFlushOnHaltTmr:7 ; ///<
+    UINT32                                              IgnCpuPrbEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xDC_STRUCT;
+
+// **** D18F3xE4 Register Definition ****
+// Address
+#define D18F3xE4_ADDRESS                                        0xe4
+
+// Type
+#define D18F3xE4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xE4_Reserved_0_0_OFFSET                            0
+#define D18F3xE4_Reserved_0_0_WIDTH                             1
+#define D18F3xE4_Reserved_0_0_MASK                              0x1
+#define D18F3xE4_Thermtp_OFFSET                                 1
+#define D18F3xE4_Thermtp_WIDTH                                  1
+#define D18F3xE4_Thermtp_MASK                                   0x2
+#define D18F3xE4_Reserved_2_2_OFFSET                            2
+#define D18F3xE4_Reserved_2_2_WIDTH                             1
+#define D18F3xE4_Reserved_2_2_MASK                              0x4
+#define D18F3xE4_ThermtpSense_OFFSET                            3
+#define D18F3xE4_ThermtpSense_WIDTH                             1
+#define D18F3xE4_ThermtpSense_MASK                              0x8
+#define D18F3xE4_Reserved_4_4_OFFSET                            4
+#define D18F3xE4_Reserved_4_4_WIDTH                             1
+#define D18F3xE4_Reserved_4_4_MASK                              0x10
+#define D18F3xE4_ThermtpEn_OFFSET                               5
+#define D18F3xE4_ThermtpEn_WIDTH                                1
+#define D18F3xE4_ThermtpEn_MASK                                 0x20
+#define D18F3xE4_Reserved_30_6_OFFSET                           6
+#define D18F3xE4_Reserved_30_6_WIDTH                            25
+#define D18F3xE4_Reserved_30_6_MASK                             0x7fffffc0
+#define D18F3xE4_SwThermtp_OFFSET                               31
+#define D18F3xE4_SwThermtp_WIDTH                                1
+#define D18F3xE4_SwThermtp_MASK                                 0x80000000
+
+/// D18F3xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  Thermtp:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             ThermtpSense:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                                ThermtpEn:1 ; ///<
+    UINT32                                            Reserved_30_6:25; ///<
+    UINT32                                                SwThermtp:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xE4_STRUCT;
+
+// **** D18F3xE8 Register Definition ****
+// Address
+#define D18F3xE8_ADDRESS                                        0xe8
+
+// Type
+#define D18F3xE8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xE8_Reserved_0_0_OFFSET                            0
+#define D18F3xE8_Reserved_0_0_WIDTH                             1
+#define D18F3xE8_Reserved_0_0_MASK                              0x1
+#define D18F3xE8_DualNode_OFFSET                                1
+#define D18F3xE8_DualNode_WIDTH                                 1
+#define D18F3xE8_DualNode_MASK                                  0x2
+#define D18F3xE8_EightNode_OFFSET                               2
+#define D18F3xE8_EightNode_WIDTH                                1
+#define D18F3xE8_EightNode_MASK                                 0x4
+#define D18F3xE8_ECC_OFFSET                                     3
+#define D18F3xE8_ECC_WIDTH                                      1
+#define D18F3xE8_ECC_MASK                                       0x8
+#define D18F3xE8_ChipKill_OFFSET                                4
+#define D18F3xE8_ChipKill_WIDTH                                 1
+#define D18F3xE8_ChipKill_MASK                                  0x10
+#define D18F3xE8_Reserved_7_5_OFFSET                            5
+#define D18F3xE8_Reserved_7_5_WIDTH                             3
+#define D18F3xE8_Reserved_7_5_MASK                              0xe0
+#define D18F3xE8_MctCap_OFFSET                                  8
+#define D18F3xE8_MctCap_WIDTH                                   1
+#define D18F3xE8_MctCap_MASK                                    0x100
+#define D18F3xE8_SvmCapable_OFFSET                              9
+#define D18F3xE8_SvmCapable_WIDTH                               1
+#define D18F3xE8_SvmCapable_MASK                                0x200
+#define D18F3xE8_HtcCapable_OFFSET                              10
+#define D18F3xE8_HtcCapable_WIDTH                               1
+#define D18F3xE8_HtcCapable_MASK                                0x400
+#define D18F3xE8_Reserved_11_11_OFFSET                          11
+#define D18F3xE8_Reserved_11_11_WIDTH                           1
+#define D18F3xE8_Reserved_11_11_MASK                            0x800
+#define D18F3xE8_Reserved_13_12_OFFSET                          12
+#define D18F3xE8_Reserved_13_12_WIDTH                           2
+#define D18F3xE8_Reserved_13_12_MASK                            0x3000
+#define D18F3xE8_MultVidPlane_OFFSET                            14
+#define D18F3xE8_MultVidPlane_WIDTH                             1
+#define D18F3xE8_MultVidPlane_MASK                              0x4000
+#define D18F3xE8_Reserved_15_15_OFFSET                          15
+#define D18F3xE8_Reserved_15_15_WIDTH                           1
+#define D18F3xE8_Reserved_15_15_MASK                            0x8000
+#define D18F3xE8_Reserved_18_16_OFFSET                          16
+#define D18F3xE8_Reserved_18_16_WIDTH                           3
+#define D18F3xE8_Reserved_18_16_MASK                            0x70000
+#define D18F3xE8_x2Apic_OFFSET                                  19
+#define D18F3xE8_x2Apic_WIDTH                                   1
+#define D18F3xE8_x2Apic_MASK                                    0x80000
+#define D18F3xE8_Reserved_23_20_OFFSET                          20
+#define D18F3xE8_Reserved_23_20_WIDTH                           4
+#define D18F3xE8_Reserved_23_20_MASK                            0xf00000
+#define D18F3xE8_MemPstateCap_OFFSET                            24
+#define D18F3xE8_MemPstateCap_WIDTH                             1
+#define D18F3xE8_MemPstateCap_MASK                              0x1000000
+#define D18F3xE8_L3Capable_OFFSET                               25
+#define D18F3xE8_L3Capable_WIDTH                                1
+#define D18F3xE8_L3Capable_MASK                                 0x2000000
+#define D18F3xE8_Reserved_28_26_OFFSET                          26
+#define D18F3xE8_Reserved_28_26_WIDTH                           3
+#define D18F3xE8_Reserved_28_26_MASK                            0x1c000000
+#define D18F3xE8_Reserved_31_29_OFFSET                          29
+#define D18F3xE8_Reserved_31_29_WIDTH                           3
+#define D18F3xE8_Reserved_31_29_MASK                            0xe0000000
+
+/// D18F3xE8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                 DualNode:1 ; ///<
+    UINT32                                                EightNode:1 ; ///<
+    UINT32                                                      ECC:1 ; ///<
+    UINT32                                                 ChipKill:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                   MctCap:1 ; ///<
+    UINT32                                               SvmCapable:1 ; ///<
+    UINT32                                               HtcCapable:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           Reserved_13_12:2 ; ///<
+    UINT32                                             MultVidPlane:1 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                                   x2Apic:1 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             MemPstateCap:1 ; ///<
+    UINT32                                                L3Capable:1 ; ///<
+    UINT32                                           Reserved_28_26:3 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xE8_STRUCT;
+
+// **** D18F3xFC Register Definition ****
+// Address
+#define D18F3xFC_ADDRESS                                        0xfc
+
+// Type
+#define D18F3xFC_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xFC_Stepping_OFFSET                                0
+#define D18F3xFC_Stepping_WIDTH                                 4
+#define D18F3xFC_Stepping_MASK                                  0xf
+#define D18F3xFC_BaseModel_OFFSET                               4
+#define D18F3xFC_BaseModel_WIDTH                                4
+#define D18F3xFC_BaseModel_MASK                                 0xf0
+#define D18F3xFC_BaseFamily_OFFSET                              8
+#define D18F3xFC_BaseFamily_WIDTH                               4
+#define D18F3xFC_BaseFamily_MASK                                0xf00
+#define D18F3xFC_Reserved_15_12_OFFSET                          12
+#define D18F3xFC_Reserved_15_12_WIDTH                           4
+#define D18F3xFC_Reserved_15_12_MASK                            0xf000
+#define D18F3xFC_ExtModel_OFFSET                                16
+#define D18F3xFC_ExtModel_WIDTH                                 4
+#define D18F3xFC_ExtModel_MASK                                  0xf0000
+#define D18F3xFC_ExtFamily_OFFSET                               20
+#define D18F3xFC_ExtFamily_WIDTH                                8
+#define D18F3xFC_ExtFamily_MASK                                 0xff00000
+#define D18F3xFC_Reserved_31_28_OFFSET                          28
+#define D18F3xFC_Reserved_31_28_WIDTH                           4
+#define D18F3xFC_Reserved_31_28_MASK                            0xf0000000
+
+/// D18F3xFC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Stepping:4 ; ///<
+    UINT32                                                BaseModel:4 ; ///<
+    UINT32                                               BaseFamily:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                 ExtModel:4 ; ///<
+    UINT32                                                ExtFamily:8 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xFC_STRUCT;
+
+// **** D18F3x140 Register Definition ****
+// Address
+#define D18F3x140_ADDRESS                                       0x140
+
+// Type
+#define D18F3x140_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x140_UpReqTok_OFFSET                               0
+#define D18F3x140_UpReqTok_WIDTH                                2
+#define D18F3x140_UpReqTok_MASK                                 0x3
+#define D18F3x140_DnReqTok_OFFSET                               2
+#define D18F3x140_DnReqTok_WIDTH                                2
+#define D18F3x140_DnReqTok_MASK                                 0xc
+#define D18F3x140_UpPreqTok_OFFSET                              4
+#define D18F3x140_UpPreqTok_WIDTH                               2
+#define D18F3x140_UpPreqTok_MASK                                0x30
+#define D18F3x140_DnPreqTok_OFFSET                              6
+#define D18F3x140_DnPreqTok_WIDTH                               2
+#define D18F3x140_DnPreqTok_MASK                                0xc0
+#define D18F3x140_UpRspTok_OFFSET                               8
+#define D18F3x140_UpRspTok_WIDTH                                2
+#define D18F3x140_UpRspTok_MASK                                 0x300
+#define D18F3x140_DnRspTok_OFFSET                               10
+#define D18F3x140_DnRspTok_WIDTH                                2
+#define D18F3x140_DnRspTok_MASK                                 0xc00
+#define D18F3x140_IsocReqTok_OFFSET                             12
+#define D18F3x140_IsocReqTok_WIDTH                              2
+#define D18F3x140_IsocReqTok_MASK                               0x3000
+#define D18F3x140_IsocPreqTok_OFFSET                            14
+#define D18F3x140_IsocPreqTok_WIDTH                             2
+#define D18F3x140_IsocPreqTok_MASK                              0xc000
+#define D18F3x140_IsocRspTok_OFFSET                             16
+#define D18F3x140_IsocRspTok_WIDTH                              2
+#define D18F3x140_IsocRspTok_MASK                               0x30000
+#define D18F3x140_Reserved_19_18_OFFSET                         18
+#define D18F3x140_Reserved_19_18_WIDTH                          2
+#define D18F3x140_Reserved_19_18_MASK                           0xc0000
+#define D18F3x140_FreeTok_OFFSET                                20
+#define D18F3x140_FreeTok_WIDTH                                 4
+#define D18F3x140_FreeTok_MASK                                  0xf00000
+#define D18F3x140_Reserved_31_24_OFFSET                         24
+#define D18F3x140_Reserved_31_24_WIDTH                          8
+#define D18F3x140_Reserved_31_24_MASK                           0xff000000
+
+/// D18F3x140
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqTok:2 ; ///<
+    UINT32                                                 DnReqTok:2 ; ///<
+    UINT32                                                UpPreqTok:2 ; ///<
+    UINT32                                                DnPreqTok:2 ; ///<
+    UINT32                                                 UpRspTok:2 ; ///<
+    UINT32                                                 DnRspTok:2 ; ///<
+    UINT32                                               IsocReqTok:2 ; ///<
+    UINT32                                              IsocPreqTok:2 ; ///<
+    UINT32                                               IsocRspTok:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                  FreeTok:4 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x140_STRUCT;
+
+// **** D18F3x144 Register Definition ****
+// Address
+#define D18F3x144_ADDRESS                                       0x144
+
+// Type
+#define D18F3x144_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x144_RspTok_OFFSET                                 0
+#define D18F3x144_RspTok_WIDTH                                  4
+#define D18F3x144_RspTok_MASK                                   0xf
+#define D18F3x144_ProbeTok_OFFSET                               4
+#define D18F3x144_ProbeTok_WIDTH                                4
+#define D18F3x144_ProbeTok_MASK                                 0xf0
+#define D18F3x144_Reserved_31_8_OFFSET                          8
+#define D18F3x144_Reserved_31_8_WIDTH                           24
+#define D18F3x144_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F3x144
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   RspTok:4 ; ///<
+    UINT32                                                 ProbeTok:4 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x144_STRUCT;
+
+// **** D18F3x148 Register Definition ****
+// Address
+#define D18F3x148_ADDRESS                                       0x148
+
+// Type
+#define D18F3x148_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x148_ReqTok0_OFFSET                                0
+#define D18F3x148_ReqTok0_WIDTH                                 2
+#define D18F3x148_ReqTok0_MASK                                  0x3
+#define D18F3x148_PReqTok0_OFFSET                               2
+#define D18F3x148_PReqTok0_WIDTH                                2
+#define D18F3x148_PReqTok0_MASK                                 0xc
+#define D18F3x148_RspTok0_OFFSET                                4
+#define D18F3x148_RspTok0_WIDTH                                 2
+#define D18F3x148_RspTok0_MASK                                  0x30
+#define D18F3x148_ProbeTok0_OFFSET                              6
+#define D18F3x148_ProbeTok0_WIDTH                               2
+#define D18F3x148_ProbeTok0_MASK                                0xc0
+#define D18F3x148_IsocReqTok0_OFFSET                            8
+#define D18F3x148_IsocReqTok0_WIDTH                             2
+#define D18F3x148_IsocReqTok0_MASK                              0x300
+#define D18F3x148_IsocPreqTok0_OFFSET                           10
+#define D18F3x148_IsocPreqTok0_WIDTH                            2
+#define D18F3x148_IsocPreqTok0_MASK                             0xc00
+#define D18F3x148_IsocRspTok0_OFFSET                            12
+#define D18F3x148_IsocRspTok0_WIDTH                             2
+#define D18F3x148_IsocRspTok0_MASK                              0x3000
+#define D18F3x148_FreeTok_1_0__OFFSET                           14
+#define D18F3x148_FreeTok_1_0__WIDTH                            2
+#define D18F3x148_FreeTok_1_0__MASK                             0xc000
+#define D18F3x148_ReqTok1_OFFSET                                16
+#define D18F3x148_ReqTok1_WIDTH                                 2
+#define D18F3x148_ReqTok1_MASK                                  0x30000
+#define D18F3x148_PReqTok1_OFFSET                               18
+#define D18F3x148_PReqTok1_WIDTH                                2
+#define D18F3x148_PReqTok1_MASK                                 0xc0000
+#define D18F3x148_RspTok1_OFFSET                                20
+#define D18F3x148_RspTok1_WIDTH                                 2
+#define D18F3x148_RspTok1_MASK                                  0x300000
+#define D18F3x148_ProbeTok1_OFFSET                              22
+#define D18F3x148_ProbeTok1_WIDTH                               2
+#define D18F3x148_ProbeTok1_MASK                                0xc00000
+#define D18F3x148_IsocReqTok1_OFFSET                            24
+#define D18F3x148_IsocReqTok1_WIDTH                             1
+#define D18F3x148_IsocReqTok1_MASK                              0x1000000
+#define D18F3x148_Reserved_25_25_OFFSET                         25
+#define D18F3x148_Reserved_25_25_WIDTH                          1
+#define D18F3x148_Reserved_25_25_MASK                           0x2000000
+#define D18F3x148_IsocPreqTok1_OFFSET                           26
+#define D18F3x148_IsocPreqTok1_WIDTH                            1
+#define D18F3x148_IsocPreqTok1_MASK                             0x4000000
+#define D18F3x148_Reserved_27_27_OFFSET                         27
+#define D18F3x148_Reserved_27_27_WIDTH                          1
+#define D18F3x148_Reserved_27_27_MASK                           0x8000000
+#define D18F3x148_IsocRspTok1_OFFSET                            28
+#define D18F3x148_IsocRspTok1_WIDTH                             1
+#define D18F3x148_IsocRspTok1_MASK                              0x10000000
+#define D18F3x148_Reserved_29_29_OFFSET                         29
+#define D18F3x148_Reserved_29_29_WIDTH                          1
+#define D18F3x148_Reserved_29_29_MASK                           0x20000000
+#define D18F3x148_FreeTok_3_2__OFFSET                           30
+#define D18F3x148_FreeTok_3_2__WIDTH                            2
+#define D18F3x148_FreeTok_3_2__MASK                             0xc0000000
+
+/// D18F3x148
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  ReqTok0:2 ; ///<
+    UINT32                                                 PReqTok0:2 ; ///<
+    UINT32                                                  RspTok0:2 ; ///<
+    UINT32                                                ProbeTok0:2 ; ///<
+    UINT32                                              IsocReqTok0:2 ; ///<
+    UINT32                                             IsocPreqTok0:2 ; ///<
+    UINT32                                              IsocRspTok0:2 ; ///<
+    UINT32                                             FreeTok_1_0_:2 ; ///<
+    UINT32                                                  ReqTok1:2 ; ///<
+    UINT32                                                 PReqTok1:2 ; ///<
+    UINT32                                                  RspTok1:2 ; ///<
+    UINT32                                                ProbeTok1:2 ; ///<
+    UINT32                                              IsocReqTok1:1 ; ///<
+    UINT32                                           Reserved_25_25:1 ; ///<
+    UINT32                                             IsocPreqTok1:1 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                              IsocRspTok1:1 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                             FreeTok_3_2_:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x148_STRUCT;
+
+// **** D18F3x17C Register Definition ****
+// Address
+#define D18F3x17C_ADDRESS                                       0x17c
+
+// Type
+#define D18F3x17C_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x17C_SPQPrbFreeCBC_OFFSET                          0
+#define D18F3x17C_SPQPrbFreeCBC_WIDTH                           4
+#define D18F3x17C_SPQPrbFreeCBC_MASK                            0xf
+#define D18F3x17C_Reserved_31_4_OFFSET                          4
+#define D18F3x17C_Reserved_31_4_WIDTH                           28
+#define D18F3x17C_Reserved_31_4_MASK                            0xfffffff0
+
+/// D18F3x17C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            SPQPrbFreeCBC:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x17C_STRUCT;
+
+// **** D18F3x180 Register Definition ****
+// Address
+#define D18F3x180_ADDRESS                                       0x180
+
+// Type
+#define D18F3x180_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x180_Reserved_1_0_OFFSET                           0
+#define D18F3x180_Reserved_1_0_WIDTH                            2
+#define D18F3x180_Reserved_1_0_MASK                             0x3
+#define D18F3x180_WDTCntSel_3__OFFSET                           2
+#define D18F3x180_WDTCntSel_3__WIDTH                            1
+#define D18F3x180_WDTCntSel_3__MASK                             0x4
+#define D18F3x180_ChgDatErrToTgtAbort_OFFSET                    3
+#define D18F3x180_ChgDatErrToTgtAbort_WIDTH                     1
+#define D18F3x180_ChgDatErrToTgtAbort_MASK                      0x8
+#define D18F3x180_ChgMstAbortToNoErr_OFFSET                     4
+#define D18F3x180_ChgMstAbortToNoErr_WIDTH                      1
+#define D18F3x180_ChgMstAbortToNoErr_MASK                       0x10
+#define D18F3x180_DisPciCfgCpuMstAbortRsp_OFFSET                5
+#define D18F3x180_DisPciCfgCpuMstAbortRsp_WIDTH                 1
+#define D18F3x180_DisPciCfgCpuMstAbortRsp_MASK                  0x20
+#define D18F3x180_SyncFloodOnDatErr_OFFSET                      6
+#define D18F3x180_SyncFloodOnDatErr_WIDTH                       1
+#define D18F3x180_SyncFloodOnDatErr_MASK                        0x40
+#define D18F3x180_SyncFloodOnTgtAbortErr_OFFSET                 7
+#define D18F3x180_SyncFloodOnTgtAbortErr_WIDTH                  1
+#define D18F3x180_SyncFloodOnTgtAbortErr_MASK                   0x80
+#define D18F3x180_PwP2pDatErrLclPropDis_OFFSET                  18
+#define D18F3x180_PwP2pDatErrLclPropDis_WIDTH                   1
+#define D18F3x180_PwP2pDatErrLclPropDis_MASK                    0x40000
+#define D18F3x180_PwP2pDatErrRmtPropDis_OFFSET                  19
+#define D18F3x180_PwP2pDatErrRmtPropDis_WIDTH                   1
+#define D18F3x180_PwP2pDatErrRmtPropDis_MASK                    0x80000
+#define D18F3x180_SyncFloodOnL3LeakErr_OFFSET                   20
+#define D18F3x180_SyncFloodOnL3LeakErr_WIDTH                    1
+#define D18F3x180_SyncFloodOnL3LeakErr_MASK                     0x100000
+#define D18F3x180_SyncFloodOnCpuLeakErr_OFFSET                  21
+#define D18F3x180_SyncFloodOnCpuLeakErr_WIDTH                   1
+#define D18F3x180_SyncFloodOnCpuLeakErr_MASK                    0x200000
+#define D18F3x180_SyncFloodOnTblWalkErr_OFFSET                  22
+#define D18F3x180_SyncFloodOnTblWalkErr_WIDTH                   1
+#define D18F3x180_SyncFloodOnTblWalkErr_MASK                    0x400000
+#define D18F3x180_Reserved_23_23_OFFSET                         23
+#define D18F3x180_Reserved_23_23_WIDTH                          1
+#define D18F3x180_Reserved_23_23_MASK                           0x800000
+#define D18F3x180_McaLogErrAddrWdtErr_OFFSET                    24
+#define D18F3x180_McaLogErrAddrWdtErr_WIDTH                     1
+#define D18F3x180_McaLogErrAddrWdtErr_MASK                      0x1000000
+#define D18F3x180_Reserved_25_25_OFFSET                         25
+#define D18F3x180_Reserved_25_25_WIDTH                          1
+#define D18F3x180_Reserved_25_25_MASK                           0x2000000
+#define D18F3x180_ChgUcToCeEn_OFFSET                            26
+#define D18F3x180_ChgUcToCeEn_WIDTH                             1
+#define D18F3x180_ChgUcToCeEn_MASK                              0x4000000
+#define D18F3x180_Reserved_31_27_OFFSET                         27
+#define D18F3x180_Reserved_31_27_WIDTH                          5
+#define D18F3x180_Reserved_31_27_MASK                           0xf8000000
+
+/// D18F3x180
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                             WDTCntSel_3_:1 ; ///<
+    UINT32                                      ChgDatErrToTgtAbort:1 ; ///<
+    UINT32                                       ChgMstAbortToNoErr:1 ; ///<
+    UINT32                                  DisPciCfgCpuMstAbortRsp:1 ; ///<
+    UINT32                                        SyncFloodOnDatErr:1 ; ///<
+    UINT32                                   SyncFloodOnTgtAbortErr:1 ; ///<
+    UINT32                                      :1 ; ///<
+    UINT32                                     :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                           :7 ; ///<
+    UINT32                                    PwP2pDatErrLclPropDis:1 ; ///<
+    UINT32                                    PwP2pDatErrRmtPropDis:1 ; ///<
+    UINT32                                     SyncFloodOnL3LeakErr:1 ; ///<
+    UINT32                                    SyncFloodOnCpuLeakErr:1 ; ///<
+    UINT32                                    SyncFloodOnTblWalkErr:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                      McaLogErrAddrWdtErr:1 ; ///<
+    UINT32                                           Reserved_25_25:1 ; ///<
+    UINT32                                              ChgUcToCeEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x180_STRUCT;
+
+// **** D18F3x190 Register Definition ****
+// Address
+#define D18F3x190_ADDRESS                                       0x190
+
+// Type
+#define D18F3x190_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x190_DisCore_OFFSET                                0
+#define D18F3x190_DisCore_WIDTH                                 32
+#define D18F3x190_DisCore_MASK                                  0xffffffff
+
+/// D18F3x190
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DisCore:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x190_STRUCT;
+
+// **** D18F3x1A0 Register Definition ****
+// Address
+#define D18F3x1A0_ADDRESS                                       0x1a0
+
+// Type
+#define D18F3x1A0_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1A0_CpuCmdBufCnt_OFFSET                           0
+#define D18F3x1A0_CpuCmdBufCnt_WIDTH                            3
+#define D18F3x1A0_CpuCmdBufCnt_MASK                             0x7
+#define D18F3x1A0_Reserved_3_3_OFFSET                           3
+#define D18F3x1A0_Reserved_3_3_WIDTH                            1
+#define D18F3x1A0_Reserved_3_3_MASK                             0x8
+#define D18F3x1A0_Reserved_8_4_OFFSET                           4
+#define D18F3x1A0_Reserved_8_4_WIDTH                            5
+#define D18F3x1A0_Reserved_8_4_MASK                             0x1f0
+#define D18F3x1A0_Reserved_11_9_OFFSET                          9
+#define D18F3x1A0_Reserved_11_9_WIDTH                           3
+#define D18F3x1A0_Reserved_11_9_MASK                            0xe00
+#define D18F3x1A0_Reserved_14_12_OFFSET                         12
+#define D18F3x1A0_Reserved_14_12_WIDTH                          3
+#define D18F3x1A0_Reserved_14_12_MASK                           0x7000
+#define D18F3x1A0_Reserved_15_15_OFFSET                         15
+#define D18F3x1A0_Reserved_15_15_WIDTH                          1
+#define D18F3x1A0_Reserved_15_15_MASK                           0x8000
+#define D18F3x1A0_CpuToNbFreeBufCnt_OFFSET                      16
+#define D18F3x1A0_CpuToNbFreeBufCnt_WIDTH                       2
+#define D18F3x1A0_CpuToNbFreeBufCnt_MASK                        0x30000
+#define D18F3x1A0_Reserved_31_18_OFFSET                         18
+#define D18F3x1A0_Reserved_31_18_WIDTH                          14
+#define D18F3x1A0_Reserved_31_18_MASK                           0xfffc0000
+
+/// D18F3x1A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CpuCmdBufCnt:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                             Reserved_8_4:5 ; ///<
+    UINT32                                            Reserved_11_9:3 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        CpuToNbFreeBufCnt:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1A0_STRUCT;
+
+// **** D18F3x1CC Register Definition ****
+// Address
+#define D18F3x1CC_ADDRESS                                       0x1cc
+
+// Type
+#define D18F3x1CC_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1CC_LvtOffset_OFFSET                              0
+#define D18F3x1CC_LvtOffset_WIDTH                               4
+#define D18F3x1CC_LvtOffset_MASK                                0xf
+#define D18F3x1CC_Reserved_7_4_OFFSET                           4
+#define D18F3x1CC_Reserved_7_4_WIDTH                            4
+#define D18F3x1CC_Reserved_7_4_MASK                             0xf0
+#define D18F3x1CC_LvtOffsetVal_OFFSET                           8
+#define D18F3x1CC_LvtOffsetVal_WIDTH                            1
+#define D18F3x1CC_LvtOffsetVal_MASK                             0x100
+#define D18F3x1CC_Reserved_31_9_OFFSET                          9
+#define D18F3x1CC_Reserved_31_9_WIDTH                           23
+#define D18F3x1CC_Reserved_31_9_MASK                            0xfffffe00
+
+/// D18F3x1CC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LvtOffset:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             LvtOffsetVal:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1CC_STRUCT;
+
+
+// **** D18F3x1FC Register Definition ****
+// Address
+#define D18F3x1FC_ADDRESS                                       0x1fc
+
+// Type
+#define D18F3x1FC_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1FC_DiDtMode_OFFSET                               0
+#define D18F3x1FC_DiDtMode_WIDTH                                1
+#define D18F3x1FC_DiDtMode_MASK                                 0x1
+#define D18F3x1FC_DiDtCfg0_OFFSET                               1
+#define D18F3x1FC_DiDtCfg0_WIDTH                                5
+#define D18F3x1FC_DiDtCfg0_MASK                                 0x3e
+#define D18F3x1FC_DiDtCfg1_OFFSET                               6
+#define D18F3x1FC_DiDtCfg1_WIDTH                                8
+#define D18F3x1FC_DiDtCfg1_MASK                                 0x3fc0
+#define D18F3x1FC_DiDtCfg2_OFFSET                               14
+#define D18F3x1FC_DiDtCfg2_WIDTH                                2
+#define D18F3x1FC_DiDtCfg2_MASK                                 0xc000
+#define D18F3x1FC_Reserved_16_16_OFFSET                         16
+#define D18F3x1FC_Reserved_16_16_WIDTH                          1
+#define D18F3x1FC_Reserved_16_16_MASK                           0x10000
+#define D18F3x1FC_DiDtCfg4_OFFSET                               17
+#define D18F3x1FC_DiDtCfg4_WIDTH                                3
+#define D18F3x1FC_DiDtCfg4_MASK                                 0xe0000
+#define D18F3x1FC_Reserved_23_20_OFFSET                         20
+#define D18F3x1FC_Reserved_23_20_WIDTH                          4
+#define D18F3x1FC_Reserved_23_20_MASK                           0xf00000
+#define D18F3x1FC_SWDllCapTableEn_OFFSET                        24
+#define D18F3x1FC_SWDllCapTableEn_WIDTH                         1
+#define D18F3x1FC_SWDllCapTableEn_MASK                          0x1000000
+#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_OFFSET             25
+#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_WIDTH              4
+#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_MASK               0x1e000000
+
+/// D18F3x1FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 DiDtMode:1 ; ///<
+    UINT32                                                 DiDtCfg0:5 ; ///<
+    UINT32                                                 DiDtCfg1:8 ; ///<
+    UINT32                                                 DiDtCfg2:2 ; ///<
+    UINT32                                           Reserved_16_16:1 ; ///<
+    UINT32                                                 DiDtCfg4:3 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                          SWDllCapTableEn:1 ; ///<
+    UINT32                               DllProcFreqCtlIndex2Rate50:4 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1FC_STRUCT;
+
+// **** D18F4x00 Register Definition ****
+// Address
+#define D18F4x00_ADDRESS                                        0x0
+
+// Type
+#define D18F4x00_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x00_VendorID_OFFSET                                0
+#define D18F4x00_VendorID_WIDTH                                 16
+#define D18F4x00_VendorID_MASK                                  0xffff
+#define D18F4x00_DeviceID_OFFSET                                16
+#define D18F4x00_DeviceID_WIDTH                                 16
+#define D18F4x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F4x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x00_STRUCT;
+
+// **** D18F4x04 Register Definition ****
+// Address
+#define D18F4x04_ADDRESS                                        0x4
+
+// Type
+#define D18F4x04_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x04_Command_OFFSET                                 0
+#define D18F4x04_Command_WIDTH                                  16
+#define D18F4x04_Command_MASK                                   0xffff
+#define D18F4x04_Status_OFFSET                                  16
+#define D18F4x04_Status_WIDTH                                   16
+#define D18F4x04_Status_MASK                                    0xffff0000
+
+/// D18F4x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x04_STRUCT;
+
+// **** D18F4x08 Register Definition ****
+// Address
+#define D18F4x08_ADDRESS                                        0x8
+
+// Type
+#define D18F4x08_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x08_RevID_OFFSET                                   0
+#define D18F4x08_RevID_WIDTH                                    8
+#define D18F4x08_RevID_MASK                                     0xff
+#define D18F4x08_ClassCode_OFFSET                               8
+#define D18F4x08_ClassCode_WIDTH                                24
+#define D18F4x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F4x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x08_STRUCT;
+
+// **** D18F4x0C Register Definition ****
+// Address
+#define D18F4x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F4x0C_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x0C_HeaderTypeReg_OFFSET                           0
+#define D18F4x0C_HeaderTypeReg_WIDTH                            32
+#define D18F4x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F4x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x0C_STRUCT;
+
+// **** D18F4x34 Register Definition ****
+// Address
+#define D18F4x34_ADDRESS                                        0x34
+
+// Type
+#define D18F4x34_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x34_CapPtr_OFFSET                                  0
+#define D18F4x34_CapPtr_WIDTH                                   8
+#define D18F4x34_CapPtr_MASK                                    0xff
+#define D18F4x34_Reserved_31_8_OFFSET                           8
+#define D18F4x34_Reserved_31_8_WIDTH                            24
+#define D18F4x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F4x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x34_STRUCT;
+
+// **** D18F4x108 Register Definition ****
+// Address
+#define D18F4x108_ADDRESS                                       0x108
+
+// Type
+#define D18F4x108_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x108_Reserved_31_0_OFFSET                          0
+#define D18F4x108_Reserved_31_0_WIDTH                           32
+#define D18F4x108_Reserved_31_0_MASK                            0xffffffff
+
+/// D18F4x108
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x108_STRUCT;
+
+// **** D18F4x10C Register Definition ****
+// Address
+#define D18F4x10C_ADDRESS                                       0x10c
+
+// Type
+#define D18F4x10C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x10C_NodeTdpLimit_OFFSET                           0
+#define D18F4x10C_NodeTdpLimit_WIDTH                            12
+#define D18F4x10C_NodeTdpLimit_MASK                             0xfff
+#define D18F4x10C_Reserved_31_12_OFFSET                         12
+#define D18F4x10C_Reserved_31_12_WIDTH                          20
+#define D18F4x10C_Reserved_31_12_MASK                           0xfffff000
+
+/// D18F4x10C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NodeTdpLimit:12; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x10C_STRUCT;
+
+// **** D18F4x110 Register Definition ****
+// Address
+#define D18F4x110_ADDRESS                                       0x110
+
+// Type
+#define D18F4x110_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x110_CSampleTimer_OFFSET                           0
+#define D18F4x110_CSampleTimer_WIDTH                            12
+#define D18F4x110_CSampleTimer_MASK                             0xfff
+#define D18F4x110_Reserved_12_12_OFFSET                         12
+#define D18F4x110_Reserved_12_12_WIDTH                          1
+#define D18F4x110_Reserved_12_12_MASK                           0x1000
+#define D18F4x110_MinResTmr_OFFSET                              13
+#define D18F4x110_MinResTmr_WIDTH                               8
+#define D18F4x110_MinResTmr_MASK                                0x1fe000
+#define D18F4x110_Reserved_31_21_OFFSET                         21
+#define D18F4x110_Reserved_31_21_WIDTH                          11
+#define D18F4x110_Reserved_31_21_MASK                           0xffe00000
+
+/// D18F4x110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CSampleTimer:12; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                                MinResTmr:8 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x110_STRUCT;
+
+// **** D18F4x118 Register Definition ****
+// Address
+#define D18F4x118_ADDRESS                                       0x118
+
+// Type
+#define D18F4x118_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x118_CpuPrbEnCstAct0_OFFSET                        0
+#define D18F4x118_CpuPrbEnCstAct0_WIDTH                         1
+#define D18F4x118_CpuPrbEnCstAct0_MASK                          0x1
+#define D18F4x118_CacheFlushEnCstAct0_OFFSET                    1
+#define D18F4x118_CacheFlushEnCstAct0_WIDTH                     1
+#define D18F4x118_CacheFlushEnCstAct0_MASK                      0x2
+#define D18F4x118_CacheFlushTmrSelCstAct0_OFFSET                2
+#define D18F4x118_CacheFlushTmrSelCstAct0_WIDTH                 2
+#define D18F4x118_CacheFlushTmrSelCstAct0_MASK                  0xc
+#define D18F4x118_Reserved_4_4_OFFSET                           4
+#define D18F4x118_Reserved_4_4_WIDTH                            1
+#define D18F4x118_Reserved_4_4_MASK                             0x10
+#define D18F4x118_ClkDivisorCstAct0_OFFSET                      5
+#define D18F4x118_ClkDivisorCstAct0_WIDTH                       3
+#define D18F4x118_ClkDivisorCstAct0_MASK                        0xe0
+#define D18F4x118_PwrGateEnCstAct0_OFFSET                       8
+#define D18F4x118_PwrGateEnCstAct0_WIDTH                        1
+#define D18F4x118_PwrGateEnCstAct0_MASK                         0x100
+#define D18F4x118_PwrOffEnCstAct0_OFFSET                        9
+#define D18F4x118_PwrOffEnCstAct0_WIDTH                         1
+#define D18F4x118_PwrOffEnCstAct0_MASK                          0x200
+#define D18F4x118_NbPwrGate0_OFFSET                             10
+#define D18F4x118_NbPwrGate0_WIDTH                              1
+#define D18F4x118_NbPwrGate0_MASK                               0x400
+#define D18F4x118_NbClkGate0_OFFSET                             11
+#define D18F4x118_NbClkGate0_WIDTH                              1
+#define D18F4x118_NbClkGate0_MASK                               0x800
+#define D18F4x118_SelfRefr0_OFFSET                              12
+#define D18F4x118_SelfRefr0_WIDTH                               1
+#define D18F4x118_SelfRefr0_MASK                                0x1000
+#define D18F4x118_SelfRefrEarly0_OFFSET                         13
+#define D18F4x118_SelfRefrEarly0_WIDTH                          1
+#define D18F4x118_SelfRefrEarly0_MASK                           0x2000
+#define D18F4x118_Reserved_15_14_OFFSET                         14
+#define D18F4x118_Reserved_15_14_WIDTH                          2
+#define D18F4x118_Reserved_15_14_MASK                           0xc000
+#define D18F4x118_CpuPrbEnCstAct1_OFFSET                        16
+#define D18F4x118_CpuPrbEnCstAct1_WIDTH                         1
+#define D18F4x118_CpuPrbEnCstAct1_MASK                          0x10000
+#define D18F4x118_CacheFlushEnCstAct1_OFFSET                    17
+#define D18F4x118_CacheFlushEnCstAct1_WIDTH                     1
+#define D18F4x118_CacheFlushEnCstAct1_MASK                      0x20000
+#define D18F4x118_CacheFlushTmrSelCstAct1_OFFSET                18
+#define D18F4x118_CacheFlushTmrSelCstAct1_WIDTH                 2
+#define D18F4x118_CacheFlushTmrSelCstAct1_MASK                  0xc0000
+#define D18F4x118_Reserved_20_20_OFFSET                         20
+#define D18F4x118_Reserved_20_20_WIDTH                          1
+#define D18F4x118_Reserved_20_20_MASK                           0x100000
+#define D18F4x118_ClkDivisorCstAct1_OFFSET                      21
+#define D18F4x118_ClkDivisorCstAct1_WIDTH                       3
+#define D18F4x118_ClkDivisorCstAct1_MASK                        0xe00000
+#define D18F4x118_PwrGateEnCstAct1_OFFSET                       24
+#define D18F4x118_PwrGateEnCstAct1_WIDTH                        1
+#define D18F4x118_PwrGateEnCstAct1_MASK                         0x1000000
+#define D18F4x118_PwrOffEnCstAct1_OFFSET                        25
+#define D18F4x118_PwrOffEnCstAct1_WIDTH                         1
+#define D18F4x118_PwrOffEnCstAct1_MASK                          0x2000000
+#define D18F4x118_NbPwrGate1_OFFSET                             26
+#define D18F4x118_NbPwrGate1_WIDTH                              1
+#define D18F4x118_NbPwrGate1_MASK                               0x4000000
+#define D18F4x118_NbClkGate1_OFFSET                             27
+#define D18F4x118_NbClkGate1_WIDTH                              1
+#define D18F4x118_NbClkGate1_MASK                               0x8000000
+#define D18F4x118_SelfRefr1_OFFSET                              28
+#define D18F4x118_SelfRefr1_WIDTH                               1
+#define D18F4x118_SelfRefr1_MASK                                0x10000000
+#define D18F4x118_SelfRefrEarly1_OFFSET                         29
+#define D18F4x118_SelfRefrEarly1_WIDTH                          1
+#define D18F4x118_SelfRefrEarly1_MASK                           0x20000000
+#define D18F4x118_Reserved_31_30_OFFSET                         30
+#define D18F4x118_Reserved_31_30_WIDTH                          2
+#define D18F4x118_Reserved_31_30_MASK                           0xc0000000
+
+/// D18F4x118
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CpuPrbEnCstAct0:1 ; ///<
+    UINT32                                      CacheFlushEnCstAct0:1 ; ///<
+    UINT32                                  CacheFlushTmrSelCstAct0:2 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                        ClkDivisorCstAct0:3 ; ///<
+    UINT32                                         PwrGateEnCstAct0:1 ; ///<
+    UINT32                                          PwrOffEnCstAct0:1 ; ///<
+    UINT32                                               NbPwrGate0:1 ; ///<
+    UINT32                                               NbClkGate0:1 ; ///<
+    UINT32                                                SelfRefr0:1 ; ///<
+    UINT32                                           SelfRefrEarly0:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                          CpuPrbEnCstAct1:1 ; ///<
+    UINT32                                      CacheFlushEnCstAct1:1 ; ///<
+    UINT32                                  CacheFlushTmrSelCstAct1:2 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                        ClkDivisorCstAct1:3 ; ///<
+    UINT32                                         PwrGateEnCstAct1:1 ; ///<
+    UINT32                                          PwrOffEnCstAct1:1 ; ///<
+    UINT32                                               NbPwrGate1:1 ; ///<
+    UINT32                                               NbClkGate1:1 ; ///<
+    UINT32                                                SelfRefr1:1 ; ///<
+    UINT32                                           SelfRefrEarly1:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x118_STRUCT;
+
+// **** D18F4x11C Register Definition ****
+// Address
+#define D18F4x11C_ADDRESS                                       0x11c
+
+// Type
+#define D18F4x11C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x11C_CpuPrbEnCstAct2_OFFSET                        0
+#define D18F4x11C_CpuPrbEnCstAct2_WIDTH                         1
+#define D18F4x11C_CpuPrbEnCstAct2_MASK                          0x1
+#define D18F4x11C_CacheFlushEnCstAct2_OFFSET                    1
+#define D18F4x11C_CacheFlushEnCstAct2_WIDTH                     1
+#define D18F4x11C_CacheFlushEnCstAct2_MASK                      0x2
+#define D18F4x11C_CacheFlushTmrSelCstAct2_OFFSET                2
+#define D18F4x11C_CacheFlushTmrSelCstAct2_WIDTH                 2
+#define D18F4x11C_CacheFlushTmrSelCstAct2_MASK                  0xc
+#define D18F4x11C_Reserved_4_4_OFFSET                           4
+#define D18F4x11C_Reserved_4_4_WIDTH                            1
+#define D18F4x11C_Reserved_4_4_MASK                             0x10
+#define D18F4x11C_ClkDivisorCstAct2_OFFSET                      5
+#define D18F4x11C_ClkDivisorCstAct2_WIDTH                       3
+#define D18F4x11C_ClkDivisorCstAct2_MASK                        0xe0
+#define D18F4x11C_PwrGateEnCstAct2_OFFSET                       8
+#define D18F4x11C_PwrGateEnCstAct2_WIDTH                        1
+#define D18F4x11C_PwrGateEnCstAct2_MASK                         0x100
+#define D18F4x11C_PwrOffEnCstAct2_OFFSET                        9
+#define D18F4x11C_PwrOffEnCstAct2_WIDTH                         1
+#define D18F4x11C_PwrOffEnCstAct2_MASK                          0x200
+#define D18F4x11C_NbPwrGate2_OFFSET                             10
+#define D18F4x11C_NbPwrGate2_WIDTH                              1
+#define D18F4x11C_NbPwrGate2_MASK                               0x400
+#define D18F4x11C_NbClkGate2_OFFSET                             11
+#define D18F4x11C_NbClkGate2_WIDTH                              1
+#define D18F4x11C_NbClkGate2_MASK                               0x800
+#define D18F4x11C_SelfRefr2_OFFSET                              12
+#define D18F4x11C_SelfRefr2_WIDTH                               1
+#define D18F4x11C_SelfRefr2_MASK                                0x1000
+#define D18F4x11C_SelfRefrEarly2_OFFSET                         13
+#define D18F4x11C_SelfRefrEarly2_WIDTH                          1
+#define D18F4x11C_SelfRefrEarly2_MASK                           0x2000
+#define D18F4x11C_Reserved_31_14_OFFSET                         14
+#define D18F4x11C_Reserved_31_14_WIDTH                          18
+#define D18F4x11C_Reserved_31_14_MASK                           0xffffc000
+
+/// D18F4x11C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CpuPrbEnCstAct2:1 ; ///<
+    UINT32                                      CacheFlushEnCstAct2:1 ; ///<
+    UINT32                                  CacheFlushTmrSelCstAct2:2 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                        ClkDivisorCstAct2:3 ; ///<
+    UINT32                                         PwrGateEnCstAct2:1 ; ///<
+    UINT32                                          PwrOffEnCstAct2:1 ; ///<
+    UINT32                                               NbPwrGate2:1 ; ///<
+    UINT32                                               NbClkGate2:1 ; ///<
+    UINT32                                                SelfRefr2:1 ; ///<
+    UINT32                                           SelfRefrEarly2:1 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x11C_STRUCT;
+
+// **** D18F4x124 Register Definition ****
+// Address
+#define D18F4x124_ADDRESS                                       0x124
+
+// Type
+#define D18F4x124_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x124_Reserved_21_0_OFFSET                          0
+#define D18F4x124_Reserved_21_0_WIDTH                           22
+#define D18F4x124_Reserved_21_0_MASK                            0x3fffff
+#define D18F4x124_IntMonPC6En_OFFSET                            22
+#define D18F4x124_IntMonPC6En_WIDTH                             1
+#define D18F4x124_IntMonPC6En_MASK                              0x400000
+#define D18F4x124_IntMonPC6Limit_OFFSET                         23
+#define D18F4x124_IntMonPC6Limit_WIDTH                          4
+#define D18F4x124_IntMonPC6Limit_MASK                           0x7800000
+#define D18F4x124_Reserved_31_27_OFFSET                         27
+#define D18F4x124_Reserved_31_27_WIDTH                          5
+#define D18F4x124_Reserved_31_27_MASK                           0xf8000000
+
+/// D18F4x124
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_21_0:22; ///<
+    UINT32                                              IntMonPC6En:1 ; ///<
+    UINT32                                           IntMonPC6Limit:4 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x124_STRUCT;
+
+// **** D18F4x128 Register Definition ****
+// Address
+#define D18F4x128_ADDRESS                                       0x128
+
+// Type
+#define D18F4x128_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x128_Reserved_0_0_OFFSET                           0
+#define D18F4x128_Reserved_0_0_WIDTH                            1
+#define D18F4x128_Reserved_0_0_MASK                             0x1
+#define D18F4x128_CoreCstatePolicy_OFFSET                       1
+#define D18F4x128_CoreCstatePolicy_WIDTH                        1
+#define D18F4x128_CoreCstatePolicy_MASK                         0x2
+#define D18F4x128_HaltCstateIndex_OFFSET                        2
+#define D18F4x128_HaltCstateIndex_WIDTH                         3
+#define D18F4x128_HaltCstateIndex_MASK                          0x1c
+#define D18F4x128_CacheFlushTmr_OFFSET                          5
+#define D18F4x128_CacheFlushTmr_WIDTH                           7
+#define D18F4x128_CacheFlushTmr_MASK                            0xfe0
+#define D18F4x128_Reserved_17_12_OFFSET                         12
+#define D18F4x128_Reserved_17_12_WIDTH                          6
+#define D18F4x128_Reserved_17_12_MASK                           0x3f000
+#define D18F4x128_CacheFlushSucMonThreshold_OFFSET              18
+#define D18F4x128_CacheFlushSucMonThreshold_WIDTH               3
+#define D18F4x128_CacheFlushSucMonThreshold_MASK                0x1c0000
+#define D18F4x128_Reserved_30_21_OFFSET                         21
+#define D18F4x128_Reserved_30_21_WIDTH                          10
+#define D18F4x128_Reserved_30_21_MASK                           0x7fe00000
+#define D18F4x128_CstateMsgDis_OFFSET                           31
+#define D18F4x128_CstateMsgDis_WIDTH                            1
+#define D18F4x128_CstateMsgDis_MASK                             0x80000000
+
+/// D18F4x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                         CoreCstatePolicy:1 ; ///<
+    UINT32                                          HaltCstateIndex:3 ; ///<
+    UINT32                                            CacheFlushTmr:7 ; ///<
+    UINT32                                           Reserved_17_12:6 ; ///<
+    UINT32                                CacheFlushSucMonThreshold:3 ; ///<
+    UINT32                                           Reserved_30_21:10; ///<
+    UINT32                                             CstateMsgDis:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x128_STRUCT;
+
+// **** D18F4x13C Register Definition ****
+// Address
+#define D18F4x13C_ADDRESS                                       0x13c
+
+// Type
+#define D18F4x13C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x13C_SmuPstateLimitEn_OFFSET                       0
+#define D18F4x13C_SmuPstateLimitEn_WIDTH                        1
+#define D18F4x13C_SmuPstateLimitEn_MASK                         0x1
+#define D18F4x13C_SmuPstateLimit_OFFSET                         1
+#define D18F4x13C_SmuPstateLimit_WIDTH                          3
+#define D18F4x13C_SmuPstateLimit_MASK                           0xe
+#define D18F4x13C_Reserved_31_4_OFFSET                          4
+#define D18F4x13C_Reserved_31_4_WIDTH                           28
+#define D18F4x13C_Reserved_31_4_MASK                            0xfffffff0
+
+/// D18F4x13C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         SmuPstateLimitEn:1 ; ///<
+    UINT32                                           SmuPstateLimit:3 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x13C_STRUCT;
+
+// **** D18F4x15C Register Definition ****
+// Address
+#define D18F4x15C_ADDRESS                                       0x15c
+
+// Type
+#define D18F4x15C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x15C_BoostSrc_OFFSET                               0
+#define D18F4x15C_BoostSrc_WIDTH                                2
+#define D18F4x15C_BoostSrc_MASK                                 0x3
+#define D18F4x15C_NumBoostStates_OFFSET                         2
+#define D18F4x15C_NumBoostStates_WIDTH                          3
+#define D18F4x15C_NumBoostStates_MASK                           0x1c
+#define D18F4x15C_Reserved_6_5_OFFSET                           5
+#define D18F4x15C_Reserved_6_5_WIDTH                            2
+#define D18F4x15C_Reserved_6_5_MASK                             0x60
+#define D18F4x15C_ApmMasterEn_OFFSET                            7
+#define D18F4x15C_ApmMasterEn_WIDTH                             1
+#define D18F4x15C_ApmMasterEn_MASK                              0x80
+#define D18F4x15C_Reserved_27_8_OFFSET                          8
+#define D18F4x15C_Reserved_27_8_WIDTH                           20
+#define D18F4x15C_Reserved_27_8_MASK                            0xfffff00
+#define D18F4x15C_Reserved_30_28_OFFSET                         28
+#define D18F4x15C_Reserved_30_28_WIDTH                          3
+#define D18F4x15C_Reserved_30_28_MASK                           0x70000000
+#define D18F4x15C_BoostLock_OFFSET                              31
+#define D18F4x15C_BoostLock_WIDTH                               1
+#define D18F4x15C_BoostLock_MASK                                0x80000000
+
+/// D18F4x15C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 BoostSrc:2 ; ///<
+    UINT32                                           NumBoostStates:3 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                              ApmMasterEn:1 ; ///<
+    UINT32                                            Reserved_27_8:20; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                                BoostLock:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x15C_STRUCT;
+
+
+// **** D18F4x164 Register Definition ****
+// Address
+#define D18F4x164_ADDRESS                                       0x164
+
+// Type
+#define D18F4x164_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x164_FixedErrata_OFFSET                            0
+#define D18F4x164_FixedErrata_WIDTH                             32
+#define D18F4x164_FixedErrata_MASK                              0xffffffff
+
+/// D18F4x164
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              FixedErrata:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x164_STRUCT;
+
+// **** D18F4x16C Register Definition ****
+// Address
+#define D18F4x16C_ADDRESS                                       0x16c
+
+// Type
+#define D18F4x16C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x16C_CstateBoost_OFFSET                            6
+#define D18F4x16C_CstateBoost_WIDTH                             3
+#define D18F4x16C_CstateBoost_MASK                              0x1c0
+#define D18F4x16C_CstateCnt_OFFSET                              9
+#define D18F4x16C_CstateCnt_WIDTH                               3
+#define D18F4x16C_CstateCnt_MASK                                0xe00
+#define D18F4x16C_Reserved_31_12_OFFSET                         12
+#define D18F4x16C_Reserved_31_12_WIDTH                          20
+#define D18F4x16C_Reserved_31_12_MASK                           0xfffff000
+
+/// D18F4x16C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             :6 ; ///<
+    UINT32                                              CstateBoost:3 ; ///<
+    UINT32                                                CstateCnt:3 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x16C_STRUCT;
+
+
+// **** D18F5x00 Register Definition ****
+// Address
+#define D18F5x00_ADDRESS                                        0x0
+
+// Type
+#define D18F5x00_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x00_VendorID_OFFSET                                0
+#define D18F5x00_VendorID_WIDTH                                 16
+#define D18F5x00_VendorID_MASK                                  0xffff
+#define D18F5x00_DeviceID_OFFSET                                16
+#define D18F5x00_DeviceID_WIDTH                                 16
+#define D18F5x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F5x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x00_STRUCT;
+
+// **** D18F5x04 Register Definition ****
+// Address
+#define D18F5x04_ADDRESS                                        0x4
+
+// Type
+#define D18F5x04_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x04_Command_OFFSET                                 0
+#define D18F5x04_Command_WIDTH                                  16
+#define D18F5x04_Command_MASK                                   0xffff
+#define D18F5x04_Status_OFFSET                                  16
+#define D18F5x04_Status_WIDTH                                   16
+#define D18F5x04_Status_MASK                                    0xffff0000
+
+/// D18F5x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x04_STRUCT;
+
+// **** D18F5x08 Register Definition ****
+// Address
+#define D18F5x08_ADDRESS                                        0x8
+
+// Type
+#define D18F5x08_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x08_RevID_OFFSET                                   0
+#define D18F5x08_RevID_WIDTH                                    8
+#define D18F5x08_RevID_MASK                                     0xff
+#define D18F5x08_ClassCode_OFFSET                               8
+#define D18F5x08_ClassCode_WIDTH                                24
+#define D18F5x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F5x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x08_STRUCT;
+
+// **** D18F5x0C Register Definition ****
+// Address
+#define D18F5x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F5x0C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x0C_HeaderTypeReg_OFFSET                           0
+#define D18F5x0C_HeaderTypeReg_WIDTH                            32
+#define D18F5x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F5x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x0C_STRUCT;
+
+// **** D18F5x34 Register Definition ****
+// Address
+#define D18F5x34_ADDRESS                                        0x34
+
+// Type
+#define D18F5x34_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x34_CapPtr_OFFSET                                  0
+#define D18F5x34_CapPtr_WIDTH                                   8
+#define D18F5x34_CapPtr_MASK                                    0xff
+#define D18F5x34_Reserved_31_8_OFFSET                           8
+#define D18F5x34_Reserved_31_8_WIDTH                            24
+#define D18F5x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F5x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x34_STRUCT;
+
+// **** D18F5x40 Register Definition ****
+// Address
+#define D18F5x40_ADDRESS                                        0x40
+
+// Type
+#define D18F5x40_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x40_EventSelect_7_0__OFFSET                        0
+#define D18F5x40_EventSelect_7_0__WIDTH                         8
+#define D18F5x40_EventSelect_7_0__MASK                          0xff
+#define D18F5x40_UnitMask_OFFSET                                8
+#define D18F5x40_UnitMask_WIDTH                                 8
+#define D18F5x40_UnitMask_MASK                                  0xff00
+#define D18F5x40_Reserved_18_16_OFFSET                          16
+#define D18F5x40_Reserved_18_16_WIDTH                           3
+#define D18F5x40_Reserved_18_16_MASK                            0x70000
+#define D18F5x40_Reserved_19_19_OFFSET                          19
+#define D18F5x40_Reserved_19_19_WIDTH                           1
+#define D18F5x40_Reserved_19_19_MASK                            0x80000
+#define D18F5x40_Int_OFFSET                                     20
+#define D18F5x40_Int_WIDTH                                      1
+#define D18F5x40_Int_MASK                                       0x100000
+#define D18F5x40_Reserved_21_21_OFFSET                          21
+#define D18F5x40_Reserved_21_21_WIDTH                           1
+#define D18F5x40_Reserved_21_21_MASK                            0x200000
+#define D18F5x40_En_OFFSET                                      22
+#define D18F5x40_En_WIDTH                                       1
+#define D18F5x40_En_MASK                                        0x400000
+#define D18F5x40_Reserved_31_23_OFFSET                          23
+#define D18F5x40_Reserved_31_23_WIDTH                           9
+#define D18F5x40_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x40_STRUCT;
+
+// **** D18F5x44 Register Definition ****
+// Address
+#define D18F5x44_ADDRESS                                        0x44
+
+// Type
+#define D18F5x44_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x44_EventSelect_11_8__OFFSET                       0
+#define D18F5x44_EventSelect_11_8__WIDTH                        4
+#define D18F5x44_EventSelect_11_8__MASK                         0xf
+#define D18F5x44_Reserved_63_36_OFFSET                          4
+#define D18F5x44_Reserved_63_36_WIDTH                           28
+#define D18F5x44_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x44_STRUCT;
+
+// **** D18F5x48 Register Definition ****
+// Address
+#define D18F5x48_ADDRESS                                        0x48
+
+// Type
+#define D18F5x48_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x48_CTR_31_0__OFFSET                               0
+#define D18F5x48_CTR_31_0__WIDTH                                32
+#define D18F5x48_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x48_STRUCT;
+
+// **** D18F5x4C Register Definition ****
+// Address
+#define D18F5x4C_ADDRESS                                        0x4c
+
+// Type
+#define D18F5x4C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x4C_CTR_47_32__OFFSET                              0
+#define D18F5x4C_CTR_47_32__WIDTH                               16
+#define D18F5x4C_CTR_47_32__MASK                                0xffff
+#define D18F5x4C_RAZ_63_48_OFFSET                               16
+#define D18F5x4C_RAZ_63_48_WIDTH                                16
+#define D18F5x4C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x4C_STRUCT;
+
+// **** D18F5x50 Register Definition ****
+// Address
+#define D18F5x50_ADDRESS                                        0x50
+
+// Type
+#define D18F5x50_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x50_EventSelect_7_0__OFFSET                        0
+#define D18F5x50_EventSelect_7_0__WIDTH                         8
+#define D18F5x50_EventSelect_7_0__MASK                          0xff
+#define D18F5x50_UnitMask_OFFSET                                8
+#define D18F5x50_UnitMask_WIDTH                                 8
+#define D18F5x50_UnitMask_MASK                                  0xff00
+#define D18F5x50_Reserved_18_16_OFFSET                          16
+#define D18F5x50_Reserved_18_16_WIDTH                           3
+#define D18F5x50_Reserved_18_16_MASK                            0x70000
+#define D18F5x50_Reserved_19_19_OFFSET                          19
+#define D18F5x50_Reserved_19_19_WIDTH                           1
+#define D18F5x50_Reserved_19_19_MASK                            0x80000
+#define D18F5x50_Int_OFFSET                                     20
+#define D18F5x50_Int_WIDTH                                      1
+#define D18F5x50_Int_MASK                                       0x100000
+#define D18F5x50_Reserved_21_21_OFFSET                          21
+#define D18F5x50_Reserved_21_21_WIDTH                           1
+#define D18F5x50_Reserved_21_21_MASK                            0x200000
+#define D18F5x50_En_OFFSET                                      22
+#define D18F5x50_En_WIDTH                                       1
+#define D18F5x50_En_MASK                                        0x400000
+#define D18F5x50_Reserved_31_23_OFFSET                          23
+#define D18F5x50_Reserved_31_23_WIDTH                           9
+#define D18F5x50_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x50_STRUCT;
+
+// **** D18F5x54 Register Definition ****
+// Address
+#define D18F5x54_ADDRESS                                        0x54
+
+// Type
+#define D18F5x54_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x54_EventSelect_11_8__OFFSET                       0
+#define D18F5x54_EventSelect_11_8__WIDTH                        4
+#define D18F5x54_EventSelect_11_8__MASK                         0xf
+#define D18F5x54_Reserved_63_36_OFFSET                          4
+#define D18F5x54_Reserved_63_36_WIDTH                           28
+#define D18F5x54_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x54_STRUCT;
+
+// **** D18F5x58 Register Definition ****
+// Address
+#define D18F5x58_ADDRESS                                        0x58
+
+// Type
+#define D18F5x58_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x58_CTR_31_0__OFFSET                               0
+#define D18F5x58_CTR_31_0__WIDTH                                32
+#define D18F5x58_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x58_STRUCT;
+
+// **** D18F5x5C Register Definition ****
+// Address
+#define D18F5x5C_ADDRESS                                        0x5c
+
+// Type
+#define D18F5x5C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x5C_CTR_47_32__OFFSET                              0
+#define D18F5x5C_CTR_47_32__WIDTH                               16
+#define D18F5x5C_CTR_47_32__MASK                                0xffff
+#define D18F5x5C_RAZ_63_48_OFFSET                               16
+#define D18F5x5C_RAZ_63_48_WIDTH                                16
+#define D18F5x5C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x5C_STRUCT;
+
+// **** D18F5x60 Register Definition ****
+// Address
+#define D18F5x60_ADDRESS                                        0x60
+
+// Type
+#define D18F5x60_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x60_EventSelect_7_0__OFFSET                        0
+#define D18F5x60_EventSelect_7_0__WIDTH                         8
+#define D18F5x60_EventSelect_7_0__MASK                          0xff
+#define D18F5x60_UnitMask_OFFSET                                8
+#define D18F5x60_UnitMask_WIDTH                                 8
+#define D18F5x60_UnitMask_MASK                                  0xff00
+#define D18F5x60_Reserved_18_16_OFFSET                          16
+#define D18F5x60_Reserved_18_16_WIDTH                           3
+#define D18F5x60_Reserved_18_16_MASK                            0x70000
+#define D18F5x60_Reserved_19_19_OFFSET                          19
+#define D18F5x60_Reserved_19_19_WIDTH                           1
+#define D18F5x60_Reserved_19_19_MASK                            0x80000
+#define D18F5x60_Int_OFFSET                                     20
+#define D18F5x60_Int_WIDTH                                      1
+#define D18F5x60_Int_MASK                                       0x100000
+#define D18F5x60_Reserved_21_21_OFFSET                          21
+#define D18F5x60_Reserved_21_21_WIDTH                           1
+#define D18F5x60_Reserved_21_21_MASK                            0x200000
+#define D18F5x60_En_OFFSET                                      22
+#define D18F5x60_En_WIDTH                                       1
+#define D18F5x60_En_MASK                                        0x400000
+#define D18F5x60_Reserved_31_23_OFFSET                          23
+#define D18F5x60_Reserved_31_23_WIDTH                           9
+#define D18F5x60_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x60_STRUCT;
+
+// **** D18F5x64 Register Definition ****
+// Address
+#define D18F5x64_ADDRESS                                        0x64
+
+// Type
+#define D18F5x64_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x64_EventSelect_11_8__OFFSET                       0
+#define D18F5x64_EventSelect_11_8__WIDTH                        4
+#define D18F5x64_EventSelect_11_8__MASK                         0xf
+#define D18F5x64_Reserved_63_36_OFFSET                          4
+#define D18F5x64_Reserved_63_36_WIDTH                           28
+#define D18F5x64_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x64_STRUCT;
+
+// **** D18F5x68 Register Definition ****
+// Address
+#define D18F5x68_ADDRESS                                        0x68
+
+// Type
+#define D18F5x68_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x68_CTR_31_0__OFFSET                               0
+#define D18F5x68_CTR_31_0__WIDTH                                32
+#define D18F5x68_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x68_STRUCT;
+
+// **** D18F5x6C Register Definition ****
+// Address
+#define D18F5x6C_ADDRESS                                        0x6c
+
+// Type
+#define D18F5x6C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x6C_CTR_47_32__OFFSET                              0
+#define D18F5x6C_CTR_47_32__WIDTH                               16
+#define D18F5x6C_CTR_47_32__MASK                                0xffff
+#define D18F5x6C_RAZ_63_48_OFFSET                               16
+#define D18F5x6C_RAZ_63_48_WIDTH                                16
+#define D18F5x6C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x6C_STRUCT;
+
+// **** D18F5x70 Register Definition ****
+// Address
+#define D18F5x70_ADDRESS                                        0x70
+
+// Type
+#define D18F5x70_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x70_EventSelect_7_0__OFFSET                        0
+#define D18F5x70_EventSelect_7_0__WIDTH                         8
+#define D18F5x70_EventSelect_7_0__MASK                          0xff
+#define D18F5x70_UnitMask_OFFSET                                8
+#define D18F5x70_UnitMask_WIDTH                                 8
+#define D18F5x70_UnitMask_MASK                                  0xff00
+#define D18F5x70_Reserved_18_16_OFFSET                          16
+#define D18F5x70_Reserved_18_16_WIDTH                           3
+#define D18F5x70_Reserved_18_16_MASK                            0x70000
+#define D18F5x70_Reserved_19_19_OFFSET                          19
+#define D18F5x70_Reserved_19_19_WIDTH                           1
+#define D18F5x70_Reserved_19_19_MASK                            0x80000
+#define D18F5x70_Int_OFFSET                                     20
+#define D18F5x70_Int_WIDTH                                      1
+#define D18F5x70_Int_MASK                                       0x100000
+#define D18F5x70_Reserved_21_21_OFFSET                          21
+#define D18F5x70_Reserved_21_21_WIDTH                           1
+#define D18F5x70_Reserved_21_21_MASK                            0x200000
+#define D18F5x70_En_OFFSET                                      22
+#define D18F5x70_En_WIDTH                                       1
+#define D18F5x70_En_MASK                                        0x400000
+#define D18F5x70_Reserved_31_23_OFFSET                          23
+#define D18F5x70_Reserved_31_23_WIDTH                           9
+#define D18F5x70_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x70_STRUCT;
+
+// **** D18F5x74 Register Definition ****
+// Address
+#define D18F5x74_ADDRESS                                        0x74
+
+// Type
+#define D18F5x74_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x74_EventSelect_11_8__OFFSET                       0
+#define D18F5x74_EventSelect_11_8__WIDTH                        4
+#define D18F5x74_EventSelect_11_8__MASK                         0xf
+#define D18F5x74_Reserved_63_36_OFFSET                          4
+#define D18F5x74_Reserved_63_36_WIDTH                           28
+#define D18F5x74_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x74_STRUCT;
+
+// **** D18F5x78 Register Definition ****
+// Address
+#define D18F5x78_ADDRESS                                        0x78
+
+// Type
+#define D18F5x78_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x78_CTR_31_0__OFFSET                               0
+#define D18F5x78_CTR_31_0__WIDTH                                32
+#define D18F5x78_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x78_STRUCT;
+
+// **** D18F5x7C Register Definition ****
+// Address
+#define D18F5x7C_ADDRESS                                        0x7c
+
+// Type
+#define D18F5x7C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x7C_CTR_47_32__OFFSET                              0
+#define D18F5x7C_CTR_47_32__WIDTH                               16
+#define D18F5x7C_CTR_47_32__MASK                                0xffff
+#define D18F5x7C_RAZ_63_48_OFFSET                               16
+#define D18F5x7C_RAZ_63_48_WIDTH                                16
+#define D18F5x7C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x7C_STRUCT;
+
+// **** D18F5x80 Register Definition ****
+// Address
+#define D18F5x80_ADDRESS                                        0x80
+
+// Type
+#define D18F5x80_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x80_Enabled_OFFSET                                 0
+#define D18F5x80_Enabled_WIDTH                                  4
+#define D18F5x80_Enabled_MASK                                   0xf
+#define D18F5x80_Reserved_15_4_OFFSET                           4
+#define D18F5x80_Reserved_15_4_WIDTH                            12
+#define D18F5x80_Reserved_15_4_MASK                             0xfff0
+#define D18F5x80_DualCore_OFFSET                                16
+#define D18F5x80_DualCore_WIDTH                                 4
+#define D18F5x80_DualCore_MASK                                  0xf0000
+#define D18F5x80_Reserved_31_20_OFFSET                          20
+#define D18F5x80_Reserved_31_20_WIDTH                           12
+#define D18F5x80_Reserved_31_20_MASK                            0xfff00000
+
+/// D18F5x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Enabled:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                                 DualCore:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x80_STRUCT;
+
+// **** D18F5x84 Register Definition ****
+// Address
+#define D18F5x84_ADDRESS                                        0x84
+
+// Type
+#define D18F5x84_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x84_CmpCap_OFFSET                                  0
+#define D18F5x84_CmpCap_WIDTH                                   8
+#define D18F5x84_CmpCap_MASK                                    0xff
+#define D18F5x84_Reserved_11_8_OFFSET                           8
+#define D18F5x84_Reserved_11_8_WIDTH                            4
+#define D18F5x84_Reserved_11_8_MASK                             0xf00
+#define D18F5x84_DctEn_OFFSET                                   12
+#define D18F5x84_DctEn_WIDTH                                    2
+#define D18F5x84_DctEn_MASK                                     0x3000
+#define D18F5x84_Reserved_15_14_OFFSET                          14
+#define D18F5x84_Reserved_15_14_WIDTH                           2
+#define D18F5x84_Reserved_15_14_MASK                            0xc000
+#define D18F5x84_DdrMaxRate_OFFSET                              16
+#define D18F5x84_DdrMaxRate_WIDTH                               5
+#define D18F5x84_DdrMaxRate_MASK                                0x1f0000
+#define D18F5x84_Reserved_23_21_OFFSET                          21
+#define D18F5x84_Reserved_23_21_WIDTH                           3
+#define D18F5x84_Reserved_23_21_MASK                            0xe00000
+#define D18F5x84_DdrMaxRateEnf_OFFSET                           24
+#define D18F5x84_DdrMaxRateEnf_WIDTH                            5
+#define D18F5x84_DdrMaxRateEnf_MASK                             0x1f000000
+#define D18F5x84_Reserved_31_29_OFFSET                          29
+#define D18F5x84_Reserved_31_29_WIDTH                           3
+#define D18F5x84_Reserved_31_29_MASK                            0xe0000000
+
+/// D18F5x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CmpCap:8 ; ///<
+    UINT32                                            Reserved_11_8:4 ; ///<
+    UINT32                                                    DctEn:2 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                               DdrMaxRate:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                            DdrMaxRateEnf:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x84_STRUCT;
+
+// **** D18F5x88 Register Definition ****
+// Address
+#define D18F5x88_ADDRESS                                        0x88
+
+// Type
+#define D18F5x88_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x88_Reserved_1_0_OFFSET                            0
+#define D18F5x88_Reserved_1_0_WIDTH                             2
+#define D18F5x88_Reserved_1_0_MASK                              0x3
+#define D18F5x88_IntStpClkHaltExitEn_OFFSET                     2
+#define D18F5x88_IntStpClkHaltExitEn_WIDTH                      1
+#define D18F5x88_IntStpClkHaltExitEn_MASK                       0x4
+
+/// D18F5x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                      IntStpClkHaltExitEn:1 ; ///<
+    UINT32                                            :29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x88_STRUCT;
+
+// **** D18F5xE0 Register Definition ****
+// Address
+#define D18F5xE0_ADDRESS                                        0xe0
+
+// Type
+#define D18F5xE0_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5xE0_RunAvgRange_OFFSET                             0
+#define D18F5xE0_RunAvgRange_WIDTH                              4
+#define D18F5xE0_RunAvgRange_MASK                               0xf
+#define D18F5xE0_Reserved_31_4_OFFSET                           4
+#define D18F5xE0_Reserved_31_4_WIDTH                            28
+#define D18F5xE0_Reserved_31_4_MASK                             0xfffffff0
+
+/// D18F5xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              RunAvgRange:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5xE0_STRUCT;
+
+
+// **** D18F5x128 Register Definition ****
+// Address
+#define D18F5x128_ADDRESS                                       0x128
+
+// Type
+#define D18F5x128_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x128_PC6Vid_6_0__OFFSET                            0
+#define D18F5x128_PC6Vid_6_0__WIDTH                             7
+#define D18F5x128_PC6Vid_6_0__MASK                              0x7f
+#define D18F5x128_PllRegTime_OFFSET                             7
+#define D18F5x128_PllRegTime_WIDTH                              2
+#define D18F5x128_PllRegTime_MASK                               0x180
+#define D18F5x128_FastSlamTimeDown_OFFSET                       9
+#define D18F5x128_FastSlamTimeDown_WIDTH                        1
+#define D18F5x128_FastSlamTimeDown_MASK                         0x200
+#define D18F5x128_PllVddOutUpTime_OFFSET                        10
+#define D18F5x128_PllVddOutUpTime_WIDTH                         2
+#define D18F5x128_PllVddOutUpTime_MASK                          0xc00
+#define D18F5x128_PwrGateTmr_OFFSET                             12
+#define D18F5x128_PwrGateTmr_WIDTH                              2
+#define D18F5x128_PwrGateTmr_MASK                               0x3000
+#define D18F5x128_PC6PwrDwnRegEn_OFFSET                         14
+#define D18F5x128_PC6PwrDwnRegEn_WIDTH                          1
+#define D18F5x128_PC6PwrDwnRegEn_MASK                           0x4000
+#define D18F5x128_CC6PwrDwnRegEn_OFFSET                         15
+#define D18F5x128_CC6PwrDwnRegEn_WIDTH                          1
+#define D18F5x128_CC6PwrDwnRegEn_MASK                           0x8000
+#define D18F5x128_Reserved_20_16_OFFSET                         16
+#define D18F5x128_Reserved_20_16_WIDTH                          5
+#define D18F5x128_Reserved_20_16_MASK                           0x1f0000
+#define D18F5x128_PC6Vid_7__OFFSET                              21
+#define D18F5x128_PC6Vid_7__WIDTH                               1
+#define D18F5x128_PC6Vid_7__MASK                                0x200000
+#define D18F5x128_NbPllPwrDwnRegEn_OFFSET                       22
+#define D18F5x128_NbPllPwrDwnRegEn_WIDTH                        1
+#define D18F5x128_NbPllPwrDwnRegEn_MASK                         0x400000
+#define D18F5x128_Reserved_31_23_OFFSET                         23
+#define D18F5x128_Reserved_31_23_WIDTH                          9
+#define D18F5x128_Reserved_31_23_MASK                           0xff800000
+
+/// D18F5x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              PC6Vid_6_0_:7 ; ///<
+    UINT32                                               PllRegTime:2 ; ///<
+    UINT32                                         FastSlamTimeDown:1 ; ///<
+    UINT32                                          PllVddOutUpTime:2 ; ///<
+    UINT32                                               PwrGateTmr:2 ; ///<
+    UINT32                                           PC6PwrDwnRegEn:1 ; ///<
+    UINT32                                           CC6PwrDwnRegEn:1 ; ///<
+    UINT32                                           Reserved_20_16:5 ; ///<
+    UINT32                                                PC6Vid_7_:1 ; ///<
+    UINT32                                         NbPllPwrDwnRegEn:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x128_STRUCT;
+
+// **** D18F5x12C Register Definition ****
+// Address
+#define D18F5x12C_ADDRESS                                       0x12c
+
+// Type
+#define D18F5x12C_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x12C_CoreOffsetTrim_OFFSET                         0
+#define D18F5x12C_CoreOffsetTrim_WIDTH                          2
+#define D18F5x12C_CoreOffsetTrim_MASK                           0x3
+#define D18F5x12C_CoreLoadLineTrim_OFFSET                       2
+#define D18F5x12C_CoreLoadLineTrim_WIDTH                        3
+#define D18F5x12C_CoreLoadLineTrim_MASK                         0x1c
+#define D18F5x12C_CorePsi1En_OFFSET                             5
+#define D18F5x12C_CorePsi1En_WIDTH                              1
+#define D18F5x12C_CorePsi1En_MASK                               0x20
+#define D18F5x12C_Reserved_29_7_OFFSET                          7
+#define D18F5x12C_Reserved_29_7_WIDTH                           23
+#define D18F5x12C_Reserved_29_7_MASK                            0x3fffff80
+#define D18F5x12C_WaitVidCompDis_OFFSET                         30
+#define D18F5x12C_WaitVidCompDis_WIDTH                          1
+#define D18F5x12C_WaitVidCompDis_MASK                           0x40000000
+#define D18F5x12C_Svi2CmdBusy_OFFSET                            31
+#define D18F5x12C_Svi2CmdBusy_WIDTH                             1
+#define D18F5x12C_Svi2CmdBusy_MASK                              0x80000000
+
+/// D18F5x12C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CoreOffsetTrim:2 ; ///<
+    UINT32                                         CoreLoadLineTrim:3 ; ///<
+    UINT32                                               CorePsi1En:1 ; ///<
+    UINT32                                                  :1 ; ///<
+    UINT32                                            Reserved_29_7:23; ///<
+    UINT32                                           WaitVidCompDis:1 ; ///<
+    UINT32                                              Svi2CmdBusy:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x12C_STRUCT;
+
+
+// **** D18F5x160 Register Definition ****
+// Address
+#define D18F5x160_ADDRESS                                       0x160
+
+// Type
+#define D18F5x160_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x160_NbPstateEn_OFFSET                             0
+#define D18F5x160_NbPstateEn_WIDTH                              1
+#define D18F5x160_NbPstateEn_MASK                               0x1
+#define D18F5x160_NbFid_OFFSET                                  1
+#define D18F5x160_NbFid_WIDTH                                   6
+#define D18F5x160_NbFid_MASK                                    0x7e
+#define D18F5x160_NbDid_OFFSET                                  7
+#define D18F5x160_NbDid_WIDTH                                   1
+#define D18F5x160_NbDid_MASK                                    0x80
+#define D18F5x160_Reserved_9_8_OFFSET                           8
+#define D18F5x160_Reserved_9_8_WIDTH                            2
+#define D18F5x160_Reserved_9_8_MASK                             0x300
+#define D18F5x160_NbVid_6_0__OFFSET                             10
+#define D18F5x160_NbVid_6_0__WIDTH                              7
+#define D18F5x160_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x160_Reserved_17_17_OFFSET                         17
+#define D18F5x160_Reserved_17_17_WIDTH                          1
+#define D18F5x160_Reserved_17_17_MASK                           0x20000
+#define D18F5x160_MemPstate_OFFSET                              18
+#define D18F5x160_MemPstate_WIDTH                               1
+#define D18F5x160_MemPstate_MASK                                0x40000
+#define D18F5x160_Reserved_20_19_OFFSET                         19
+#define D18F5x160_Reserved_20_19_WIDTH                          2
+#define D18F5x160_Reserved_20_19_MASK                           0x180000
+#define D18F5x160_NbVid_7__OFFSET                               21
+#define D18F5x160_NbVid_7__WIDTH                                1
+#define D18F5x160_NbVid_7__MASK                                 0x200000
+#define D18F5x160_NbIddDiv_OFFSET                               22
+#define D18F5x160_NbIddDiv_WIDTH                                2
+#define D18F5x160_NbIddDiv_MASK                                 0xc00000
+#define D18F5x160_NbIddValue_OFFSET                             24
+#define D18F5x160_NbIddValue_WIDTH                              8
+#define D18F5x160_NbIddValue_MASK                               0xff000000
+
+/// D18F5x160
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x160_STRUCT;
+
+// **** D18F5x164 Register Definition ****
+// Address
+#define D18F5x164_ADDRESS                                       0x164
+
+// Type
+#define D18F5x164_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x164_NbPstateEn_OFFSET                             0
+#define D18F5x164_NbPstateEn_WIDTH                              1
+#define D18F5x164_NbPstateEn_MASK                               0x1
+#define D18F5x164_NbFid_OFFSET                                  1
+#define D18F5x164_NbFid_WIDTH                                   6
+#define D18F5x164_NbFid_MASK                                    0x7e
+#define D18F5x164_NbDid_OFFSET                                  7
+#define D18F5x164_NbDid_WIDTH                                   1
+#define D18F5x164_NbDid_MASK                                    0x80
+#define D18F5x164_Reserved_9_8_OFFSET                           8
+#define D18F5x164_Reserved_9_8_WIDTH                            2
+#define D18F5x164_Reserved_9_8_MASK                             0x300
+#define D18F5x164_NbVid_6_0__OFFSET                             10
+#define D18F5x164_NbVid_6_0__WIDTH                              7
+#define D18F5x164_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x164_Reserved_17_17_OFFSET                         17
+#define D18F5x164_Reserved_17_17_WIDTH                          1
+#define D18F5x164_Reserved_17_17_MASK                           0x20000
+#define D18F5x164_MemPstate_OFFSET                              18
+#define D18F5x164_MemPstate_WIDTH                               1
+#define D18F5x164_MemPstate_MASK                                0x40000
+#define D18F5x164_Reserved_20_19_OFFSET                         19
+#define D18F5x164_Reserved_20_19_WIDTH                          2
+#define D18F5x164_Reserved_20_19_MASK                           0x180000
+#define D18F5x164_NbVid_7__OFFSET                               21
+#define D18F5x164_NbVid_7__WIDTH                                1
+#define D18F5x164_NbVid_7__MASK                                 0x200000
+#define D18F5x164_NbIddDiv_OFFSET                               22
+#define D18F5x164_NbIddDiv_WIDTH                                2
+#define D18F5x164_NbIddDiv_MASK                                 0xc00000
+#define D18F5x164_NbIddValue_OFFSET                             24
+#define D18F5x164_NbIddValue_WIDTH                              8
+#define D18F5x164_NbIddValue_MASK                               0xff000000
+
+/// D18F5x164
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x164_STRUCT;
+
+// **** D18F5x168 Register Definition ****
+// Address
+#define D18F5x168_ADDRESS                                       0x168
+
+// Type
+#define D18F5x168_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x168_NbPstateEn_OFFSET                             0
+#define D18F5x168_NbPstateEn_WIDTH                              1
+#define D18F5x168_NbPstateEn_MASK                               0x1
+#define D18F5x168_NbFid_OFFSET                                  1
+#define D18F5x168_NbFid_WIDTH                                   6
+#define D18F5x168_NbFid_MASK                                    0x7e
+#define D18F5x168_NbDid_OFFSET                                  7
+#define D18F5x168_NbDid_WIDTH                                   1
+#define D18F5x168_NbDid_MASK                                    0x80
+#define D18F5x168_Reserved_9_8_OFFSET                           8
+#define D18F5x168_Reserved_9_8_WIDTH                            2
+#define D18F5x168_Reserved_9_8_MASK                             0x300
+#define D18F5x168_NbVid_6_0__OFFSET                             10
+#define D18F5x168_NbVid_6_0__WIDTH                              7
+#define D18F5x168_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x168_Reserved_17_17_OFFSET                         17
+#define D18F5x168_Reserved_17_17_WIDTH                          1
+#define D18F5x168_Reserved_17_17_MASK                           0x20000
+#define D18F5x168_MemPstate_OFFSET                              18
+#define D18F5x168_MemPstate_WIDTH                               1
+#define D18F5x168_MemPstate_MASK                                0x40000
+#define D18F5x168_Reserved_20_19_OFFSET                         19
+#define D18F5x168_Reserved_20_19_WIDTH                          2
+#define D18F5x168_Reserved_20_19_MASK                           0x180000
+#define D18F5x168_NbVid_7__OFFSET                               21
+#define D18F5x168_NbVid_7__WIDTH                                1
+#define D18F5x168_NbVid_7__MASK                                 0x200000
+#define D18F5x168_NbIddDiv_OFFSET                               22
+#define D18F5x168_NbIddDiv_WIDTH                                2
+#define D18F5x168_NbIddDiv_MASK                                 0xc00000
+#define D18F5x168_NbIddValue_OFFSET                             24
+#define D18F5x168_NbIddValue_WIDTH                              8
+#define D18F5x168_NbIddValue_MASK                               0xff000000
+
+/// D18F5x168
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x168_STRUCT;
+
+// **** D18F5x16C Register Definition ****
+// Address
+#define D18F5x16C_ADDRESS                                       0x16c
+
+// Type
+#define D18F5x16C_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x16C_NbPstateEn_OFFSET                             0
+#define D18F5x16C_NbPstateEn_WIDTH                              1
+#define D18F5x16C_NbPstateEn_MASK                               0x1
+#define D18F5x16C_NbFid_OFFSET                                  1
+#define D18F5x16C_NbFid_WIDTH                                   6
+#define D18F5x16C_NbFid_MASK                                    0x7e
+#define D18F5x16C_NbDid_OFFSET                                  7
+#define D18F5x16C_NbDid_WIDTH                                   1
+#define D18F5x16C_NbDid_MASK                                    0x80
+#define D18F5x16C_Reserved_9_8_OFFSET                           8
+#define D18F5x16C_Reserved_9_8_WIDTH                            2
+#define D18F5x16C_Reserved_9_8_MASK                             0x300
+#define D18F5x16C_NbVid_6_0__OFFSET                             10
+#define D18F5x16C_NbVid_6_0__WIDTH                              7
+#define D18F5x16C_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x16C_Reserved_17_17_OFFSET                         17
+#define D18F5x16C_Reserved_17_17_WIDTH                          1
+#define D18F5x16C_Reserved_17_17_MASK                           0x20000
+#define D18F5x16C_MemPstate_OFFSET                              18
+#define D18F5x16C_MemPstate_WIDTH                               1
+#define D18F5x16C_MemPstate_MASK                                0x40000
+#define D18F5x16C_Reserved_20_19_OFFSET                         19
+#define D18F5x16C_Reserved_20_19_WIDTH                          2
+#define D18F5x16C_Reserved_20_19_MASK                           0x180000
+#define D18F5x16C_NbVid_7__OFFSET                               21
+#define D18F5x16C_NbVid_7__WIDTH                                1
+#define D18F5x16C_NbVid_7__MASK                                 0x200000
+#define D18F5x16C_NbIddDiv_OFFSET                               22
+#define D18F5x16C_NbIddDiv_WIDTH                                2
+#define D18F5x16C_NbIddDiv_MASK                                 0xc00000
+#define D18F5x16C_NbIddValue_OFFSET                             24
+#define D18F5x16C_NbIddValue_WIDTH                              8
+#define D18F5x16C_NbIddValue_MASK                               0xff000000
+
+/// D18F5x16C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x16C_STRUCT;
+
+// **** D18F5x170 Register Definition ****
+// Address
+#define D18F5x170_ADDRESS                                       0x170
+
+// Type
+#define D18F5x170_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x170_NbPstateMaxVal_OFFSET                         0
+#define D18F5x170_NbPstateMaxVal_WIDTH                          2
+#define D18F5x170_NbPstateMaxVal_MASK                           0x3
+#define D18F5x170_Reserved_2_2_OFFSET                           2
+#define D18F5x170_Reserved_2_2_WIDTH                            1
+#define D18F5x170_Reserved_2_2_MASK                             0x4
+#define D18F5x170_NbPstateLo_OFFSET                             3
+#define D18F5x170_NbPstateLo_WIDTH                              2
+#define D18F5x170_NbPstateLo_MASK                               0x18
+#define D18F5x170_Reserved_5_5_OFFSET                           5
+#define D18F5x170_Reserved_5_5_WIDTH                            1
+#define D18F5x170_Reserved_5_5_MASK                             0x20
+#define D18F5x170_NbPstateHi_OFFSET                             6
+#define D18F5x170_NbPstateHi_WIDTH                              2
+#define D18F5x170_NbPstateHi_MASK                               0xc0
+#define D18F5x170_Reserved_8_8_OFFSET                           8
+#define D18F5x170_Reserved_8_8_WIDTH                            1
+#define D18F5x170_Reserved_8_8_MASK                             0x100
+#define D18F5x170_NbPstateThreshold_OFFSET                      9
+#define D18F5x170_NbPstateThreshold_WIDTH                       3
+#define D18F5x170_NbPstateThreshold_MASK                        0xe00
+#define D18F5x170_Reserved_12_12_OFFSET                         12
+#define D18F5x170_Reserved_12_12_WIDTH                          1
+#define D18F5x170_Reserved_12_12_MASK                           0x1000
+#define D18F5x170_NbPstateDisOnP0_OFFSET                        13
+#define D18F5x170_NbPstateDisOnP0_WIDTH                         1
+#define D18F5x170_NbPstateDisOnP0_MASK                          0x2000
+#define D18F5x170_SwNbPstateLoDis_OFFSET                        14
+#define D18F5x170_SwNbPstateLoDis_WIDTH                         1
+#define D18F5x170_SwNbPstateLoDis_MASK                          0x4000
+#define D18F5x170_Reserved_22_15_OFFSET                         15
+#define D18F5x170_Reserved_22_15_WIDTH                          8
+#define D18F5x170_Reserved_22_15_MASK                           0x7f8000
+#define D18F5x170_NbPstateGnbSlowDis_OFFSET                     23
+#define D18F5x170_NbPstateGnbSlowDis_WIDTH                      1
+#define D18F5x170_NbPstateGnbSlowDis_MASK                       0x800000
+#define D18F5x170_NbPstateLoRes_OFFSET                          24
+#define D18F5x170_NbPstateLoRes_WIDTH                           3
+#define D18F5x170_NbPstateLoRes_MASK                            0x7000000
+#define D18F5x170_NbPstateHiRes_OFFSET                          27
+#define D18F5x170_NbPstateHiRes_WIDTH                           3
+#define D18F5x170_NbPstateHiRes_MASK                            0x38000000
+#define D18F5x170_Reserved_30_30_OFFSET                         30
+#define D18F5x170_Reserved_30_30_WIDTH                          1
+#define D18F5x170_Reserved_30_30_MASK                           0x40000000
+#define D18F5x170_MemPstateDis_OFFSET                           31
+#define D18F5x170_MemPstateDis_WIDTH                            1
+#define D18F5x170_MemPstateDis_MASK                             0x80000000
+
+/// D18F5x170
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           NbPstateMaxVal:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                               NbPstateLo:2 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                               NbPstateHi:2 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                        NbPstateThreshold:3 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                          NbPstateDisOnP0:1 ; ///<
+    UINT32                                          SwNbPstateLoDis:1 ; ///<
+    UINT32                                           Reserved_22_15:8 ; ///<
+    UINT32                                       NbPstateGnbSlowDis:1 ; ///<
+    UINT32                                            NbPstateLoRes:3 ; ///<
+    UINT32                                            NbPstateHiRes:3 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             MemPstateDis:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x170_STRUCT;
+
+// **** D18F5x174 Register Definition ****
+// Address
+#define D18F5x174_ADDRESS                                       0x174
+
+// Type
+#define D18F5x174_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x174_NbPstateDis_OFFSET                            0
+#define D18F5x174_NbPstateDis_WIDTH                             1
+#define D18F5x174_NbPstateDis_MASK                              0x1
+#define D18F5x174_StartupNbPstate_OFFSET                        1
+#define D18F5x174_StartupNbPstate_WIDTH                         2
+#define D18F5x174_StartupNbPstate_MASK                          0x6
+#define D18F5x174_CurNbFid_OFFSET                               3
+#define D18F5x174_CurNbFid_WIDTH                                6
+#define D18F5x174_CurNbFid_MASK                                 0x1f8
+#define D18F5x174_CurNbDid_OFFSET                               9
+#define D18F5x174_CurNbDid_WIDTH                                1
+#define D18F5x174_CurNbDid_MASK                                 0x200
+#define D18F5x174_Reserved_11_10_OFFSET                         10
+#define D18F5x174_Reserved_11_10_WIDTH                          2
+#define D18F5x174_Reserved_11_10_MASK                           0xc00
+#define D18F5x174_CurNbVid_6_0__OFFSET                          12
+#define D18F5x174_CurNbVid_6_0__WIDTH                           7
+#define D18F5x174_CurNbVid_6_0__MASK                            0x7f000
+#define D18F5x174_CurNbPstate_OFFSET                            19
+#define D18F5x174_CurNbPstate_WIDTH                             2
+#define D18F5x174_CurNbPstate_MASK                              0x180000
+#define D18F5x174_Reserved_22_21_OFFSET                         21
+#define D18F5x174_Reserved_22_21_WIDTH                          2
+#define D18F5x174_Reserved_22_21_MASK                           0x600000
+#define D18F5x174_CurNbVid_7__OFFSET                            23
+#define D18F5x174_CurNbVid_7__WIDTH                             1
+#define D18F5x174_CurNbVid_7__MASK                              0x800000
+#define D18F5x174_CurMemPstate_OFFSET                           24
+#define D18F5x174_CurMemPstate_WIDTH                            1
+#define D18F5x174_CurMemPstate_MASK                             0x1000000
+#define D18F5x174_Reserved_31_25_OFFSET                         25
+#define D18F5x174_Reserved_31_25_WIDTH                          7
+#define D18F5x174_Reserved_31_25_MASK                           0xfe000000
+
+/// D18F5x174
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              NbPstateDis:1 ; ///<
+    UINT32                                          StartupNbPstate:2 ; ///<
+    UINT32                                                 CurNbFid:6 ; ///<
+    UINT32                                                 CurNbDid:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                                            CurNbVid_6_0_:7 ; ///<
+    UINT32                                              CurNbPstate:2 ; ///<
+    UINT32                                           Reserved_22_21:2 ; ///<
+    UINT32                                              CurNbVid_7_:1 ; ///<
+    UINT32                                             CurMemPstate:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x174_STRUCT;
+
+// **** D18F5x178 Register Definition ****
+// Address
+#define D18F5x178_ADDRESS                                       0x178
+
+// Type
+#define D18F5x178_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x178_Reserved_1_0_OFFSET                           0
+#define D18F5x178_Reserved_1_0_WIDTH                            2
+#define D18F5x178_Reserved_1_0_MASK                             0x3
+#define D18F5x178_CstateFusionDis_OFFSET                        2
+#define D18F5x178_CstateFusionDis_WIDTH                         1
+#define D18F5x178_CstateFusionDis_MASK                          0x4
+#define D18F5x178_CstateThreeWayHsEn_OFFSET                     3
+#define D18F5x178_CstateThreeWayHsEn_WIDTH                      1
+#define D18F5x178_CstateThreeWayHsEn_MASK                       0x8
+#define D18F5x178_Reserved_9_4_OFFSET                           4
+#define D18F5x178_Reserved_9_4_WIDTH                            6
+#define D18F5x178_Reserved_9_4_MASK                             0x3f0
+#define D18F5x178_InbWakeS3Dis_OFFSET                           10
+#define D18F5x178_InbWakeS3Dis_WIDTH                            1
+#define D18F5x178_InbWakeS3Dis_MASK                             0x400
+#define D18F5x178_AllowSelfRefrS3Dis_OFFSET                     11
+#define D18F5x178_AllowSelfRefrS3Dis_WIDTH                      1
+#define D18F5x178_AllowSelfRefrS3Dis_MASK                       0x800
+#define D18F5x178_CstateFusionHsDis_OFFSET                      18
+#define D18F5x178_CstateFusionHsDis_WIDTH                       1
+#define D18F5x178_CstateFusionHsDis_MASK                        0x40000
+#define D18F5x178_SwGfxDis_OFFSET                               19
+#define D18F5x178_SwGfxDis_WIDTH                                1
+#define D18F5x178_SwGfxDis_MASK                                 0x80000
+#define D18F5x178_Reserved_31_20_OFFSET                         20
+#define D18F5x178_Reserved_31_20_WIDTH                          12
+#define D18F5x178_Reserved_31_20_MASK                           0xfff00000
+
+/// D18F5x178
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                          CstateFusionDis:1 ; ///<
+    UINT32                                       CstateThreeWayHsEn:1 ; ///<
+    UINT32                                             Reserved_9_4:6 ; ///<
+    UINT32                                             InbWakeS3Dis:1 ; ///<
+    UINT32                                       AllowSelfRefrS3Dis:1 ; ///<
+    UINT32                                           :6 ; ///<
+    UINT32                                        CstateFusionHsDis:1 ; ///<
+    UINT32                                                 SwGfxDis:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x178_STRUCT;
+
+// **** D18F5x17C Register Definition ****
+// Address
+#define D18F5x17C_ADDRESS                                       0x17c
+
+// Type
+#define D18F5x17C_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x17C_MaxVid_OFFSET                                 0
+#define D18F5x17C_MaxVid_WIDTH                                  8
+#define D18F5x17C_MaxVid_MASK                                   0xff
+#define D18F5x17C_Reserved_9_8_OFFSET                           8
+#define D18F5x17C_Reserved_9_8_WIDTH                            2
+#define D18F5x17C_Reserved_9_8_MASK                             0x300
+#define D18F5x17C_MinVid_OFFSET                                 10
+#define D18F5x17C_MinVid_WIDTH                                  8
+#define D18F5x17C_MinVid_MASK                                   0x3fc00
+#define D18F5x17C_Reserved_22_18_OFFSET                         18
+#define D18F5x17C_Reserved_22_18_WIDTH                          5
+#define D18F5x17C_Reserved_22_18_MASK                           0x7c0000
+#define D18F5x17C_NbPsi0Vid_7_0__OFFSET                         23
+#define D18F5x17C_NbPsi0Vid_7_0__WIDTH                          8
+#define D18F5x17C_NbPsi0Vid_7_0__MASK                           0x7f800000
+#define D18F5x17C_NbPsi0VidEn_OFFSET                            31
+#define D18F5x17C_NbPsi0VidEn_WIDTH                             1
+#define D18F5x17C_NbPsi0VidEn_MASK                              0x80000000
+
+/// D18F5x17C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   MaxVid:8 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                                   MinVid:8 ; ///<
+    UINT32                                           Reserved_22_18:5 ; ///<
+    UINT32                                           NbPsi0Vid_7_0_:8 ; ///<
+    UINT32                                              NbPsi0VidEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x17C_STRUCT;
+
+// **** D18F5x188 Register Definition ****
+// Address
+#define D18F5x188_ADDRESS                                       0x188
+
+// Type
+#define D18F5x188_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x188_NbOffsetTrim_OFFSET                           0
+#define D18F5x188_NbOffsetTrim_WIDTH                            2
+#define D18F5x188_NbOffsetTrim_MASK                             0x3
+#define D18F5x188_NbLoadLineTrim_OFFSET                         2
+#define D18F5x188_NbLoadLineTrim_WIDTH                          3
+#define D18F5x188_NbLoadLineTrim_MASK                           0x1c
+#define D18F5x188_NbPsi1_OFFSET                                 5
+#define D18F5x188_NbPsi1_WIDTH                                  1
+#define D18F5x188_NbPsi1_MASK                                   0x20
+#define D18F5x188_Reserved_31_7_OFFSET                          7
+#define D18F5x188_Reserved_31_7_WIDTH                           25
+#define D18F5x188_Reserved_31_7_MASK                            0xffffff80
+
+/// D18F5x188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NbOffsetTrim:2 ; ///<
+    UINT32                                           NbLoadLineTrim:3 ; ///<
+    UINT32                                                   NbPsi1:1 ; ///<
+    UINT32                                                    NbTfn:1 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x188_STRUCT;
+
+// **** D18F5x194 Register Definition ****
+// Address
+#define D18F5x194_ADDRESS                                       0x194
+
+// Type
+#define D18F5x194_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x194_Index_OFFSET                                  0
+#define D18F5x194_Index_WIDTH                                   4
+#define D18F5x194_Index_MASK                                    0xf
+#define D18F5x194_Reserved_31_4_OFFSET                          4
+#define D18F5x194_Reserved_31_4_WIDTH                           28
+#define D18F5x194_Reserved_31_4_MASK                            0xfffffff0
+
+/// D18F5x194
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Index:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x194_STRUCT;
+
+// **** D18F5x198 Register Definition ****
+// Address
+#define D18F5x198_ADDRESS                                       0x198
+
+// Type
+#define D18F5x198_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x198_Data_OFFSET                                   0
+#define D18F5x198_Data_WIDTH                                    32
+#define D18F5x198_Data_MASK                                     0xffffffff
+
+/// D18F5x198
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x198_STRUCT;
+
+// **** DxF0x00 Register Definition ****
+// Address
+#define DxF0x00_ADDRESS                                         0x0
+
+// Type
+#define DxF0x00_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x00_VendorID_OFFSET                                 0
+#define DxF0x00_VendorID_WIDTH                                  16
+#define DxF0x00_VendorID_MASK                                   0xffff
+#define DxF0x00_DeviceID_OFFSET                                 16
+#define DxF0x00_DeviceID_WIDTH                                  16
+#define DxF0x00_DeviceID_MASK                                   0xffff0000
+
+/// DxF0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x00_STRUCT;
+
+// **** DxF0x04 Register Definition ****
+// Address
+#define DxF0x04_ADDRESS                                         0x4
+
+// Type
+#define DxF0x04_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x04_IoAccessEn_OFFSET                               0
+#define DxF0x04_IoAccessEn_WIDTH                                1
+#define DxF0x04_IoAccessEn_MASK                                 0x1
+#define DxF0x04_MemAccessEn_OFFSET                              1
+#define DxF0x04_MemAccessEn_WIDTH                               1
+#define DxF0x04_MemAccessEn_MASK                                0x2
+#define DxF0x04_BusMasterEn_OFFSET                              2
+#define DxF0x04_BusMasterEn_WIDTH                               1
+#define DxF0x04_BusMasterEn_MASK                                0x4
+#define DxF0x04_SpecialCycleEn_OFFSET                           3
+#define DxF0x04_SpecialCycleEn_WIDTH                            1
+#define DxF0x04_SpecialCycleEn_MASK                             0x8
+#define DxF0x04_MemWriteInvalidateEn_OFFSET                     4
+#define DxF0x04_MemWriteInvalidateEn_WIDTH                      1
+#define DxF0x04_MemWriteInvalidateEn_MASK                       0x10
+#define DxF0x04_PalSnoopEn_OFFSET                               5
+#define DxF0x04_PalSnoopEn_WIDTH                                1
+#define DxF0x04_PalSnoopEn_MASK                                 0x20
+#define DxF0x04_ParityErrorEn_OFFSET                            6
+#define DxF0x04_ParityErrorEn_WIDTH                             1
+#define DxF0x04_ParityErrorEn_MASK                              0x40
+#define DxF0x04_Stepping_OFFSET                                 7
+#define DxF0x04_Stepping_WIDTH                                  1
+#define DxF0x04_Stepping_MASK                                   0x80
+#define DxF0x04_SerrEn_OFFSET                                   8
+#define DxF0x04_SerrEn_WIDTH                                    1
+#define DxF0x04_SerrEn_MASK                                     0x100
+#define DxF0x04_FastB2BEn_OFFSET                                9
+#define DxF0x04_FastB2BEn_WIDTH                                 1
+#define DxF0x04_FastB2BEn_MASK                                  0x200
+#define DxF0x04_IntDis_OFFSET                                   10
+#define DxF0x04_IntDis_WIDTH                                    1
+#define DxF0x04_IntDis_MASK                                     0x400
+#define DxF0x04_Reserved_18_11_OFFSET                           11
+#define DxF0x04_Reserved_18_11_WIDTH                            8
+#define DxF0x04_Reserved_18_11_MASK                             0x7f800
+#define DxF0x04_IntStatus_OFFSET                                19
+#define DxF0x04_IntStatus_WIDTH                                 1
+#define DxF0x04_IntStatus_MASK                                  0x80000
+#define DxF0x04_CapList_OFFSET                                  20
+#define DxF0x04_CapList_WIDTH                                   1
+#define DxF0x04_CapList_MASK                                    0x100000
+#define DxF0x04_PCI66En_OFFSET                                  21
+#define DxF0x04_PCI66En_WIDTH                                   1
+#define DxF0x04_PCI66En_MASK                                    0x200000
+#define DxF0x04_UDFEn_OFFSET                                    22
+#define DxF0x04_UDFEn_WIDTH                                     1
+#define DxF0x04_UDFEn_MASK                                      0x400000
+#define DxF0x04_FastBackCapable_OFFSET                          23
+#define DxF0x04_FastBackCapable_WIDTH                           1
+#define DxF0x04_FastBackCapable_MASK                            0x800000
+#define DxF0x04_DataPerr_OFFSET                                 24
+#define DxF0x04_DataPerr_WIDTH                                  1
+#define DxF0x04_DataPerr_MASK                                   0x1000000
+#define DxF0x04_DevselTiming_OFFSET                             25
+#define DxF0x04_DevselTiming_WIDTH                              2
+#define DxF0x04_DevselTiming_MASK                               0x6000000
+#define DxF0x04_SignalTargetAbort_OFFSET                        27
+#define DxF0x04_SignalTargetAbort_WIDTH                         1
+#define DxF0x04_SignalTargetAbort_MASK                          0x8000000
+#define DxF0x04_ReceivedTargetAbort_OFFSET                      28
+#define DxF0x04_ReceivedTargetAbort_WIDTH                       1
+#define DxF0x04_ReceivedTargetAbort_MASK                        0x10000000
+#define DxF0x04_ReceivedMasterAbort_OFFSET                      29
+#define DxF0x04_ReceivedMasterAbort_WIDTH                       1
+#define DxF0x04_ReceivedMasterAbort_MASK                        0x20000000
+#define DxF0x04_SignaledSystemError_OFFSET                      30
+#define DxF0x04_SignaledSystemError_WIDTH                       1
+#define DxF0x04_SignaledSystemError_MASK                        0x40000000
+#define DxF0x04_ParityErrorDetected_OFFSET                      31
+#define DxF0x04_ParityErrorDetected_WIDTH                       1
+#define DxF0x04_ParityErrorDetected_MASK                        0x80000000
+
+/// DxF0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                           SpecialCycleEn:1 ; ///<
+    UINT32                                     MemWriteInvalidateEn:1 ; ///<
+    UINT32                                               PalSnoopEn:1 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                                 Stepping:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                FastB2BEn:1 ; ///<
+    UINT32                                                   IntDis:1 ; ///<
+    UINT32                                           Reserved_18_11:8 ; ///<
+    UINT32                                                IntStatus:1 ; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                                    UDFEn:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                                 DataPerr:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x04_STRUCT;
+
+// **** DxF0x08 Register Definition ****
+// Address
+#define DxF0x08_ADDRESS                                         0x8
+
+// Type
+#define DxF0x08_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x08_RevID_OFFSET                                    0
+#define DxF0x08_RevID_WIDTH                                     8
+#define DxF0x08_RevID_MASK                                      0xff
+#define DxF0x08_ClassCode_OFFSET                                8
+#define DxF0x08_ClassCode_WIDTH                                 24
+#define DxF0x08_ClassCode_MASK                                  0xffffff00
+
+/// DxF0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x08_STRUCT;
+
+// **** DxF0x0C Register Definition ****
+// Address
+#define DxF0x0C_ADDRESS                                         0xc
+
+// Type
+#define DxF0x0C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x0C_CacheLineSize_OFFSET                            0
+#define DxF0x0C_CacheLineSize_WIDTH                             8
+#define DxF0x0C_CacheLineSize_MASK                              0xff
+#define DxF0x0C_LatencyTimer_OFFSET                             8
+#define DxF0x0C_LatencyTimer_WIDTH                              8
+#define DxF0x0C_LatencyTimer_MASK                               0xff00
+#define DxF0x0C_HeaderTypeReg_OFFSET                            16
+#define DxF0x0C_HeaderTypeReg_WIDTH                             8
+#define DxF0x0C_HeaderTypeReg_MASK                              0xff0000
+#define DxF0x0C_BIST_OFFSET                                     24
+#define DxF0x0C_BIST_WIDTH                                      8
+#define DxF0x0C_BIST_MASK                                       0xff000000
+
+/// DxF0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x0C_STRUCT;
+
+// **** DxF0x18 Register Definition ****
+// Address
+#define DxF0x18_ADDRESS                                         0x18
+
+// Type
+#define DxF0x18_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x18_PrimaryBus_OFFSET                               0
+#define DxF0x18_PrimaryBus_WIDTH                                8
+#define DxF0x18_PrimaryBus_MASK                                 0xff
+#define DxF0x18_SecondaryBus_OFFSET                             8
+#define DxF0x18_SecondaryBus_WIDTH                              8
+#define DxF0x18_SecondaryBus_MASK                               0xff00
+#define DxF0x18_SubBusNumber_OFFSET                             16
+#define DxF0x18_SubBusNumber_WIDTH                              8
+#define DxF0x18_SubBusNumber_MASK                               0xff0000
+#define DxF0x18_SecondaryLatencyTimer_OFFSET                    24
+#define DxF0x18_SecondaryLatencyTimer_WIDTH                     8
+#define DxF0x18_SecondaryLatencyTimer_MASK                      0xff000000
+
+/// DxF0x18
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PrimaryBus:8 ; ///<
+    UINT32                                             SecondaryBus:8 ; ///<
+    UINT32                                             SubBusNumber:8 ; ///<
+    UINT32                                    SecondaryLatencyTimer:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x18_STRUCT;
+
+// **** DxF0x1C Register Definition ****
+// Address
+#define DxF0x1C_ADDRESS                                         0x1c
+
+// Type
+#define DxF0x1C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x1C_Reserved_3_0_OFFSET                             0
+#define DxF0x1C_Reserved_3_0_WIDTH                              4
+#define DxF0x1C_Reserved_3_0_MASK                               0xf
+#define DxF0x1C_IOBase_15_12__OFFSET                            4
+#define DxF0x1C_IOBase_15_12__WIDTH                             4
+#define DxF0x1C_IOBase_15_12__MASK                              0xf0
+#define DxF0x1C_Reserved_11_8_OFFSET                            8
+#define DxF0x1C_Reserved_11_8_WIDTH                             4
+#define DxF0x1C_Reserved_11_8_MASK                              0xf00
+#define DxF0x1C_IOLimit_15_12__OFFSET                           12
+#define DxF0x1C_IOLimit_15_12__WIDTH                            4
+#define DxF0x1C_IOLimit_15_12__MASK                             0xf000
+#define DxF0x1C_Reserved_19_16_OFFSET                           16
+#define DxF0x1C_Reserved_19_16_WIDTH                            4
+#define DxF0x1C_Reserved_19_16_MASK                             0xf0000
+#define DxF0x1C_CapList_OFFSET                                  20
+#define DxF0x1C_CapList_WIDTH                                   1
+#define DxF0x1C_CapList_MASK                                    0x100000
+#define DxF0x1C_PCI66En_OFFSET                                  21
+#define DxF0x1C_PCI66En_WIDTH                                   1
+#define DxF0x1C_PCI66En_MASK                                    0x200000
+#define DxF0x1C_UDFEn_OFFSET                                    22
+#define DxF0x1C_UDFEn_WIDTH                                     1
+#define DxF0x1C_UDFEn_MASK                                      0x400000
+#define DxF0x1C_FastBackCapable_OFFSET                          23
+#define DxF0x1C_FastBackCapable_WIDTH                           1
+#define DxF0x1C_FastBackCapable_MASK                            0x800000
+#define DxF0x1C_MasterDataPerr_OFFSET                           24
+#define DxF0x1C_MasterDataPerr_WIDTH                            1
+#define DxF0x1C_MasterDataPerr_MASK                             0x1000000
+#define DxF0x1C_DevselTiming_OFFSET                             25
+#define DxF0x1C_DevselTiming_WIDTH                              2
+#define DxF0x1C_DevselTiming_MASK                               0x6000000
+#define DxF0x1C_SignalTargetAbort_OFFSET                        27
+#define DxF0x1C_SignalTargetAbort_WIDTH                         1
+#define DxF0x1C_SignalTargetAbort_MASK                          0x8000000
+#define DxF0x1C_ReceivedTargetAbort_OFFSET                      28
+#define DxF0x1C_ReceivedTargetAbort_WIDTH                       1
+#define DxF0x1C_ReceivedTargetAbort_MASK                        0x10000000
+#define DxF0x1C_ReceivedMasterAbort_OFFSET                      29
+#define DxF0x1C_ReceivedMasterAbort_WIDTH                       1
+#define DxF0x1C_ReceivedMasterAbort_MASK                        0x20000000
+#define DxF0x1C_ReceivedSystemError_OFFSET                      30
+#define DxF0x1C_ReceivedSystemError_WIDTH                       1
+#define DxF0x1C_ReceivedSystemError_MASK                        0x40000000
+#define DxF0x1C_ParityErrorDetected_OFFSET                      31
+#define DxF0x1C_ParityErrorDetected_WIDTH                       1
+#define DxF0x1C_ParityErrorDetected_MASK                        0x80000000
+
+/// DxF0x1C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                            IOBase_15_12_:4 ; ///<
+    UINT32                                            Reserved_11_8:4 ; ///<
+    UINT32                                           IOLimit_15_12_:4 ; ///<
+    UINT32                                           Reserved_19_16:4 ; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                                    UDFEn:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                           MasterDataPerr:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      ReceivedSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x1C_STRUCT;
+
+// **** DxF0x20 Register Definition ****
+// Address
+#define DxF0x20_ADDRESS                                         0x20
+
+// Type
+#define DxF0x20_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x20_Reserved_3_0_OFFSET                             0
+#define DxF0x20_Reserved_3_0_WIDTH                              4
+#define DxF0x20_Reserved_3_0_MASK                               0xf
+#define DxF0x20_MemBase_OFFSET                                  4
+#define DxF0x20_MemBase_WIDTH                                   12
+#define DxF0x20_MemBase_MASK                                    0xfff0
+#define DxF0x20_Reserved_19_16_OFFSET                           16
+#define DxF0x20_Reserved_19_16_WIDTH                            4
+#define DxF0x20_Reserved_19_16_MASK                             0xf0000
+#define DxF0x20_MemLimit_OFFSET                                 20
+#define DxF0x20_MemLimit_WIDTH                                  12
+#define DxF0x20_MemLimit_MASK                                   0xfff00000
+
+/// DxF0x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                  MemBase:12; ///<
+    UINT32                                           Reserved_19_16:4 ; ///<
+    UINT32                                                 MemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x20_STRUCT;
+
+// **** DxF0x24 Register Definition ****
+// Address
+#define DxF0x24_ADDRESS                                         0x24
+
+// Type
+#define DxF0x24_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x24_PrefMemBaseR_OFFSET                             0
+#define DxF0x24_PrefMemBaseR_WIDTH                              4
+#define DxF0x24_PrefMemBaseR_MASK                               0xf
+#define DxF0x24_PrefMemBase_31_20__OFFSET                       4
+#define DxF0x24_PrefMemBase_31_20__WIDTH                        12
+#define DxF0x24_PrefMemBase_31_20__MASK                         0xfff0
+#define DxF0x24_PrefMemLimitR_OFFSET                            16
+#define DxF0x24_PrefMemLimitR_WIDTH                             4
+#define DxF0x24_PrefMemLimitR_MASK                              0xf0000
+#define DxF0x24_PrefMemLimit_OFFSET                             20
+#define DxF0x24_PrefMemLimit_WIDTH                              12
+#define DxF0x24_PrefMemLimit_MASK                               0xfff00000
+
+/// DxF0x24
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PrefMemBaseR:4 ; ///<
+    UINT32                                       PrefMemBase_31_20_:12; ///<
+    UINT32                                            PrefMemLimitR:4 ; ///<
+    UINT32                                             PrefMemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x24_STRUCT;
+
+// **** DxF0x28 Register Definition ****
+// Address
+#define DxF0x28_ADDRESS                                         0x28
+
+// Type
+#define DxF0x28_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x28_PrefMemBase_63_32__OFFSET                       0
+#define DxF0x28_PrefMemBase_63_32__WIDTH                        32
+#define DxF0x28_PrefMemBase_63_32__MASK                         0xffffffff
+
+/// DxF0x28
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PrefMemBase_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x28_STRUCT;
+
+// **** DxF0x2C Register Definition ****
+// Address
+#define DxF0x2C_ADDRESS                                         0x2c
+
+// Type
+#define DxF0x2C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x2C_PrefMemLimit_63_32__OFFSET                      0
+#define DxF0x2C_PrefMemLimit_63_32__WIDTH                       32
+#define DxF0x2C_PrefMemLimit_63_32__MASK                        0xffffffff
+
+/// DxF0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      PrefMemLimit_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x2C_STRUCT;
+
+// **** DxF0x30 Register Definition ****
+// Address
+#define DxF0x30_ADDRESS                                         0x30
+
+// Type
+#define DxF0x30_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x30_IOBase_31_16__OFFSET                            0
+#define DxF0x30_IOBase_31_16__WIDTH                             16
+#define DxF0x30_IOBase_31_16__MASK                              0xffff
+#define DxF0x30_IOLimit_31_16__OFFSET                           16
+#define DxF0x30_IOLimit_31_16__WIDTH                            16
+#define DxF0x30_IOLimit_31_16__MASK                             0xffff0000
+
+/// DxF0x30
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            IOBase_31_16_:16; ///<
+    UINT32                                           IOLimit_31_16_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x30_STRUCT;
+
+// **** DxF0x34 Register Definition ****
+// Address
+#define DxF0x34_ADDRESS                                         0x34
+
+// Type
+#define DxF0x34_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x34_CapPtr_OFFSET                                   0
+#define DxF0x34_CapPtr_WIDTH                                    8
+#define DxF0x34_CapPtr_MASK                                     0xff
+#define DxF0x34_Reserved_31_8_OFFSET                            8
+#define DxF0x34_Reserved_31_8_WIDTH                             24
+#define DxF0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// DxF0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x34_STRUCT;
+
+// **** DxF0x3C Register Definition ****
+// Address
+#define DxF0x3C_ADDRESS                                         0x3c
+
+// Type
+#define DxF0x3C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x3C_IntLine_OFFSET                                  0
+#define DxF0x3C_IntLine_WIDTH                                   8
+#define DxF0x3C_IntLine_MASK                                    0xff
+#define DxF0x3C_IntPin_OFFSET                                   8
+#define DxF0x3C_IntPin_WIDTH                                    3
+#define DxF0x3C_IntPin_MASK                                     0x700
+#define DxF0x3C_IntPinR_OFFSET                                  11
+#define DxF0x3C_IntPinR_WIDTH                                   5
+#define DxF0x3C_IntPinR_MASK                                    0xf800
+#define DxF0x3C_ParityResponseEn_OFFSET                         16
+#define DxF0x3C_ParityResponseEn_WIDTH                          1
+#define DxF0x3C_ParityResponseEn_MASK                           0x10000
+#define DxF0x3C_SerrEn_OFFSET                                   17
+#define DxF0x3C_SerrEn_WIDTH                                    1
+#define DxF0x3C_SerrEn_MASK                                     0x20000
+#define DxF0x3C_IsaEn_OFFSET                                    18
+#define DxF0x3C_IsaEn_WIDTH                                     1
+#define DxF0x3C_IsaEn_MASK                                      0x40000
+#define DxF0x3C_VgaEn_OFFSET                                    19
+#define DxF0x3C_VgaEn_WIDTH                                     1
+#define DxF0x3C_VgaEn_MASK                                      0x80000
+#define DxF0x3C_Vga16En_OFFSET                                  20
+#define DxF0x3C_Vga16En_WIDTH                                   1
+#define DxF0x3C_Vga16En_MASK                                    0x100000
+#define DxF0x3C_MasterAbortMode_OFFSET                          21
+#define DxF0x3C_MasterAbortMode_WIDTH                           1
+#define DxF0x3C_MasterAbortMode_MASK                            0x200000
+#define DxF0x3C_SecondaryBusReset_OFFSET                        22
+#define DxF0x3C_SecondaryBusReset_WIDTH                         1
+#define DxF0x3C_SecondaryBusReset_MASK                          0x400000
+#define DxF0x3C_FastB2BCap_OFFSET                               23
+#define DxF0x3C_FastB2BCap_WIDTH                                1
+#define DxF0x3C_FastB2BCap_MASK                                 0x800000
+#define DxF0x3C_Reserved_31_24_OFFSET                           24
+#define DxF0x3C_Reserved_31_24_WIDTH                            8
+#define DxF0x3C_Reserved_31_24_MASK                             0xff000000
+
+/// DxF0x3C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  IntLine:8 ; ///<
+    UINT32                                                   IntPin:3 ; ///<
+    UINT32                                                  IntPinR:5 ; ///<
+    UINT32                                         ParityResponseEn:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                    IsaEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                          MasterAbortMode:1 ; ///<
+    UINT32                                        SecondaryBusReset:1 ; ///<
+    UINT32                                               FastB2BCap:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x3C_STRUCT;
+
+// **** DxF0x50 Register Definition ****
+// Address
+#define DxF0x50_ADDRESS                                         0x50
+
+// Type
+#define DxF0x50_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x50_CapID_OFFSET                                    0
+#define DxF0x50_CapID_WIDTH                                     8
+#define DxF0x50_CapID_MASK                                      0xff
+#define DxF0x50_NextPtr_OFFSET                                  8
+#define DxF0x50_NextPtr_WIDTH                                   8
+#define DxF0x50_NextPtr_MASK                                    0xff00
+#define DxF0x50_Version_OFFSET                                  16
+#define DxF0x50_Version_WIDTH                                   3
+#define DxF0x50_Version_MASK                                    0x70000
+#define DxF0x50_PmeClock_OFFSET                                 19
+#define DxF0x50_PmeClock_WIDTH                                  1
+#define DxF0x50_PmeClock_MASK                                   0x80000
+#define DxF0x50_Reserved_20_20_OFFSET                           20
+#define DxF0x50_Reserved_20_20_WIDTH                            1
+#define DxF0x50_Reserved_20_20_MASK                             0x100000
+#define DxF0x50_DevSpecificInit_OFFSET                          21
+#define DxF0x50_DevSpecificInit_WIDTH                           1
+#define DxF0x50_DevSpecificInit_MASK                            0x200000
+#define DxF0x50_AuxCurrent_OFFSET                               22
+#define DxF0x50_AuxCurrent_WIDTH                                3
+#define DxF0x50_AuxCurrent_MASK                                 0x1c00000
+#define DxF0x50_D1Support_OFFSET                                25
+#define DxF0x50_D1Support_WIDTH                                 1
+#define DxF0x50_D1Support_MASK                                  0x2000000
+#define DxF0x50_D2Support_OFFSET                                26
+#define DxF0x50_D2Support_WIDTH                                 1
+#define DxF0x50_D2Support_MASK                                  0x4000000
+#define DxF0x50_PmeSupport_OFFSET                               27
+#define DxF0x50_PmeSupport_WIDTH                                5
+#define DxF0x50_PmeSupport_MASK                                 0xf8000000
+
+/// DxF0x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:3 ; ///<
+    UINT32                                                 PmeClock:1 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                          DevSpecificInit:1 ; ///<
+    UINT32                                               AuxCurrent:3 ; ///<
+    UINT32                                                D1Support:1 ; ///<
+    UINT32                                                D2Support:1 ; ///<
+    UINT32                                               PmeSupport:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x50_STRUCT;
+
+// **** DxF0x54 Register Definition ****
+// Address
+#define DxF0x54_ADDRESS                                         0x54
+
+// Type
+#define DxF0x54_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x54_PowerState_OFFSET                               0
+#define DxF0x54_PowerState_WIDTH                                2
+#define DxF0x54_PowerState_MASK                                 0x3
+#define DxF0x54_Reserved_2_2_OFFSET                             2
+#define DxF0x54_Reserved_2_2_WIDTH                              1
+#define DxF0x54_Reserved_2_2_MASK                               0x4
+#define DxF0x54_NoSoftReset_OFFSET                              3
+#define DxF0x54_NoSoftReset_WIDTH                               1
+#define DxF0x54_NoSoftReset_MASK                                0x8
+#define DxF0x54_Reserved_7_4_OFFSET                             4
+#define DxF0x54_Reserved_7_4_WIDTH                              4
+#define DxF0x54_Reserved_7_4_MASK                               0xf0
+#define DxF0x54_PmeEn_OFFSET                                    8
+#define DxF0x54_PmeEn_WIDTH                                     1
+#define DxF0x54_PmeEn_MASK                                      0x100
+#define DxF0x54_DataSelect_OFFSET                               9
+#define DxF0x54_DataSelect_WIDTH                                4
+#define DxF0x54_DataSelect_MASK                                 0x1e00
+#define DxF0x54_DataScale_OFFSET                                13
+#define DxF0x54_DataScale_WIDTH                                 2
+#define DxF0x54_DataScale_MASK                                  0x6000
+#define DxF0x54_PmeStatus_OFFSET                                15
+#define DxF0x54_PmeStatus_WIDTH                                 1
+#define DxF0x54_PmeStatus_MASK                                  0x8000
+#define DxF0x54_Reserved_21_16_OFFSET                           16
+#define DxF0x54_Reserved_21_16_WIDTH                            6
+#define DxF0x54_Reserved_21_16_MASK                             0x3f0000
+#define DxF0x54_B2B3Support_OFFSET                              22
+#define DxF0x54_B2B3Support_WIDTH                               1
+#define DxF0x54_B2B3Support_MASK                                0x400000
+#define DxF0x54_BusPwrEn_OFFSET                                 23
+#define DxF0x54_BusPwrEn_WIDTH                                  1
+#define DxF0x54_BusPwrEn_MASK                                   0x800000
+#define DxF0x54_PmeData_OFFSET                                  24
+#define DxF0x54_PmeData_WIDTH                                   8
+#define DxF0x54_PmeData_MASK                                    0xff000000
+
+/// DxF0x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PowerState:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                              NoSoftReset:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    PmeEn:1 ; ///<
+    UINT32                                               DataSelect:4 ; ///<
+    UINT32                                                DataScale:2 ; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                           Reserved_21_16:6 ; ///<
+    UINT32                                              B2B3Support:1 ; ///<
+    UINT32                                                 BusPwrEn:1 ; ///<
+    UINT32                                                  PmeData:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x54_STRUCT;
+
+// **** DxF0x58 Register Definition ****
+// Address
+#define DxF0x58_ADDRESS                                         0x58
+
+// Type
+#define DxF0x58_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x58_CapID_OFFSET                                    0
+#define DxF0x58_CapID_WIDTH                                     8
+#define DxF0x58_CapID_MASK                                      0xff
+#define DxF0x58_NextPtr_OFFSET                                  8
+#define DxF0x58_NextPtr_WIDTH                                   8
+#define DxF0x58_NextPtr_MASK                                    0xff00
+#define DxF0x58_Version_OFFSET                                  16
+#define DxF0x58_Version_WIDTH                                   4
+#define DxF0x58_Version_MASK                                    0xf0000
+#define DxF0x58_DeviceType_OFFSET                               20
+#define DxF0x58_DeviceType_WIDTH                                4
+#define DxF0x58_DeviceType_MASK                                 0xf00000
+#define DxF0x58_SlotImplemented_OFFSET                          24
+#define DxF0x58_SlotImplemented_WIDTH                           1
+#define DxF0x58_SlotImplemented_MASK                            0x1000000
+#define DxF0x58_IntMessageNum_OFFSET                            25
+#define DxF0x58_IntMessageNum_WIDTH                             5
+#define DxF0x58_IntMessageNum_MASK                              0x3e000000
+#define DxF0x58_Reserved_31_30_OFFSET                           30
+#define DxF0x58_Reserved_31_30_WIDTH                            2
+#define DxF0x58_Reserved_31_30_MASK                             0xc0000000
+
+/// DxF0x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:4 ; ///<
+    UINT32                                               DeviceType:4 ; ///<
+    UINT32                                          SlotImplemented:1 ; ///<
+    UINT32                                            IntMessageNum:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x58_STRUCT;
+
+// **** DxF0x5C Register Definition ****
+// Address
+#define DxF0x5C_ADDRESS                                         0x5c
+
+// Type
+#define DxF0x5C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x5C_MaxPayloadSupport_OFFSET                        0
+#define DxF0x5C_MaxPayloadSupport_WIDTH                         3
+#define DxF0x5C_MaxPayloadSupport_MASK                          0x7
+#define DxF0x5C_PhantomFunc_OFFSET                              3
+#define DxF0x5C_PhantomFunc_WIDTH                               2
+#define DxF0x5C_PhantomFunc_MASK                                0x18
+#define DxF0x5C_ExtendedTag_OFFSET                              5
+#define DxF0x5C_ExtendedTag_WIDTH                               1
+#define DxF0x5C_ExtendedTag_MASK                                0x20
+#define DxF0x5C_L0SAcceptableLatency_OFFSET                     6
+#define DxF0x5C_L0SAcceptableLatency_WIDTH                      3
+#define DxF0x5C_L0SAcceptableLatency_MASK                       0x1c0
+#define DxF0x5C_L1AcceptableLatency_OFFSET                      9
+#define DxF0x5C_L1AcceptableLatency_WIDTH                       3
+#define DxF0x5C_L1AcceptableLatency_MASK                        0xe00
+#define DxF0x5C_Reserved_14_12_OFFSET                           12
+#define DxF0x5C_Reserved_14_12_WIDTH                            3
+#define DxF0x5C_Reserved_14_12_MASK                             0x7000
+#define DxF0x5C_RoleBasedErrReporting_OFFSET                    15
+#define DxF0x5C_RoleBasedErrReporting_WIDTH                     1
+#define DxF0x5C_RoleBasedErrReporting_MASK                      0x8000
+#define DxF0x5C_Reserved_17_16_OFFSET                           16
+#define DxF0x5C_Reserved_17_16_WIDTH                            2
+#define DxF0x5C_Reserved_17_16_MASK                             0x30000
+#define DxF0x5C_CapturedSlotPowerLimit_OFFSET                   18
+#define DxF0x5C_CapturedSlotPowerLimit_WIDTH                    8
+#define DxF0x5C_CapturedSlotPowerLimit_MASK                     0x3fc0000
+#define DxF0x5C_CapturedSlotPowerScale_OFFSET                   26
+#define DxF0x5C_CapturedSlotPowerScale_WIDTH                    2
+#define DxF0x5C_CapturedSlotPowerScale_MASK                     0xc000000
+#define DxF0x5C_FlrCapable_OFFSET                               28
+#define DxF0x5C_FlrCapable_WIDTH                                1
+#define DxF0x5C_FlrCapable_MASK                                 0x10000000
+#define DxF0x5C_Reserved_31_29_OFFSET                           29
+#define DxF0x5C_Reserved_31_29_WIDTH                            3
+#define DxF0x5C_Reserved_31_29_MASK                             0xe0000000
+
+/// DxF0x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        MaxPayloadSupport:3 ; ///<
+    UINT32                                              PhantomFunc:2 ; ///<
+    UINT32                                              ExtendedTag:1 ; ///<
+    UINT32                                     L0SAcceptableLatency:3 ; ///<
+    UINT32                                      L1AcceptableLatency:3 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                    RoleBasedErrReporting:1 ; ///<
+    UINT32                                           Reserved_17_16:2 ; ///<
+    UINT32                                   CapturedSlotPowerLimit:8 ; ///<
+    UINT32                                   CapturedSlotPowerScale:2 ; ///<
+    UINT32                                               FlrCapable:1 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x5C_STRUCT;
+
+// **** DxF0x60 Register Definition ****
+// Address
+#define DxF0x60_ADDRESS                                         0x60
+
+// Type
+#define DxF0x60_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x60_CorrErrEn_OFFSET                                0
+#define DxF0x60_CorrErrEn_WIDTH                                 1
+#define DxF0x60_CorrErrEn_MASK                                  0x1
+#define DxF0x60_NonFatalErrEn_OFFSET                            1
+#define DxF0x60_NonFatalErrEn_WIDTH                             1
+#define DxF0x60_NonFatalErrEn_MASK                              0x2
+#define DxF0x60_FatalErrEn_OFFSET                               2
+#define DxF0x60_FatalErrEn_WIDTH                                1
+#define DxF0x60_FatalErrEn_MASK                                 0x4
+#define DxF0x60_UsrReportEn_OFFSET                              3
+#define DxF0x60_UsrReportEn_WIDTH                               1
+#define DxF0x60_UsrReportEn_MASK                                0x8
+#define DxF0x60_RelaxedOrdEn_OFFSET                             4
+#define DxF0x60_RelaxedOrdEn_WIDTH                              1
+#define DxF0x60_RelaxedOrdEn_MASK                               0x10
+#define DxF0x60_MaxPayloadSize_OFFSET                           5
+#define DxF0x60_MaxPayloadSize_WIDTH                            3
+#define DxF0x60_MaxPayloadSize_MASK                             0xe0
+#define DxF0x60_ExtendedTagEn_OFFSET                            8
+#define DxF0x60_ExtendedTagEn_WIDTH                             1
+#define DxF0x60_ExtendedTagEn_MASK                              0x100
+#define DxF0x60_PhantomFuncEn_OFFSET                            9
+#define DxF0x60_PhantomFuncEn_WIDTH                             1
+#define DxF0x60_PhantomFuncEn_MASK                              0x200
+#define DxF0x60_AuxPowerPmEn_OFFSET                             10
+#define DxF0x60_AuxPowerPmEn_WIDTH                              1
+#define DxF0x60_AuxPowerPmEn_MASK                               0x400
+#define DxF0x60_NoSnoopEnable_OFFSET                            11
+#define DxF0x60_NoSnoopEnable_WIDTH                             1
+#define DxF0x60_NoSnoopEnable_MASK                              0x800
+#define DxF0x60_MaxRequestSize_OFFSET                           12
+#define DxF0x60_MaxRequestSize_WIDTH                            3
+#define DxF0x60_MaxRequestSize_MASK                             0x7000
+#define DxF0x60_BridgeCfgRetryEn_OFFSET                         15
+#define DxF0x60_BridgeCfgRetryEn_WIDTH                          1
+#define DxF0x60_BridgeCfgRetryEn_MASK                           0x8000
+#define DxF0x60_CorrErr_OFFSET                                  16
+#define DxF0x60_CorrErr_WIDTH                                   1
+#define DxF0x60_CorrErr_MASK                                    0x10000
+#define DxF0x60_NonFatalErr_OFFSET                              17
+#define DxF0x60_NonFatalErr_WIDTH                               1
+#define DxF0x60_NonFatalErr_MASK                                0x20000
+#define DxF0x60_FatalErr_OFFSET                                 18
+#define DxF0x60_FatalErr_WIDTH                                  1
+#define DxF0x60_FatalErr_MASK                                   0x40000
+#define DxF0x60_UsrDetected_OFFSET                              19
+#define DxF0x60_UsrDetected_WIDTH                               1
+#define DxF0x60_UsrDetected_MASK                                0x80000
+#define DxF0x60_AuxPwr_OFFSET                                   20
+#define DxF0x60_AuxPwr_WIDTH                                    1
+#define DxF0x60_AuxPwr_MASK                                     0x100000
+#define DxF0x60_TransactionsPending_OFFSET                      21
+#define DxF0x60_TransactionsPending_WIDTH                       1
+#define DxF0x60_TransactionsPending_MASK                        0x200000
+#define DxF0x60_Reserved_31_22_OFFSET                           22
+#define DxF0x60_Reserved_31_22_WIDTH                            10
+#define DxF0x60_Reserved_31_22_MASK                             0xffc00000
+
+/// DxF0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CorrErrEn:1 ; ///<
+    UINT32                                            NonFatalErrEn:1 ; ///<
+    UINT32                                               FatalErrEn:1 ; ///<
+    UINT32                                              UsrReportEn:1 ; ///<
+    UINT32                                             RelaxedOrdEn:1 ; ///<
+    UINT32                                           MaxPayloadSize:3 ; ///<
+    UINT32                                            ExtendedTagEn:1 ; ///<
+    UINT32                                            PhantomFuncEn:1 ; ///<
+    UINT32                                             AuxPowerPmEn:1 ; ///<
+    UINT32                                            NoSnoopEnable:1 ; ///<
+    UINT32                                           MaxRequestSize:3 ; ///<
+    UINT32                                         BridgeCfgRetryEn:1 ; ///<
+    UINT32                                                  CorrErr:1 ; ///<
+    UINT32                                              NonFatalErr:1 ; ///<
+    UINT32                                                 FatalErr:1 ; ///<
+    UINT32                                              UsrDetected:1 ; ///<
+    UINT32                                                   AuxPwr:1 ; ///<
+    UINT32                                      TransactionsPending:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x60_STRUCT;
+
+// **** DxF0x64 Register Definition ****
+// Address
+#define DxF0x64_ADDRESS                                         0x64
+
+// Type
+#define DxF0x64_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x64_LinkSpeed_OFFSET                                0
+#define DxF0x64_LinkSpeed_WIDTH                                 4
+#define DxF0x64_LinkSpeed_MASK                                  0xf
+#define DxF0x64_LinkWidth_OFFSET                                4
+#define DxF0x64_LinkWidth_WIDTH                                 6
+#define DxF0x64_LinkWidth_MASK                                  0x3f0
+#define DxF0x64_PMSupport_OFFSET                                10
+#define DxF0x64_PMSupport_WIDTH                                 2
+#define DxF0x64_PMSupport_MASK                                  0xc00
+#define DxF0x64_L0sExitLatency_OFFSET                           12
+#define DxF0x64_L0sExitLatency_WIDTH                            3
+#define DxF0x64_L0sExitLatency_MASK                             0x7000
+#define DxF0x64_L1ExitLatency_OFFSET                            15
+#define DxF0x64_L1ExitLatency_WIDTH                             3
+#define DxF0x64_L1ExitLatency_MASK                              0x38000
+#define DxF0x64_ClockPowerManagement_OFFSET                     18
+#define DxF0x64_ClockPowerManagement_WIDTH                      1
+#define DxF0x64_ClockPowerManagement_MASK                       0x40000
+#define DxF0x64_SurpriseDownErrReporting_OFFSET                 19
+#define DxF0x64_SurpriseDownErrReporting_WIDTH                  1
+#define DxF0x64_SurpriseDownErrReporting_MASK                   0x80000
+#define DxF0x64_DlActiveReportingCapable_OFFSET                 20
+#define DxF0x64_DlActiveReportingCapable_WIDTH                  1
+#define DxF0x64_DlActiveReportingCapable_MASK                   0x100000
+#define DxF0x64_LinkBWNotificationCap_OFFSET                    21
+#define DxF0x64_LinkBWNotificationCap_WIDTH                     1
+#define DxF0x64_LinkBWNotificationCap_MASK                      0x200000
+#define DxF0x64_AspmOptionalityCompliance_OFFSET                22
+#define DxF0x64_AspmOptionalityCompliance_WIDTH                 1
+#define DxF0x64_AspmOptionalityCompliance_MASK                  0x400000
+#define DxF0x64_Reserved_23_23_OFFSET                           23
+#define DxF0x64_Reserved_23_23_WIDTH                            1
+#define DxF0x64_Reserved_23_23_MASK                             0x800000
+#define DxF0x64_PortNumber_OFFSET                               24
+#define DxF0x64_PortNumber_WIDTH                                8
+#define DxF0x64_PortNumber_MASK                                 0xff000000
+
+/// DxF0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LinkSpeed:4 ; ///<
+    UINT32                                                LinkWidth:6 ; ///<
+    UINT32                                                PMSupport:2 ; ///<
+    UINT32                                           L0sExitLatency:3 ; ///<
+    UINT32                                            L1ExitLatency:3 ; ///<
+    UINT32                                     ClockPowerManagement:1 ; ///<
+    UINT32                                 SurpriseDownErrReporting:1 ; ///<
+    UINT32                                 DlActiveReportingCapable:1 ; ///<
+    UINT32                                    LinkBWNotificationCap:1 ; ///<
+    UINT32                                AspmOptionalityCompliance:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                               PortNumber:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x64_STRUCT;
+
+// **** DxF0x68 Register Definition ****
+// Address
+#define DxF0x68_ADDRESS                                         0x68
+
+// Type
+#define DxF0x68_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x68_PmControl_OFFSET                                0
+#define DxF0x68_PmControl_WIDTH                                 2
+#define DxF0x68_PmControl_MASK                                  0x3
+#define DxF0x68_Reserved_2_2_OFFSET                             2
+#define DxF0x68_Reserved_2_2_WIDTH                              1
+#define DxF0x68_Reserved_2_2_MASK                               0x4
+#define DxF0x68_ReadCplBoundary_OFFSET                          3
+#define DxF0x68_ReadCplBoundary_WIDTH                           1
+#define DxF0x68_ReadCplBoundary_MASK                            0x8
+#define DxF0x68_LinkDis_OFFSET                                  4
+#define DxF0x68_LinkDis_WIDTH                                   1
+#define DxF0x68_LinkDis_MASK                                    0x10
+#define DxF0x68_RetrainLink_OFFSET                              5
+#define DxF0x68_RetrainLink_WIDTH                               1
+#define DxF0x68_RetrainLink_MASK                                0x20
+#define DxF0x68_CommonClockCfg_OFFSET                           6
+#define DxF0x68_CommonClockCfg_WIDTH                            1
+#define DxF0x68_CommonClockCfg_MASK                             0x40
+#define DxF0x68_ExtendedSync_OFFSET                             7
+#define DxF0x68_ExtendedSync_WIDTH                              1
+#define DxF0x68_ExtendedSync_MASK                               0x80
+#define DxF0x68_ClockPowerManagementEn_OFFSET                   8
+#define DxF0x68_ClockPowerManagementEn_WIDTH                    1
+#define DxF0x68_ClockPowerManagementEn_MASK                     0x100
+#define DxF0x68_HWAutonomousWidthDisable_OFFSET                 9
+#define DxF0x68_HWAutonomousWidthDisable_WIDTH                  1
+#define DxF0x68_HWAutonomousWidthDisable_MASK                   0x200
+#define DxF0x68_LinkBWManagementEn_OFFSET                       10
+#define DxF0x68_LinkBWManagementEn_WIDTH                        1
+#define DxF0x68_LinkBWManagementEn_MASK                         0x400
+#define DxF0x68_LinkAutonomousBWIntEn_OFFSET                    11
+#define DxF0x68_LinkAutonomousBWIntEn_WIDTH                     1
+#define DxF0x68_LinkAutonomousBWIntEn_MASK                      0x800
+#define DxF0x68_Reserved_15_12_OFFSET                           12
+#define DxF0x68_Reserved_15_12_WIDTH                            4
+#define DxF0x68_Reserved_15_12_MASK                             0xf000
+#define DxF0x68_LinkSpeed_OFFSET                                16
+#define DxF0x68_LinkSpeed_WIDTH                                 4
+#define DxF0x68_LinkSpeed_MASK                                  0xf0000
+#define DxF0x68_NegotiatedLinkWidth_OFFSET                      20
+#define DxF0x68_NegotiatedLinkWidth_WIDTH                       6
+#define DxF0x68_NegotiatedLinkWidth_MASK                        0x3f00000
+#define DxF0x68_Reserved_26_26_OFFSET                           26
+#define DxF0x68_Reserved_26_26_WIDTH                            1
+#define DxF0x68_Reserved_26_26_MASK                             0x4000000
+#define DxF0x68_LinkTraining_OFFSET                             27
+#define DxF0x68_LinkTraining_WIDTH                              1
+#define DxF0x68_LinkTraining_MASK                               0x8000000
+#define DxF0x68_SlotClockCfg_OFFSET                             28
+#define DxF0x68_SlotClockCfg_WIDTH                              1
+#define DxF0x68_SlotClockCfg_MASK                               0x10000000
+#define DxF0x68_DlActive_OFFSET                                 29
+#define DxF0x68_DlActive_WIDTH                                  1
+#define DxF0x68_DlActive_MASK                                   0x20000000
+#define DxF0x68_LinkBWManagementStatus_OFFSET                   30
+#define DxF0x68_LinkBWManagementStatus_WIDTH                    1
+#define DxF0x68_LinkBWManagementStatus_MASK                     0x40000000
+#define DxF0x68_LinkAutonomousBWStatus_OFFSET                   31
+#define DxF0x68_LinkAutonomousBWStatus_WIDTH                    1
+#define DxF0x68_LinkAutonomousBWStatus_MASK                     0x80000000
+
+/// DxF0x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PmControl:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          ReadCplBoundary:1 ; ///<
+    UINT32                                                  LinkDis:1 ; ///<
+    UINT32                                              RetrainLink:1 ; ///<
+    UINT32                                           CommonClockCfg:1 ; ///<
+    UINT32                                             ExtendedSync:1 ; ///<
+    UINT32                                   ClockPowerManagementEn:1 ; ///<
+    UINT32                                 HWAutonomousWidthDisable:1 ; ///<
+    UINT32                                       LinkBWManagementEn:1 ; ///<
+    UINT32                                    LinkAutonomousBWIntEn:1 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                LinkSpeed:4 ; ///<
+    UINT32                                      NegotiatedLinkWidth:6 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                             LinkTraining:1 ; ///<
+    UINT32                                             SlotClockCfg:1 ; ///<
+    UINT32                                                 DlActive:1 ; ///<
+    UINT32                                   LinkBWManagementStatus:1 ; ///<
+    UINT32                                   LinkAutonomousBWStatus:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x68_STRUCT;
+
+// **** DxF0x6C Register Definition ****
+// Address
+#define DxF0x6C_ADDRESS                                         0x6c
+
+// Type
+#define DxF0x6C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x6C_AttnButtonPresent_OFFSET                        0
+#define DxF0x6C_AttnButtonPresent_WIDTH                         1
+#define DxF0x6C_AttnButtonPresent_MASK                          0x1
+#define DxF0x6C_PwrControllerPresent_OFFSET                     1
+#define DxF0x6C_PwrControllerPresent_WIDTH                      1
+#define DxF0x6C_PwrControllerPresent_MASK                       0x2
+#define DxF0x6C_MrlSensorPresent_OFFSET                         2
+#define DxF0x6C_MrlSensorPresent_WIDTH                          1
+#define DxF0x6C_MrlSensorPresent_MASK                           0x4
+#define DxF0x6C_AttnIndicatorPresent_OFFSET                     3
+#define DxF0x6C_AttnIndicatorPresent_WIDTH                      1
+#define DxF0x6C_AttnIndicatorPresent_MASK                       0x8
+#define DxF0x6C_PwrIndicatorPresent_OFFSET                      4
+#define DxF0x6C_PwrIndicatorPresent_WIDTH                       1
+#define DxF0x6C_PwrIndicatorPresent_MASK                        0x10
+#define DxF0x6C_HotplugSurprise_OFFSET                          5
+#define DxF0x6C_HotplugSurprise_WIDTH                           1
+#define DxF0x6C_HotplugSurprise_MASK                            0x20
+#define DxF0x6C_HotplugCapable_OFFSET                           6
+#define DxF0x6C_HotplugCapable_WIDTH                            1
+#define DxF0x6C_HotplugCapable_MASK                             0x40
+#define DxF0x6C_SlotPwrLimitValue_OFFSET                        7
+#define DxF0x6C_SlotPwrLimitValue_WIDTH                         8
+#define DxF0x6C_SlotPwrLimitValue_MASK                          0x7f80
+#define DxF0x6C_SlotPwrLimitScale_OFFSET                        15
+#define DxF0x6C_SlotPwrLimitScale_WIDTH                         2
+#define DxF0x6C_SlotPwrLimitScale_MASK                          0x18000
+#define DxF0x6C_ElecMechIlPresent_OFFSET                        17
+#define DxF0x6C_ElecMechIlPresent_WIDTH                         1
+#define DxF0x6C_ElecMechIlPresent_MASK                          0x20000
+#define DxF0x6C_NoCmdCplSupport_OFFSET                          18
+#define DxF0x6C_NoCmdCplSupport_WIDTH                           1
+#define DxF0x6C_NoCmdCplSupport_MASK                            0x40000
+#define DxF0x6C_PhysicalSlotNumber_OFFSET                       19
+#define DxF0x6C_PhysicalSlotNumber_WIDTH                        13
+#define DxF0x6C_PhysicalSlotNumber_MASK                         0xfff80000
+
+/// DxF0x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AttnButtonPresent:1 ; ///<
+    UINT32                                     PwrControllerPresent:1 ; ///<
+    UINT32                                         MrlSensorPresent:1 ; ///<
+    UINT32                                     AttnIndicatorPresent:1 ; ///<
+    UINT32                                      PwrIndicatorPresent:1 ; ///<
+    UINT32                                          HotplugSurprise:1 ; ///<
+    UINT32                                           HotplugCapable:1 ; ///<
+    UINT32                                        SlotPwrLimitValue:8 ; ///<
+    UINT32                                        SlotPwrLimitScale:2 ; ///<
+    UINT32                                        ElecMechIlPresent:1 ; ///<
+    UINT32                                          NoCmdCplSupport:1 ; ///<
+    UINT32                                       PhysicalSlotNumber:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x6C_STRUCT;
+
+// **** DxF0x70 Register Definition ****
+// Address
+#define DxF0x70_ADDRESS                                         0x70
+
+// Type
+#define DxF0x70_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x70_AttnButtonPressedEn_OFFSET                      0
+#define DxF0x70_AttnButtonPressedEn_WIDTH                       1
+#define DxF0x70_AttnButtonPressedEn_MASK                        0x1
+#define DxF0x70_PwrFaultDetectedEn_OFFSET                       1
+#define DxF0x70_PwrFaultDetectedEn_WIDTH                        1
+#define DxF0x70_PwrFaultDetectedEn_MASK                         0x2
+#define DxF0x70_MrlSensorChangedEn_OFFSET                       2
+#define DxF0x70_MrlSensorChangedEn_WIDTH                        1
+#define DxF0x70_MrlSensorChangedEn_MASK                         0x4
+#define DxF0x70_PresenceDetectChangedEn_OFFSET                  3
+#define DxF0x70_PresenceDetectChangedEn_WIDTH                   1
+#define DxF0x70_PresenceDetectChangedEn_MASK                    0x8
+#define DxF0x70_CmdCplIntrEn_OFFSET                             4
+#define DxF0x70_CmdCplIntrEn_WIDTH                              1
+#define DxF0x70_CmdCplIntrEn_MASK                               0x10
+#define DxF0x70_HotplugIntrEn_OFFSET                            5
+#define DxF0x70_HotplugIntrEn_WIDTH                             1
+#define DxF0x70_HotplugIntrEn_MASK                              0x20
+#define DxF0x70_AttnIndicatorControl_OFFSET                     6
+#define DxF0x70_AttnIndicatorControl_WIDTH                      2
+#define DxF0x70_AttnIndicatorControl_MASK                       0xc0
+#define DxF0x70_PwrIndicatorCntl_OFFSET                         8
+#define DxF0x70_PwrIndicatorCntl_WIDTH                          2
+#define DxF0x70_PwrIndicatorCntl_MASK                           0x300
+#define DxF0x70_PwrControllerCntl_OFFSET                        10
+#define DxF0x70_PwrControllerCntl_WIDTH                         1
+#define DxF0x70_PwrControllerCntl_MASK                          0x400
+#define DxF0x70_ElecMechIlCntl_OFFSET                           11
+#define DxF0x70_ElecMechIlCntl_WIDTH                            1
+#define DxF0x70_ElecMechIlCntl_MASK                             0x800
+#define DxF0x70_DlStateChangedEn_OFFSET                         12
+#define DxF0x70_DlStateChangedEn_WIDTH                          1
+#define DxF0x70_DlStateChangedEn_MASK                           0x1000
+#define DxF0x70_Reserved_15_13_OFFSET                           13
+#define DxF0x70_Reserved_15_13_WIDTH                            3
+#define DxF0x70_Reserved_15_13_MASK                             0xe000
+#define DxF0x70_AttnButtonPressed_OFFSET                        16
+#define DxF0x70_AttnButtonPressed_WIDTH                         1
+#define DxF0x70_AttnButtonPressed_MASK                          0x10000
+#define DxF0x70_PwrFaultDetected_OFFSET                         17
+#define DxF0x70_PwrFaultDetected_WIDTH                          1
+#define DxF0x70_PwrFaultDetected_MASK                           0x20000
+#define DxF0x70_MrlSensorChanged_OFFSET                         18
+#define DxF0x70_MrlSensorChanged_WIDTH                          1
+#define DxF0x70_MrlSensorChanged_MASK                           0x40000
+#define DxF0x70_PresenceDetectChanged_OFFSET                    19
+#define DxF0x70_PresenceDetectChanged_WIDTH                     1
+#define DxF0x70_PresenceDetectChanged_MASK                      0x80000
+#define DxF0x70_CmdCpl_OFFSET                                   20
+#define DxF0x70_CmdCpl_WIDTH                                    1
+#define DxF0x70_CmdCpl_MASK                                     0x100000
+#define DxF0x70_MrlSensorState_OFFSET                           21
+#define DxF0x70_MrlSensorState_WIDTH                            1
+#define DxF0x70_MrlSensorState_MASK                             0x200000
+#define DxF0x70_PresenceDetectState_OFFSET                      22
+#define DxF0x70_PresenceDetectState_WIDTH                       1
+#define DxF0x70_PresenceDetectState_MASK                        0x400000
+#define DxF0x70_ElecMechIlSts_OFFSET                            23
+#define DxF0x70_ElecMechIlSts_WIDTH                             1
+#define DxF0x70_ElecMechIlSts_MASK                              0x800000
+#define DxF0x70_DlStateChanged_OFFSET                           24
+#define DxF0x70_DlStateChanged_WIDTH                            1
+#define DxF0x70_DlStateChanged_MASK                             0x1000000
+#define DxF0x70_Reserved_31_25_OFFSET                           25
+#define DxF0x70_Reserved_31_25_WIDTH                            7
+#define DxF0x70_Reserved_31_25_MASK                             0xfe000000
+
+/// DxF0x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      AttnButtonPressedEn:1 ; ///<
+    UINT32                                       PwrFaultDetectedEn:1 ; ///<
+    UINT32                                       MrlSensorChangedEn:1 ; ///<
+    UINT32                                  PresenceDetectChangedEn:1 ; ///<
+    UINT32                                             CmdCplIntrEn:1 ; ///<
+    UINT32                                            HotplugIntrEn:1 ; ///<
+    UINT32                                     AttnIndicatorControl:2 ; ///<
+    UINT32                                         PwrIndicatorCntl:2 ; ///<
+    UINT32                                        PwrControllerCntl:1 ; ///<
+    UINT32                                           ElecMechIlCntl:1 ; ///<
+    UINT32                                         DlStateChangedEn:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                        AttnButtonPressed:1 ; ///<
+    UINT32                                         PwrFaultDetected:1 ; ///<
+    UINT32                                         MrlSensorChanged:1 ; ///<
+    UINT32                                    PresenceDetectChanged:1 ; ///<
+    UINT32                                                   CmdCpl:1 ; ///<
+    UINT32                                           MrlSensorState:1 ; ///<
+    UINT32                                      PresenceDetectState:1 ; ///<
+    UINT32                                            ElecMechIlSts:1 ; ///<
+    UINT32                                           DlStateChanged:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x70_STRUCT;
+
+// **** DxF0x74 Register Definition ****
+// Address
+#define DxF0x74_ADDRESS                                         0x74
+
+// Type
+#define DxF0x74_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x74_SerrOnCorrErrEn_OFFSET                          0
+#define DxF0x74_SerrOnCorrErrEn_WIDTH                           1
+#define DxF0x74_SerrOnCorrErrEn_MASK                            0x1
+#define DxF0x74_SerrOnNonFatalErrEn_OFFSET                      1
+#define DxF0x74_SerrOnNonFatalErrEn_WIDTH                       1
+#define DxF0x74_SerrOnNonFatalErrEn_MASK                        0x2
+#define DxF0x74_SerrOnFatalErrEn_OFFSET                         2
+#define DxF0x74_SerrOnFatalErrEn_WIDTH                          1
+#define DxF0x74_SerrOnFatalErrEn_MASK                           0x4
+#define DxF0x74_PmIntEn_OFFSET                                  3
+#define DxF0x74_PmIntEn_WIDTH                                   1
+#define DxF0x74_PmIntEn_MASK                                    0x8
+#define DxF0x74_CrsSoftVisibilityEn_OFFSET                      4
+#define DxF0x74_CrsSoftVisibilityEn_WIDTH                       1
+#define DxF0x74_CrsSoftVisibilityEn_MASK                        0x10
+#define DxF0x74_Reserved_15_5_OFFSET                            5
+#define DxF0x74_Reserved_15_5_WIDTH                             11
+#define DxF0x74_Reserved_15_5_MASK                              0xffe0
+#define DxF0x74_CrsSoftVisibility_OFFSET                        16
+#define DxF0x74_CrsSoftVisibility_WIDTH                         1
+#define DxF0x74_CrsSoftVisibility_MASK                          0x10000
+#define DxF0x74_Reserved_31_17_OFFSET                           17
+#define DxF0x74_Reserved_31_17_WIDTH                            15
+#define DxF0x74_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          SerrOnCorrErrEn:1 ; ///<
+    UINT32                                      SerrOnNonFatalErrEn:1 ; ///<
+    UINT32                                         SerrOnFatalErrEn:1 ; ///<
+    UINT32                                                  PmIntEn:1 ; ///<
+    UINT32                                      CrsSoftVisibilityEn:1 ; ///<
+    UINT32                                            Reserved_15_5:11; ///<
+    UINT32                                        CrsSoftVisibility:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x74_STRUCT;
+
+// **** DxF0x78 Register Definition ****
+// Address
+#define DxF0x78_ADDRESS                                         0x78
+
+// Type
+#define DxF0x78_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x78_PmeRequestorId_OFFSET                           0
+#define DxF0x78_PmeRequestorId_WIDTH                            16
+#define DxF0x78_PmeRequestorId_MASK                             0xffff
+#define DxF0x78_PmeStatus_OFFSET                                16
+#define DxF0x78_PmeStatus_WIDTH                                 1
+#define DxF0x78_PmeStatus_MASK                                  0x10000
+#define DxF0x78_PmePending_OFFSET                               17
+#define DxF0x78_PmePending_WIDTH                                1
+#define DxF0x78_PmePending_MASK                                 0x20000
+#define DxF0x78_Reserved_31_18_OFFSET                           18
+#define DxF0x78_Reserved_31_18_WIDTH                            14
+#define DxF0x78_Reserved_31_18_MASK                             0xfffc0000
+
+/// DxF0x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PmeRequestorId:16; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                               PmePending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x78_STRUCT;
+
+// **** DxF0x7C Register Definition ****
+// Address
+#define DxF0x7C_ADDRESS                                         0x7c
+
+// Type
+#define DxF0x7C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x7C_CplTimeoutRangeSup_OFFSET                       0
+#define DxF0x7C_CplTimeoutRangeSup_WIDTH                        4
+#define DxF0x7C_CplTimeoutRangeSup_MASK                         0xf
+#define DxF0x7C_CplTimeoutDisSup_OFFSET                         4
+#define DxF0x7C_CplTimeoutDisSup_WIDTH                          1
+#define DxF0x7C_CplTimeoutDisSup_MASK                           0x10
+#define DxF0x7C_AriForwardingSupported_OFFSET                   5
+#define DxF0x7C_AriForwardingSupported_WIDTH                    1
+#define DxF0x7C_AriForwardingSupported_MASK                     0x20
+#define DxF0x7C_Reserved_31_6_OFFSET                            6
+#define DxF0x7C_Reserved_31_6_WIDTH                             26
+#define DxF0x7C_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       CplTimeoutRangeSup:4 ; ///<
+    UINT32                                         CplTimeoutDisSup:1 ; ///<
+    UINT32                                   AriForwardingSupported:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x7C_STRUCT;
+
+// **** DxF0x80 Register Definition ****
+// Address
+#define DxF0x80_ADDRESS                                         0x80
+
+// Type
+#define DxF0x80_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x80_CplTimeoutValue_OFFSET                          0
+#define DxF0x80_CplTimeoutValue_WIDTH                           4
+#define DxF0x80_CplTimeoutValue_MASK                            0xf
+#define DxF0x80_CplTimeoutDis_OFFSET                            4
+#define DxF0x80_CplTimeoutDis_WIDTH                             1
+#define DxF0x80_CplTimeoutDis_MASK                              0x10
+#define DxF0x80_AriForwardingEn_OFFSET                          5
+#define DxF0x80_AriForwardingEn_WIDTH                           1
+#define DxF0x80_AriForwardingEn_MASK                            0x20
+#define DxF0x80_Reserved_31_6_OFFSET                            6
+#define DxF0x80_Reserved_31_6_WIDTH                             26
+#define DxF0x80_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CplTimeoutValue:4 ; ///<
+    UINT32                                            CplTimeoutDis:1 ; ///<
+    UINT32                                          AriForwardingEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x80_STRUCT;
+
+// **** DxF0x84 Register Definition ****
+// Address
+#define DxF0x84_ADDRESS                                         0x84
+
+// Type
+#define DxF0x84_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x84_Reserved_31_0_OFFSET                            0
+#define DxF0x84_Reserved_31_0_WIDTH                             32
+#define DxF0x84_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x84_STRUCT;
+
+// **** DxF0x88 Register Definition ****
+// Address
+#define DxF0x88_ADDRESS                                         0x88
+
+// Type
+#define DxF0x88_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x88_TargetLinkSpeed_OFFSET                          0
+#define DxF0x88_TargetLinkSpeed_WIDTH                           4
+#define DxF0x88_TargetLinkSpeed_MASK                            0xf
+#define DxF0x88_EnterCompliance_OFFSET                          4
+#define DxF0x88_EnterCompliance_WIDTH                           1
+#define DxF0x88_EnterCompliance_MASK                            0x10
+#define DxF0x88_HwAutonomousSpeedDisable_OFFSET                 5
+#define DxF0x88_HwAutonomousSpeedDisable_WIDTH                  1
+#define DxF0x88_HwAutonomousSpeedDisable_MASK                   0x20
+#define DxF0x88_SelectableDeemphasis_OFFSET                     6
+#define DxF0x88_SelectableDeemphasis_WIDTH                      1
+#define DxF0x88_SelectableDeemphasis_MASK                       0x40
+#define DxF0x88_XmitMargin_OFFSET                               7
+#define DxF0x88_XmitMargin_WIDTH                                3
+#define DxF0x88_XmitMargin_MASK                                 0x380
+#define DxF0x88_EnterModCompliance_OFFSET                       10
+#define DxF0x88_EnterModCompliance_WIDTH                        1
+#define DxF0x88_EnterModCompliance_MASK                         0x400
+#define DxF0x88_ComplianceSOS_OFFSET                            11
+#define DxF0x88_ComplianceSOS_WIDTH                             1
+#define DxF0x88_ComplianceSOS_MASK                              0x800
+#define DxF0x88_ComplianceDeemphasis_OFFSET                     12
+#define DxF0x88_ComplianceDeemphasis_WIDTH                      1
+#define DxF0x88_ComplianceDeemphasis_MASK                       0x1000
+#define DxF0x88_Reserved_15_13_OFFSET                           13
+#define DxF0x88_Reserved_15_13_WIDTH                            3
+#define DxF0x88_Reserved_15_13_MASK                             0xe000
+#define DxF0x88_CurDeemphasisLevel_OFFSET                       16
+#define DxF0x88_CurDeemphasisLevel_WIDTH                        1
+#define DxF0x88_CurDeemphasisLevel_MASK                         0x10000
+#define DxF0x88_Reserved_31_17_OFFSET                           17
+#define DxF0x88_Reserved_31_17_WIDTH                            15
+#define DxF0x88_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TargetLinkSpeed:4 ; ///<
+    UINT32                                          EnterCompliance:1 ; ///<
+    UINT32                                 HwAutonomousSpeedDisable:1 ; ///<
+    UINT32                                     SelectableDeemphasis:1 ; ///<
+    UINT32                                               XmitMargin:3 ; ///<
+    UINT32                                       EnterModCompliance:1 ; ///<
+    UINT32                                            ComplianceSOS:1 ; ///<
+    UINT32                                     ComplianceDeemphasis:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                       CurDeemphasisLevel:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x88_STRUCT;
+
+// **** DxF0x8C Register Definition ****
+// Address
+#define DxF0x8C_ADDRESS                                         0x8c
+
+// Type
+#define DxF0x8C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x8C_Reserved_31_0_OFFSET                            0
+#define DxF0x8C_Reserved_31_0_WIDTH                             32
+#define DxF0x8C_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x8C_STRUCT;
+
+// **** DxF0x90 Register Definition ****
+// Address
+#define DxF0x90_ADDRESS                                         0x90
+
+// Type
+#define DxF0x90_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x90_Reserved_31_0_OFFSET                            0
+#define DxF0x90_Reserved_31_0_WIDTH                             32
+#define DxF0x90_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x90_STRUCT;
+
+// **** DxF0x128 Register Definition ****
+// Address
+#define DxF0x128_ADDRESS                                        0x128
+
+// Type
+#define DxF0x128_TYPE                                           TYPE_D4F0
+// Field Data
+#define DxF0x128_Reserved_15_0_OFFSET                           0
+#define DxF0x128_Reserved_15_0_WIDTH                            16
+#define DxF0x128_Reserved_15_0_MASK                             0xffff
+#define DxF0x128_PortArbTableStatus_OFFSET                      16
+#define DxF0x128_PortArbTableStatus_WIDTH                       1
+#define DxF0x128_PortArbTableStatus_MASK                        0x10000
+#define DxF0x128_VcNegotiationPending_OFFSET                    17
+#define DxF0x128_VcNegotiationPending_WIDTH                     1
+#define DxF0x128_VcNegotiationPending_MASK                      0x20000
+#define DxF0x128_Reserved_31_18_OFFSET                          18
+#define DxF0x128_Reserved_31_18_WIDTH                           14
+#define DxF0x128_Reserved_31_18_MASK                            0xfffc0000
+
+/// DxF0x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                       PortArbTableStatus:1 ; ///<
+    UINT32                                     VcNegotiationPending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x128_STRUCT;
+
+// **** D0F0x64_x00 Register Definition ****
+// Address
+#define D0F0x64_x00_ADDRESS                                     0x0
+
+// Type
+#define D0F0x64_x00_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x00_Reserved_5_0_OFFSET                         0
+#define D0F0x64_x00_Reserved_5_0_WIDTH                          6
+#define D0F0x64_x00_Reserved_5_0_MASK                           0x3f
+#define D0F0x64_x00_NbFchCfgEn_OFFSET                           6
+#define D0F0x64_x00_NbFchCfgEn_WIDTH                            1
+#define D0F0x64_x00_NbFchCfgEn_MASK                             0x40
+#define D0F0x64_x00_HwInitWrLock_OFFSET                         7
+#define D0F0x64_x00_HwInitWrLock_WIDTH                          1
+#define D0F0x64_x00_HwInitWrLock_MASK                           0x80
+#define D0F0x64_x00_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x00_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x00_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_5_0:6 ; ///<
+    UINT32                                               NbFchCfgEn:1 ; ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x00_STRUCT;
+
+// **** D0F0x64_x0B Register Definition ****
+// Address
+#define D0F0x64_x0B_ADDRESS                                     0xb
+
+// Type
+#define D0F0x64_x0B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x0B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x0B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x0B_SetPowEn_OFFSET                             20
+#define D0F0x64_x0B_SetPowEn_WIDTH                              1
+#define D0F0x64_x0B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x0B_IocFchSetPowEn_OFFSET                       21
+#define D0F0x64_x0B_IocFchSetPowEn_WIDTH                        1
+#define D0F0x64_x0B_IocFchSetPowEn_MASK                         0x200000
+#define D0F0x64_x0B_Reserved_22_22_OFFSET                       22
+#define D0F0x64_x0B_Reserved_22_22_WIDTH                        1
+#define D0F0x64_x0B_Reserved_22_22_MASK                         0x400000
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET                23
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH                 1
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK                  0x800000
+#define D0F0x64_x0B_Reserved_31_24_OFFSET                       24
+#define D0F0x64_x0B_Reserved_31_24_WIDTH                        8
+#define D0F0x64_x0B_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x64_x0B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           IocFchSetPowEn:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    IocFchSetPmeTurnOffEn:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0B_STRUCT;
+
+// **** D0F0x64_x0C Register Definition ****
+// Address
+#define D0F0x64_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x64_x0C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0C_Reserved_1_0_OFFSET                         0
+#define D0F0x64_x0C_Reserved_1_0_WIDTH                          2
+#define D0F0x64_x0C_Reserved_1_0_MASK                           0x3
+#define D0F0x64_x0C_Dev2BridgeDis_OFFSET                        2
+#define D0F0x64_x0C_Dev2BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev2BridgeDis_MASK                          0x4
+#define D0F0x64_x0C_Dev3BridgeDis_OFFSET                        3
+#define D0F0x64_x0C_Dev3BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev3BridgeDis_MASK                          0x8
+#define D0F0x64_x0C_Dev4BridgeDis_OFFSET                        4
+#define D0F0x64_x0C_Dev4BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev4BridgeDis_MASK                          0x10
+#define D0F0x64_x0C_Dev5BridgeDis_OFFSET                        5
+#define D0F0x64_x0C_Dev5BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev5BridgeDis_MASK                          0x20
+#define D0F0x64_x0C_Dev6BridgeDis_OFFSET                        6
+#define D0F0x64_x0C_Dev6BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev6BridgeDis_MASK                          0x40
+#define D0F0x64_x0C_Dev7BridgeDis_OFFSET                        7
+#define D0F0x64_x0C_Dev7BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev7BridgeDis_MASK                          0x80
+#define D0F0x64_x0C_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x0C_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x0C_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            Dev2BridgeDis:1 ; ///<
+    UINT32                                            Dev3BridgeDis:1 ; ///<
+    UINT32                                            Dev4BridgeDis:1 ; ///<
+    UINT32                                            Dev5BridgeDis:1 ; ///<
+    UINT32                                            Dev6BridgeDis:1 ; ///<
+    UINT32                                            Dev7BridgeDis:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0C_STRUCT;
+
+// **** D0F0x64_x0D Register Definition ****
+// Address
+#define D0F0x64_x0D_ADDRESS                                     0xd
+
+// Type
+#define D0F0x64_x0D_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET                      0
+#define D0F0x64_x0D_PciDev0Fn2RegEn_WIDTH                       1
+#define D0F0x64_x0D_PciDev0Fn2RegEn_MASK                        0x1
+#define D0F0x64_x0D_Reserved_31_1_OFFSET                        1
+#define D0F0x64_x0D_Reserved_31_1_WIDTH                         31
+#define D0F0x64_x0D_Reserved_31_1_MASK                          0xfffffffe
+
+/// D0F0x64_x0D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          PciDev0Fn2RegEn:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0D_STRUCT;
+
+// **** D0F0x64_x16 Register Definition ****
+// Address
+#define D0F0x64_x16_ADDRESS                                     0x16
+
+// Type
+#define D0F0x64_x16_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x16_AerUrMsgEn_OFFSET                           0
+#define D0F0x64_x16_AerUrMsgEn_WIDTH                            1
+#define D0F0x64_x16_AerUrMsgEn_MASK                             0x1
+#define D0F0x64_x16_Reserved_31_1_OFFSET                        1
+#define D0F0x64_x16_Reserved_31_1_WIDTH                         31
+#define D0F0x64_x16_Reserved_31_1_MASK                          0xfffffffe
+
+/// D0F0x64_x16
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               AerUrMsgEn:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x16_STRUCT;
+
+// **** D0F0x64_x19 Register Definition ****
+// Address
+#define D0F0x64_x19_ADDRESS                                     0x19
+
+// Type
+#define D0F0x64_x19_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x19_TomEn_OFFSET                                0
+#define D0F0x64_x19_TomEn_WIDTH                                 1
+#define D0F0x64_x19_TomEn_MASK                                  0x1
+#define D0F0x64_x19_Reserved_22_1_OFFSET                        1
+#define D0F0x64_x19_Reserved_22_1_WIDTH                         22
+#define D0F0x64_x19_Reserved_22_1_MASK                          0x7ffffe
+#define D0F0x64_x19_Tom2_31_23__OFFSET                          23
+#define D0F0x64_x19_Tom2_31_23__WIDTH                           9
+#define D0F0x64_x19_Tom2_31_23__MASK                            0xff800000
+
+/// D0F0x64_x19
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    TomEn:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                              Tom2_31_23_:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x19_STRUCT;
+
+// **** D0F0x64_x1A Register Definition ****
+// Address
+#define D0F0x64_x1A_ADDRESS                                     0x1a
+
+// Type
+#define D0F0x64_x1A_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1A_Tom2_39_32__OFFSET                          0
+#define D0F0x64_x1A_Tom2_39_32__WIDTH                           8
+#define D0F0x64_x1A_Tom2_39_32__MASK                            0xff
+#define D0F0x64_x1A_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x1A_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x1A_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x1A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Tom2_39_32_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1A_STRUCT;
+
+// **** D0F0x64_x1C Register Definition ****
+// Address
+#define D0F0x64_x1C_ADDRESS                                     0x1c
+
+// Type
+#define D0F0x64_x1C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1C_WriteDis_OFFSET                             0
+#define D0F0x64_x1C_WriteDis_WIDTH                              1
+#define D0F0x64_x1C_WriteDis_MASK                               0x1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET              1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH               1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK                0x2
+#define D0F0x64_x1C_F064BarEn_OFFSET                            2
+#define D0F0x64_x1C_F064BarEn_WIDTH                             1
+#define D0F0x64_x1C_F064BarEn_MASK                              0x4
+#define D0F0x64_x1C_MemApSize_OFFSET                            3
+#define D0F0x64_x1C_MemApSize_WIDTH                             3
+#define D0F0x64_x1C_MemApSize_MASK                              0x38
+#define D0F0x64_x1C_RegApSize_OFFSET                            6
+#define D0F0x64_x1C_RegApSize_WIDTH                             1
+#define D0F0x64_x1C_RegApSize_MASK                              0x40
+#define D0F0x64_x1C_Reserved_7_7_OFFSET                         7
+#define D0F0x64_x1C_Reserved_7_7_WIDTH                          1
+#define D0F0x64_x1C_Reserved_7_7_MASK                           0x80
+#define D0F0x64_x1C_AudioEn_OFFSET                              8
+#define D0F0x64_x1C_AudioEn_WIDTH                               1
+#define D0F0x64_x1C_AudioEn_MASK                                0x100
+#define D0F0x64_x1C_MsiDis_OFFSET                               9
+#define D0F0x64_x1C_MsiDis_WIDTH                                1
+#define D0F0x64_x1C_MsiDis_MASK                                 0x200
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET           10
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH            1
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK             0x400
+#define D0F0x64_x1C_Audio64BarEn_OFFSET                         11
+#define D0F0x64_x1C_Audio64BarEn_WIDTH                          1
+#define D0F0x64_x1C_Audio64BarEn_MASK                           0x800
+#define D0F0x64_x1C_Reserved_15_12_OFFSET                       12
+#define D0F0x64_x1C_Reserved_15_12_WIDTH                        4
+#define D0F0x64_x1C_Reserved_15_12_MASK                         0xf000
+#define D0F0x64_x1C_IoBarDis_OFFSET                             16
+#define D0F0x64_x1C_IoBarDis_WIDTH                              1
+#define D0F0x64_x1C_IoBarDis_MASK                               0x10000
+#define D0F0x64_x1C_F0En_OFFSET                                 17
+#define D0F0x64_x1C_F0En_WIDTH                                  1
+#define D0F0x64_x1C_F0En_MASK                                   0x20000
+#define D0F0x64_x1C_Reserved_22_18_OFFSET                       18
+#define D0F0x64_x1C_Reserved_22_18_WIDTH                        5
+#define D0F0x64_x1C_Reserved_22_18_MASK                         0x7c0000
+#define D0F0x64_x1C_RcieEn_OFFSET                               23
+#define D0F0x64_x1C_RcieEn_WIDTH                                1
+#define D0F0x64_x1C_RcieEn_MASK                                 0x800000
+#define D0F0x64_x1C_Reserved_31_24_OFFSET                       24
+#define D0F0x64_x1C_Reserved_31_24_WIDTH                        8
+#define D0F0x64_x1C_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x64_x1C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 WriteDis:1 ; ///<
+    UINT32                                  F0NonlegacyDeviceTypeEn:1 ; ///<
+    UINT32                                                F064BarEn:1 ; ///<
+    UINT32                                                MemApSize:3 ; ///<
+    UINT32                                                RegApSize:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                  AudioEn:1 ; ///<
+    UINT32                                                   MsiDis:1 ; ///<
+    UINT32                               AudioNonlegacyDeviceTypeEn:1 ; ///<
+    UINT32                                             Audio64BarEn:1 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                 IoBarDis:1 ; ///<
+    UINT32                                                     F0En:1 ; ///<
+    UINT32                                           Reserved_22_18:5 ; ///<
+    UINT32                                                   RcieEn:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1C_STRUCT;
+
+// **** D0F0x64_x1D Register Definition ****
+// Address
+#define D0F0x64_x1D_ADDRESS                                     0x1d
+
+// Type
+#define D0F0x64_x1D_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET                       0
+#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH                        1
+#define D0F0x64_x1D_IntGfxAsPcieEn_MASK                         0x1
+#define D0F0x64_x1D_VgaEn_OFFSET                                1
+#define D0F0x64_x1D_VgaEn_WIDTH                                 1
+#define D0F0x64_x1D_VgaEn_MASK                                  0x2
+#define D0F0x64_x1D_Reserved_2_2_OFFSET                         2
+#define D0F0x64_x1D_Reserved_2_2_WIDTH                          1
+#define D0F0x64_x1D_Reserved_2_2_MASK                           0x4
+#define D0F0x64_x1D_Vga16En_OFFSET                              3
+#define D0F0x64_x1D_Vga16En_WIDTH                               1
+#define D0F0x64_x1D_Vga16En_MASK                                0x8
+#define D0F0x64_x1D_Reserved_31_4_OFFSET                        4
+#define D0F0x64_x1D_Reserved_31_4_WIDTH                         28
+#define D0F0x64_x1D_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F0x64_x1D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           IntGfxAsPcieEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1D_STRUCT;
+
+// **** D0F0x64_x20 Register Definition ****
+// Address
+#define D0F0x64_x20_ADDRESS                                     0x20
+
+// Type
+#define D0F0x64_x20_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x20_ProgDevMapEn_OFFSET                         0
+#define D0F0x64_x20_ProgDevMapEn_WIDTH                          1
+#define D0F0x64_x20_ProgDevMapEn_MASK                           0x1
+#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET                   1
+#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH                    1
+#define D0F0x64_x20_IocPcieDevRemapDis_MASK                     0x2
+#define D0F0x64_x20_Reserved_3_2_OFFSET                         2
+#define D0F0x64_x20_Reserved_3_2_WIDTH                          2
+#define D0F0x64_x20_Reserved_3_2_MASK                           0xc
+#define D0F0x64_x20_GppPortBDevmap_OFFSET                       4
+#define D0F0x64_x20_GppPortBDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortBDevmap_MASK                         0xf0
+#define D0F0x64_x20_GppPortCDevmap_OFFSET                       8
+#define D0F0x64_x20_GppPortCDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortCDevmap_MASK                         0xf00
+#define D0F0x64_x20_GppPortDDevmap_OFFSET                       12
+#define D0F0x64_x20_GppPortDDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortDDevmap_MASK                         0xf000
+#define D0F0x64_x20_GppPortEDevmap_OFFSET                       16
+#define D0F0x64_x20_GppPortEDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortEDevmap_MASK                         0xf0000
+#define D0F0x64_x20_Reserved_31_20_OFFSET                       20
+#define D0F0x64_x20_Reserved_31_20_WIDTH                        12
+#define D0F0x64_x20_Reserved_31_20_MASK                         0xfff00000
+
+/// D0F0x64_x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             ProgDevMapEn:1 ; ///<
+    UINT32                                       IocPcieDevRemapDis:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                           GppPortBDevmap:4 ; ///<
+    UINT32                                           GppPortCDevmap:4 ; ///<
+    UINT32                                           GppPortDDevmap:4 ; ///<
+    UINT32                                           GppPortEDevmap:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x20_STRUCT;
+
+// **** D0F0x64_x21 Register Definition ****
+// Address
+#define D0F0x64_x21_ADDRESS                                     0x21
+
+// Type
+#define D0F0x64_x21_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x21_Reserved_11_0_OFFSET                        0
+#define D0F0x64_x21_Reserved_11_0_WIDTH                         12
+#define D0F0x64_x21_Reserved_11_0_MASK                          0xfff
+#define D0F0x64_x21_GfxPortADevmap_OFFSET                       12
+#define D0F0x64_x21_GfxPortADevmap_WIDTH                        4
+#define D0F0x64_x21_GfxPortADevmap_MASK                         0xf000
+#define D0F0x64_x21_GfxPortBDevmap_OFFSET                       16
+#define D0F0x64_x21_GfxPortBDevmap_WIDTH                        4
+#define D0F0x64_x21_GfxPortBDevmap_MASK                         0xf0000
+#define D0F0x64_x21_Reserved_31_20_OFFSET                       20
+#define D0F0x64_x21_Reserved_31_20_WIDTH                        12
+#define D0F0x64_x21_Reserved_31_20_MASK                         0xfff00000
+
+/// D0F0x64_x21
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           GfxPortADevmap:4 ; ///<
+    UINT32                                           GfxPortBDevmap:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x21_STRUCT;
+
+// **** D0F0x64_x22 Register Definition ****
+// Address
+#define D0F0x64_x22_ADDRESS                                     0x22
+
+// Type
+#define D0F0x64_x22_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x22_Reserved_25_0_OFFSET                        0
+#define D0F0x64_x22_Reserved_25_0_WIDTH                         26
+#define D0F0x64_x22_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x64_x22_SoftOverrideClk4_OFFSET                     26
+#define D0F0x64_x22_SoftOverrideClk4_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x64_x22_SoftOverrideClk3_OFFSET                     27
+#define D0F0x64_x22_SoftOverrideClk3_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x64_x22_SoftOverrideClk2_OFFSET                     28
+#define D0F0x64_x22_SoftOverrideClk2_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x64_x22_SoftOverrideClk1_OFFSET                     29
+#define D0F0x64_x22_SoftOverrideClk1_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x64_x22_SoftOverrideClk0_OFFSET                     30
+#define D0F0x64_x22_SoftOverrideClk0_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x64_x22_Reserved_31_31_OFFSET                       31
+#define D0F0x64_x22_Reserved_31_31_WIDTH                        1
+#define D0F0x64_x22_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x64_x22
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x22_STRUCT;
+
+// **** D0F0x64_x23 Register Definition ****
+// Address
+#define D0F0x64_x23_ADDRESS                                     0x23
+
+// Type
+#define D0F0x64_x23_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x23_Reserved_25_0_OFFSET                        0
+#define D0F0x64_x23_Reserved_25_0_WIDTH                         26
+#define D0F0x64_x23_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x64_x23_SoftOverrideClk4_OFFSET                     26
+#define D0F0x64_x23_SoftOverrideClk4_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x64_x23_SoftOverrideClk3_OFFSET                     27
+#define D0F0x64_x23_SoftOverrideClk3_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x64_x23_SoftOverrideClk2_OFFSET                     28
+#define D0F0x64_x23_SoftOverrideClk2_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x64_x23_SoftOverrideClk1_OFFSET                     29
+#define D0F0x64_x23_SoftOverrideClk1_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x64_x23_SoftOverrideClk0_OFFSET                     30
+#define D0F0x64_x23_SoftOverrideClk0_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x64_x23_Reserved_31_31_OFFSET                       31
+#define D0F0x64_x23_Reserved_31_31_WIDTH                        1
+#define D0F0x64_x23_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x64_x23
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x23_STRUCT;
+
+
+// **** D0F0x64_x46 Register Definition ****
+// Address
+#define D0F0x64_x46_ADDRESS                                     0x46
+
+// Type
+#define D0F0x64_x46_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x46_Reserved_0_0_OFFSET                         0
+#define D0F0x64_x46_Reserved_0_0_WIDTH                          1
+#define D0F0x64_x46_Reserved_0_0_MASK                           0x1
+#define D0F0x64_x46_Reserved_15_3_OFFSET                        3
+#define D0F0x64_x46_Reserved_15_3_WIDTH                         13
+#define D0F0x64_x46_Reserved_15_3_MASK                          0xfff8
+#define D0F0x64_x46_Msi64bitEn_OFFSET                           16
+#define D0F0x64_x46_Msi64bitEn_WIDTH                            1
+#define D0F0x64_x46_Msi64bitEn_MASK                             0x10000
+#define D0F0x64_x46_Reserved_31_17_OFFSET                       17
+#define D0F0x64_x46_Reserved_31_17_WIDTH                        15
+#define D0F0x64_x46_Reserved_31_17_MASK                         0xfffe0000
+
+/// D0F0x64_x46
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  :2 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                               Msi64bitEn:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x46_STRUCT;
+
+
+// **** D0F0x64_x53 Register Definition ****
+// Address
+#define D0F0x64_x53_ADDRESS                                     0x53
+
+// Type
+#define D0F0x64_x53_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x53_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x53_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x53_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x53_SetPowEn_OFFSET                             20
+#define D0F0x64_x53_SetPowEn_WIDTH                              1
+#define D0F0x64_x53_SetPowEn_MASK                               0x100000
+#define D0F0x64_x53_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x53_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x53_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x53
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x53_STRUCT;
+
+// **** D0F0x64_x55 Register Definition ****
+// Address
+#define D0F0x64_x55_ADDRESS                                     0x55
+
+// Type
+#define D0F0x64_x55_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x55_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x55_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x55_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x55_SetPowEn_OFFSET                             20
+#define D0F0x64_x55_SetPowEn_WIDTH                              1
+#define D0F0x64_x55_SetPowEn_MASK                               0x100000
+#define D0F0x64_x55_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x55_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x55_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x55
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x55_STRUCT;
+
+// **** D0F0x64_x57 Register Definition ****
+// Address
+#define D0F0x64_x57_ADDRESS                                     0x57
+
+// Type
+#define D0F0x64_x57_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x57_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x57_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x57_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x57_SetPowEn_OFFSET                             20
+#define D0F0x64_x57_SetPowEn_WIDTH                              1
+#define D0F0x64_x57_SetPowEn_MASK                               0x100000
+#define D0F0x64_x57_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x57_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x57_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x57
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x57_STRUCT;
+
+// **** D0F0x64_x59 Register Definition ****
+// Address
+#define D0F0x64_x59_ADDRESS                                     0x59
+
+// Type
+#define D0F0x64_x59_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x59_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x59_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x59_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x59_SetPowEn_OFFSET                             20
+#define D0F0x64_x59_SetPowEn_WIDTH                              1
+#define D0F0x64_x59_SetPowEn_MASK                               0x100000
+#define D0F0x64_x59_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x59_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x59_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x59
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x59_STRUCT;
+
+// **** D0F0x64_x5B Register Definition ****
+// Address
+#define D0F0x64_x5B_ADDRESS                                     0x5b
+
+// Type
+#define D0F0x64_x5B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x5B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x5B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x5B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x5B_SetPowEn_OFFSET                             20
+#define D0F0x64_x5B_SetPowEn_WIDTH                              1
+#define D0F0x64_x5B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x5B_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x5B_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x5B_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x5B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x5B_STRUCT;
+
+// **** D0F0x98_x06 Register Definition ****
+// Address
+#define D0F0x98_x06_ADDRESS                                     0x6
+
+// Type
+#define D0F0x98_x06_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x06_Reserved_25_0_OFFSET                        0
+#define D0F0x98_x06_Reserved_25_0_WIDTH                         26
+#define D0F0x98_x06_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x98_x06_UmiNpMemWrEn_OFFSET                         26
+#define D0F0x98_x06_UmiNpMemWrEn_WIDTH                          1
+#define D0F0x98_x06_UmiNpMemWrEn_MASK                           0x4000000
+#define D0F0x98_x06_Reserved_31_27_OFFSET                       27
+#define D0F0x98_x06_Reserved_31_27_WIDTH                        5
+#define D0F0x98_x06_Reserved_31_27_MASK                         0xf8000000
+
+/// D0F0x98_x06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                             UmiNpMemWrEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x06_STRUCT;
+
+// **** D0F0x98_x07 Register Definition ****
+// Address
+#define D0F0x98_x07_ADDRESS                                     0x7
+
+// Type
+#define D0F0x98_x07_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x07_IocBwOptEn_OFFSET                           0
+#define D0F0x98_x07_IocBwOptEn_WIDTH                            1
+#define D0F0x98_x07_IocBwOptEn_MASK                             0x1
+#define D0F0x98_x07_Reserved_3_1_OFFSET                         1
+#define D0F0x98_x07_Reserved_3_1_WIDTH                          3
+#define D0F0x98_x07_Reserved_3_1_MASK                           0xe
+#define D0F0x98_x07_IommuBwOptEn_OFFSET                         4
+#define D0F0x98_x07_IommuBwOptEn_WIDTH                          1
+#define D0F0x98_x07_IommuBwOptEn_MASK                           0x10
+#define D0F0x98_x07_Reserved_5_5_OFFSET                         5
+#define D0F0x98_x07_Reserved_5_5_WIDTH                          1
+#define D0F0x98_x07_Reserved_5_5_MASK                           0x20
+#define D0F0x98_x07_DmaReqRespPassPWMode_OFFSET                 6
+#define D0F0x98_x07_DmaReqRespPassPWMode_WIDTH                  1
+#define D0F0x98_x07_DmaReqRespPassPWMode_MASK                   0x40
+#define D0F0x98_x07_IommuIsocPassPWMode_OFFSET                  7
+#define D0F0x98_x07_IommuIsocPassPWMode_WIDTH                   1
+#define D0F0x98_x07_IommuIsocPassPWMode_MASK                    0x80
+#define D0F0x98_x07_Reserved_13_8_OFFSET                        8
+#define D0F0x98_x07_Reserved_13_8_WIDTH                         6
+#define D0F0x98_x07_Reserved_13_8_MASK                          0x3f00
+#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET                 14
+#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH                  1
+#define D0F0x98_x07_MSIHTIntConversionEn_MASK                   0x4000
+#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET                     15
+#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH                      1
+#define D0F0x98_x07_DropZeroMaskWrEn_MASK                       0x8000
+#define D0F0x98_x07_Reserved_29_16_OFFSET                       16
+#define D0F0x98_x07_Reserved_29_16_WIDTH                        14
+#define D0F0x98_x07_Reserved_29_16_MASK                         0x3fff0000
+#define D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET             30
+#define D0F0x98_x07_UnadjustThrottlingStpclk_WIDTH              1
+#define D0F0x98_x07_UnadjustThrottlingStpclk_MASK               0x40000000
+#define D0F0x98_x07_SMUCsrIsocEn_OFFSET                         31
+#define D0F0x98_x07_SMUCsrIsocEn_WIDTH                          1
+#define D0F0x98_x07_SMUCsrIsocEn_MASK                           0x80000000
+
+/// D0F0x98_x07
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IocBwOptEn:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                             IommuBwOptEn:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                     DmaReqRespPassPWMode:1 ; ///<
+    UINT32                                      IommuIsocPassPWMode:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                     MSIHTIntConversionEn:1 ; ///<
+    UINT32                                         DropZeroMaskWrEn:1 ; ///<
+    UINT32                                           Reserved_29_16:14; ///<
+    UINT32                                 UnadjustThrottlingStpclk:1 ; ///<
+    UINT32                                             SMUCsrIsocEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x07_STRUCT;
+
+// **** D0F0x98_x08 Register Definition ****
+// Address
+#define D0F0x98_x08_ADDRESS                                     0x8
+
+// Type
+#define D0F0x98_x08_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x08_NpWrrLenA_OFFSET                            0
+#define D0F0x98_x08_NpWrrLenA_WIDTH                             8
+#define D0F0x98_x08_NpWrrLenA_MASK                              0xff
+#define D0F0x98_x08_NpWrrLenB_OFFSET                            8
+#define D0F0x98_x08_NpWrrLenB_WIDTH                             8
+#define D0F0x98_x08_NpWrrLenB_MASK                              0xff00
+#define D0F0x98_x08_NpWrrLenC_OFFSET                            16
+#define D0F0x98_x08_NpWrrLenC_WIDTH                             8
+#define D0F0x98_x08_NpWrrLenC_MASK                              0xff0000
+#define D0F0x98_x08_Reserved_31_24_OFFSET                       24
+#define D0F0x98_x08_Reserved_31_24_WIDTH                        8
+#define D0F0x98_x08_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x98_x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                NpWrrLenA:8 ; ///<
+    UINT32                                                NpWrrLenB:8 ; ///<
+    UINT32                                                NpWrrLenC:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x08_STRUCT;
+
+// **** D0F0x98_x09 Register Definition ****
+// Address
+#define D0F0x98_x09_ADDRESS                                     0x9
+
+// Type
+#define D0F0x98_x09_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x09_PWrrLenA_OFFSET                             0
+#define D0F0x98_x09_PWrrLenA_WIDTH                              8
+#define D0F0x98_x09_PWrrLenA_MASK                               0xff
+#define D0F0x98_x09_PWrrLenB_OFFSET                             8
+#define D0F0x98_x09_PWrrLenB_WIDTH                              8
+#define D0F0x98_x09_PWrrLenB_MASK                               0xff00
+#define D0F0x98_x09_Reserved_31_16_OFFSET                       16
+#define D0F0x98_x09_Reserved_31_16_WIDTH                        16
+#define D0F0x98_x09_Reserved_31_16_MASK                         0xffff0000
+
+/// D0F0x98_x09
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 PWrrLenA:8 ; ///<
+    UINT32                                                 PWrrLenB:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x09_STRUCT;
+
+// **** D0F0x98_x0C Register Definition ****
+// Address
+#define D0F0x98_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x98_x0C_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x0C_GcmWrrLenA_OFFSET                           0
+#define D0F0x98_x0C_GcmWrrLenA_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenA_MASK                             0xff
+#define D0F0x98_x0C_GcmWrrLenB_OFFSET                           8
+#define D0F0x98_x0C_GcmWrrLenB_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenB_MASK                             0xff00
+#define D0F0x98_x0C_Reserved_29_16_OFFSET                       16
+#define D0F0x98_x0C_Reserved_29_16_WIDTH                        14
+#define D0F0x98_x0C_Reserved_29_16_MASK                         0x3fff0000
+#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET                    30
+#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH                     1
+#define D0F0x98_x0C_StrictSelWinnerEn_MASK                      0x40000000
+#define D0F0x98_x0C_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x0C_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x0C_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               GcmWrrLenA:8 ; ///<
+    UINT32                                               GcmWrrLenB:8 ; ///<
+    UINT32                                           Reserved_29_16:14; ///<
+    UINT32                                        StrictSelWinnerEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x0C_STRUCT;
+
+// **** D0F0x98_x1E Register Definition ****
+// Address
+#define D0F0x98_x1E_ADDRESS                                     0x1e
+
+// Type
+#define D0F0x98_x1E_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x1E_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x1E_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x1E_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x1E_HiPriEn_OFFSET                              1
+#define D0F0x98_x1E_HiPriEn_WIDTH                               1
+#define D0F0x98_x1E_HiPriEn_MASK                                0x2
+#define D0F0x98_x1E_Reserved_31_2_OFFSET                        2
+#define D0F0x98_x1E_Reserved_31_2_WIDTH                         30
+#define D0F0x98_x1E_Reserved_31_2_MASK                          0xfffffffc
+
+/// D0F0x98_x1E
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  HiPriEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x1E_STRUCT;
+
+// **** D0F0x98_x26 Register Definition ****
+// Address
+#define D0F0x98_x26_ADDRESS                                     0x26
+
+// Type
+#define D0F0x98_x26_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x26_IOMMUUrAddr_39_32__OFFSET                   0
+#define D0F0x98_x26_IOMMUUrAddr_39_32__WIDTH                    8
+#define D0F0x98_x26_IOMMUUrAddr_39_32__MASK                     0xff
+#define D0F0x98_x26_Reserved_31_8_OFFSET                        8
+#define D0F0x98_x26_Reserved_31_8_WIDTH                         24
+#define D0F0x98_x26_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x98_x26
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       IOMMUUrAddr_39_32_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x26_STRUCT;
+
+// **** D0F0x98_x27 Register Definition ****
+// Address
+#define D0F0x98_x27_ADDRESS                                     0x27
+
+// Type
+#define D0F0x98_x27_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x27_Reserved_5_0_OFFSET                         0
+#define D0F0x98_x27_Reserved_5_0_WIDTH                          6
+#define D0F0x98_x27_Reserved_5_0_MASK                           0x3f
+#define D0F0x98_x27_IOMMUUrAddr_31_6__OFFSET                    6
+#define D0F0x98_x27_IOMMUUrAddr_31_6__WIDTH                     26
+#define D0F0x98_x27_IOMMUUrAddr_31_6__MASK                      0xffffffc0
+
+/// D0F0x98_x27
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_5_0:6 ; ///<
+    UINT32                                        IOMMUUrAddr_31_6_:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x27_STRUCT;
+
+// **** D0F0x98_x28 Register Definition ****
+// Address
+#define D0F0x98_x28_ADDRESS                                     0x28
+
+// Type
+#define D0F0x98_x28_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x28_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x28_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x28_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x28_ForceCoherentIntr_OFFSET                    1
+#define D0F0x98_x28_ForceCoherentIntr_WIDTH                     1
+#define D0F0x98_x28_ForceCoherentIntr_MASK                      0x2
+#define D0F0x98_x28_Reserved_31_2_OFFSET                        2
+#define D0F0x98_x28_Reserved_31_2_WIDTH                         30
+#define D0F0x98_x28_Reserved_31_2_MASK                          0xfffffffc
+
+/// D0F0x98_x28
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                        ForceCoherentIntr:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x28_STRUCT;
+
+
+// **** D0F0x98_x2C Register Definition ****
+// Address
+#define D0F0x98_x2C_ADDRESS                                     0x2c
+
+// Type
+#define D0F0x98_x2C_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x2C_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x2C_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x2C_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x2C_DynWakeEn_OFFSET                            1
+#define D0F0x98_x2C_DynWakeEn_WIDTH                             1
+#define D0F0x98_x2C_DynWakeEn_MASK                              0x2
+#define D0F0x98_x2C_Reserved_7_2_OFFSET                         2
+#define D0F0x98_x2C_Reserved_7_2_WIDTH                          6
+#define D0F0x98_x2C_Reserved_7_2_MASK                           0xfc
+#define D0F0x98_x2C_OrbRxIdlesMask_OFFSET                       8
+#define D0F0x98_x2C_OrbRxIdlesMask_WIDTH                        1
+#define D0F0x98_x2C_OrbRxIdlesMask_MASK                         0x100
+#define D0F0x98_x2C_SBDmaActiveMask_OFFSET                      9
+#define D0F0x98_x2C_SBDmaActiveMask_WIDTH                       1
+#define D0F0x98_x2C_SBDmaActiveMask_MASK                        0x200
+#define D0F0x98_x2C_NBOutbWakeMask_OFFSET                       10
+#define D0F0x98_x2C_NBOutbWakeMask_WIDTH                        1
+#define D0F0x98_x2C_NBOutbWakeMask_MASK                         0x400
+#define D0F0x98_x2C_Reserved_15_11_OFFSET                       11
+#define D0F0x98_x2C_Reserved_15_11_WIDTH                        5
+#define D0F0x98_x2C_Reserved_15_11_MASK                         0xf800
+#define D0F0x98_x2C_WakeHysteresis_OFFSET                       16
+#define D0F0x98_x2C_WakeHysteresis_WIDTH                        16
+#define D0F0x98_x2C_WakeHysteresis_MASK                         0xffff0000
+
+/// D0F0x98_x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                DynWakeEn:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                           OrbRxIdlesMask:1 ; ///<
+    UINT32                                          SBDmaActiveMask:1 ; ///<
+    UINT32                                           NBOutbWakeMask:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           WakeHysteresis:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x2C_STRUCT;
+
+// **** D0F0x98_x3A Register Definition ****
+// Address
+#define D0F0x98_x3A_ADDRESS                                     0x3a
+
+// Type
+#define D0F0x98_x3A_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x3A_ClumpingEn_OFFSET                           0
+#define D0F0x98_x3A_ClumpingEn_WIDTH                            32
+#define D0F0x98_x3A_ClumpingEn_MASK                             0xffffffff
+
+/// D0F0x98_x3A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               ClumpingEn:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x3A_STRUCT;
+
+// **** D0F0x98_x49 Register Definition ****
+// Address
+#define D0F0x98_x49_ADDRESS                                     0x49
+
+// Type
+#define D0F0x98_x49_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x49_Reserved_23_0_OFFSET                        0
+#define D0F0x98_x49_Reserved_23_0_WIDTH                         24
+#define D0F0x98_x49_Reserved_23_0_MASK                          0xffffff
+#define D0F0x98_x49_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x49_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x49_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x49_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x49_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x49_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x49_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x49_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x49_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x49_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x49_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x49_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x49_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x49_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x49_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x49_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x49_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x49
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x49_STRUCT;
+
+// **** D0F0x98_x4A Register Definition ****
+// Address
+#define D0F0x98_x4A_ADDRESS                                     0x4a
+
+// Type
+#define D0F0x98_x4A_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x4A_Reserved_23_0_OFFSET                        0
+#define D0F0x98_x4A_Reserved_23_0_WIDTH                         24
+#define D0F0x98_x4A_Reserved_23_0_MASK                          0xffffff
+#define D0F0x98_x4A_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x4A_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x4A_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x4A_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x4A_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x4A_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x4A_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x4A_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x4A_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x4A_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x4A_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x4A_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x4A_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x4A_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x4A_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x4A_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x4A_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x4A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x4A_STRUCT;
+
+// **** D0F0xBC_x1F200 Register Definition ****
+// Address
+#define D0F0xBC_x1F200_ADDRESS                                  0x1f200
+
+// Type
+#define D0F0xBC_x1F200_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F200_StateValid_OFFSET                        0
+#define D0F0xBC_x1F200_StateValid_WIDTH                         1
+#define D0F0xBC_x1F200_StateValid_MASK                          0x1
+#define D0F0xBC_x1F200_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F200_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F200_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F200_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F200_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F200_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F200_VID_OFFSET                               16
+#define D0F0xBC_x1F200_VID_WIDTH                                8
+#define D0F0xBC_x1F200_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F200_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F200_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F200_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F200
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F200_STRUCT;
+
+// **** D0F0xBC_x1F208 Register Definition ****
+// Address
+#define D0F0xBC_x1F208_ADDRESS                                  0x1f208
+
+// Type
+#define D0F0xBC_x1F208_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F208_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F208_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F208_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F208_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F208_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F208_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F208_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F208_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F208_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F208
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F208_STRUCT;
+
+// **** D0F0xBC_x1F210 Register Definition ****
+// Address
+#define D0F0xBC_x1F210_ADDRESS                                  0x1f210
+
+// Type
+#define D0F0xBC_x1F210_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F210_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F210_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F210_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F210_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F210_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F210_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F210
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F210_STRUCT;
+
+// **** D0F0xBC_x1F220 Register Definition ****
+// Address
+#define D0F0xBC_x1F220_ADDRESS                                  0x1f220
+
+// Type
+#define D0F0xBC_x1F220_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F220_StateValid_OFFSET                        0
+#define D0F0xBC_x1F220_StateValid_WIDTH                         1
+#define D0F0xBC_x1F220_StateValid_MASK                          0x1
+#define D0F0xBC_x1F220_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F220_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F220_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F220_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F220_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F220_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F220_VID_OFFSET                               16
+#define D0F0xBC_x1F220_VID_WIDTH                                8
+#define D0F0xBC_x1F220_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F220_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F220_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F220_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F220
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F220_STRUCT;
+
+// **** D0F0xBC_x1F228 Register Definition ****
+// Address
+#define D0F0xBC_x1F228_ADDRESS                                  0x1f228
+
+// Type
+#define D0F0xBC_x1F228_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F228_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F228_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F228_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F228_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F228_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F228_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F228_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F228_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F228_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F228
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F228_STRUCT;
+
+// **** D0F0xBC_x1F230 Register Definition ****
+// Address
+#define D0F0xBC_x1F230_ADDRESS                                  0x1f230
+
+// Type
+#define D0F0xBC_x1F230_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F230_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F230_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F230_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F230_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F230_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F230_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F230
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F230_STRUCT;
+
+// **** D0F0xBC_x1F240 Register Definition ****
+// Address
+#define D0F0xBC_x1F240_ADDRESS                                  0x1f240
+
+// Type
+#define D0F0xBC_x1F240_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F240_StateValid_OFFSET                        0
+#define D0F0xBC_x1F240_StateValid_WIDTH                         1
+#define D0F0xBC_x1F240_StateValid_MASK                          0x1
+#define D0F0xBC_x1F240_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F240_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F240_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F240_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F240_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F240_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F240_VID_OFFSET                               16
+#define D0F0xBC_x1F240_VID_WIDTH                                8
+#define D0F0xBC_x1F240_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F240_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F240_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F240_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F240
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F240_STRUCT;
+
+// **** D0F0xBC_x1F248 Register Definition ****
+// Address
+#define D0F0xBC_x1F248_ADDRESS                                  0x1f248
+
+// Type
+#define D0F0xBC_x1F248_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F248_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F248_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F248_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F248_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F248_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F248_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F248_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F248_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F248_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F248
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F248_STRUCT;
+
+// **** D0F0xBC_x1F250 Register Definition ****
+// Address
+#define D0F0xBC_x1F250_ADDRESS                                  0x1f250
+
+// Type
+#define D0F0xBC_x1F250_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F250_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F250_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F250_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F250_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F250_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F250_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F250
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F250_STRUCT;
+
+// **** D0F0xBC_x1F260 Register Definition ****
+// Address
+#define D0F0xBC_x1F260_ADDRESS                                  0x1f260
+
+// Type
+#define D0F0xBC_x1F260_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F260_StateValid_OFFSET                        0
+#define D0F0xBC_x1F260_StateValid_WIDTH                         1
+#define D0F0xBC_x1F260_StateValid_MASK                          0x1
+#define D0F0xBC_x1F260_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F260_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F260_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F260_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F260_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F260_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F260_VID_OFFSET                               16
+#define D0F0xBC_x1F260_VID_WIDTH                                8
+#define D0F0xBC_x1F260_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F260_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F260_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F260_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F260
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F260_STRUCT;
+
+// **** D0F0xBC_x1F268 Register Definition ****
+// Address
+#define D0F0xBC_x1F268_ADDRESS                                  0x1f268
+
+// Type
+#define D0F0xBC_x1F268_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F268_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F268_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F268_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F268_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F268_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F268_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F268_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F268_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F268_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F268
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F268_STRUCT;
+
+// **** D0F0xBC_x1F270 Register Definition ****
+// Address
+#define D0F0xBC_x1F270_ADDRESS                                  0x1f270
+
+// Type
+#define D0F0xBC_x1F270_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F270_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F270_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F270_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F270_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F270_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F270_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F270
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F270_STRUCT;
+
+// **** D0F0xBC_x1F280 Register Definition ****
+// Address
+#define D0F0xBC_x1F280_ADDRESS                                  0x1f280
+
+// Type
+#define D0F0xBC_x1F280_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F280_StateValid_OFFSET                        0
+#define D0F0xBC_x1F280_StateValid_WIDTH                         1
+#define D0F0xBC_x1F280_StateValid_MASK                          0x1
+#define D0F0xBC_x1F280_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F280_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F280_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F280_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F280_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F280_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F280_VID_OFFSET                               16
+#define D0F0xBC_x1F280_VID_WIDTH                                8
+#define D0F0xBC_x1F280_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F280_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F280_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F280_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F280
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F280_STRUCT;
+
+// **** D0F0xBC_x1F288 Register Definition ****
+// Address
+#define D0F0xBC_x1F288_ADDRESS                                  0x1f288
+
+// Type
+#define D0F0xBC_x1F288_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F288_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F288_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F288_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F288_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F288_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F288_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F288_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F288_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F288_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F288
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F288_STRUCT;
+
+// **** D0F0xBC_x1F290 Register Definition ****
+// Address
+#define D0F0xBC_x1F290_ADDRESS                                  0x1f290
+
+// Type
+#define D0F0xBC_x1F290_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F290_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F290_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F290_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F290_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F290_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F290_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F290
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F290_STRUCT;
+
+// **** D0F0xBC_x1F2A0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2A0_ADDRESS                                  0x1f2a0
+
+// Type
+#define D0F0xBC_x1F2A0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2A0_StateValid_OFFSET                        0
+#define D0F0xBC_x1F2A0_StateValid_WIDTH                         1
+#define D0F0xBC_x1F2A0_StateValid_MASK                          0x1
+#define D0F0xBC_x1F2A0_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F2A0_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F2A0_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F2A0_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F2A0_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F2A0_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F2A0_VID_OFFSET                               16
+#define D0F0xBC_x1F2A0_VID_WIDTH                                8
+#define D0F0xBC_x1F2A0_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F2A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2A0_STRUCT;
+
+// **** D0F0xBC_x1F2A8 Register Definition ****
+// Address
+#define D0F0xBC_x1F2A8_ADDRESS                                  0x1f2a8
+
+// Type
+#define D0F0xBC_x1F2A8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2A8_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F2A8_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F2A8_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F2A8_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F2A8_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F2A8_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F2A8_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F2A8_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F2A8_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F2A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2A8_STRUCT;
+
+// **** D0F0xBC_x1F2B0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2B0_ADDRESS                                  0x1f2b0
+
+// Type
+#define D0F0xBC_x1F2B0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2B0_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F2B0_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F2B0_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F2B0_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F2B0_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F2B0_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F2B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2B0_STRUCT;
+
+// **** D0F0xBC_x1F2C0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2C0_ADDRESS                                  0x1f2c0
+
+// Type
+#define D0F0xBC_x1F2C0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2C0_StateValid_OFFSET                        0
+#define D0F0xBC_x1F2C0_StateValid_WIDTH                         1
+#define D0F0xBC_x1F2C0_StateValid_MASK                          0x1
+#define D0F0xBC_x1F2C0_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F2C0_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F2C0_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F2C0_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F2C0_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F2C0_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F2C0_VID_OFFSET                               16
+#define D0F0xBC_x1F2C0_VID_WIDTH                                8
+#define D0F0xBC_x1F2C0_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F2C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2C0_STRUCT;
+
+// **** D0F0xBC_x1F2C8 Register Definition ****
+// Address
+#define D0F0xBC_x1F2C8_ADDRESS                                  0x1f2c8
+
+// Type
+#define D0F0xBC_x1F2C8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2C8_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F2C8_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F2C8_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F2C8_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F2C8_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F2C8_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F2C8_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F2C8_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F2C8_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F2C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2C8_STRUCT;
+
+// **** D0F0xBC_x1F2D0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2D0_ADDRESS                                  0x1f2d0
+
+// Type
+#define D0F0xBC_x1F2D0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2D0_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F2D0_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F2D0_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F2D0_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F2D0_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F2D0_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F2D0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2D0_STRUCT;
+
+// **** D0F0xBC_x1F2E0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2E0_ADDRESS                                  0x1f2e0
+
+// Type
+#define D0F0xBC_x1F2E0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2E0_StateValid_OFFSET                        0
+#define D0F0xBC_x1F2E0_StateValid_WIDTH                         1
+#define D0F0xBC_x1F2E0_StateValid_MASK                          0x1
+#define D0F0xBC_x1F2E0_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F2E0_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F2E0_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F2E0_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F2E0_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F2E0_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F2E0_VID_OFFSET                               16
+#define D0F0xBC_x1F2E0_VID_WIDTH                                8
+#define D0F0xBC_x1F2E0_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F2E0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2E0_STRUCT;
+
+// **** D0F0xBC_x1F2E8 Register Definition ****
+// Address
+#define D0F0xBC_x1F2E8_ADDRESS                                  0x1f2e8
+
+// Type
+#define D0F0xBC_x1F2E8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2E8_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F2E8_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F2E8_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F2E8_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F2E8_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F2E8_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F2E8_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F2E8_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F2E8_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F2E8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2E8_STRUCT;
+
+// **** D0F0xBC_x1F2F0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2F0_ADDRESS                                  0x1f2f0
+
+// Type
+#define D0F0xBC_x1F2F0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2F0_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F2F0_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F2F0_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F2F0_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F2F0_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F2F0_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F2F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2F0_STRUCT;
+
+// **** D0F0xBC_x1F300 Register Definition ****
+// Address
+#define D0F0xBC_x1F300_ADDRESS                                  0x1f300
+
+// Type
+#define D0F0xBC_x1F300_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F300_LclkDpmEn_OFFSET                         0
+#define D0F0xBC_x1F300_LclkDpmEn_WIDTH                          1
+#define D0F0xBC_x1F300_LclkDpmEn_MASK                           0x1
+#define D0F0xBC_x1F300_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F300_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F300_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F300_LclkDpmType_OFFSET                       8
+#define D0F0xBC_x1F300_LclkDpmType_WIDTH                        1
+#define D0F0xBC_x1F300_LclkDpmType_MASK                         0x100
+#define D0F0xBC_x1F300_Reserved_15_9_OFFSET                     9
+#define D0F0xBC_x1F300_Reserved_15_9_WIDTH                      7
+#define D0F0xBC_x1F300_Reserved_15_9_MASK                       0xfe00
+#define D0F0xBC_x1F300_LclkDpmBootState_OFFSET                  16
+#define D0F0xBC_x1F300_LclkDpmBootState_WIDTH                   8
+#define D0F0xBC_x1F300_LclkDpmBootState_MASK                    0xff0000
+#define D0F0xBC_x1F300_VoltageChgEn_OFFSET                      24
+#define D0F0xBC_x1F300_VoltageChgEn_WIDTH                       1
+#define D0F0xBC_x1F300_VoltageChgEn_MASK                        0x1000000
+#define D0F0xBC_x1F300_Reserved_31_25_OFFSET                    25
+#define D0F0xBC_x1F300_Reserved_31_25_WIDTH                     7
+#define D0F0xBC_x1F300_Reserved_31_25_MASK                      0xfe000000
+
+/// D0F0xBC_x1F300
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LclkDpmEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDpmType:1 ; ///<
+    UINT32                                            Reserved_15_9:7 ; ///<
+    UINT32                                         LclkDpmBootState:8 ; ///<
+    UINT32                                             VoltageChgEn:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F300_STRUCT;
+
+// **** D0F0xBC_x1F308 Register Definition ****
+// Address
+#define D0F0xBC_x1F308_ADDRESS                                  0x1f308
+
+// Type
+#define D0F0xBC_x1F308_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET           0
+#define D0F0xBC_x1F308_LclkThermalThrottlingEn_WIDTH            1
+#define D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK             0x1
+#define D0F0xBC_x1F308_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F308_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F308_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F308_TemperatureSel_OFFSET                    8
+#define D0F0xBC_x1F308_TemperatureSel_WIDTH                     1
+#define D0F0xBC_x1F308_TemperatureSel_MASK                      0x100
+#define D0F0xBC_x1F308_Reserved_15_9_OFFSET                     9
+#define D0F0xBC_x1F308_Reserved_15_9_WIDTH                      7
+#define D0F0xBC_x1F308_Reserved_15_9_MASK                       0xfe00
+#define D0F0xBC_x1F308_LclkTtMode_OFFSET                        16
+#define D0F0xBC_x1F308_LclkTtMode_WIDTH                         3
+#define D0F0xBC_x1F308_LclkTtMode_MASK                          0x70000
+
+/// D0F0xBC_x1F308
+typedef union {
+  struct {                                                              ///<
+    UINT32                                  LclkThermalThrottlingEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                           TemperatureSel:1 ; ///<
+    UINT32                                            Reserved_15_9:7 ; ///<
+    UINT32                                               LclkTtMode:3 ; ///<
+    UINT32                                           :13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F308_STRUCT;
+
+// **** D0F0xBC_x1F30C Register Definition ****
+// Address
+#define D0F0xBC_x1F30C_ADDRESS                                  0x1f30c
+
+// Type
+#define D0F0xBC_x1F30C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F30C_LowThreshold_OFFSET                      0
+#define D0F0xBC_x1F30C_LowThreshold_WIDTH                       16
+#define D0F0xBC_x1F30C_LowThreshold_MASK                        0xffff
+#define D0F0xBC_x1F30C_HighThreshold_OFFSET                     16
+#define D0F0xBC_x1F30C_HighThreshold_WIDTH                      16
+#define D0F0xBC_x1F30C_HighThreshold_MASK                       0xffff0000
+
+/// D0F0xBC_x1F30C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             LowThreshold:16; ///<
+    UINT32                                            HighThreshold:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F30C_STRUCT;
+
+// **** D0F0xBC_x1F380 Register Definition ****
+// Address
+#define D0F0xBC_x1F380_ADDRESS                                  0x1f380
+
+// Type
+#define D0F0xBC_x1F380_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F380_InterruptsEnabled_OFFSET                 0
+#define D0F0xBC_x1F380_InterruptsEnabled_WIDTH                  1
+#define D0F0xBC_x1F380_InterruptsEnabled_MASK                   0x1
+#define D0F0xBC_x1F380_Reserved_23_1_OFFSET                     1
+#define D0F0xBC_x1F380_Reserved_23_1_WIDTH                      23
+#define D0F0xBC_x1F380_Reserved_23_1_MASK                       0xfffffe
+#define D0F0xBC_x1F380_TestCount_OFFSET                         24
+#define D0F0xBC_x1F380_TestCount_WIDTH                          8
+#define D0F0xBC_x1F380_TestCount_MASK                           0xff000000
+
+/// D0F0xBC_x1F380
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        InterruptsEnabled:1 ; ///<
+    UINT32                                            Reserved_23_1:23; ///<
+    UINT32                                                TestCount:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F380_STRUCT;
+
+// **** D0F0xBC_x1F384 Register Definition ****
+// Address
+#define D0F0xBC_x1F384_ADDRESS                                  0x1f384
+
+// Type
+#define D0F0xBC_x1F384_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F384_FirmwareVid_OFFSET                       0
+#define D0F0xBC_x1F384_FirmwareVid_WIDTH                        8
+#define D0F0xBC_x1F384_FirmwareVid_MASK                         0xff
+#define D0F0xBC_x1F384_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F384_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F384_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F384
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              FirmwareVid:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F384_STRUCT;
+
+// **** D0F0xBC_x1F388 Register Definition ****
+// Address
+#define D0F0xBC_x1F388_ADDRESS                                  0x1f388
+
+// Type
+#define D0F0xBC_x1F388_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F388_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F388_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F388_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F388_TcenId_OFFSET                            6
+#define D0F0xBC_x1F388_TcenId_WIDTH                             4
+#define D0F0xBC_x1F388_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F388_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F388_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F388_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F388
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  CsrAddr:6 ; ///<
+    UINT32                                                   TcenId:4 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F388_STRUCT;
+
+// **** D0F0xBC_x1F39C Register Definition ****
+// Address
+#define D0F0xBC_x1F39C_ADDRESS                                  0x1f39c
+
+// Type
+#define D0F0xBC_x1F39C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F39C_Rx_OFFSET                                0
+#define D0F0xBC_x1F39C_Rx_WIDTH                                 1
+#define D0F0xBC_x1F39C_Rx_MASK                                  0x1
+#define D0F0xBC_x1F39C_Tx_OFFSET                                1
+#define D0F0xBC_x1F39C_Tx_WIDTH                                 1
+#define D0F0xBC_x1F39C_Tx_MASK                                  0x2
+#define D0F0xBC_x1F39C_Core_OFFSET                              2
+#define D0F0xBC_x1F39C_Core_WIDTH                               1
+#define D0F0xBC_x1F39C_Core_MASK                                0x4
+#define D0F0xBC_x1F39C_SkipPhy_OFFSET                           3
+#define D0F0xBC_x1F39C_SkipPhy_WIDTH                            1
+#define D0F0xBC_x1F39C_SkipPhy_MASK                             0x8
+#define D0F0xBC_x1F39C_SkipCore_OFFSET                          4
+#define D0F0xBC_x1F39C_SkipCore_WIDTH                           1
+#define D0F0xBC_x1F39C_SkipCore_MASK                            0x10
+#define D0F0xBC_x1F39C_Reserved_15_5_OFFSET                     5
+#define D0F0xBC_x1F39C_Reserved_15_5_WIDTH                      11
+#define D0F0xBC_x1F39C_Reserved_15_5_MASK                       0xffe0
+#define D0F0xBC_x1F39C_LowerLaneID_OFFSET                       16
+#define D0F0xBC_x1F39C_LowerLaneID_WIDTH                        8
+#define D0F0xBC_x1F39C_LowerLaneID_MASK                         0xff0000
+#define D0F0xBC_x1F39C_UpperLaneID_OFFSET                       24
+#define D0F0xBC_x1F39C_UpperLaneID_WIDTH                        8
+#define D0F0xBC_x1F39C_UpperLaneID_MASK                         0xff000000
+
+/// D0F0xBC_x1F39C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       Rx:1 ; ///<
+    UINT32                                                       Tx:1 ; ///<
+    UINT32                                                     Core:1 ; ///<
+    UINT32                                                  SkipPhy:1 ; ///<
+    UINT32                                                 SkipCore:1 ; ///<
+    UINT32                                            Reserved_15_5:11; ///<
+    UINT32                                              LowerLaneID:8 ; ///<
+    UINT32                                              UpperLaneID:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F39C_STRUCT;
+
+// **** D0F0xBC_x1F3D8 Register Definition ****
+// Address
+#define D0F0xBC_x1F3D8_ADDRESS                                  0x1f3d8
+
+// Type
+#define D0F0xBC_x1F3D8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET                     0
+#define D0F0xBC_x1F3D8_LoadLineTrim3_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim3_MASK                       0xff
+#define D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET                     8
+#define D0F0xBC_x1F3D8_LoadLineTrim2_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim2_MASK                       0xff00
+#define D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET                     16
+#define D0F0xBC_x1F3D8_LoadLineTrim1_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim1_MASK                       0xff0000
+#define D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET                     24
+#define D0F0xBC_x1F3D8_LoadLineTrim0_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim0_MASK                       0xff000000
+
+/// D0F0xBC_x1F3D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LoadLineTrim3:8 ; ///<
+    UINT32                                            LoadLineTrim2:8 ; ///<
+    UINT32                                            LoadLineTrim1:8 ; ///<
+    UINT32                                            LoadLineTrim0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3D8_STRUCT;
+
+// **** D0F0xBC_x1F3DC Register Definition ****
+// Address
+#define D0F0xBC_x1F3DC_ADDRESS                                  0x1f3dc
+
+// Type
+#define D0F0xBC_x1F3DC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET                     0
+#define D0F0xBC_x1F3DC_LoadLineTrim7_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim7_MASK                       0xff
+#define D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET                     8
+#define D0F0xBC_x1F3DC_LoadLineTrim6_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim6_MASK                       0xff00
+#define D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET                     16
+#define D0F0xBC_x1F3DC_LoadLineTrim5_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim5_MASK                       0xff0000
+#define D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET                     24
+#define D0F0xBC_x1F3DC_LoadLineTrim4_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim4_MASK                       0xff000000
+
+/// D0F0xBC_x1F3DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LoadLineTrim7:8 ; ///<
+    UINT32                                            LoadLineTrim6:8 ; ///<
+    UINT32                                            LoadLineTrim5:8 ; ///<
+    UINT32                                            LoadLineTrim4:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3DC_STRUCT;
+
+// **** D0F0xBC_x1F3F8 Register Definition ****
+// Address
+#define D0F0xBC_x1F3F8_ADDRESS                                  0x1f3f8
+
+// Type
+#define D0F0xBC_x1F3F8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET                0
+#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH                 8
+#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_MASK                  0xff
+#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET              8
+#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH               8
+#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_MASK                0xff00
+#define D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET                   16
+#define D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH                    8
+#define D0F0xBC_x1F3F8_SviTrimValueVdd_MASK                     0xff0000
+#define D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET                 24
+#define D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH                  8
+#define D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK                   0xff000000
+
+/// D0F0xBC_x1F3F8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       SviInitLoadLineVdd:8 ; ///<
+    UINT32                                     SviInitLoadLineVddNB:8 ; ///<
+    UINT32                                          SviTrimValueVdd:8 ; ///<
+    UINT32                                        SviTrimValueVddNB:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3F8_STRUCT;
+
+// **** D0F0xBC_x1F3FC Register Definition ****
+// Address
+#define D0F0xBC_x1F3FC_ADDRESS                                  0x1f3fc
+
+// Type
+#define D0F0xBC_x1F3FC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3FC_SviVidStepBase_OFFSET                    0
+#define D0F0xBC_x1F3FC_SviVidStepBase_WIDTH                     16
+#define D0F0xBC_x1F3FC_SviVidStepBase_MASK                      0xffff
+#define D0F0xBC_x1F3FC_SviVidStep_OFFSET                        16
+#define D0F0xBC_x1F3FC_SviVidStep_WIDTH                         16
+#define D0F0xBC_x1F3FC_SviVidStep_MASK                          0xffff0000
+
+/// D0F0xBC_x1F3FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SviVidStepBase:16; ///<
+    UINT32                                               SviVidStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3FC_STRUCT;
+
+// **** D0F0xBC_x1F400 Register Definition ****
+// Address
+#define D0F0xBC_x1F400_ADDRESS                                  0x1f400
+
+// Type
+#define D0F0xBC_x1F400_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET              0
+#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH               8
+#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK                0xff
+#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET            8
+#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH             8
+#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK              0xff00
+#define D0F0xBC_x1F400_PstateMax_OFFSET                         16
+#define D0F0xBC_x1F400_PstateMax_WIDTH                          8
+#define D0F0xBC_x1F400_PstateMax_MASK                           0xff0000
+#define D0F0xBC_x1F400_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F400_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F400_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F400
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     SviLoadLineOffsetVdd:8 ; ///<
+    UINT32                                   SviLoadLineOffsetVddNB:8 ; ///<
+    UINT32                                                PstateMax:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F400_STRUCT;
+
+// **** D0F0xBC_x1F404 Register Definition ****
+// Address
+#define D0F0xBC_x1F404_ADDRESS                                  0x1f404
+
+// Type
+#define D0F0xBC_x1F404_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F404_LoadLineOffset3_OFFSET                   0
+#define D0F0xBC_x1F404_LoadLineOffset3_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset3_MASK                     0xff
+#define D0F0xBC_x1F404_LoadLineOffset2_OFFSET                   8
+#define D0F0xBC_x1F404_LoadLineOffset2_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset2_MASK                     0xff00
+#define D0F0xBC_x1F404_LoadLineOffset1_OFFSET                   16
+#define D0F0xBC_x1F404_LoadLineOffset1_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset1_MASK                     0xff0000
+#define D0F0xBC_x1F404_LoadLineOffset0_OFFSET                   24
+#define D0F0xBC_x1F404_LoadLineOffset0_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset0_MASK                     0xff000000
+
+/// D0F0xBC_x1F404
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          LoadLineOffset3:8 ; ///<
+    UINT32                                          LoadLineOffset2:8 ; ///<
+    UINT32                                          LoadLineOffset1:8 ; ///<
+    UINT32                                          LoadLineOffset0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F404_STRUCT;
+
+// **** D0F0xBC_x1F428 Register Definition ****
+// Address
+#define D0F0xBC_x1F428_ADDRESS                                  0x1f428
+
+// Type
+#define D0F0xBC_x1F428_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET             0
+#define D0F0xBC_x1F428_EnableVpcAccumulators_WIDTH              1
+#define D0F0xBC_x1F428_EnableVpcAccumulators_MASK               0x1
+#define D0F0xBC_x1F428_EnableBapm_OFFSET                        1
+#define D0F0xBC_x1F428_EnableBapm_WIDTH                         1
+#define D0F0xBC_x1F428_EnableBapm_MASK                          0x2
+#define D0F0xBC_x1F428_EnableTdcLimit_OFFSET                    2
+#define D0F0xBC_x1F428_EnableTdcLimit_WIDTH                     1
+#define D0F0xBC_x1F428_EnableTdcLimit_MASK                      0x4
+#define D0F0xBC_x1F428_EnableLpmx_OFFSET                        3
+#define D0F0xBC_x1F428_EnableLpmx_WIDTH                         1
+#define D0F0xBC_x1F428_EnableLpmx_MASK                          0x8
+#define D0F0xBC_x1F428_EnableHtcLimit_OFFSET                    4
+#define D0F0xBC_x1F428_EnableHtcLimit_WIDTH                     1
+#define D0F0xBC_x1F428_EnableHtcLimit_MASK                      0x10
+#define D0F0xBC_x1F428_EnableNbDpm_OFFSET                       5
+#define D0F0xBC_x1F428_EnableNbDpm_WIDTH                        1
+#define D0F0xBC_x1F428_EnableNbDpm_MASK                         0x20
+#define D0F0xBC_x1F428_EnableLoadline_OFFSET                    6
+#define D0F0xBC_x1F428_EnableLoadline_WIDTH                     1
+#define D0F0xBC_x1F428_EnableLoadline_MASK                      0x40
+#define D0F0xBC_x1F428_Reserved_15_7_OFFSET                     7
+#define D0F0xBC_x1F428_Reserved_15_7_WIDTH                      9
+#define D0F0xBC_x1F428_Reserved_15_7_MASK                       0xff80
+#define D0F0xBC_x1F428_Reserved_23_20_OFFSET                    20
+#define D0F0xBC_x1F428_Reserved_23_20_WIDTH                     4
+#define D0F0xBC_x1F428_Reserved_23_20_MASK                      0xf00000
+#define D0F0xBC_x1F428_PstateAllCpusIdle_OFFSET                 24
+#define D0F0xBC_x1F428_PstateAllCpusIdle_WIDTH                  3
+#define D0F0xBC_x1F428_PstateAllCpusIdle_MASK                   0x7000000
+#define D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET               27
+#define D0F0xBC_x1F428_NbPstateAllCpusIdle_WIDTH                1
+#define D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK                 0x8000000
+#define D0F0xBC_x1F428_BapmCoeffOverride_OFFSET                 28
+#define D0F0xBC_x1F428_BapmCoeffOverride_WIDTH                  1
+#define D0F0xBC_x1F428_BapmCoeffOverride_MASK                   0x10000000
+#define D0F0xBC_x1F428_SviMode_OFFSET                           29
+#define D0F0xBC_x1F428_SviMode_WIDTH                            1
+#define D0F0xBC_x1F428_SviMode_MASK                             0x20000000
+#define D0F0xBC_x1F428_Reserved_31_30_OFFSET                    30
+#define D0F0xBC_x1F428_Reserved_31_30_WIDTH                     2
+#define D0F0xBC_x1F428_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F0xBC_x1F428
+typedef union {
+  struct {                                                              ///<
+    UINT32                                    EnableVpcAccumulators:1 ; ///<
+    UINT32                                               EnableBapm:1 ; ///<
+    UINT32                                           EnableTdcLimit:1 ; ///<
+    UINT32                                               EnableLpmx:1 ; ///<
+    UINT32               field_4:1;
+    UINT32                                              EnableNbDpm:1 ; ///<
+    UINT32                                           EnableLoadline:1 ; ///<
+    UINT32                                            Reserved_15_7:9 ; ///<
+    UINT32                                       :1 ; ///<
+    UINT32                                                  :1 ; ///<
+    UINT32                                                 :1 ; ///<
+    UINT32                                 line180        :1 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                        PstateAllCpusIdle:3 ; ///<
+    UINT32                                      NbPstateAllCpusIdle:1 ; ///<
+    UINT32                                        BapmCoeffOverride:1 ; ///<
+    UINT32                                                  SviMode:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F428_STRUCT;
+
+// **** D0F0xBC_x1F460 Register Definition ****
+// Address
+#define D0F0xBC_x1F460_ADDRESS                                  0x1f460
+
+// Type
+#define D0F0xBC_x1F460_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F460_LclkDpm_OFFSET                           0
+#define D0F0xBC_x1F460_LclkDpm_WIDTH                            8
+#define D0F0xBC_x1F460_LclkDpm_MASK                             0xff
+#define D0F0xBC_x1F460_ThermalCntl_OFFSET                       8
+#define D0F0xBC_x1F460_ThermalCntl_WIDTH                        8
+#define D0F0xBC_x1F460_ThermalCntl_MASK                         0xff00
+#define D0F0xBC_x1F460_VoltageCntl_OFFSET                       16
+#define D0F0xBC_x1F460_VoltageCntl_WIDTH                        8
+#define D0F0xBC_x1F460_VoltageCntl_MASK                         0xff0000
+#define D0F0xBC_x1F460_Loadline_OFFSET                          24
+#define D0F0xBC_x1F460_Loadline_WIDTH                           8
+#define D0F0xBC_x1F460_Loadline_MASK                            0xff000000
+
+/// D0F0xBC_x1F460
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  LclkDpm:8 ; ///<
+    UINT32                                              ThermalCntl:8 ; ///<
+    UINT32                                              VoltageCntl:8 ; ///<
+    UINT32                                                 Loadline:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F460_STRUCT;
+
+// **** D0F0xBC_x1F464 Register Definition ****
+// Address
+#define D0F0xBC_x1F464_ADDRESS                                  0x1f464
+
+// Type
+#define D0F0xBC_x1F464_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F464_SclkDpm_OFFSET                           0
+#define D0F0xBC_x1F464_SclkDpm_WIDTH                            8
+#define D0F0xBC_x1F464_SclkDpm_MASK                             0xff
+#define D0F0xBC_x1F464_StaticSimdPgCntl_OFFSET                  8
+#define D0F0xBC_x1F464_StaticSimdPgCntl_WIDTH                   8
+#define D0F0xBC_x1F464_StaticSimdPgCntl_MASK                    0xff00
+#define D0F0xBC_x1F464_DynSimdPgCntl_OFFSET                     16
+#define D0F0xBC_x1F464_DynSimdPgCntl_WIDTH                      8
+#define D0F0xBC_x1F464_DynSimdPgCntl_MASK                       0xff0000
+#define D0F0xBC_x1F464_TdpCntl_OFFSET                           24
+#define D0F0xBC_x1F464_TdpCntl_WIDTH                            8
+#define D0F0xBC_x1F464_TdpCntl_MASK                             0xff000000
+
+/// D0F0xBC_x1F464
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  SclkDpm:8 ; ///<
+    UINT32                                         StaticSimdPgCntl:8 ; ///<
+    UINT32                                            DynSimdPgCntl:8 ; ///<
+    UINT32                                                  TdpCntl:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F464_STRUCT;
+
+// **** D0F0xBC_x1F468 Register Definition ****
+// Address
+#define D0F0xBC_x1F468_ADDRESS                                  0x1f468
+
+// Type
+#define D0F0xBC_x1F468_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F468_TimerPeriod_OFFSET                       0
+#define D0F0xBC_x1F468_TimerPeriod_WIDTH                        32
+#define D0F0xBC_x1F468_TimerPeriod_MASK                         0xffffffff
+
+/// D0F0xBC_x1F468
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              TimerPeriod:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F468_STRUCT;
+
+// **** D0F0xBC_x1F46C Register Definition ****
+// Address
+#define D0F0xBC_x1F46C_ADDRESS                                  0x1f46c
+
+// Type
+#define D0F0xBC_x1F46C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F46C_VpcPeriod_OFFSET                         0
+#define D0F0xBC_x1F46C_VpcPeriod_WIDTH                          16
+#define D0F0xBC_x1F46C_VpcPeriod_MASK                           0xffff
+#define D0F0xBC_x1F46C_BapmPeriod_OFFSET                        16
+#define D0F0xBC_x1F46C_BapmPeriod_WIDTH                         8
+#define D0F0xBC_x1F46C_BapmPeriod_MASK                          0xff0000
+#define D0F0xBC_x1F46C_LpmxPeriod_OFFSET                        24
+#define D0F0xBC_x1F46C_LpmxPeriod_WIDTH                         8
+#define D0F0xBC_x1F46C_LpmxPeriod_MASK                          0xff000000
+
+/// D0F0xBC_x1F46C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                VpcPeriod:16; ///<
+    UINT32                                               BapmPeriod:8 ; ///<
+    UINT32                                               LpmxPeriod:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F46C_STRUCT;
+
+// **** D0F0xBC_x1F5F8 Register Definition ****
+// Address
+#define D0F0xBC_x1F5F8_ADDRESS                                  0x1f5f8
+
+// Type
+#define D0F0xBC_x1F5F8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET                      0
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH                       2
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_MASK                        0x3
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET                      2
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH                       2
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_MASK                        0xc
+#define D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET                        4
+#define D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH                         2
+#define D0F0xBC_x1F5F8_DpmXNbPsLo_MASK                          0x30
+#define D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET                        6
+#define D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH                         2
+#define D0F0xBC_x1F5F8_DpmXNbPsHi_MASK                          0xc0
+#define D0F0xBC_x1F5F8_Hysteresis_OFFSET                        8
+#define D0F0xBC_x1F5F8_Hysteresis_WIDTH                         8
+#define D0F0xBC_x1F5F8_Hysteresis_MASK                          0xff00
+#define D0F0xBC_x1F5F8_SkipPG_OFFSET                            16
+#define D0F0xBC_x1F5F8_SkipPG_WIDTH                             1
+#define D0F0xBC_x1F5F8_SkipPG_MASK                              0x10000
+#define D0F0xBC_x1F5F8_SkipDPM0_OFFSET                          17
+#define D0F0xBC_x1F5F8_SkipDPM0_WIDTH                           1
+#define D0F0xBC_x1F5F8_SkipDPM0_MASK                            0x20000
+#define D0F0xBC_x1F5F8_Reserved_21_18_OFFSET                    18
+#define D0F0xBC_x1F5F8_Reserved_21_18_WIDTH                     4
+#define D0F0xBC_x1F5F8_Reserved_21_18_MASK                      0x3c0000
+#define D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET                      22
+#define D0F0xBC_x1F5F8_EnableNbPsi1_WIDTH                       1
+#define D0F0xBC_x1F5F8_EnableNbPsi1_MASK                        0x400000
+#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET               23
+#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_WIDTH                1
+#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK                 0x800000
+#define D0F0xBC_x1F5F8_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F5F8_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F5F8_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F5F8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Dpm0PgNbPsLo:2 ; ///<
+    UINT32                                             Dpm0PgNbPsHi:2 ; ///<
+    UINT32                                               DpmXNbPsLo:2 ; ///<
+    UINT32                                               DpmXNbPsHi:2 ; ///<
+    UINT32                                               Hysteresis:8 ; ///<
+    UINT32                                                   SkipPG:1 ; ///<
+    UINT32                                                 SkipDPM0:1 ; ///<
+    UINT32                                           Reserved_21_18:4 ; ///<
+    UINT32                                             EnableNbPsi1:1 ; ///<
+    UINT32                                      EnableDpmPstatePoll:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F5F8_STRUCT;
+
+// **** D0F0xBC_x1F5FC Register Definition ****
+// Address
+#define D0F0xBC_x1F5FC_ADDRESS                                  0x1f5fc
+
+// Type
+#define D0F0xBC_x1F5FC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F5FC_ChangeInProgress_OFFSET                  0
+#define D0F0xBC_x1F5FC_ChangeInProgress_WIDTH                   1
+#define D0F0xBC_x1F5FC_ChangeInProgress_MASK                    0x1
+#define D0F0xBC_x1F5FC_CurrentPstatePair_OFFSET                 1
+#define D0F0xBC_x1F5FC_CurrentPstatePair_WIDTH                  1
+#define D0F0xBC_x1F5FC_CurrentPstatePair_MASK                   0x2
+#define D0F0xBC_x1F5FC_Reserved_7_2_OFFSET                      2
+#define D0F0xBC_x1F5FC_Reserved_7_2_WIDTH                       6
+#define D0F0xBC_x1F5FC_Reserved_7_2_MASK                        0xfc
+#define D0F0xBC_x1F5FC_PSI1Sts_OFFSET                           8
+#define D0F0xBC_x1F5FC_PSI1Sts_WIDTH                            1
+#define D0F0xBC_x1F5FC_PSI1Sts_MASK                             0x100
+#define D0F0xBC_x1F5FC_Reserved_31_9_OFFSET                     9
+#define D0F0xBC_x1F5FC_Reserved_31_9_WIDTH                      23
+#define D0F0xBC_x1F5FC_Reserved_31_9_MASK                       0xfffffe00
+
+/// D0F0xBC_x1F5FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         ChangeInProgress:1 ; ///<
+    UINT32                                        CurrentPstatePair:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                                  PSI1Sts:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F5FC_STRUCT;
+
+// **** D0F0xBC_x1F610 Register Definition ****
+// Address
+#define D0F0xBC_x1F610_ADDRESS                                  0x1f610
+
+// Type
+#define D0F0xBC_x1F610_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F610_RESERVED_OFFSET                          0
+#define D0F0xBC_x1F610_RESERVED_WIDTH                           8
+#define D0F0xBC_x1F610_RESERVED_MASK                            0xff
+#define D0F0xBC_x1F610_GFXH_OFFSET                              8
+#define D0F0xBC_x1F610_GFXH_WIDTH                               8
+#define D0F0xBC_x1F610_GFXH_MASK                                0xff00
+#define D0F0xBC_x1F610_GFXL_OFFSET                              16
+#define D0F0xBC_x1F610_GFXL_WIDTH                               8
+#define D0F0xBC_x1F610_GFXL_MASK                                0xff0000
+#define D0F0xBC_x1F610_GPPSB_OFFSET                             24
+#define D0F0xBC_x1F610_GPPSB_WIDTH                              8
+#define D0F0xBC_x1F610_GPPSB_MASK                               0xff000000
+
+/// D0F0xBC_x1F610
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 RESERVED:8 ; ///<
+    UINT32                                                     GFXH:8 ; ///<
+    UINT32                                                     GFXL:8 ; ///<
+    UINT32                                                    GPPSB:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F610_STRUCT;
+
+
+// **** D0F0xBC_x1F628 Register Definition ****
+// Address
+#define D0F0xBC_x1F628_ADDRESS                                  0x1f628
+
+// Type
+#define D0F0xBC_x1F628_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F628_Reserved_15_0_OFFSET                     0
+#define D0F0xBC_x1F628_Reserved_15_0_WIDTH                      16
+#define D0F0xBC_x1F628_Reserved_15_0_MASK                       0xffff
+#define D0F0xBC_x1F628_HtcActivePstateLimit_OFFSET              16
+#define D0F0xBC_x1F628_HtcActivePstateLimit_WIDTH               8
+#define D0F0xBC_x1F628_HtcActivePstateLimit_MASK                0xff0000
+#define D0F0xBC_x1F628_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F628_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F628_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F628
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_15_0:16;///<
+    UINT32                                      HtcActivePstateLimit:8; ///<
+    UINT32                                            Reserved_31_24:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F628_STRUCT;
+
+// **** D0F0xBC_x1F62C Register Definition ****
+// Address
+#define D0F0xBC_x1F62C_ADDRESS                                  0x1f62c
+
+// Type
+#define D0F0xBC_x1F62C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F62C_Idd_OFFSET                               0
+#define D0F0xBC_x1F62C_Idd_WIDTH                                16
+#define D0F0xBC_x1F62C_Idd_MASK                                 0xffff
+#define D0F0xBC_x1F62C_Iddnb_OFFSET                             16
+#define D0F0xBC_x1F62C_Iddnb_WIDTH                              16
+#define D0F0xBC_x1F62C_Iddnb_MASK                               0xffff0000
+
+/// D0F0xBC_x1F62C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Idd:16; ///<
+    UINT32                                                    Iddnb:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F62C_STRUCT;
+
+// **** D0F0xBC_x1F638 Register Definition ****
+// Address
+#define D0F0xBC_x1F638_ADDRESS                                  0x1f638
+
+// Type
+#define D0F0xBC_x1F638_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F638_TdcPeriod_OFFSET                         0
+#define D0F0xBC_x1F638_TdcPeriod_WIDTH                          8
+#define D0F0xBC_x1F638_TdcPeriod_MASK                           0xff
+#define D0F0xBC_x1F638_HtcPeriod_OFFSET                         8
+#define D0F0xBC_x1F638_HtcPeriod_WIDTH                          8
+#define D0F0xBC_x1F638_HtcPeriod_MASK                           0xff00
+#define D0F0xBC_x1F638_NbdpmPeriod_OFFSET                       16
+#define D0F0xBC_x1F638_NbdpmPeriod_WIDTH                        8
+#define D0F0xBC_x1F638_NbdpmPeriod_MASK                         0xff0000
+#define D0F0xBC_x1F638_PginterlockPeriod_OFFSET                 24
+#define D0F0xBC_x1F638_PginterlockPeriod_WIDTH                  8
+#define D0F0xBC_x1F638_PginterlockPeriod_MASK                   0xff000000
+
+/// D0F0xBC_x1F638
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                TdcPeriod:8 ; ///<
+    UINT32                                                HtcPeriod:8 ; ///<
+    UINT32                                              NbdpmPeriod:8 ; ///<
+    UINT32                                        PginterlockPeriod:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F638_STRUCT;
+
+// **** D0F0xBC_x1F6E4 Register Definition ****
+// Address
+#define D0F0xBC_x1F6E4_ADDRESS                                  0x1f6e4
+
+// Type
+#define D0F0xBC_x1F6E4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET                      0
+#define D0F0xBC_x1F6E4_DdrVoltFloor_WIDTH                       8
+#define D0F0xBC_x1F6E4_DdrVoltFloor_MASK                        0xff
+#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET                  8
+#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_WIDTH                   8
+#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK                    0xff00
+#define D0F0xBC_x1F6E4_Reserved_OFFSET                          16
+#define D0F0xBC_x1F6E4_Reserved_WIDTH                           16
+#define D0F0xBC_x1F6E4_Reserved_MASK                            0xffff0000
+
+/// D0F0xBC_x1F6E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DdrVoltFloor:8 ; ///<
+    UINT32                                         BapmDdrVoltFloor:8 ; ///<
+    UINT32                                                 Reserved:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F6E4_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32          ex996_0:8 ;
+    UINT32          ex996_1:8 ;
+    UINT32          ex996_2:8 ;
+    UINT32          ex996_3:8 ;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex996_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32           ex997_0:16;
+    UINT32           ex997_1:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex997_STRUCT;
+
+// **** D0F0xBC_x1F6B4 Register Definition ****
+// Address
+#define D0F0xBC_x1F6B4_ADDRESS                                  0x1f6b4
+
+// Type
+#define D0F0xBC_x1F6B4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F6B4_TjOffset_OFFSET                          0
+#define D0F0xBC_x1F6B4_TjOffset_WIDTH                           8
+#define D0F0xBC_x1F6B4_TjOffset_MASK                            0xff
+#define D0F0xBC_x1F6B4_Reserved_OFFSET                          8
+#define D0F0xBC_x1F6B4_Reserved_WIDTH                           24
+#define D0F0xBC_x1F6B4_Reserved_MASK                            0xffffff00
+
+/// D0F0xBC_x1F6B4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 TjOffset:8 ; ///<
+    UINT32                                                 Reserved:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F6B4_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32           ex998_0:16;
+    UINT32           ex998_1:8;
+    UINT32           ex998_2:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex998_STRUCT;
+
+// **** D0F0xBC_x1F844 Register Definition ****
+// Address
+#define D0F0xBC_x1F844_ADDRESS                                  0x1f844
+
+// Type
+#define D0F0xBC_x1F844_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F844_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F844_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F844_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F844_TcenId_OFFSET                            6
+#define D0F0xBC_x1F844_TcenId_WIDTH                             4
+#define D0F0xBC_x1F844_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F844_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F844_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F844_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F844
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CsrAddr:6; ///<
+    UINT32                                                    TcenId:4; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F844_STRUCT;
+
+// **** D0F0xBC_x1F848 Register Definition ****
+// Address
+#define D0F0xBC_x1F848_ADDRESS                                  0x1f848
+
+// Type
+#define D0F0xBC_x1F848_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F848_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F848_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F848_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F848_TcenId_OFFSET                            6
+#define D0F0xBC_x1F848_TcenId_WIDTH                             4
+#define D0F0xBC_x1F848_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F848_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F848_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F848_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F848
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CsrAddr:6; ///<
+    UINT32                                                    TcenId:4; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F848_STRUCT;
+
+// **** D0F0xBC_x1F84C Register Definition ****
+// Address
+#define D0F0xBC_x1F84C_ADDRESS                                  0x1f84c
+
+// Type
+#define D0F0xBC_x1F84C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F84C_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F84C_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F84C_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F84C_TcenId_OFFSET                            6
+#define D0F0xBC_x1F84C_TcenId_WIDTH                             4
+#define D0F0xBC_x1F84C_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F84C_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F84C_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F84C_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F84C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CsrAddr:6; ///<
+    UINT32                                                    TcenId:4; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F84C_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32           ex999_0:8;
+    UINT32           ex999_1:8;
+    UINT32           ex999_2:8;
+    UINT32           ex999_3:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex999_STRUCT;
+
+// **** D0F0xBC_x1F870 Register Definition ****
+// Address
+#define D0F0xBC_x1F870_ADDRESS                                  0x1f870
+
+// Type
+#define D0F0xBC_x1F870_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F870_AmbientTempBase_OFFSET                   0
+#define D0F0xBC_x1F870_AmbientTempBase_WIDTH                    8
+#define D0F0xBC_x1F870_AmbientTempBase_MASK                     0xff
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_OFFSET                 8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_WIDTH                  8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_MASK                   0xff00
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_OFFSET                 16
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_WIDTH                  8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_MASK                   0xff0000
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_OFFSET                 24
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_WIDTH                  8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_MASK                   0xff000000
+
+/// D0F0xBC_x1F870
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           AmbientTempBase:8; ///<
+    UINT32                                          BAPMTI_TjOffset_2:8; ///<
+    UINT32                                          BAPMTI_TjOffset_1:8; ///<
+    UINT32                                          BAPMTI_TjOffset_0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F870_STRUCT;
+
+/// D0F0xBC_x1F878
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                FUSE_DATA:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F878_STRUCT;
+
+// **** D0F0xBC_x1F87C Register Definition ****
+// Address
+#define D0F0xBC_x1F87C_ADDRESS                                  0x1f87c
+
+// Type
+#define D0F0xBC_x1F87C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_OFFSET                  0
+#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_WIDTH                   16
+#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK                    0xffff
+#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_OFFSET              16
+#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_WIDTH               16
+#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK                0xffff0000
+
+/// D0F0xBC_x1F87C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         LL_PCIE_LoadStep:16; ///<
+    UINT32                                     LL_VddNbLoadStepBase:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F87C_STRUCT;
+
+// **** D0F0xBC_x1F880 Register Definition ****
+// Address
+#define D0F0xBC_x1F880_ADDRESS                                  0x1f880
+
+// Type
+#define D0F0xBC_x1F880_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F880_LL_VCE_LoadStep_OFFSET                   0
+#define D0F0xBC_x1F880_LL_VCE_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F880_LL_VCE_LoadStep_MASK                     0xffff
+#define D0F0xBC_x1F880_LL_UVD_LoadStep_OFFSET                   16
+#define D0F0xBC_x1F880_LL_UVD_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F880_LL_UVD_LoadStep_MASK                     0xffff0000
+
+/// D0F0xBC_x1F880
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          LL_VCE_LoadStep:16; ///<
+    UINT32                                          LL_UVD_LoadStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F880_STRUCT;
+
+// **** D0F0xBC_x1F884 Register Definition ****
+// Address
+#define D0F0xBC_x1F884_ADDRESS                                  0x1f884
+
+// Type
+#define D0F0xBC_x1F884_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F884_LL_DCE2_LoadStep_OFFSET                  0
+#define D0F0xBC_x1F884_LL_DCE2_LoadStep_WIDTH                   16
+#define D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK                    0xffff
+#define D0F0xBC_x1F884_LL_DCE_LoadStep_OFFSET                   16
+#define D0F0xBC_x1F884_LL_DCE_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F884_LL_DCE_LoadStep_MASK                     0xffff0000
+
+/// D0F0xBC_x1F884
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         LL_DCE2_LoadStep:16; ///<
+    UINT32                                          LL_DCE_LoadStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F884_STRUCT;
+
+// **** D0F0xBC_x1F888 Register Definition ****
+// Address
+#define D0F0xBC_x1F888_ADDRESS                                  0x1f888
+
+// Type
+#define D0F0xBC_x1F888_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F888_VddNbTdp_OFFSET                          0
+#define D0F0xBC_x1F888_VddNbTdp_WIDTH                           16
+#define D0F0xBC_x1F888_VddNbTdp_MASK                            0xffff
+#define D0F0xBC_x1F888_LL_GPU_LoadStep_OFFSET                   16
+#define D0F0xBC_x1F888_LL_GPU_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F888_LL_GPU_LoadStep_MASK                     0xffff0000
+
+/// D0F0xBC_x1F888
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VddNbTdp:16; ///<
+    UINT32                                          LL_GPU_LoadStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F888_STRUCT;
+
+// **** D0F0xBC_x1F88C Register Definition ****
+// Address
+#define D0F0xBC_x1F88C_ADDRESS                                  0x1f88c
+
+// Type
+#define D0F0xBC_x1F88C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F88C_NbVid_3_OFFSET                           0
+#define D0F0xBC_x1F88C_NbVid_3_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_3_MASK                             0xff
+#define D0F0xBC_x1F88C_NbVid_2_OFFSET                           8
+#define D0F0xBC_x1F88C_NbVid_2_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_2_MASK                             0xff00
+#define D0F0xBC_x1F88C_NbVid_1_OFFSET                           16
+#define D0F0xBC_x1F88C_NbVid_1_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_1_MASK                             0xff0000
+#define D0F0xBC_x1F88C_NbVid_0_OFFSET                           24
+#define D0F0xBC_x1F88C_NbVid_0_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_0_MASK                             0xff000000
+
+/// D0F0xBC_x1F88C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  NbVid_3:8 ; ///<
+    UINT32                                                  NbVid_2:8 ; ///<
+    UINT32                                                  NbVid_1:8 ; ///<
+    UINT32                                                  NbVid_0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F88C_STRUCT;
+
+// **** D0F0xBC_x1F890 Register Definition ****
+// Address
+#define D0F0xBC_x1F890_ADDRESS                                  0x1f890
+
+// Type
+#define D0F0xBC_x1F890_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F890_CpuVid_3_OFFSET                           0
+#define D0F0xBC_x1F890_CpuVid_3_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_3_MASK                             0xff
+#define D0F0xBC_x1F890_CpuVid_2_OFFSET                           8
+#define D0F0xBC_x1F890_CpuVid_2_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_2_MASK                             0xff00
+#define D0F0xBC_x1F890_CpuVid_1_OFFSET                           16
+#define D0F0xBC_x1F890_CpuVid_1_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_1_MASK                             0xff0000
+#define D0F0xBC_x1F890_CpuVid_0_OFFSET                           24
+#define D0F0xBC_x1F890_CpuVid_0_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_0_MASK                             0xff000000
+
+/// D0F0xBC_x1F890
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CpuVid_3:8 ; ///<
+    UINT32                                                 CpuVid_2:8 ; ///<
+    UINT32                                                 CpuVid_1:8 ; ///<
+    UINT32                                                 CpuVid_0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F890_STRUCT;
+
+// **** D0F0xBC_x1F894 Register Definition ****
+// Address
+#define D0F0xBC_x1F894_ADDRESS                                  0x1f894
+
+// Type
+#define D0F0xBC_x1F894_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F894_CpuVid_7_OFFSET                           0
+#define D0F0xBC_x1F894_CpuVid_7_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_7_MASK                             0xff
+#define D0F0xBC_x1F894_CpuVid_6_OFFSET                           8
+#define D0F0xBC_x1F894_CpuVid_6_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_6_MASK                             0xff00
+#define D0F0xBC_x1F894_CpuVid_5_OFFSET                           16
+#define D0F0xBC_x1F894_CpuVid_5_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_5_MASK                             0xff0000
+#define D0F0xBC_x1F894_CpuVid_4_OFFSET                           24
+#define D0F0xBC_x1F894_CpuVid_4_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_4_MASK                             0xff000000
+
+/// D0F0xBC_x1F894
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CpuVid_7:8 ; ///<
+    UINT32                                                 CpuVid_6:8 ; ///<
+    UINT32                                                 CpuVid_5:8 ; ///<
+    UINT32                                                 CpuVid_4:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F894_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1000_0:16;
+    UINT32            ex1000_1:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1000_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1001_0:16;
+    UINT32            ex1001_1:8;
+    UINT32            ex1001_2:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1001_STRUCT;
+
+// **** D0F0xBC_x1F8D4 Register Definition ****
+// Address
+#define D0F0xBC_x1F8D4_ADDRESS                                  0x1f8d4
+
+// Type
+#define D0F0xBC_x1F8D4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8D4_BapmPstateVid_3_OFFSET                   0
+#define D0F0xBC_x1F8D4_BapmPstateVid_3_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_3_MASK                     0xff
+#define D0F0xBC_x1F8D4_BapmPstateVid_2_OFFSET                   8
+#define D0F0xBC_x1F8D4_BapmPstateVid_2_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_2_MASK                     0xff00
+#define D0F0xBC_x1F8D4_BapmPstateVid_1_OFFSET                   16
+#define D0F0xBC_x1F8D4_BapmPstateVid_1_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_1_MASK                     0xff0000
+#define D0F0xBC_x1F8D4_BapmPstateVid_0_OFFSET                   24
+#define D0F0xBC_x1F8D4_BapmPstateVid_0_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_0_MASK                     0xff000000
+
+/// D0F0xBC_x1F8D4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           BapmPstateVid_3:8; ///<
+    UINT32                                           BapmPstateVid_2:8; ///<
+    UINT32                                           BapmPstateVid_1:8; ///<
+    UINT32                                           BapmPstateVid_0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8D4_STRUCT;
+
+// **** D0F0xBC_x1F8D4 Register Definition ****
+// Address
+#define D0F0xBC_x1F8D8_ADDRESS                                  0x1f8d8
+
+// Type
+#define D0F0xBC_x1F8D8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8D8_BapmPstateVid_7_OFFSET                   0
+#define D0F0xBC_x1F8D8_BapmPstateVid_7_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_7_MASK                     0xff
+#define D0F0xBC_x1F8D8_BapmPstateVid_6_OFFSET                   8
+#define D0F0xBC_x1F8D8_BapmPstateVid_6_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_6_MASK                     0xff00
+#define D0F0xBC_x1F8D8_BapmPstateVid_5_OFFSET                   16
+#define D0F0xBC_x1F8D8_BapmPstateVid_5_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_5_MASK                     0xff0000
+#define D0F0xBC_x1F8D8_BapmPstateVid_4_OFFSET                   24
+#define D0F0xBC_x1F8D8_BapmPstateVid_4_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_4_MASK                     0xff000000
+
+/// D0F0xBC_x1F8D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           BapmPstateVid_7:8; ///<
+    UINT32                                           BapmPstateVid_6:8; ///<
+    UINT32                                           BapmPstateVid_5:8; ///<
+    UINT32                                           BapmPstateVid_4:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8D8_STRUCT;
+
+// **** D0F0xBC_x1F8DC Register Definition ****
+// Address
+#define D0F0xBC_x1F8DC_ADDRESS                                  0x1f8dc
+
+// Type
+#define D0F0xBC_x1F8DC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8DC_SClkVid3_OFFSET                          0
+#define D0F0xBC_x1F8DC_SClkVid3_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid3_MASK                            0xff
+#define D0F0xBC_x1F8DC_SClkVid2_OFFSET                          8
+#define D0F0xBC_x1F8DC_SClkVid2_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid2_MASK                            0xff00
+#define D0F0xBC_x1F8DC_SClkVid1_OFFSET                          16
+#define D0F0xBC_x1F8DC_SClkVid1_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid1_MASK                            0xff0000
+#define D0F0xBC_x1F8DC_SClkVid0_OFFSET                          24
+#define D0F0xBC_x1F8DC_SClkVid0_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid0_MASK                            0xff000000
+
+/// D0F0xBC_x1F8DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  SClkVid3:8; ///<
+    UINT32                                                  SClkVid2:8; ///<
+    UINT32                                                  SClkVid1:8; ///<
+    UINT32                                                  SClkVid0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8DC_STRUCT;
+
+// **** D0F0xBC_x1F8E0 Register Definition ****
+// Address
+#define D0F0xBC_x1F8E0_ADDRESS                                  0x1f8e0
+
+// Type
+#define D0F0xBC_x1F8E0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8E0_BapmSclkVid_2_OFFSET                     0
+#define D0F0xBC_x1F8E0_BapmSclkVid_2_WIDTH                      8
+#define D0F0xBC_x1F8E0_BapmSclkVid_2_MASK                       0xff
+#define D0F0xBC_x1F8E0_BapmSclkVid_1_OFFSET                     8
+#define D0F0xBC_x1F8E0_BapmSclkVid_1_WIDTH                      8
+#define D0F0xBC_x1F8E0_BapmSclkVid_1_MASK                       0xff00
+#define D0F0xBC_x1F8E0_BapmSclkVid_0_OFFSET                     16
+#define D0F0xBC_x1F8E0_BapmSclkVid_0_WIDTH                      8
+#define D0F0xBC_x1F8E0_BapmSclkVid_0_MASK                       0xff0000
+#define D0F0xBC_x1F8E0_DdrVoltFloor_OFFSET                      24
+#define D0F0xBC_x1F8E0_DdrVoltFloor_WIDTH                       8
+#define D0F0xBC_x1F8E0_DdrVoltFloor_MASK                        0xff000000
+
+/// D0F0xBC_x1F8E0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             BapmSclkVid_2:8; ///<
+    UINT32                                             BapmSclkVid_1:8; ///<
+    UINT32                                             BapmSclkVid_0:8; ///<
+    UINT32                                              DdrVoltFloor:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8E0_STRUCT;
+
+// **** D0F0xBC_x1F8E4 Register Definition ****
+// Address
+#define D0F0xBC_x1F8E4_ADDRESS                                  0x1f8e4
+
+// Type
+#define D0F0xBC_x1F8E4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8E4_BapmNbVid_1_OFFSET                       0
+#define D0F0xBC_x1F8E4_BapmNbVid_1_WIDTH                        8
+#define D0F0xBC_x1F8E4_BapmNbVid_1_MASK                         0xff
+#define D0F0xBC_x1F8E4_BapmNbVid_0_OFFSET                       8
+#define D0F0xBC_x1F8E4_BapmNbVid_0_WIDTH                        8
+#define D0F0xBC_x1F8E4_BapmNbVid_0_MASK                         0xff00
+#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_OFFSET                  16
+#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_WIDTH                   8
+#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_MASK                    0xff0000
+#define D0F0xBC_x1F8E4_BapmSclkVid_3_OFFSET                     24
+#define D0F0xBC_x1F8E4_BapmSclkVid_3_WIDTH                      8
+#define D0F0xBC_x1F8E4_BapmSclkVid_3_MASK                       0xff000000
+
+/// D0F0xBC_x1F8E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               BapmNbVid_1:8; ///<
+    UINT32                                               BapmNbVid_0:8; ///<
+    UINT32                                          BapmDdrVoltFloor:8; ///<
+    UINT32                                             BapmSclkVid_3:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8E4_STRUCT;
+
+// **** D0F0xBC_x1F8E8 Register Definition ****
+// Address
+#define D0F0xBC_x1F8E8_ADDRESS                                  0x1f8e8
+
+// Type
+#define D0F0xBC_x1F8E8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8E8_Reserved_15_0_OFFSET                     0
+#define D0F0xBC_x1F8E8_Reserved_15_0_WIDTH                      16
+#define D0F0xBC_x1F8E8_Reserved_15_0_MASK                       0xffff
+#define D0F0xBC_x1F8E8_BapmNbVid_3_OFFSET                       16
+#define D0F0xBC_x1F8E8_BapmNbVid_3_WIDTH                        8
+#define D0F0xBC_x1F8E8_BapmNbVid_3_MASK                         0xff0000
+#define D0F0xBC_x1F8E8_BapmNbVid_2_OFFSET                       24
+#define D0F0xBC_x1F8E8_BapmNbVid_2_WIDTH                        8
+#define D0F0xBC_x1F8E8_BapmNbVid_2_MASK                         0xff000000
+
+/// D0F0xBC_x1F8E8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                              BapmNbVid_3:8;  ///<
+    UINT32                                              BapmNbVid_2:8;  ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8E8_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1002_0:10;
+    UINT32            ex1002_1:20;
+    UINT32            ex1002_2:2;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1002_STRUCT;
+
+// **** D0F0xBC_x1F85C Register Definition ****
+// Address
+#define D0F0xBC_x1F85C_ADDRESS                                  0x1f85c
+
+// Type
+#define D0F0xBC_x1F85C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F85C_VCETdp_OFFSET                            0
+#define D0F0xBC_x1F85C_VCETdp_WIDTH                             20
+#define D0F0xBC_x1F85C_VCETdp_MASK                              0xfffff
+#define D0F0xBC_x1F85C_spare8_OFFSET                            20
+#define D0F0xBC_x1F85C_spare8_WIDTH                             1
+#define D0F0xBC_x1F85C_spare8_MASK                              0x100000
+#define D0F0xBC_x1F85C_TdpAgeValue_OFFSET                       21
+#define D0F0xBC_x1F85C_TdpAgeValue_WIDTH                        3
+#define D0F0xBC_x1F85C_TdpAgeValue_MASK                         0xe00000
+#define D0F0xBC_x1F85C_TdpAgeRate_OFFSET                        24
+#define D0F0xBC_x1F85C_TdpAgeRate_WIDTH                         8
+#define D0F0xBC_x1F85C_TdpAgeRate_MASK                          0xff000000
+
+/// D0F0xBC_x1F85C
+typedef union {
+  struct {                                                               ///<
+    UINT32                                                    VCETdp:20; ///<
+    UINT32                                                    spare8:1;  ///<
+    UINT32                                               TdpAgeValue:3;  ///<
+    UINT32                                                TdpAgeRate:8;  ///<
+  } Field;                                                               ///<
+  UINT32 Value;                                                          ///<
+} D0F0xBC_x1F85C_STRUCT;
+
+// **** D0F0xBC_x1F860 Register Definition ****
+// Address
+#define D0F0xBC_x1F860_ADDRESS                                  0x1f860
+
+// Type
+#define D0F0xBC_x1F860_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_OFFSET                   0
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_WIDTH                    8
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_MASK                     0xff
+#define D0F0xBC_x1F860_BAPMTI_TjMax_1_OFFSET                    8
+#define D0F0xBC_x1F860_BAPMTI_TjMax_1_WIDTH                     8
+#define D0F0xBC_x1F860_BAPMTI_TjMax_1_MASK                      0xff00
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_OFFSET                   16
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_WIDTH                    8
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_MASK                     0xff0000
+#define D0F0xBC_x1F860_BAPMTI_TjMax_0_OFFSET                    24
+#define D0F0xBC_x1F860_BAPMTI_TjMax_0_WIDTH                     8
+#define D0F0xBC_x1F860_BAPMTI_TjMax_0_MASK                      0xff000000
+
+/// D0F0xBC_x1F860
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           BAPMTI_TjHyst_1:8; ///<
+    UINT32                                            BAPMTI_TjMax_1:8; ///<
+    UINT32                                           BAPMTI_TjHyst_0:8; ///<
+    UINT32                                            BAPMTI_TjMax_0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F860_STRUCT;
+
+// **** D0F0xBC_x1F864 Register Definition ****
+// Address
+#define D0F0xBC_x1F864_ADDRESS                                  0x1f864
+
+// Type
+#define D0F0xBC_x1F864_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F864_PCIe2PhyOffset_OFFSET                    0
+#define D0F0xBC_x1F864_PCIe2PhyOffset_WIDTH                     8
+#define D0F0xBC_x1F864_PCIe2PhyOffset_MASK                      0xff
+#define D0F0xBC_x1F864_PCIe1PhyOffset_OFFSET                    8
+#define D0F0xBC_x1F864_PCIe1PhyOffset_WIDTH                     8
+#define D0F0xBC_x1F864_PCIe1PhyOffset_MASK                      0xff00
+#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_OFFSET                  16
+#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_WIDTH                   8
+#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_MASK                    0xff0000
+#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_OFFSET                   24
+#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_WIDTH                    8
+#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_MASK                     0xff000000
+
+/// D0F0xBC_x1F864
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PCIe2PhyOffset:8; ///<
+    UINT32                                            PCIe1PhyOffset:8; ///<
+    UINT32                                          BAPMTI_GpuTjHyst:8; ///<
+    UINT32                                           BAPMTI_GpuTjMax:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F864_STRUCT;
+
+// **** D0F0xBC_x1F86C Register Definition ****
+// Address
+#define D0F0xBC_x1F86C_ADDRESS                                  0x1f86c
+
+// Type
+#define D0F0xBC_x1F86C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F86C_Reserved_22_0_OFFSET                     0
+#define D0F0xBC_x1F86C_Reserved_22_0_WIDTH                      23
+#define D0F0xBC_x1F86C_Reserved_22_0_MASK                       0x7fffff
+#define D0F0xBC_x1F86C_BapmLhtcCap_OFFSET                       23
+#define D0F0xBC_x1F86C_BapmLhtcCap_WIDTH                        1
+#define D0F0xBC_x1F86C_BapmLhtcCap_MASK                         0x800000
+#define D0F0xBC_x1F86C_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F86C_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F86C_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F86C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_22_0:23;///<
+    UINT32                                               BapmLhtcCap:1; ///<
+    UINT32                                            Reserved_31_24:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F86C_STRUCT;
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1003_0:32;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1003_STRUCT;
+
+
+
+// **** D0F0xBC_x1FE00 Register Definition ****
+// Address
+#define D0F0xBC_x1FE00_ADDRESS                                  0x1fe00
+
+// Type
+#define D0F0xBC_x1FE00_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1FE00_Data_OFFSET                              0
+#define D0F0xBC_x1FE00_Data_WIDTH                               32
+#define D0F0xBC_x1FE00_Data_MASK                                0xffffffff
+
+/// D0F0xBC_x1FE00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1FE00_STRUCT;
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              INTR_MASK_0:1 ; ///<
+    UINT32                                              INTR_MASK_1:1 ; ///<
+    UINT32                                              INTR_MASK_2:1 ; ///<
+    UINT32                                              INTR_MASK_3:1 ; ///<
+    UINT32                                              INTR_MASK_4:1 ; ///<
+    UINT32                                              INTR_MASK_5:1 ; ///<
+    UINT32                                              INTR_MASK_6:1 ; ///<
+    UINT32                                              INTR_MASK_7:1 ; ///<
+    UINT32                                              INTR_MASK_8:1 ; ///<
+    UINT32                                              INTR_MASK_9:1 ; ///<
+    UINT32                                             INTR_MASK_10:1 ; ///<
+    UINT32                                             INTR_MASK_11:1 ; ///<
+    UINT32                                             INTR_MASK_12:1 ; ///<
+    UINT32                                             INTR_MASK_13:1 ; ///<
+    UINT32                                             INTR_MASK_14:1 ; ///<
+    UINT32                                             INTR_MASK_15:1 ; ///<
+    UINT32                                             INTR_MASK_16:1 ; ///<
+    UINT32                                             INTR_MASK_17:1 ; ///<
+    UINT32                                             INTR_MASK_18:1 ; ///<
+    UINT32                                             INTR_MASK_19:1 ; ///<
+    UINT32                                             INTR_MASK_20:1 ; ///<
+    UINT32                                             INTR_MASK_21:1 ; ///<
+    UINT32                                             INTR_MASK_22:1 ; ///<
+    UINT32                                             INTR_MASK_23:1 ; ///<
+    UINT32                                             INTR_MASK_24:1 ; ///<
+    UINT32                                             INTR_MASK_25:1 ; ///<
+    UINT32                                             INTR_MASK_26:1 ; ///<
+    UINT32                                             INTR_MASK_27:1 ; ///<
+    UINT32                                             INTR_MASK_28:1 ; ///<
+    UINT32                                             INTR_MASK_29:1 ; ///<
+    UINT32                                             INTR_MASK_30:1 ; ///<
+    UINT32                                             INTR_MASK_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1005_STRUCT;
+
+// **** D0F0xBC_xE0000004 Register Definition ****
+// Address
+#define D0F0xBC_xE0000004_ADDRESS                               0xe0000004
+
+// Type
+#define D0F0xBC_xE0000004_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_OFFSET            0
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_WIDTH             1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_MASK              0x1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_OFFSET           1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_WIDTH            1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_MASK             0x2
+#define D0F0xBC_xE0000004_drv_rst_mode_OFFSET                   2
+#define D0F0xBC_xE0000004_drv_rst_mode_WIDTH                    1
+#define D0F0xBC_xE0000004_drv_rst_mode_MASK                     0x4
+#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_OFFSET    3
+#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_WIDTH     1
+#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_MASK      0x8
+#define D0F0xBC_xE0000004_Reserved_OFFSET                       4
+#define D0F0xBC_xE0000004_Reserved_WIDTH                        1
+#define D0F0xBC_xE0000004_Reserved_MASK                         0x10
+#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_OFFSET      5
+#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_WIDTH       1
+#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_MASK        0x20
+#define D0F0xBC_xE0000004_TP_Tester_OFFSET                      6
+#define D0F0xBC_xE0000004_TP_Tester_WIDTH                       1
+#define D0F0xBC_xE0000004_TP_Tester_MASK                        0x40
+#define D0F0xBC_xE0000004_boot_seq_done_OFFSET                  7
+#define D0F0xBC_xE0000004_boot_seq_done_WIDTH                   1
+#define D0F0xBC_xE0000004_boot_seq_done_MASK                    0x80
+#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_OFFSET           8
+#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_WIDTH            1
+#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_MASK             0x100
+#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_OFFSET               9
+#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_WIDTH                1
+#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_MASK                 0x200
+#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_OFFSET               10
+#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_WIDTH                1
+#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_MASK                 0x400
+#define D0F0xBC_xE0000004_FCH_HALT_OFFSET                       11
+#define D0F0xBC_xE0000004_FCH_HALT_WIDTH                        1
+#define D0F0xBC_xE0000004_FCH_HALT_MASK                         0x800
+#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_OFFSET         12
+#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_WIDTH          1
+#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_MASK           0x1000
+#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_OFFSET           13
+#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_WIDTH            1
+#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_MASK             0x2000
+#define D0F0xBC_xE0000004_Reserved14_23_OFFSET                  14
+#define D0F0xBC_xE0000004_Reserved14_23_WIDTH                   10
+#define D0F0xBC_xE0000004_Reserved14_23_MASK                    0xffc000
+#define D0F0xBC_xE0000004_lm32_irq31_sel_OFFSET                 24
+#define D0F0xBC_xE0000004_lm32_irq31_sel_WIDTH                  2
+#define D0F0xBC_xE0000004_lm32_irq31_sel_MASK                   0x3000000
+#define D0F0xBC_xE0000004_Reserved26_31_OFFSET                  26
+#define D0F0xBC_xE0000004_Reserved26_31_WIDTH                   6
+#define D0F0xBC_xE0000004_Reserved26_31_MASK                    0xfc000000
+
+/// D0F0xBC_xE0000004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      RCU_TST_jpc_rep_req:1 ; ///<
+    UINT32                                     RCU_TST_jpc_rep_done:1 ; ///<
+    UINT32                                             drv_rst_mode:1 ; ///<
+    UINT32                              SMU_DC_efuse_status_invalid:1 ; ///<
+    UINT32                                                 Reserved:1 ; ///<
+    UINT32                                TST_RCU_jpc_DtmSMSCntDone:1 ; ///<
+    UINT32                                                TP_Tester:1 ; ///<
+    UINT32                                            boot_seq_done:1 ; ///<
+    UINT32                                     sclk_deep_sleep_exit:1 ; ///<
+    UINT32                                         BREAK_PT1_ACTIVE:1 ; ///<
+    UINT32                                         BREAK_PT2_ACTIVE:1 ; ///<
+    UINT32                                                 FCH_HALT:1 ; ///<
+    UINT32                                   FCH_LOCKDOWN_WRITE_DIS:1 ; ///<
+    UINT32                                     RCU_GIO_fch_lockdown:1 ; ///<
+    UINT32                                            Reserved14_23:10; ///<
+    UINT32                                           lm32_irq31_sel:2 ; ///<
+    UINT32                                            Reserved26_31:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0000004_STRUCT;
+
+// **** D0F0xBC_xE0000120 Register Definition ****
+// Address
+#define D0F0xBC_xE0000120_ADDRESS                               0xe0000120
+
+// Type
+#define D0F0xBC_xE0000120_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0000120_ActivityCntRst_OFFSET                 0
+#define D0F0xBC_xE0000120_ActivityCntRst_WIDTH                  1
+#define D0F0xBC_xE0000120_ActivityCntRst_MASK                   0x1
+#define D0F0xBC_xE0000120_PeriodCntRst_OFFSET                   1
+#define D0F0xBC_xE0000120_PeriodCntRst_WIDTH                    1
+#define D0F0xBC_xE0000120_PeriodCntRst_MASK                     0x2
+#define D0F0xBC_xE0000120_Reserved_2_2_OFFSET                   2
+#define D0F0xBC_xE0000120_Reserved_2_2_WIDTH                    1
+#define D0F0xBC_xE0000120_Reserved_2_2_MASK                     0x4
+#define D0F0xBC_xE0000120_BusyCntSel_OFFSET                     3
+#define D0F0xBC_xE0000120_BusyCntSel_WIDTH                      2
+#define D0F0xBC_xE0000120_BusyCntSel_MASK                       0x18
+#define D0F0xBC_xE0000120_Reserved_7_5_OFFSET                   5
+#define D0F0xBC_xE0000120_Reserved_7_5_WIDTH                    3
+#define D0F0xBC_xE0000120_Reserved_7_5_MASK                     0xe0
+#define D0F0xBC_xE0000120_EnBifCnt_OFFSET                       8
+#define D0F0xBC_xE0000120_EnBifCnt_WIDTH                        1
+#define D0F0xBC_xE0000120_EnBifCnt_MASK                         0x100
+#define D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET                     9
+#define D0F0xBC_xE0000120_EnOrbUsCnt_WIDTH                      1
+#define D0F0xBC_xE0000120_EnOrbUsCnt_MASK                       0x200
+#define D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET                     10
+#define D0F0xBC_xE0000120_EnOrbDsCnt_WIDTH                      1
+#define D0F0xBC_xE0000120_EnOrbDsCnt_MASK                       0x400
+#define D0F0xBC_xE0000120_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE0000120_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE0000120_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE0000120
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           ActivityCntRst:1 ; ///<
+    UINT32                                             PeriodCntRst:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                               BusyCntSel:2 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                 EnBifCnt:1 ; ///<
+    UINT32                                               EnOrbUsCnt:1 ; ///<
+    UINT32                                               EnOrbDsCnt:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0000120_STRUCT;
+
+// **** D0F0xBC_xE0001008 Register Definition ****
+// Address
+#define D0F0xBC_xE0001008_ADDRESS                               0xe0001008
+
+// Type
+#define D0F0xBC_xE0001008_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0001008_SClkVid0_OFFSET                       0
+#define D0F0xBC_xE0001008_SClkVid0_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid0_MASK                         0xff
+#define D0F0xBC_xE0001008_SClkVid1_OFFSET                       8
+#define D0F0xBC_xE0001008_SClkVid1_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid1_MASK                         0xff00
+#define D0F0xBC_xE0001008_SClkVid2_OFFSET                       16
+#define D0F0xBC_xE0001008_SClkVid2_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid2_MASK                         0xff0000
+#define D0F0xBC_xE0001008_SClkVid3_OFFSET                       24
+#define D0F0xBC_xE0001008_SClkVid3_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid3_MASK                         0xff000000
+
+/// D0F0xBC_xE0001008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 SClkVid0:8 ; ///<
+    UINT32                                                 SClkVid1:8 ; ///<
+    UINT32                                                 SClkVid2:8 ; ///<
+    UINT32                                                 SClkVid3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0001008_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 WriteDis:1 ; ///<
+    UINT32                                                    RfRm7:1 ; ///<
+    UINT32                                                      Rme:1 ; ///<
+    UINT32                                             MbistDisable:1 ; ///<
+    UINT32                                        HardRepairDisable:1 ; ///<
+    UINT32                                        SoftRepairDisable:1 ; ///<
+    UINT32                                         SmsPwrdwnDisable:1 ; ///<
+    UINT32                                           Crbbmp1500Disa:1 ; ///<
+    UINT32                                           Crbbmp1500Disb:1 ; ///<
+    UINT32                                                   GpuDis:1 ; ///<
+    UINT32                      ex1006_0:6;
+    UINT32                      ex1006_1:2;
+    UINT32                                                DftSpare1:1 ; ///<
+    UINT32                                                DftSpare2:1 ; ///<
+    UINT32                                                DftSpare3:1 ; ///<
+    UINT32                                               VceDisable:1 ; ///<
+    UINT32                                           DceScanDisable:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1006_STRUCT;
+
+// **** D0F0xBC_xE0003000 Register Definition ****
+// Address
+#define D0F0xBC_xE0003000_ADDRESS                               0xe0003000
+
+// Type
+#define D0F0xBC_xE0003000_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003000_IntToggle_OFFSET                      0
+#define D0F0xBC_xE0003000_IntToggle_WIDTH                       1
+#define D0F0xBC_xE0003000_IntToggle_MASK                        0x1
+#define D0F0xBC_xE0003000_ServiceIndex_OFFSET                   1
+#define D0F0xBC_xE0003000_ServiceIndex_WIDTH                    16
+#define D0F0xBC_xE0003000_ServiceIndex_MASK                     0x1fffe
+#define D0F0xBC_xE0003000_Reserved_31_17_OFFSET                 17
+#define D0F0xBC_xE0003000_Reserved_31_17_WIDTH                  15
+#define D0F0xBC_xE0003000_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xBC_xE0003000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                IntToggle:1 ; ///<
+    UINT32                                             ServiceIndex:16; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003000_STRUCT;
+
+// **** D0F0xBC_xE0003004 Register Definition ****
+// Address
+#define D0F0xBC_xE0003004_ADDRESS                               0xe0003004
+
+// Type
+#define D0F0xBC_xE0003004_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003004_IntAck_OFFSET                         0
+#define D0F0xBC_xE0003004_IntAck_WIDTH                          1
+#define D0F0xBC_xE0003004_IntAck_MASK                           0x1
+#define D0F0xBC_xE0003004_IntDone_OFFSET                        1
+#define D0F0xBC_xE0003004_IntDone_WIDTH                         1
+#define D0F0xBC_xE0003004_IntDone_MASK                          0x2
+#define D0F0xBC_xE0003004_Reserved_31_2_OFFSET                  2
+#define D0F0xBC_xE0003004_Reserved_31_2_WIDTH                   30
+#define D0F0xBC_xE0003004_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xBC_xE0003004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   IntAck:1 ; ///<
+    UINT32                                                  IntDone:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003004_STRUCT;
+
+// **** D0F0xBC_xE0003024 Register Definition ****
+// Address
+#define D0F0xBC_xE0003024_ADDRESS                               0xe0003024
+
+// Type
+#define D0F0xBC_xE0003024_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003024_SMU_SCRATCH_A_OFFSET                  0
+#define D0F0xBC_xE0003024_SMU_SCRATCH_A_WIDTH                   32
+#define D0F0xBC_xE0003024_SMU_SCRATCH_A_MASK                    0xffffffff
+
+/// D0F0xBC_xE0003024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            SMU_SCRATCH_A:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003024_STRUCT;
+
+// **** D0F0xBC_xE0003034 Register Definition ****
+// Address
+#define D0F0xBC_xE0003034_ADDRESS                               0xe0003034
+
+// Type
+#define D0F0xBC_xE0003034_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003034_PmAllcpusincc6_OFFSET                 0
+#define D0F0xBC_xE0003034_PmAllcpusincc6_WIDTH                  1
+#define D0F0xBC_xE0003034_PmAllcpusincc6_MASK                   0x1
+#define D0F0xBC_xE0003034_PmNbps_OFFSET                         1
+#define D0F0xBC_xE0003034_PmNbps_WIDTH                          1
+#define D0F0xBC_xE0003034_PmNbps_MASK                           0x2
+#define D0F0xBC_xE0003034_PmCommitselfrefr_OFFSET               2
+#define D0F0xBC_xE0003034_PmCommitselfrefr_WIDTH                2
+#define D0F0xBC_xE0003034_PmCommitselfrefr_MASK                 0xc
+#define D0F0xBC_xE0003034_PmPreselfrefresh_OFFSET               4
+#define D0F0xBC_xE0003034_PmPreselfrefresh_WIDTH                1
+#define D0F0xBC_xE0003034_PmPreselfrefresh_MASK                 0x10
+#define D0F0xBC_xE0003034_PmReqnbpstate_OFFSET                  5
+#define D0F0xBC_xE0003034_PmReqnbpstate_WIDTH                   1
+#define D0F0xBC_xE0003034_PmReqnbpstate_MASK                    0x20
+#define D0F0xBC_xE0003034_Reserved_8_6_OFFSET                   6
+#define D0F0xBC_xE0003034_Reserved_8_6_WIDTH                    3
+#define D0F0xBC_xE0003034_Reserved_8_6_MASK                     0x1c0
+#define D0F0xBC_xE0003034_NbNbps_OFFSET                         9
+#define D0F0xBC_xE0003034_NbNbps_WIDTH                          1
+#define D0F0xBC_xE0003034_NbNbps_MASK                           0x200
+#define D0F0xBC_xE0003034_NbCommitselfrefr_OFFSET               10
+#define D0F0xBC_xE0003034_NbCommitselfrefr_WIDTH                2
+#define D0F0xBC_xE0003034_NbCommitselfrefr_MASK                 0xc00
+#define D0F0xBC_xE0003034_NbPreselfrefresh_OFFSET               12
+#define D0F0xBC_xE0003034_NbPreselfrefresh_WIDTH                1
+#define D0F0xBC_xE0003034_NbPreselfrefresh_MASK                 0x1000
+#define D0F0xBC_xE0003034_NbReqnbpstate_OFFSET                  13
+#define D0F0xBC_xE0003034_NbReqnbpstate_WIDTH                   1
+#define D0F0xBC_xE0003034_NbReqnbpstate_MASK                    0x2000
+#define D0F0xBC_xE0003034_McNbps_OFFSET                         14
+#define D0F0xBC_xE0003034_McNbps_WIDTH                          1
+#define D0F0xBC_xE0003034_McNbps_MASK                           0x4000
+#define D0F0xBC_xE0003034_GmconCommitselfrefr_OFFSET            15
+#define D0F0xBC_xE0003034_GmconCommitselfrefr_WIDTH             2
+#define D0F0xBC_xE0003034_GmconCommitselfrefr_MASK              0x18000
+#define D0F0xBC_xE0003034_GmconPreselfrefresh_OFFSET            17
+#define D0F0xBC_xE0003034_GmconPreselfrefresh_WIDTH             1
+#define D0F0xBC_xE0003034_GmconPreselfrefresh_MASK              0x20000
+#define D0F0xBC_xE0003034_GmconReqnbpstate_OFFSET               18
+#define D0F0xBC_xE0003034_GmconReqnbpstate_WIDTH                1
+#define D0F0xBC_xE0003034_GmconReqnbpstate_MASK                 0x40000
+#define D0F0xBC_xE0003034_SysIso_OFFSET                         19
+#define D0F0xBC_xE0003034_SysIso_WIDTH                          1
+#define D0F0xBC_xE0003034_SysIso_MASK                           0x80000
+#define D0F0xBC_xE0003034_CpIso_OFFSET                          20
+#define D0F0xBC_xE0003034_CpIso_WIDTH                           1
+#define D0F0xBC_xE0003034_CpIso_MASK                            0x100000
+#define D0F0xBC_xE0003034_Dc0Iso_OFFSET                         21
+#define D0F0xBC_xE0003034_Dc0Iso_WIDTH                          1
+#define D0F0xBC_xE0003034_Dc0Iso_MASK                           0x200000
+#define D0F0xBC_xE0003034_Dc1Iso_OFFSET                         22
+#define D0F0xBC_xE0003034_Dc1Iso_WIDTH                          1
+#define D0F0xBC_xE0003034_Dc1Iso_MASK                           0x400000
+#define D0F0xBC_xE0003034_DciIso_OFFSET                         23
+#define D0F0xBC_xE0003034_DciIso_WIDTH                          1
+#define D0F0xBC_xE0003034_DciIso_MASK                           0x800000
+#define D0F0xBC_xE0003034_DcipgIso_OFFSET                       24
+#define D0F0xBC_xE0003034_DcipgIso_WIDTH                        1
+#define D0F0xBC_xE0003034_DcipgIso_MASK                         0x1000000
+#define D0F0xBC_xE0003034_DdiIso_OFFSET                         25
+#define D0F0xBC_xE0003034_DdiIso_WIDTH                          1
+#define D0F0xBC_xE0003034_DdiIso_MASK                           0x2000000
+#define D0F0xBC_xE0003034_GmcIso_OFFSET                         26
+#define D0F0xBC_xE0003034_GmcIso_WIDTH                          1
+#define D0F0xBC_xE0003034_GmcIso_MASK                           0x4000000
+#define D0F0xBC_xE0003034_Reserved_27_27_OFFSET                 27
+#define D0F0xBC_xE0003034_Reserved_27_27_WIDTH                  1
+#define D0F0xBC_xE0003034_Reserved_27_27_MASK                   0x8000000
+#define D0F0xBC_xE0003034_GmcPmSel_OFFSET                       28
+#define D0F0xBC_xE0003034_GmcPmSel_WIDTH                        2
+#define D0F0xBC_xE0003034_GmcPmSel_MASK                         0x30000000
+#define D0F0xBC_xE0003034_CpPmSel_OFFSET                        30
+#define D0F0xBC_xE0003034_CpPmSel_WIDTH                         2
+#define D0F0xBC_xE0003034_CpPmSel_MASK                          0xc0000000
+
+/// D0F0xBC_xE0003034
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PmAllcpusincc6:1 ; ///<
+    UINT32                                                   PmNbps:1 ; ///<
+    UINT32                                         PmCommitselfrefr:2 ; ///<
+    UINT32                                         PmPreselfrefresh:1 ; ///<
+    UINT32                                            PmReqnbpstate:1 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                                   NbNbps:1 ; ///<
+    UINT32                                         NbCommitselfrefr:2 ; ///<
+    UINT32                                         NbPreselfrefresh:1 ; ///<
+    UINT32                                            NbReqnbpstate:1 ; ///<
+    UINT32                                                   McNbps:1 ; ///<
+    UINT32                                      GmconCommitselfrefr:2 ; ///<
+    UINT32                                      GmconPreselfrefresh:1 ; ///<
+    UINT32                                         GmconReqnbpstate:1 ; ///<
+    UINT32                                                   SysIso:1 ; ///<
+    UINT32                                                    CpIso:1 ; ///<
+    UINT32                                                   Dc0Iso:1 ; ///<
+    UINT32                                                   Dc1Iso:1 ; ///<
+    UINT32                                                   DciIso:1 ; ///<
+    UINT32                                                 DcipgIso:1 ; ///<
+    UINT32                                                   DdiIso:1 ; ///<
+    UINT32                                                   GmcIso:1 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                                 GmcPmSel:2 ; ///<
+    UINT32                                                  CpPmSel:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003034_STRUCT;
+
+// **** D0F0xBC_xE0003048 Register Definition ****
+// Address
+#define D0F0xBC_xE0003048_ADDRESS                               0xe0003048
+
+// Type
+#define D0F0xBC_xE0003048_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003048_Fracv_OFFSET                          0
+#define D0F0xBC_xE0003048_Fracv_WIDTH                           12
+#define D0F0xBC_xE0003048_Fracv_MASK                            0xfff
+#define D0F0xBC_xE0003048_Intv_OFFSET                           12
+#define D0F0xBC_xE0003048_Intv_WIDTH                            7
+#define D0F0xBC_xE0003048_Intv_MASK                             0x7f000
+#define D0F0xBC_xE0003048_Reserved_31_19_OFFSET                 19
+#define D0F0xBC_xE0003048_Reserved_31_19_WIDTH                  13
+#define D0F0xBC_xE0003048_Reserved_31_19_MASK                   0xfff80000
+
+/// D0F0xBC_xE0003048
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Fracv:12; ///<
+    UINT32                                                     Intv:7 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003048_STRUCT;
+
+// **** D0F0xBC_xE0003088 Register Definition ****
+// Address
+#define D0F0xBC_xE0003088_ADDRESS                               0xe0003088
+
+// Type
+#define D0F0xBC_xE0003088_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003088_SmuAuthDone_OFFSET                    0
+#define D0F0xBC_xE0003088_SmuAuthDone_WIDTH                     1
+#define D0F0xBC_xE0003088_SmuAuthDone_MASK                      0x1
+#define D0F0xBC_xE0003088_SmuAuthPass_OFFSET                    1
+#define D0F0xBC_xE0003088_SmuAuthPass_WIDTH                     1
+#define D0F0xBC_xE0003088_SmuAuthPass_MASK                      0x2
+#define D0F0xBC_xE0003088_Reserved_31_2_OFFSET                  2
+#define D0F0xBC_xE0003088_Reserved_31_2_WIDTH                   30
+#define D0F0xBC_xE0003088_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xBC_xE0003088
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              SmuAuthDone:1 ; ///<
+    UINT32                                              SmuAuthPass:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003088_STRUCT;
+
+// **** D0F0xBC_xE00030A4 Register Definition ****
+// Address
+#define D0F0xBC_xE00030A4_ADDRESS                               0xe00030a4
+
+// Type
+#define D0F0xBC_xE00030A4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE00030A4_Reserved_15_0_OFFSET                  0
+#define D0F0xBC_xE00030A4_Reserved_15_0_WIDTH                   16
+#define D0F0xBC_xE00030A4_Reserved_15_0_MASK                    0xffff
+#define D0F0xBC_xE00030A4_SmuProtectedMode_OFFSET               16
+#define D0F0xBC_xE00030A4_SmuProtectedMode_WIDTH                1
+#define D0F0xBC_xE00030A4_SmuProtectedMode_MASK                 0x10000
+#define D0F0xBC_xE00030A4_Reserved_31_17_OFFSET                 17
+#define D0F0xBC_xE00030A4_Reserved_31_17_WIDTH                  15
+#define D0F0xBC_xE00030A4_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xBC_xE00030A4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                         SmuProtectedMode:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE00030A4_STRUCT;
+
+// **** D0F0xBC_xE0104040 Register Definition ****
+// Address
+#define D0F0xBC_xE0104040_ADDRESS                               0xe0104040
+
+// Type
+#define D0F0xBC_xE0104040_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0104040_Reserved_6_0_OFFSET                   0
+#define D0F0xBC_xE0104040_Reserved_6_0_WIDTH                    7
+#define D0F0xBC_xE0104040_Reserved_6_0_MASK                     0x7f
+#define D0F0xBC_xE0104040_DeviceID_OFFSET                       7
+#define D0F0xBC_xE0104040_DeviceID_WIDTH                        16
+#define D0F0xBC_xE0104040_DeviceID_MASK                         0x7fff80
+#define D0F0xBC_xE0104040_Reserved_31_17_OFFSET                 23
+#define D0F0xBC_xE0104040_Reserved_31_17_WIDTH                  9
+#define D0F0xBC_xE0104040_Reserved_31_17_MASK                   0xff800000
+
+/// D0F0xBC_xE0104040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_6_0:7;  ///<
+    UINT32                                                DeviceID:16 ; ///<
+    UINT32                                           Reserved_31_23:9; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104040_STRUCT;
+
+// **** D0F0xBC_xE0104168 Register Definition ****
+// Address
+#define D0F0xBC_xE0104168_ADDRESS                               0xe0104168
+
+// Type
+#define D0F0xBC_xE0104168_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0104168_GnbLPML15_5_0_OFFSET                  0
+#define D0F0xBC_xE0104168_GnbLPML15_5_0_WIDTH                   6
+#define D0F0xBC_xE0104168_GnbLPML15_5_0_MASK                    0x3f
+#define D0F0xBC_xE0104168_MemClkVid0_7_0_OFFSET                 6
+#define D0F0xBC_xE0104168_MemClkVid0_7_0_WIDTH                  8
+#define D0F0xBC_xE0104168_MemClkVid0_7_0_MASK                   0x3fc0
+#define D0F0xBC_xE0104168_MemClkVid1_7_0_OFFSET                 14
+#define D0F0xBC_xE0104168_MemClkVid1_7_0_WIDTH                  8
+#define D0F0xBC_xE0104168_MemClkVid1_7_0_MASK                   0x3fc000
+#define D0F0xBC_xE0104168_MemClkVid2_7_0_OFFSET                 22
+#define D0F0xBC_xE0104168_MemClkVid2_7_0_WIDTH                  8
+#define D0F0xBC_xE0104168_MemClkVid2_7_0_MASK                   0x3fc00000
+#define D0F0xBC_xE0104168_MemClkVid3_1_0_OFFSET                 30
+#define D0F0xBC_xE0104168_MemClkVid3_1_0_WIDTH                  2
+#define D0F0xBC_xE0104168_MemClkVid3_1_0_MASK                   0xc0000000
+
+/// D0F0xBC_xE0104168
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            GnbLPML15_5_0:6 ; ///<
+    UINT32                                           MemClkVid0_7_0:8 ; ///<
+    UINT32                                           MemClkVid1_7_0:8 ; ///<
+    UINT32                                           MemClkVid2_7_0:8 ; ///<
+    UINT32                                           MemClkVid3_1_0:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104168_STRUCT;
+
+// **** D0F0xBC_xE010416C Register Definition ****
+// Address
+#define D0F0xBC_xE010416C_ADDRESS                               0xe010416c
+
+// Type
+#define D0F0xBC_xE010416C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE010416C_MemClkVid3_7_2_OFFSET                 0
+#define D0F0xBC_xE010416C_MemClkVid3_7_2_WIDTH                  6
+#define D0F0xBC_xE010416C_MemClkVid3_7_2_MASK                   0x3f
+#define D0F0xBC_xE010416C_MemClkVid4_7_0_OFFSET                 6
+#define D0F0xBC_xE010416C_MemClkVid4_7_0_WIDTH                  8
+#define D0F0xBC_xE010416C_MemClkVid4_7_0_MASK                   0x3fc0
+#define D0F0xBC_xE010416C_MemClkVid5_7_0_OFFSET                 14
+#define D0F0xBC_xE010416C_MemClkVid5_7_0_WIDTH                  8
+#define D0F0xBC_xE010416C_MemClkVid5_7_0_MASK                   0x3fc000
+#define D0F0xBC_xE010416C_MemClkVid6_7_0_OFFSET                 22
+#define D0F0xBC_xE010416C_MemClkVid6_7_0_WIDTH                  8
+#define D0F0xBC_xE010416C_MemClkVid6_7_0_MASK                   0x3fc00000
+#define D0F0xBC_xE010416C_MemClkVid7_1_0_OFFSET                 30
+#define D0F0xBC_xE010416C_MemClkVid7_1_0_WIDTH                  2
+#define D0F0xBC_xE010416C_MemClkVid7_1_0_MASK                   0xc0000000
+
+/// D0F0xBC_xE010416C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MemClkVid3_7_2:6 ; ///<
+    UINT32                                           MemClkVid4_7_0:8 ; ///<
+    UINT32                                           MemClkVid5_7_0:8 ; ///<
+    UINT32                                           MemClkVid6_7_0:8 ; ///<
+    UINT32                                           MemClkVid7_1_0:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010416C_STRUCT;
+
+// **** D0F0xBC_xE0104170 Register Definition ****
+// Address
+#define D0F0xBC_xE0104170_ADDRESS                               0xe0104170
+
+// Type
+#define D0F0xBC_xE0104170_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0104170_MemClkVid7_7_2_OFFSET                 0
+#define D0F0xBC_xE0104170_MemClkVid7_7_2_WIDTH                  6
+#define D0F0xBC_xE0104170_MemClkVid7_7_2_MASK                   0x3f
+#define D0F0xBC_xE0104170_MemClkVid8_7_0_OFFSET                 6
+#define D0F0xBC_xE0104170_MemClkVid8_7_0_WIDTH                  8
+#define D0F0xBC_xE0104170_MemClkVid8_7_0_MASK                   0x3fc0
+#define D0F0xBC_xE0104170_AmbientTempBase_7_0_OFFSET            14
+#define D0F0xBC_xE0104170_AmbientTempBase_7_0_WIDTH             8
+#define D0F0xBC_xE0104170_AmbientTempBase_7_0_MASK              0x3fc000
+#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_OFFSET                22
+#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_WIDTH                 10
+#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_MASK                  0xffc00000
+
+/// D0F0xBC_xE0104170
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MemClkVid7_7_2:6 ; ///<
+    UINT32                                           MemClkVid8_7_0:8 ; ///<
+    UINT32                                      AmbientTempBase_7_0:8 ; ///<
+    UINT32                                          SMU_SPARE31_9_0:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104170_STRUCT;
+
+// **** D0F0xBC_xE0300000 Register Definition ****
+// Address
+#define D0F0xBC_xE0300000_ADDRESS                               0xe0300000
+
+// Type
+#define D0F0xBC_xE0300000_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300000_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300000_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300000_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300000_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300000_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300000_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300000_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300000_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300000_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300000_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300000_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300000_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300000_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300000_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300000_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300000_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300000_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300000_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300000_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300000_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300000_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300000_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300000_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300000_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300000_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300000_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300000_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300000_STRUCT;
+
+// **** D0F0xBC_xE0300004 Register Definition ****
+// Address
+#define D0F0xBC_xE0300004_ADDRESS                               0xe0300004
+
+// Type
+#define D0F0xBC_xE0300004_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300004_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300004_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300004_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300004_STRUCT;
+
+// **** D0F0xBC_xE0300008 Register Definition ****
+// Address
+#define D0F0xBC_xE0300008_ADDRESS                               0xe0300008
+
+// Type
+#define D0F0xBC_xE0300008_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300008_ReadValue_OFFSET                      0
+#define D0F0xBC_xE0300008_ReadValue_WIDTH                       24
+#define D0F0xBC_xE0300008_ReadValue_MASK                        0xffffff
+#define D0F0xBC_xE0300008_ReadValid_OFFSET                      24
+#define D0F0xBC_xE0300008_ReadValid_WIDTH                       1
+#define D0F0xBC_xE0300008_ReadValid_MASK                        0x1000000
+#define D0F0xBC_xE0300008_Reserved_31_25_OFFSET                 25
+#define D0F0xBC_xE0300008_Reserved_31_25_WIDTH                  7
+#define D0F0xBC_xE0300008_Reserved_31_25_MASK                   0xfe000000
+
+/// D0F0xBC_xE0300008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ReadValue:24; ///<
+    UINT32                                                ReadValid:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300008_STRUCT;
+
+// **** D0F0xBC_xE030000C Register Definition ****
+// Address
+#define D0F0xBC_xE030000C_ADDRESS                               0xe030000c
+
+// Type
+#define D0F0xBC_xE030000C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030000C_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE030000C_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE030000C_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE030000C_PowerDown_OFFSET                      8
+#define D0F0xBC_xE030000C_PowerDown_WIDTH                       1
+#define D0F0xBC_xE030000C_PowerDown_MASK                        0x100
+#define D0F0xBC_xE030000C_PowerUp_OFFSET                        9
+#define D0F0xBC_xE030000C_PowerUp_WIDTH                         1
+#define D0F0xBC_xE030000C_PowerUp_MASK                          0x200
+#define D0F0xBC_xE030000C_P1Select_OFFSET                       10
+#define D0F0xBC_xE030000C_P1Select_WIDTH                        1
+#define D0F0xBC_xE030000C_P1Select_MASK                         0x400
+#define D0F0xBC_xE030000C_P2Select_OFFSET                       11
+#define D0F0xBC_xE030000C_P2Select_WIDTH                        1
+#define D0F0xBC_xE030000C_P2Select_MASK                         0x800
+#define D0F0xBC_xE030000C_WriteOp_OFFSET                        12
+#define D0F0xBC_xE030000C_WriteOp_WIDTH                         1
+#define D0F0xBC_xE030000C_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE030000C_ReadOp_OFFSET                         13
+#define D0F0xBC_xE030000C_ReadOp_WIDTH                          1
+#define D0F0xBC_xE030000C_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE030000C_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE030000C_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE030000C_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE030000C_RegAddr_OFFSET                        28
+#define D0F0xBC_xE030000C_RegAddr_WIDTH                         4
+#define D0F0xBC_xE030000C_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE030000C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030000C_STRUCT;
+
+// **** D0F0xBC_xE0300010 Register Definition ****
+// Address
+#define D0F0xBC_xE0300010_ADDRESS                               0xe0300010
+
+// Type
+#define D0F0xBC_xE0300010_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300010_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300010_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300010_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300010_STRUCT;
+
+// **** D0F0xBC_xE0300018 Register Definition ****
+// Address
+#define D0F0xBC_xE0300018_ADDRESS                               0xe0300018
+
+// Type
+#define D0F0xBC_xE0300018_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300018_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300018_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300018_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300018_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300018_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300018_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300018_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300018_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300018_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300018_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300018_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300018_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300018_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300018_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300018_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300018_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300018_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300018_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300018_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300018_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300018_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300018_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300018_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300018_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300018_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300018_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300018_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300018
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300018_STRUCT;
+
+// **** D0F0xBC_xE030001C Register Definition ****
+// Address
+#define D0F0xBC_xE030001C_ADDRESS                               0xe030001c
+
+// Type
+#define D0F0xBC_xE030001C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030001C_Write_value_OFFSET                    0
+#define D0F0xBC_xE030001C_Write_value_WIDTH                     32
+#define D0F0xBC_xE030001C_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE030001C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030001C_STRUCT;
+
+// **** D0F0xBC_xE0300024 Register Definition ****
+// Address
+#define D0F0xBC_xE0300024_ADDRESS                               0xe0300024
+
+// Type
+#define D0F0xBC_xE0300024_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300024_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300024_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300024_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300024_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300024_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300024_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300024_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300024_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300024_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300024_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300024_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300024_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300024_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300024_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300024_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300024_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300024_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300024_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300024_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300024_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300024_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300024_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300024_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300024_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300024_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300024_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300024_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300024_STRUCT;
+
+// **** D0F0xBC_xE0300028 Register Definition ****
+// Address
+#define D0F0xBC_xE0300028_ADDRESS                               0xe0300028
+
+// Type
+#define D0F0xBC_xE0300028_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300028_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300028_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300028_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300028
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300028_STRUCT;
+
+// **** D0F0xBC_xE0300030 Register Definition ****
+// Address
+#define D0F0xBC_xE0300030_ADDRESS                               0xe0300030
+
+// Type
+#define D0F0xBC_xE0300030_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300030_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300030_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300030_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300030_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300030_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300030_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300030_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300030_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300030_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300030_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300030_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300030_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300030_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300030_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300030_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300030_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300030_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300030_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300030_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300030_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300030_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300030_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300030_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300030_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300030_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300030_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300030_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300030
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300030_STRUCT;
+
+// **** D0F0xBC_xE0300034 Register Definition ****
+// Address
+#define D0F0xBC_xE0300034_ADDRESS                               0xe0300034
+
+// Type
+#define D0F0xBC_xE0300034_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300034_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300034_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300034_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300034
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300034_STRUCT;
+
+// **** D0F0xBC_xE030003C Register Definition ****
+// Address
+#define D0F0xBC_xE030003C_ADDRESS                               0xe030003c
+
+// Type
+#define D0F0xBC_xE030003C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030003C_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE030003C_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE030003C_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE030003C_PowerDown_OFFSET                      8
+#define D0F0xBC_xE030003C_PowerDown_WIDTH                       1
+#define D0F0xBC_xE030003C_PowerDown_MASK                        0x100
+#define D0F0xBC_xE030003C_PowerUp_OFFSET                        9
+#define D0F0xBC_xE030003C_PowerUp_WIDTH                         1
+#define D0F0xBC_xE030003C_PowerUp_MASK                          0x200
+#define D0F0xBC_xE030003C_P1Select_OFFSET                       10
+#define D0F0xBC_xE030003C_P1Select_WIDTH                        1
+#define D0F0xBC_xE030003C_P1Select_MASK                         0x400
+#define D0F0xBC_xE030003C_P2Select_OFFSET                       11
+#define D0F0xBC_xE030003C_P2Select_WIDTH                        1
+#define D0F0xBC_xE030003C_P2Select_MASK                         0x800
+#define D0F0xBC_xE030003C_WriteOp_OFFSET                        12
+#define D0F0xBC_xE030003C_WriteOp_WIDTH                         1
+#define D0F0xBC_xE030003C_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE030003C_ReadOp_OFFSET                         13
+#define D0F0xBC_xE030003C_ReadOp_WIDTH                          1
+#define D0F0xBC_xE030003C_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE030003C_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE030003C_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE030003C_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE030003C_RegAddr_OFFSET                        28
+#define D0F0xBC_xE030003C_RegAddr_WIDTH                         4
+#define D0F0xBC_xE030003C_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE030003C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030003C_STRUCT;
+
+// **** D0F0xBC_xE0300040 Register Definition ****
+// Address
+#define D0F0xBC_xE0300040_ADDRESS                               0xe0300040
+
+// Type
+#define D0F0xBC_xE0300040_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300040_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300040_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300040_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300040_STRUCT;
+
+// **** D0F0xBC_xE0300054 Register Definition ****
+// Address
+#define D0F0xBC_xE0300054_ADDRESS                               0xe0300054
+
+// Type
+#define D0F0xBC_xE0300054_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300054_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300054_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300054_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300054_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300054_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300054_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300054_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300054_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300054_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300054_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300054_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300054_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300054_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300054_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300054_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300054_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300054_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300054_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300054_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300054_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300054_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300054_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300054_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300054_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300054_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300054_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300054_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300054
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300054_STRUCT;
+
+// **** D0F0xBC_xE0300058 Register Definition ****
+// Address
+#define D0F0xBC_xE0300058_ADDRESS                               0xe0300058
+
+// Type
+#define D0F0xBC_xE0300058_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300058_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300058_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300058_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300058
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300058_STRUCT;
+
+// **** D0F0xBC_xE0300070 Register Definition ****
+// Address
+#define D0F0xBC_xE0300070_ADDRESS                               0xe0300070
+
+// Type
+#define D0F0xBC_xE0300070_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300070_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300070_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300070_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300070_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300070_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300070_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300070_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300070_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300070_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300070_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300070_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300070_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300070_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300070_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300070_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300070_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300070_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300070_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300070_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300070_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300070_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300070_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300070_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300070_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300070_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300070_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300070_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300070
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300070_STRUCT;
+
+// **** D0F0xBC_xE0300074 Register Definition ****
+// Address
+#define D0F0xBC_xE0300074_ADDRESS                               0xe0300074
+
+// Type
+#define D0F0xBC_xE0300074_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300074_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300074_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300074_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300074
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300074_STRUCT;
+
+// **** D0F0xBC_xE030008C Register Definition ****
+// Address
+#define D0F0xBC_xE030008C_ADDRESS                               0xe030008c
+
+// Type
+#define D0F0xBC_xE030008C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030008C_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE030008C_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE030008C_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE030008C_PowerDown_OFFSET                      8
+#define D0F0xBC_xE030008C_PowerDown_WIDTH                       1
+#define D0F0xBC_xE030008C_PowerDown_MASK                        0x100
+#define D0F0xBC_xE030008C_PowerUp_OFFSET                        9
+#define D0F0xBC_xE030008C_PowerUp_WIDTH                         1
+#define D0F0xBC_xE030008C_PowerUp_MASK                          0x200
+#define D0F0xBC_xE030008C_P1Select_OFFSET                       10
+#define D0F0xBC_xE030008C_P1Select_WIDTH                        1
+#define D0F0xBC_xE030008C_P1Select_MASK                         0x400
+#define D0F0xBC_xE030008C_P2Select_OFFSET                       11
+#define D0F0xBC_xE030008C_P2Select_WIDTH                        1
+#define D0F0xBC_xE030008C_P2Select_MASK                         0x800
+#define D0F0xBC_xE030008C_WriteOp_OFFSET                        12
+#define D0F0xBC_xE030008C_WriteOp_WIDTH                         1
+#define D0F0xBC_xE030008C_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE030008C_ReadOp_OFFSET                         13
+#define D0F0xBC_xE030008C_ReadOp_WIDTH                          1
+#define D0F0xBC_xE030008C_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE030008C_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE030008C_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE030008C_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE030008C_RegAddr_OFFSET                        28
+#define D0F0xBC_xE030008C_RegAddr_WIDTH                         4
+#define D0F0xBC_xE030008C_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE030008C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030008C_STRUCT;
+
+// **** D0F0xBC_xE0300090 Register Definition ****
+// Address
+#define D0F0xBC_xE0300090_ADDRESS                               0xe0300090
+
+// Type
+#define D0F0xBC_xE0300090_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300090_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300090_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300090_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300090
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300090_STRUCT;
+
+// **** D0F0xBC_xE03000A8 Register Definition ****
+// Address
+#define D0F0xBC_xE03000A8_ADDRESS                               0xe03000a8
+
+// Type
+#define D0F0xBC_xE03000A8_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000A8_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000A8_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000A8_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000A8_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000A8_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000A8_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000A8_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000A8_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000A8_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000A8_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000A8_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000A8_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000A8_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000A8_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000A8_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000A8_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000A8_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000A8_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000A8_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000A8_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000A8_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000A8_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000A8_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000A8_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000A8_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000A8_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000A8_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000A8_STRUCT;
+
+// **** D0F0xBC_xE03000AC Register Definition ****
+// Address
+#define D0F0xBC_xE03000AC_ADDRESS                               0xe03000ac
+
+// Type
+#define D0F0xBC_xE03000AC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000AC_WriteValue_OFFSET                     0
+#define D0F0xBC_xE03000AC_WriteValue_WIDTH                      32
+#define D0F0xBC_xE03000AC_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE03000AC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000AC_STRUCT;
+
+// **** D0F0xBC_xE03000C4 Register Definition ****
+// Address
+#define D0F0xBC_xE03000C4_ADDRESS                               0xe03000c4
+
+// Type
+#define D0F0xBC_xE03000C4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000C4_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000C4_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000C4_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000C4_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000C4_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000C4_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000C4_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000C4_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000C4_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000C4_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000C4_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000C4_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000C4_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000C4_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000C4_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000C4_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000C4_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000C4_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000C4_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000C4_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000C4_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000C4_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000C4_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000C4_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000C4_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000C4_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000C4_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000C4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000C4_STRUCT;
+
+// **** D0F0xBC_xE03000C8 Register Definition ****
+// Address
+#define D0F0xBC_xE03000C8_ADDRESS                               0xe03000c8
+
+// Type
+#define D0F0xBC_xE03000C8_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000C8_WriteValue_OFFSET                     0
+#define D0F0xBC_xE03000C8_WriteValue_WIDTH                      32
+#define D0F0xBC_xE03000C8_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE03000C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000C8_STRUCT;
+
+// **** D0F0xBC_xE03000E0 Register Definition ****
+// Address
+#define D0F0xBC_xE03000E0_ADDRESS                               0xe03000e0
+
+// Type
+#define D0F0xBC_xE03000E0_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000E0_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000E0_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000E0_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000E0_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000E0_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000E0_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000E0_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000E0_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000E0_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000E0_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000E0_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000E0_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000E0_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000E0_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000E0_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000E0_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000E0_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000E0_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000E0_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000E0_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000E0_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000E0_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000E0_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000E0_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000E0_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000E0_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000E0_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000E0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000E0_STRUCT;
+
+// **** D0F0xBC_xE03000E4 Register Definition ****
+// Address
+#define D0F0xBC_xE03000E4_ADDRESS                               0xe03000e4
+
+// Type
+#define D0F0xBC_xE03000E4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000E4_WriteValue_OFFSET                     0
+#define D0F0xBC_xE03000E4_WriteValue_WIDTH                      32
+#define D0F0xBC_xE03000E4_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE03000E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000E4_STRUCT;
+
+// **** D0F0xBC_xE03000FC Register Definition ****
+// Address
+#define D0F0xBC_xE03000FC_ADDRESS                               0xe03000fc
+
+// Type
+#define D0F0xBC_xE03000FC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000FC_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000FC_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000FC_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000FC_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000FC_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000FC_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000FC_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000FC_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000FC_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000FC_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000FC_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000FC_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000FC_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000FC_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000FC_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000FC_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000FC_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000FC_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000FC_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000FC_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000FC_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000FC_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000FC_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000FC_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000FC_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000FC_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000FC_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000FC_STRUCT;
+
+// **** D0F0xBC_xE0300100 Register Definition ****
+// Address
+#define D0F0xBC_xE0300100_ADDRESS                               0xe0300100
+
+// Type
+#define D0F0xBC_xE0300100_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300100_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300100_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300100_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300100
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300100_STRUCT;
+
+// **** D0F0xBC_xE0300200 Register Definition ****
+// Address
+#define D0F0xBC_xE0300200_ADDRESS                               0xe0300200
+
+// Type
+#define D0F0xBC_xE0300200_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300200_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300200_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300200_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300200_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300200_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300200_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300200_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE0300200_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE0300200_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE0300200
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300200_STRUCT;
+
+
+// Type
+#define D0F0xBC_xE0300208_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300208_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300208_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300208_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300208_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300208_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300208_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300208_Reserved_12_11_OFFSET                 11
+#define D0F0xBC_xE0300208_Reserved_12_11_WIDTH                  2
+#define D0F0xBC_xE0300208_Reserved_12_11_MASK                   0x1800
+#define D0F0xBC_xE0300208_P1PsoDaug_OFFSET                      13
+#define D0F0xBC_xE0300208_P1PsoDaug_WIDTH                       1
+#define D0F0xBC_xE0300208_P1PsoDaug_MASK                        0x2000
+#define D0F0xBC_xE0300208_Reserved_31_14_OFFSET                 14
+#define D0F0xBC_xE0300208_Reserved_31_14_WIDTH                  18
+#define D0F0xBC_xE0300208_Reserved_31_14_MASK                   0xffffc000
+
+/// D0F0xBC_xE0300208
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                :1 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300208_STRUCT;
+
+// **** D0F0xBC_xE030020C Register Definition ****
+// Address
+#define D0F0xBC_xE030020C_ADDRESS                               0xe030020c
+
+// Type
+#define D0F0xBC_xE030020C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030020C_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE030020C_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE030020C_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE030020C_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE030020C_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE030020C_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE030020C_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE030020C_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE030020C_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE030020C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030020C_STRUCT;
+
+// **** D0F0xBC_xE0300210 Register Definition ****
+// Address
+#define D0F0xBC_xE0300210_ADDRESS                               0xe0300210
+
+// Type
+#define D0F0xBC_xE0300210_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300210_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300210_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300210_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300210_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300210_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300210_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300210_Reserved_12_11_OFFSET                 11
+#define D0F0xBC_xE0300210_Reserved_12_11_WIDTH                  2
+#define D0F0xBC_xE0300210_Reserved_12_11_MASK                   0x1800
+#define D0F0xBC_xE0300210_Reserved_31_14_OFFSET                 14
+#define D0F0xBC_xE0300210_Reserved_31_14_WIDTH                  18
+#define D0F0xBC_xE0300210_Reserved_31_14_MASK                   0xffffc000
+
+/// D0F0xBC_xE0300210
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                :1 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300210_STRUCT;
+
+// **** D0F0xBC_xE0300218 Register Definition ****
+// Address
+#define D0F0xBC_xE0300218_ADDRESS                               0xe0300218
+
+// Type
+#define D0F0xBC_xE0300218_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300218_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300218_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300218_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300218_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300218_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300218_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300218_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE0300218_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE0300218_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE0300218
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300218_STRUCT;
+
+// **** D0F0xBC_xE03002DC Register Definition ****
+// Address
+#define D0F0xBC_xE03002DC_ADDRESS                               0xe03002dc
+
+// Type
+#define D0F0xBC_xE03002DC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET              0
+#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_WIDTH               1
+#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_MASK                0x1
+#define D0F0xBC_xE03002DC_Reserved_OFFSET                       1
+#define D0F0xBC_xE03002DC_Reserved_WIDTH                        31
+#define D0F0xBC_xE03002DC_Reserved_MASK                         0xfffffffe
+
+/// D0F0xBC_xE03002DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DC2_PGFSM_CONTROL:1 ; ///<
+    UINT32                                                 Reserved:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002DC_STRUCT;
+
+// **** D0F0xBC_xE03002E4 Register Definition ****
+// Address
+#define D0F0xBC_xE03002E4_ADDRESS                               0xe03002e4
+
+// Type
+#define D0F0xBC_xE03002E4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_OFFSET                  0
+#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_MASK                    0x1
+#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_OFFSET                  1
+#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_MASK                    0x2
+#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_OFFSET                  2
+#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_MASK                    0x4
+#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_OFFSET                  3
+#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_MASK                    0x8
+#define D0F0xBC_xE03002E4_SmuPaPsoDaug_OFFSET                   4
+#define D0F0xBC_xE03002E4_SmuPaPsoDaug_WIDTH                    1
+#define D0F0xBC_xE03002E4_SmuPaPsoDaug_MASK                     0x10
+#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_OFFSET                  5
+#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_MASK                    0x20
+#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_OFFSET                  6
+#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_MASK                    0x40
+#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_OFFSET                  7
+#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_MASK                    0x80
+#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_OFFSET                  8
+#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_MASK                    0x100
+#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_OFFSET                 9
+#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_WIDTH                  1
+#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_MASK                   0x200
+#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_OFFSET                 10
+#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_WIDTH                  1
+#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_MASK                   0x400
+#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_OFFSET                  11
+#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_MASK                    0x800
+#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_OFFSET                  12
+#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_MASK                    0x1000
+#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_OFFSET                  13
+#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_MASK                    0x2000
+#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_OFFSET                  14
+#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_MASK                    0x4000
+#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_OFFSET                  15
+#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_MASK                    0x8000
+#define D0F0xBC_xE03002E4_SmuTcPsoDaug_OFFSET                   16
+#define D0F0xBC_xE03002E4_SmuTcPsoDaug_WIDTH                    1
+#define D0F0xBC_xE03002E4_SmuTcPsoDaug_MASK                     0x10000
+#define D0F0xBC_xE03002E4_SmuScPsoDaug_OFFSET                   17
+#define D0F0xBC_xE03002E4_SmuScPsoDaug_WIDTH                    1
+#define D0F0xBC_xE03002E4_SmuScPsoDaug_MASK                     0x20000
+#define D0F0xBC_xE03002E4_Reserved_31_18_OFFSET                 18
+#define D0F0xBC_xE03002E4_Reserved_31_18_WIDTH                  14
+#define D0F0xBC_xE03002E4_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xBC_xE03002E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            SmuCb0PsoDaug:1 ; ///<
+    UINT32                                            SmuCb1PsoDaug:1 ; ///<
+    UINT32                                            SmuDb0PsoDaug:1 ; ///<
+    UINT32                                            SmuDb1PsoDaug:1 ; ///<
+    UINT32                                             SmuPaPsoDaug:1 ; ///<
+    UINT32                                            SmuSpmPsoDaug:1 ; ///<
+    UINT32                                            SmuSpsPsoDaug:1 ; ///<
+    UINT32                                            SmuSqbPsoDaug:1 ; ///<
+    UINT32                                            SmuSxmPsoDaug:1 ; ///<
+    UINT32                                           SmuSxs0PsoDaug:1 ; ///<
+    UINT32                                           SmuSxs1PsoDaug:1 ; ///<
+    UINT32                                            SmuXbrPsoDaug:1 ; ///<
+    UINT32                                            SmuGdsPsoDaug:1 ; ///<
+    UINT32                                            SmuVgtPsoDaug:1 ; ///<
+    UINT32                                            SmuSqaPsoDaug:1 ; ///<
+    UINT32                                            SmuSqcPsoDaug:1 ; ///<
+    UINT32                                             SmuTcPsoDaug:1 ; ///<
+    UINT32                                             SmuScPsoDaug:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002E4_STRUCT;
+
+// **** D0F0xBC_xE03002F0 Register Definition ****
+// Address
+#define D0F0xBC_xE03002F0_ADDRESS                               0xe03002f0
+
+// Type
+#define D0F0xBC_xE03002F0_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_OFFSET                 0
+#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_MASK                   0x1
+#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_OFFSET                 1
+#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_MASK                   0x2
+#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_OFFSET                 2
+#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_MASK                   0x4
+#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_OFFSET                  3
+#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_MASK                    0x8
+#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_OFFSET                  4
+#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_MASK                    0x10
+#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_OFFSET                 5
+#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_MASK                   0x20
+#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_OFFSET                 6
+#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_MASK                   0x40
+#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_OFFSET                 7
+#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_MASK                   0x80
+#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_OFFSET                  8
+#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_MASK                    0x100
+#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_OFFSET                  9
+#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_MASK                    0x200
+#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_OFFSET                 10
+#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_MASK                   0x400
+#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_OFFSET                 11
+#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_MASK                   0x800
+#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_OFFSET                 12
+#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_MASK                   0x1000
+#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_OFFSET                  13
+#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_MASK                    0x2000
+#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_OFFSET                  14
+#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_MASK                    0x4000
+#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_OFFSET                 15
+#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_MASK                   0x8000
+#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_OFFSET                 16
+#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_MASK                   0x10000
+#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_OFFSET                 17
+#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_MASK                   0x20000
+#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_OFFSET                  18
+#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_MASK                    0x40000
+#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_OFFSET                  19
+#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_MASK                    0x80000
+#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_OFFSET                 20
+#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_MASK                   0x100000
+#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_OFFSET                 21
+#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_MASK                   0x200000
+#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_OFFSET                 22
+#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_MASK                   0x400000
+#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_OFFSET                  23
+#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_MASK                    0x800000
+#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_OFFSET                  24
+#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_MASK                    0x1000000
+#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_OFFSET                 25
+#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_MASK                   0x2000000
+#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_OFFSET                 26
+#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_MASK                   0x4000000
+#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_OFFSET                 27
+#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_MASK                   0x8000000
+#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_OFFSET                  28
+#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_MASK                    0x10000000
+#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_OFFSET                  29
+#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_MASK                    0x20000000
+#define D0F0xBC_xE03002F0_Reserved_31_30_OFFSET                 30
+#define D0F0xBC_xE03002F0_Reserved_31_30_WIDTH                  2
+#define D0F0xBC_xE03002F0_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xBC_xE03002F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SmuTatd0P1IsoN:1 ; ///<
+    UINT32                                           SmuSp000P1IsoN:1 ; ///<
+    UINT32                                           SmuSp002P1IsoN:1 ; ///<
+    UINT32                                            SmuLds0P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp0P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd1P1IsoN:1 ; ///<
+    UINT32                                           SmuSp010P1IsoN:1 ; ///<
+    UINT32                                           SmuSp012P1IsoN:1 ; ///<
+    UINT32                                            SmuLds1P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp1P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd2P1IsoN:1 ; ///<
+    UINT32                                           SmuSp020P1IsoN:1 ; ///<
+    UINT32                                           SmuSp022P1IsoN:1 ; ///<
+    UINT32                                            SmuLds2P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp2P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd3P1IsoN:1 ; ///<
+    UINT32                                           SmuSp030P1IsoN:1 ; ///<
+    UINT32                                           SmuSp032P1IsoN:1 ; ///<
+    UINT32                                            SmuLds3P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp3P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd4P1IsoN:1 ; ///<
+    UINT32                                           SmuSp040P1IsoN:1 ; ///<
+    UINT32                                           SmuSp042P1IsoN:1 ; ///<
+    UINT32                                            SmuLds4P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp4P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd5P1IsoN:1 ; ///<
+    UINT32                                           SmuSp050P1IsoN:1 ; ///<
+    UINT32                                           SmuSp052P1IsoN:1 ; ///<
+    UINT32                                            SmuLds5P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp5P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002F0_STRUCT;
+
+// **** D0F0xBC_xE03002F4 Register Definition ****
+// Address
+#define D0F0xBC_xE03002F4_ADDRESS                               0xe03002f4
+
+// Type
+#define D0F0xBC_xE03002F4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002F4_SmuCb0IsoN_OFFSET                     0
+#define D0F0xBC_xE03002F4_SmuCb0IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuCb0IsoN_MASK                       0x1
+#define D0F0xBC_xE03002F4_SmuCb1IsoN_OFFSET                     1
+#define D0F0xBC_xE03002F4_SmuCb1IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuCb1IsoN_MASK                       0x2
+#define D0F0xBC_xE03002F4_SmuDb0IsoN_OFFSET                     2
+#define D0F0xBC_xE03002F4_SmuDb0IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuDb0IsoN_MASK                       0x4
+#define D0F0xBC_xE03002F4_SmuDb1IsoN_OFFSET                     3
+#define D0F0xBC_xE03002F4_SmuDb1IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuDb1IsoN_MASK                       0x8
+#define D0F0xBC_xE03002F4_SmuPaIsoN_OFFSET                      4
+#define D0F0xBC_xE03002F4_SmuPaIsoN_WIDTH                       1
+#define D0F0xBC_xE03002F4_SmuPaIsoN_MASK                        0x10
+#define D0F0xBC_xE03002F4_SmuSpmIsoN_OFFSET                     5
+#define D0F0xBC_xE03002F4_SmuSpmIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSpmIsoN_MASK                       0x20
+#define D0F0xBC_xE03002F4_SmuSpsIsoN_OFFSET                     6
+#define D0F0xBC_xE03002F4_SmuSpsIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSpsIsoN_MASK                       0x40
+#define D0F0xBC_xE03002F4_SmuSqbIsoN_OFFSET                     7
+#define D0F0xBC_xE03002F4_SmuSqbIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSqbIsoN_MASK                       0x80
+#define D0F0xBC_xE03002F4_SmuSxmIsoN_OFFSET                     8
+#define D0F0xBC_xE03002F4_SmuSxmIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSxmIsoN_MASK                       0x100
+#define D0F0xBC_xE03002F4_SmuSxs0IsoN_OFFSET                    9
+#define D0F0xBC_xE03002F4_SmuSxs0IsoN_WIDTH                     1
+#define D0F0xBC_xE03002F4_SmuSxs0IsoN_MASK                      0x200
+#define D0F0xBC_xE03002F4_SmuSxs1IsoN_OFFSET                    10
+#define D0F0xBC_xE03002F4_SmuSxs1IsoN_WIDTH                     1
+#define D0F0xBC_xE03002F4_SmuSxs1IsoN_MASK                      0x400
+#define D0F0xBC_xE03002F4_SmuXbrIsoN_OFFSET                     11
+#define D0F0xBC_xE03002F4_SmuXbrIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuXbrIsoN_MASK                       0x800
+#define D0F0xBC_xE03002F4_SmuGdsIsoN_OFFSET                     12
+#define D0F0xBC_xE03002F4_SmuGdsIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuGdsIsoN_MASK                       0x1000
+#define D0F0xBC_xE03002F4_SmuVgtIsoN_OFFSET                     13
+#define D0F0xBC_xE03002F4_SmuVgtIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuVgtIsoN_MASK                       0x2000
+#define D0F0xBC_xE03002F4_SmuSqaIsoN_OFFSET                     14
+#define D0F0xBC_xE03002F4_SmuSqaIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSqaIsoN_MASK                       0x4000
+#define D0F0xBC_xE03002F4_SmuSqcIsoN_OFFSET                     15
+#define D0F0xBC_xE03002F4_SmuSqcIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSqcIsoN_MASK                       0x8000
+#define D0F0xBC_xE03002F4_SmuTcIsoN_OFFSET                      16
+#define D0F0xBC_xE03002F4_SmuTcIsoN_WIDTH                       1
+#define D0F0xBC_xE03002F4_SmuTcIsoN_MASK                        0x10000
+#define D0F0xBC_xE03002F4_SmuScIsoN_OFFSET                      17
+#define D0F0xBC_xE03002F4_SmuScIsoN_WIDTH                       1
+#define D0F0xBC_xE03002F4_SmuScIsoN_MASK                        0x20000
+#define D0F0xBC_xE03002F4_Reserved_31_18_OFFSET                 18
+#define D0F0xBC_xE03002F4_Reserved_31_18_WIDTH                  14
+#define D0F0xBC_xE03002F4_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xBC_xE03002F4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               SmuCb0IsoN:1 ; ///<
+    UINT32                                               SmuCb1IsoN:1 ; ///<
+    UINT32                                               SmuDb0IsoN:1 ; ///<
+    UINT32                                               SmuDb1IsoN:1 ; ///<
+    UINT32                                                SmuPaIsoN:1 ; ///<
+    UINT32                                               SmuSpmIsoN:1 ; ///<
+    UINT32                                               SmuSpsIsoN:1 ; ///<
+    UINT32                                               SmuSqbIsoN:1 ; ///<
+    UINT32                                               SmuSxmIsoN:1 ; ///<
+    UINT32                                              SmuSxs0IsoN:1 ; ///<
+    UINT32                                              SmuSxs1IsoN:1 ; ///<
+    UINT32                                               SmuXbrIsoN:1 ; ///<
+    UINT32                                               SmuGdsIsoN:1 ; ///<
+    UINT32                                               SmuVgtIsoN:1 ; ///<
+    UINT32                                               SmuSqaIsoN:1 ; ///<
+    UINT32                                               SmuSqcIsoN:1 ; ///<
+    UINT32                                                SmuTcIsoN:1 ; ///<
+    UINT32                                                SmuScIsoN:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002F4_STRUCT;
+
+// **** D0F0xBC_xE03002F8 Register Definition ****
+// Address
+#define D0F0xBC_xE03002F8_ADDRESS                               0xe03002f8
+
+// Type
+#define D0F0xBC_xE03002F8_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_OFFSET                 0
+#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_MASK                   0x1
+#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_OFFSET                 1
+#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_MASK                   0x2
+#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_OFFSET                 2
+#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_MASK                   0x4
+#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_OFFSET                  3
+#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_MASK                    0x8
+#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_OFFSET                  4
+#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_MASK                    0x10
+#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_OFFSET                 5
+#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_MASK                   0x20
+#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_OFFSET                 6
+#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_MASK                   0x40
+#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_OFFSET                 7
+#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_MASK                   0x80
+#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_OFFSET                  8
+#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_MASK                    0x100
+#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_OFFSET                  9
+#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_MASK                    0x200
+#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_OFFSET                 10
+#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_MASK                   0x400
+#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_OFFSET                 11
+#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_MASK                   0x800
+#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_OFFSET                 12
+#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_MASK                   0x1000
+#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_OFFSET                  13
+#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_MASK                    0x2000
+#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_OFFSET                  14
+#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_MASK                    0x4000
+#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_OFFSET                 15
+#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_MASK                   0x8000
+#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_OFFSET                 16
+#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_MASK                   0x10000
+#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_OFFSET                 17
+#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_MASK                   0x20000
+#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_OFFSET                  18
+#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_MASK                    0x40000
+#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_OFFSET                  19
+#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_MASK                    0x80000
+#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_OFFSET                 20
+#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_MASK                   0x100000
+#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_OFFSET                 21
+#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_MASK                   0x200000
+#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_OFFSET                 22
+#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_MASK                   0x400000
+#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_OFFSET                  23
+#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_MASK                    0x800000
+#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_OFFSET                  24
+#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_MASK                    0x1000000
+#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_OFFSET                 25
+#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_MASK                   0x2000000
+#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_OFFSET                 26
+#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_MASK                   0x4000000
+#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_OFFSET                 27
+#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_MASK                   0x8000000
+#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_OFFSET                  28
+#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_MASK                    0x10000000
+#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_OFFSET                  29
+#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_MASK                    0x20000000
+#define D0F0xBC_xE03002F8_Reserved_31_30_OFFSET                 30
+#define D0F0xBC_xE03002F8_Reserved_31_30_WIDTH                  2
+#define D0F0xBC_xE03002F8_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xBC_xE03002F8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SmuTatd0P2IsoN:1 ; ///<
+    UINT32                                           SmuSp000P2IsoN:1 ; ///<
+    UINT32                                           SmuSp002P2IsoN:1 ; ///<
+    UINT32                                            SmuLds0P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp0P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd1P2IsoN:1 ; ///<
+    UINT32                                           SmuSp010P2IsoN:1 ; ///<
+    UINT32                                           SmuSp012P2IsoN:1 ; ///<
+    UINT32                                            SmuLds1P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp1P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd2P2IsoN:1 ; ///<
+    UINT32                                           SmuSp020P2IsoN:1 ; ///<
+    UINT32                                           SmuSp022P2IsoN:1 ; ///<
+    UINT32                                            SmuLds2P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp2P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd3P2IsoN:1 ; ///<
+    UINT32                                           SmuSp030P2IsoN:1 ; ///<
+    UINT32                                           SmuSp032P2IsoN:1 ; ///<
+    UINT32                                            SmuLds3P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp3P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd4P2IsoN:1 ; ///<
+    UINT32                                           SmuSp040P2IsoN:1 ; ///<
+    UINT32                                           SmuSp042P2IsoN:1 ; ///<
+    UINT32                                            SmuLds4P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp4P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd5P2IsoN:1 ; ///<
+    UINT32                                           SmuSp050P2IsoN:1 ; ///<
+    UINT32                                           SmuSp052P2IsoN:1 ; ///<
+    UINT32                                            SmuLds5P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp5P2IsoN:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002F8_STRUCT;
+
+// **** D0F0xBC_xE03002FC Register Definition ****
+// Address
+#define D0F0xBC_xE03002FC_ADDRESS                               0xe03002fc
+
+// Type
+#define D0F0xBC_xE03002FC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_OFFSET              0
+#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_MASK                0x1
+#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_OFFSET              1
+#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_MASK                0x2
+#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_OFFSET              2
+#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_MASK                0x4
+#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_OFFSET               3
+#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_MASK                 0x8
+#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_OFFSET               4
+#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_MASK                 0x10
+#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_OFFSET              5
+#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_MASK                0x20
+#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_OFFSET              6
+#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_MASK                0x40
+#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_OFFSET              7
+#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_MASK                0x80
+#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_OFFSET               8
+#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_MASK                 0x100
+#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_OFFSET               9
+#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_MASK                 0x200
+#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_OFFSET              10
+#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_MASK                0x400
+#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_OFFSET              11
+#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_MASK                0x800
+#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_OFFSET              12
+#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_MASK                0x1000
+#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_OFFSET               13
+#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_MASK                 0x2000
+#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_OFFSET               14
+#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_MASK                 0x4000
+#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_OFFSET              15
+#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_MASK                0x8000
+#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_OFFSET              16
+#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_MASK                0x10000
+#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_OFFSET              17
+#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_MASK                0x20000
+#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_OFFSET               18
+#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_MASK                 0x40000
+#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_OFFSET               19
+#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_MASK                 0x80000
+#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_OFFSET              20
+#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_MASK                0x100000
+#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_OFFSET              21
+#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_MASK                0x200000
+#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_OFFSET              22
+#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_MASK                0x400000
+#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_OFFSET               23
+#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_MASK                 0x800000
+#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_OFFSET               24
+#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_MASK                 0x1000000
+#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_OFFSET              25
+#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_MASK                0x2000000
+#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_OFFSET              26
+#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_MASK                0x4000000
+#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_OFFSET              27
+#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_MASK                0x8000000
+#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_OFFSET               28
+#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_MASK                 0x10000000
+#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_OFFSET               29
+#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_MASK                 0x20000000
+#define D0F0xBC_xE03002FC_Reserved_31_30_OFFSET                 30
+#define D0F0xBC_xE03002FC_Reserved_31_30_WIDTH                  2
+#define D0F0xBC_xE03002FC_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xBC_xE03002FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SmuTatd0P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp000P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp002P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds0P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp0P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd1P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp010P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp012P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds1P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp1P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd2P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp020P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp022P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds2P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp2P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd3P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp030P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp032P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds3P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp3P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd4P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp040P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp042P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds4P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp4P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd5P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp050P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp052P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds5P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp5P2PsoDaug:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002FC_STRUCT;
+
+// **** D0F0xBC_xE0300320 Register Definition ****
+// Address
+#define D0F0xBC_xE0300320_ADDRESS                               0xe0300320
+
+// Type
+#define D0F0xBC_xE0300320_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300320_PgdPgfsmClockEn_OFFSET                0
+#define D0F0xBC_xE0300320_PgdPgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300320_PgdPgfsmClockEn_MASK                  0x1
+#define D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET              1
+#define D0F0xBC_xE0300320_IommuPgfsmClockEn_WIDTH               1
+#define D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK                0x2
+#define D0F0xBC_xE0300320_Reserved_31_2_OFFSET                  2
+#define D0F0xBC_xE0300320_Reserved_31_2_WIDTH                   30
+#define D0F0xBC_xE0300320_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xBC_xE0300320
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          PgdPgfsmClockEn:1 ; ///<
+    UINT32                                        IommuPgfsmClockEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300320_STRUCT;
+
+// **** D0F0xBC_xE0300324 Register Definition ****
+// Address
+#define D0F0xBC_xE0300324_ADDRESS                               0xe0300324
+
+// Type
+#define D0F0xBC_xE0300324_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300324_VcePgfsmClockEn_OFFSET                0
+#define D0F0xBC_xE0300324_VcePgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300324_VcePgfsmClockEn_MASK                  0x1
+#define D0F0xBC_xE0300324_UvdPgfsmClockEn_OFFSET                1
+#define D0F0xBC_xE0300324_UvdPgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK                  0x2
+#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET                2
+#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK                  0x4
+#define D0F0xBC_xE0300324_Reserved_31_3_OFFSET                  3
+#define D0F0xBC_xE0300324_Reserved_31_3_WIDTH                   29
+#define D0F0xBC_xE0300324_Reserved_31_3_MASK                    0xfffffff8
+
+/// D0F0xBC_xE0300324
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          VcePgfsmClockEn:1 ; ///<
+    UINT32                                          UvdPgfsmClockEn:1 ; ///<
+    UINT32                                          Dc2PgfsmClockEn:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300324_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        Simd0PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd1PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd2PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd3PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd4PgfsmClockEn:1 ; ///<
+    UINT32        ex1009_0:1;
+    UINT32        ex1009_1:1;
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1009_STRUCT;
+
+// **** D0F0xBC_xFF000000 Register Definition ****
+// Address
+#define D0F0xBC_xFF000000_ADDRESS                               0xff000000
+
+// Type
+#define D0F0xBC_xFF000000_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xFF000000_GckFuseProg_OFFSET                    0
+#define D0F0xBC_xFF000000_GckFuseProg_WIDTH                     1
+#define D0F0xBC_xFF000000_GckFuseProg_MASK                      0x1
+#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET         1
+#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH          6
+#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_MASK           0x7e
+#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_OFFSET             7
+#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_WIDTH              6
+#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_MASK               0x1f80
+#define D0F0xBC_xFF000000_MainPllRefAdj_OFFSET                  13
+#define D0F0xBC_xFF000000_MainPllRefAdj_WIDTH                   5
+#define D0F0xBC_xFF000000_MainPllRefAdj_MASK                    0x3e000
+#define D0F0xBC_xFF000000_PllMiscFuseCtl_OFFSET                 18
+#define D0F0xBC_xFF000000_PllMiscFuseCtl_WIDTH                  4
+#define D0F0xBC_xFF000000_PllMiscFuseCtl_MASK                   0x3c0000
+#define D0F0xBC_xFF000000_Reserved_31_22_OFFSET                 22
+#define D0F0xBC_xFF000000_Reserved_31_22_WIDTH                  10
+#define D0F0xBC_xFF000000_Reserved_31_22_MASK                   0xffc00000
+
+/// D0F0xBC_xFF000000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              GckFuseProg:1 ; ///<
+    UINT32                                   MainPllOpFreqIdStartup:6 ; ///<
+    UINT32                                       MainPllOpFreqIdMax:6 ; ///<
+    UINT32                                            MainPllRefAdj:5 ; ///<
+    UINT32                                           PllMiscFuseCtl:4 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xFF000000_STRUCT;
+
+// **** D0F0xE4_WRAP_0046 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0046_ADDRESS                               0x46
+
+// Type
+#define D0F0xE4_WRAP_0046_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0046_SubsystemVendorID_OFFSET              0
+#define D0F0xE4_WRAP_0046_SubsystemVendorID_WIDTH               16
+#define D0F0xE4_WRAP_0046_SubsystemVendorID_MASK                0xffff
+#define D0F0xE4_WRAP_0046_SubsystemID_OFFSET                    16
+#define D0F0xE4_WRAP_0046_SubsystemID_WIDTH                     16
+#define D0F0xE4_WRAP_0046_SubsystemID_MASK                      0xffff0000
+
+/// D0F0xE4_WRAP_0046
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorID:16; ///<
+    UINT32                                              SubsystemID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0046_STRUCT;
+
+// **** D0F0xE4_WRAP_0080 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0080_ADDRESS                               0x80
+
+// Type
+#define D0F0xE4_WRAP_0080_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET             0
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH              4
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK               0xf
+#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET                  4
+#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH                   28
+#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK                    0xfffffff0
+
+/// D0F0xE4_WRAP_0080
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       StrapBifLinkConfig:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0080_STRUCT;
+
+// **** D0F0xE4_WRAP_0800 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0800_ADDRESS                               0x800
+
+// Type
+#define D0F0xE4_WRAP_0800_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET                   0
+#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH                    1
+#define D0F0xE4_WRAP_0800_HoldTraining_MASK                     0x1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_WRAP_0800
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HoldTraining:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0800_STRUCT;
+
+// **** D0F0xE4_WRAP_0803 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0803_ADDRESS                               0x803
+
+// Type
+#define D0F0xE4_WRAP_0803_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0803
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0803_STRUCT;
+
+// **** D0F0xE4_WRAP_0903 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0903_ADDRESS                               0x903
+
+// Type
+#define D0F0xE4_WRAP_0903_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0903
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0903_STRUCT;
+
+
+// **** D0F0xE4_WRAP_8011 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8011_ADDRESS                               0x8011
+
+// Type
+#define D0F0xE4_WRAP_8011_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET            0
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH             6
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK              0x3f
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET              6
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH               1
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK                0x40
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET             7
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH              1
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK               0x80
+#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET                  8
+#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH                   1
+#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK                    0x100
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET            9
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK              0x200
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET           10
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK             0xfc00
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET               16
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH                1
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK                 0x10000
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET           17
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK             0x7e0000
+#define D0F0xE4_WRAP_8011_DebugBusClkEnable_OFFSET              23
+#define D0F0xE4_WRAP_8011_DebugBusClkEnable_WIDTH               1
+#define D0F0xE4_WRAP_8011_DebugBusClkEnable_MASK                0x800000
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET            24
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK              0x1000000
+#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_OFFSET            25
+#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_WIDTH             1
+#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_MASK              0x2000000
+#define D0F0xE4_WRAP_8011_Reserved_30_26_OFFSET                 26
+#define D0F0xE4_WRAP_8011_Reserved_30_26_WIDTH                  5
+#define D0F0xE4_WRAP_8011_Reserved_30_26_MASK                   0x7c000000
+#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET                  31
+#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH                   1
+#define D0F0xE4_WRAP_8011_StrapBifValid_MASK                    0x80000000
+
+/// D0F0xE4_WRAP_8011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      TxclkDynGateLatency:6 ; ///<
+    UINT32                                        TxclkPermGateEven:1 ; ///<
+    UINT32                                       TxclkDynGateEnable:1 ; ///<
+    UINT32                                            TxclkPermStop:1 ; ///<
+    UINT32                                      TxclkRegsGateEnable:1 ; ///<
+    UINT32                                     TxclkRegsGateLatency:6 ; ///<
+    UINT32                                         RcvrDetClkEnable:1 ; ///<
+    UINT32                                     TxclkPermGateLatency:6 ; ///<
+    UINT32                                        DebugBusClkEnable:1 ; ///<
+    UINT32                                      TxclkLcntGateEnable:1 ; ///<
+    UINT32                                      DdiDualLinkOverride:1 ; ///<
+    UINT32                                           Reserved_30_26:5 ; ///<
+    UINT32                                            StrapBifValid:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8011_STRUCT;
+
+// **** D0F0xE4_WRAP_8016 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8016_ADDRESS                               0x8016
+
+// Type
+#define D0F0xE4_WRAP_8016_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET                0
+#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH                 6
+#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK                  0x3f
+#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET                  6
+#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH                   10
+#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK                    0xffc0
+#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET             16
+#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH              6
+#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK               0x3f0000
+#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET                   22
+#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH                    1
+#define D0F0xE4_WRAP_8016_LclkGateFree_MASK                     0x400000
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET              23
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH               1
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK                0x800000
+#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET                 24
+#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH                  8
+#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK                   0xff000000
+
+/// D0F0xE4_WRAP_8016
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CalibAckLatency:6 ; ///<
+    UINT32                                            Reserved_15_6:10; ///<
+    UINT32                                       LclkDynGateLatency:6 ; ///<
+    UINT32                                             LclkGateFree:1 ; ///<
+    UINT32                                        LclkDynGateEnable:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8016_STRUCT;
+
+// **** D0F0xE4_WRAP_8021 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8021_ADDRESS                               0x8021
+
+// Type
+#define D0F0xE4_WRAP_8021_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8021_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8021_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8021_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8021_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8021_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8021_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8021_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8021_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8021_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8021_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8021
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8021_STRUCT;
+
+// **** D0F0xE4_WRAP_8022 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8022_ADDRESS                               0x8022
+
+// Type
+#define D0F0xE4_WRAP_8022_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8022_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8022_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8022_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8022_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8022_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8022_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8022_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8022_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8022_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8022_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8022
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8022_STRUCT;
+
+// **** D0F0xE4_WRAP_8023 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8023_ADDRESS                               0x8023
+
+// Type
+#define D0F0xE4_WRAP_8023_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET                     0
+#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH                      16
+#define D0F0xE4_WRAP_8023_LaneEnable_MASK                       0xffff
+#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_WRAP_8023
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               LaneEnable:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8023_STRUCT;
+
+// **** D0F0xE4_WRAP_8031 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8031_ADDRESS                               0x8031
+
+// Type
+#define D0F0xE4_WRAP_8031_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET                 0
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH                  10
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK                   0x3ff
+#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET                 10
+#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH                  6
+#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK                   0xfc00
+#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET                     16
+#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH                      1
+#define D0F0xE4_WRAP_8031_LnCntValid_MASK                       0x10000
+#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET                 17
+#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH                  15
+#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xE4_WRAP_8031
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LnCntBandwidth:10; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                               LnCntValid:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8031_STRUCT;
+
+// **** D0F0xE4_WRAP_8040 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8040_ADDRESS                               0x8040
+
+// Type
+#define D0F0xE4_WRAP_8040_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET                       0
+#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH                        1
+#define D0F0xE4_WRAP_8040_OwnSlice_MASK                         0x1
+#define D0F0xE4_WRAP_8040_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_WRAP_8040_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_WRAP_8040_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_WRAP_8040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 OwnSlice:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8040_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+// **** D0F0xE4_WRAP_8060 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8060_ADDRESS                               0x8060
+
+// Type
+#define D0F0xE4_WRAP_8060_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET                    0
+#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH                     1
+#define D0F0xE4_WRAP_8060_Reconfigure_MASK                      0x1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET                  2
+#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH                   1
+#define D0F0xE4_WRAP_8060_ResetComplete_MASK                    0x4
+#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET                  3
+#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH                   13
+#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK                    0xfff8
+#define D0F0xE4_WRAP_8060_Bif0GlobalReset_OFFSET                16
+#define D0F0xE4_WRAP_8060_Bif0GlobalReset_WIDTH                 1
+#define D0F0xE4_WRAP_8060_Bif0GlobalReset_MASK                  0x10000
+#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_OFFSET           17
+#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_WIDTH            1
+#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_MASK             0x20000
+#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET                 18
+#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH                  14
+#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xE4_WRAP_8060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reconfigure:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                            ResetComplete:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          Bif0GlobalReset:1 ; ///<
+    UINT32                                     Bif0CalibrationReset:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8060_STRUCT;
+
+// **** D0F0xE4_WRAP_8062 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8062_ADDRESS                               0x8062
+
+// Type
+#define D0F0xE4_WRAP_8062_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET                  0
+#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH                   1
+#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK                    0x1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET                    2
+#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH                     3
+#define D0F0xE4_WRAP_8062_ResetPeriod_MASK                      0x1c
+#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET                   5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH                    5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK                     0x3e0
+#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET                    10
+#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH                     1
+#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK                      0x400
+#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET                 11
+#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH                  1
+#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK                   0x800
+#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET                 12
+#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH                  20
+#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK                   0xfffff000
+
+/// D0F0xE4_WRAP_8062
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ReconfigureEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              ResetPeriod:3 ; ///<
+    UINT32                                             Reserved_9_5:5 ; ///<
+    UINT32                                              BlockOnIdle:1 ; ///<
+    UINT32                                           ConfigXferMode:1 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8062_STRUCT;
+
+// **** D0F0xE4_WRAP_80F0 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F0_ADDRESS                               0x80f0
+
+// Type
+#define D0F0xE4_WRAP_80F0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET                   0
+#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH                    32
+#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK                     0xffffffff
+
+/// D0F0xE4_WRAP_80F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             MicroSeconds:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F0_STRUCT;
+
+// **** D0F0xE4_WRAP_80F1 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F1_ADDRESS                               0x80f1
+
+// Type
+#define D0F0xE4_WRAP_80F1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET                      0
+#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH                       8
+#define D0F0xE4_WRAP_80F1_ClockRate_MASK                        0xff
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET                  8
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH                   24
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK                    0xffffff00
+
+/// D0F0xE4_WRAP_80F1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ClockRate:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F1_STRUCT;
+
+// **** D0F0xE4_WRAP_FFF1 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_FFF1_ADDRESS                               0xfff1
+
+// Type
+#define D0F0xE4_WRAP_FFF1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_FFF1_Reserved_0_0_OFFSET                   0
+#define D0F0xE4_WRAP_FFF1_Reserved_0_0_WIDTH                    1
+#define D0F0xE4_WRAP_FFF1_Reserved_0_0_MASK                     0x1
+#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_OFFSET               1
+#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_WIDTH                4
+#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_MASK                 0x1e
+#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_OFFSET       5
+#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_WIDTH        1
+#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_MASK         0x20
+#define D0F0xE4_WRAP_FFF1_LcSupportGen2_OFFSET                  6
+#define D0F0xE4_WRAP_FFF1_LcSupportGen2_WIDTH                   1
+#define D0F0xE4_WRAP_FFF1_LcSupportGen2_MASK                    0x40
+#define D0F0xE4_WRAP_FFF1_ROSupportGen2_OFFSET                  7
+#define D0F0xE4_WRAP_FFF1_ROSupportGen2_WIDTH                   1
+#define D0F0xE4_WRAP_FFF1_ROSupportGen2_MASK                    0x80
+#define D0F0xE4_WRAP_FFF1_Reserved_31_8_OFFSET                  8
+#define D0F0xE4_WRAP_FFF1_Reserved_31_8_WIDTH                   24
+#define D0F0xE4_WRAP_FFF1_Reserved_31_8_MASK                    0xffffff00
+
+/// D0F0xE4_WRAP_FFF1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                         PcieSpareGppFch2:4 ; ///<
+    UINT32                                 CoreBphyRstPwrSnifferDis:1 ; ///<
+    UINT32                                            LcSupportGen2:1 ; ///<
+    UINT32                                            ROSupportGen2:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_FFF1_STRUCT;
+
+// **** D0F0xE4_PIF_0010 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0010_ADDRESS                                0x10
+
+// Type
+#define D0F0xE4_PIF_0010_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET                    0
+#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH                     4
+#define D0F0xE4_PIF_0010_Reserved_3_0_MASK                      0xf
+#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET                  4
+#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH                   1
+#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK                    0x10
+#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET                    5
+#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH                     1
+#define D0F0xE4_PIF_0010_Reserved_5_5_MASK                      0x20
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET           6
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH            1
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK             0x40
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET               7
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH                1
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK                 0x80
+#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET                   8
+#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH                    9
+#define D0F0xE4_PIF_0010_Reserved_16_8_MASK                     0x1ff00
+#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET                     17
+#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK                       0xe0000
+#define D0F0xE4_PIF_0010_Reserved_31_20_OFFSET                  20
+#define D0F0xE4_PIF_0010_Reserved_31_20_WIDTH                   12
+#define D0F0xE4_PIF_0010_Reserved_31_20_MASK                    0xfff00000
+
+/// D0F0xE4_PIF_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                           EiDetCycleMode:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                    RxDetectFifoResetMode:1 ; ///<
+    UINT32                                        RxDetectTxPwrMode:1 ; ///<
+    UINT32                                            Reserved_16_8:9 ; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0010_STRUCT;
+
+// **** D0F0xE4_PIF_0011 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0011_ADDRESS                                0x11
+
+// Type
+#define D0F0xE4_PIF_0011_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0011_X2Lane10_OFFSET                        0
+#define D0F0xE4_PIF_0011_X2Lane10_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane10_MASK                          0x1
+#define D0F0xE4_PIF_0011_X2Lane32_OFFSET                        1
+#define D0F0xE4_PIF_0011_X2Lane32_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane32_MASK                          0x2
+#define D0F0xE4_PIF_0011_X2Lane54_OFFSET                        2
+#define D0F0xE4_PIF_0011_X2Lane54_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane54_MASK                          0x4
+#define D0F0xE4_PIF_0011_X2Lane76_OFFSET                        3
+#define D0F0xE4_PIF_0011_X2Lane76_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane76_MASK                          0x8
+#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET                    4
+#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH                     4
+#define D0F0xE4_PIF_0011_Reserved_7_4_MASK                      0xf0
+#define D0F0xE4_PIF_0011_X4Lane30_OFFSET                        8
+#define D0F0xE4_PIF_0011_X4Lane30_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane30_MASK                          0x100
+#define D0F0xE4_PIF_0011_X4Lane74_OFFSET                        9
+#define D0F0xE4_PIF_0011_X4Lane74_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane74_MASK                          0x200
+#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET                  10
+#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH                   2
+#define D0F0xE4_PIF_0011_Reserved_11_10_MASK                    0xc00
+#define D0F0xE4_PIF_0011_X4Lane52_OFFSET                        12
+#define D0F0xE4_PIF_0011_X4Lane52_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane52_MASK                          0x1000
+#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0011_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0011_X8Lane70_OFFSET                        16
+#define D0F0xE4_PIF_0011_X8Lane70_WIDTH                         1
+#define D0F0xE4_PIF_0011_X8Lane70_MASK                          0x10000
+#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET                  17
+#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH                   8
+#define D0F0xE4_PIF_0011_Reserved_24_17_MASK                    0x1fe0000
+#define D0F0xE4_PIF_0011_MultiPif_OFFSET                        25
+#define D0F0xE4_PIF_0011_MultiPif_WIDTH                         1
+#define D0F0xE4_PIF_0011_MultiPif_MASK                          0x2000000
+#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET                  26
+#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH                   6
+#define D0F0xE4_PIF_0011_Reserved_31_26_MASK                    0xfc000000
+
+/// D0F0xE4_PIF_0011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 X2Lane10:1 ; ///<
+    UINT32                                                 X2Lane32:1 ; ///<
+    UINT32                                                 X2Lane54:1 ; ///<
+    UINT32                                                 X2Lane76:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                 X4Lane30:1 ; ///<
+    UINT32                                                 X4Lane74:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                                                 X4Lane52:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                 X8Lane70:1 ; ///<
+    UINT32                                           Reserved_24_17:8 ; ///<
+    UINT32                                                 MultiPif:1 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0011_STRUCT;
+
+// **** D0F0xE4_PIF_0012 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0012_ADDRESS                                0x12
+
+// Type
+#define D0F0xE4_PIF_0012_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0012_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0012_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0012_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0012_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0012_STRUCT;
+
+// **** D0F0xE4_PIF_0013 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0013_ADDRESS                                0x13
+
+// Type
+#define D0F0xE4_PIF_0013_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0013_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0013_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0013_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0013_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0013_STRUCT;
+
+// **** D0F0xE4_PIF_0015 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0015_ADDRESS                                0x15
+
+// Type
+#define D0F0xE4_PIF_0015_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET                   0
+#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK                     0x1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET                   1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK                     0x2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET                   2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK                     0x4
+#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET                   3
+#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK                     0x8
+#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET                   4
+#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK                     0x10
+#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET                   5
+#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK                     0x20
+#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET                   6
+#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK                     0x40
+#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET                   7
+#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK                     0x80
+#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PIF_0015_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PIF_0015
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            TxPhyStatus00:1 ; ///<
+    UINT32                                            TxPhyStatus01:1 ; ///<
+    UINT32                                            TxPhyStatus02:1 ; ///<
+    UINT32                                            TxPhyStatus03:1 ; ///<
+    UINT32                                            TxPhyStatus04:1 ; ///<
+    UINT32                                            TxPhyStatus05:1 ; ///<
+    UINT32                                            TxPhyStatus06:1 ; ///<
+    UINT32                                            TxPhyStatus07:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0015_STRUCT;
+
+// **** D0F0xE4_CORE_0002 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0002_ADDRESS                               0x2
+
+// Type
+#define D0F0xE4_CORE_0002_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET                     0
+#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH                      1
+#define D0F0xE4_CORE_0002_HwDebug_0__MASK                       0x1
+#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_CORE_0002_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_CORE_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               HwDebug_0_:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0002_STRUCT;
+
+// **** D0F0xE4_CORE_0010 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0010_ADDRESS                               0x10
+
+// Type
+#define D0F0xE4_CORE_0010_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET                   0
+#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH                    1
+#define D0F0xE4_CORE_0010_HwInitWrLock_MASK                     0x1
+#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET                   1
+#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH                    8
+#define D0F0xE4_CORE_0010_Reserved_8_1_MASK                     0x1fe
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET                  9
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH                   1
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK                    0x200
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET             10
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH              3
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK               0x1c00
+#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET                 13
+#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH                  19
+#define D0F0xE4_CORE_0010_Reserved_31_13_MASK                   0xffffe000
+
+/// D0F0xE4_CORE_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                             Reserved_8_1:8 ; ///<
+    UINT32                                            UmiNpMemWrite:1 ; ///<
+    UINT32                                       RxSbAdjPayloadSize:3 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0010_STRUCT;
+
+// **** D0F0xE4_CORE_0011 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0011_ADDRESS                               0x11
+
+// Type
+#define D0F0xE4_CORE_0011_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET                  0
+#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH                   4
+#define D0F0xE4_CORE_0011_DynClkLatency_MASK                    0xf
+#define D0F0xE4_CORE_0011_Reserved_15_4_OFFSET                  4
+#define D0F0xE4_CORE_0011_Reserved_15_4_WIDTH                   12
+#define D0F0xE4_CORE_0011_Reserved_15_4_MASK                    0xfff0
+#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_OFFSET           16
+#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_WIDTH            1
+#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_MASK             0x10000
+#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_OFFSET           17
+#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_WIDTH            3
+#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_MASK             0xe0000
+#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_OFFSET       20
+#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_WIDTH        1
+#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_MASK         0x100000
+#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_OFFSET       21
+#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_WIDTH        3
+#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_MASK         0xe00000
+#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_OFFSET              24
+#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_WIDTH               1
+#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_MASK                0x1000000
+#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_OFFSET        25
+#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_WIDTH         1
+#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_MASK          0x2000000
+#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_OFFSET        26
+#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_WIDTH         1
+#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_MASK          0x4000000
+#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_OFFSET        27
+#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_WIDTH         3
+#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_MASK          0x38000000
+#define D0F0xE4_CORE_0011_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_CORE_0011_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_CORE_0011_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_CORE_0011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DynClkLatency:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                     CiMaxPayloadSizeMode:1 ; ///<
+    UINT32                                     CiPrivMaxPayloadSize:3 ; ///<
+    UINT32                                 CiMaxReadRequestSizeMode:1 ; ///<
+    UINT32                                 CiPrivMaxReadRequestSize:3 ; ///<
+    UINT32                                        CiMaxReadSafeMode:1 ; ///<
+    UINT32                                  CiExtendedTagEnOverride:1 ; ///<
+    UINT32                                  CiMaxCplPayloadSizeMode:1 ; ///<
+    UINT32                                  CiPrivMaxCplPayloadSize:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0011_STRUCT;
+
+// **** D0F0xE4_CORE_001C Register Definition ****
+// Address
+#define D0F0xE4_CORE_001C_ADDRESS                               0x1c
+
+// Type
+#define D0F0xE4_CORE_001C_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET              0
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH               1
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK                0x1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET                  1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK                    0x3e
+#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET                  6
+#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK                    0x7c0
+#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET                 11
+#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH                  21
+#define D0F0xE4_CORE_001C_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xE4_CORE_001C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxArbRoundRobinEn:1 ; ///<
+    UINT32                                            TxArbSlvLimit:5 ; ///<
+    UINT32                                            TxArbMstLimit:5 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_001C_STRUCT;
+
+// **** D0F0xE4_CORE_0020 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0020_ADDRESS                               0x20
+
+// Type
+#define D0F0xE4_CORE_0020_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0020_Reserved_7_0_OFFSET                   0
+#define D0F0xE4_CORE_0020_Reserved_7_0_WIDTH                    8
+#define D0F0xE4_CORE_0020_Reserved_7_0_MASK                     0xff
+#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET               8
+#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH                1
+#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK                 0x100
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET                9
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH                 1
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK                  0x200
+#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET                 10
+#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH                  22
+#define D0F0xE4_CORE_0020_Reserved_31_10_MASK                   0xfffffc00
+
+/// D0F0xE4_CORE_0020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                         CiSlvOrderingDis:1 ; ///<
+    UINT32                                          CiRcOrderingDis:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0020_STRUCT;
+
+// **** D0F0xE4_CORE_0040 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0040_ADDRESS                               0x40
+
+// Type
+#define D0F0xE4_CORE_0040_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET                  0
+#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH                   14
+#define D0F0xE4_CORE_0040_Reserved_13_0_MASK                    0x3fff
+#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET                  14
+#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH                   2
+#define D0F0xE4_CORE_0040_PElecIdleMode_MASK                    0xc000
+#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_CORE_0040_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_CORE_0040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_13_0:14; ///<
+    UINT32                                            PElecIdleMode:2 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0040_STRUCT;
+
+// **** D0F0xE4_CORE_00B0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00B0_ADDRESS                               0xb0
+
+// Type
+#define D0F0xE4_CORE_00B0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET                   0
+#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK                     0x3
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET                   2
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK                     0x4
+#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET                   3
+#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK                     0x18
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET                   5
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK                     0x20
+#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_CORE_00B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                             StrapF0MsiEn:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                             StrapF0AerEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00B0_STRUCT;
+
+// **** D0F0xE4_CORE_00C0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00C0_ADDRESS                               0xc0
+
+// Type
+#define D0F0xE4_CORE_00C0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET                  0
+#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH                   28
+#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK                    0xfffffff
+#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET                28
+#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH                 1
+#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK                  0x10000000
+#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET                29
+#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH                 1
+#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK                  0x20000000
+#define D0F0xE4_CORE_00C0_StrapFlrEn_OFFSET                     30
+#define D0F0xE4_CORE_00C0_StrapFlrEn_WIDTH                      1
+#define D0F0xE4_CORE_00C0_StrapFlrEn_MASK                       0x40000000
+#define D0F0xE4_CORE_00C0_Reserved_31_31_OFFSET                 31
+#define D0F0xE4_CORE_00C0_Reserved_31_31_WIDTH                  1
+#define D0F0xE4_CORE_00C0_Reserved_31_31_MASK                   0x80000000
+
+/// D0F0xE4_CORE_00C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_27_0:28; ///<
+    UINT32                                          StrapReverseAll:1 ; ///<
+    UINT32                                          StrapMstAdr64En:1 ; ///<
+    UINT32                                               StrapFlrEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00C0_STRUCT;
+
+// **** D0F0xE4_CORE_00C1 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00C1_ADDRESS                               0xc1
+
+// Type
+#define D0F0xE4_CORE_00C1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET   0
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH    1
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK     0x1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET            1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH             1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK              0x2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET                  2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH                   30
+#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xE4_CORE_00C1
+typedef union {
+  struct {                                                              ///<
+    UINT32                             StrapLinkBwNotificationCapEn:1 ; ///<
+    UINT32                                      StrapGen2Compliance:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00C1_STRUCT;
+
+// **** D0F0xE4_PHY_0009 Register Definition ****
+// Address
+#define D0F0xE4_PHY_0009_ADDRESS                                0x9
+
+// Type
+#define D0F0xE4_PHY_0009_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_0009_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_0009_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_0009_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_0009_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_0009_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_0009_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_0009_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_0009_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_0009_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_0009
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_0009_STRUCT;
+
+// **** D0F0xE4_PHY_000A Register Definition ****
+// Address
+#define D0F0xE4_PHY_000A_ADDRESS                                0xa
+
+// Type
+#define D0F0xE4_PHY_000A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_000A_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_000A_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_000A_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_000A_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_000A_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_000A_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_000A_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_000A_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_000A_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_000A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000A_STRUCT;
+
+// **** D0F0xE4_PHY_000B Register Definition ****
+// Address
+#define D0F0xE4_PHY_000B_ADDRESS                                0xb
+
+// Type
+#define D0F0xE4_PHY_000B_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET                      0
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK                        0x1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET                      1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK                        0x2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET                   2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH                    1
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK                     0x4
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET                    3
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK                      0x8
+#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET                    4
+#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK                      0x10
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET               5
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH                1
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK                 0x20
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET                    6
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK                      0x40
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET              7
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH               1
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK                0x80
+#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET                      8
+#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK                        0x100
+#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET                   9
+#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH                    5
+#define D0F0xE4_PHY_000B_Reserved_13_9_MASK                     0x3e00
+#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET                    14
+#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK                      0x4000
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET                  15
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH                   1
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK                    0x8000
+#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_000B_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_000B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               TxPwrSbiEn:1 ; ///<
+    UINT32                                               RxPwrSbiEn:1 ; ///<
+    UINT32                                            PcieModeSbiEn:1 ; ///<
+    UINT32                                             FreqDivSbiEn:1 ; ///<
+    UINT32                                             DllLockSbiEn:1 ; ///<
+    UINT32                                        OffsetCancelSbiEn:1 ; ///<
+    UINT32                                             SkipBitSbiEn:1 ; ///<
+    UINT32                                       IncoherentClkSbiEn:1 ; ///<
+    UINT32                                               EiDetSbiEn:1 ; ///<
+    UINT32                                            Reserved_13_9:5 ; ///<
+    UINT32                                             MargPktSbiEn:1 ; ///<
+    UINT32                                           PllCmpPktSbiEn:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000B_STRUCT;
+
+// **** D0F0xE4_PHY_2000 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2000_ADDRESS                                0x2000
+
+// Type
+#define D0F0xE4_PHY_2000_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET                  0
+#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH                   3
+#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK                    0x7
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET               3
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH                1
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK                 0x8
+#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET                   4
+#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH                    28
+#define D0F0xE4_PHY_2000_Reserved_31_4_MASK                     0xfffffff0
+
+/// D0F0xE4_PHY_2000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PllPowerDownEn:3 ; ///<
+    UINT32                                        PllAutoPwrDownDis:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2000_STRUCT;
+
+// **** D0F0xE4_PHY_2002 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2002_ADDRESS                                0x2002
+
+// Type
+#define D0F0xE4_PHY_2002_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2002_Reserved_26_0_OFFSET                   0
+#define D0F0xE4_PHY_2002_Reserved_26_0_WIDTH                    27
+#define D0F0xE4_PHY_2002_Reserved_26_0_MASK                     0x7ffffff
+#define D0F0xE4_PHY_2002_RoCalEn_OFFSET                         27
+#define D0F0xE4_PHY_2002_RoCalEn_WIDTH                          1
+#define D0F0xE4_PHY_2002_RoCalEn_MASK                           0x8000000
+#define D0F0xE4_PHY_2002_Reserved_30_28_OFFSET                  28
+#define D0F0xE4_PHY_2002_Reserved_30_28_WIDTH                   3
+#define D0F0xE4_PHY_2002_Reserved_30_28_MASK                    0x70000000
+#define D0F0xE4_PHY_2002_IsLc_OFFSET                            31
+#define D0F0xE4_PHY_2002_IsLc_WIDTH                             1
+#define D0F0xE4_PHY_2002_IsLc_MASK                              0x80000000
+
+/// D0F0xE4_PHY_2002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_26_0:27; ///<
+    UINT32                                                  RoCalEn:1 ; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                                     IsLc:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2002_STRUCT;
+
+// **** D0F0xE4_PHY_2005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2005_ADDRESS                                0x2005
+
+// Type
+#define D0F0xE4_PHY_2005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET                      0
+#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH                       4
+#define D0F0xE4_PHY_2005_PllClkFreq_MASK                        0xf
+#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET                    4
+#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH                     5
+#define D0F0xE4_PHY_2005_Reserved_8_4_MASK                      0x1f0
+#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET                   9
+#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH                    2
+#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK                     0x600
+#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET                  11
+#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH                   2
+#define D0F0xE4_PHY_2005_Reserved_12_11_MASK                    0x1800
+#define D0F0xE4_PHY_2005_PllMode_OFFSET                         13
+#define D0F0xE4_PHY_2005_PllMode_WIDTH                          2
+#define D0F0xE4_PHY_2005_PllMode_MASK                           0x6000
+#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET                  15
+#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH                   17
+#define D0F0xE4_PHY_2005_Reserved_31_15_MASK                    0xffff8000
+
+/// D0F0xE4_PHY_2005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PllClkFreq:4 ; ///<
+    UINT32                                             Reserved_8_4:5 ; ///<
+    UINT32                                            PllClkFreqExt:2 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                  PllMode:2 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2005_STRUCT;
+
+// **** D0F0xE4_PHY_2008 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2008_ADDRESS                                0x2008
+
+// Type
+#define D0F0xE4_PHY_2008_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET                0
+#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH                 1
+#define D0F0xE4_PHY_2008_PllControlUpdate_MASK                  0x1
+#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET                   1
+#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH                    22
+#define D0F0xE4_PHY_2008_Reserved_22_1_MASK                     0x7ffffe
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET              23
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH               3
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK                0x3800000
+#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET                  26
+#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH                   3
+#define D0F0xE4_PHY_2008_Reserved_28_26_MASK                    0x1c000000
+#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET                      29
+#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH                       1
+#define D0F0xE4_PHY_2008_VdDetectEn_MASK                        0x20000000
+#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_2008_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_2008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PllControlUpdate:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                       MeasCycCntVal_2_0_:3 ; ///<
+    UINT32                                           Reserved_28_26:3 ; ///<
+    UINT32                                               VdDetectEn:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2008_STRUCT;
+
+// **** D0F0xE4_PHY_4001 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4001_ADDRESS                                0x4001
+
+// Type
+#define D0F0xE4_PHY_4001_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET                   0
+#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH                    15
+#define D0F0xE4_PHY_4001_Reserved_14_0_MASK                     0x7fff
+#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET                  15
+#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH                   1
+#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK                    0x8000
+#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_4001_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_4001
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                           ForceDccRecalc:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4001_STRUCT;
+
+// **** D0F0xE4_PHY_4002 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4002_ADDRESS                                0x4002
+
+// Type
+#define D0F0xE4_PHY_4002_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET                    0
+#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH                     3
+#define D0F0xE4_PHY_4002_Reserved_2_0_MASK                      0x7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET              3
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH               1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK                0x8
+#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET                  4
+#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH                   3
+#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK                    0x70
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET                7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH                 1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK                  0x80
+#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET                   8
+#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH                    6
+#define D0F0xE4_PHY_4002_Reserved_13_8_MASK                     0x3f00
+#define D0F0xE4_PHY_4002_LfcMin_OFFSET                          14
+#define D0F0xE4_PHY_4002_LfcMin_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMin_MASK                            0x3fc000
+#define D0F0xE4_PHY_4002_LfcMax_OFFSET                          22
+#define D0F0xE4_PHY_4002_LfcMax_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMax_MASK                            0x3fc00000
+#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_4002_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_4002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                       SamClkPiOffsetSign:1 ; ///<
+    UINT32                                           SamClkPiOffset:3 ; ///<
+    UINT32                                         SamClkPiOffsetEn:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                                   LfcMin:8 ; ///<
+    UINT32                                                   LfcMax:8 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4002_STRUCT;
+
+// **** D0F0xE4_PHY_4005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4005_ADDRESS                                0x4005
+
+// Type
+#define D0F0xE4_PHY_4005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET                    0
+#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH                     9
+#define D0F0xE4_PHY_4005_Reserved_8_0_MASK                      0x1ff
+#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET                   9
+#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH                    1
+#define D0F0xE4_PHY_4005_JitterInjHold_MASK                     0x200
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET                 10
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH                  6
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK                   0xfc00
+#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET                  16
+#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH                   7
+#define D0F0xE4_PHY_4005_Reserved_22_16_MASK                    0x7f0000
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET                  23
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH                   6
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK                    0x1f800000
+#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET                    29
+#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH                     1
+#define D0F0xE4_PHY_4005_JitterInjDir_MASK                      0x20000000
+#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET                     30
+#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH                      1
+#define D0F0xE4_PHY_4005_JitterInjEn_MASK                       0x40000000
+#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET                  31
+#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH                   1
+#define D0F0xE4_PHY_4005_Reserved_31_31_MASK                    0x80000000
+
+/// D0F0xE4_PHY_4005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                            JitterInjHold:1 ; ///<
+    UINT32                                          JitterInjOffCnt:6 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                           JitterInjOnCnt:6 ; ///<
+    UINT32                                             JitterInjDir:1 ; ///<
+    UINT32                                              JitterInjEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4005_STRUCT;
+
+// **** D0F0xE4_PHY_4006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4006_ADDRESS                                0x4006
+
+// Type
+#define D0F0xE4_PHY_4006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET                    0
+#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH                     5
+#define D0F0xE4_PHY_4006_Reserved_4_0_MASK                      0x1f
+#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET                      5
+#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH                       2
+#define D0F0xE4_PHY_4006_DfeVoltage_MASK                        0x60
+#define D0F0xE4_PHY_4006_DfeEn_OFFSET                           7
+#define D0F0xE4_PHY_4006_DfeEn_WIDTH                            1
+#define D0F0xE4_PHY_4006_DfeEn_MASK                             0x80
+#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PHY_4006_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PHY_4006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                               DfeVoltage:2 ; ///<
+    UINT32                                                    DfeEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4006_STRUCT;
+
+// **** D0F0xE4_PHY_400A Register Definition ****
+// Address
+#define D0F0xE4_PHY_400A_ADDRESS                                0x400a
+
+// Type
+#define D0F0xE4_PHY_400A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET                 0
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH                  1
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK                   0x1
+#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET                    1
+#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH                     3
+#define D0F0xE4_PHY_400A_Reserved_3_1_MASK                      0xe
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET                4
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH                 1
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK                  0x10
+#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET                    5
+#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH                     2
+#define D0F0xE4_PHY_400A_Reserved_6_5_MASK                      0x60
+#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET                    7
+#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH                     1
+#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK                      0x80
+#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET                   8
+#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH                    5
+#define D0F0xE4_PHY_400A_Reserved_12_8_MASK                     0x1f00
+#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET                  13
+#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH                   2
+#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK                    0x6000
+#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET                  15
+#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH                   2
+#define D0F0xE4_PHY_400A_Reserved_16_15_MASK                    0x18000
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET               17
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH                1
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK                 0x20000
+#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET                  18
+#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH                   11
+#define D0F0xE4_PHY_400A_Reserved_28_18_MASK                    0x1ffc0000
+#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET                     29
+#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK                       0xe0000000
+
+/// D0F0xE4_PHY_400A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          EnCoreLoopFirst:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                         LockDetOnLs2Exit:1 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                             BiasDisInLs2:1 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           AnalogWaitTime:2 ; ///<
+    UINT32                                           Reserved_16_15:2 ; ///<
+    UINT32                                        DllLockFastModeEn:1 ; ///<
+    UINT32                                           Reserved_28_18:11; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_400A_STRUCT;
+
+// **** D0F0xE4_PHY_4010 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4010_ADDRESS                               0x4010
+
+// Type
+#define D0F0xE4_PHY_4010_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4010_PhyFuseValid_OFFSET                   0
+#define D0F0xE4_PHY_4010_PhyFuseValid_WIDTH                    1
+#define D0F0xE4_PHY_4010_PhyFuseValid_MASK                     0x1
+#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_OFFSET    1
+#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_WIDTH     1
+#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_MASK      0x2
+#define D0F0xE4_PHY_4010_Reserved_2_2_OFFSET                   2
+#define D0F0xE4_PHY_4010_Reserved_2_2_WIDTH                    1
+#define D0F0xE4_PHY_4010_Reserved_2_2_MASK                     0x4
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_OFFSET    3
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_WIDTH     1
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_MASK      0x8
+#define D0F0xE4_PHY_4010_Reserved_4_4_OFFSET                   4
+#define D0F0xE4_PHY_4010_Reserved_4_4_WIDTH                    1
+#define D0F0xE4_PHY_4010_Reserved_4_4_MASK                     0x10
+#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_OFFSET     5
+#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_WIDTH      1
+#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_MASK       0x20
+#define D0F0xE4_PHY_4010_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_PHY_4010_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_PHY_4010_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_OFFSET        7
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_WIDTH         4
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_MASK          0x780
+#define D0F0xE4_PHY_4010_Reserved_12_11_OFFSET                 11
+#define D0F0xE4_PHY_4010_Reserved_12_11_WIDTH                  2
+#define D0F0xE4_PHY_4010_Reserved_12_11_MASK                   0x1800
+#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_OFFSET         13
+#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_WIDTH          1
+#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_MASK           0x2000
+#define D0F0xE4_PHY_4010_Reserved_14_14_OFFSET                 14
+#define D0F0xE4_PHY_4010_Reserved_14_14_WIDTH                  1
+#define D0F0xE4_PHY_4010_Reserved_14_14_MASK                   0x4000
+#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_OFFSET      15
+#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_WIDTH       2
+#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_MASK        0x18000
+#define D0F0xE4_PHY_4010_Reserved_19_17_OFFSET                 17
+#define D0F0xE4_PHY_4010_Reserved_19_17_WIDTH                  3
+#define D0F0xE4_PHY_4010_Reserved_19_17_MASK                   0xe0000
+#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_OFFSET          20
+#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_WIDTH           1
+#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_MASK            0x100000
+#define D0F0xE4_PHY_4010_FuseFuncRxSpare_OFFSET                21
+#define D0F0xE4_PHY_4010_FuseFuncRxSpare_WIDTH                 1
+#define D0F0xE4_PHY_4010_FuseFuncRxSpare_MASK                  0x200000
+#define D0F0xE4_PHY_4010_Reserved_31_22_OFFSET                 22
+#define D0F0xE4_PHY_4010_Reserved_31_22_WIDTH                  10
+#define D0F0xE4_PHY_4010_Reserved_31_22_MASK                   0xffc00000
+
+/// D0F0xE4_PHY_4010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhyFuseValid:1 ; ///<
+    UINT32                              FuseFuncDllRCFilterOverride:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                              FuseFuncDllFastLockStepSize:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                               FuseFuncDllMidLockStepSize:1 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                  FuseFuncDllFastLockStop:4 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                   FuseFuncDllInputDccDis:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                FuseFuncDllProcessCompCtl:2 ; ///<
+    UINT32                                           Reserved_19_17:3 ; ///<
+    UINT32                                    FuseFuncDllRdacSupSel:1 ; ///<
+    UINT32                                          FuseFuncRxSpare:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4010_STRUCT;
+
+// **** D0F0xE4_PHY_4011 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4011_ADDRESS                               0x4011
+
+// Type
+#define D0F0xE4_PHY_4011_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4011_PhyFuseValid_OFFSET                   0
+#define D0F0xE4_PHY_4011_PhyFuseValid_WIDTH                    1
+#define D0F0xE4_PHY_4011_PhyFuseValid_MASK                     0x1
+#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_OFFSET             1
+#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_WIDTH              3
+#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_MASK               0xe
+#define D0F0xE4_PHY_4011_Reserved_5_4_OFFSET                   4
+#define D0F0xE4_PHY_4011_Reserved_5_4_WIDTH                    2
+#define D0F0xE4_PHY_4011_Reserved_5_4_MASK                     0x30
+#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_OFFSET             6
+#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_WIDTH              3
+#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_MASK               0x1c0
+#define D0F0xE4_PHY_4011_Reserved_10_9_OFFSET                  9
+#define D0F0xE4_PHY_4011_Reserved_10_9_WIDTH                   2
+#define D0F0xE4_PHY_4011_Reserved_10_9_MASK                    0x600
+#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_OFFSET         11
+#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_WIDTH          3
+#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_MASK           0x3800
+#define D0F0xE4_PHY_4011_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_PHY_4011_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_PHY_4011_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_OFFSET         16
+#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_WIDTH          1
+#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_MASK           0x10000
+#define D0F0xE4_PHY_4011_Reserved_18_17_OFFSET                 17
+#define D0F0xE4_PHY_4011_Reserved_18_17_WIDTH                  2
+#define D0F0xE4_PHY_4011_Reserved_18_17_MASK                   0x60000
+#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_OFFSET            19
+#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_WIDTH             2
+#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_MASK              0x180000
+#define D0F0xE4_PHY_4011_Reserved_22_21_OFFSET                 21
+#define D0F0xE4_PHY_4011_Reserved_22_21_WIDTH                  2
+#define D0F0xE4_PHY_4011_Reserved_22_21_MASK                   0x600000
+#define D0F0xE4_PHY_4011_FuseProcRxSpare_OFFSET                23
+#define D0F0xE4_PHY_4011_FuseProcRxSpare_WIDTH                 1
+#define D0F0xE4_PHY_4011_FuseProcRxSpare_MASK                  0x800000
+#define D0F0xE4_PHY_4011_Reserved_31_24_OFFSET                 24
+#define D0F0xE4_PHY_4011_Reserved_31_24_WIDTH                  8
+#define D0F0xE4_PHY_4011_Reserved_31_24_MASK                   0xff000000
+
+/// D0F0xE4_PHY_4011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhyFuseValid:1 ; ///<
+    UINT32                                       FuseProcDllVrefAdj:3 ; ///<
+    UINT32                                             Reserved_5_4:2 ; ///<
+    UINT32                                       FuseProcDllIrefAdj:3 ; ///<
+    UINT32                                            Reserved_10_9:2 ; ///<
+    UINT32                                   FuseProcDllProcessComp:3 ; ///<
+    UINT32                                           Reserved_15_14:1 ; ///<
+    UINT32                                   FuseProcDllRCFilterCtl:1 ; ///<
+    UINT32                                           Reserved_18_17:2 ; ///<
+    UINT32                                      FuseProcEiDetThresh:2 ; ///<
+    UINT32                                           Reserved_22_21:2 ; ///<
+    UINT32                                          FuseProcRxSpare:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4011_STRUCT;
+
+// **** D0F0xE4_PHY_500F Register Definition ****
+// Address
+#define D0F0xE4_PHY_500F_ADDRESS                               0x500F
+
+// Type
+#define D0F0xE4_PHY_500F_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_OFFSET        0
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_WIDTH         4
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_MASK          0xf
+#define D0F0xE4_PHY_500F_Reserved_6_4_OFFSET                   4
+#define D0F0xE4_PHY_500F_Reserved_6_4_WIDTH                    3
+#define D0F0xE4_PHY_500F_Reserved_6_4_MASK                     0x70
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_OFFSET        7
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_WIDTH         4
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_MASK          0x780
+#define D0F0xE4_PHY_500F_Reserved_11_11_OFFSET                 11
+#define D0F0xE4_PHY_500F_Reserved_11_11_WIDTH                  1
+#define D0F0xE4_PHY_500F_Reserved_11_11_MASK                   0x800
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_OFFSET      12
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_WIDTH       1
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_MASK        0x1000
+#define D0F0xE4_PHY_500F_Reserved_13_13_OFFSET                 13
+#define D0F0xE4_PHY_500F_Reserved_13_13_WIDTH                  1
+#define D0F0xE4_PHY_500F_Reserved_13_13_MASK                   0x2000
+
+/// D0F0xE4_PHY_500F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                  DllProcessFreqCtlIndex1:4 ; ///<
+    UINT32                                             Reserved_6_4:3 ; ///<
+    UINT32                                  DllProcessFreqCtlIndex2:4 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                DllProcessFreqCtlOverride:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32  :4 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_500F_STRUCT;
+
+// **** D0F0xE4_PHY_6005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6005_ADDRESS                                0x6005
+
+// Type
+#define D0F0xE4_PHY_6005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET                   0
+#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH                    29
+#define D0F0xE4_PHY_6005_Reserved_28_0_MASK                     0x1fffffff
+#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET                       29
+#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH                        1
+#define D0F0xE4_PHY_6005_IsOwnMstr_MASK                         0x20000000
+#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET                  30
+#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH                   1
+#define D0F0xE4_PHY_6005_Reserved_30_30_MASK                    0x40000000
+#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET                    31
+#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH                     1
+#define D0F0xE4_PHY_6005_GangedModeEn_MASK                      0x80000000
+
+/// D0F0xE4_PHY_6005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_28_0:29; ///<
+    UINT32                                                IsOwnMstr:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             GangedModeEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6005_STRUCT;
+
+// **** D0F0xE4_PHY_6006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6006_ADDRESS                                0x6006
+
+// Type
+#define D0F0xE4_PHY_6006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET                     0
+#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH                      8
+#define D0F0xE4_PHY_6006_TxMarginNom_MASK                       0xff
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET                   8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH                    8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK                     0xff00
+#define D0F0xE4_PHY_6006_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_6006_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_6006_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_6006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              TxMarginNom:8 ; ///<
+    UINT32                                            DeemphGen1Nom:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6006_STRUCT;
+
+// **** D0F2xF4_x00 Register Definition ****
+// Address
+#define D0F2xF4_x00_ADDRESS                                     0x0
+
+// Type
+#define D0F2xF4_x00_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x00_L2PerfEvent0_OFFSET                         0
+#define D0F2xF4_x00_L2PerfEvent0_WIDTH                          8
+#define D0F2xF4_x00_L2PerfEvent0_MASK                           0xff
+#define D0F2xF4_x00_L2PerfEvent1_OFFSET                         8
+#define D0F2xF4_x00_L2PerfEvent1_WIDTH                          8
+#define D0F2xF4_x00_L2PerfEvent1_MASK                           0xff00
+#define D0F2xF4_x00_L2PerfCountUpper0_OFFSET                    16
+#define D0F2xF4_x00_L2PerfCountUpper0_WIDTH                     8
+#define D0F2xF4_x00_L2PerfCountUpper0_MASK                      0xff0000
+#define D0F2xF4_x00_L2PerfCountUpper1_OFFSET                    24
+#define D0F2xF4_x00_L2PerfCountUpper1_WIDTH                     8
+#define D0F2xF4_x00_L2PerfCountUpper1_MASK                      0xff000000
+
+/// D0F2xF4_x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent0:8 ; ///<
+    UINT32                                             L2PerfEvent1:8 ; ///<
+    UINT32                                        L2PerfCountUpper0:8 ; ///<
+    UINT32                                        L2PerfCountUpper1:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x00_STRUCT;
+
+// **** D0F2xF4_x01 Register Definition ****
+// Address
+#define D0F2xF4_x01_ADDRESS                                     0x1
+
+// Type
+#define D0F2xF4_x01_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x01_L2PerfCount0_OFFSET                         0
+#define D0F2xF4_x01_L2PerfCount0_WIDTH                          32
+#define D0F2xF4_x01_L2PerfCount0_MASK                           0xffffffff
+
+/// D0F2xF4_x01
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x01_STRUCT;
+
+// **** D0F2xF4_x02 Register Definition ****
+// Address
+#define D0F2xF4_x02_ADDRESS                                     0x2
+
+// Type
+#define D0F2xF4_x02_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x02_L2PerfCount1_OFFSET                         0
+#define D0F2xF4_x02_L2PerfCount1_WIDTH                          32
+#define D0F2xF4_x02_L2PerfCount1_MASK                           0xffffffff
+
+/// D0F2xF4_x02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x02_STRUCT;
+
+// **** D0F2xF4_x03 Register Definition ****
+// Address
+#define D0F2xF4_x03_ADDRESS                                     0x3
+
+// Type
+#define D0F2xF4_x03_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x03_L2PerfEvent2_OFFSET                         0
+#define D0F2xF4_x03_L2PerfEvent2_WIDTH                          8
+#define D0F2xF4_x03_L2PerfEvent2_MASK                           0xff
+#define D0F2xF4_x03_L2PerfEvent3_OFFSET                         8
+#define D0F2xF4_x03_L2PerfEvent3_WIDTH                          8
+#define D0F2xF4_x03_L2PerfEvent3_MASK                           0xff00
+#define D0F2xF4_x03_L2PerfCountUpper2_OFFSET                    16
+#define D0F2xF4_x03_L2PerfCountUpper2_WIDTH                     8
+#define D0F2xF4_x03_L2PerfCountUpper2_MASK                      0xff0000
+#define D0F2xF4_x03_L2PerfCountUpper3_OFFSET                    24
+#define D0F2xF4_x03_L2PerfCountUpper3_WIDTH                     8
+#define D0F2xF4_x03_L2PerfCountUpper3_MASK                      0xff000000
+
+/// D0F2xF4_x03
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent2:8 ; ///<
+    UINT32                                             L2PerfEvent3:8 ; ///<
+    UINT32                                        L2PerfCountUpper2:8 ; ///<
+    UINT32                                        L2PerfCountUpper3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x03_STRUCT;
+
+// **** D0F2xF4_x04 Register Definition ****
+// Address
+#define D0F2xF4_x04_ADDRESS                                     0x4
+
+// Type
+#define D0F2xF4_x04_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x04_L2PerfCount2_OFFSET                         0
+#define D0F2xF4_x04_L2PerfCount2_WIDTH                          32
+#define D0F2xF4_x04_L2PerfCount2_MASK                           0xffffffff
+
+/// D0F2xF4_x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount2:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x04_STRUCT;
+
+// **** D0F2xF4_x05 Register Definition ****
+// Address
+#define D0F2xF4_x05_ADDRESS                                     0x5
+
+// Type
+#define D0F2xF4_x05_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x05_L2PerfCount3_OFFSET                         0
+#define D0F2xF4_x05_L2PerfCount3_WIDTH                          32
+#define D0F2xF4_x05_L2PerfCount3_MASK                           0xffffffff
+
+/// D0F2xF4_x05
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount3:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x05_STRUCT;
+
+// **** D0F2xF4_x06 Register Definition ****
+// Address
+#define D0F2xF4_x06_ADDRESS                                     0x6
+
+// Type
+#define D0F2xF4_x06_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x06_L2DEBUG0_OFFSET                             0
+#define D0F2xF4_x06_L2DEBUG0_WIDTH                              32
+#define D0F2xF4_x06_L2DEBUG0_MASK                               0xffffffff
+
+/// D0F2xF4_x06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L2DEBUG0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x06_STRUCT;
+
+// **** D0F2xF4_x07 Register Definition ****
+// Address
+#define D0F2xF4_x07_ADDRESS                                     0x7
+
+// Type
+#define D0F2xF4_x07_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x07_L2DEBUG1_OFFSET                             0
+#define D0F2xF4_x07_L2DEBUG1_WIDTH                              32
+#define D0F2xF4_x07_L2DEBUG1_MASK                               0xffffffff
+
+/// D0F2xF4_x07
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L2DEBUG1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x07_STRUCT;
+
+// **** D0F2xF4_x08 Register Definition ****
+// Address
+#define D0F2xF4_x08_ADDRESS                                     0x8
+
+// Type
+#define D0F2xF4_x08_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x08_L2STATUS0_OFFSET                            0
+#define D0F2xF4_x08_L2STATUS0_WIDTH                             32
+#define D0F2xF4_x08_L2STATUS0_MASK                              0xffffffff
+
+/// D0F2xF4_x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L2STATUS0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x08_STRUCT;
+
+// **** D0F2xF4_x0C Register Definition ****
+// Address
+#define D0F2xF4_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F2xF4_x0C_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x0C_PTCAddrTransReqCheck_OFFSET                 0
+#define D0F2xF4_x0C_PTCAddrTransReqCheck_WIDTH                  1
+#define D0F2xF4_x0C_PTCAddrTransReqCheck_MASK                   0x1
+#define D0F2xF4_x0C_AllowL1CacheVZero_OFFSET                    1
+#define D0F2xF4_x0C_AllowL1CacheVZero_WIDTH                     1
+#define D0F2xF4_x0C_AllowL1CacheVZero_MASK                      0x2
+#define D0F2xF4_x0C_AllowL1CacheATSRsp_OFFSET                   2
+#define D0F2xF4_x0C_AllowL1CacheATSRsp_WIDTH                    1
+#define D0F2xF4_x0C_AllowL1CacheATSRsp_MASK                     0x4
+#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_OFFSET                  3
+#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_WIDTH                   1
+#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_MASK                    0x8
+#define D0F2xF4_x0C_IFifoTWCredits_OFFSET                       4
+#define D0F2xF4_x0C_IFifoTWCredits_WIDTH                        6
+#define D0F2xF4_x0C_IFifoTWCredits_MASK                         0x3f0
+#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_OFFSET                 10
+#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_WIDTH                  1
+#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_MASK                   0x400
+#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_OFFSET               11
+#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_WIDTH                1
+#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_MASK                 0x800
+#define D0F2xF4_x0C_IFifoCMBCredits_OFFSET                      12
+#define D0F2xF4_x0C_IFifoCMBCredits_WIDTH                       6
+#define D0F2xF4_x0C_IFifoCMBCredits_MASK                        0x3f000
+#define D0F2xF4_x0C_FLTCMBPriority_OFFSET                       18
+#define D0F2xF4_x0C_FLTCMBPriority_WIDTH                        1
+#define D0F2xF4_x0C_FLTCMBPriority_MASK                         0x40000
+#define D0F2xF4_x0C_Reserved_19_19_OFFSET                       19
+#define D0F2xF4_x0C_Reserved_19_19_WIDTH                        1
+#define D0F2xF4_x0C_Reserved_19_19_MASK                         0x80000
+#define D0F2xF4_x0C_IFifoBurstLength_OFFSET                     20
+#define D0F2xF4_x0C_IFifoBurstLength_WIDTH                      4
+#define D0F2xF4_x0C_IFifoBurstLength_MASK                       0xf00000
+#define D0F2xF4_x0C_IFifoClientPriority_OFFSET                  24
+#define D0F2xF4_x0C_IFifoClientPriority_WIDTH                   8
+#define D0F2xF4_x0C_IFifoClientPriority_MASK                    0xff000000
+
+/// D0F2xF4_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     PTCAddrTransReqCheck:1 ; ///<
+    UINT32                                        AllowL1CacheVZero:1 ; ///<
+    UINT32                                       AllowL1CacheATSRsp:1 ; ///<
+    UINT32                                      DTCHitVZeroOrIVZero:1 ; ///<
+    UINT32                                           IFifoTWCredits:6 ; ///<
+    UINT32                                     SIDEPTEOnUntransExcl:1 ; ///<
+    UINT32                                   SIDEPTEOnAddrTransExcl:1 ; ///<
+    UINT32                                          IFifoCMBCredits:6 ; ///<
+    UINT32                                           FLTCMBPriority:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                         IFifoBurstLength:4 ; ///<
+    UINT32                                      IFifoClientPriority:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x0C_STRUCT;
+
+// **** D0F2xF4_x0D Register Definition ****
+// Address
+#define D0F2xF4_x0D_ADDRESS                                     0xd
+
+// Type
+#define D0F2xF4_x0D_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x0D_SeqInvBurstLimitInv_OFFSET                  0
+#define D0F2xF4_x0D_SeqInvBurstLimitInv_WIDTH                   8
+#define D0F2xF4_x0D_SeqInvBurstLimitInv_MASK                    0xff
+#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_OFFSET                8
+#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_WIDTH                 8
+#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_MASK                  0xff00
+#define D0F2xF4_x0D_SeqInvBurstLimitEn_OFFSET                   16
+#define D0F2xF4_x0D_SeqInvBurstLimitEn_WIDTH                    1
+#define D0F2xF4_x0D_SeqInvBurstLimitEn_MASK                     0x10000
+#define D0F2xF4_x0D_Reserved_23_17_OFFSET                       17
+#define D0F2xF4_x0D_Reserved_23_17_WIDTH                        7
+#define D0F2xF4_x0D_Reserved_23_17_MASK                         0xfe0000
+#define D0F2xF4_x0D_PerfThreshold_OFFSET                        24
+#define D0F2xF4_x0D_PerfThreshold_WIDTH                         8
+#define D0F2xF4_x0D_PerfThreshold_MASK                          0xff000000
+
+/// D0F2xF4_x0D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      SeqInvBurstLimitInv:8 ; ///<
+    UINT32                                    SeqInvBurstLimitL2Req:8 ; ///<
+    UINT32                                       SeqInvBurstLimitEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PerfThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x0D_STRUCT;
+
+// **** D0F2xF4_x10 Register Definition ****
+// Address
+#define D0F2xF4_x10_ADDRESS                                     0x10
+
+// Type
+#define D0F2xF4_x10_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x10_DTCReplacementSel_OFFSET                    0
+#define D0F2xF4_x10_DTCReplacementSel_WIDTH                     2
+#define D0F2xF4_x10_DTCReplacementSel_MASK                      0x3
+#define D0F2xF4_x10_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x10_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x10_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x10_DTCLRUUpdatePri_OFFSET                      3
+#define D0F2xF4_x10_DTCLRUUpdatePri_WIDTH                       1
+#define D0F2xF4_x10_DTCLRUUpdatePri_MASK                        0x8
+#define D0F2xF4_x10_DTCParityEn_OFFSET                          4
+#define D0F2xF4_x10_DTCParityEn_WIDTH                           1
+#define D0F2xF4_x10_DTCParityEn_MASK                            0x10
+#define D0F2xF4_x10_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x10_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x10_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x10_DTCInvalidationSel_OFFSET                   8
+#define D0F2xF4_x10_DTCInvalidationSel_WIDTH                    2
+#define D0F2xF4_x10_DTCInvalidationSel_MASK                     0x300
+#define D0F2xF4_x10_DTCSoftInvalidate_OFFSET                    10
+#define D0F2xF4_x10_DTCSoftInvalidate_WIDTH                     1
+#define D0F2xF4_x10_DTCSoftInvalidate_MASK                      0x400
+#define D0F2xF4_x10_Reserved_12_11_OFFSET                       11
+#define D0F2xF4_x10_Reserved_12_11_WIDTH                        2
+#define D0F2xF4_x10_Reserved_12_11_MASK                         0x1800
+#define D0F2xF4_x10_DTCBypass_OFFSET                            13
+#define D0F2xF4_x10_DTCBypass_WIDTH                             1
+#define D0F2xF4_x10_DTCBypass_MASK                              0x2000
+#define D0F2xF4_x10_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x10_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x10_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x10_DTCParitySupport_OFFSET                     15
+#define D0F2xF4_x10_DTCParitySupport_WIDTH                      1
+#define D0F2xF4_x10_DTCParitySupport_MASK                       0x8000
+#define D0F2xF4_x10_DTCWays_OFFSET                              16
+#define D0F2xF4_x10_DTCWays_WIDTH                               8
+#define D0F2xF4_x10_DTCWays_MASK                                0xff0000
+#define D0F2xF4_x10_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x10_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x10_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x10_DTCEntries_OFFSET                           28
+#define D0F2xF4_x10_DTCEntries_WIDTH                            4
+#define D0F2xF4_x10_DTCEntries_MASK                             0xf0000000
+
+/// D0F2xF4_x10
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DTCReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          DTCLRUUpdatePri:1 ; ///<
+    UINT32                                              DTCParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                       DTCInvalidationSel:2 ; ///<
+    UINT32                                        DTCSoftInvalidate:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                DTCBypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                         DTCParitySupport:1 ; ///<
+    UINT32                                                  DTCWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                               DTCEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x10_STRUCT;
+
+// **** D0F2xF4_x11 Register Definition ****
+// Address
+#define D0F2xF4_x11_ADDRESS                                     0x11
+
+// Type
+#define D0F2xF4_x11_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x11_DTCFuncBits_OFFSET                          0
+#define D0F2xF4_x11_DTCFuncBits_WIDTH                           2
+#define D0F2xF4_x11_DTCFuncBits_MASK                            0x3
+#define D0F2xF4_x11_DTCDevBits_OFFSET                           2
+#define D0F2xF4_x11_DTCDevBits_WIDTH                            3
+#define D0F2xF4_x11_DTCDevBits_MASK                             0x1c
+#define D0F2xF4_x11_DTCBusBits_OFFSET                           5
+#define D0F2xF4_x11_DTCBusBits_WIDTH                            4
+#define D0F2xF4_x11_DTCBusBits_MASK                             0x1e0
+#define D0F2xF4_x11_Reserved_9_9_OFFSET                         9
+#define D0F2xF4_x11_Reserved_9_9_WIDTH                          1
+#define D0F2xF4_x11_Reserved_9_9_MASK                           0x200
+#define D0F2xF4_x11_DtcAltHashEn_OFFSET                         10
+#define D0F2xF4_x11_DtcAltHashEn_WIDTH                          1
+#define D0F2xF4_x11_DtcAltHashEn_MASK                           0x400
+#define D0F2xF4_x11_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x11_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x11_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x11_DtcAddressMask_OFFSET                       16
+#define D0F2xF4_x11_DtcAddressMask_WIDTH                        16
+#define D0F2xF4_x11_DtcAddressMask_MASK                         0xffff0000
+
+/// D0F2xF4_x11
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DTCFuncBits:2 ; ///<
+    UINT32                                               DTCDevBits:3 ; ///<
+    UINT32                                               DTCBusBits:4 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             DtcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           DtcAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x11_STRUCT;
+
+// **** D0F2xF4_x12 Register Definition ****
+// Address
+#define D0F2xF4_x12_ADDRESS                                     0x12
+
+// Type
+#define D0F2xF4_x12_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x12_DTCWayDisable_OFFSET                        0
+#define D0F2xF4_x12_DTCWayDisable_WIDTH                         16
+#define D0F2xF4_x12_DTCWayDisable_MASK                          0xffff
+#define D0F2xF4_x12_DTCWayAccessDisable_OFFSET                  16
+#define D0F2xF4_x12_DTCWayAccessDisable_WIDTH                   16
+#define D0F2xF4_x12_DTCWayAccessDisable_MASK                    0xffff0000
+
+/// D0F2xF4_x12
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DTCWayDisable:16; ///<
+    UINT32                                      DTCWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x12_STRUCT;
+
+// **** D0F2xF4_x14 Register Definition ****
+// Address
+#define D0F2xF4_x14_ADDRESS                                     0x14
+
+// Type
+#define D0F2xF4_x14_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x14_ITCReplacementSel_OFFSET                    0
+#define D0F2xF4_x14_ITCReplacementSel_WIDTH                     2
+#define D0F2xF4_x14_ITCReplacementSel_MASK                      0x3
+#define D0F2xF4_x14_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x14_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x14_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x14_ITCLRUUpdatePri_OFFSET                      3
+#define D0F2xF4_x14_ITCLRUUpdatePri_WIDTH                       1
+#define D0F2xF4_x14_ITCLRUUpdatePri_MASK                        0x8
+#define D0F2xF4_x14_ITCParityEn_OFFSET                          4
+#define D0F2xF4_x14_ITCParityEn_WIDTH                           1
+#define D0F2xF4_x14_ITCParityEn_MASK                            0x10
+#define D0F2xF4_x14_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x14_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x14_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x14_ITCInvalidationSel_OFFSET                   8
+#define D0F2xF4_x14_ITCInvalidationSel_WIDTH                    2
+#define D0F2xF4_x14_ITCInvalidationSel_MASK                     0x300
+#define D0F2xF4_x14_ITCSoftInvalidate_OFFSET                    10
+#define D0F2xF4_x14_ITCSoftInvalidate_WIDTH                     1
+#define D0F2xF4_x14_ITCSoftInvalidate_MASK                      0x400
+#define D0F2xF4_x14_Reserved_12_11_OFFSET                       11
+#define D0F2xF4_x14_Reserved_12_11_WIDTH                        2
+#define D0F2xF4_x14_Reserved_12_11_MASK                         0x1800
+#define D0F2xF4_x14_ITCBypass_OFFSET                            13
+#define D0F2xF4_x14_ITCBypass_WIDTH                             1
+#define D0F2xF4_x14_ITCBypass_MASK                              0x2000
+#define D0F2xF4_x14_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x14_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x14_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x14_ITCParitySupport_OFFSET                     15
+#define D0F2xF4_x14_ITCParitySupport_WIDTH                      1
+#define D0F2xF4_x14_ITCParitySupport_MASK                       0x8000
+#define D0F2xF4_x14_ITCWays_OFFSET                              16
+#define D0F2xF4_x14_ITCWays_WIDTH                               8
+#define D0F2xF4_x14_ITCWays_MASK                                0xff0000
+#define D0F2xF4_x14_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x14_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x14_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x14_ITCEntries_OFFSET                           28
+#define D0F2xF4_x14_ITCEntries_WIDTH                            4
+#define D0F2xF4_x14_ITCEntries_MASK                             0xf0000000
+
+/// D0F2xF4_x14
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ITCReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          ITCLRUUpdatePri:1 ; ///<
+    UINT32                                              ITCParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                       ITCInvalidationSel:2 ; ///<
+    UINT32                                        ITCSoftInvalidate:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                ITCBypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                         ITCParitySupport:1 ; ///<
+    UINT32                                                  ITCWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                               ITCEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x14_STRUCT;
+
+// **** D0F2xF4_x15 Register Definition ****
+// Address
+#define D0F2xF4_x15_ADDRESS                                     0x15
+
+// Type
+#define D0F2xF4_x15_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x15_ITCFuncBits_OFFSET                          0
+#define D0F2xF4_x15_ITCFuncBits_WIDTH                           2
+#define D0F2xF4_x15_ITCFuncBits_MASK                            0x3
+#define D0F2xF4_x15_ITCDevBits_OFFSET                           2
+#define D0F2xF4_x15_ITCDevBits_WIDTH                            3
+#define D0F2xF4_x15_ITCDevBits_MASK                             0x1c
+#define D0F2xF4_x15_ITCBusBits_OFFSET                           5
+#define D0F2xF4_x15_ITCBusBits_WIDTH                            4
+#define D0F2xF4_x15_ITCBusBits_MASK                             0x1e0
+#define D0F2xF4_x15_Reserved_9_9_OFFSET                         9
+#define D0F2xF4_x15_Reserved_9_9_WIDTH                          1
+#define D0F2xF4_x15_Reserved_9_9_MASK                           0x200
+#define D0F2xF4_x15_ItcAltHashEn_OFFSET                         10
+#define D0F2xF4_x15_ItcAltHashEn_WIDTH                          1
+#define D0F2xF4_x15_ItcAltHashEn_MASK                           0x400
+#define D0F2xF4_x15_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x15_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x15_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x15_ITCAddressMask_OFFSET                       16
+#define D0F2xF4_x15_ITCAddressMask_WIDTH                        16
+#define D0F2xF4_x15_ITCAddressMask_MASK                         0xffff0000
+
+/// D0F2xF4_x15
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              ITCFuncBits:2 ; ///<
+    UINT32                                               ITCDevBits:3 ; ///<
+    UINT32                                               ITCBusBits:4 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             ItcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           ITCAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x15_STRUCT;
+
+// **** D0F2xF4_x16 Register Definition ****
+// Address
+#define D0F2xF4_x16_ADDRESS                                     0x16
+
+// Type
+#define D0F2xF4_x16_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x16_ITCWayDisable_OFFSET                        0
+#define D0F2xF4_x16_ITCWayDisable_WIDTH                         16
+#define D0F2xF4_x16_ITCWayDisable_MASK                          0xffff
+#define D0F2xF4_x16_ITCWayAccessDisable_OFFSET                  16
+#define D0F2xF4_x16_ITCWayAccessDisable_WIDTH                   16
+#define D0F2xF4_x16_ITCWayAccessDisable_MASK                    0xffff0000
+
+/// D0F2xF4_x16
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ITCWayDisable:16; ///<
+    UINT32                                      ITCWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x16_STRUCT;
+
+// **** D0F2xF4_x18 Register Definition ****
+// Address
+#define D0F2xF4_x18_ADDRESS                                     0x18
+
+// Type
+#define D0F2xF4_x18_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x18_PTCAReplacementSel_OFFSET                   0
+#define D0F2xF4_x18_PTCAReplacementSel_WIDTH                    2
+#define D0F2xF4_x18_PTCAReplacementSel_MASK                     0x3
+#define D0F2xF4_x18_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x18_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x18_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x18_PTCALRUUpdatePri_OFFSET                     3
+#define D0F2xF4_x18_PTCALRUUpdatePri_WIDTH                      1
+#define D0F2xF4_x18_PTCALRUUpdatePri_MASK                       0x8
+#define D0F2xF4_x18_PTCAParityEn_OFFSET                         4
+#define D0F2xF4_x18_PTCAParityEn_WIDTH                          1
+#define D0F2xF4_x18_PTCAParityEn_MASK                           0x10
+#define D0F2xF4_x18_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x18_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x18_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x18_PTCAInvalidationSel_OFFSET                  8
+#define D0F2xF4_x18_PTCAInvalidationSel_WIDTH                   2
+#define D0F2xF4_x18_PTCAInvalidationSel_MASK                    0x300
+#define D0F2xF4_x18_PTCASoftInvalidate_OFFSET                   10
+#define D0F2xF4_x18_PTCASoftInvalidate_WIDTH                    1
+#define D0F2xF4_x18_PTCASoftInvalidate_MASK                     0x400
+#define D0F2xF4_x18_PTCA2MMode_OFFSET                           11
+#define D0F2xF4_x18_PTCA2MMode_WIDTH                            1
+#define D0F2xF4_x18_PTCA2MMode_MASK                             0x800
+#define D0F2xF4_x18_Reserved_12_12_OFFSET                       12
+#define D0F2xF4_x18_Reserved_12_12_WIDTH                        1
+#define D0F2xF4_x18_Reserved_12_12_MASK                         0x1000
+#define D0F2xF4_x18_PTCABypass_OFFSET                           13
+#define D0F2xF4_x18_PTCABypass_WIDTH                            1
+#define D0F2xF4_x18_PTCABypass_MASK                             0x2000
+#define D0F2xF4_x18_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x18_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x18_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x18_PTCAParitySupport_OFFSET                    15
+#define D0F2xF4_x18_PTCAParitySupport_WIDTH                     1
+#define D0F2xF4_x18_PTCAParitySupport_MASK                      0x8000
+#define D0F2xF4_x18_PTCAWays_OFFSET                             16
+#define D0F2xF4_x18_PTCAWays_WIDTH                              8
+#define D0F2xF4_x18_PTCAWays_MASK                               0xff0000
+#define D0F2xF4_x18_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x18_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x18_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x18_PTCAEntries_OFFSET                          28
+#define D0F2xF4_x18_PTCAEntries_WIDTH                           4
+#define D0F2xF4_x18_PTCAEntries_MASK                            0xf0000000
+
+/// D0F2xF4_x18
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PTCAReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                         PTCALRUUpdatePri:1 ; ///<
+    UINT32                                             PTCAParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                      PTCAInvalidationSel:2 ; ///<
+    UINT32                                       PTCASoftInvalidate:1 ; ///<
+    UINT32                                               PTCA2MMode:1 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                               PTCABypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                        PTCAParitySupport:1 ; ///<
+    UINT32                                                 PTCAWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                              PTCAEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x18_STRUCT;
+
+// **** D0F2xF4_x19 Register Definition ****
+// Address
+#define D0F2xF4_x19_ADDRESS                                     0x19
+
+// Type
+#define D0F2xF4_x19_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x19_PTCAFuncBits_OFFSET                         0
+#define D0F2xF4_x19_PTCAFuncBits_WIDTH                          2
+#define D0F2xF4_x19_PTCAFuncBits_MASK                           0x3
+#define D0F2xF4_x19_PTCADevBits_OFFSET                          2
+#define D0F2xF4_x19_PTCADevBits_WIDTH                           3
+#define D0F2xF4_x19_PTCADevBits_MASK                            0x1c
+#define D0F2xF4_x19_PTCABusBits_OFFSET                          5
+#define D0F2xF4_x19_PTCABusBits_WIDTH                           4
+#define D0F2xF4_x19_PTCABusBits_MASK                            0x1e0
+#define D0F2xF4_x19_Reserved_9_9_OFFSET                         9
+#define D0F2xF4_x19_Reserved_9_9_WIDTH                          1
+#define D0F2xF4_x19_Reserved_9_9_MASK                           0x200
+#define D0F2xF4_x19_PtcAltHashEn_OFFSET                         10
+#define D0F2xF4_x19_PtcAltHashEn_WIDTH                          1
+#define D0F2xF4_x19_PtcAltHashEn_MASK                           0x400
+#define D0F2xF4_x19_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x19_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x19_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x19_PTCAAddressMask_OFFSET                      16
+#define D0F2xF4_x19_PTCAAddressMask_WIDTH                       16
+#define D0F2xF4_x19_PTCAAddressMask_MASK                        0xffff0000
+
+/// D0F2xF4_x19
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PTCAFuncBits:2 ; ///<
+    UINT32                                              PTCADevBits:3 ; ///<
+    UINT32                                              PTCABusBits:4 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             PtcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                          PTCAAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x19_STRUCT;
+
+// **** D0F2xF4_x1A Register Definition ****
+// Address
+#define D0F2xF4_x1A_ADDRESS                                     0x1a
+
+// Type
+#define D0F2xF4_x1A_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x1A_PTCAWayDisable_OFFSET                       0
+#define D0F2xF4_x1A_PTCAWayDisable_WIDTH                        16
+#define D0F2xF4_x1A_PTCAWayDisable_MASK                         0xffff
+#define D0F2xF4_x1A_PTCAWayAccessDisable_OFFSET                 16
+#define D0F2xF4_x1A_PTCAWayAccessDisable_WIDTH                  16
+#define D0F2xF4_x1A_PTCAWayAccessDisable_MASK                   0xffff0000
+
+/// D0F2xF4_x1A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PTCAWayDisable:16; ///<
+    UINT32                                     PTCAWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x1A_STRUCT;
+
+// **** D0F2xF4_x20 Register Definition ****
+// Address
+#define D0F2xF4_x20_ADDRESS                                     0x20
+
+// Type
+#define D0F2xF4_x20_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x20_QUEUECredits_OFFSET                         0
+#define D0F2xF4_x20_QUEUECredits_WIDTH                          6
+#define D0F2xF4_x20_QUEUECredits_MASK                           0x3f
+#define D0F2xF4_x20_Reserved_6_6_OFFSET                         6
+#define D0F2xF4_x20_Reserved_6_6_WIDTH                          1
+#define D0F2xF4_x20_Reserved_6_6_MASK                           0x40
+#define D0F2xF4_x20_QUEUEOverride_OFFSET                        7
+#define D0F2xF4_x20_QUEUEOverride_WIDTH                         1
+#define D0F2xF4_x20_QUEUEOverride_MASK                          0x80
+#define D0F2xF4_x20_FLTCMBCredits_OFFSET                        8
+#define D0F2xF4_x20_FLTCMBCredits_WIDTH                         6
+#define D0F2xF4_x20_FLTCMBCredits_MASK                          0x3f00
+#define D0F2xF4_x20_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x20_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x20_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x20_FLTCMBOverride_OFFSET                       15
+#define D0F2xF4_x20_FLTCMBOverride_WIDTH                        1
+#define D0F2xF4_x20_FLTCMBOverride_MASK                         0x8000
+#define D0F2xF4_x20_FCELCredits_OFFSET                          16
+#define D0F2xF4_x20_FCELCredits_WIDTH                           6
+#define D0F2xF4_x20_FCELCredits_MASK                            0x3f0000
+#define D0F2xF4_x20_Reserved_22_22_OFFSET                       22
+#define D0F2xF4_x20_Reserved_22_22_WIDTH                        1
+#define D0F2xF4_x20_Reserved_22_22_MASK                         0x400000
+#define D0F2xF4_x20_FCELOverride_OFFSET                         23
+#define D0F2xF4_x20_FCELOverride_WIDTH                          1
+#define D0F2xF4_x20_FCELOverride_MASK                           0x800000
+#define D0F2xF4_x20_PprLoggerCredits_OFFSET                     24
+#define D0F2xF4_x20_PprLoggerCredits_WIDTH                      4
+#define D0F2xF4_x20_PprLoggerCredits_MASK                       0xf000000
+#define D0F2xF4_x20_Reserved_31_28_OFFSET                       28
+#define D0F2xF4_x20_Reserved_31_28_WIDTH                        4
+#define D0F2xF4_x20_Reserved_31_28_MASK                         0xf0000000
+
+/// D0F2xF4_x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             QUEUECredits:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                            QUEUEOverride:1 ; ///<
+    UINT32                                            FLTCMBCredits:6 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                           FLTCMBOverride:1 ; ///<
+    UINT32                                              FCELCredits:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                             FCELOverride:1 ; ///<
+    UINT32                                         PprLoggerCredits:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x20_STRUCT;
+
+// **** D0F2xF4_x22 Register Definition ****
+// Address
+#define D0F2xF4_x22_ADDRESS                                     0x22
+
+// Type
+#define D0F2xF4_x22_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x22_L2aUpdateFilterBypass_OFFSET                0
+#define D0F2xF4_x22_L2aUpdateFilterBypass_WIDTH                 1
+#define D0F2xF4_x22_L2aUpdateFilterBypass_MASK                  0x1
+#define D0F2xF4_x22_L2aUpdateFilterRdlatency_OFFSET             1
+#define D0F2xF4_x22_L2aUpdateFilterRdlatency_WIDTH              4
+#define D0F2xF4_x22_L2aUpdateFilterRdlatency_MASK               0x1e
+#define D0F2xF4_x22_Reserved_31_5_OFFSET                        5
+#define D0F2xF4_x22_Reserved_31_5_WIDTH                         27
+#define D0F2xF4_x22_Reserved_31_5_MASK                          0xffffffe0
+
+/// D0F2xF4_x22
+typedef union {
+  struct {                                                              ///<
+    UINT32                                    L2aUpdateFilterBypass:1 ; ///<
+    UINT32                                 L2aUpdateFilterRdlatency:4 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x22_STRUCT;
+
+
+
+
+
+
+
+// **** D0F2xF4_x30 Register Definition ****
+// Address
+#define D0F2xF4_x30_ADDRESS                                     0x30
+
+// Type
+#define D0F2xF4_x30_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x30_ERRRuleLock1_OFFSET                         0
+#define D0F2xF4_x30_ERRRuleLock1_WIDTH                          1
+#define D0F2xF4_x30_ERRRuleLock1_MASK                           0x1
+#define D0F2xF4_x30_Reserved_3_1_OFFSET                         1
+#define D0F2xF4_x30_Reserved_3_1_WIDTH                          3
+#define D0F2xF4_x30_Reserved_3_1_MASK                           0xe
+#define D0F2xF4_x30_ERRRuleDisable3_OFFSET                      4
+#define D0F2xF4_x30_ERRRuleDisable3_WIDTH                       28
+#define D0F2xF4_x30_ERRRuleDisable3_MASK                        0xfffffff0
+
+/// D0F2xF4_x30
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             ERRRuleLock1:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                          ERRRuleDisable3:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x30_STRUCT;
+
+// **** D0F2xF4_x31 Register Definition ****
+// Address
+#define D0F2xF4_x31_ADDRESS                                     0x31
+
+// Type
+#define D0F2xF4_x31_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x31_ERRRuleDisable4_OFFSET                      0
+#define D0F2xF4_x31_ERRRuleDisable4_WIDTH                       32
+#define D0F2xF4_x31_ERRRuleDisable4_MASK                        0xffffffff
+
+/// D0F2xF4_x31
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable4:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x31_STRUCT;
+
+// **** D0F2xF4_x32 Register Definition ****
+// Address
+#define D0F2xF4_x32_ADDRESS                                     0x32
+
+// Type
+#define D0F2xF4_x32_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x32_ERRRuleDisable5_OFFSET                      0
+#define D0F2xF4_x32_ERRRuleDisable5_WIDTH                       32
+#define D0F2xF4_x32_ERRRuleDisable5_MASK                        0xffffffff
+
+/// D0F2xF4_x32
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable5:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x32_STRUCT;
+
+// **** D0F2xF4_x33 Register Definition ****
+// Address
+#define D0F2xF4_x33_ADDRESS                                     0x33
+
+// Type
+#define D0F2xF4_x33_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x33_CKGateL2ARegsDisable_OFFSET                 0
+#define D0F2xF4_x33_CKGateL2ARegsDisable_WIDTH                  1
+#define D0F2xF4_x33_CKGateL2ARegsDisable_MASK                   0x1
+#define D0F2xF4_x33_CKGateL2ADynamicDisable_OFFSET              1
+#define D0F2xF4_x33_CKGateL2ADynamicDisable_WIDTH               1
+#define D0F2xF4_x33_CKGateL2ADynamicDisable_MASK                0x2
+#define D0F2xF4_x33_CKGateL2ACacheDisable_OFFSET                2
+#define D0F2xF4_x33_CKGateL2ACacheDisable_WIDTH                 1
+#define D0F2xF4_x33_CKGateL2ACacheDisable_MASK                  0x4
+#define D0F2xF4_x33_CKGateL2ASpare_OFFSET                       3
+#define D0F2xF4_x33_CKGateL2ASpare_WIDTH                        1
+#define D0F2xF4_x33_CKGateL2ASpare_MASK                         0x8
+#define D0F2xF4_x33_CKGateL2ALength_OFFSET                      4
+#define D0F2xF4_x33_CKGateL2ALength_WIDTH                       2
+#define D0F2xF4_x33_CKGateL2ALength_MASK                        0x30
+#define D0F2xF4_x33_CKGateL2AStop_OFFSET                        6
+#define D0F2xF4_x33_CKGateL2AStop_WIDTH                         2
+#define D0F2xF4_x33_CKGateL2AStop_MASK                          0xc0
+#define D0F2xF4_x33_Reserved_31_8_OFFSET                        8
+#define D0F2xF4_x33_Reserved_31_8_WIDTH                         24
+#define D0F2xF4_x33_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F2xF4_x33
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     CKGateL2ARegsDisable:1 ; ///<
+    UINT32                                  CKGateL2ADynamicDisable:1 ; ///<
+    UINT32                                    CKGateL2ACacheDisable:1 ; ///<
+    UINT32                                           CKGateL2ASpare:1 ; ///<
+    UINT32                                          CKGateL2ALength:2 ; ///<
+    UINT32                                            CKGateL2AStop:2 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x33_STRUCT;
+
+// **** D0F2xF4_x34 Register Definition ****
+// Address
+#define D0F2xF4_x34_ADDRESS                                     0x34
+
+// Type
+#define D0F2xF4_x34_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x34_L2aregGstPgsize_OFFSET                      0
+#define D0F2xF4_x34_L2aregGstPgsize_WIDTH                       2
+#define D0F2xF4_x34_L2aregGstPgsize_MASK                        0x3
+#define D0F2xF4_x34_L2aregHostPgsize_OFFSET                     2
+#define D0F2xF4_x34_L2aregHostPgsize_WIDTH                      2
+#define D0F2xF4_x34_L2aregHostPgsize_MASK                       0xc
+#define D0F2xF4_x34_Reserved_31_4_OFFSET                        4
+#define D0F2xF4_x34_Reserved_31_4_WIDTH                         28
+#define D0F2xF4_x34_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F2xF4_x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L2aregGstPgsize:2 ; ///<
+    UINT32                                         L2aregHostPgsize:2 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x34_STRUCT;
+
+// **** D0F2xF4_x40 Register Definition ****
+// Address
+#define D0F2xF4_x40_ADDRESS                                     0x40
+
+// Type
+#define D0F2xF4_x40_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x40_L2PerfEvent4_OFFSET                         0
+#define D0F2xF4_x40_L2PerfEvent4_WIDTH                          8
+#define D0F2xF4_x40_L2PerfEvent4_MASK                           0xff
+#define D0F2xF4_x40_L2PerfEvent5_OFFSET                         8
+#define D0F2xF4_x40_L2PerfEvent5_WIDTH                          8
+#define D0F2xF4_x40_L2PerfEvent5_MASK                           0xff00
+#define D0F2xF4_x40_L2PerfCountUpper4_OFFSET                    16
+#define D0F2xF4_x40_L2PerfCountUpper4_WIDTH                     8
+#define D0F2xF4_x40_L2PerfCountUpper4_MASK                      0xff0000
+#define D0F2xF4_x40_L2PerfCountUpper5_OFFSET                    24
+#define D0F2xF4_x40_L2PerfCountUpper5_WIDTH                     8
+#define D0F2xF4_x40_L2PerfCountUpper5_MASK                      0xff000000
+
+/// D0F2xF4_x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent4:8 ; ///<
+    UINT32                                             L2PerfEvent5:8 ; ///<
+    UINT32                                        L2PerfCountUpper4:8 ; ///<
+    UINT32                                        L2PerfCountUpper5:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x40_STRUCT;
+
+// **** D0F2xF4_x41 Register Definition ****
+// Address
+#define D0F2xF4_x41_ADDRESS                                     0x41
+
+// Type
+#define D0F2xF4_x41_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x41_L2PerfCount4_OFFSET                         0
+#define D0F2xF4_x41_L2PerfCount4_WIDTH                          32
+#define D0F2xF4_x41_L2PerfCount4_MASK                           0xffffffff
+
+/// D0F2xF4_x41
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount4:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x41_STRUCT;
+
+// **** D0F2xF4_x42 Register Definition ****
+// Address
+#define D0F2xF4_x42_ADDRESS                                     0x42
+
+// Type
+#define D0F2xF4_x42_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x42_L2PerfCount5_OFFSET                         0
+#define D0F2xF4_x42_L2PerfCount5_WIDTH                          32
+#define D0F2xF4_x42_L2PerfCount5_MASK                           0xffffffff
+
+/// D0F2xF4_x42
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount5:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x42_STRUCT;
+
+// **** D0F2xF4_x43 Register Definition ****
+// Address
+#define D0F2xF4_x43_ADDRESS                                     0x43
+
+// Type
+#define D0F2xF4_x43_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x43_L2PerfEvent6_OFFSET                         0
+#define D0F2xF4_x43_L2PerfEvent6_WIDTH                          8
+#define D0F2xF4_x43_L2PerfEvent6_MASK                           0xff
+#define D0F2xF4_x43_L2PerfEvent7_OFFSET                         8
+#define D0F2xF4_x43_L2PerfEvent7_WIDTH                          8
+#define D0F2xF4_x43_L2PerfEvent7_MASK                           0xff00
+#define D0F2xF4_x43_L2PerfCountUpper6_OFFSET                    16
+#define D0F2xF4_x43_L2PerfCountUpper6_WIDTH                     8
+#define D0F2xF4_x43_L2PerfCountUpper6_MASK                      0xff0000
+#define D0F2xF4_x43_L2PerfCountUpper7_OFFSET                    24
+#define D0F2xF4_x43_L2PerfCountUpper7_WIDTH                     8
+#define D0F2xF4_x43_L2PerfCountUpper7_MASK                      0xff000000
+
+/// D0F2xF4_x43
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent6:8 ; ///<
+    UINT32                                             L2PerfEvent7:8 ; ///<
+    UINT32                                        L2PerfCountUpper6:8 ; ///<
+    UINT32                                        L2PerfCountUpper7:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x43_STRUCT;
+
+// **** D0F2xF4_x44 Register Definition ****
+// Address
+#define D0F2xF4_x44_ADDRESS                                     0x44
+
+// Type
+#define D0F2xF4_x44_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x44_L2PerfCount6_OFFSET                         0
+#define D0F2xF4_x44_L2PerfCount6_WIDTH                          32
+#define D0F2xF4_x44_L2PerfCount6_MASK                           0xffffffff
+
+/// D0F2xF4_x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount6:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x44_STRUCT;
+
+// **** D0F2xF4_x45 Register Definition ****
+// Address
+#define D0F2xF4_x45_ADDRESS                                     0x45
+
+// Type
+#define D0F2xF4_x45_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x45_L2PerfCount7_OFFSET                         0
+#define D0F2xF4_x45_L2PerfCount7_WIDTH                          32
+#define D0F2xF4_x45_L2PerfCount7_MASK                           0xffffffff
+
+/// D0F2xF4_x45
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount7:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x45_STRUCT;
+
+// **** D0F2xF4_x46 Register Definition ****
+// Address
+#define D0F2xF4_x46_ADDRESS                                     0x46
+
+// Type
+#define D0F2xF4_x46_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x46_L2DEBUG2_OFFSET                             0
+#define D0F2xF4_x46_L2DEBUG2_WIDTH                              32
+#define D0F2xF4_x46_L2DEBUG2_MASK                               0xffffffff
+
+/// D0F2xF4_x46
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L2DEBUG2:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x46_STRUCT;
+
+// **** D0F2xF4_x47 Register Definition ****
+// Address
+#define D0F2xF4_x47_ADDRESS                                     0x47
+
+// Type
+#define D0F2xF4_x47_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x47_Reserved_0_0_OFFSET                         0
+#define D0F2xF4_x47_Reserved_0_0_WIDTH                          1
+#define D0F2xF4_x47_Reserved_0_0_MASK                           0x1
+#define D0F2xF4_x47_TwNwEn_OFFSET                               1
+#define D0F2xF4_x47_TwNwEn_WIDTH                                1
+#define D0F2xF4_x47_TwNwEn_MASK                                 0x2
+#define D0F2xF4_x47_TwAtomicFilterEn_OFFSET                     2
+#define D0F2xF4_x47_TwAtomicFilterEn_WIDTH                      1
+#define D0F2xF4_x47_TwAtomicFilterEn_MASK                       0x4
+#define D0F2xF4_x47_Reserved_31_3_OFFSET                        3
+#define D0F2xF4_x47_Reserved_31_3_WIDTH                         29
+#define D0F2xF4_x47_Reserved_31_3_MASK                          0xfffffff8
+
+/// D0F2xF4_x47
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                   TwNwEn:1 ; ///<
+    UINT32                                         TwAtomicFilterEn:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x47_STRUCT;
+
+// **** D0F2xF4_x48 Register Definition ****
+// Address
+#define D0F2xF4_x48_ADDRESS                                     0x48
+
+// Type
+#define D0F2xF4_x48_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x48_L2STATUS1_OFFSET                            0
+#define D0F2xF4_x48_L2STATUS1_WIDTH                             32
+#define D0F2xF4_x48_L2STATUS1_MASK                              0xffffffff
+
+/// D0F2xF4_x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L2STATUS1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x48_STRUCT;
+
+// **** D0F2xF4_x4C Register Definition ****
+// Address
+#define D0F2xF4_x4C_ADDRESS                                     0x4c
+
+// Type
+#define D0F2xF4_x4C_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x4C_QueueArbFBPri_OFFSET                        0
+#define D0F2xF4_x4C_QueueArbFBPri_WIDTH                         1
+#define D0F2xF4_x4C_QueueArbFBPri_MASK                          0x1
+#define D0F2xF4_x4C_PTCAddrTransReqUpdate_OFFSET                1
+#define D0F2xF4_x4C_PTCAddrTransReqUpdate_WIDTH                 1
+#define D0F2xF4_x4C_PTCAddrTransReqUpdate_MASK                  0x2
+#define D0F2xF4_x4C_FC1Dis_OFFSET                               2
+#define D0F2xF4_x4C_FC1Dis_WIDTH                                1
+#define D0F2xF4_x4C_FC1Dis_MASK                                 0x4
+#define D0F2xF4_x4C_DTCUpdateVOneIVZero_OFFSET                  3
+#define D0F2xF4_x4C_DTCUpdateVOneIVZero_WIDTH                   1
+#define D0F2xF4_x4C_DTCUpdateVOneIVZero_MASK                    0x8
+#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_OFFSET                  4
+#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_WIDTH                   1
+#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_MASK                    0x10
+#define D0F2xF4_x4C_FC2Dis_OFFSET                               5
+#define D0F2xF4_x4C_FC2Dis_WIDTH                                1
+#define D0F2xF4_x4C_FC2Dis_MASK                                 0x20
+#define D0F2xF4_x4C_FC3Dis_OFFSET                               6
+#define D0F2xF4_x4C_FC3Dis_WIDTH                                1
+#define D0F2xF4_x4C_FC3Dis_MASK                                 0x40
+#define D0F2xF4_x4C_FC2AltMode_OFFSET                           7
+#define D0F2xF4_x4C_FC2AltMode_WIDTH                            1
+#define D0F2xF4_x4C_FC2AltMode_MASK                             0x80
+#define D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET                   8
+#define D0F2xF4_x4C_GstPartialPtcCntrl_WIDTH                    2
+#define D0F2xF4_x4C_GstPartialPtcCntrl_MASK                     0x300
+#define D0F2xF4_x4C_Reserved_31_10_OFFSET                       10
+#define D0F2xF4_x4C_Reserved_31_10_WIDTH                        22
+#define D0F2xF4_x4C_Reserved_31_10_MASK                         0xfffffc00
+
+/// D0F2xF4_x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            QueueArbFBPri:1 ; ///<
+    UINT32                                    PTCAddrTransReqUpdate:1 ; ///<
+    UINT32                                                   FC1Dis:1 ; ///<
+    UINT32                                      DTCUpdateVOneIVZero:1 ; ///<
+    UINT32                                      DTCUpdateVZeroIVOne:1 ; ///<
+    UINT32                                                   FC2Dis:1 ; ///<
+    UINT32                                                   FC3Dis:1 ; ///<
+    UINT32                                               FC2AltMode:1 ; ///<
+    UINT32                                       GstPartialPtcCntrl:2 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x4C_STRUCT;
+
+// **** D0F2xF4_x4D Register Definition ****
+// Address
+#define D0F2xF4_x4D_ADDRESS                                     0x4d
+
+// Type
+#define D0F2xF4_x4D_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x4D_SeqInvBurstLimitInv_OFFSET                  0
+#define D0F2xF4_x4D_SeqInvBurstLimitInv_WIDTH                   8
+#define D0F2xF4_x4D_SeqInvBurstLimitInv_MASK                    0xff
+#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_OFFSET               8
+#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_WIDTH                8
+#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_MASK                 0xff00
+#define D0F2xF4_x4D_SeqInvBurstLimitEn_OFFSET                   16
+#define D0F2xF4_x4D_SeqInvBurstLimitEn_WIDTH                    1
+#define D0F2xF4_x4D_SeqInvBurstLimitEn_MASK                     0x10000
+#define D0F2xF4_x4D_Reserved_23_17_OFFSET                       17
+#define D0F2xF4_x4D_Reserved_23_17_WIDTH                        7
+#define D0F2xF4_x4D_Reserved_23_17_MASK                         0xfe0000
+#define D0F2xF4_x4D_Perf2Threshold_OFFSET                       24
+#define D0F2xF4_x4D_Perf2Threshold_WIDTH                        8
+#define D0F2xF4_x4D_Perf2Threshold_MASK                         0xff000000
+
+/// D0F2xF4_x4D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      SeqInvBurstLimitInv:8 ; ///<
+    UINT32                                   SeqInvBurstLimitPDCReq:8 ; ///<
+    UINT32                                       SeqInvBurstLimitEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                           Perf2Threshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x4D_STRUCT;
+
+// **** D0F2xF4_x50 Register Definition ****
+// Address
+#define D0F2xF4_x50_ADDRESS                                     0x50
+
+// Type
+#define D0F2xF4_x50_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x50_PDCReplacementSel_OFFSET                    0
+#define D0F2xF4_x50_PDCReplacementSel_WIDTH                     2
+#define D0F2xF4_x50_PDCReplacementSel_MASK                      0x3
+#define D0F2xF4_x50_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x50_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x50_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x50_PDCLRUUpdatePri_OFFSET                      3
+#define D0F2xF4_x50_PDCLRUUpdatePri_WIDTH                       1
+#define D0F2xF4_x50_PDCLRUUpdatePri_MASK                        0x8
+#define D0F2xF4_x50_PDCParityEn_OFFSET                          4
+#define D0F2xF4_x50_PDCParityEn_WIDTH                           1
+#define D0F2xF4_x50_PDCParityEn_MASK                            0x10
+#define D0F2xF4_x50_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x50_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x50_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x50_PDCInvalidationSel_OFFSET                   8
+#define D0F2xF4_x50_PDCInvalidationSel_WIDTH                    2
+#define D0F2xF4_x50_PDCInvalidationSel_MASK                     0x300
+#define D0F2xF4_x50_PDCSoftInvalidate_OFFSET                    10
+#define D0F2xF4_x50_PDCSoftInvalidate_WIDTH                     1
+#define D0F2xF4_x50_PDCSoftInvalidate_MASK                      0x400
+#define D0F2xF4_x50_Reserved_11_11_OFFSET                       11
+#define D0F2xF4_x50_Reserved_11_11_WIDTH                        1
+#define D0F2xF4_x50_Reserved_11_11_MASK                         0x800
+#define D0F2xF4_x50_PDCSearchDirection_OFFSET                   12
+#define D0F2xF4_x50_PDCSearchDirection_WIDTH                    1
+#define D0F2xF4_x50_PDCSearchDirection_MASK                     0x1000
+#define D0F2xF4_x50_PDCBypass_OFFSET                            13
+#define D0F2xF4_x50_PDCBypass_WIDTH                             1
+#define D0F2xF4_x50_PDCBypass_MASK                              0x2000
+#define D0F2xF4_x50_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x50_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x50_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x50_PDCParitySupport_OFFSET                     15
+#define D0F2xF4_x50_PDCParitySupport_WIDTH                      1
+#define D0F2xF4_x50_PDCParitySupport_MASK                       0x8000
+#define D0F2xF4_x50_PDCWays_OFFSET                              16
+#define D0F2xF4_x50_PDCWays_WIDTH                               8
+#define D0F2xF4_x50_PDCWays_MASK                                0xff0000
+#define D0F2xF4_x50_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x50_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x50_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x50_PDCEntries_OFFSET                           28
+#define D0F2xF4_x50_PDCEntries_WIDTH                            4
+#define D0F2xF4_x50_PDCEntries_MASK                             0xf0000000
+
+/// D0F2xF4_x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        PDCReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          PDCLRUUpdatePri:1 ; ///<
+    UINT32                                              PDCParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                       PDCInvalidationSel:2 ; ///<
+    UINT32                                        PDCSoftInvalidate:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                       PDCSearchDirection:1 ; ///<
+    UINT32                                                PDCBypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                         PDCParitySupport:1 ; ///<
+    UINT32                                                  PDCWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                               PDCEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x50_STRUCT;
+
+// **** D0F2xF4_x51 Register Definition ****
+// Address
+#define D0F2xF4_x51_ADDRESS                                     0x51
+
+// Type
+#define D0F2xF4_x51_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x51_PDCDomainBits_OFFSET                        0
+#define D0F2xF4_x51_PDCDomainBits_WIDTH                         6
+#define D0F2xF4_x51_PDCDomainBits_MASK                          0x3f
+#define D0F2xF4_x51_Reserved_7_6_OFFSET                         6
+#define D0F2xF4_x51_Reserved_7_6_WIDTH                          2
+#define D0F2xF4_x51_Reserved_7_6_MASK                           0xc0
+#define D0F2xF4_x51_PDCLvlHash_OFFSET                           8
+#define D0F2xF4_x51_PDCLvlHash_WIDTH                            1
+#define D0F2xF4_x51_PDCLvlHash_MASK                             0x100
+#define D0F2xF4_x51_PDCUpperLvlAddrHash_OFFSET                  9
+#define D0F2xF4_x51_PDCUpperLvlAddrHash_WIDTH                   1
+#define D0F2xF4_x51_PDCUpperLvlAddrHash_MASK                    0x200
+#define D0F2xF4_x51_PdcAltHashEn_OFFSET                         10
+#define D0F2xF4_x51_PdcAltHashEn_WIDTH                          1
+#define D0F2xF4_x51_PdcAltHashEn_MASK                           0x400
+#define D0F2xF4_x51_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x51_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x51_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x51_PDCAddressMask_OFFSET                       16
+#define D0F2xF4_x51_PDCAddressMask_WIDTH                        16
+#define D0F2xF4_x51_PDCAddressMask_MASK                         0xffff0000
+
+/// D0F2xF4_x51
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PDCDomainBits:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                               PDCLvlHash:1 ; ///<
+    UINT32                                      PDCUpperLvlAddrHash:1 ; ///<
+    UINT32                                             PdcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           PDCAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x51_STRUCT;
+
+// **** D0F2xF4_x52 Register Definition ****
+// Address
+#define D0F2xF4_x52_ADDRESS                                     0x52
+
+// Type
+#define D0F2xF4_x52_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x52_PDCWayDisable_OFFSET                        0
+#define D0F2xF4_x52_PDCWayDisable_WIDTH                         16
+#define D0F2xF4_x52_PDCWayDisable_MASK                          0xffff
+#define D0F2xF4_x52_PDCWayAccessDisable_OFFSET                  16
+#define D0F2xF4_x52_PDCWayAccessDisable_WIDTH                   16
+#define D0F2xF4_x52_PDCWayAccessDisable_MASK                    0xffff0000
+
+/// D0F2xF4_x52
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PDCWayDisable:16; ///<
+    UINT32                                      PDCWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x52_STRUCT;
+
+// **** D0F2xF4_x53 Register Definition ****
+// Address
+#define D0F2xF4_x53_ADDRESS                                     0x53
+
+// Type
+#define D0F2xF4_x53_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x53_L2bUpdateFilterBypass_OFFSET                0
+#define D0F2xF4_x53_L2bUpdateFilterBypass_WIDTH                 1
+#define D0F2xF4_x53_L2bUpdateFilterBypass_MASK                  0x1
+#define D0F2xF4_x53_L2bUpdateFilterRdlatency_OFFSET             1
+#define D0F2xF4_x53_L2bUpdateFilterRdlatency_WIDTH              4
+#define D0F2xF4_x53_L2bUpdateFilterRdlatency_MASK               0x1e
+#define D0F2xF4_x53_Reserved_31_5_OFFSET                        5
+#define D0F2xF4_x53_Reserved_31_5_WIDTH                         27
+#define D0F2xF4_x53_Reserved_31_5_MASK                          0xffffffe0
+
+/// D0F2xF4_x53
+typedef union {
+  struct {                                                              ///<
+    UINT32                                    L2bUpdateFilterBypass:1 ; ///<
+    UINT32                                 L2bUpdateFilterRdlatency:4 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x53_STRUCT;
+
+// **** D0F2xF4_x54 Register Definition ****
+// Address
+#define D0F2xF4_x54_ADDRESS                                     0x54
+
+// Type
+#define D0F2xF4_x54_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x54_TWQueueLimit_OFFSET                         0
+#define D0F2xF4_x54_TWQueueLimit_WIDTH                          6
+#define D0F2xF4_x54_TWQueueLimit_MASK                           0x3f
+#define D0F2xF4_x54_TWForceCoherent_OFFSET                      6
+#define D0F2xF4_x54_TWForceCoherent_WIDTH                       1
+#define D0F2xF4_x54_TWForceCoherent_MASK                        0x40
+#define D0F2xF4_x54_Reserved_7_7_OFFSET                         7
+#define D0F2xF4_x54_Reserved_7_7_WIDTH                          1
+#define D0F2xF4_x54_Reserved_7_7_MASK                           0x80
+#define D0F2xF4_x54_TWPrefetchEn_OFFSET                         8
+#define D0F2xF4_x54_TWPrefetchEn_WIDTH                          1
+#define D0F2xF4_x54_TWPrefetchEn_MASK                           0x100
+#define D0F2xF4_x54_TWPrefetchOnly4KDis_OFFSET                  9
+#define D0F2xF4_x54_TWPrefetchOnly4KDis_WIDTH                   1
+#define D0F2xF4_x54_TWPrefetchOnly4KDis_MASK                    0x200
+#define D0F2xF4_x54_TWPTEOnUntransExcl_OFFSET                   10
+#define D0F2xF4_x54_TWPTEOnUntransExcl_WIDTH                    1
+#define D0F2xF4_x54_TWPTEOnUntransExcl_MASK                     0x400
+#define D0F2xF4_x54_TWPTEOnAddrTransExcl_OFFSET                 11
+#define D0F2xF4_x54_TWPTEOnAddrTransExcl_WIDTH                  1
+#define D0F2xF4_x54_TWPTEOnAddrTransExcl_MASK                   0x800
+#define D0F2xF4_x54_TWPrefetchRange_OFFSET                      12
+#define D0F2xF4_x54_TWPrefetchRange_WIDTH                       3
+#define D0F2xF4_x54_TWPrefetchRange_MASK                        0x7000
+#define D0F2xF4_x54_Reserved_15_15_OFFSET                       15
+#define D0F2xF4_x54_Reserved_15_15_WIDTH                        1
+#define D0F2xF4_x54_Reserved_15_15_MASK                         0x8000
+#define D0F2xF4_x54_TwfilterDis_OFFSET                          16
+#define D0F2xF4_x54_TwfilterDis_WIDTH                           1
+#define D0F2xF4_x54_TwfilterDis_MASK                            0x10000
+#define D0F2xF4_x54_Twfilter64bDis_OFFSET                       17
+#define D0F2xF4_x54_Twfilter64bDis_WIDTH                        1
+#define D0F2xF4_x54_Twfilter64bDis_MASK                         0x20000
+#define D0F2xF4_x54_Reserved_31_18_OFFSET                       18
+#define D0F2xF4_x54_Reserved_31_18_WIDTH                        14
+#define D0F2xF4_x54_Reserved_31_18_MASK                         0xfffc0000
+
+/// D0F2xF4_x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             TWQueueLimit:6 ; ///<
+    UINT32                                          TWForceCoherent:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                             TWPrefetchEn:1 ; ///<
+    UINT32                                      TWPrefetchOnly4KDis:1 ; ///<
+    UINT32                                       TWPTEOnUntransExcl:1 ; ///<
+    UINT32                                     TWPTEOnAddrTransExcl:1 ; ///<
+    UINT32                                          TWPrefetchRange:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                              TwfilterDis:1 ; ///<
+    UINT32                                           Twfilter64bDis:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x54_STRUCT;
+
+// **** D0F2xF4_x56 Register Definition ****
+// Address
+#define D0F2xF4_x56_ADDRESS                                     0x56
+
+// Type
+#define D0F2xF4_x56_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x56_CPPrefetchDis_OFFSET                        0
+#define D0F2xF4_x56_CPPrefetchDis_WIDTH                         1
+#define D0F2xF4_x56_CPPrefetchDis_MASK                          0x1
+#define D0F2xF4_x56_CPFlushOnWait_OFFSET                        1
+#define D0F2xF4_x56_CPFlushOnWait_WIDTH                         1
+#define D0F2xF4_x56_CPFlushOnWait_MASK                          0x2
+#define D0F2xF4_x56_CPFlushOnInv_OFFSET                         2
+#define D0F2xF4_x56_CPFlushOnInv_WIDTH                          1
+#define D0F2xF4_x56_CPFlushOnInv_MASK                           0x4
+#define D0F2xF4_x56_Reserved_15_3_OFFSET                        3
+#define D0F2xF4_x56_Reserved_15_3_WIDTH                         13
+#define D0F2xF4_x56_Reserved_15_3_MASK                          0xfff8
+#define D0F2xF4_x56_CPRdDelay_OFFSET                            16
+#define D0F2xF4_x56_CPRdDelay_WIDTH                             16
+#define D0F2xF4_x56_CPRdDelay_MASK                              0xffff0000
+
+/// D0F2xF4_x56
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CPPrefetchDis:1 ; ///<
+    UINT32                                            CPFlushOnWait:1 ; ///<
+    UINT32                                             CPFlushOnInv:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                                CPRdDelay:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x56_STRUCT;
+
+// **** D0F2xF4_x57 Register Definition ****
+// Address
+#define D0F2xF4_x57_ADDRESS                                     0x57
+
+// Type
+#define D0F2xF4_x57_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x57_L1ImuPcieGfxDis_OFFSET                      0
+#define D0F2xF4_x57_L1ImuPcieGfxDis_WIDTH                       1
+#define D0F2xF4_x57_L1ImuPcieGfxDis_MASK                        0x1
+#define D0F2xF4_x57_Reserved_1_1_OFFSET                         1
+#define D0F2xF4_x57_Reserved_1_1_WIDTH                          1
+#define D0F2xF4_x57_Reserved_1_1_MASK                           0x2
+#define D0F2xF4_x57_L1ImuIntGfxDis_OFFSET                       2
+#define D0F2xF4_x57_L1ImuIntGfxDis_WIDTH                        1
+#define D0F2xF4_x57_L1ImuIntGfxDis_MASK                         0x4
+#define D0F2xF4_x57_Reserved_31_3_OFFSET                        3
+#define D0F2xF4_x57_Reserved_31_3_WIDTH                         29
+#define D0F2xF4_x57_Reserved_31_3_MASK                          0xfffffff8
+
+/// D0F2xF4_x57
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L1ImuPcieGfxDis:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                           L1ImuIntGfxDis:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x57_STRUCT;
+
+// **** D0F2xF4_x58 Register Definition ****
+// Address
+#define D0F2xF4_x58_ADDRESS                                     0x58
+
+// Type
+#define D0F2xF4_x58_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x58_IommuL2GuestAddrMask_OFFSET                 0
+#define D0F2xF4_x58_IommuL2GuestAddrMask_WIDTH                  24
+#define D0F2xF4_x58_IommuL2GuestAddrMask_MASK                   0xffffff
+#define D0F2xF4_x58_Reserved_31_24_OFFSET                       24
+#define D0F2xF4_x58_Reserved_31_24_WIDTH                        8
+#define D0F2xF4_x58_Reserved_31_24_MASK                         0xff000000
+
+/// D0F2xF4_x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     IommuL2GuestAddrMask:24; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x58_STRUCT;
+
+// **** D0F2xF4_x60 Register Definition ****
+// Address
+#define D0F2xF4_x60_ADDRESS                                     0x60
+
+// Type
+#define D0F2xF4_x60_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x60_TWDebugEn_OFFSET                            0
+#define D0F2xF4_x60_TWDebugEn_WIDTH                             1
+#define D0F2xF4_x60_TWDebugEn_MASK                              0x1
+#define D0F2xF4_x60_TWDebugNoWrap_OFFSET                        1
+#define D0F2xF4_x60_TWDebugNoWrap_WIDTH                         1
+#define D0F2xF4_x60_TWDebugNoWrap_MASK                          0x2
+#define D0F2xF4_x60_TWDebugForceDisable_OFFSET                  2
+#define D0F2xF4_x60_TWDebugForceDisable_WIDTH                   1
+#define D0F2xF4_x60_TWDebugForceDisable_MASK                    0x4
+#define D0F2xF4_x60_Reserved_14_3_OFFSET                        3
+#define D0F2xF4_x60_Reserved_14_3_WIDTH                         12
+#define D0F2xF4_x60_Reserved_14_3_MASK                          0x7ff8
+#define D0F2xF4_x60_TWDebugMask_OFFSET                          15
+#define D0F2xF4_x60_TWDebugMask_WIDTH                           17
+#define D0F2xF4_x60_TWDebugMask_MASK                            0xffff8000
+
+/// D0F2xF4_x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                TWDebugEn:1 ; ///<
+    UINT32                                            TWDebugNoWrap:1 ; ///<
+    UINT32                                      TWDebugForceDisable:1 ; ///<
+    UINT32                                            Reserved_14_3:12; ///<
+    UINT32                                              TWDebugMask:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x60_STRUCT;
+
+// **** D0F2xF4_x61 Register Definition ****
+// Address
+#define D0F2xF4_x61_ADDRESS                                     0x61
+
+// Type
+#define D0F2xF4_x61_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x61_Reserved_11_0_OFFSET                        0
+#define D0F2xF4_x61_Reserved_11_0_WIDTH                         12
+#define D0F2xF4_x61_Reserved_11_0_MASK                          0xfff
+#define D0F2xF4_x61_TWDebugAddrLo_OFFSET                        12
+#define D0F2xF4_x61_TWDebugAddrLo_WIDTH                         20
+#define D0F2xF4_x61_TWDebugAddrLo_MASK                          0xfffff000
+
+/// D0F2xF4_x61
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                            TWDebugAddrLo:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x61_STRUCT;
+
+// **** D0F2xF4_x62 Register Definition ****
+// Address
+#define D0F2xF4_x62_ADDRESS                                     0x62
+
+// Type
+#define D0F2xF4_x62_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x62_TWDebugAddrHi_OFFSET                        0
+#define D0F2xF4_x62_TWDebugAddrHi_WIDTH                         32
+#define D0F2xF4_x62_TWDebugAddrHi_MASK                          0xffffffff
+
+/// D0F2xF4_x62
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            TWDebugAddrHi:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x62_STRUCT;
+
+// **** D0F2xF4_x6A Register Definition ****
+// Address
+#define D0F2xF4_x6A_ADDRESS                                     0x6a
+
+// Type
+#define D0F2xF4_x6A_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x6A_IntEventOrderEn_OFFSET                      0
+#define D0F2xF4_x6A_IntEventOrderEn_WIDTH                       1
+#define D0F2xF4_x6A_IntEventOrderEn_MASK                        0x1
+#define D0F2xF4_x6A_IntCPOrderEn_OFFSET                         1
+#define D0F2xF4_x6A_IntCPOrderEn_WIDTH                          1
+#define D0F2xF4_x6A_IntCPOrderEn_MASK                           0x2
+#define D0F2xF4_x6A_IntPPROrderEn_OFFSET                        2
+#define D0F2xF4_x6A_IntPPROrderEn_WIDTH                         1
+#define D0F2xF4_x6A_IntPPROrderEn_MASK                          0x4
+#define D0F2xF4_x6A_Reserved_31_3_OFFSET                        3
+#define D0F2xF4_x6A_Reserved_31_3_WIDTH                         29
+#define D0F2xF4_x6A_Reserved_31_3_MASK                          0xfffffff8
+
+/// D0F2xF4_x6A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          IntEventOrderEn:1 ; ///<
+    UINT32                                             IntCPOrderEn:1 ; ///<
+    UINT32                                            IntPPROrderEn:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x6A_STRUCT;
+
+// **** D0F2xF4_x70 Register Definition ****
+// Address
+#define D0F2xF4_x70_ADDRESS                                     0x70
+
+// Type
+#define D0F2xF4_x70_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x70_FC1Credits_OFFSET                           0
+#define D0F2xF4_x70_FC1Credits_WIDTH                            6
+#define D0F2xF4_x70_FC1Credits_MASK                             0x3f
+#define D0F2xF4_x70_Reserved_6_6_OFFSET                         6
+#define D0F2xF4_x70_Reserved_6_6_WIDTH                          1
+#define D0F2xF4_x70_Reserved_6_6_MASK                           0x40
+#define D0F2xF4_x70_FC1Override_OFFSET                          7
+#define D0F2xF4_x70_FC1Override_WIDTH                           1
+#define D0F2xF4_x70_FC1Override_MASK                            0x80
+#define D0F2xF4_x70_FC2Credits_OFFSET                           8
+#define D0F2xF4_x70_FC2Credits_WIDTH                            6
+#define D0F2xF4_x70_FC2Credits_MASK                             0x3f00
+#define D0F2xF4_x70_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x70_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x70_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x70_FC2Override_OFFSET                          15
+#define D0F2xF4_x70_FC2Override_WIDTH                           1
+#define D0F2xF4_x70_FC2Override_MASK                            0x8000
+#define D0F2xF4_x70_FC3Credits_OFFSET                           16
+#define D0F2xF4_x70_FC3Credits_WIDTH                            6
+#define D0F2xF4_x70_FC3Credits_MASK                             0x3f0000
+#define D0F2xF4_x70_Reserved_22_22_OFFSET                       22
+#define D0F2xF4_x70_Reserved_22_22_WIDTH                        1
+#define D0F2xF4_x70_Reserved_22_22_MASK                         0x400000
+#define D0F2xF4_x70_FC3Override_OFFSET                          23
+#define D0F2xF4_x70_FC3Override_WIDTH                           1
+#define D0F2xF4_x70_FC3Override_MASK                            0x800000
+#define D0F2xF4_x70_DTECredits_OFFSET                           24
+#define D0F2xF4_x70_DTECredits_WIDTH                            6
+#define D0F2xF4_x70_DTECredits_MASK                             0x3f000000
+#define D0F2xF4_x70_Reserved_30_30_OFFSET                       30
+#define D0F2xF4_x70_Reserved_30_30_WIDTH                        1
+#define D0F2xF4_x70_Reserved_30_30_MASK                         0x40000000
+#define D0F2xF4_x70_DTEOverride_OFFSET                          31
+#define D0F2xF4_x70_DTEOverride_WIDTH                           1
+#define D0F2xF4_x70_DTEOverride_MASK                            0x80000000
+
+/// D0F2xF4_x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               FC1Credits:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                              FC1Override:1 ; ///<
+    UINT32                                               FC2Credits:6 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                              FC2Override:1 ; ///<
+    UINT32                                               FC3Credits:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                              FC3Override:1 ; ///<
+    UINT32                                               DTECredits:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                              DTEOverride:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x70_STRUCT;
+
+// **** D0F2xF4_x71 Register Definition ****
+// Address
+#define D0F2xF4_x71_ADDRESS                                     0x71
+
+// Type
+#define D0F2xF4_x71_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x71_PDTIECredits_OFFSET                         0
+#define D0F2xF4_x71_PDTIECredits_WIDTH                          6
+#define D0F2xF4_x71_PDTIECredits_MASK                           0x3f
+#define D0F2xF4_x71_Reserved_6_6_OFFSET                         6
+#define D0F2xF4_x71_Reserved_6_6_WIDTH                          1
+#define D0F2xF4_x71_Reserved_6_6_MASK                           0x40
+#define D0F2xF4_x71_PDTIEOverride_OFFSET                        7
+#define D0F2xF4_x71_PDTIEOverride_WIDTH                         1
+#define D0F2xF4_x71_PDTIEOverride_MASK                          0x80
+#define D0F2xF4_x71_TWELCredits_OFFSET                          8
+#define D0F2xF4_x71_TWELCredits_WIDTH                           6
+#define D0F2xF4_x71_TWELCredits_MASK                            0x3f00
+#define D0F2xF4_x71_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x71_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x71_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x71_TWELOverride_OFFSET                         15
+#define D0F2xF4_x71_TWELOverride_WIDTH                          1
+#define D0F2xF4_x71_TWELOverride_MASK                           0x8000
+#define D0F2xF4_x71_CpPrefetchCredits_OFFSET                    16
+#define D0F2xF4_x71_CpPrefetchCredits_WIDTH                     4
+#define D0F2xF4_x71_CpPrefetchCredits_MASK                      0xf0000
+#define D0F2xF4_x71_PprMcifCredits_OFFSET                       20
+#define D0F2xF4_x71_PprMcifCredits_WIDTH                        4
+#define D0F2xF4_x71_PprMcifCredits_MASK                         0xf00000
+#define D0F2xF4_x71_Reserved_31_24_OFFSET                       24
+#define D0F2xF4_x71_Reserved_31_24_WIDTH                        8
+#define D0F2xF4_x71_Reserved_31_24_MASK                         0xff000000
+
+/// D0F2xF4_x71
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PDTIECredits:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                            PDTIEOverride:1 ; ///<
+    UINT32                                              TWELCredits:6 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                             TWELOverride:1 ; ///<
+    UINT32                                        CpPrefetchCredits:4 ; ///<
+    UINT32                                           PprMcifCredits:4 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x71_STRUCT;
+
+// **** D0F2xF4_x78 Register Definition ****
+// Address
+#define D0F2xF4_x78_ADDRESS                                     0x78
+
+// Type
+#define D0F2xF4_x78_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x78_MCIFBaseReadCredits_OFFSET                  0
+#define D0F2xF4_x78_MCIFBaseReadCredits_WIDTH                   5
+#define D0F2xF4_x78_MCIFBaseReadCredits_MASK                    0x1f
+#define D0F2xF4_x78_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x78_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x78_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x78_MCIFIsocReadCredits_OFFSET                  8
+#define D0F2xF4_x78_MCIFIsocReadCredits_WIDTH                   5
+#define D0F2xF4_x78_MCIFIsocReadCredits_MASK                    0x1f00
+#define D0F2xF4_x78_Reserved_15_13_OFFSET                       13
+#define D0F2xF4_x78_Reserved_15_13_WIDTH                        3
+#define D0F2xF4_x78_Reserved_15_13_MASK                         0xe000
+#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_OFFSET              16
+#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_WIDTH               5
+#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_MASK                0x1f0000
+#define D0F2xF4_x78_Reserved_23_21_OFFSET                       21
+#define D0F2xF4_x78_Reserved_23_21_WIDTH                        3
+#define D0F2xF4_x78_Reserved_23_21_MASK                         0xe00000
+#define D0F2xF4_x78_MCIFBaseWriteDataCredits_OFFSET             24
+#define D0F2xF4_x78_MCIFBaseWriteDataCredits_WIDTH              5
+#define D0F2xF4_x78_MCIFBaseWriteDataCredits_MASK               0x1f000000
+#define D0F2xF4_x78_Reserved_31_29_OFFSET                       29
+#define D0F2xF4_x78_Reserved_31_29_WIDTH                        3
+#define D0F2xF4_x78_Reserved_31_29_MASK                         0xe0000000
+
+/// D0F2xF4_x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      MCIFBaseReadCredits:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                      MCIFIsocReadCredits:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                  MCIFBaseWriteHdrCredits:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                 MCIFBaseWriteDataCredits:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x78_STRUCT;
+
+
+
+
+
+
+
+// **** D0F2xF4_x80 Register Definition ****
+// Address
+#define D0F2xF4_x80_ADDRESS                                     0x80
+
+// Type
+#define D0F2xF4_x80_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x80_ERRRuleLock0_OFFSET                         0
+#define D0F2xF4_x80_ERRRuleLock0_WIDTH                          1
+#define D0F2xF4_x80_ERRRuleLock0_MASK                           0x1
+#define D0F2xF4_x80_Reserved_3_1_OFFSET                         1
+#define D0F2xF4_x80_Reserved_3_1_WIDTH                          3
+#define D0F2xF4_x80_Reserved_3_1_MASK                           0xe
+#define D0F2xF4_x80_ERRRuleDisable0_OFFSET                      4
+#define D0F2xF4_x80_ERRRuleDisable0_WIDTH                       28
+#define D0F2xF4_x80_ERRRuleDisable0_MASK                        0xfffffff0
+
+/// D0F2xF4_x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             ERRRuleLock0:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                          ERRRuleDisable0:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x80_STRUCT;
+
+// **** D0F2xF4_x81 Register Definition ****
+// Address
+#define D0F2xF4_x81_ADDRESS                                     0x81
+
+// Type
+#define D0F2xF4_x81_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x81_ERRRuleDisable1_OFFSET                      0
+#define D0F2xF4_x81_ERRRuleDisable1_WIDTH                       32
+#define D0F2xF4_x81_ERRRuleDisable1_MASK                        0xffffffff
+
+/// D0F2xF4_x81
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x81_STRUCT;
+
+// **** D0F2xF4_x82 Register Definition ****
+// Address
+#define D0F2xF4_x82_ADDRESS                                     0x82
+
+// Type
+#define D0F2xF4_x82_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x82_ERRRuleDisable2_OFFSET                      0
+#define D0F2xF4_x82_ERRRuleDisable2_WIDTH                       32
+#define D0F2xF4_x82_ERRRuleDisable2_MASK                        0xffffffff
+
+/// D0F2xF4_x82
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable2:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x82_STRUCT;
+
+// **** D0F2xF4_x90 Register Definition ****
+// Address
+#define D0F2xF4_x90_ADDRESS                                     0x90
+
+// Type
+#define D0F2xF4_x90_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET                 0
+#define D0F2xF4_x90_CKGateL2BRegsDisable_WIDTH                  1
+#define D0F2xF4_x90_CKGateL2BRegsDisable_MASK                   0x1
+#define D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET              1
+#define D0F2xF4_x90_CKGateL2BDynamicDisable_WIDTH               1
+#define D0F2xF4_x90_CKGateL2BDynamicDisable_MASK                0x2
+#define D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET                 2
+#define D0F2xF4_x90_CKGateL2BMiscDisable_WIDTH                  1
+#define D0F2xF4_x90_CKGateL2BMiscDisable_MASK                   0x4
+#define D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET                3
+#define D0F2xF4_x90_CKGateL2BCacheDisable_WIDTH                 1
+#define D0F2xF4_x90_CKGateL2BCacheDisable_MASK                  0x8
+#define D0F2xF4_x90_CKGateL2BLength_OFFSET                      4
+#define D0F2xF4_x90_CKGateL2BLength_WIDTH                       2
+#define D0F2xF4_x90_CKGateL2BLength_MASK                        0x30
+#define D0F2xF4_x90_CKGateL2BStop_OFFSET                        6
+#define D0F2xF4_x90_CKGateL2BStop_WIDTH                         2
+#define D0F2xF4_x90_CKGateL2BStop_MASK                          0xc0
+#define D0F2xF4_x90_Reserved_31_8_OFFSET                        8
+#define D0F2xF4_x90_Reserved_31_8_WIDTH                         24
+#define D0F2xF4_x90_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F2xF4_x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     CKGateL2BRegsDisable:1 ; ///<
+    UINT32                                  CKGateL2BDynamicDisable:1 ; ///<
+    UINT32                                     CKGateL2BMiscDisable:1 ; ///<
+    UINT32                                    CKGateL2BCacheDisable:1 ; ///<
+    UINT32                                          CKGateL2BLength:2 ; ///<
+    UINT32                                            CKGateL2BStop:2 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x90_STRUCT;
+
+// **** D0F2xF4_x92 Register Definition ****
+// Address
+#define D0F2xF4_x92_ADDRESS                                     0x92
+
+// Type
+#define D0F2xF4_x92_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x92_PprInttimedelay_OFFSET                      0
+#define D0F2xF4_x92_PprInttimedelay_WIDTH                       8
+#define D0F2xF4_x92_PprInttimedelay_MASK                        0xff
+#define D0F2xF4_x92_PprIntreqdelay_OFFSET                       8
+#define D0F2xF4_x92_PprIntreqdelay_WIDTH                        8
+#define D0F2xF4_x92_PprIntreqdelay_MASK                         0xff00
+#define D0F2xF4_x92_PprIntcoallesceEn_OFFSET                    16
+#define D0F2xF4_x92_PprIntcoallesceEn_WIDTH                     1
+#define D0F2xF4_x92_PprIntcoallesceEn_MASK                      0x10000
+#define D0F2xF4_x92_Reserved_31_17_OFFSET                       17
+#define D0F2xF4_x92_Reserved_31_17_WIDTH                        15
+#define D0F2xF4_x92_Reserved_31_17_MASK                         0xfffe0000
+
+/// D0F2xF4_x92
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          PprInttimedelay:8 ; ///<
+    UINT32                                           PprIntreqdelay:8 ; ///<
+    UINT32                                        PprIntcoallesceEn:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x92_STRUCT;
+
+// **** D0F2xF4_x94 Register Definition ****
+// Address
+#define D0F2xF4_x94_ADDRESS                                     0x94
+
+// Type
+#define D0F2xF4_x94_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x94_L2bregGstPgsize_OFFSET                      0
+#define D0F2xF4_x94_L2bregGstPgsize_WIDTH                       2
+#define D0F2xF4_x94_L2bregGstPgsize_MASK                        0x3
+#define D0F2xF4_x94_L2bregHostPgsize_OFFSET                     2
+#define D0F2xF4_x94_L2bregHostPgsize_WIDTH                      2
+#define D0F2xF4_x94_L2bregHostPgsize_MASK                       0xc
+#define D0F2xF4_x94_Reserved_31_4_OFFSET                        4
+#define D0F2xF4_x94_Reserved_31_4_WIDTH                         28
+#define D0F2xF4_x94_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F2xF4_x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L2bregGstPgsize:2 ; ///<
+    UINT32                                         L2bregHostPgsize:2 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x94_STRUCT;
+
+// **** D0F2xFC_x32_L1 Register Definition ****
+// Address
+#define D0F2xFC_x32_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x32)
+
+// Type
+#define D0F2xFC_x32_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET                 0
+#define D0F2xFC_x32_L1_AtsMultipleRespEn_WIDTH                  1
+#define D0F2xFC_x32_L1_AtsMultipleRespEn_MASK                   0x1
+#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET               1
+#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_WIDTH                1
+#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK                 0x2
+#define D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET                 2
+#define D0F2xFC_x32_L1_TimeoutPulseExtEn_WIDTH                  1
+#define D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK                   0x4
+#define D0F2xFC_x32_L1_TlpprefixerrEn_OFFSET                    3
+#define D0F2xFC_x32_L1_TlpprefixerrEn_WIDTH                     1
+#define D0F2xFC_x32_L1_TlpprefixerrEn_MASK                      0x8
+#define D0F2xFC_x32_L1_Reserved_31_4_OFFSET                     4
+#define D0F2xFC_x32_L1_Reserved_31_4_WIDTH                      28
+#define D0F2xFC_x32_L1_Reserved_31_4_MASK                       0xfffffff0
+
+/// D0F2xFC_x32_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AtsMultipleRespEn:1 ; ///<
+    UINT32                                      AtsMultipleL1toL2En:1 ; ///<
+    UINT32                                        TimeoutPulseExtEn:1 ; ///<
+    UINT32                                           TlpprefixerrEn:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x32_L1_STRUCT;
+
+// **** D0F2xFC_x11_L1 Register Definition ****
+// Address
+#define D0F2xFC_x11_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x11)
+
+// Type
+#define D0F2xFC_x11_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x11_L1_L1cachelinedis0_OFFSET                   0
+#define D0F2xFC_x11_L1_L1cachelinedis0_WIDTH                    6
+#define D0F2xFC_x11_L1_L1cachelinedis0_MASK                     0x3f
+#define D0F2xFC_x11_L1_Reserved_7_6_OFFSET                      6
+#define D0F2xFC_x11_L1_Reserved_7_6_WIDTH                       2
+#define D0F2xFC_x11_L1_Reserved_7_6_MASK                        0xc0
+#define D0F2xFC_x11_L1_L1cachelinedis1_OFFSET                   8
+#define D0F2xFC_x11_L1_L1cachelinedis1_WIDTH                    6
+#define D0F2xFC_x11_L1_L1cachelinedis1_MASK                     0x3f00
+#define D0F2xFC_x11_L1_Reserved_31_14_OFFSET                    14
+#define D0F2xFC_x11_L1_Reserved_31_14_WIDTH                     18
+#define D0F2xFC_x11_L1_Reserved_31_14_MASK                      0xffffc000
+
+/// D0F2xFC_x11_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L1cachelinedis0:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                          L1cachelinedis1:6 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x11_L1_STRUCT;
+
+// **** D0F2xFC_x34_L1 Register Definition ****
+// Address
+#define D0F2xFC_x34_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x34)
+
+// Type
+#define D0F2xFC_x34_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x34_L1_L1MempwrEn_OFFSET                        0
+#define D0F2xFC_x34_L1_L1MempwrEn_WIDTH                         1
+#define D0F2xFC_x34_L1_L1MempwrEn_MASK                          0x1
+#define D0F2xFC_x34_L1_Reserved_7_1_OFFSET                      1
+#define D0F2xFC_x34_L1_Reserved_7_1_WIDTH                       7
+#define D0F2xFC_x34_L1_Reserved_7_1_MASK                        0xfe
+#define D0F2xFC_x34_L1_L1MempwrTimer0_OFFSET                    8
+#define D0F2xFC_x34_L1_L1MempwrTimer0_WIDTH                     8
+#define D0F2xFC_x34_L1_L1MempwrTimer0_MASK                      0xff00
+#define D0F2xFC_x34_L1_L1MempwrTimer1_OFFSET                    16
+#define D0F2xFC_x34_L1_L1MempwrTimer1_WIDTH                     8
+#define D0F2xFC_x34_L1_L1MempwrTimer1_MASK                      0xff0000
+#define D0F2xFC_x34_L1_L1MempwrTimer2_OFFSET                    24
+#define D0F2xFC_x34_L1_L1MempwrTimer2_WIDTH                     8
+#define D0F2xFC_x34_L1_L1MempwrTimer2_MASK                      0xff000000
+
+/// D0F2xFC_x34_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               L1MempwrEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                           L1MempwrTimer0:8 ; ///<
+    UINT32                                           L1MempwrTimer1:8 ; ///<
+    UINT32                                           L1MempwrTimer2:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x34_L1_STRUCT;
+
+// **** D0F2xFC_x0F_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0F_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0F)
+
+// Type
+#define D0F2xFC_x0F_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_OFFSET               0
+#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_WIDTH                32
+#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_MASK                 0xffffffff
+
+/// D0F2xFC_x0F_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      AtsTlbinvPulseWidth:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0F_L1_STRUCT;
+
+// **** D0F2xFC_x0E_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0E_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0E)
+
+// Type
+#define D0F2xFC_x0E_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0E_L1_Reserved_0_0_OFFSET                      0
+#define D0F2xFC_x0E_L1_Reserved_0_0_WIDTH                       1
+#define D0F2xFC_x0E_L1_Reserved_0_0_MASK                        0x1
+#define D0F2xFC_x0E_L1_MsiToHtRemapDis_OFFSET                   1
+#define D0F2xFC_x0E_L1_MsiToHtRemapDis_WIDTH                    1
+#define D0F2xFC_x0E_L1_MsiToHtRemapDis_MASK                     0x2
+#define D0F2xFC_x0E_L1_L1AbrtAtsDis_OFFSET                      2
+#define D0F2xFC_x0E_L1_L1AbrtAtsDis_WIDTH                       1
+#define D0F2xFC_x0E_L1_L1AbrtAtsDis_MASK                        0x4
+#define D0F2xFC_x0E_L1_Reserved_5_3_OFFSET                      3
+#define D0F2xFC_x0E_L1_Reserved_5_3_WIDTH                       3
+#define D0F2xFC_x0E_L1_Reserved_5_3_MASK                        0x38
+#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_OFFSET                     6
+#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_WIDTH                      3
+#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_MASK                       0x1c0
+#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_OFFSET                  9
+#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_WIDTH                   1
+#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_MASK                    0x200
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_OFFSET                     10
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_WIDTH                      1
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_MASK                       0x400
+#define D0F2xFC_x0E_L1_Reserved_11_11_OFFSET                    11
+#define D0F2xFC_x0E_L1_Reserved_11_11_WIDTH                     1
+#define D0F2xFC_x0E_L1_Reserved_11_11_MASK                      0x800
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_OFFSET            12
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_WIDTH             8
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_MASK              0xff000
+#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_OFFSET                 20
+#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_WIDTH                  8
+#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_MASK                   0xff00000
+#define D0F2xFC_x0E_L1_Reserved_31_28_OFFSET                    28
+#define D0F2xFC_x0E_L1_Reserved_31_28_WIDTH                     4
+#define D0F2xFC_x0E_L1_Reserved_31_28_MASK                      0xf0000000
+
+/// D0F2xFC_x0E_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                          MsiToHtRemapDis:1 ; ///<
+    UINT32                                             L1AbrtAtsDis:1 ; ///<
+    UINT32                                             Reserved_5_3:3 ; ///<
+    UINT32                                            MsiHtRsvIntMt:3 ; ///<
+    UINT32                                         MsiHtRsvIntRqEio:1 ; ///<
+    UINT32                                            MsiHtRsvIntDM:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                   MsiHtRsvIntDestination:8 ; ///<
+    UINT32                                        MsiHtRsvIntVector:8 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0E_L1_STRUCT;
+
+
+// **** D0F2xFC_x37_L1 Register Definition ****
+// Address
+#define D0F2xFC_x37_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x37)
+
+// Type
+#define D0F2xFC_x37_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x37_L1_L1EfrSup_OFFSET                          0
+#define D0F2xFC_x37_L1_L1EfrSup_WIDTH                           1
+#define D0F2xFC_x37_L1_L1EfrSup_MASK                            0x1
+#define D0F2xFC_x37_L1_L1PprSup_OFFSET                          1
+#define D0F2xFC_x37_L1_L1PprSup_WIDTH                           1
+#define D0F2xFC_x37_L1_L1PprSup_MASK                            0x2
+#define D0F2xFC_x37_L1_Reserved_31_2_OFFSET                     2
+#define D0F2xFC_x37_L1_Reserved_31_2_WIDTH                      30
+#define D0F2xFC_x37_L1_Reserved_31_2_MASK                       0xfffffffc
+
+/// D0F2xFC_x37_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L1EfrSup:1 ; ///<
+    UINT32                                                 L1PprSup:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x37_L1_STRUCT;
+
+
+// **** D0F2xFC_x20_L1 Register Definition ****
+// Address
+#define D0F2xFC_x20_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x20)
+
+// Type
+#define D0F2xFC_x20_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x20_L1_EntryStatus0_OFFSET                      0
+#define D0F2xFC_x20_L1_EntryStatus0_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus0_MASK                        0x7
+#define D0F2xFC_x20_L1_EntryStatus1_OFFSET                      3
+#define D0F2xFC_x20_L1_EntryStatus1_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus1_MASK                        0x38
+#define D0F2xFC_x20_L1_EntryStatus2_OFFSET                      6
+#define D0F2xFC_x20_L1_EntryStatus2_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus2_MASK                        0x1c0
+#define D0F2xFC_x20_L1_EntryStatus3_OFFSET                      9
+#define D0F2xFC_x20_L1_EntryStatus3_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus3_MASK                        0xe00
+#define D0F2xFC_x20_L1_EntryStatus4_OFFSET                      12
+#define D0F2xFC_x20_L1_EntryStatus4_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus4_MASK                        0x7000
+#define D0F2xFC_x20_L1_EntryStatus5_OFFSET                      15
+#define D0F2xFC_x20_L1_EntryStatus5_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus5_MASK                        0x38000
+#define D0F2xFC_x20_L1_EntryStatus6_OFFSET                      18
+#define D0F2xFC_x20_L1_EntryStatus6_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus6_MASK                        0x1c0000
+#define D0F2xFC_x20_L1_EntryStatus7_OFFSET                      21
+#define D0F2xFC_x20_L1_EntryStatus7_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus7_MASK                        0xe00000
+#define D0F2xFC_x20_L1_EntryStatus8_OFFSET                      24
+#define D0F2xFC_x20_L1_EntryStatus8_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus8_MASK                        0x7000000
+#define D0F2xFC_x20_L1_EntryStatus9_OFFSET                      27
+#define D0F2xFC_x20_L1_EntryStatus9_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus9_MASK                        0x38000000
+#define D0F2xFC_x20_L1_Reserved_31_30_OFFSET                    30
+#define D0F2xFC_x20_L1_Reserved_31_30_WIDTH                     2
+#define D0F2xFC_x20_L1_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F2xFC_x20_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             EntryStatus0:3 ; ///<
+    UINT32                                             EntryStatus1:3 ; ///<
+    UINT32                                             EntryStatus2:3 ; ///<
+    UINT32                                             EntryStatus3:3 ; ///<
+    UINT32                                             EntryStatus4:3 ; ///<
+    UINT32                                             EntryStatus5:3 ; ///<
+    UINT32                                             EntryStatus6:3 ; ///<
+    UINT32                                             EntryStatus7:3 ; ///<
+    UINT32                                             EntryStatus8:3 ; ///<
+    UINT32                                             EntryStatus9:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x20_L1_STRUCT;
+
+// **** D0F2xFC_x35_L1 Register Definition ****
+// Address
+#define D0F2xFC_x35_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x35)
+
+// Type
+#define D0F2xFC_x35_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x35_L1_L1MempwrTimer3_OFFSET                    0
+#define D0F2xFC_x35_L1_L1MempwrTimer3_WIDTH                     8
+#define D0F2xFC_x35_L1_L1MempwrTimer3_MASK                      0xff
+#define D0F2xFC_x35_L1_Reserved_31_8_OFFSET                     8
+#define D0F2xFC_x35_L1_Reserved_31_8_WIDTH                      24
+#define D0F2xFC_x35_L1_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F2xFC_x35_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           L1MempwrTimer3:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x35_L1_STRUCT;
+
+
+// **** D0F2xFC_x0C_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0C_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0C)
+
+// Type
+#define D0F2xFC_x0C_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0C_L1_UnfilterDis_OFFSET                       0
+#define D0F2xFC_x0C_L1_UnfilterDis_WIDTH                        1
+#define D0F2xFC_x0C_L1_UnfilterDis_MASK                         0x1
+#define D0F2xFC_x0C_L1_FragmentDis_OFFSET                       1
+#define D0F2xFC_x0C_L1_FragmentDis_WIDTH                        1
+#define D0F2xFC_x0C_L1_FragmentDis_MASK                         0x2
+#define D0F2xFC_x0C_L1_CacheirOnly_OFFSET                       2
+#define D0F2xFC_x0C_L1_CacheirOnly_WIDTH                        1
+#define D0F2xFC_x0C_L1_CacheirOnly_MASK                         0x4
+#define D0F2xFC_x0C_L1_CacheiwOnly_OFFSET                       3
+#define D0F2xFC_x0C_L1_CacheiwOnly_WIDTH                        1
+#define D0F2xFC_x0C_L1_CacheiwOnly_MASK                         0x8
+#define D0F2xFC_x0C_L1_Reserved0_OFFSET                         4
+#define D0F2xFC_x0C_L1_Reserved0_WIDTH                          1
+#define D0F2xFC_x0C_L1_Reserved0_MASK                           0x10
+#define D0F2xFC_x0C_L1_ReplacementSel_OFFSET                    5
+#define D0F2xFC_x0C_L1_ReplacementSel_WIDTH                     1
+#define D0F2xFC_x0C_L1_ReplacementSel_MASK                      0x20
+#define D0F2xFC_x0C_L1_Reserved_7_6_OFFSET                      6
+#define D0F2xFC_x0C_L1_Reserved_7_6_WIDTH                       2
+#define D0F2xFC_x0C_L1_Reserved_7_6_MASK                        0xc0
+#define D0F2xFC_x0C_L1_L2Credits_OFFSET                         8
+#define D0F2xFC_x0C_L1_L2Credits_WIDTH                          6
+#define D0F2xFC_x0C_L1_L2Credits_MASK                           0x3f00
+#define D0F2xFC_x0C_L1_Reserved1_OFFSET                         14
+#define D0F2xFC_x0C_L1_Reserved1_WIDTH                          6
+#define D0F2xFC_x0C_L1_Reserved1_MASK                           0xfc000
+#define D0F2xFC_x0C_L1_L1Banks_OFFSET                           20
+#define D0F2xFC_x0C_L1_L1Banks_WIDTH                            2
+#define D0F2xFC_x0C_L1_L1Banks_MASK                             0x300000
+#define D0F2xFC_x0C_L1_Reserved_23_22_OFFSET                    22
+#define D0F2xFC_x0C_L1_Reserved_23_22_WIDTH                     2
+#define D0F2xFC_x0C_L1_Reserved_23_22_MASK                      0xc00000
+#define D0F2xFC_x0C_L1_L1Entries_OFFSET                         24
+#define D0F2xFC_x0C_L1_L1Entries_WIDTH                          4
+#define D0F2xFC_x0C_L1_L1Entries_MASK                           0xf000000
+#define D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET                 28
+#define D0F2xFC_x0C_L1_L1VirtOrderQueues_WIDTH                  3
+#define D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK                   0x70000000
+#define D0F2xFC_x0C_L1_Reserved_31_31_OFFSET                    31
+#define D0F2xFC_x0C_L1_Reserved_31_31_WIDTH                     1
+#define D0F2xFC_x0C_L1_Reserved_31_31_MASK                      0x80000000
+
+/// D0F2xFC_x0C_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              UnfilterDis:1 ; ///<
+    UINT32                                              FragmentDis:1 ; ///<
+    UINT32                                              CacheirOnly:1 ; ///<
+    UINT32                                              CacheiwOnly:1 ; ///<
+    UINT32                                                Reserved0:1 ; ///<
+    UINT32                                           ReplacementSel:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                L2Credits:6 ; ///<
+    UINT32                                                Reserved1:6 ; ///<
+    UINT32                                                  L1Banks:2 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                L1Entries:4 ; ///<
+    UINT32                                        L1VirtOrderQueues:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0C_L1_STRUCT;
+
+
+// **** D0F2xFC_x08_L1 Register Definition ****
+// Address
+#define D0F2xFC_x08_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x08)
+
+// Type
+#define D0F2xFC_x08_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x08_L1_L1debugStatus_OFFSET                     0
+#define D0F2xFC_x08_L1_L1debugStatus_WIDTH                      32
+#define D0F2xFC_x08_L1_L1debugStatus_MASK                       0xffffffff
+
+/// D0F2xFC_x08_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            L1debugStatus:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x08_L1_STRUCT;
+
+
+// **** D0F2xFC_x10_L1 Register Definition ****
+// Address
+#define D0F2xFC_x10_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x10)
+
+// Type
+#define D0F2xFC_x10_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x10_L1_L1cachebanksel0_OFFSET                   0
+#define D0F2xFC_x10_L1_L1cachebanksel0_WIDTH                    16
+#define D0F2xFC_x10_L1_L1cachebanksel0_MASK                     0xffff
+#define D0F2xFC_x10_L1_Reserved_31_16_OFFSET                    16
+#define D0F2xFC_x10_L1_Reserved_31_16_WIDTH                     16
+#define D0F2xFC_x10_L1_Reserved_31_16_MASK                      0xffff0000
+
+/// D0F2xFC_x10_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L1cachebanksel0:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x10_L1_STRUCT;
+
+// **** D0F2xFC_x23_L1 Register Definition ****
+// Address
+#define D0F2xFC_x23_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x23)
+
+// Type
+#define D0F2xFC_x23_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x23_L1_EntryStatus30_OFFSET                     0
+#define D0F2xFC_x23_L1_EntryStatus30_WIDTH                      3
+#define D0F2xFC_x23_L1_EntryStatus30_MASK                       0x7
+#define D0F2xFC_x23_L1_EntryStatus31_OFFSET                     3
+#define D0F2xFC_x23_L1_EntryStatus31_WIDTH                      3
+#define D0F2xFC_x23_L1_EntryStatus31_MASK                       0x38
+#define D0F2xFC_x23_L1_Reserved_7_6_OFFSET                      6
+#define D0F2xFC_x23_L1_Reserved_7_6_WIDTH                       2
+#define D0F2xFC_x23_L1_Reserved_7_6_MASK                        0xc0
+#define D0F2xFC_x23_L1_InvalidationStatus_OFFSET                8
+#define D0F2xFC_x23_L1_InvalidationStatus_WIDTH                 8
+#define D0F2xFC_x23_L1_InvalidationStatus_MASK                  0xff00
+#define D0F2xFC_x23_L1_Reserved_31_16_OFFSET                    16
+#define D0F2xFC_x23_L1_Reserved_31_16_WIDTH                     16
+#define D0F2xFC_x23_L1_Reserved_31_16_MASK                      0xffff0000
+
+/// D0F2xFC_x23_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            EntryStatus30:3 ; ///<
+    UINT32                                            EntryStatus31:3 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                       InvalidationStatus:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x23_L1_STRUCT;
+
+// **** D0F2xFC_x22_L1 Register Definition ****
+// Address
+#define D0F2xFC_x22_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x22)
+
+// Type
+#define D0F2xFC_x22_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x22_L1_EntryStatus20_OFFSET                     0
+#define D0F2xFC_x22_L1_EntryStatus20_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus20_MASK                       0x7
+#define D0F2xFC_x22_L1_EntryStatus21_OFFSET                     3
+#define D0F2xFC_x22_L1_EntryStatus21_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus21_MASK                       0x38
+#define D0F2xFC_x22_L1_EntryStatus22_OFFSET                     6
+#define D0F2xFC_x22_L1_EntryStatus22_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus22_MASK                       0x1c0
+#define D0F2xFC_x22_L1_EntryStatus23_OFFSET                     9
+#define D0F2xFC_x22_L1_EntryStatus23_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus23_MASK                       0xe00
+#define D0F2xFC_x22_L1_EntryStatus24_OFFSET                     12
+#define D0F2xFC_x22_L1_EntryStatus24_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus24_MASK                       0x7000
+#define D0F2xFC_x22_L1_EntryStatus25_OFFSET                     15
+#define D0F2xFC_x22_L1_EntryStatus25_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus25_MASK                       0x38000
+#define D0F2xFC_x22_L1_EntryStatus26_OFFSET                     18
+#define D0F2xFC_x22_L1_EntryStatus26_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus26_MASK                       0x1c0000
+#define D0F2xFC_x22_L1_EntryStatus27_OFFSET                     21
+#define D0F2xFC_x22_L1_EntryStatus27_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus27_MASK                       0xe00000
+#define D0F2xFC_x22_L1_EntryStatus28_OFFSET                     24
+#define D0F2xFC_x22_L1_EntryStatus28_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus28_MASK                       0x7000000
+#define D0F2xFC_x22_L1_EntryStatus29_OFFSET                     27
+#define D0F2xFC_x22_L1_EntryStatus29_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus29_MASK                       0x38000000
+#define D0F2xFC_x22_L1_Reserved_31_30_OFFSET                    30
+#define D0F2xFC_x22_L1_Reserved_31_30_WIDTH                     2
+#define D0F2xFC_x22_L1_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F2xFC_x22_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            EntryStatus20:3 ; ///<
+    UINT32                                            EntryStatus21:3 ; ///<
+    UINT32                                            EntryStatus22:3 ; ///<
+    UINT32                                            EntryStatus23:3 ; ///<
+    UINT32                                            EntryStatus24:3 ; ///<
+    UINT32                                            EntryStatus25:3 ; ///<
+    UINT32                                            EntryStatus26:3 ; ///<
+    UINT32                                            EntryStatus27:3 ; ///<
+    UINT32                                            EntryStatus28:3 ; ///<
+    UINT32                                            EntryStatus29:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x22_L1_STRUCT;
+
+// **** D0F2xFC_x01_L1 Register Definition ****
+// Address
+#define D0F2xFC_x01_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x01)
+
+// Type
+#define D0F2xFC_x01_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x01_L1_L1PerfCount0_OFFSET                      0
+#define D0F2xFC_x01_L1_L1PerfCount0_WIDTH                       32
+#define D0F2xFC_x01_L1_L1PerfCount0_MASK                        0xffffffff
+
+/// D0F2xFC_x01_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1PerfCount0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x01_L1_STRUCT;
+
+// **** D0F2xFC_x36_L1 Register Definition ****
+// Address
+#define D0F2xFC_x36_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x36)
+
+// Type
+#define D0F2xFC_x36_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x36_L1_L1CanonicalErrEn_OFFSET                  0
+#define D0F2xFC_x36_L1_L1CanonicalErrEn_WIDTH                   1
+#define D0F2xFC_x36_L1_L1CanonicalErrEn_MASK                    0x1
+#define D0F2xFC_x36_L1_Reserved_7_1_OFFSET                      1
+#define D0F2xFC_x36_L1_Reserved_7_1_WIDTH                       7
+#define D0F2xFC_x36_L1_Reserved_7_1_MASK                        0xfe
+#define D0F2xFC_x36_L1_L1GuestAddrMsk_OFFSET                    8
+#define D0F2xFC_x36_L1_L1GuestAddrMsk_WIDTH                     24
+#define D0F2xFC_x36_L1_L1GuestAddrMsk_MASK                      0xffffff00
+
+/// D0F2xFC_x36_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         L1CanonicalErrEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                           L1GuestAddrMsk:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x36_L1_STRUCT;
+
+// **** D0F2xFC_x0D_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0D_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0D)
+
+// Type
+#define D0F2xFC_x0D_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0D_L1_VOQPortBits_OFFSET                       0
+#define D0F2xFC_x0D_L1_VOQPortBits_WIDTH                        3
+#define D0F2xFC_x0D_L1_VOQPortBits_MASK                         0x7
+#define D0F2xFC_x0D_L1_Reserved_3_3_OFFSET                      3
+#define D0F2xFC_x0D_L1_Reserved_3_3_WIDTH                       1
+#define D0F2xFC_x0D_L1_Reserved_3_3_MASK                        0x8
+#define D0F2xFC_x0D_L1_VOQFuncBits_OFFSET                       4
+#define D0F2xFC_x0D_L1_VOQFuncBits_WIDTH                        3
+#define D0F2xFC_x0D_L1_VOQFuncBits_MASK                         0x70
+#define D0F2xFC_x0D_L1_Reserved_7_7_OFFSET                      7
+#define D0F2xFC_x0D_L1_Reserved_7_7_WIDTH                       1
+#define D0F2xFC_x0D_L1_Reserved_7_7_MASK                        0x80
+#define D0F2xFC_x0D_L1_VOQXorMode_OFFSET                        8
+#define D0F2xFC_x0D_L1_VOQXorMode_WIDTH                         1
+#define D0F2xFC_x0D_L1_VOQXorMode_MASK                          0x100
+#define D0F2xFC_x0D_L1_CacheByPass_OFFSET                       9
+#define D0F2xFC_x0D_L1_CacheByPass_WIDTH                        1
+#define D0F2xFC_x0D_L1_CacheByPass_MASK                         0x200
+#define D0F2xFC_x0D_L1_L1CacheParityEn_OFFSET                   10
+#define D0F2xFC_x0D_L1_L1CacheParityEn_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1CacheParityEn_MASK                     0x400
+#define D0F2xFC_x0D_L1_L1ParityEn_OFFSET                        11
+#define D0F2xFC_x0D_L1_L1ParityEn_WIDTH                         1
+#define D0F2xFC_x0D_L1_L1ParityEn_MASK                          0x800
+#define D0F2xFC_x0D_L1_L1DTEDis_OFFSET                          12
+#define D0F2xFC_x0D_L1_L1DTEDis_WIDTH                           1
+#define D0F2xFC_x0D_L1_L1DTEDis_MASK                            0x1000
+#define D0F2xFC_x0D_L1_BlockL1Dis_OFFSET                        13
+#define D0F2xFC_x0D_L1_BlockL1Dis_WIDTH                         1
+#define D0F2xFC_x0D_L1_BlockL1Dis_MASK                          0x2000
+#define D0F2xFC_x0D_L1_WqEntrydis_OFFSET                        14
+#define D0F2xFC_x0D_L1_WqEntrydis_WIDTH                         5
+#define D0F2xFC_x0D_L1_WqEntrydis_MASK                          0x7c000
+#define D0F2xFC_x0D_L1_AtsNobufferInsert_OFFSET                 19
+#define D0F2xFC_x0D_L1_AtsNobufferInsert_WIDTH                  1
+#define D0F2xFC_x0D_L1_AtsNobufferInsert_MASK                   0x80000
+#define D0F2xFC_x0D_L1_SndFilterDis_OFFSET                      20
+#define D0F2xFC_x0D_L1_SndFilterDis_WIDTH                       1
+#define D0F2xFC_x0D_L1_SndFilterDis_MASK                        0x100000
+#define D0F2xFC_x0D_L1_L1orderEn_OFFSET                         21
+#define D0F2xFC_x0D_L1_L1orderEn_WIDTH                          1
+#define D0F2xFC_x0D_L1_L1orderEn_MASK                           0x200000
+#define D0F2xFC_x0D_L1_L1CacheInvAllEn_OFFSET                   22
+#define D0F2xFC_x0D_L1_L1CacheInvAllEn_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1CacheInvAllEn_MASK                     0x400000
+#define D0F2xFC_x0D_L1_SelectTimeoutPulse_OFFSET                23
+#define D0F2xFC_x0D_L1_SelectTimeoutPulse_WIDTH                 3
+#define D0F2xFC_x0D_L1_SelectTimeoutPulse_MASK                  0x3800000
+#define D0F2xFC_x0D_L1_L1CacheSelReqid_OFFSET                   26
+#define D0F2xFC_x0D_L1_L1CacheSelReqid_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1CacheSelReqid_MASK                     0x4000000
+#define D0F2xFC_x0D_L1_L1CacheSelInterleave_OFFSET              27
+#define D0F2xFC_x0D_L1_L1CacheSelInterleave_WIDTH               1
+#define D0F2xFC_x0D_L1_L1CacheSelInterleave_MASK                0x8000000
+#define D0F2xFC_x0D_L1_PretransNovaFilteren_OFFSET              28
+#define D0F2xFC_x0D_L1_PretransNovaFilteren_WIDTH               1
+#define D0F2xFC_x0D_L1_PretransNovaFilteren_MASK                0x10000000
+#define D0F2xFC_x0D_L1_Untrans2mFilteren_OFFSET                 29
+#define D0F2xFC_x0D_L1_Untrans2mFilteren_WIDTH                  1
+#define D0F2xFC_x0D_L1_Untrans2mFilteren_MASK                   0x20000000
+#define D0F2xFC_x0D_L1_L1DebugCntrMode_OFFSET                   30
+#define D0F2xFC_x0D_L1_L1DebugCntrMode_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1DebugCntrMode_MASK                     0x40000000
+#define D0F2xFC_x0D_L1_Reserved_31_31_OFFSET                    31
+#define D0F2xFC_x0D_L1_Reserved_31_31_WIDTH                     1
+#define D0F2xFC_x0D_L1_Reserved_31_31_MASK                      0x80000000
+
+/// D0F2xFC_x0D_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              VOQPortBits:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                              VOQFuncBits:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                               VOQXorMode:1 ; ///<
+    UINT32                                              CacheByPass:1 ; ///<
+    UINT32                                          L1CacheParityEn:1 ; ///<
+    UINT32                                               L1ParityEn:1 ; ///<
+    UINT32                                                 L1DTEDis:1 ; ///<
+    UINT32                                               BlockL1Dis:1 ; ///<
+    UINT32                                               WqEntrydis:5 ; ///<
+    UINT32                                        AtsNobufferInsert:1 ; ///<
+    UINT32                                             SndFilterDis:1 ; ///<
+    UINT32                                                L1orderEn:1 ; ///<
+    UINT32                                          L1CacheInvAllEn:1 ; ///<
+    UINT32                                       SelectTimeoutPulse:3 ; ///<
+    UINT32                                          L1CacheSelReqid:1 ; ///<
+    UINT32                                     L1CacheSelInterleave:1 ; ///<
+    UINT32                                     PretransNovaFilteren:1 ; ///<
+    UINT32                                        Untrans2mFilteren:1 ; ///<
+    UINT32                                          L1DebugCntrMode:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0D_L1_STRUCT;
+
+// **** D0F2xFC_x33_L1 Register Definition ****
+// Address
+#define D0F2xFC_x33_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x33)
+
+// Type
+#define D0F2xFC_x33_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x33_L1_L1ClkgateLen_OFFSET                      0
+#define D0F2xFC_x33_L1_L1ClkgateLen_WIDTH                       2
+#define D0F2xFC_x33_L1_L1ClkgateLen_MASK                        0x3
+#define D0F2xFC_x33_L1_Reserved_3_2_OFFSET                      2
+#define D0F2xFC_x33_L1_Reserved_3_2_WIDTH                       2
+#define D0F2xFC_x33_L1_Reserved_3_2_MASK                        0xc
+#define D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET                    4
+#define D0F2xFC_x33_L1_L1DmaClkgateEn_WIDTH                     1
+#define D0F2xFC_x33_L1_L1DmaClkgateEn_MASK                      0x10
+#define D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET                  5
+#define D0F2xFC_x33_L1_L1CacheClkgateEn_WIDTH                   1
+#define D0F2xFC_x33_L1_L1CacheClkgateEn_MASK                    0x20
+#define D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET                  6
+#define D0F2xFC_x33_L1_L1CpslvClkgateEn_WIDTH                   1
+#define D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK                    0x40
+#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET               7
+#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_WIDTH                1
+#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK                 0x80
+#define D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET                   8
+#define D0F2xFC_x33_L1_L1PerfClkgateEn_WIDTH                    1
+#define D0F2xFC_x33_L1_L1PerfClkgateEn_MASK                     0x100
+#define D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET                 9
+#define D0F2xFC_x33_L1_L1MemoryClkgateEn_WIDTH                  1
+#define D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK                   0x200
+#define D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET                    10
+#define D0F2xFC_x33_L1_L1RegClkgateEn_WIDTH                     1
+#define D0F2xFC_x33_L1_L1RegClkgateEn_MASK                      0x400
+#define D0F2xFC_x33_L1_L1HostreqClkgateEn_OFFSET                11
+#define D0F2xFC_x33_L1_L1HostreqClkgateEn_WIDTH                 1
+#define D0F2xFC_x33_L1_L1HostreqClkgateEn_MASK                  0x800
+#define D0F2xFC_x33_L1_Reserved_30_12_OFFSET                    12
+#define D0F2xFC_x33_L1_Reserved_30_12_WIDTH                     19
+#define D0F2xFC_x33_L1_Reserved_30_12_MASK                      0x7ffff000
+#define D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET                     31
+#define D0F2xFC_x33_L1_L1L2ClkgateEn_WIDTH                      1
+#define D0F2xFC_x33_L1_L1L2ClkgateEn_MASK                       0x80000000
+
+/// D0F2xFC_x33_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1ClkgateLen:2 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                           L1DmaClkgateEn:1 ; ///<
+    UINT32                                         L1CacheClkgateEn:1 ; ///<
+    UINT32                                         L1CpslvClkgateEn:1 ; ///<
+    UINT32                                      L1DmaInputClkgateEn:1 ; ///<
+    UINT32                                          L1PerfClkgateEn:1 ; ///<
+    UINT32                                        L1MemoryClkgateEn:1 ; ///<
+    UINT32                                           L1RegClkgateEn:1 ; ///<
+    UINT32                                       L1HostreqClkgateEn:1 ; ///<
+    UINT32                                           Reserved_30_12:19; ///<
+    UINT32                                            L1L2ClkgateEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x33_L1_STRUCT;
+
+
+// **** D0F2xFC_x21_L1 Register Definition ****
+// Address
+#define D0F2xFC_x21_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x21)
+
+// Type
+#define D0F2xFC_x21_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x21_L1_EntryStatus10_OFFSET                     0
+#define D0F2xFC_x21_L1_EntryStatus10_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus10_MASK                       0x7
+#define D0F2xFC_x21_L1_EntryStatus11_OFFSET                     3
+#define D0F2xFC_x21_L1_EntryStatus11_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus11_MASK                       0x38
+#define D0F2xFC_x21_L1_EntryStatus12_OFFSET                     6
+#define D0F2xFC_x21_L1_EntryStatus12_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus12_MASK                       0x1c0
+#define D0F2xFC_x21_L1_EntryStatus13_OFFSET                     9
+#define D0F2xFC_x21_L1_EntryStatus13_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus13_MASK                       0xe00
+#define D0F2xFC_x21_L1_EntryStatus14_OFFSET                     12
+#define D0F2xFC_x21_L1_EntryStatus14_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus14_MASK                       0x7000
+#define D0F2xFC_x21_L1_EntryStatus15_OFFSET                     15
+#define D0F2xFC_x21_L1_EntryStatus15_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus15_MASK                       0x38000
+#define D0F2xFC_x21_L1_EntryStatus16_OFFSET                     18
+#define D0F2xFC_x21_L1_EntryStatus16_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus16_MASK                       0x1c0000
+#define D0F2xFC_x21_L1_EntryStatus17_OFFSET                     21
+#define D0F2xFC_x21_L1_EntryStatus17_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus17_MASK                       0xe00000
+#define D0F2xFC_x21_L1_EntryStatus18_OFFSET                     24
+#define D0F2xFC_x21_L1_EntryStatus18_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus18_MASK                       0x7000000
+#define D0F2xFC_x21_L1_EntryStatus19_OFFSET                     27
+#define D0F2xFC_x21_L1_EntryStatus19_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus19_MASK                       0x38000000
+#define D0F2xFC_x21_L1_Reserved_31_30_OFFSET                    30
+#define D0F2xFC_x21_L1_Reserved_31_30_WIDTH                     2
+#define D0F2xFC_x21_L1_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F2xFC_x21_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            EntryStatus10:3 ; ///<
+    UINT32                                            EntryStatus11:3 ; ///<
+    UINT32                                            EntryStatus12:3 ; ///<
+    UINT32                                            EntryStatus13:3 ; ///<
+    UINT32                                            EntryStatus14:3 ; ///<
+    UINT32                                            EntryStatus15:3 ; ///<
+    UINT32                                            EntryStatus16:3 ; ///<
+    UINT32                                            EntryStatus17:3 ; ///<
+    UINT32                                            EntryStatus18:3 ; ///<
+    UINT32                                            EntryStatus19:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x21_L1_STRUCT;
+
+// **** D0F2xFC_x00_L1 Register Definition ****
+// Address
+#define D0F2xFC_x00_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x00)
+
+// Type
+#define D0F2xFC_x00_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x00_L1_L1PerfEvent0_OFFSET                      0
+#define D0F2xFC_x00_L1_L1PerfEvent0_WIDTH                       8
+#define D0F2xFC_x00_L1_L1PerfEvent0_MASK                        0xff
+#define D0F2xFC_x00_L1_L1PerfEvent1_OFFSET                      8
+#define D0F2xFC_x00_L1_L1PerfEvent1_WIDTH                       8
+#define D0F2xFC_x00_L1_L1PerfEvent1_MASK                        0xff00
+#define D0F2xFC_x00_L1_L1PerfCountHi0_OFFSET                    16
+#define D0F2xFC_x00_L1_L1PerfCountHi0_WIDTH                     8
+#define D0F2xFC_x00_L1_L1PerfCountHi0_MASK                      0xff0000
+#define D0F2xFC_x00_L1_L1PerfCountHi1_OFFSET                    24
+#define D0F2xFC_x00_L1_L1PerfCountHi1_WIDTH                     8
+#define D0F2xFC_x00_L1_L1PerfCountHi1_MASK                      0xff000000
+
+/// D0F2xFC_x00_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1PerfEvent0:8 ; ///<
+    UINT32                                             L1PerfEvent1:8 ; ///<
+    UINT32                                           L1PerfCountHi0:8 ; ///<
+    UINT32                                           L1PerfCountHi1:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x00_L1_STRUCT;
+
+// **** D0F2xFC_x02_L1 Register Definition ****
+// Address
+#define D0F2xFC_x02_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x02)
+
+// Type
+#define D0F2xFC_x02_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x02_L1_L1PerfCount1_OFFSET                      0
+#define D0F2xFC_x02_L1_L1PerfCount1_WIDTH                       32
+#define D0F2xFC_x02_L1_L1PerfCount1_MASK                        0xffffffff
+
+/// D0F2xFC_x02_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1PerfCount1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x02_L1_STRUCT;
+
+
+
+// **** D0F2xFC_x07_L1 Register Definition ****
+// Address
+#define D0F2xFC_x07_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x07)
+
+// Type
+#define D0F2xFC_x07_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x07_L1_PhantomFuncEn_OFFSET                     0
+#define D0F2xFC_x07_L1_PhantomFuncEn_WIDTH                      1
+#define D0F2xFC_x07_L1_PhantomFuncEn_MASK                       0x1
+#define D0F2xFC_x07_L1_Reserved_10_1_OFFSET                     1
+#define D0F2xFC_x07_L1_Reserved_10_1_WIDTH                      10
+#define D0F2xFC_x07_L1_Reserved_10_1_MASK                       0x7fe
+#define D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET                   11
+#define D0F2xFC_x07_L1_SpecReqFilterEn_WIDTH                    1
+#define D0F2xFC_x07_L1_SpecReqFilterEn_MASK                     0x800
+#define D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET                       12
+#define D0F2xFC_x07_L1_AtsSeqNumEn_WIDTH                        1
+#define D0F2xFC_x07_L1_AtsSeqNumEn_MASK                         0x1000
+#define D0F2xFC_x07_L1_Reserved_13_13_OFFSET                    13
+#define D0F2xFC_x07_L1_Reserved_13_13_WIDTH                     1
+#define D0F2xFC_x07_L1_Reserved_13_13_MASK                      0x2000
+#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET             14
+#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_WIDTH              1
+#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK               0x4000
+#define D0F2xFC_x07_L1_Reserved_16_15_OFFSET                    15
+#define D0F2xFC_x07_L1_Reserved_16_15_WIDTH                     2
+#define D0F2xFC_x07_L1_Reserved_16_15_MASK                      0x18000
+#define D0F2xFC_x07_L1_L1NwEn_OFFSET                            17
+#define D0F2xFC_x07_L1_L1NwEn_WIDTH                             1
+#define D0F2xFC_x07_L1_L1NwEn_MASK                              0x20000
+#define D0F2xFC_x07_L1_Reserved_31_18_OFFSET                    18
+#define D0F2xFC_x07_L1_Reserved_31_18_WIDTH                     14
+#define D0F2xFC_x07_L1_Reserved_31_18_MASK                      0xfffc0000
+
+/// D0F2xFC_x07_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PhantomFuncEn:1 ; ///<
+    UINT32                                            Reserved_10_1:10; ///<
+    UINT32                                          SpecReqFilterEn:1 ; ///<
+    UINT32                                              AtsSeqNumEn:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                    AtsPhysPageOverlapDis:1 ; ///<
+    UINT32                                           Reserved_16_15:2 ; ///<
+    UINT32                                                   L1NwEn:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x07_L1_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct1_mp0_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct0_mp0_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct1_mp1_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct0_mp1_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct1_mp0_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct0_mp0_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct1_mp1_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct0_mp1_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct1_mp1_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct1_mp0_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct0_mp1_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct0_mp0_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct1_mp1_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct0_mp0_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct0_mp1_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct1_mp0_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct0_mp0_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct1_mp0_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct1_mp1_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct0_mp1_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct1_mp0_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct0_mp1_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct1_mp1_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct0_mp0_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct0_mp1_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct0_mp0_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct1_mp0_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct1_mp1_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_000B_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000B_dct0_ADDRESS                        0xb
+
+// Type
+#define D18F2x9C_x0000_000B_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_OFFSET           0
+#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_WIDTH            23
+#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_MASK             0x7fffff
+#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_OFFSET      23
+#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_WIDTH       1
+#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_MASK        0x800000
+#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_OFFSET          24
+#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_WIDTH           2
+#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_MASK            0x3000000
+#define D18F2x9C_x0000_000B_dct0_PhyPS_OFFSET                   26
+#define D18F2x9C_x0000_000B_dct0_PhyPS_WIDTH                    1
+#define D18F2x9C_x0000_000B_dct0_PhyPS_MASK                     0x4000000
+#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_OFFSET          27
+#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_WIDTH           3
+#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_MASK            0x38000000
+#define D18F2x9C_x0000_000B_dct0_PhyPSReq_OFFSET                30
+#define D18F2x9C_x0000_000B_dct0_PhyPSReq_WIDTH                 1
+#define D18F2x9C_x0000_000B_dct0_PhyPSReq_MASK                  0x40000000
+#define D18F2x9C_x0000_000B_dct0_DynModeChange_OFFSET           31
+#define D18F2x9C_x0000_000B_dct0_DynModeChange_WIDTH            1
+#define D18F2x9C_x0000_000B_dct0_DynModeChange_MASK             0x80000000
+
+/// D18F2x9C_x0000_000B_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                       PhySelfRefreshMode:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    PhyPS:1 ; ///<
+    UINT32                                           Reserved_29_27:3 ; ///<
+    UINT32                                                 PhyPSReq:1 ; ///<
+    UINT32                                            DynModeChange:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000B_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_000B_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000B_dct1_ADDRESS                        0xb
+
+// Type
+#define D18F2x9C_x0000_000B_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_OFFSET           0
+#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_WIDTH            23
+#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_MASK             0x7fffff
+#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_OFFSET      23
+#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_WIDTH       1
+#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_MASK        0x800000
+#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_OFFSET          24
+#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_WIDTH           2
+#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_MASK            0x3000000
+#define D18F2x9C_x0000_000B_dct1_PhyPS_OFFSET                   26
+#define D18F2x9C_x0000_000B_dct1_PhyPS_WIDTH                    1
+#define D18F2x9C_x0000_000B_dct1_PhyPS_MASK                     0x4000000
+#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_OFFSET          27
+#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_WIDTH           3
+#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_MASK            0x38000000
+#define D18F2x9C_x0000_000B_dct1_PhyPSReq_OFFSET                30
+#define D18F2x9C_x0000_000B_dct1_PhyPSReq_WIDTH                 1
+#define D18F2x9C_x0000_000B_dct1_PhyPSReq_MASK                  0x40000000
+#define D18F2x9C_x0000_000B_dct1_DynModeChange_OFFSET           31
+#define D18F2x9C_x0000_000B_dct1_DynModeChange_WIDTH            1
+#define D18F2x9C_x0000_000B_dct1_DynModeChange_MASK             0x80000000
+
+/// D18F2x9C_x0000_000B_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                       PhySelfRefreshMode:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    PhyPS:1 ; ///<
+    UINT32                                           Reserved_29_27:3 ; ///<
+    UINT32                                                 PhyPSReq:1 ; ///<
+    UINT32                                            DynModeChange:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000B_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_000C_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000C_dct1_ADDRESS                        0xc
+
+// Type
+#define D18F2x9C_x0000_000C_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_000C_dct1_ChipSelTri_OFFSET              0
+#define D18F2x9C_x0000_000C_dct1_ChipSelTri_WIDTH               8
+#define D18F2x9C_x0000_000C_dct1_ChipSelTri_MASK                0xff
+#define D18F2x9C_x0000_000C_dct1_ODTTri_OFFSET                  8
+#define D18F2x9C_x0000_000C_dct1_ODTTri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct1_ODTTri_MASK                    0xf00
+#define D18F2x9C_x0000_000C_dct1_CKETri_OFFSET                  12
+#define D18F2x9C_x0000_000C_dct1_CKETri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct1_CKETri_MASK                    0xf000
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_OFFSET     16
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_WIDTH      5
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_MASK       0x1f0000
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_OFFSET     21
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_MASK       0x3e00000
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_OFFSET     26
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_MASK       0x7c000000
+#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_000C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               ChipSelTri:8 ; ///<
+    UINT32                                                   ODTTri:4 ; ///<
+    UINT32                                                   CKETri:4 ; ///<
+    UINT32                                      FenceThresholdTxPad:5 ; ///<
+    UINT32                                      FenceThresholdRxDll:5 ; ///<
+    UINT32                                      FenceThresholdTxDll:5 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000C_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_000C_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000C_dct0_ADDRESS                        0xc
+
+// Type
+#define D18F2x9C_x0000_000C_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_000C_dct0_ChipSelTri_OFFSET              0
+#define D18F2x9C_x0000_000C_dct0_ChipSelTri_WIDTH               8
+#define D18F2x9C_x0000_000C_dct0_ChipSelTri_MASK                0xff
+#define D18F2x9C_x0000_000C_dct0_ODTTri_OFFSET                  8
+#define D18F2x9C_x0000_000C_dct0_ODTTri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct0_ODTTri_MASK                    0xf00
+#define D18F2x9C_x0000_000C_dct0_CKETri_OFFSET                  12
+#define D18F2x9C_x0000_000C_dct0_CKETri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct0_CKETri_MASK                    0xf000
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_OFFSET     16
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_WIDTH      5
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_MASK       0x1f0000
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_OFFSET     21
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_MASK       0x3e00000
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_OFFSET     26
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_MASK       0x7c000000
+#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_000C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               ChipSelTri:8 ; ///<
+    UINT32                                                   ODTTri:4 ; ///<
+    UINT32                                                   CKETri:4 ; ///<
+    UINT32                                      FenceThresholdTxPad:5 ; ///<
+    UINT32                                      FenceThresholdRxDll:5 ; ///<
+    UINT32                                      FenceThresholdTxDll:5 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000C_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct0_mp1_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct1_mp1_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct0_mp0_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct1_mp0_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct0_mp1_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct1_mp0_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct0_mp0_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct1_mp1_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct1_mp0_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct1_mp1_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct0_mp0_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct0_mp1_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct1_mp1_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct1_mp0_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct0_mp0_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct0_mp1_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct1_mp0_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct0_mp1_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct0_mp0_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct1_mp1_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct0_mp0_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct1_mp1_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct1_mp0_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct0_mp1_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct0_mp1_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct0_mp0_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct1_mp1_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct1_mp0_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct1_mp0_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct0_mp0_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct0_mp1_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct1_mp1_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct1_mp1_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct1_mp0_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct0_mp1_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct0_mp0_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct0_mp1_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct1_mp0_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct1_mp1_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct0_mp0_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct0_mp1_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct1_mp0_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct1_mp1_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct0_mp0_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct0_mp1_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct1_mp0_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct1_mp1_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct0_mp0_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct1_mp1_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct1_mp0_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct0_mp1_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct0_mp0_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct1_mp0_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct0_mp0_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct1_mp1_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct0_mp1_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct0_mp1_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct1_mp0_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct0_mp0_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct1_mp1_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct0_mp0_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct0_mp1_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct1_mp0_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct1_mp1_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct1_mp1_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct0_mp0_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct1_mp0_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct0_mp1_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct1_mp1_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct0_mp1_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct0_mp0_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct1_mp0_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct0_mp0_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct0_mp1_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct1_mp0_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct1_mp1_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct1_mp1_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct1_mp0_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct0_mp0_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct0_mp1_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct0_mp0_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct1_mp1_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct1_mp0_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct0_mp1_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct1_mp1_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct0_mp1_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct1_mp0_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct0_mp0_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct1_mp1_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct0_mp1_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct0_mp0_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct1_mp0_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct0_mp1_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct0_mp0_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct1_mp0_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct1_mp1_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct1_mp0_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct0_mp1_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct0_mp0_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct1_mp1_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct0_mp1_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct1_mp1_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct1_mp0_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct0_mp0_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct1_mp1_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct0_mp0_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct1_mp0_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct0_mp1_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct1_mp0_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct0_mp1_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct1_mp1_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct0_mp0_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct0_mp0_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct1_mp0_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct1_mp1_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct0_mp1_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct1_mp1_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct1_mp0_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct0_mp1_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct0_mp0_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct1_mp1_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct1_mp0_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct0_mp1_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct0_mp0_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct0_mp1_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct0_mp0_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct1_mp1_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct1_mp0_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct0_mp0_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct1_mp1_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct1_mp0_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct0_mp1_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0050_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0050_dct0_ADDRESS                        0x50
+
+// Type
+#define D18F2x9C_x0000_0050_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0050_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0050_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_0050_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0050_dct1_ADDRESS                        0x50
+
+// Type
+#define D18F2x9C_x0000_0050_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0050_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0050_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_0051_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0051_dct1_ADDRESS                        0x51
+
+// Type
+#define D18F2x9C_x0000_0051_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0051_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0051_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_0051_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0051_dct0_ADDRESS                        0x51
+
+// Type
+#define D18F2x9C_x0000_0051_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0051_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0051_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct0_mp1_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct1_mp1_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct1_mp0_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct0_mp0_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct1_mp1_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct1_mp0_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct0_mp0_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct0_mp1_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct1_mp1_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct0_mp1_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct0_mp0_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct1_mp0_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct0_mp1_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct1_mp0_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct0_mp0_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct1_mp1_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct0_mp1_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct1_mp0_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct1_mp1_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct0_mp0_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct1_mp1_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct1_mp0_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct0_mp1_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct0_mp0_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct1_mp1_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct1_mp0_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct0_mp1_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct0_mp0_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct0_mp0_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct1_mp0_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct0_mp1_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct1_mp1_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct1_mp0_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct1_mp1_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct0_mp0_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct0_mp1_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct1_mp1_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct0_mp1_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct1_mp0_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct0_mp0_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct0_mp0_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct1_mp1_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct0_mp1_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct1_mp0_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct0_mp0_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct0_mp1_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct1_mp0_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct1_mp1_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0D0F_E00A_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0D0F_E00A_dct0_ADDRESS                    0x0d0fe00a
+
+// Type
+#define D18F2x9C_x0D0F_E00A_dct0_TYPE                       TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_OFFSET        0
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_WIDTH         4
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_MASK          0xf
+#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_OFFSET          4
+#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_WIDTH           1
+#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_MASK            0x10
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_OFFSET       5
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_WIDTH        7
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_MASK         0xfe0
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_OFFSET      15
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_WIDTH       17
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_MASK        0xffff8000
+
+/// D18F2x9C_x0D0F_E00A_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                               SkewMemClk:1 ; ///<
+    UINT32                                            Reserved_11_5:7 ; ///<
+    UINT32                                        :2 ; ///<
+    UINT32                                          :1 ; ///<
+    UINT32                                          Reserved_31_15:17 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0D0F_E00A_dct0_STRUCT;
+
+// **** D18F2x9C_x0D0F_E00A_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0D0F_E00A_dct1_ADDRESS                    0x0d0fe00a
+
+// Type
+#define D18F2x9C_x0D0F_E00A_dct1_TYPE                       TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_OFFSET        0
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_WIDTH         4
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_MASK          0xf
+#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_OFFSET          4
+#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_WIDTH           1
+#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_MASK            0x10
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_OFFSET       5
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_WIDTH        7
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_MASK         0xfe0
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_OFFSET      15
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_WIDTH       17
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_MASK        0xffff8000
+
+/// D18F2x9C_x0D0F_E00A_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                               SkewMemClk:1 ; ///<
+    UINT32                                            Reserved_11_5:7 ; ///<
+    UINT32                                        :2 ; ///<
+    UINT32                                          :1 ; ///<
+    UINT32                                          Reserved_31_15:17 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0D0F_E00A_dct1_STRUCT;
+
+
+// **** DxF0xE4_x01 Register Definition ****
+// Address
+#define DxF0xE4_x01_ADDRESS                                     0x1
+
+// Type
+#define DxF0xE4_x01_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x01_Scratch_OFFSET                              0
+#define DxF0xE4_x01_Scratch_WIDTH                               32
+#define DxF0xE4_x01_Scratch_MASK                                0xffffffff
+
+/// DxF0xE4_x01
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Scratch:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x01_STRUCT;
+
+// **** DxF0xE4_x02 Register Definition ****
+// Address
+#define DxF0xE4_x02_ADDRESS                                     0x2
+
+// Type
+#define DxF0xE4_x02_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x02_Reserved_14_0_OFFSET                        0
+#define DxF0xE4_x02_Reserved_14_0_WIDTH                         15
+#define DxF0xE4_x02_Reserved_14_0_MASK                          0x7fff
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET               15
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH                1
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK                 0x8000
+#define DxF0xE4_x02_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_x02_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_x02_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_x02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                   RegsLcAllowTxL1Control:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x02_STRUCT;
+
+// **** DxF0xE4_x50 Register Definition ****
+// Address
+#define DxF0xE4_x50_ADDRESS                                     0x50
+
+// Type
+#define DxF0xE4_x50_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x50_PortLaneReversal_OFFSET                     0
+#define DxF0xE4_x50_PortLaneReversal_WIDTH                      1
+#define DxF0xE4_x50_PortLaneReversal_MASK                       0x1
+#define DxF0xE4_x50_PhyLinkWidth_OFFSET                         1
+#define DxF0xE4_x50_PhyLinkWidth_WIDTH                          6
+#define DxF0xE4_x50_PhyLinkWidth_MASK                           0x7e
+#define DxF0xE4_x50_Reserved_31_7_OFFSET                        7
+#define DxF0xE4_x50_Reserved_31_7_WIDTH                         25
+#define DxF0xE4_x50_Reserved_31_7_MASK                          0xffffff80
+
+/// DxF0xE4_x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PortLaneReversal:1 ; ///<
+    UINT32                                             PhyLinkWidth:6 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x50_STRUCT;
+
+// **** DxF0xE4_x70 Register Definition ****
+// Address
+#define DxF0xE4_x70_ADDRESS                                     0x70
+
+// Type
+#define DxF0xE4_x70_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x70_Reserved_15_0_OFFSET                        0
+#define DxF0xE4_x70_Reserved_15_0_WIDTH                         16
+#define DxF0xE4_x70_Reserved_15_0_MASK                          0xffff
+#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET                      16
+#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH                       3
+#define DxF0xE4_x70_RxRcbCplTimeout_MASK                        0x70000
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET                  19
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH                   1
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK                    0x80000
+#define DxF0xE4_x70_Reserved_31_20_OFFSET                       20
+#define DxF0xE4_x70_Reserved_31_20_WIDTH                        12
+#define DxF0xE4_x70_Reserved_31_20_MASK                         0xfff00000
+
+/// DxF0xE4_x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                          RxRcbCplTimeout:3 ; ///<
+    UINT32                                      RxRcbCplTimeoutMode:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x70_STRUCT;
+
+// **** DxF0xE4_xA0 Register Definition ****
+// Address
+#define DxF0xE4_xA0_ADDRESS                                     0xa0
+
+// Type
+#define DxF0xE4_xA0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA0_Reserved_3_0_OFFSET                         0
+#define DxF0xE4_xA0_Reserved_3_0_WIDTH                          4
+#define DxF0xE4_xA0_Reserved_3_0_MASK                           0xf
+#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET                     4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH                      4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK                       0xf0
+#define DxF0xE4_xA0_LcL0sInactivity_OFFSET                      8
+#define DxF0xE4_xA0_LcL0sInactivity_WIDTH                       4
+#define DxF0xE4_xA0_LcL0sInactivity_MASK                        0xf00
+#define DxF0xE4_xA0_LcL1Inactivity_OFFSET                       12
+#define DxF0xE4_xA0_LcL1Inactivity_WIDTH                        4
+#define DxF0xE4_xA0_LcL1Inactivity_MASK                         0xf000
+#define DxF0xE4_xA0_Reserved_22_16_OFFSET                       16
+#define DxF0xE4_xA0_Reserved_22_16_WIDTH                        7
+#define DxF0xE4_xA0_Reserved_22_16_MASK                         0x7f0000
+#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET                     23
+#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH                      1
+#define DxF0xE4_xA0_LcL1ImmediateAck_MASK                       0x800000
+#define DxF0xE4_xA0_Reserved_31_24_OFFSET                       24
+#define DxF0xE4_xA0_Reserved_31_24_WIDTH                        8
+#define DxF0xE4_xA0_Reserved_31_24_MASK                         0xff000000
+
+/// DxF0xE4_xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                         Lc16xClearTxPipe:4 ; ///<
+    UINT32                                          LcL0sInactivity:4 ; ///<
+    UINT32                                           LcL1Inactivity:4 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                         LcL1ImmediateAck:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA0_STRUCT;
+
+// **** DxF0xE4_xA1 Register Definition ****
+// Address
+#define DxF0xE4_xA1_ADDRESS                                     0xa1
+
+// Type
+#define DxF0xE4_xA1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA1_Reserved_10_0_OFFSET                        0
+#define DxF0xE4_xA1_Reserved_10_0_WIDTH                         11
+#define DxF0xE4_xA1_Reserved_10_0_MASK                          0x7ff
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET               11
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH                1
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK                 0x800
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET                12
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH                 1
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK                  0x1000
+#define DxF0xE4_xA1_Reserved_31_13_OFFSET                       13
+#define DxF0xE4_xA1_Reserved_31_13_WIDTH                        19
+#define DxF0xE4_xA1_Reserved_31_13_MASK                         0xffffe000
+
+/// DxF0xE4_xA1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_10_0:11; ///<
+    UINT32                                   LcDontGotoL0sifL1Armed:1 ; ///<
+    UINT32                                    LcInitSpdChgWithCsrEn:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA1_STRUCT;
+
+// **** DxF0xE4_xA2 Register Definition ****
+// Address
+#define DxF0xE4_xA2_ADDRESS                                     0xa2
+
+// Type
+#define DxF0xE4_xA2_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA2_LcLinkWidth_OFFSET                          0
+#define DxF0xE4_xA2_LcLinkWidth_WIDTH                           3
+#define DxF0xE4_xA2_LcLinkWidth_MASK                            0x7
+#define DxF0xE4_xA2_Reserved_3_3_OFFSET                         3
+#define DxF0xE4_xA2_Reserved_3_3_WIDTH                          1
+#define DxF0xE4_xA2_Reserved_3_3_MASK                           0x8
+#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET                        4
+#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH                         3
+#define DxF0xE4_xA2_LcLinkWidthRd_MASK                          0x70
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET           7
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH            1
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK             0x80
+#define DxF0xE4_xA2_LcReconfigNow_OFFSET                        8
+#define DxF0xE4_xA2_LcReconfigNow_WIDTH                         1
+#define DxF0xE4_xA2_LcReconfigNow_MASK                          0x100
+#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET               9
+#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH                1
+#define DxF0xE4_xA2_LcRenegotiationSupport_MASK                 0x200
+#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET                      10
+#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH                       1
+#define DxF0xE4_xA2_LcRenegotiateEn_MASK                        0x400
+#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET                    11
+#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH                     1
+#define DxF0xE4_xA2_LcShortReconfigEn_MASK                      0x800
+#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET                 12
+#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH                  1
+#define DxF0xE4_xA2_LcUpconfigureSupport_MASK                   0x1000
+#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET                     13
+#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH                      1
+#define DxF0xE4_xA2_LcUpconfigureDis_MASK                       0x2000
+#define DxF0xE4_xA2_Reserved_19_14_OFFSET                       14
+#define DxF0xE4_xA2_Reserved_19_14_WIDTH                        6
+#define DxF0xE4_xA2_Reserved_19_14_MASK                         0xfc000
+#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET                    20
+#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH                     1
+#define DxF0xE4_xA2_LcUpconfigCapable_MASK                      0x100000
+#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET                   21
+#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH                    2
+#define DxF0xE4_xA2_LcDynLanesPwrState_MASK                     0x600000
+#define DxF0xE4_xA2_Reserved_31_23_OFFSET                       23
+#define DxF0xE4_xA2_Reserved_31_23_WIDTH                        9
+#define DxF0xE4_xA2_Reserved_31_23_MASK                         0xff800000
+
+/// DxF0xE4_xA2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LcLinkWidth:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            LcLinkWidthRd:3 ; ///<
+    UINT32                               LcReconfigArcMissingEscape:1 ; ///<
+    UINT32                                            LcReconfigNow:1 ; ///<
+    UINT32                                   LcRenegotiationSupport:1 ; ///<
+    UINT32                                          LcRenegotiateEn:1 ; ///<
+    UINT32                                        LcShortReconfigEn:1 ; ///<
+    UINT32                                     LcUpconfigureSupport:1 ; ///<
+    UINT32                                         LcUpconfigureDis:1 ; ///<
+    UINT32                                           Reserved_19_14:6 ; ///<
+    UINT32                                        LcUpconfigCapable:1 ; ///<
+    UINT32                                       LcDynLanesPwrState:2 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA2_STRUCT;
+
+// **** DxF0xE4_xA3 Register Definition ****
+// Address
+#define DxF0xE4_xA3_ADDRESS                                     0xa3
+
+// Type
+#define DxF0xE4_xA3_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA3_Reserved_8_0_OFFSET                         0
+#define DxF0xE4_xA3_Reserved_8_0_WIDTH                          9
+#define DxF0xE4_xA3_Reserved_8_0_MASK                           0x1ff
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET              9
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH               1
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK                0x200
+#define DxF0xE4_xA3_Reserved_31_10_OFFSET                       10
+#define DxF0xE4_xA3_Reserved_31_10_WIDTH                        22
+#define DxF0xE4_xA3_Reserved_31_10_MASK                         0xfffffc00
+
+/// DxF0xE4_xA3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                  LcXmitFtsBeforeRecovery:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA3_STRUCT;
+
+// **** DxF0xE4_xA4 Register Definition ****
+// Address
+#define DxF0xE4_xA4_ADDRESS                                     0xa4
+
+// Type
+#define DxF0xE4_xA4_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET                        0
+#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH                         1
+#define DxF0xE4_xA4_LcGen2EnStrap_MASK                          0x1
+#define DxF0xE4_xA4_Reserved_5_1_OFFSET                         1
+#define DxF0xE4_xA4_Reserved_5_1_WIDTH                          5
+#define DxF0xE4_xA4_Reserved_5_1_MASK                           0x3e
+#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET              6
+#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH               1
+#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK                0x40
+#define DxF0xE4_xA4_Reserved_8_7_OFFSET                         7
+#define DxF0xE4_xA4_Reserved_8_7_WIDTH                          2
+#define DxF0xE4_xA4_Reserved_8_7_MASK                           0x180
+#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET            9
+#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH             1
+#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK              0x200
+#define DxF0xE4_xA4_Reserved_11_10_OFFSET                       10
+#define DxF0xE4_xA4_Reserved_11_10_WIDTH                        2
+#define DxF0xE4_xA4_Reserved_11_10_MASK                         0xc00
+#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET           12
+#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH            1
+#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK             0x1000
+#define DxF0xE4_xA4_Reserved_18_13_OFFSET                       13
+#define DxF0xE4_xA4_Reserved_18_13_WIDTH                        6
+#define DxF0xE4_xA4_Reserved_18_13_MASK                         0x7e000
+#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET              19
+#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH               1
+#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK                0x80000
+#define DxF0xE4_xA4_Reserved_26_20_OFFSET                       20
+#define DxF0xE4_xA4_Reserved_26_20_WIDTH                        7
+#define DxF0xE4_xA4_Reserved_26_20_MASK                         0x7f00000
+#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET          27
+#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH           1
+#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK            0x8000000
+#define DxF0xE4_xA4_Reserved_31_28_OFFSET                       28
+#define DxF0xE4_xA4_Reserved_31_28_WIDTH                        4
+#define DxF0xE4_xA4_Reserved_31_28_MASK                         0xf0000000
+
+/// DxF0xE4_xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LcGen2EnStrap:1 ; ///<
+    UINT32                                             Reserved_5_1:5 ; ///<
+    UINT32                                  LcForceDisSwSpeedChange:1 ; ///<
+    UINT32                                             Reserved_8_7:2 ; ///<
+    UINT32                                LcInitiateLinkSpeedChange:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                               LcSpeedChangeAttemptFailed:1 ; ///<
+    UINT32                                           Reserved_18_13:6 ; ///<
+    UINT32                                  LcOtherSideSupportsGen2:1 ; ///<
+    UINT32                                           Reserved_26_20:7 ; ///<
+    UINT32                              LcMultUpstreamAutoSpdChngEn:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA4_STRUCT;
+
+// **** DxF0xE4_xA5 Register Definition ****
+// Address
+#define DxF0xE4_xA5_ADDRESS                                     0xa5
+
+// Type
+#define DxF0xE4_xA5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA5_LcCurrentState_OFFSET                       0
+#define DxF0xE4_xA5_LcCurrentState_WIDTH                        6
+#define DxF0xE4_xA5_LcCurrentState_MASK                         0x3f
+#define DxF0xE4_xA5_Reserved_7_6_OFFSET                         6
+#define DxF0xE4_xA5_Reserved_7_6_WIDTH                          2
+#define DxF0xE4_xA5_Reserved_7_6_MASK                           0xc0
+#define DxF0xE4_xA5_LcPrevState1_OFFSET                         8
+#define DxF0xE4_xA5_LcPrevState1_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState1_MASK                           0x3f00
+#define DxF0xE4_xA5_Reserved_15_14_OFFSET                       14
+#define DxF0xE4_xA5_Reserved_15_14_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_15_14_MASK                         0xc000
+#define DxF0xE4_xA5_LcPrevState2_OFFSET                         16
+#define DxF0xE4_xA5_LcPrevState2_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState2_MASK                           0x3f0000
+#define DxF0xE4_xA5_Reserved_23_22_OFFSET                       22
+#define DxF0xE4_xA5_Reserved_23_22_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_23_22_MASK                         0xc00000
+#define DxF0xE4_xA5_LcPrevState3_OFFSET                         24
+#define DxF0xE4_xA5_LcPrevState3_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState3_MASK                           0x3f000000
+#define DxF0xE4_xA5_Reserved_31_30_OFFSET                       30
+#define DxF0xE4_xA5_Reserved_31_30_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_31_30_MASK                         0xc0000000
+
+/// DxF0xE4_xA5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LcCurrentState:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                             LcPrevState1:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                             LcPrevState2:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                             LcPrevState3:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA5_STRUCT;
+
+// **** DxF0xE4_xB1 Register Definition ****
+// Address
+#define DxF0xE4_xB1_ADDRESS                                     0xb1
+
+// Type
+#define DxF0xE4_xB1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB1_Reserved_18_0_OFFSET                        0
+#define DxF0xE4_xB1_Reserved_18_0_WIDTH                         19
+#define DxF0xE4_xB1_Reserved_18_0_MASK                          0x7ffff
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET                  19
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH                   1
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK                    0x80000
+#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET                    20
+#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH                     1
+#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK                      0x100000
+#define DxF0xE4_xB1_Reserved_31_21_OFFSET                       21
+#define DxF0xE4_xB1_Reserved_31_21_WIDTH                        11
+#define DxF0xE4_xB1_Reserved_31_21_MASK                         0xffe00000
+
+/// DxF0xE4_xB1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_18_0:19; ///<
+    UINT32                                      LcDeassertRxEnInL0s:1 ; ///<
+    UINT32                                        LcBlockElIdleinL0:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB1_STRUCT;
+
+// **** DxF0xE4_xB5 Register Definition ****
+// Address
+#define DxF0xE4_xB5_ADDRESS                                     0xb5
+
+// Type
+#define DxF0xE4_xB5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET                   0
+#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH                    1
+#define DxF0xE4_xB5_LcSelectDeemphasis_MASK                     0x1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET               1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH                2
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK                 0x6
+#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET                     3
+#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH                      1
+#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK                       0x8
+#define DxF0xE4_xB5_Reserved_29_4_OFFSET                        4
+#define DxF0xE4_xB5_Reserved_29_4_WIDTH                         26
+#define DxF0xE4_xB5_Reserved_29_4_MASK                          0x3ffffff0
+#define DxF0xE4_xB5_LcGoToRecovery_OFFSET                       30
+#define DxF0xE4_xB5_LcGoToRecovery_WIDTH                        1
+#define DxF0xE4_xB5_LcGoToRecovery_MASK                         0x40000000
+#define DxF0xE4_xB5_Reserved_31_31_OFFSET                       31
+#define DxF0xE4_xB5_Reserved_31_31_WIDTH                        1
+#define DxF0xE4_xB5_Reserved_31_31_MASK                         0x80000000
+
+/// DxF0xE4_xB5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       LcSelectDeemphasis:1 ; ///<
+    UINT32                                   LcSelectDeemphasisCntl:2 ; ///<
+    UINT32                                         LcRcvdDeemphasis:1 ; ///<
+    UINT32                                            Reserved_29_4:26; ///<
+    UINT32                                           LcGoToRecovery:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB5_STRUCT;
+
+// **** DxF0xE4_xC0 Register Definition ****
+// Address
+#define DxF0xE4_xC0_ADDRESS                                     0xc0
+
+// Type
+#define DxF0xE4_xC0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xC0_Reserved_12_0_OFFSET                        0
+#define DxF0xE4_xC0_Reserved_12_0_WIDTH                         13
+#define DxF0xE4_xC0_Reserved_12_0_MASK                          0x1fff
+#define DxF0xE4_xC0_StrapForceCompliance_OFFSET                 13
+#define DxF0xE4_xC0_StrapForceCompliance_WIDTH                  1
+#define DxF0xE4_xC0_StrapForceCompliance_MASK                   0x2000
+#define DxF0xE4_xC0_Reserved_14_14_OFFSET                       14
+#define DxF0xE4_xC0_Reserved_14_14_WIDTH                        1
+#define DxF0xE4_xC0_Reserved_14_14_MASK                         0x4000
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET       15
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH        1
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK         0x8000
+#define DxF0xE4_xC0_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_xC0_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_xC0_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_xC0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_12_0:13; ///<
+    UINT32                                     StrapForceCompliance:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                           StrapAutoRcSpeedNegotiationDis:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xC0_STRUCT;
+
+// **** DxF0xE4_xC1 Register Definition ****
+// Address
+#define DxF0xE4_xC1_ADDRESS                                     0xc1
+
+// Type
+#define DxF0xE4_xC1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xC1_StrapReverseLanes_OFFSET                    0
+#define DxF0xE4_xC1_StrapReverseLanes_WIDTH                     1
+#define DxF0xE4_xC1_StrapReverseLanes_MASK                      0x1
+#define DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET                     1
+#define DxF0xE4_xC1_StrapE2EPrefixEn_WIDTH                      1
+#define DxF0xE4_xC1_StrapE2EPrefixEn_MASK                       0x2
+#define DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET            2
+#define DxF0xE4_xC1_StrapExtendedFmtSupported_WIDTH             1
+#define DxF0xE4_xC1_StrapExtendedFmtSupported_MASK              0x4
+#define DxF0xE4_xC1_Reserved_31_3_OFFSET                        3
+#define DxF0xE4_xC1_Reserved_31_3_WIDTH                         29
+#define DxF0xE4_xC1_Reserved_31_3_MASK                          0xfffffff8
+
+/// DxF0xE4_xC1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        StrapReverseLanes:1 ; ///<
+    UINT32                                         StrapE2EPrefixEn:1 ; ///<
+    UINT32                                StrapExtendedFmtSupported:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xC1_STRUCT;
+
+// **** GMMx00 Register Definition ****
+// Address
+#define GMMx00_ADDRESS                                          0x0
+
+// Type
+#define GMMx00_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx00_MM_OFFSET_OFFSET                                 0
+#define GMMx00_MM_OFFSET_WIDTH                                  31
+#define GMMx00_MM_OFFSET_MASK                                   0x7fffffff
+#define GMMx00_MM_APER_OFFSET                                   31
+#define GMMx00_MM_APER_WIDTH                                    1
+#define GMMx00_MM_APER_MASK                                     0x80000000
+
+/// GMMx00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                MM_OFFSET:31; ///<
+    UINT32                                                  MM_APER:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx00_STRUCT;
+
+// **** GMMx04 Register Definition ****
+// Address
+#define GMMx04_ADDRESS                                          0x4
+
+// Type
+#define GMMx04_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx04_MM_DATA_OFFSET                                   0
+#define GMMx04_MM_DATA_WIDTH                                    32
+#define GMMx04_MM_DATA_MASK                                     0xffffffff
+
+/// GMMx04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  MM_DATA:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx04_STRUCT;
+
+// **** GMMx63C Register Definition ****
+// Address
+#define GMMx63C_ADDRESS                                         0x63c
+
+// Type
+#define GMMx63C_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx63C_VoltageForceEn_OFFSET                           0
+#define GMMx63C_VoltageForceEn_WIDTH                            1
+#define GMMx63C_VoltageForceEn_MASK                             0x1
+#define GMMx63C_VoltageChangeEn_OFFSET                          1
+#define GMMx63C_VoltageChangeEn_WIDTH                           1
+#define GMMx63C_VoltageChangeEn_MASK                            0x2
+#define GMMx63C_VoltageChangeReq_OFFSET                         2
+#define GMMx63C_VoltageChangeReq_WIDTH                          1
+#define GMMx63C_VoltageChangeReq_MASK                           0x4
+#define GMMx63C_Reserved_7_3_OFFSET                             3
+#define GMMx63C_Reserved_7_3_WIDTH                              5
+#define GMMx63C_Reserved_7_3_MASK                               0xf8
+#define GMMx63C_VoltageLevel_OFFSET                             8
+#define GMMx63C_VoltageLevel_WIDTH                              8
+#define GMMx63C_VoltageLevel_MASK                               0xff00
+#define GMMx63C_Reserved_31_16_OFFSET                           16
+#define GMMx63C_Reserved_31_16_WIDTH                            16
+#define GMMx63C_Reserved_31_16_MASK                             0xffff0000
+
+/// GMMx63C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                             VoltageLevel:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx63C_STRUCT;
+
+// **** GMMx640 Register Definition ****
+// Address
+#define GMMx640_ADDRESS                                         0x640
+
+// Type
+#define GMMx640_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx640_VoltageChangeAck_OFFSET                         0
+#define GMMx640_VoltageChangeAck_WIDTH                          1
+#define GMMx640_VoltageChangeAck_MASK                           0x1
+#define GMMx640_CurrentVoltageLevel_OFFSET                      1
+#define GMMx640_CurrentVoltageLevel_WIDTH                       8
+#define GMMx640_CurrentVoltageLevel_MASK                        0x1fe
+#define GMMx640_Reserved_31_9_OFFSET                            9
+#define GMMx640_Reserved_31_9_WIDTH                             23
+#define GMMx640_Reserved_31_9_MASK                              0xfffffe00
+
+/// GMMx640
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:8 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx640_STRUCT;
+
+
+
+// **** GMMx770 Register Definition ****
+// Address
+#define GMMx770_ADDRESS                                         0x770
+
+// Type
+#define GMMx770_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx770_VoltageChangeReq_OFFSET                         0
+#define GMMx770_VoltageChangeReq_WIDTH                          1
+#define GMMx770_VoltageChangeReq_MASK                           0x1
+#define GMMx770_VoltageLevel_OFFSET                             1
+#define GMMx770_VoltageLevel_WIDTH                              8
+#define GMMx770_VoltageLevel_MASK                               0x1fe
+#define GMMx770_VoltageChangeEn_OFFSET                          9
+#define GMMx770_VoltageChangeEn_WIDTH                           1
+#define GMMx770_VoltageChangeEn_MASK                            0x200
+#define GMMx770_VoltageForceEn_OFFSET                           10
+#define GMMx770_VoltageForceEn_WIDTH                            1
+#define GMMx770_VoltageForceEn_MASK                             0x400
+#define GMMx770_Reserved_31_11_OFFSET                           11
+#define GMMx770_Reserved_31_11_WIDTH                            21
+#define GMMx770_Reserved_31_11_MASK                             0xfffff800
+
+/// GMMx770
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             VoltageLevel:8 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx770_STRUCT;
+
+// **** GMMx774 Register Definition ****
+// Address
+#define GMMx774_ADDRESS                                         0x774
+
+// Type
+#define GMMx774_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx774_VoltageChangeAck_OFFSET                         0
+#define GMMx774_VoltageChangeAck_WIDTH                          1
+#define GMMx774_VoltageChangeAck_MASK                           0x1
+#define GMMx774_CurrentVoltageLevel_OFFSET                      1
+#define GMMx774_CurrentVoltageLevel_WIDTH                       8
+#define GMMx774_CurrentVoltageLevel_MASK                        0x1fe
+#define GMMx774_Reserved_31_9_OFFSET                            9
+#define GMMx774_Reserved_31_9_WIDTH                             23
+#define GMMx774_Reserved_31_9_MASK                              0xfffffe00
+
+/// GMMx774
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:8 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx774_STRUCT;
+
+// **** GMMx7A0 Register Definition ****
+// Address
+#define GMMx7A0_ADDRESS                                         0x7a0
+
+// Type
+#define GMMx7A0_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx7A0_DivId_OFFSET                                    0
+#define GMMx7A0_DivId_WIDTH                                     3
+#define GMMx7A0_DivId_MASK                                      0x7
+#define GMMx7A0_RampDis_OFFSET                                  3
+#define GMMx7A0_RampDis_WIDTH                                   1
+#define GMMx7A0_RampDis_MASK                                    0x8
+#define GMMx7A0_Hysteresis_OFFSET                               4
+#define GMMx7A0_Hysteresis_WIDTH                                12
+#define GMMx7A0_Hysteresis_MASK                                 0xfff0
+#define GMMx7A0_SclkRunningMask_OFFSET                          16
+#define GMMx7A0_SclkRunningMask_WIDTH                           1
+#define GMMx7A0_SclkRunningMask_MASK                            0x10000
+#define GMMx7A0_SmuBusyMask_OFFSET                              17
+#define GMMx7A0_SmuBusyMask_WIDTH                               1
+#define GMMx7A0_SmuBusyMask_MASK                                0x20000
+#define GMMx7A0_PcieLclkIdle1Mask_OFFSET                        18
+#define GMMx7A0_PcieLclkIdle1Mask_WIDTH                         1
+#define GMMx7A0_PcieLclkIdle1Mask_MASK                          0x40000
+#define GMMx7A0_PcieLclkIdle2Mask_OFFSET                        19
+#define GMMx7A0_PcieLclkIdle2Mask_WIDTH                         1
+#define GMMx7A0_PcieLclkIdle2Mask_MASK                          0x80000
+#define GMMx7A0_L1imugfxIdleMask_OFFSET                         20
+#define GMMx7A0_L1imugfxIdleMask_WIDTH                          1
+#define GMMx7A0_L1imugfxIdleMask_MASK                           0x100000
+#define GMMx7A0_L1imugppsbIdleMask_OFFSET                       21
+#define GMMx7A0_L1imugppsbIdleMask_WIDTH                        1
+#define GMMx7A0_L1imugppsbIdleMask_MASK                         0x200000
+#define GMMx7A0_L1imubifIdleMask_OFFSET                         22
+#define GMMx7A0_L1imubifIdleMask_WIDTH                          1
+#define GMMx7A0_L1imubifIdleMask_MASK                           0x400000
+#define GMMx7A0_L1imuintgenIdleMask_OFFSET                      23
+#define GMMx7A0_L1imuintgenIdleMask_WIDTH                       1
+#define GMMx7A0_L1imuintgenIdleMask_MASK                        0x800000
+#define GMMx7A0_L2imuIdleMask_OFFSET                            24
+#define GMMx7A0_L2imuIdleMask_WIDTH                             1
+#define GMMx7A0_L2imuIdleMask_MASK                              0x1000000
+#define GMMx7A0_OrbIdleMask_OFFSET                              25
+#define GMMx7A0_OrbIdleMask_WIDTH                               1
+#define GMMx7A0_OrbIdleMask_MASK                                0x2000000
+#define GMMx7A0_OnInbWakeMask_OFFSET                            26
+#define GMMx7A0_OnInbWakeMask_WIDTH                             1
+#define GMMx7A0_OnInbWakeMask_MASK                              0x4000000
+#define GMMx7A0_OnInbWakeAckMask_OFFSET                         27
+#define GMMx7A0_OnInbWakeAckMask_WIDTH                          1
+#define GMMx7A0_OnInbWakeAckMask_MASK                           0x8000000
+#define GMMx7A0_OnOutbWakeMask_OFFSET                           28
+#define GMMx7A0_OnOutbWakeMask_WIDTH                            1
+#define GMMx7A0_OnOutbWakeMask_MASK                             0x10000000
+#define GMMx7A0_OnOutbWakeAckMask_OFFSET                        29
+#define GMMx7A0_OnOutbWakeAckMask_WIDTH                         1
+#define GMMx7A0_OnOutbWakeAckMask_MASK                          0x20000000
+#define GMMx7A0_DmaactiveMask_OFFSET                            30
+#define GMMx7A0_DmaactiveMask_WIDTH                             1
+#define GMMx7A0_DmaactiveMask_MASK                              0x40000000
+#define GMMx7A0_EnableDs_OFFSET                                 31
+#define GMMx7A0_EnableDs_WIDTH                                  1
+#define GMMx7A0_EnableDs_MASK                                   0x80000000
+
+/// GMMx7A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    DivId:3 ; ///<
+    UINT32                                                  RampDis:1 ; ///<
+    UINT32                                               Hysteresis:12; ///<
+    UINT32                                          SclkRunningMask:1 ; ///<
+    UINT32                                              SmuBusyMask:1 ; ///<
+    UINT32                                        PcieLclkIdle1Mask:1 ; ///<
+    UINT32                                        PcieLclkIdle2Mask:1 ; ///<
+    UINT32                                         L1imugfxIdleMask:1 ; ///<
+    UINT32                                       L1imugppsbIdleMask:1 ; ///<
+    UINT32                                         L1imubifIdleMask:1 ; ///<
+    UINT32                                      L1imuintgenIdleMask:1 ; ///<
+    UINT32                                            L2imuIdleMask:1 ; ///<
+    UINT32                                              OrbIdleMask:1 ; ///<
+    UINT32                                            OnInbWakeMask:1 ; ///<
+    UINT32                                         OnInbWakeAckMask:1 ; ///<
+    UINT32                                           OnOutbWakeMask:1 ; ///<
+    UINT32                                        OnOutbWakeAckMask:1 ; ///<
+    UINT32                                            DmaactiveMask:1 ; ///<
+    UINT32                                                 EnableDs:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx7A0_STRUCT;
+
+// **** GMMx7B0 Register Definition ****
+// Address
+#define GMMx7B0_ADDRESS                                         0x7b0
+
+// Type
+#define GMMx7B0_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx7B0_SMU_VOLTAGE_EN_OFFSET                           0
+#define GMMx7B0_SMU_VOLTAGE_EN_WIDTH                            1
+#define GMMx7B0_SMU_VOLTAGE_EN_MASK                             0x1
+#define GMMx7B0_SMU_VOLTAGE_LEVEL_OFFSET                        1
+#define GMMx7B0_SMU_VOLTAGE_LEVEL_WIDTH                         8
+#define GMMx7B0_SMU_VOLTAGE_LEVEL_MASK                          0x1fe
+#define GMMx7B0_Reserved_OFFSET                                 9
+#define GMMx7B0_Reserved_WIDTH                                  23
+#define GMMx7B0_Reserved_MASK                                   0xfffffe00
+
+/// GMMx7B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SMU_VOLTAGE_EN:1 ; ///<
+    UINT32                                        SMU_VOLTAGE_LEVEL:8 ; ///<
+    UINT32                                                 Reserved:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx7B0_STRUCT;
+
+// **** GMMx898 Register Definition ****
+// Address
+#define GMMx898_ADDRESS                                         0x898
+
+// Type
+#define GMMx898_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx898_Threshold_OFFSET                                0
+#define GMMx898_Threshold_WIDTH                                 8
+#define GMMx898_Threshold_MASK                                  0xff
+#define GMMx898_Reserved_31_8_OFFSET                            8
+#define GMMx898_Reserved_31_8_WIDTH                             24
+#define GMMx898_Reserved_31_8_MASK                              0xffffff00
+
+/// GMMx898
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                Threshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx898_STRUCT;
+
+// **** GMMxC64 Register Definition ****
+// Address
+#define GMMxC64_ADDRESS                                         0xc64
+
+// Type
+#define GMMxC64_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET                   0
+#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_WIDTH                    1
+#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK                     0x1
+#define GMMxC64_Reserved_OFFSET                                 1
+#define GMMxC64_Reserved_WIDTH                                  31
+#define GMMxC64_Reserved_MASK                                   0xfffffffe
+
+/// GMMxC64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                   MCIFMEM_CACHE_MODE_DIS:1 ; ///<
+    UINT32                                                 Reserved:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMxC64_STRUCT;
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CHAN0:4 ; ///<
+    UINT32                                                    CHAN1:4 ; ///<
+    UINT32                                                    CHAN2:4 ; ///<
+    UINT32                                                 NOOFCHAN:2 ; ///<
+    UINT32                                                 Reserved:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1012_STRUCT;
+
+
+
+
+
+// **** GMMx2024 Register Definition ****
+// Address
+#define GMMx2024_ADDRESS                                        0x2024
+
+// Type
+#define GMMx2024_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2024_FB_BASE_OFFSET                                 0
+#define GMMx2024_FB_BASE_WIDTH                                  16
+#define GMMx2024_FB_BASE_MASK                                   0xffff
+#define GMMx2024_FB_TOP_OFFSET                                  16
+#define GMMx2024_FB_TOP_WIDTH                                   16
+#define GMMx2024_FB_TOP_MASK                                    0xffff0000
+
+/// GMMx2024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FB_BASE:16; ///<
+    UINT32                                                   FB_TOP:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2024_STRUCT;
+
+// **** GMMx2068 Register Definition ****
+// Address
+#define GMMx2068_ADDRESS                                        0x2068
+
+// Type
+#define GMMx2068_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2068_FB_OFFSET_OFFSET                               0
+#define GMMx2068_FB_OFFSET_WIDTH                                18
+#define GMMx2068_FB_OFFSET_MASK                                 0x3ffff
+#define GMMx2068_Reserved_OFFSET                                18
+#define GMMx2068_Reserved_WIDTH                                 14
+#define GMMx2068_Reserved_MASK                                  0xfffc0000
+
+/// GMMx2068
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                FB_OFFSET:18; ///<
+    UINT32                                                 Reserved:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2068_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         DEFAULT_STEERING:2 ; ///<
+    UINT32                                          CLIENT_STEERING:2 ; ///<
+    UINT32                                                 Reserved:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1017_STRUCT;
+
+
+
+
+
+
+
+// **** GMMx20EC Register Definition ****
+// Address
+
+// **** GMMx2114 Register Definition ****
+// Address
+#define GMMx2114_ADDRESS                                        0x2114
+
+// Type
+#define GMMx2114_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2114_STOR1_PRI_OFFSET                               0
+#define GMMx2114_STOR1_PRI_WIDTH                                8
+#define GMMx2114_STOR1_PRI_MASK                                 0xff
+#define GMMx2114_Reserved_OFFSET                                8
+#define GMMx2114_Reserved_WIDTH                                 24
+#define GMMx2114_Reserved_MASK                                  0xffffff00
+
+/// GMMx2114
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                STOR1_PRI:8 ; ///<
+    UINT32                                                 Reserved:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2114_STRUCT;
+
+
+// **** GMMx2188 Register Definition ****
+// Address
+#define GMMx2188_ADDRESS                                        0x2188
+
+// Type
+#define GMMx2188_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2188_ENABLE_OFFSET                                  0
+#define GMMx2188_ENABLE_WIDTH                                   1
+#define GMMx2188_ENABLE_MASK                                    0x1
+#define GMMx2188_PRESCALE_OFFSET                                1
+#define GMMx2188_PRESCALE_WIDTH                                 2
+#define GMMx2188_PRESCALE_MASK                                  0x6
+#define GMMx2188_BLACKOUT_EXEMPT_OFFSET                         3
+#define GMMx2188_BLACKOUT_EXEMPT_WIDTH                          1
+#define GMMx2188_BLACKOUT_EXEMPT_MASK                           0x8
+#define GMMx2188_STALL_MODE_OFFSET                              4
+#define GMMx2188_STALL_MODE_WIDTH                               2
+#define GMMx2188_STALL_MODE_MASK                                0x30
+#define GMMx2188_STALL_OVERRIDE_OFFSET                          6
+#define GMMx2188_STALL_OVERRIDE_WIDTH                           1
+#define GMMx2188_STALL_OVERRIDE_MASK                            0x40
+#define GMMx2188_MAXBURST_OFFSET                                7
+#define GMMx2188_MAXBURST_WIDTH                                 4
+#define GMMx2188_MAXBURST_MASK                                  0x780
+#define GMMx2188_LAZY_TIMER_OFFSET                              11
+#define GMMx2188_LAZY_TIMER_WIDTH                               4
+#define GMMx2188_LAZY_TIMER_MASK                                0x7800
+#define GMMx2188_STALL_OVERRIDE_WTM_OFFSET                      15
+#define GMMx2188_STALL_OVERRIDE_WTM_WIDTH                       1
+#define GMMx2188_STALL_OVERRIDE_WTM_MASK                        0x8000
+#define GMMx2188_Reserved_OFFSET                                16
+#define GMMx2188_Reserved_WIDTH                                 16
+#define GMMx2188_Reserved_MASK                                  0xffff0000
+
+/// GMMx2188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   ENABLE:1 ; ///<
+    UINT32                                                 PRESCALE:2 ; ///<
+    UINT32                                          BLACKOUT_EXEMPT:1 ; ///<
+    UINT32                                               STALL_MODE:2 ; ///<
+    UINT32                                           STALL_OVERRIDE:1 ; ///<
+    UINT32                                                 MAXBURST:4 ; ///<
+    UINT32                                               LAZY_TIMER:4 ; ///<
+    UINT32                                       STALL_OVERRIDE_WTM:1 ; ///<
+    UINT32                                                 Reserved:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2188_STRUCT;
+
+
+
+
+#define GMMx21F4_STALL_OVERRIDE_OFFSET                          6
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             UVD_OPTIMIZE:1 ; ///<
+    UINT32                                             VCE_OPTIMIZE:1 ; ///<
+    UINT32                                          XB_UVD_OPTIMIZE:1 ; ///<
+    UINT32                                          XB_VCE_OPTIMIZE:1 ; ///<
+    UINT32                                   CITF_UVD_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                   CITF_UMC_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                   CITF_VCE_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                  CITF_VCEU_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                                 Reserved:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1034_STRUCT;
+
+
+// **** GMMx25C0 Register Definition ****
+// Address
+#define GMMx25C0_ADDRESS                                        0x25c0
+
+// Type
+#define GMMx25C0_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx25C0_Reserved_OFFSET                                0
+#define GMMx25C0_Reserved_WIDTH                                 2
+#define GMMx25C0_Reserved_MASK                                  0x3
+#define GMMx25C0_IGNOREPM_OFFSET                                2
+#define GMMx25C0_IGNOREPM_WIDTH                                 1
+#define GMMx25C0_IGNOREPM_MASK                                  0x4
+#define GMMx25C0_EXEMPTPM_OFFSET                                3
+#define GMMx25C0_EXEMPTPM_WIDTH                                 1
+#define GMMx25C0_EXEMPTPM_MASK                                  0x8
+#define GMMx25C0_GFX_IDLE_OVERRIDE_OFFSET                       4
+#define GMMx25C0_GFX_IDLE_OVERRIDE_WIDTH                        2
+#define GMMx25C0_GFX_IDLE_OVERRIDE_MASK                         0x30
+#define GMMx25C0_MCD_SRBM_MASK_ENABLE_OFFSET                    6
+#define GMMx25C0_MCD_SRBM_MASK_ENABLE_WIDTH                     1
+#define GMMx25C0_MCD_SRBM_MASK_ENABLE_MASK                      0x40
+#define GMMx25C0_DUMMY_OFFSET                                   7
+#define GMMx25C0_DUMMY_WIDTH                                    7
+#define GMMx25C0_DUMMY_MASK                                     0x3f80
+#define GMMx25C0_Reserved14_31_OFFSET                           14
+#define GMMx25C0_Reserved14_31_WIDTH                            18
+#define GMMx25C0_Reserved14_31_MASK                             0xffffc000
+
+/// GMMx25C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:2 ; ///<
+    UINT32                                                 IGNOREPM:1 ; ///<
+    UINT32                                                 EXEMPTPM:1 ; ///<
+    UINT32                                        GFX_IDLE_OVERRIDE:2 ; ///<
+    UINT32                                     MCD_SRBM_MASK_ENABLE:1 ; ///<
+    UINT32                                                    DUMMY:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx25C0_STRUCT;
+
+// **** GMMx25C8 Register Definition ****
+// Address
+#define GMMx25C8_ADDRESS                                        0x25c8
+
+// Type
+#define GMMx25C8_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx25C8_READ_LCL_OFFSET                                0
+#define GMMx25C8_READ_LCL_WIDTH                                 8
+#define GMMx25C8_READ_LCL_MASK                                  0xff
+#define GMMx25C8_READ_HUB_OFFSET                                8
+#define GMMx25C8_READ_HUB_WIDTH                                 8
+#define GMMx25C8_READ_HUB_MASK                                  0xff00
+#define GMMx25C8_READ_PRI_OFFSET                                16
+#define GMMx25C8_READ_PRI_WIDTH                                 8
+#define GMMx25C8_READ_PRI_MASK                                  0xff0000
+#define GMMx25C8_LCL_PRI_OFFSET                                 24
+#define GMMx25C8_LCL_PRI_WIDTH                                  1
+#define GMMx25C8_LCL_PRI_MASK                                   0x1000000
+#define GMMx25C8_HUB_PRI_OFFSET                                 25
+#define GMMx25C8_HUB_PRI_WIDTH                                  1
+#define GMMx25C8_HUB_PRI_MASK                                   0x2000000
+#define GMMx25C8_Reserved_OFFSET                                26
+#define GMMx25C8_Reserved_WIDTH                                 6
+#define GMMx25C8_Reserved_MASK                                  0xfc000000
+
+/// GMMx25C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 READ_LCL:8 ; ///<
+    UINT32                                                 READ_HUB:8 ; ///<
+    UINT32                                                 READ_PRI:8 ; ///<
+    UINT32                                                  LCL_PRI:1 ; ///<
+    UINT32                                                  HUB_PRI:1 ; ///<
+    UINT32                                                 Reserved:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx25C8_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1047_0:8;
+    UINT32            ex1047_1:8;
+    UINT32            ex1047_2:8;
+    UINT32            ex1047_3:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1047_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1048_0:8;
+    UINT32            ex1048_1:8;
+    UINT32            ex1048_2:8;
+    UINT32            ex1048_3:5;
+    UINT32                                                 Reserved:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1048_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1060_0:8;
+    UINT32            ex1060_1:8;
+    UINT32            ex1060_2:8;
+    UINT32            ex1060_3:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1060_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1061_0:8;
+    UINT32            ex1061_1:8;
+    UINT32            ex1061_2:8;
+    UINT32            ex1061_3:5;
+    UINT32                                                 Reserved:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1061_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1062_0:5;
+    UINT32            ex1062_1:5;
+    UINT32                                                   STATE2:5 ; ///<
+    UINT32                                                   STATE3:5 ; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1062_STRUCT;
+
+// **** GMMx2814 Register Definition ****
+// Address
+#define GMMx2814_ADDRESS                                        0x2814
+
+// Type
+#define GMMx2814_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2814_CSENABLE_OFFSET                                0
+#define GMMx2814_CSENABLE_WIDTH                                 1
+#define GMMx2814_CSENABLE_MASK                                  0x1
+#define GMMx2814_Reserved_OFFSET                                1
+#define GMMx2814_Reserved_WIDTH                                 4
+#define GMMx2814_Reserved_MASK                                  0x1e
+#define GMMx2814_BASEADDR21_11_OFFSET                           5
+#define GMMx2814_BASEADDR21_11_WIDTH                            11
+#define GMMx2814_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2814_Reserved16_18_OFFSET                           16
+#define GMMx2814_Reserved16_18_WIDTH                            3
+#define GMMx2814_Reserved16_18_MASK                             0x70000
+#define GMMx2814_BASEADDR38_27_OFFSET                           19
+#define GMMx2814_BASEADDR38_27_WIDTH                            12
+#define GMMx2814_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2814_Reserved31_31_OFFSET                           31
+#define GMMx2814_Reserved31_31_WIDTH                            1
+#define GMMx2814_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2814
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2814_STRUCT;
+
+// **** GMMx2818 Register Definition ****
+// Address
+#define GMMx2818_ADDRESS                                        0x2818
+
+// Type
+#define GMMx2818_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2818_CSENABLE_OFFSET                                0
+#define GMMx2818_CSENABLE_WIDTH                                 1
+#define GMMx2818_CSENABLE_MASK                                  0x1
+#define GMMx2818_Reserved_OFFSET                                1
+#define GMMx2818_Reserved_WIDTH                                 4
+#define GMMx2818_Reserved_MASK                                  0x1e
+#define GMMx2818_BASEADDR21_11_OFFSET                           5
+#define GMMx2818_BASEADDR21_11_WIDTH                            11
+#define GMMx2818_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2818_Reserved16_18_OFFSET                           16
+#define GMMx2818_Reserved16_18_WIDTH                            3
+#define GMMx2818_Reserved16_18_MASK                             0x70000
+#define GMMx2818_BASEADDR38_27_OFFSET                           19
+#define GMMx2818_BASEADDR38_27_WIDTH                            12
+#define GMMx2818_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2818_Reserved31_31_OFFSET                           31
+#define GMMx2818_Reserved31_31_WIDTH                            1
+#define GMMx2818_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2818
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2818_STRUCT;
+
+// **** GMMx281C Register Definition ****
+// Address
+#define GMMx281C_ADDRESS                                        0x281c
+
+// Type
+#define GMMx281C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx281C_CSENABLE_OFFSET                                0
+#define GMMx281C_CSENABLE_WIDTH                                 1
+#define GMMx281C_CSENABLE_MASK                                  0x1
+#define GMMx281C_Reserved_OFFSET                                1
+#define GMMx281C_Reserved_WIDTH                                 4
+#define GMMx281C_Reserved_MASK                                  0x1e
+#define GMMx281C_BASEADDR21_11_OFFSET                           5
+#define GMMx281C_BASEADDR21_11_WIDTH                            11
+#define GMMx281C_BASEADDR21_11_MASK                             0xffe0
+#define GMMx281C_Reserved16_18_OFFSET                           16
+#define GMMx281C_Reserved16_18_WIDTH                            3
+#define GMMx281C_Reserved16_18_MASK                             0x70000
+#define GMMx281C_BASEADDR38_27_OFFSET                           19
+#define GMMx281C_BASEADDR38_27_WIDTH                            12
+#define GMMx281C_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx281C_Reserved31_31_OFFSET                           31
+#define GMMx281C_Reserved31_31_WIDTH                            1
+#define GMMx281C_Reserved31_31_MASK                             0x80000000
+
+/// GMMx281C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx281C_STRUCT;
+
+// **** GMMx2820 Register Definition ****
+// Address
+#define GMMx2820_ADDRESS                                        0x2820
+
+// Type
+#define GMMx2820_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2820_CSENABLE_OFFSET                                0
+#define GMMx2820_CSENABLE_WIDTH                                 1
+#define GMMx2820_CSENABLE_MASK                                  0x1
+#define GMMx2820_Reserved_OFFSET                                1
+#define GMMx2820_Reserved_WIDTH                                 4
+#define GMMx2820_Reserved_MASK                                  0x1e
+#define GMMx2820_BASEADDR21_11_OFFSET                           5
+#define GMMx2820_BASEADDR21_11_WIDTH                            11
+#define GMMx2820_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2820_Reserved16_18_OFFSET                           16
+#define GMMx2820_Reserved16_18_WIDTH                            3
+#define GMMx2820_Reserved16_18_MASK                             0x70000
+#define GMMx2820_BASEADDR38_27_OFFSET                           19
+#define GMMx2820_BASEADDR38_27_WIDTH                            12
+#define GMMx2820_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2820_Reserved31_31_OFFSET                           31
+#define GMMx2820_Reserved31_31_WIDTH                            1
+#define GMMx2820_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2820
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2820_STRUCT;
+
+// **** GMMx2824 Register Definition ****
+// Address
+#define GMMx2824_ADDRESS                                        0x2824
+
+// Type
+#define GMMx2824_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2824_CSENABLE_OFFSET                                0
+#define GMMx2824_CSENABLE_WIDTH                                 1
+#define GMMx2824_CSENABLE_MASK                                  0x1
+#define GMMx2824_Reserved_OFFSET                                1
+#define GMMx2824_Reserved_WIDTH                                 4
+#define GMMx2824_Reserved_MASK                                  0x1e
+#define GMMx2824_BASEADDR21_11_OFFSET                           5
+#define GMMx2824_BASEADDR21_11_WIDTH                            11
+#define GMMx2824_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2824_Reserved16_18_OFFSET                           16
+#define GMMx2824_Reserved16_18_WIDTH                            3
+#define GMMx2824_Reserved16_18_MASK                             0x70000
+#define GMMx2824_BASEADDR38_27_OFFSET                           19
+#define GMMx2824_BASEADDR38_27_WIDTH                            12
+#define GMMx2824_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2824_Reserved31_31_OFFSET                           31
+#define GMMx2824_Reserved31_31_WIDTH                            1
+#define GMMx2824_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2824
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2824_STRUCT;
+
+// **** GMMx2828 Register Definition ****
+// Address
+#define GMMx2828_ADDRESS                                        0x2828
+
+// Type
+#define GMMx2828_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2828_CSENABLE_OFFSET                                0
+#define GMMx2828_CSENABLE_WIDTH                                 1
+#define GMMx2828_CSENABLE_MASK                                  0x1
+#define GMMx2828_Reserved_OFFSET                                1
+#define GMMx2828_Reserved_WIDTH                                 4
+#define GMMx2828_Reserved_MASK                                  0x1e
+#define GMMx2828_BASEADDR21_11_OFFSET                           5
+#define GMMx2828_BASEADDR21_11_WIDTH                            11
+#define GMMx2828_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2828_Reserved16_18_OFFSET                           16
+#define GMMx2828_Reserved16_18_WIDTH                            3
+#define GMMx2828_Reserved16_18_MASK                             0x70000
+#define GMMx2828_BASEADDR38_27_OFFSET                           19
+#define GMMx2828_BASEADDR38_27_WIDTH                            12
+#define GMMx2828_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2828_Reserved31_31_OFFSET                           31
+#define GMMx2828_Reserved31_31_WIDTH                            1
+#define GMMx2828_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2828
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2828_STRUCT;
+
+// **** GMMx282C Register Definition ****
+// Address
+#define GMMx282C_ADDRESS                                        0x282c
+
+// Type
+#define GMMx282C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx282C_CSENABLE_OFFSET                                0
+#define GMMx282C_CSENABLE_WIDTH                                 1
+#define GMMx282C_CSENABLE_MASK                                  0x1
+#define GMMx282C_Reserved_OFFSET                                1
+#define GMMx282C_Reserved_WIDTH                                 4
+#define GMMx282C_Reserved_MASK                                  0x1e
+#define GMMx282C_BASEADDR21_11_OFFSET                           5
+#define GMMx282C_BASEADDR21_11_WIDTH                            11
+#define GMMx282C_BASEADDR21_11_MASK                             0xffe0
+#define GMMx282C_Reserved16_18_OFFSET                           16
+#define GMMx282C_Reserved16_18_WIDTH                            3
+#define GMMx282C_Reserved16_18_MASK                             0x70000
+#define GMMx282C_BASEADDR38_27_OFFSET                           19
+#define GMMx282C_BASEADDR38_27_WIDTH                            12
+#define GMMx282C_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx282C_Reserved31_31_OFFSET                           31
+#define GMMx282C_Reserved31_31_WIDTH                            1
+#define GMMx282C_Reserved31_31_MASK                             0x80000000
+
+/// GMMx282C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx282C_STRUCT;
+
+// **** GMMx2830 Register Definition ****
+// Address
+#define GMMx2830_ADDRESS                                        0x2830
+
+// Type
+#define GMMx2830_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2830_CSENABLE_OFFSET                                0
+#define GMMx2830_CSENABLE_WIDTH                                 1
+#define GMMx2830_CSENABLE_MASK                                  0x1
+#define GMMx2830_Reserved_OFFSET                                1
+#define GMMx2830_Reserved_WIDTH                                 4
+#define GMMx2830_Reserved_MASK                                  0x1e
+#define GMMx2830_BASEADDR21_11_OFFSET                           5
+#define GMMx2830_BASEADDR21_11_WIDTH                            11
+#define GMMx2830_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2830_Reserved16_18_OFFSET                           16
+#define GMMx2830_Reserved16_18_WIDTH                            3
+#define GMMx2830_Reserved16_18_MASK                             0x70000
+#define GMMx2830_BASEADDR38_27_OFFSET                           19
+#define GMMx2830_BASEADDR38_27_WIDTH                            12
+#define GMMx2830_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2830_Reserved31_31_OFFSET                           31
+#define GMMx2830_Reserved31_31_WIDTH                            1
+#define GMMx2830_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2830
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2830_STRUCT;
+
+// **** GMMx2834 Register Definition ****
+// Address
+#define GMMx2834_ADDRESS                                        0x2834
+
+// Type
+#define GMMx2834_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2834_Reserved_OFFSET                                0
+#define GMMx2834_Reserved_WIDTH                                 5
+#define GMMx2834_Reserved_MASK                                  0x1f
+#define GMMx2834_ADDRMASK21_11_OFFSET                           5
+#define GMMx2834_ADDRMASK21_11_WIDTH                            11
+#define GMMx2834_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx2834_Reserved16_18_OFFSET                           16
+#define GMMx2834_Reserved16_18_WIDTH                            3
+#define GMMx2834_Reserved16_18_MASK                             0x70000
+#define GMMx2834_ADDRMASK38_27_OFFSET                           19
+#define GMMx2834_ADDRMASK38_27_WIDTH                            12
+#define GMMx2834_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx2834_Reserved31_31_OFFSET                           31
+#define GMMx2834_Reserved31_31_WIDTH                            1
+#define GMMx2834_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2834
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2834_STRUCT;
+
+// **** GMMx2838 Register Definition ****
+// Address
+#define GMMx2838_ADDRESS                                        0x2838
+
+// Type
+#define GMMx2838_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2838_Reserved_OFFSET                                0
+#define GMMx2838_Reserved_WIDTH                                 5
+#define GMMx2838_Reserved_MASK                                  0x1f
+#define GMMx2838_ADDRMASK21_11_OFFSET                           5
+#define GMMx2838_ADDRMASK21_11_WIDTH                            11
+#define GMMx2838_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx2838_Reserved16_18_OFFSET                           16
+#define GMMx2838_Reserved16_18_WIDTH                            3
+#define GMMx2838_Reserved16_18_MASK                             0x70000
+#define GMMx2838_ADDRMASK38_27_OFFSET                           19
+#define GMMx2838_ADDRMASK38_27_WIDTH                            12
+#define GMMx2838_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx2838_Reserved31_31_OFFSET                           31
+#define GMMx2838_Reserved31_31_WIDTH                            1
+#define GMMx2838_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2838
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2838_STRUCT;
+
+// **** GMMx283C Register Definition ****
+// Address
+#define GMMx283C_ADDRESS                                        0x283c
+
+// Type
+#define GMMx283C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx283C_Reserved_OFFSET                                0
+#define GMMx283C_Reserved_WIDTH                                 5
+#define GMMx283C_Reserved_MASK                                  0x1f
+#define GMMx283C_ADDRMASK21_11_OFFSET                           5
+#define GMMx283C_ADDRMASK21_11_WIDTH                            11
+#define GMMx283C_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx283C_Reserved16_18_OFFSET                           16
+#define GMMx283C_Reserved16_18_WIDTH                            3
+#define GMMx283C_Reserved16_18_MASK                             0x70000
+#define GMMx283C_ADDRMASK38_27_OFFSET                           19
+#define GMMx283C_ADDRMASK38_27_WIDTH                            12
+#define GMMx283C_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx283C_Reserved31_31_OFFSET                           31
+#define GMMx283C_Reserved31_31_WIDTH                            1
+#define GMMx283C_Reserved31_31_MASK                             0x80000000
+
+/// GMMx283C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx283C_STRUCT;
+
+// **** GMMx2840 Register Definition ****
+// Address
+#define GMMx2840_ADDRESS                                        0x2840
+
+// Type
+#define GMMx2840_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2840_Reserved_OFFSET                                0
+#define GMMx2840_Reserved_WIDTH                                 5
+#define GMMx2840_Reserved_MASK                                  0x1f
+#define GMMx2840_ADDRMASK21_11_OFFSET                           5
+#define GMMx2840_ADDRMASK21_11_WIDTH                            11
+#define GMMx2840_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx2840_Reserved16_18_OFFSET                           16
+#define GMMx2840_Reserved16_18_WIDTH                            3
+#define GMMx2840_Reserved16_18_MASK                             0x70000
+#define GMMx2840_ADDRMASK38_27_OFFSET                           19
+#define GMMx2840_ADDRMASK38_27_WIDTH                            12
+#define GMMx2840_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx2840_Reserved31_31_OFFSET                           31
+#define GMMx2840_Reserved31_31_WIDTH                            1
+#define GMMx2840_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2840
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2840_STRUCT;
+
+// **** GMMx2844 Register Definition ****
+// Address
+#define GMMx2844_ADDRESS                                        0x2844
+
+// Type
+#define GMMx2844_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2844_DIMM0ADDRMAP_OFFSET                            0
+#define GMMx2844_DIMM0ADDRMAP_WIDTH                             4
+#define GMMx2844_DIMM0ADDRMAP_MASK                              0xf
+#define GMMx2844_DIMM1ADDRMAP_OFFSET                            4
+#define GMMx2844_DIMM1ADDRMAP_WIDTH                             4
+#define GMMx2844_DIMM1ADDRMAP_MASK                              0xf0
+#define GMMx2844_Reserved_OFFSET                                8
+#define GMMx2844_Reserved_WIDTH                                 8
+#define GMMx2844_Reserved_MASK                                  0xff00
+#define GMMx2844_BANKSWIZZLEMODE_OFFSET                         16
+#define GMMx2844_BANKSWIZZLEMODE_WIDTH                          1
+#define GMMx2844_BANKSWIZZLEMODE_MASK                           0x10000
+#define GMMx2844_DDR3MODE_OFFSET                                17
+#define GMMx2844_DDR3MODE_WIDTH                                 1
+#define GMMx2844_DDR3MODE_MASK                                  0x20000
+#define GMMx2844_BURSTLENGTH32_OFFSET                           18
+#define GMMx2844_BURSTLENGTH32_WIDTH                            1
+#define GMMx2844_BURSTLENGTH32_MASK                             0x40000
+#define GMMx2844_BANKSWAP_OFFSET                                19
+#define GMMx2844_BANKSWAP_WIDTH                                 1
+#define GMMx2844_BANKSWAP_MASK                                  0x80000
+#define GMMx2844_Reserved20_31_OFFSET                           20
+#define GMMx2844_Reserved20_31_WIDTH                            12
+#define GMMx2844_Reserved20_31_MASK                             0xfff00000
+
+/// GMMx2844
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DIMM0ADDRMAP:4 ; ///<
+    UINT32                                             DIMM1ADDRMAP:4 ; ///<
+    UINT32                                                 Reserved:8 ; ///<
+    UINT32                                          BANKSWIZZLEMODE:1 ; ///<
+    UINT32                                                 DDR3MODE:1 ; ///<
+    UINT32                                            BURSTLENGTH32:1 ; ///<
+    UINT32                                                 BANKSWAP:1 ; ///<
+    UINT32                                            Reserved20_31:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2844_STRUCT;
+
+// **** GMMx2848 Register Definition ****
+// Address
+#define GMMx2848_ADDRESS                                        0x2848
+
+// Type
+#define GMMx2848_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2848_DIMM0ADDRMAP_OFFSET                            0
+#define GMMx2848_DIMM0ADDRMAP_WIDTH                             4
+#define GMMx2848_DIMM0ADDRMAP_MASK                              0xf
+#define GMMx2848_DIMM1ADDRMAP_OFFSET                            4
+#define GMMx2848_DIMM1ADDRMAP_WIDTH                             4
+#define GMMx2848_DIMM1ADDRMAP_MASK                              0xf0
+#define GMMx2848_Reserved_OFFSET                                8
+#define GMMx2848_Reserved_WIDTH                                 8
+#define GMMx2848_Reserved_MASK                                  0xff00
+#define GMMx2848_BANKSWIZZLEMODE_OFFSET                         16
+#define GMMx2848_BANKSWIZZLEMODE_WIDTH                          1
+#define GMMx2848_BANKSWIZZLEMODE_MASK                           0x10000
+#define GMMx2848_DDR3MODE_OFFSET                                17
+#define GMMx2848_DDR3MODE_WIDTH                                 1
+#define GMMx2848_DDR3MODE_MASK                                  0x20000
+#define GMMx2848_BURSTLENGTH32_OFFSET                           18
+#define GMMx2848_BURSTLENGTH32_WIDTH                            1
+#define GMMx2848_BURSTLENGTH32_MASK                             0x40000
+#define GMMx2848_BANKSWAP_OFFSET                                19
+#define GMMx2848_BANKSWAP_WIDTH                                 1
+#define GMMx2848_BANKSWAP_MASK                                  0x80000
+#define GMMx2848_Reserved20_31_OFFSET                           20
+#define GMMx2848_Reserved20_31_WIDTH                            12
+#define GMMx2848_Reserved20_31_MASK                             0xfff00000
+
+/// GMMx2848
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DIMM0ADDRMAP:4 ; ///<
+    UINT32                                             DIMM1ADDRMAP:4 ; ///<
+    UINT32                                                 Reserved:8 ; ///<
+    UINT32                                          BANKSWIZZLEMODE:1 ; ///<
+    UINT32                                                 DDR3MODE:1 ; ///<
+    UINT32                                            BURSTLENGTH32:1 ; ///<
+    UINT32                                                 BANKSWAP:1 ; ///<
+    UINT32                                            Reserved20_31:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2848_STRUCT;
+
+// **** GMMx284C Register Definition ****
+// Address
+#define GMMx284C_ADDRESS                                        0x284c
+
+// Type
+#define GMMx284C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx284C_DCTSELHIRNGEN_OFFSET                           0
+#define GMMx284C_DCTSELHIRNGEN_WIDTH                            1
+#define GMMx284C_DCTSELHIRNGEN_MASK                             0x1
+#define GMMx284C_DCTSELHI_OFFSET                                1
+#define GMMx284C_DCTSELHI_WIDTH                                 1
+#define GMMx284C_DCTSELHI_MASK                                  0x2
+#define GMMx284C_DCTSELINTLVEN_OFFSET                           2
+#define GMMx284C_DCTSELINTLVEN_WIDTH                            1
+#define GMMx284C_DCTSELINTLVEN_MASK                             0x4
+#define GMMx284C_Reserved_OFFSET                                3
+#define GMMx284C_Reserved_WIDTH                                 3
+#define GMMx284C_Reserved_MASK                                  0x38
+#define GMMx284C_DCTSELINTLVADDR_1_0_OFFSET                     6
+#define GMMx284C_DCTSELINTLVADDR_1_0_WIDTH                      2
+#define GMMx284C_DCTSELINTLVADDR_1_0_MASK                       0xc0
+#define GMMx284C_Reserved8_10_OFFSET                            8
+#define GMMx284C_Reserved8_10_WIDTH                             3
+#define GMMx284C_Reserved8_10_MASK                              0x700
+#define GMMx284C_DCTSELBASEADDR39_27_OFFSET                     11
+#define GMMx284C_DCTSELBASEADDR39_27_WIDTH                      13
+#define GMMx284C_DCTSELBASEADDR39_27_MASK                       0xfff800
+#define GMMx284C_Reserved24_31_OFFSET                           24
+#define GMMx284C_Reserved24_31_WIDTH                            8
+#define GMMx284C_Reserved24_31_MASK                             0xff000000
+
+/// GMMx284C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DCTSELHIRNGEN:1 ; ///<
+    UINT32                                                 DCTSELHI:1 ; ///<
+    UINT32                                            DCTSELINTLVEN:1 ; ///<
+    UINT32                                                 Reserved:3 ; ///<
+    UINT32                                      DCTSELINTLVADDR_1_0:2 ; ///<
+    UINT32                                             Reserved8_10:3 ; ///<
+    UINT32                                      DCTSELBASEADDR39_27:13; ///<
+    UINT32                                            Reserved24_31:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx284C_STRUCT;
+
+// **** GMMx2850 Register Definition ****
+// Address
+#define GMMx2850_ADDRESS                                        0x2850
+
+// Type
+#define GMMx2850_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2850_Reserved_OFFSET                                0
+#define GMMx2850_Reserved_WIDTH                                 9
+#define GMMx2850_Reserved_MASK                                  0x1ff
+#define GMMx2850_DCTSELINTLVADDR_2_OFFSET                       9
+#define GMMx2850_DCTSELINTLVADDR_2_WIDTH                        1
+#define GMMx2850_DCTSELINTLVADDR_2_MASK                         0x200
+#define GMMx2850_DCTSELBASEOFFSET_39_26_OFFSET                  10
+#define GMMx2850_DCTSELBASEOFFSET_39_26_WIDTH                   14
+#define GMMx2850_DCTSELBASEOFFSET_39_26_MASK                    0xfffc00
+#define GMMx2850_Reserved24_31_OFFSET                           24
+#define GMMx2850_Reserved24_31_WIDTH                            8
+#define GMMx2850_Reserved24_31_MASK                             0xff000000
+
+/// GMMx2850
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:9 ; ///<
+    UINT32                                        DCTSELINTLVADDR_2:1 ; ///<
+    UINT32                                   DCTSELBASEOFFSET_39_26:14; ///<
+    UINT32                                            Reserved24_31:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2850_STRUCT;
+
+// **** GMMx2854 Register Definition ****
+// Address
+#define GMMx2854_ADDRESS                                        0x2854
+
+// Type
+#define GMMx2854_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2854_DRAMHOLEVALID_OFFSET                           0
+#define GMMx2854_DRAMHOLEVALID_WIDTH                            1
+#define GMMx2854_DRAMHOLEVALID_MASK                             0x1
+#define GMMx2854_Reserved_OFFSET                                1
+#define GMMx2854_Reserved_WIDTH                                 1
+#define GMMx2854_Reserved_MASK                                  0x2
+#define GMMx2854_DRAMHTHOLEVALID_OFFSET                         2
+#define GMMx2854_DRAMHTHOLEVALID_WIDTH                          1
+#define GMMx2854_DRAMHTHOLEVALID_MASK                           0x4
+#define GMMx2854_Reserved3_6_OFFSET                             3
+#define GMMx2854_Reserved3_6_WIDTH                              4
+#define GMMx2854_Reserved3_6_MASK                               0x78
+#define GMMx2854_DRAMHOLEOFFSET31_23_OFFSET                     7
+#define GMMx2854_DRAMHOLEOFFSET31_23_WIDTH                      9
+#define GMMx2854_DRAMHOLEOFFSET31_23_MASK                       0xff80
+#define GMMx2854_Reserved16_23_OFFSET                           16
+#define GMMx2854_Reserved16_23_WIDTH                            8
+#define GMMx2854_Reserved16_23_MASK                             0xff0000
+#define GMMx2854_DRAMHOLEBASE31_24_OFFSET                       24
+#define GMMx2854_DRAMHOLEBASE31_24_WIDTH                        8
+#define GMMx2854_DRAMHOLEBASE31_24_MASK                         0xff000000
+
+/// GMMx2854
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DRAMHOLEVALID:1 ; ///<
+    UINT32                                                 Reserved:1 ; ///<
+    UINT32                                          DRAMHTHOLEVALID:1 ; ///<
+    UINT32                                              Reserved3_6:4 ; ///<
+    UINT32                                      DRAMHOLEOFFSET31_23:9 ; ///<
+    UINT32                                            Reserved16_23:8 ; ///<
+    UINT32                                        DRAMHOLEBASE31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2854_STRUCT;
+
+// **** GMMx285C Register Definition ****
+// Address
+#define GMMx285C_ADDRESS                                        0x285c
+
+// Type
+#define GMMx285C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx285C_INTLVRGNSWAPEN_OFFSET                          0
+#define GMMx285C_INTLVRGNSWAPEN_WIDTH                           1
+#define GMMx285C_INTLVRGNSWAPEN_MASK                            0x1
+#define GMMx285C_Reserved_OFFSET                                1
+#define GMMx285C_Reserved_WIDTH                                 2
+#define GMMx285C_Reserved_MASK                                  0x6
+#define GMMx285C_INTLVRGNBASEADDR33_27_OFFSET                   3
+#define GMMx285C_INTLVRGNBASEADDR33_27_WIDTH                    7
+#define GMMx285C_INTLVRGNBASEADDR33_27_MASK                     0x3f8
+#define GMMx285C_Reserved10_10_OFFSET                           10
+#define GMMx285C_Reserved10_10_WIDTH                            1
+#define GMMx285C_Reserved10_10_MASK                             0x400
+#define GMMx285C_INTLVRGNLMTADDR33_27_OFFSET                    11
+#define GMMx285C_INTLVRGNLMTADDR33_27_WIDTH                     7
+#define GMMx285C_INTLVRGNLMTADDR33_27_MASK                      0x3f800
+#define GMMx285C_Reserved18_19_OFFSET                           18
+#define GMMx285C_Reserved18_19_WIDTH                            2
+#define GMMx285C_Reserved18_19_MASK                             0xc0000
+#define GMMx285C_INTLVRGNSIZE33_27_OFFSET                       20
+#define GMMx285C_INTLVRGNSIZE33_27_WIDTH                        7
+#define GMMx285C_INTLVRGNSIZE33_27_MASK                         0x7f00000
+#define GMMx285C_Reserved27_31_OFFSET                           27
+#define GMMx285C_Reserved27_31_WIDTH                            5
+#define GMMx285C_Reserved27_31_MASK                             0xf8000000
+
+/// GMMx285C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           INTLVRGNSWAPEN:1 ; ///<
+    UINT32                                                 Reserved:2 ; ///<
+    UINT32                                    INTLVRGNBASEADDR33_27:7 ; ///<
+    UINT32                                            Reserved10_10:1 ; ///<
+    UINT32                                     INTLVRGNLMTADDR33_27:7 ; ///<
+    UINT32                                            Reserved18_19:2 ; ///<
+    UINT32                                        INTLVRGNSIZE33_27:7 ; ///<
+    UINT32                                            Reserved27_31:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx285C_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     BASE:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1064_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      TOP:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1065_STRUCT;
+
+// **** GMMx2870 Register Definition ****
+// Address
+#define GMMx2870_ADDRESS                                        0x2870
+
+// Type
+#define GMMx2870_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2870_BASE_OFFSET                                    0
+#define GMMx2870_BASE_WIDTH                                     20
+#define GMMx2870_BASE_MASK                                      0xfffff
+#define GMMx2870_Reserved_OFFSET                                20
+#define GMMx2870_Reserved_WIDTH                                 12
+#define GMMx2870_Reserved_MASK                                  0xfff00000
+
+/// GMMx2870
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     BASE:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2870_STRUCT;
+
+// **** GMMx2874 Register Definition ****
+// Address
+#define GMMx2874_ADDRESS                                        0x2874
+
+// Type
+#define GMMx2874_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2874_TOP_OFFSET                                     0
+#define GMMx2874_TOP_WIDTH                                      20
+#define GMMx2874_TOP_MASK                                       0xfffff
+#define GMMx2874_Reserved_OFFSET                                20
+#define GMMx2874_Reserved_WIDTH                                 12
+#define GMMx2874_Reserved_MASK                                  0xfff00000
+
+/// GMMx2874
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      TOP:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2874_STRUCT;
+
+
+// **** GMMx287C Register Definition ****
+// Address
+#define GMMx287C_ADDRESS                                        0x287c
+
+// Type
+#define GMMx287C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx287C_DEF_OFFSET                                     0
+#define GMMx287C_DEF_WIDTH                                      28
+#define GMMx287C_DEF_MASK                                       0xfffffff
+#define GMMx287C_Reserved_OFFSET                                28
+#define GMMx287C_Reserved_WIDTH                                 4
+#define GMMx287C_Reserved_MASK                                  0xf0000000
+
+/// GMMx287C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      DEF:28; ///<
+    UINT32                                                 Reserved:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx287C_STRUCT;
+
+// **** GMMx2888 Register Definition ****
+// Address
+#define GMMx2888_ADDRESS                                        0x2888
+
+// Type
+#define GMMx2888_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2888_NO_XBAR_OFFSET                                 0
+#define GMMx2888_NO_XBAR_WIDTH                                  1
+#define GMMx2888_NO_XBAR_MASK                                   0x1
+#define GMMx2888_XBAR_UVD_HP_RD_OFFSET                          1
+#define GMMx2888_XBAR_UVD_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_UVD_HP_RD_MASK                            0x2
+#define GMMx2888_XBAR_UMC_HP_RD_OFFSET                          2
+#define GMMx2888_XBAR_UMC_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_UMC_HP_RD_MASK                            0x4
+#define GMMx2888_XBAR_VCE_HP_RD_OFFSET                          3
+#define GMMx2888_XBAR_VCE_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_VCE_HP_RD_MASK                            0x8
+#define GMMx2888_XBAR_VCEU_HP_RD_OFFSET                         4
+#define GMMx2888_XBAR_VCEU_HP_RD_WIDTH                          1
+#define GMMx2888_XBAR_VCEU_HP_RD_MASK                           0x10
+#define GMMx2888_XBAR_VMC_HP_RD_OFFSET                          5
+#define GMMx2888_XBAR_VMC_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_VMC_HP_RD_MASK                            0x20
+#define GMMx2888_XBAR_DMIF_HP_RD_OFFSET                         6
+#define GMMx2888_XBAR_DMIF_HP_RD_WIDTH                          1
+#define GMMx2888_XBAR_DMIF_HP_RD_MASK                           0x40
+#define GMMx2888_XBAR_UVD_HP_WR_OFFSET                          7
+#define GMMx2888_XBAR_UVD_HP_WR_WIDTH                           1
+#define GMMx2888_XBAR_UVD_HP_WR_MASK                            0x80
+#define GMMx2888_XBAR_UMC_HP_WR_OFFSET                          8
+#define GMMx2888_XBAR_UMC_HP_WR_WIDTH                           1
+#define GMMx2888_XBAR_UMC_HP_WR_MASK                            0x100
+#define GMMx2888_XBAR_VCE_HP_WR_OFFSET                          9
+#define GMMx2888_XBAR_VCE_HP_WR_WIDTH                           1
+#define GMMx2888_XBAR_VCE_HP_WR_MASK                            0x200
+#define GMMx2888_XBAR_VCEU_HP_WR_OFFSET                         10
+#define GMMx2888_XBAR_VCEU_HP_WR_WIDTH                          1
+#define GMMx2888_XBAR_VCEU_HP_WR_MASK                           0x400
+#define GMMx2888_Reserved_OFFSET                                11
+#define GMMx2888_Reserved_WIDTH                                 21
+#define GMMx2888_Reserved_MASK                                  0xfffff800
+
+/// GMMx2888
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  NO_XBAR:1 ; ///<
+    UINT32                                           XBAR_UVD_HP_RD:1 ; ///<
+    UINT32                                           XBAR_UMC_HP_RD:1 ; ///<
+    UINT32                                           XBAR_VCE_HP_RD:1 ; ///<
+    UINT32                                          XBAR_VCEU_HP_RD:1 ; ///<
+    UINT32                                           XBAR_VMC_HP_RD:1 ; ///<
+    UINT32                                          XBAR_DMIF_HP_RD:1 ; ///<
+    UINT32                                           XBAR_UVD_HP_WR:1 ; ///<
+    UINT32                                           XBAR_UMC_HP_WR:1 ; ///<
+    UINT32                                           XBAR_VCE_HP_WR:1 ; ///<
+    UINT32                                          XBAR_VCEU_HP_WR:1 ; ///<
+    UINT32                                                 Reserved:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2888_STRUCT;
+
+
+// **** GMMx28D4 Register Definition ****
+// Address
+#define GMMx28D4_ADDRESS                                        0x28d4
+
+// Type
+#define GMMx28D4_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_OFFSET                  0
+#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_WIDTH                   1
+#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_MASK                    0x1
+#define GMMx28D4_RENG_EXECUTE_NOW_OFFSET                        1
+#define GMMx28D4_RENG_EXECUTE_NOW_WIDTH                         1
+#define GMMx28D4_RENG_EXECUTE_NOW_MASK                          0x2
+#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_OFFSET              2
+#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_WIDTH               10
+#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_MASK                0xffc
+#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_OFFSET                12
+#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_WIDTH                 10
+#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_MASK                  0x3ff000
+#define GMMx28D4_RENG_EXECUTE_END_PTR_OFFSET                    22
+#define GMMx28D4_RENG_EXECUTE_END_PTR_WIDTH                     10
+#define GMMx28D4_RENG_EXECUTE_END_PTR_MASK                      0xffc00000
+
+/// GMMx28D4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                   RENG_EXECUTE_ON_PWR_UP:1 ; ///<
+    UINT32                                         RENG_EXECUTE_NOW:1 ; ///<
+    UINT32                               RENG_EXECUTE_NOW_START_PTR:10; ///<
+    UINT32                                 RENG_EXECUTE_DSP_END_PTR:10; ///<
+    UINT32                                     RENG_EXECUTE_END_PTR:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx28D4_STRUCT;
+
+// **** GMMx28D8 Register Definition ****
+// Address
+#define GMMx28D8_ADDRESS                                        0x28d8
+
+// Type
+#define GMMx28D8_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_OFFSET        0
+#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_WIDTH         10
+#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_MASK          0x3ff
+#define GMMx28D8_RENG_EXECUTE_NOW_MODE_OFFSET                   10
+#define GMMx28D8_RENG_EXECUTE_NOW_MODE_WIDTH                    1
+#define GMMx28D8_RENG_EXECUTE_NOW_MODE_MASK                     0x400
+#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_OFFSET              11
+#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_WIDTH               1
+#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_MASK                0x800
+#define GMMx28D8_RENG_SRBM_CREDITS_MCD_OFFSET                   12
+#define GMMx28D8_RENG_SRBM_CREDITS_MCD_WIDTH                    4
+#define GMMx28D8_RENG_SRBM_CREDITS_MCD_MASK                     0xf000
+#define GMMx28D8_STCTRL_STUTTER_EN_OFFSET                       16
+#define GMMx28D8_STCTRL_STUTTER_EN_WIDTH                        1
+#define GMMx28D8_STCTRL_STUTTER_EN_MASK                         0x10000
+#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_OFFSET               17
+#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_WIDTH                2
+#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_MASK                 0x60000
+#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_OFFSET              19
+#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_WIDTH               2
+#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_MASK                0x180000
+#define GMMx28D8_STCTRL_IGNORE_PRE_SR_OFFSET                    21
+#define GMMx28D8_STCTRL_IGNORE_PRE_SR_WIDTH                     1
+#define GMMx28D8_STCTRL_IGNORE_PRE_SR_MASK                      0x200000
+#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_OFFSET                22
+#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_WIDTH                 1
+#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_MASK                  0x400000
+#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_OFFSET                 23
+#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_WIDTH                  1
+#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_MASK                   0x800000
+#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_OFFSET          24
+#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_WIDTH           1
+#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_MASK            0x1000000
+#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_OFFSET                 25
+#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_WIDTH                  1
+#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_MASK                   0x2000000
+#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_OFFSET              26
+#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_WIDTH               1
+#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_MASK                0x4000000
+#define GMMx28D8_CRITICAL_REGS_LOCK_OFFSET                      27
+#define GMMx28D8_CRITICAL_REGS_LOCK_WIDTH                       1
+#define GMMx28D8_CRITICAL_REGS_LOCK_MASK                        0x8000000
+#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_OFFSET                   28
+#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_WIDTH                    2
+#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_MASK                     0x30000000
+#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_OFFSET                   30
+#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_WIDTH                    1
+#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_MASK                     0x40000000
+#define GMMx28D8_Reserved_OFFSET                                31
+#define GMMx28D8_Reserved_WIDTH                                 1
+#define GMMx28D8_Reserved_MASK                                  0x80000000
+
+/// GMMx28D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                         RENG_EXECUTE_NONSECURE_START_PTR:10; ///<
+    UINT32                                    RENG_EXECUTE_NOW_MODE:1 ; ///<
+    UINT32                               RENG_EXECUTE_ON_REG_UPDATE:1 ; ///<
+    UINT32                                    RENG_SRBM_CREDITS_MCD:4 ; ///<
+    UINT32                                        STCTRL_STUTTER_EN:1 ; ///<
+    UINT32                                STCTRL_GMC_IDLE_THRESHOLD:2 ; ///<
+    UINT32                               STCTRL_SRBM_IDLE_THRESHOLD:2 ; ///<
+    UINT32                                     STCTRL_IGNORE_PRE_SR:1 ; ///<
+    UINT32                                 STCTRL_IGNORE_ALLOW_STOP:1 ; ///<
+    UINT32                                  STCTRL_IGNORE_SR_COMMIT:1 ; ///<
+    UINT32                           STCTRL_IGNORE_PROTECTION_FAULT:1 ; ///<
+    UINT32                                  STCTRL_DISABLE_ALLOW_SR:1 ; ///<
+    UINT32                               STCTRL_DISABLE_GMC_OFFLINE:1 ; ///<
+    UINT32                                       CRITICAL_REGS_LOCK:1 ; ///<
+    UINT32                                    ALLOW_DEEP_SLEEP_MODE:2 ; ///<
+    UINT32                                    STCTRL_FORCE_ALLOW_SR:1 ; ///<
+    UINT32                                                 Reserved:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx28D8_STRUCT;
+
+// **** GMMx2C04 Register Definition ****
+// Address
+#define GMMx2C04_ADDRESS                                        0x2c04
+
+// Type
+#define GMMx2C04_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2C04_NONSURF_BASE_OFFSET                            0
+#define GMMx2C04_NONSURF_BASE_WIDTH                             32
+#define GMMx2C04_NONSURF_BASE_MASK                              0xffffffff
+
+/// GMMx2C04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NONSURF_BASE:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2C04_STRUCT;
+
+// **** GMMx5428 Register Definition ****
+// Address
+#define GMMx5428_ADDRESS                                        0x5428
+
+// Type
+#define GMMx5428_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5428_CONFIG_MEMSIZE_OFFSET                          0
+#define GMMx5428_CONFIG_MEMSIZE_WIDTH                           32
+#define GMMx5428_CONFIG_MEMSIZE_MASK                            0xffffffff
+
+/// GMMx5428
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CONFIG_MEMSIZE:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5428_STRUCT;
+
+// **** GMMx5490 Register Definition ****
+// Address
+#define GMMx5490_ADDRESS                                        0x5490
+
+// Type
+#define GMMx5490_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5490_FB_READ_EN_OFFSET                              0
+#define GMMx5490_FB_READ_EN_WIDTH                               1
+#define GMMx5490_FB_READ_EN_MASK                                0x1
+#define GMMx5490_FB_WRITE_EN_OFFSET                             1
+#define GMMx5490_FB_WRITE_EN_WIDTH                              1
+#define GMMx5490_FB_WRITE_EN_MASK                               0x2
+#define GMMx5490_Reserved_OFFSET                                2
+#define GMMx5490_Reserved_WIDTH                                 30
+#define GMMx5490_Reserved_MASK                                  0xfffffffc
+
+/// GMMx5490
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               FB_READ_EN:1 ; ///<
+    UINT32                                              FB_WRITE_EN:1 ; ///<
+    UINT32                                                 Reserved:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5490_STRUCT;
+
+// **** MSRC001_0010 Register Definition ****
+// Address
+#define MSRC001_0010_ADDRESS                                    0xc0010010
+
+// Type
+#define MSRC001_0010_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_0010_Reserved_15_0_OFFSET                       0
+#define MSRC001_0010_Reserved_15_0_WIDTH                        16
+#define MSRC001_0010_Reserved_15_0_MASK                         0xffff
+#define MSRC001_0010_ChgToDirtyDis_OFFSET                       16
+#define MSRC001_0010_ChgToDirtyDis_WIDTH                        1
+#define MSRC001_0010_ChgToDirtyDis_MASK                         0x10000
+#define MSRC001_0010_Reserved_17_17_OFFSET                      17
+#define MSRC001_0010_Reserved_17_17_WIDTH                       1
+#define MSRC001_0010_Reserved_17_17_MASK                        0x20000
+#define MSRC001_0010_MtrrFixDramEn_OFFSET                       18
+#define MSRC001_0010_MtrrFixDramEn_WIDTH                        1
+#define MSRC001_0010_MtrrFixDramEn_MASK                         0x40000
+#define MSRC001_0010_MtrrFixDramModEn_OFFSET                    19
+#define MSRC001_0010_MtrrFixDramModEn_WIDTH                     1
+#define MSRC001_0010_MtrrFixDramModEn_MASK                      0x80000
+#define MSRC001_0010_MtrrVarDramEn_OFFSET                       20
+#define MSRC001_0010_MtrrVarDramEn_WIDTH                        1
+#define MSRC001_0010_MtrrVarDramEn_MASK                         0x100000
+#define MSRC001_0010_MtrrTom2En_OFFSET                          21
+#define MSRC001_0010_MtrrTom2En_WIDTH                           1
+#define MSRC001_0010_MtrrTom2En_MASK                            0x200000
+#define MSRC001_0010_Tom2ForceMemTypeWB_OFFSET                  22
+#define MSRC001_0010_Tom2ForceMemTypeWB_WIDTH                   1
+#define MSRC001_0010_Tom2ForceMemTypeWB_MASK                    0x400000
+#define MSRC001_0010_Reserved_63_23_OFFSET                      23
+#define MSRC001_0010_Reserved_63_23_WIDTH                       41
+#define MSRC001_0010_Reserved_63_23_MASK                        0xffffffffff800000
+
+/// MSRC001_0010
+typedef union {
+  struct {                                                              ///<
+    UINT64                                            Reserved_15_0:16; ///<
+    UINT64                                            ChgToDirtyDis:1 ; ///<
+    UINT64                                           Reserved_17_17:1 ; ///<
+    UINT64                                            MtrrFixDramEn:1 ; ///<
+    UINT64                                         MtrrFixDramModEn:1 ; ///<
+    UINT64                                            MtrrVarDramEn:1 ; ///<
+    UINT64                                               MtrrTom2En:1 ; ///<
+    UINT64                                       Tom2ForceMemTypeWB:1 ; ///<
+    UINT64                                           Reserved_63_23:41; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_0010_STRUCT;
+
+// **** MSRC001_001A Register Definition ****
+// Address
+#define MSRC001_001A_ADDRESS                                    0xc001001a
+
+// Type
+#define MSRC001_001A_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_001A_RAZ_22_0_OFFSET                            0
+#define MSRC001_001A_RAZ_22_0_WIDTH                             23
+#define MSRC001_001A_RAZ_22_0_MASK                              0x7fffff
+#define MSRC001_001A_TOM_47_23__OFFSET                          23
+#define MSRC001_001A_TOM_47_23__WIDTH                           25
+#define MSRC001_001A_TOM_47_23__MASK                            0xffffff800000
+#define MSRC001_001A_RAZ_63_48_OFFSET                           48
+#define MSRC001_001A_RAZ_63_48_WIDTH                            16
+#define MSRC001_001A_RAZ_63_48_MASK                             0xffff000000000000
+
+/// MSRC001_001A
+typedef union {
+  struct {                                                              ///<
+    UINT64                                                 RAZ_22_0:23; ///<
+    UINT64                                               TOM_47_23_:25; ///<
+    UINT64                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_001A_STRUCT;
+
+// **** MSRC001_001D Register Definition ****
+// Address
+#define MSRC001_001D_ADDRESS                                    0xc001001d
+
+// Type
+#define MSRC001_001D_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_001D_RAZ_22_0_OFFSET                            0
+#define MSRC001_001D_RAZ_22_0_WIDTH                             23
+#define MSRC001_001D_RAZ_22_0_MASK                              0x7fffff
+#define MSRC001_001D_TOM2_47_23__OFFSET                         23
+#define MSRC001_001D_TOM2_47_23__WIDTH                          25
+#define MSRC001_001D_TOM2_47_23__MASK                           0xffffff800000
+#define MSRC001_001D_RAZ_63_48_OFFSET                           48
+#define MSRC001_001D_RAZ_63_48_WIDTH                            16
+#define MSRC001_001D_RAZ_63_48_MASK                             0xffff000000000000
+
+/// MSRC001_001D
+typedef union {
+  struct {                                                              ///<
+    UINT64                                                 RAZ_22_0:23; ///<
+    UINT64                                              TOM2_47_23_:25; ///<
+    UINT64                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_001D_STRUCT;
+
+// **** D0F0xBC_xE01040A8 Field Definition ****
+// Address
+#define D0F0xBC_xE01040A8_ADDRESS                               0xe01040a8
+
+// Type
+#define D0F0xBC_xE01040A8_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE01040A8_Reserved0_14_OFFSET                   0
+#define D0F0xBC_xE01040A8_Reserved0_14_WIDTH                    15
+#define D0F0xBC_xE01040A8_Reserved0_14_MASK                     0x7fff
+#define D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET                 15
+#define D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH                  7
+#define D0F0xBC_xE01040A8_SviLoadLineVdd_MASK                   0x3f8000
+#define D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET               22
+#define D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH                7
+#define D0F0xBC_xE01040A8_SviLoadLineVddNb_MASK                 0x1fc00000
+#define D0F0xBC_xE01040A8_Reserved29_31_OFFSET                  29
+#define D0F0xBC_xE01040A8_Reserved29_31_WIDTH                   3
+#define D0F0xBC_xE01040A8_Reserved29_31_MASK                    0xe0000000
+
+/// D0F0xBC_xE01040A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved0_14:15; ///<
+    UINT32                                           SviLoadLineVdd:7 ; ///<
+    UINT32                                         SviLoadLineVddNb:7 ; ///<
+    UINT32                                            Reserved29_31:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE01040A8_STRUCT;
+
+// **** D0F0xBC_xE0104158 Field Definition ****
+// Address
+#define D0F0xBC_xE0104158_ADDRESS                               0xe0104158
+
+// Type
+#define D0F0xBC_xE0104158_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104158_Reserved0_9_OFFSET                    0
+#define D0F0xBC_xE0104158_Reserved0_9_WIDTH                     10
+#define D0F0xBC_xE0104158_Reserved0_9_MASK                      0x3ff
+#define D0F0xBC_xE0104158_EClkDid0_OFFSET                       10
+#define D0F0xBC_xE0104158_EClkDid0_WIDTH                        7
+#define D0F0xBC_xE0104158_EClkDid0_MASK                         0x1fc00
+#define D0F0xBC_xE0104158_EClkDid1_OFFSET                       17
+#define D0F0xBC_xE0104158_EClkDid1_WIDTH                        7
+#define D0F0xBC_xE0104158_EClkDid1_MASK                         0xfe0000
+#define D0F0xBC_xE0104158_EClkDid2_OFFSET                       24
+#define D0F0xBC_xE0104158_EClkDid2_WIDTH                        7
+#define D0F0xBC_xE0104158_EClkDid2_MASK                         0x7f000000
+#define D0F0xBC_xE0104158_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0104158_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0104158_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0104158
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_9:10; ///<
+    UINT32                                                 EClkDid0:7 ; ///<
+    UINT32                                                 EClkDid1:7 ; ///<
+    UINT32                                                 EClkDid2:7 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104158_STRUCT;
+
+// **** D0F0xBC_xE010415B Field Definition ****
+// Address
+#define D0F0xBC_xE010415B_ADDRESS                               0xe010415b
+
+// Type
+#define D0F0xBC_xE010415B_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010415B_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010415B_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010415B_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010415B_EClkDid3_OFFSET                       7
+#define D0F0xBC_xE010415B_EClkDid3_WIDTH                        7
+#define D0F0xBC_xE010415B_EClkDid3_MASK                         0x3f80
+#define D0F0xBC_xE010415B_Reserved14_31_OFFSET                  14
+#define D0F0xBC_xE010415B_Reserved14_31_WIDTH                   18
+#define D0F0xBC_xE010415B_Reserved14_31_MASK                    0xffffc000
+
+/// D0F0xBC_xE010415B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                                 EClkDid3:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010415B_STRUCT;
+
+// **** D0F0xBC_xE0104184 Field Definition ****
+// Address
+#define D0F0xBC_xE0104184_ADDRESS                               0xe0104184
+
+// Type
+#define D0F0xBC_xE0104184_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET             0
+#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH              3
+#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_MASK               0x7
+#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET           3
+#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH            3
+#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_MASK             0x38
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET           6
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH            2
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_MASK             0xc0
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET         8
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH          2
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_MASK           0x300
+#define D0F0xBC_xE0104184_VCEFlag0_OFFSET                       10
+#define D0F0xBC_xE0104184_VCEFlag0_WIDTH                        8
+#define D0F0xBC_xE0104184_VCEFlag0_MASK                         0x3fc00
+#define D0F0xBC_xE0104184_VCEFlag1_OFFSET                       18
+#define D0F0xBC_xE0104184_VCEFlag1_WIDTH                        8
+#define D0F0xBC_xE0104184_VCEFlag1_MASK                         0x3fc0000
+#define D0F0xBC_xE0104184_Reserved26_31_OFFSET                  26
+#define D0F0xBC_xE0104184_Reserved26_31_WIDTH                   6
+#define D0F0xBC_xE0104184_Reserved26_31_MASK                    0xfc000000
+
+/// D0F0xBC_xE0104184
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       SviLoadLineTrimVdd:3 ; ///<
+    UINT32                                     SviLoadLineTrimVddNb:3 ; ///<
+    UINT32                                     SviLoadLineOffsetVdd:2 ; ///<
+    UINT32                                   SviLoadLineOffsetVddNb:2 ; ///<
+    UINT32                                                 VCEFlag0:8 ; ///<
+    UINT32                                                 VCEFlag1:8 ; ///<
+    UINT32                                            Reserved26_31:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104184_STRUCT;
+
+// **** D0F0xBC_xE0104187 Field Definition ****
+// Address
+#define D0F0xBC_xE0104187_ADDRESS                               0xe0104187
+
+// Type
+#define D0F0xBC_xE0104187_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104187_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE0104187_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE0104187_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE0104187_VCEFlag2_OFFSET                       2
+#define D0F0xBC_xE0104187_VCEFlag2_WIDTH                        8
+#define D0F0xBC_xE0104187_VCEFlag2_MASK                         0x3fc
+#define D0F0xBC_xE0104187_Reserved10_31_OFFSET                  10
+#define D0F0xBC_xE0104187_Reserved10_31_WIDTH                   22
+#define D0F0xBC_xE0104187_Reserved10_31_MASK                    0xfffffc00
+
+/// D0F0xBC_xE0104187
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                                 VCEFlag2:8 ; ///<
+    UINT32                                            Reserved10_31:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104187_STRUCT;
+
+// **** D0F0xBC_xE0104188 Field Definition ****
+// Address
+#define D0F0xBC_xE0104188_ADDRESS                               0xe0104188
+
+// Type
+#define D0F0xBC_xE0104188_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104188_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE0104188_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE0104188_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE0104188_VCEFlag3_OFFSET                       2
+#define D0F0xBC_xE0104188_VCEFlag3_WIDTH                        8
+#define D0F0xBC_xE0104188_VCEFlag3_MASK                         0x3fc
+#define D0F0xBC_xE0104188_ReqSclkSel0_OFFSET                    10
+#define D0F0xBC_xE0104188_ReqSclkSel0_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel0_MASK                      0x1c00
+#define D0F0xBC_xE0104188_ReqSclkSel1_OFFSET                    13
+#define D0F0xBC_xE0104188_ReqSclkSel1_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel1_MASK                      0xe000
+#define D0F0xBC_xE0104188_ReqSclkSel2_OFFSET                    16
+#define D0F0xBC_xE0104188_ReqSclkSel2_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel2_MASK                      0x70000
+#define D0F0xBC_xE0104188_ReqSclkSel3_OFFSET                    19
+#define D0F0xBC_xE0104188_ReqSclkSel3_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel3_MASK                      0x380000
+#define D0F0xBC_xE0104188_VCEMclk_OFFSET                        22
+#define D0F0xBC_xE0104188_VCEMclk_WIDTH                         4
+#define D0F0xBC_xE0104188_VCEMclk_MASK                          0x3c00000
+#define D0F0xBC_xE0104188_LhtcPstateLimit_OFFSET                26
+#define D0F0xBC_xE0104188_LhtcPstateLimit_WIDTH                 3
+#define D0F0xBC_xE0104188_LhtcPstateLimit_MASK                  0x1c000000
+#define D0F0xBC_xE0104188_BapmMeasuredTemp_OFFSET               29
+#define D0F0xBC_xE0104188_BapmMeasuredTemp_WIDTH                1
+#define D0F0xBC_xE0104188_BapmMeasuredTemp_MASK                 0x20000000
+#define D0F0xBC_xE0104188_BapmDisable_OFFSET                    30
+#define D0F0xBC_xE0104188_BapmDisable_WIDTH                     1
+#define D0F0xBC_xE0104188_BapmDisable_MASK                      0x40000000
+#define D0F0xBC_xE0104188_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0104188_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0104188_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0104188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                                 VCEFlag3:8 ; ///<
+    UINT32                                              ReqSclkSel0:3 ; ///<
+    UINT32                                              ReqSclkSel1:3 ; ///<
+    UINT32                                              ReqSclkSel2:3 ; ///<
+    UINT32                                              ReqSclkSel3:3 ; ///<
+    UINT32                                                  VCEMclk:4 ; ///<
+    UINT32                                          LhtcPstateLimit:3 ; ///<
+    UINT32                                         BapmMeasuredTemp:1 ; ///<
+    UINT32                                              BapmDisable:1 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104188_STRUCT;
+
+// **** D0F0xBC_xE0106020 Field Definition ****
+// Address
+#define D0F0xBC_xE0106020_ADDRESS                               0xe0106020
+
+// Type
+#define D0F0xBC_xE0106020_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0106020_Reserved0_24_OFFSET                   0
+#define D0F0xBC_xE0106020_Reserved0_24_WIDTH                    25
+#define D0F0xBC_xE0106020_Reserved0_24_MASK                     0x1ffffff
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET          25
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH           2
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_MASK            0x6000000
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET          27
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH           2
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_MASK            0x18000000
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET          29
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH           2
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_MASK            0x60000000
+#define D0F0xBC_xE0106020_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0106020_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0106020_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0106020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved0_24:25; ///<
+    UINT32                                    PowerplayDClkVClkSel0:2 ; ///<
+    UINT32                                    PowerplayDClkVClkSel1:2 ; ///<
+    UINT32                                    PowerplayDClkVClkSel2:2 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0106020_STRUCT;
+
+// **** D0F0xBC_xE0106023 Field Definition ****
+// Address
+#define D0F0xBC_xE0106023_ADDRESS                               0xe0106023
+
+// Type
+#define D0F0xBC_xE0106023_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0106023_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE0106023_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE0106023_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET          7
+#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH           2
+#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_MASK            0x180
+#define D0F0xBC_xE0106023_Reserved9_31_OFFSET                   9
+#define D0F0xBC_xE0106023_Reserved9_31_WIDTH                    23
+#define D0F0xBC_xE0106023_Reserved9_31_MASK                     0xfffffe00
+
+/// D0F0xBC_xE0106023
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                    PowerplayDClkVClkSel3:2 ; ///<
+    UINT32                                             Reserved9_31:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0106023_STRUCT;
+
+// **** D0F0xBC_xE0106024 Field Definition ****
+// Address
+#define D0F0xBC_xE0106024_ADDRESS                               0xe0106024
+
+// Type
+#define D0F0xBC_xE0106024_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0106024_Reserved0_0_OFFSET                    0
+#define D0F0xBC_xE0106024_Reserved0_0_WIDTH                     1
+#define D0F0xBC_xE0106024_Reserved0_0_MASK                      0x1
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET          1
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH           2
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_MASK            0x6
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET          3
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH           2
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_MASK            0x18
+#define D0F0xBC_xE0106024_Reserved5_31_OFFSET                   5
+#define D0F0xBC_xE0106024_Reserved5_31_WIDTH                    27
+#define D0F0xBC_xE0106024_Reserved5_31_MASK                     0xffffffe0
+
+/// D0F0xBC_xE0106024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_0:1 ; ///<
+    UINT32                                    PowerplayDClkVClkSel4:2 ; ///<
+    UINT32                                    PowerplayDClkVClkSel5:2 ; ///<
+    UINT32                                             Reserved5_31:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0106024_STRUCT;
+
+
+// **** D0F0xBC_xE010705C Field Definition ****
+// Address
+#define D0F0xBC_xE010705C_ADDRESS                               0xe010705c
+
+// Type
+#define D0F0xBC_xE010705C_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010705C_Reserved0_17_OFFSET                   0
+#define D0F0xBC_xE010705C_Reserved0_17_WIDTH                    18
+#define D0F0xBC_xE010705C_Reserved0_17_MASK                     0x3ffff
+#define D0F0xBC_xE010705C_PowerplayTableRev_OFFSET              18
+#define D0F0xBC_xE010705C_PowerplayTableRev_WIDTH               4
+#define D0F0xBC_xE010705C_PowerplayTableRev_MASK                0x3c0000
+#define D0F0xBC_xE010705C_SClkThermDid_OFFSET                   22
+#define D0F0xBC_xE010705C_SClkThermDid_WIDTH                    7
+#define D0F0xBC_xE010705C_SClkThermDid_MASK                     0x1fc00000
+#define D0F0xBC_xE010705C_PcieGen2Vid_OFFSET                    29
+#define D0F0xBC_xE010705C_PcieGen2Vid_WIDTH                     2
+#define D0F0xBC_xE010705C_PcieGen2Vid_MASK                      0x60000000
+#define D0F0xBC_xE010705C_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE010705C_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE010705C_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE010705C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved0_17:18; ///<
+    UINT32                                        PowerplayTableRev:4 ; ///<
+    UINT32                                             SClkThermDid:7 ; ///<
+    UINT32                                              PcieGen2Vid:2 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010705C_STRUCT;
+
+// **** D0F0xBC_xE010705F Field Definition ****
+// Address
+#define D0F0xBC_xE010705F_ADDRESS                               0xe010705f
+
+// Type
+#define D0F0xBC_xE010705F_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010705F_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010705F_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010705F_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010705F_SClkDpmVid0_OFFSET                    7
+#define D0F0xBC_xE010705F_SClkDpmVid0_WIDTH                     2
+#define D0F0xBC_xE010705F_SClkDpmVid0_MASK                      0x180
+#define D0F0xBC_xE010705F_Reserved9_31_OFFSET                   9
+#define D0F0xBC_xE010705F_Reserved9_31_WIDTH                    23
+#define D0F0xBC_xE010705F_Reserved9_31_MASK                     0xfffffe00
+
+/// D0F0xBC_xE010705F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                              SClkDpmVid0:2 ; ///<
+    UINT32                                             Reserved9_31:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010705F_STRUCT;
+
+// **** D0F0xBC_xE0107060 Field Definition ****
+// Address
+#define D0F0xBC_xE0107060_ADDRESS                               0xe0107060
+
+// Type
+#define D0F0xBC_xE0107060_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107060_Reserved0_0_OFFSET                    0
+#define D0F0xBC_xE0107060_Reserved0_0_WIDTH                     1
+#define D0F0xBC_xE0107060_Reserved0_0_MASK                      0x1
+#define D0F0xBC_xE0107060_SClkDpmVid1_OFFSET                    1
+#define D0F0xBC_xE0107060_SClkDpmVid1_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid1_MASK                      0x6
+#define D0F0xBC_xE0107060_SClkDpmVid2_OFFSET                    3
+#define D0F0xBC_xE0107060_SClkDpmVid2_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid2_MASK                      0x18
+#define D0F0xBC_xE0107060_SClkDpmVid3_OFFSET                    5
+#define D0F0xBC_xE0107060_SClkDpmVid3_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid3_MASK                      0x60
+#define D0F0xBC_xE0107060_SClkDpmVid4_OFFSET                    7
+#define D0F0xBC_xE0107060_SClkDpmVid4_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid4_MASK                      0x180
+#define D0F0xBC_xE0107060_SClkDpmDid0_OFFSET                    9
+#define D0F0xBC_xE0107060_SClkDpmDid0_WIDTH                     7
+#define D0F0xBC_xE0107060_SClkDpmDid0_MASK                      0xfe00
+#define D0F0xBC_xE0107060_SClkDpmDid1_OFFSET                    16
+#define D0F0xBC_xE0107060_SClkDpmDid1_WIDTH                     7
+#define D0F0xBC_xE0107060_SClkDpmDid1_MASK                      0x7f0000
+#define D0F0xBC_xE0107060_SClkDpmDid2_OFFSET                    23
+#define D0F0xBC_xE0107060_SClkDpmDid2_WIDTH                     7
+#define D0F0xBC_xE0107060_SClkDpmDid2_MASK                      0x3f800000
+#define D0F0xBC_xE0107060_Reserved30_31_OFFSET                  30
+#define D0F0xBC_xE0107060_Reserved30_31_WIDTH                   2
+#define D0F0xBC_xE0107060_Reserved30_31_MASK                    0xc0000000
+
+/// D0F0xBC_xE0107060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_0:1 ; ///<
+    UINT32                                              SClkDpmVid1:2 ; ///<
+    UINT32                                              SClkDpmVid2:2 ; ///<
+    UINT32                                              SClkDpmVid3:2 ; ///<
+    UINT32                                              SClkDpmVid4:2 ; ///<
+    UINT32                                              SClkDpmDid0:7 ; ///<
+    UINT32                                              SClkDpmDid1:7 ; ///<
+    UINT32                                              SClkDpmDid2:7 ; ///<
+    UINT32                                            Reserved30_31:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107060_STRUCT;
+
+// **** D0F0xBC_xE0107063 Field Definition ****
+// Address
+#define D0F0xBC_xE0107063_ADDRESS                               0xe0107063
+
+// Type
+#define D0F0xBC_xE0107063_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107063_Reserved0_5_OFFSET                    0
+#define D0F0xBC_xE0107063_Reserved0_5_WIDTH                     6
+#define D0F0xBC_xE0107063_Reserved0_5_MASK                      0x3f
+#define D0F0xBC_xE0107063_SClkDpmDid3_OFFSET                    6
+#define D0F0xBC_xE0107063_SClkDpmDid3_WIDTH                     7
+#define D0F0xBC_xE0107063_SClkDpmDid3_MASK                      0x1fc0
+#define D0F0xBC_xE0107063_Reserved13_31_OFFSET                  13
+#define D0F0xBC_xE0107063_Reserved13_31_WIDTH                   19
+#define D0F0xBC_xE0107063_Reserved13_31_MASK                    0xffffe000
+
+/// D0F0xBC_xE0107063
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_5:6 ; ///<
+    UINT32                                              SClkDpmDid3:7 ; ///<
+    UINT32                                            Reserved13_31:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107063_STRUCT;
+
+// **** D0F0xBC_xE0107064 Field Definition ****
+// Address
+#define D0F0xBC_xE0107064_ADDRESS                               0xe0107064
+
+// Type
+#define D0F0xBC_xE0107064_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107064_Reserved0_4_OFFSET                    0
+#define D0F0xBC_xE0107064_Reserved0_4_WIDTH                     5
+#define D0F0xBC_xE0107064_Reserved0_4_MASK                      0x1f
+#define D0F0xBC_xE0107064_SClkDpmDid4_OFFSET                    5
+#define D0F0xBC_xE0107064_SClkDpmDid4_WIDTH                     7
+#define D0F0xBC_xE0107064_SClkDpmDid4_MASK                      0xfe0
+#define D0F0xBC_xE0107064_Reserved12_31_OFFSET                  12
+#define D0F0xBC_xE0107064_Reserved12_31_WIDTH                   20
+#define D0F0xBC_xE0107064_Reserved12_31_MASK                    0xfffff000
+
+/// D0F0xBC_xE0107064
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_4:5 ; ///<
+    UINT32                                              SClkDpmDid4:7 ; ///<
+    UINT32                                            Reserved12_31:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107064_STRUCT;
+
+// **** D0F0xBC_xE0107067 Field Definition ****
+// Address
+#define D0F0xBC_xE0107067_ADDRESS                               0xe0107067
+
+// Type
+#define D0F0xBC_xE0107067_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107067_Reserved0_3_OFFSET                    0
+#define D0F0xBC_xE0107067_Reserved0_3_WIDTH                     4
+#define D0F0xBC_xE0107067_Reserved0_3_MASK                      0xf
+#define D0F0xBC_xE0107067_DispClkDid0_OFFSET                    4
+#define D0F0xBC_xE0107067_DispClkDid0_WIDTH                     7
+#define D0F0xBC_xE0107067_DispClkDid0_MASK                      0x7f0
+#define D0F0xBC_xE0107067_Reserved11_31_OFFSET                  11
+#define D0F0xBC_xE0107067_Reserved11_31_WIDTH                   21
+#define D0F0xBC_xE0107067_Reserved11_31_MASK                    0xfffff800
+
+/// D0F0xBC_xE0107067
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_3:4 ; ///<
+    UINT32                                              DispClkDid0:7 ; ///<
+    UINT32                                            Reserved11_31:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107067_STRUCT;
+
+// **** D0F0xBC_xE0107068 Field Definition ****
+// Address
+#define D0F0xBC_xE0107068_ADDRESS                               0xe0107068
+
+// Type
+#define D0F0xBC_xE0107068_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107068_Reserved0_2_OFFSET                    0
+#define D0F0xBC_xE0107068_Reserved0_2_WIDTH                     3
+#define D0F0xBC_xE0107068_Reserved0_2_MASK                      0x7
+#define D0F0xBC_xE0107068_DispClkDid1_OFFSET                    3
+#define D0F0xBC_xE0107068_DispClkDid1_WIDTH                     7
+#define D0F0xBC_xE0107068_DispClkDid1_MASK                      0x3f8
+#define D0F0xBC_xE0107068_DispClkDid2_OFFSET                    10
+#define D0F0xBC_xE0107068_DispClkDid2_WIDTH                     7
+#define D0F0xBC_xE0107068_DispClkDid2_MASK                      0x1fc00
+#define D0F0xBC_xE0107068_DispClkDid3_OFFSET                    17
+#define D0F0xBC_xE0107068_DispClkDid3_WIDTH                     7
+#define D0F0xBC_xE0107068_DispClkDid3_MASK                      0xfe0000
+#define D0F0xBC_xE0107068_LClkDpmDid0_OFFSET                    24
+#define D0F0xBC_xE0107068_LClkDpmDid0_WIDTH                     7
+#define D0F0xBC_xE0107068_LClkDpmDid0_MASK                      0x7f000000
+#define D0F0xBC_xE0107068_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0107068_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0107068_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0107068
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_2:3 ; ///<
+    UINT32                                              DispClkDid1:7 ; ///<
+    UINT32                                              DispClkDid2:7 ; ///<
+    UINT32                                              DispClkDid3:7 ; ///<
+    UINT32                                              LClkDpmDid0:7 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107068_STRUCT;
+
+// **** D0F0xBC_xE010706B Field Definition ****
+// Address
+#define D0F0xBC_xE010706B_ADDRESS                               0xe010706b
+
+// Type
+#define D0F0xBC_xE010706B_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010706B_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010706B_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010706B_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010706B_LClkDpmDid1_OFFSET                    7
+#define D0F0xBC_xE010706B_LClkDpmDid1_WIDTH                     7
+#define D0F0xBC_xE010706B_LClkDpmDid1_MASK                      0x3f80
+#define D0F0xBC_xE010706B_Reserved14_31_OFFSET                  14
+#define D0F0xBC_xE010706B_Reserved14_31_WIDTH                   18
+#define D0F0xBC_xE010706B_Reserved14_31_MASK                    0xffffc000
+
+/// D0F0xBC_xE010706B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                              LClkDpmDid1:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010706B_STRUCT;
+
+// **** D0F0xBC_xE010706C Field Definition ****
+// Address
+#define D0F0xBC_xE010706C_ADDRESS                               0xe010706c
+
+// Type
+#define D0F0xBC_xE010706C_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010706C_Reserved0_5_OFFSET                    0
+#define D0F0xBC_xE010706C_Reserved0_5_WIDTH                     6
+#define D0F0xBC_xE010706C_Reserved0_5_MASK                      0x3f
+#define D0F0xBC_xE010706C_LClkDpmDid2_OFFSET                    6
+#define D0F0xBC_xE010706C_LClkDpmDid2_WIDTH                     7
+#define D0F0xBC_xE010706C_LClkDpmDid2_MASK                      0x1fc0
+#define D0F0xBC_xE010706C_LClkDpmDid3_OFFSET                    13
+#define D0F0xBC_xE010706C_LClkDpmDid3_WIDTH                     7
+#define D0F0xBC_xE010706C_LClkDpmDid3_MASK                      0xfe000
+#define D0F0xBC_xE010706C_LClkDpmValid_OFFSET                   20
+#define D0F0xBC_xE010706C_LClkDpmValid_WIDTH                    4
+#define D0F0xBC_xE010706C_LClkDpmValid_MASK                     0xf00000
+#define D0F0xBC_xE010706C_DClkDid0_OFFSET                       24
+#define D0F0xBC_xE010706C_DClkDid0_WIDTH                        7
+#define D0F0xBC_xE010706C_DClkDid0_MASK                         0x7f000000
+#define D0F0xBC_xE010706C_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE010706C_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE010706C_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE010706C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_5:6 ; ///<
+    UINT32                                              LClkDpmDid2:7 ; ///<
+    UINT32                                              LClkDpmDid3:7 ; ///<
+    UINT32                                             LClkDpmValid:4 ; ///<
+    UINT32                                                 DClkDid0:7 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010706C_STRUCT;
+
+// **** D0F0xBC_xE010706F Field Definition ****
+// Address
+#define D0F0xBC_xE010706F_ADDRESS                               0xe010706f
+
+// Type
+#define D0F0xBC_xE010706F_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010706F_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010706F_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010706F_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010706F_DClkDid1_OFFSET                       7
+#define D0F0xBC_xE010706F_DClkDid1_WIDTH                        7
+#define D0F0xBC_xE010706F_DClkDid1_MASK                         0x3f80
+#define D0F0xBC_xE010706F_Reserved14_31_OFFSET                  14
+#define D0F0xBC_xE010706F_Reserved14_31_WIDTH                   18
+#define D0F0xBC_xE010706F_Reserved14_31_MASK                    0xffffc000
+
+/// D0F0xBC_xE010706F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                                 DClkDid1:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010706F_STRUCT;
+
+// **** D0F0xBC_xE0107070 Field Definition ****
+// Address
+#define D0F0xBC_xE0107070_ADDRESS                               0xe0107070
+
+// Type
+#define D0F0xBC_xE0107070_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107070_Reserved0_5_OFFSET                    0
+#define D0F0xBC_xE0107070_Reserved0_5_WIDTH                     6
+#define D0F0xBC_xE0107070_Reserved0_5_MASK                      0x3f
+#define D0F0xBC_xE0107070_DClkDid2_OFFSET                       6
+#define D0F0xBC_xE0107070_DClkDid2_WIDTH                        7
+#define D0F0xBC_xE0107070_DClkDid2_MASK                         0x1fc0
+#define D0F0xBC_xE0107070_DClkDid3_OFFSET                       13
+#define D0F0xBC_xE0107070_DClkDid3_WIDTH                        7
+#define D0F0xBC_xE0107070_DClkDid3_MASK                         0xfe000
+#define D0F0xBC_xE0107070_VClkDid0_OFFSET                       20
+#define D0F0xBC_xE0107070_VClkDid0_WIDTH                        7
+#define D0F0xBC_xE0107070_VClkDid0_MASK                         0x7f00000
+#define D0F0xBC_xE0107070_Reserved27_31_OFFSET                  27
+#define D0F0xBC_xE0107070_Reserved27_31_WIDTH                   5
+#define D0F0xBC_xE0107070_Reserved27_31_MASK                    0xf8000000
+
+/// D0F0xBC_xE0107070
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_5:6 ; ///<
+    UINT32                                                 DClkDid2:7 ; ///<
+    UINT32                                                 DClkDid3:7 ; ///<
+    UINT32                                                 VClkDid0:7 ; ///<
+    UINT32                                            Reserved27_31:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107070_STRUCT;
+
+// **** D0F0xBC_xE0107073 Field Definition ****
+// Address
+#define D0F0xBC_xE0107073_ADDRESS                               0xe0107073
+
+// Type
+#define D0F0xBC_xE0107073_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107073_Reserved0_2_OFFSET                    0
+#define D0F0xBC_xE0107073_Reserved0_2_WIDTH                     3
+#define D0F0xBC_xE0107073_Reserved0_2_MASK                      0x7
+#define D0F0xBC_xE0107073_VClkDid1_OFFSET                       3
+#define D0F0xBC_xE0107073_VClkDid1_WIDTH                        7
+#define D0F0xBC_xE0107073_VClkDid1_MASK                         0x3f8
+#define D0F0xBC_xE0107073_Reserved10_31_OFFSET                  10
+#define D0F0xBC_xE0107073_Reserved10_31_WIDTH                   22
+#define D0F0xBC_xE0107073_Reserved10_31_MASK                    0xfffffc00
+
+/// D0F0xBC_xE0107073
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_2:3 ; ///<
+    UINT32                                                 VClkDid1:7 ; ///<
+    UINT32                                            Reserved10_31:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107073_STRUCT;
+
+// **** D0F0xBC_xE0107074 Field Definition ****
+// Address
+#define D0F0xBC_xE0107074_ADDRESS                               0xe0107074
+
+// Type
+#define D0F0xBC_xE0107074_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107074_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE0107074_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE0107074_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE0107074_VClkDid2_OFFSET                       2
+#define D0F0xBC_xE0107074_VClkDid2_WIDTH                        7
+#define D0F0xBC_xE0107074_VClkDid2_MASK                         0x1fc
+#define D0F0xBC_xE0107074_VClkDid3_OFFSET                       9
+#define D0F0xBC_xE0107074_VClkDid3_WIDTH                        7
+#define D0F0xBC_xE0107074_VClkDid3_MASK                         0xfe00
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET         16
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH          5
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_MASK           0x1f0000
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET         21
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH          5
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_MASK           0x3e00000
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET         26
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH          5
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_MASK           0x7c000000
+#define D0F0xBC_xE0107074_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0107074_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0107074_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0107074
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                                 VClkDid2:7 ; ///<
+    UINT32                                                 VClkDid3:7 ; ///<
+    UINT32                                   PowerplaySclkDpmValid0:5 ; ///<
+    UINT32                                   PowerplaySclkDpmValid1:5 ; ///<
+    UINT32                                   PowerplaySclkDpmValid2:5 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107074_STRUCT;
+
+// **** D0F0xBC_xE0107077 Field Definition ****
+// Address
+#define D0F0xBC_xE0107077_ADDRESS                               0xe0107077
+
+// Type
+#define D0F0xBC_xE0107077_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107077_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE0107077_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE0107077_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET         7
+#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH          5
+#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_MASK           0xf80
+#define D0F0xBC_xE0107077_Reserved12_31_OFFSET                  12
+#define D0F0xBC_xE0107077_Reserved12_31_WIDTH                   20
+#define D0F0xBC_xE0107077_Reserved12_31_MASK                    0xfffff000
+
+/// D0F0xBC_xE0107077
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                   PowerplaySclkDpmValid3:5 ; ///<
+    UINT32                                            Reserved12_31:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107077_STRUCT;
+
+// **** D0F0xBC_xE0107078 Field Definition ****
+// Address
+#define D0F0xBC_xE0107078_ADDRESS                               0xe0107078
+
+// Type
+#define D0F0xBC_xE0107078_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107078_Reserved0_3_OFFSET                    0
+#define D0F0xBC_xE0107078_Reserved0_3_WIDTH                     4
+#define D0F0xBC_xE0107078_Reserved0_3_MASK                      0xf
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET         4
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH          5
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_MASK           0x1f0
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET         9
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH          5
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_MASK           0x3e00
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET          14
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_MASK            0xc000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET          16
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_MASK            0x30000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET          18
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_MASK            0xc0000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET          20
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_MASK            0x300000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET          22
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_MASK            0xc00000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET          24
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_MASK            0x3000000
+#define D0F0xBC_xE0107078_Reserved26_31_OFFSET                  26
+#define D0F0xBC_xE0107078_Reserved26_31_WIDTH                   6
+#define D0F0xBC_xE0107078_Reserved26_31_MASK                    0xfc000000
+
+/// D0F0xBC_xE0107078
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_3:4 ; ///<
+    UINT32                                   PowerplaySclkDpmValid4:5 ; ///<
+    UINT32                                   PowerplaySclkDpmValid5:5 ; ///<
+    UINT32                                    PowerplayPolicyLabel0:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel1:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel2:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel3:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel4:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel5:2 ; ///<
+    UINT32                                            Reserved26_31:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107078_STRUCT;
+
+// **** D0F0xBC_xE010707B Field Definition ****
+// Address
+#define D0F0xBC_xE010707B_ADDRESS                               0xe010707b
+
+// Type
+#define D0F0xBC_xE010707B_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010707B_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE010707B_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE010707B_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET            2
+#define D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH             7
+#define D0F0xBC_xE010707B_PowerplayStateFlag0_MASK              0x1fc
+#define D0F0xBC_xE010707B_Reserved9_31_OFFSET                   9
+#define D0F0xBC_xE010707B_Reserved9_31_WIDTH                    23
+#define D0F0xBC_xE010707B_Reserved9_31_MASK                     0xfffffe00
+
+/// D0F0xBC_xE010707B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                      PowerplayStateFlag0:7 ; ///<
+    UINT32                                             Reserved9_31:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010707B_STRUCT;
+
+// **** D0F0xBC_xE010707C Field Definition ****
+// Address
+#define D0F0xBC_xE010707C_ADDRESS                               0xe010707c
+
+// Type
+#define D0F0xBC_xE010707C_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010707C_Reserved0_0_OFFSET                    0
+#define D0F0xBC_xE010707C_Reserved0_0_WIDTH                     1
+#define D0F0xBC_xE010707C_Reserved0_0_MASK                      0x1
+#define D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET            1
+#define D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag1_MASK              0xfe
+#define D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET            8
+#define D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag2_MASK              0x7f00
+#define D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET            15
+#define D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag3_MASK              0x3f8000
+#define D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET            22
+#define D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag4_MASK              0x1fc00000
+#define D0F0xBC_xE010707C_Reserved29_31_OFFSET                  29
+#define D0F0xBC_xE010707C_Reserved29_31_WIDTH                   3
+#define D0F0xBC_xE010707C_Reserved29_31_MASK                    0xe0000000
+
+/// D0F0xBC_xE010707C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_0:1 ; ///<
+    UINT32                                      PowerplayStateFlag1:7 ; ///<
+    UINT32                                      PowerplayStateFlag2:7 ; ///<
+    UINT32                                      PowerplayStateFlag3:7 ; ///<
+    UINT32                                      PowerplayStateFlag4:7 ; ///<
+    UINT32                                            Reserved29_31:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010707C_STRUCT;
+
+// **** D0F0xBC_xE010707F Field Definition ****
+// Address
+#define D0F0xBC_xE010707F_ADDRESS                               0xe010707f
+
+// Type
+#define D0F0xBC_xE010707F_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010707F_Reserved0_4_OFFSET                    0
+#define D0F0xBC_xE010707F_Reserved0_4_WIDTH                     5
+#define D0F0xBC_xE010707F_Reserved0_4_MASK                      0x1f
+#define D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET            5
+#define D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH             7
+#define D0F0xBC_xE010707F_PowerplayStateFlag5_MASK              0xfe0
+#define D0F0xBC_xE010707F_Reserved12_31_OFFSET                  12
+#define D0F0xBC_xE010707F_Reserved12_31_WIDTH                   20
+#define D0F0xBC_xE010707F_Reserved12_31_MASK                    0xfffff000
+
+/// D0F0xBC_xE010707F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_4:5 ; ///<
+    UINT32                                      PowerplayStateFlag5:7 ; ///<
+    UINT32                                            Reserved12_31:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010707F_STRUCT;
+
+// **** D0F0xBC_x1F630 Register Definition ****
+// Address
+#define D0F0xBC_x1F630_ADDRESS                                  0x1f630
+
+// Type
+#define D0F0xBC_x1F630_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F630_RECONF_WAIT_OFFSET                       0
+#define D0F0xBC_x1F630_RECONF_WAIT_WIDTH                        8
+#define D0F0xBC_x1F630_RECONF_WAIT_MASK                         0xff
+#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET                    8
+#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH                     8
+#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK                      0x00ff00
+
+/// D0F0xBC_x1F630
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              RECONF_WAIT:8;  ///<
+    UINT32                                           RECONF_WRAPPER:8;  ///<
+    UINT32                                                Reserved:16;  ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F630_STRUCT;
+
+// **** D0F0xE4_WRAP_8012 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8012_ADDRESS                               0x8012
+
+// Type
+#define D0F0xE4_WRAP_8012_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET           0
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK             0x3f
+#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET            7
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK              0x80
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET         8
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK           0x3f00
+#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET         16
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK           0x3f0000
+#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET          23
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH           1
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK            0x800000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET       24
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH        6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK         0x3f000000
+#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     Pif1xIdleGateLatency:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                      Pif1xIdleGateEnable:1 ; ///<
+    UINT32                                   Pif1xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                   Pif2p5xIdleGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    Pif2p5xIdleGateEnable:1 ; ///<
+    UINT32                                 Pif2p5xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8012_STRUCT;
+
+// **** D0F0xE4_WRAP_8014 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8014_ADDRESS                               0x8014
+
+// Type
+#define D0F0xE4_WRAP_8014_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET            0
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK              0x1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET            1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK              0x2
+#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_OFFSET            2
+#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_MASK              0x4
+#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_OFFSET            3
+#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_MASK              0x8
+#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_OFFSET            4
+#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_MASK              0x10
+#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_OFFSET            5
+#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_MASK              0x20
+#define D0F0xE4_WRAP_8014_Reserved_7_6_OFFSET                   6
+#define D0F0xE4_WRAP_8014_Reserved_7_6_WIDTH                    2
+#define D0F0xE4_WRAP_8014_Reserved_7_6_MASK                     0xc0
+#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_OFFSET          8
+#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_MASK            0x100
+#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_OFFSET          9
+#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_MASK            0x200
+#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_OFFSET          10
+#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_MASK            0x400
+#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_OFFSET          11
+#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_MASK            0x800
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET           12
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK             0x1000
+#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET           13
+#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK             0x2000
+#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET           14
+#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK             0x4000
+#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET           15
+#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK             0x8000
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET         16
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK           0x10000
+#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_OFFSET         17
+#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_MASK           0x20000
+#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_OFFSET         18
+#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_MASK           0x40000
+#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_OFFSET         19
+#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_MASK           0x80000
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET  20
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH   1
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK    0x100000
+#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET                 21
+#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH                  3
+#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK                   0xe00000
+#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_OFFSET              24
+#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_MASK                0x1000000
+#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_OFFSET              25
+#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_MASK                0x2000000
+#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_OFFSET              26
+#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_MASK                0x4000000
+#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_OFFSET              27
+#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_MASK                0x8000000
+#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET                     28
+#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH                      4
+#define D0F0xE4_WRAP_8014_SpareRegRw_MASK                       0xf0000000
+
+/// D0F0xE4_WRAP_8014
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      TxclkPermGateEnable:1 ; ///<
+    UINT32                                      TxclkPrbsGateEnable:1 ; ///<
+    UINT32                                      DdiGatePifA1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifB1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifC1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifD1xEnable:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                    DdiGatePifA2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifB2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifC2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifD2p5xEnable:1 ; ///<
+    UINT32                                     PcieGatePifA1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifB1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifC1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifD1xEnable:1 ; ///<
+    UINT32                                   PcieGatePifA2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifB2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifC2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifD2p5xEnable:1 ; ///<
+    UINT32                            TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                        DdiGateDigAEnable:1 ; ///<
+    UINT32                                        DdiGateDigBEnable:1 ; ///<
+    UINT32                                        DdiGateDigCEnable:1 ; ///<
+    UINT32                                        DdiGateDigDEnable:1 ; ///<
+    UINT32                                               SpareRegRw:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8014_STRUCT;
+
+// **** D0F0xE4_WRAP_8015 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8015_ADDRESS                               0x8015
+
+// Type
+#define D0F0xE4_WRAP_8015_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET          16
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK            0x3f0000
+#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET           23
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK             0x800000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET          24
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK            0x3f000000
+#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET                 30
+#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK                   0x40000000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET           31
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK             0x80000000
+
+/// D0F0xE4_WRAP_8015
+typedef union {
+  struct {                                                              ///<
+    UINT32  /*                                      EnableD0StateReport*/:1 ; ///<
+    UINT32  /*                                             Reserved_1_1*/:1 ; ///<
+    UINT32  line477/*                               SlowRefclkThroughTxclk2p5x*/:1 ; ///<
+    UINT32  line478/*                                SlowRefclkEnableTxclk2p5x*/:1 ; ///<
+    UINT32  line479/*                                SlowRefclkDivideTxclk2p5x*/:2 ; ///<
+    UINT32  line480/*                                 SlowRefclkBurstTxclk2p5x*/:2 ; ///<
+    UINT32  /*                                             Reserved_8_8*/:1 ; ///<
+    UINT32  line482/*                                  SlowRefclkLcntGateForce*/:1 ; ///<
+    UINT32  line483/*                                 SlowRefclkThroughTxclk1x*/:1 ; ///<
+    UINT32  line484/*                                  SlowRefclkEnableTxclk1x*/:1 ; ///<
+    UINT32  line485/*                                  SlowRefclkDivideTxclk1x*/:2 ; ///<
+    UINT32  line486/*                                   SlowRefclkBurstTxclk1x*/:2 ; ///<
+    UINT32                                    RefclkRegsGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                     RefclkRegsGateEnable:1 ; ///<
+    UINT32                                    RefclkBphyGateLatency:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                     RefclkBphyGateEnable:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8015_STRUCT;
+
+// **** PGFSM_Delay_Reg_0 Register Definition ****
+// Address
+
+// **** GMMx670 Register Definition ****
+// Address
+#define GMMx670_ADDRESS                                         0x670
+
+// Type
+#define GMMx670_TYPE                                            TYPE_GMM
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1071_0:1;
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                             TdpClampMode:8 ; ///<
+    UINT32            ex1071_3:8;
+    UINT32            ex1071_4:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1071_STRUCT;
+
+
+
+// **** GMMx600 Register Definition ****
+// Address
+#define GMMx600_ADDRESS                                         0x600
+
+// Type
+#define GMMx600_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx600_IndClkDiv_OFFSET                                0
+#define GMMx600_IndClkDiv_WIDTH                                 7
+#define GMMx600_IndClkDiv_MASK                                  0x7f
+#define GMMx600_Reserved_7_7_OFFSET                             7
+#define GMMx600_Reserved_7_7_WIDTH                              1
+#define GMMx600_Reserved_7_7_MASK                               0x80
+#define GMMx600_ClkDirCntlEn_OFFSET                             8
+#define GMMx600_ClkDirCntlEn_WIDTH                              1
+#define GMMx600_ClkDirCntlEn_MASK                               0x100
+#define GMMx600_ClkDirCntlTog_OFFSET                            9
+#define GMMx600_ClkDirCntlTog_WIDTH                             1
+#define GMMx600_ClkDirCntlTog_MASK                              0x200
+#define GMMx600_ClkDirCntlDiv_OFFSET                            10
+#define GMMx600_ClkDirCntlDiv_WIDTH                             7
+#define GMMx600_ClkDirCntlDiv_MASK                              0x1fc00
+#define GMMx600_Reserved_31_17_OFFSET                           17
+#define GMMx600_Reserved_31_17_WIDTH                            15
+#define GMMx600_Reserved_31_17_MASK                             0xfffe0000
+
+/// GMMx600
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                IndClkDiv:7 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                             ClkDirCntlEn:1 ; ///<
+    UINT32                                            ClkDirCntlTog:1 ; ///<
+    UINT32                                            ClkDirCntlDiv:7 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx600_STRUCT;
+
+// **** GMMx604 Register Definition ****
+// Address
+#define GMMx604_ADDRESS                                         0x604
+
+// Type
+#define GMMx604_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx604_SclkStatus_OFFSET                               0
+#define GMMx604_SclkStatus_WIDTH                                1
+#define GMMx604_SclkStatus_MASK                                 0x1
+#define GMMx604_SclkForceStatus_OFFSET                          1
+#define GMMx604_SclkForceStatus_WIDTH                           1
+#define GMMx604_SclkForceStatus_MASK                            0x2
+#define GMMx604_SclkOverclkDetect_OFFSET                        2
+#define GMMx604_SclkOverclkDetect_WIDTH                         1
+#define GMMx604_SclkOverclkDetect_MASK                          0x4
+#define GMMx604_SclkDirCntlTogDone_OFFSET                       3
+#define GMMx604_SclkDirCntlTogDone_WIDTH                        1
+#define GMMx604_SclkDirCntlTogDone_MASK                         0x8
+#define GMMx604_Reserved_31_4_OFFSET                            4
+#define GMMx604_Reserved_31_4_WIDTH                             28
+#define GMMx604_Reserved_31_4_MASK                              0xfffffff0
+
+/// GMMx604
+typedef union {
+  struct {                                                              ///<
+    UINT64                                               SclkStatus:1 ; ///<
+    UINT64                                          SclkForceStatus:1 ; ///<
+    UINT64                                        SclkOverclkDetect:1 ; ///<
+    UINT64                                       SclkDirCntlTogDone:1 ; ///<
+    UINT64                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} GMMx604_STRUCT;
+
+// **** GMMx5F50 Register Definition ****
+// Address
+#define GMMx5F50_ADDRESS                                        0x5F50
+
+// Type
+#define GMMx5F50_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5F50_PortConnectivity_OFFSET                        0
+#define GMMx5F50_PortConnectivity_WIDTH                         3
+#define GMMx5F50_PortConnectivity_MASK                          0x7
+#define GMMx5F50_Reserved_3_3_OFFSET                            3
+#define GMMx5F50_Reserved_3_3_WIDTH                             1
+#define GMMx5F50_Reserved_3_3_MASK                              0x8
+#define GMMx5F50_PortConnectivityOverrideEnable_OFFSET          4
+#define GMMx5F50_PortConnectivityOverrideEnable_WIDTH           1
+#define GMMx5F50_PortConnectivityOverrideEnable_MASK            0x10
+#define GMMx5F50_Reserved_31_5_OFFSET                           5
+#define GMMx5F50_Reserved_31_5_WIDTH                            27
+#define GMMx5F50_Reserved_31_5_MASK                             0xffffffe0
+
+/// GMMx5F50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PortConnectivity:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                           PortConnectivityOverrideEnable:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5F50_STRUCT;
+
+// **** D0F0xE4_WRAP_8020 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8020_ADDRESS                               0x8020
+
+// Type
+#define D0F0xE4_WRAP_8020_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8020_Reserved_0_0_OFFSET                   0
+#define D0F0xE4_WRAP_8020_Reserved_0_0_WIDTH                    1
+#define D0F0xE4_WRAP_8020_Reserved_0_0_MASK                     0x1
+#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET               3
+#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_WIDTH                1
+#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK                 0x8
+#define D0F0xE4_WRAP_8020_Reserved_31_5_OFFSET                  5
+#define D0F0xE4_WRAP_8020_Reserved_31_5_WIDTH                   27
+#define D0F0xE4_WRAP_8020_Reserved_31_5_MASK                    0xffffffe0
+
+/// D0F0xE4_WRAP_8020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                           :2 ; ///<
+    UINT32                                         PrbsPcieLbSelect:1 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8020_STRUCT;
+
+// **** D0F0xE4_WRAP_8025 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8025_ADDRESS                               0x8025
+
+// Type
+#define D0F0xE4_WRAP_8025_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET                    0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK                      0x7
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET                    3
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK                      0x18
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET                   5
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK                     0x20
+#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET                   6
+#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH                    2
+#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK                     0xc0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET                    8
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK                      0x700
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET                    11
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK                      0x1800
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET                   13
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK                     0x2000
+#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET                    16
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK                      0x70000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET                    19
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK                      0x180000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET                   21
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK                     0x200000
+#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET                 22
+#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK                   0xc00000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET                    24
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK                      0x7000000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET                    27
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK                      0x18000000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET                   29
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK                     0x20000000
+#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8025
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LMTxPhyCmd0:3 ; ///<
+    UINT32                                              LMRxPhyCmd0:2 ; ///<
+    UINT32                                             LMLinkSpeed0:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                              LMTxPhyCmd1:3 ; ///<
+    UINT32                                              LMRxPhyCmd1:2 ; ///<
+    UINT32                                             LMLinkSpeed1:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                              LMTxPhyCmd2:3 ; ///<
+    UINT32                                              LMRxPhyCmd2:2 ; ///<
+    UINT32                                             LMLinkSpeed2:1 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              LMTxPhyCmd3:3 ; ///<
+    UINT32                                              LMRxPhyCmd3:2 ; ///<
+    UINT32                                             LMLinkSpeed3:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8025_STRUCT;
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1072_0:8;
+    UINT32                                               NumDropLsb:8 ; ///<
+    UINT32            ex1072_2:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1072_STRUCT;
+
+// **** D0F0xBC_x1F840 Register Definition ****
+// Address
+#define D0F0xBC_x1F840_ADDRESS                                  0x1f840
+
+// Type
+#define D0F0xBC_x1F840_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F840_IddspikeOCP_OFFSET                               0
+#define D0F0xBC_x1F840_IddspikeOCP_WIDTH                                16
+#define D0F0xBC_x1F840_IddspikeOCP_MASK                                 0xffff
+#define D0F0xBC_x1F840_IddNbspikeOCP_OFFSET                             16
+#define D0F0xBC_x1F840_IddNbspikeOCP_WIDTH                              16
+#define D0F0xBC_x1F840_IddNbspikeOCP_MASK                               0xffff0000
+
+/// D0F0xBC_x1F840
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IddspikeOCP:16; ///<
+    UINT32                                            IddNbspikeOCP:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F840_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1073_0:32;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1073_STRUCT;
+
+// **** D0F0xBC_xE010703C Register Definition ****
+// Address
+#define D0F0xBC_xE010703C_ADDRESS                               0xe010703c
+
+// Type
+#define D0F0xBC_xE010703C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE010703C_Reserved_2_0_OFFSET                   0
+#define D0F0xBC_xE010703C_Reserved_2_0_WIDTH                    3
+#define D0F0xBC_xE010703C_Reserved_2_0_MASK                     0x7
+#define D0F0xBC_xE010703C_NbPstateHi_OFFSET                     3
+#define D0F0xBC_xE010703C_NbPstateHi_WIDTH                      2
+#define D0F0xBC_xE010703C_NbPstateHi_MASK                       0x18
+#define D0F0xBC_xE010703C_NbPstateLo_OFFSET                     5
+#define D0F0xBC_xE010703C_NbPstateLo_WIDTH                      2
+#define D0F0xBC_xE010703C_NbPstateLo_MASK                       0x60
+#define D0F0xBC_xE010703C_Reserved_31_7_OFFSET                  7
+#define D0F0xBC_xE010703C_Reserved_31_7_WIDTH                   25
+#define D0F0xBC_xE010703C_Reserved_31_7_MASK                    0xffffff80
+
+/// D0F0xBC_xE010703C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                               NbPstateHi:2 ; ///<
+    UINT32                                               NbPstateLo:2 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010703C_STRUCT;
+
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1075_0:11;
+    UINT32                                           Reserved_31_11:21 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1075_STRUCT;
+
+
+
+// Address
+#define D0F0xBC_x1F480_ADDRESS                                  0x1f480
+
+// Type
+#define D0F0xBC_x1F480_TYPE                                     TYPE_D0F0xBC
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
new file mode 100644
index 0000000000..2fb8100c6d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
@@ -0,0 +1,153 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB early init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "GeneralServices.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[];
+extern  OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval                          Initialization status.
+ */
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early before CPU
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval                          Initialization status.
+ */
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  AGESA_STATUS            Status;
+
+  // Only run code on BSP
+  if (IsBsp (&EarlyParamsPtr->StdHeader, &Status)) {
+    Status = GnbLibDispatchFeatures (&GnbEarlierFeatureTable[0], &EarlyParamsPtr->StdHeader);
+  }
+
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
new file mode 100644
index 0000000000..3b0366a39a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
@@ -0,0 +1,164 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB env init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATENV_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[];
+extern  BUILD_OPT_CFG UserOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT   GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbEnvConfigPtr     Pointer to gnb env configuration params.
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ */
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT   GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+  GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex;
+  GnbEnvConfigPtr->IommuSupport = UserOptions.CfgIommuSupport;
+  GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum;
+  GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate;
+  GnbEnvConfigPtr->LvdsPowerOnSeqDigonToDe = UserOptions.CfgLvdsPowerOnSeqDigonToDe;
+  GnbEnvConfigPtr->LvdsPowerOnSeqDeToVaryBl = UserOptions.CfgLvdsPowerOnSeqDeToVaryBl;
+  GnbEnvConfigPtr->LvdsPowerOnSeqDeToDigon = UserOptions.CfgLvdsPowerOnSeqDeToDigon;
+  GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToDe = UserOptions.CfgLvdsPowerOnSeqVaryBlToDe;
+  GnbEnvConfigPtr->LvdsPowerOnSeqOnToOffDelay = UserOptions.CfgLvdsPowerOnSeqOnToOffDelay;
+  GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToBlon = UserOptions.CfgLvdsPowerOnSeqVaryBlToBlon;
+  GnbEnvConfigPtr->LvdsPowerOnSeqBlonToVaryBl = UserOptions.CfgLvdsPowerOnSeqBlonToVaryBl;
+  GnbEnvConfigPtr->LvdsMaxPixelClockFreq = UserOptions.CfgLvdsMaxPixelClockFreq;
+  GnbEnvConfigPtr->LcdBitDepthControlValue = UserOptions.CfgLcdBitDepthControlValue;
+  GnbEnvConfigPtr->Lvds24bbpPanelMode = UserOptions.CfgLvds24bbpPanelMode;
+  GnbEnvConfigPtr->LvdsMiscControl.Value = 0;
+  GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value;
+  GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum;
+  GnbEnvConfigPtr->GnbRemoteDisplaySupport = UserOptions.CfgGnbRemoteDisplaySupport;
+  GnbEnvConfigPtr->LvdsMiscVoltAdjustment = UserOptions.CfgLvdsMiscVoltAdjustment;
+  GnbEnvConfigPtr->DisplayMiscControl.Value = UserOptions.CfgDisplayMiscControl.Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ * @retval                        Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
new file mode 100644
index 0000000000..0e1a7c3dc5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB late init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern  OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in,out] LateParamsPtr    Pointer to late configuration params.
+ * @retval                         Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
new file mode 100644
index 0000000000..cae5ff726f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB mid init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATMID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in,out] MidParamsPtr    Pointer to mid configuration params.
+ * @retval                        Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
new file mode 100644
index 0000000000..a0cf40b3b4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
@@ -0,0 +1,176 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB POST init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "Ids.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[];
+extern  OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[];
+extern  BUILD_OPT_CFG             UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtPostDef (
+  IN OUT   GNB_POST_CONFIGURATION  *GnbPostConfigPtr,
+  IN       AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbPostConfigPtr     Pointer to GNB POST configuration params.
+ * @param[in] PostParamsPtr        Pointer to POST configuration params.
+ */
+VOID
+GnbInitDataStructAtPostDef (
+  IN OUT   GNB_POST_CONFIGURATION  *GnbPostConfigPtr,
+  IN       AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  GnbPostConfigPtr->IgpuEnableDisablePolicy = UserOptions.CfgIgpuEnableDisablePolicy;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr Pointer to post configuration parameters
+ * @retval                      Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  AGESA_STATUS          Status;
+  Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post after DRAM init
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr Pointer to post configuration parameters
+ * @retval                      Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  AGESA_STATUS          Status;
+  Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
new file mode 100644
index 0000000000..6949cb4162
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB reset init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
new file mode 100644
index 0000000000..01bb2cef6a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB late init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATS3SAVE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern  OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS  *AmdS3SaveParams
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at S3 save
+ *
+ *
+ *
+ * @param[in,out] AmdS3SaveParams    Pointer to AMD_S3SAVE_PARAMS.
+ * @retval                         Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS  *AmdS3SaveParams
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbS3SaveFeatureTable[0], &AmdS3SaveParams->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h
new file mode 100644
index 0000000000..a212096f40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBTIMERLIB_H_
+#define _GNBTIMERLIB_H_
+
+VOID
+GnbLibStallS3Save (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+VOID
+GnbLibStall (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+UINT32
+GnbLibTimeStamp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
new file mode 100644
index 0000000000..c1f302376f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
@@ -0,0 +1,184 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various Timer services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbLib.h"
+#include  "GnbTimerLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_LIBRARY_GNBTIMERLIBWRAP0_GNBTIMERLIBWRAP0_FILECODE
+
+
+VOID
+GnbLibStallS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Stall and save to script table
+ *
+ *
+ *
+ * @param[in] Microsecond     Stall time
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibStallS3Save (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, GnbLibStallS3Script_ID, sizeof (Microsecond), &Microsecond);
+  GnbLibStall (Microsecond, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Stall
+ *
+ *
+ *
+ * @param[in] Microsecond     Stall time
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibStall (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 TimeStampStart;
+  UINT32 TimeStampDelta;
+  UINT32 TimeStampCurrent;
+
+  TimeStampStart = GnbLibTimeStamp (StdHeader);
+  do {
+    TimeStampCurrent = GnbLibTimeStamp (StdHeader);
+    TimeStampDelta = ((TimeStampCurrent > TimeStampStart) ? (TimeStampCurrent - TimeStampStart) : (0xffffffffull - TimeStampStart + TimeStampCurrent));
+  } while (TimeStampDelta < Microsecond);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Stall S3 script
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        pointer to UINT32 number of us
+ */
+VOID
+GnbLibStallS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  )
+{
+  GnbLibStall (* ((UINT32*) Context), StdHeader);
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Time stamp in us
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a bridge
+ * @retval    FALSE           Device is not a bridge
+ */
+
+UINT32
+GnbLibTimeStamp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32  TimeStamp;
+  GnbLibPciIndirectRead (
+    MAKE_SBDFO (0, 0, 0, 0, 0xE0),
+    0x13080F0,
+    AccessWidth32,
+    &TimeStamp,
+    StdHeader
+    );
+  return TimeStamp;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h
new file mode 100644
index 0000000000..82842b5d48
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBCOMMONLIB_H_
+#define _GNBCOMMONLIB_H_
+
+#include "GnbLib.h"
+#include "GnbLibCpuAcc.h"
+#include "GnbLibHeap.h"
+#include "GnbLibIoAcc.h"
+#include "GnbLibMemAcc.h"
+#include "GnbLibPci.h"
+#include "GnbLibPciAcc.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
new file mode 100644
index 0000000000..e79dfb7a60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -0,0 +1,548 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuServices.h"
+#include  "Gnb.h"
+#include  "GnbLib.h"
+#include  "GnbLibIoAcc.h"
+#include  "GnbLibPciAcc.h"
+#include  "GnbLibMemAcc.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_SERVICE  *ServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read GNB indirect registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width           Width
+ * @param[out] Value           Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectRead (
+  IN       UINT32       Address,
+  IN       UINT32       IndirectAddress,
+  IN       ACCESS_WIDTH Width,
+     OUT   VOID         *Value,
+  IN       VOID         *Config
+  )
+{
+  UINT32  IndexOffset;
+  IndexOffset = LibAmdAccessWidth (Width);
+  GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
+  GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read GNB indirect registers field
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] FieldOffset     Field offset
+ * @param[in] FieldWidth      Field width
+ * @param[out] Value          Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectReadField (
+  IN       UINT32       Address,
+  IN       UINT32       IndirectAddress,
+  IN       UINT8        FieldOffset,
+  IN       UINT8        FieldWidth,
+     OUT   UINT32       *Value,
+  IN       VOID         *Config
+  )
+{
+  UINT32  Mask;
+  GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config);
+  Mask = (1 << FieldWidth) - 1;
+  *Value = (*Value >> FieldOffset) & Mask;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GNB indirect registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width           Width
+ * @param[in] Value           Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+
+VOID
+GnbLibPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  IndexOffset;
+  IndexOffset = LibAmdAccessWidth (Width);
+  GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
+  GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GNB indirect registers field
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] FieldOffset     Field offset
+ * @param[in] FieldWidth      Field width
+ * @param[in] Value           Pointer to value
+ * @param[in] S3Save          Save for S3 (TRUE/FALSE)
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectWriteField (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT8         FieldOffset,
+  IN      UINT8         FieldWidth,
+  IN      UINT32        Value,
+  IN      BOOLEAN       S3Save,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  UINT32  Mask;
+  GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config);
+  Mask = (1 << FieldWidth) - 1;
+  Data &= (~(Mask << FieldOffset));
+  Data |= ((Value & Mask) << FieldOffset);
+  GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write GNB indirect registers field
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width           Width
+ * @param[in] Mask            And Mask
+ * @param[in] Value           Or Value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectRMW (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibPciIndirectRead (
+    Address,
+    IndirectAddress,
+    (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width,
+    &Data,
+    Config
+    );
+  Data = (Data & Mask) | Value;
+  GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCI registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address
+ * @param[in] Width           Access width
+ * @param[in] Mask            AND Mask
+ * @param[in] Value           OR Value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciRMW (
+  IN      UINT32        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibPciRead (Address, Width, &Data, Config);
+  Data = (Data & Mask) | Value;
+  GnbLibPciWrite (Address, Width, &Data, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write I/O registers
+ *
+ *
+ *
+ * @param[in] Address         I/O Port
+ * @param[in] Width           Access width
+ * @param[in] Mask            AND Mask
+ * @param[in] Value           OR Mask
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibIoRMW (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibIoRead (Address, Width, &Data, Config);
+  Data = (Data & Mask) | Value;
+  GnbLibIoWrite (Address, Width, &Data, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Indirect IO block read
+ *
+ *
+ *
+ * @param[in] IndexPort       Index Port
+ * @param[in] DataPort        Data Port
+ * @param[in] Width           Access width
+ * @param[in] IndexAddress    Index Address
+ * @param[in] Count           Count
+ * @param[in] Buffer          Buffer
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibIndirectIoBlockRead (
+  IN      UINT16        IndexPort,
+  IN      UINT16        DataPort,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        IndexAddress,
+  IN      UINT32        Count,
+  IN      VOID          *Buffer,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Index;
+
+  for (Index = IndexAddress; Index < (IndexAddress + Count); Index++) {
+    GnbLibIoWrite (IndexPort, Width, &Index, Config);
+    GnbLibIoRead (DataPort, Width,  Buffer, Config);
+    Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get IOAPIC ID
+ *
+ *
+ *
+ * @param[in] IoApicBaseAddress   IO APIC base address
+ * @param[in] Config              Pointer to standard header
+ */
+UINT8
+GnbLiGetIoapicId (
+  IN      UINT64        IoApicBaseAddress,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Value;
+  Value = 0x0;
+  GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config);
+  GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config);
+  return (UINT8) (Value >> 24);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write MMIO registers
+ *
+ *
+ *
+ * @param[in] Address         Physical address
+ * @param[in] Width           Access width
+ * @param[in] Mask            AND Mask
+ * @param[in] Value           OR Value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibMemRMW (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibMemRead (Address, Width, &Data, Config);
+  Data = (Data & Mask) | Value;
+  GnbLibMemWrite (Address, Width, &Data, Config);
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Claculate power of number
+ *
+ *
+ *
+ * @param[in]   Value         Number
+ * @param[in]   Power         Power
+ */
+
+UINT32
+GnbLibPowerOf (
+  IN      UINT32  Value,
+  IN      UINT32  Power
+  )
+{
+  UINT32  Result;
+  if (Power == 0) {
+    return 1;
+  }
+  Result = Value;
+  while ((--Power) > 0) {
+    Result *= Value;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Search buffer for pattern
+ *
+ *
+ * @param[in]  Buf1           Pointer to source buffer which will be subject of search
+ * @param[in]  Buf1Length     Length of the source buffer
+ * @param[in]  Buf2           Pointer to pattern buffer
+ * @param[in]  Buf2Length     Length of the pattern buffer
+ * @retval     Pointer on first accurance of Buf2 in Buf1 or NULL
+ */
+
+VOID*
+GnbLibFind (
+  IN      UINT8               *Buf1,
+  IN      UINTN               Buf1Length,
+  IN      UINT8               *Buf2,
+  IN      UINTN               Buf2Length
+  )
+{
+  UINT8 *CurrentBuf1Ptr;
+  CurrentBuf1Ptr = Buf1;
+  while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
+    UINT8 *SourceBufPtr;
+    UINT8 *PatternBufPtr;
+    UINTN PatternBufLength;
+    SourceBufPtr = CurrentBuf1Ptr;
+    PatternBufPtr = Buf2;
+    PatternBufLength = Buf2Length;
+    while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
+    if (PatternBufLength == 0) {
+      return CurrentBuf1Ptr;
+    }
+    CurrentBuf1Ptr++;
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump buffer to HDTOUT
+ *
+ *
+ * @param[in]     Buffer          Buffer pointer
+ * @param[in]     Count           Count of data elements
+ * @param[in]     DataWidth       DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD
+ * @param[in]     LineWidth       Number of data item per line
+ */
+VOID
+GnbLibDebugDumpBuffer (
+  IN       VOID             *Buffer,
+  IN       UINT32           Count,
+  IN       UINT8            DataWidth,
+  IN       UINT8            LineWidth
+  )
+{
+  UINT32  Index;
+  UINT32  DataItemCount;
+  ASSERT (LineWidth != 0);
+  ASSERT (DataWidth >= 1 && DataWidth <= 4);
+  DataItemCount = 0;
+  for (Index = 0; Index < Count; ) {
+    switch (DataWidth) {
+    case 1:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index));
+      Index += 1;
+      break;
+    case 2:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index));
+      Index += 2;
+      break;
+    case 3:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index));
+      Index += 4;
+      break;
+    case 4:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4));
+      Index += 8;
+      break;
+    default:
+      IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n");
+      return;
+    }
+    if (++DataItemCount >= LineWidth) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "\n");
+      DataItemCount = 0;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump buffer to HDTOUT
+ *
+ *
+ * @param[in]     ServiceId       Service ID
+ * @param[in]     SocketId        Socket ID
+ * @param[in]     ServiceProtocol Service protocol
+ * @param[in]     StdHeader       Standard Configuration Header
+ */
+AGESA_STATUS
+GnbLibLocateService (
+  IN       GNB_SERVICE_ID       ServiceId,
+  IN       UINT8                SocketId,
+  IN       VOID                 **ServiceProtocol,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  GNB_SERVICE     *SeviceEntry;
+  CPU_LOGICAL_ID  LogicalId;
+  SeviceEntry = ServiceTable;
+  GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader);
+  while (SeviceEntry != NULL) {
+    if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) {
+      *ServiceProtocol = SeviceEntry->ServiceProtocol;
+      return AGESA_SUCCESS;
+    }
+    SeviceEntry = SeviceEntry->NextService;
+  }
+  return AGESA_UNSUPPORTED;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h
new file mode 100644
index 0000000000..ffbeba60af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h
@@ -0,0 +1,193 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBLIB_H_
+#define _GNBLIB_H_
+
+#define IOC_WRITE_ENABLE 0x80
+
+VOID
+GnbLibPciIndirectReadField (
+  IN       UINT32       Address,
+  IN       UINT32       IndirectAddress,
+  IN       UINT8        FieldOffset,
+  IN       UINT8        FieldWidth,
+     OUT   UINT32       *Value,
+  IN       VOID         *Config
+  );
+
+VOID
+GnbLibPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibPciIndirectRead (
+  IN       UINT32        Address,
+  IN       UINT32        IndirectAddress,
+  IN       ACCESS_WIDTH  Width,
+     OUT   VOID          *Value,
+  IN       VOID          *Config
+  );
+
+VOID
+GnbLibPciIndirectRMW (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibPciIndirectWriteField (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT8         FieldOffset,
+  IN      UINT8         FieldWidth,
+  IN      UINT32        Value,
+  IN      BOOLEAN       S3Save,
+  IN      VOID          *Config
+  );
+
+
+VOID
+GnbLibPciRMW (
+  IN      UINT32        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibIoRMW (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+
+UINT32
+GnbLibPowerOf (
+  IN      UINT32            Value,
+  IN      UINT32            Power
+  );
+
+VOID*
+GnbLibFind (
+  IN      UINT8             *Buf1,
+  IN      UINTN             Buf1Length,
+  IN      UINT8             *Buf2,
+  IN      UINTN             Buf2Length
+  );
+
+VOID
+GnbLibIndirectIoBlockRead (
+  IN      UINT16            IndexPort,
+  IN      UINT16            DataPort,
+  IN      ACCESS_WIDTH      Width,
+  IN      UINT32            IndexAddress,
+  IN      UINT32            Count,
+  IN      VOID              *Buffer,
+  IN      VOID              *Config
+  );
+
+UINT8
+GnbLiGetIoapicId (
+  IN      UINT64            IoApicBaseAddress,
+  IN      VOID              *Config
+  );
+
+VOID
+GnbLibDebugDumpBuffer (
+  IN       VOID             *Buffer,
+  IN       UINT32           Count,
+  IN       UINT8            DataWidth,
+  IN       UINT8            LineWidth
+  );
+
+AGESA_STATUS
+GnbLibLocateService (
+  IN       GNB_SERVICE_ID       ServiceId,
+  IN       UINT8                SocketId,
+  IN       VOID                 **ServiceProtocol,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
new file mode 100644
index 0000000000..39259f7e4d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -0,0 +1,157 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access various CPU registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "GnbLibCpuAcc.h"
+#include  "GnbLibPciAcc.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read CPU (DCT) indirect registers
+ *
+ *
+ *
+ * @param[in]  Address         PCI address of DCT register
+ * @param[in]  IndirectAddress Offset of DCT register
+ * @param[out] Value           Pointer to value
+ * @param[in]  Config          Pointer to standard header
+ */
+VOID
+GnbLibCpuPciIndirectRead (
+  IN       UINT32        Address,
+  IN       UINT32        IndirectAddress,
+     OUT   UINT32        *Value,
+  IN       VOID          *Config
+  )
+{
+  UINT32  OffsetRegisterValue;
+  GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config);
+  do {
+    GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
+  } while ((OffsetRegisterValue & BIT31) == 0);
+  GnbLibPciRead (Address + 4, AccessWidth32, Value, Config);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write CPU (DCT) indirect registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address of DCT register
+ * @param[in] IndirectAddress Offset of DCT register
+ * @param[in] Value           Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibCpuPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT32        *Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  OffsetRegisterValue;
+  OffsetRegisterValue = IndirectAddress | BIT30;
+  GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config);
+  GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config);
+  do {
+    GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
+  } while ((OffsetRegisterValue & BIT31) == 0);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h
new file mode 100644
index 0000000000..4eea7b8be1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access various CPU registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _CPUACCLIB_H_
+#define _CPUACCLIB_H_
+
+VOID
+GnbLibCpuPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT32        *Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibCpuPciIndirectRead (
+  IN       UINT32        Address,
+  IN       UINT32        IndirectAddress,
+     OUT   UINT32        *Value,
+  IN       VOID          *Config
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
new file mode 100644
index 0000000000..aa243de9ef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access heap.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "GnbLibPciAcc.h"
+#include  "GnbLibHeap.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      Length            Buffer length
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer allocation fail
+ *
+ */
+
+VOID *
+GnbAllocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = (UINT32) Length;
+  AllocHeapParams.BufferHandle = Handle;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return NULL;
+  }
+  return AllocHeapParams.BufferPtr;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap and clear it
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      Length            Buffer length
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer allocation fail
+ *
+ */
+
+VOID *
+GnbAllocateHeapBufferAndClear (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  VOID  *Buffer;
+  Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader);
+  if (Buffer != NULL) {
+    LibAmdMemFill (Buffer, 0x00, Length, StdHeader);
+  }
+  return Buffer;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locates a previously allocated buffer on the heap.
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer handle not found
+ *
+ */
+
+VOID *
+GnbLocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  LOCATE_HEAP_PTR       LocHeapParams;
+  LocHeapParams.BufferHandle = Handle;
+  Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return NULL;
+  }
+  return LocHeapParams.BufferPtr;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h
new file mode 100644
index 0000000000..61a618a900
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h
@@ -0,0 +1,96 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access heap.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBHEAPLIB_H_
+#define _GNBHEAPLIB_H_
+
+VOID *
+GnbAllocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+VOID *
+GnbLocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+VOID *
+GnbAllocateHeapBufferAndClear (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
new file mode 100644
index 0000000000..b5341f87bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -0,0 +1,149 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+* Service procedure to access I/O registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "amdlib.h"
+#include "GnbLibIoAcc.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+
+/*---------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write I/O Port
+ *
+ *
+ *
+ * @param[in] Address         Physical Address
+ * @param[in] Width           Access width
+ * @param[in] Value           Pointer to value
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibIoWrite (
+  IN       UINT16      Address,
+  IN       ACCESS_WIDTH Width,
+  IN       VOID         *Value,
+  IN       VOID         *StdHeader
+  )
+{
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value);
+  }
+  LibAmdIoWrite (Width, Address, Value, StdHeader);
+}
+/**
+ * Read IO port
+ *
+ *
+ *
+ * @param[in]   Address         Physical Address
+ * @param[in]   Width           Access width
+ * @param[out]  Value           Pointer to value
+ * @param[in]   StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibIoRead (
+  IN       UINT16       Address,
+  IN       ACCESS_WIDTH Width,
+     OUT   VOID         *Value,
+  IN       VOID         *StdHeader
+  )
+{
+  LibAmdIoRead (Width, Address, Value, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h
new file mode 100644
index 0000000000..0066fad004
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h
@@ -0,0 +1,93 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access I/O registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _IOACCLIB_H_
+#define _IOACCLIB_H_
+
+
+VOID
+GnbLibIoWrite (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+VOID
+GnbLibIoRead (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  OUT     VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
new file mode 100644
index 0000000000..affdb10218
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access MMIO registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "amdlib.h"
+#include  "GnbLibMemAcc.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write Memory/MMIO registers
+ *
+ *
+ *
+ * @param[in] Address         Physical Address
+ * @param[in] Width           Access width
+ * @param[in] Value           Pointer to value
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibMemWrite (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *StdHeader
+  )
+{
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value);
+  }
+  LibAmdMemWrite (Width, Address, Value, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read Memory/MMIO registers
+ *
+ *
+ *
+ * @param[in]   Address         Physical Address
+ * @param[in]   Width           Access width
+ * @param[out]  Value           Pointer to value
+ * @param[in]   StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibMemRead (
+  IN       UINT64       Address,
+  IN       ACCESS_WIDTH Width,
+     OUT   VOID         *Value,
+  IN       VOID         *StdHeader
+  )
+{
+  LibAmdMemRead (Width, Address, Value, StdHeader);
+}
+
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h
new file mode 100644
index 0000000000..e0179d2669
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access MMIO registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _MEMACCLIB_H_
+#define _MEMACCLIB_H_
+
+VOID
+GnbLibMemWrite (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+VOID
+GnbLibMemRead (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  OUT     VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+VOID
+GnbLibMemRMW (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
new file mode 100644
index 0000000000..1353342a54
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
@@ -0,0 +1,430 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbLibPciAcc.h"
+#include  "GnbLibPci.h"
+#include  "GnbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device present
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is present
+ * @retval    FALSE           Device is not present
+ */
+
+BOOLEAN
+GnbLibPciIsDevicePresent (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32  DeviceId;
+  GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader);
+  if (DeviceId == 0xffffffff) {
+    return FALSE;
+  } else {
+    return TRUE;
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device is bridge
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a bridge
+ * @retval    FALSE           Device is not a bridge
+ */
+
+BOOLEAN
+GnbLibPciIsBridgeDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   Header;
+  GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader);
+  if ((Header & 0x7f) == 1) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device is multifunction
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a multifunction device.
+ * @retval    FALSE           Device is a single function device.
+ *
+ */
+BOOLEAN
+GnbLibPciIsMultiFunctionDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   Header;
+  GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader);
+  if ((Header & 0x80) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device is PCIe device
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a PCIe device
+ * @retval    FALSE           Device is not a PCIe device
+ *
+ */
+
+BOOLEAN
+GnbLibPciIsPcieDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Find PCI capability pointer
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] CapabilityId    PCI capability ID
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Register address of capability pointer
+ *
+ */
+
+UINT8
+GnbLibFindPciCapability (
+  IN      UINT32              Address,
+  IN      UINT8               CapabilityId,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8     CapabilityPtr;
+  UINT8     CurrentCapabilityId;
+  CapabilityPtr = 0x34;
+  if (!GnbLibPciIsDevicePresent (Address, StdHeader)) {
+    return  0;
+  }
+  while (CapabilityPtr != 0) {
+    GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader);
+    if (CapabilityPtr != 0) {
+      GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader);
+      if (CurrentCapabilityId == CapabilityId) {
+        break;
+      }
+      CapabilityPtr++;
+    }
+  }
+  return  CapabilityPtr;
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Find PCIe extended capability pointer
+ *
+ *
+ *
+ * @param[in] Address               PCI address (as described in PCI_ADDR)
+ * @param[in] ExtendedCapabilityId  Extended PCIe capability ID
+ * @param[in] StdHeader             Standard configuration header
+ * @retval                          Register address of extended capability pointer
+ *
+ */
+
+#if 0 /* Not used */
+UINT16
+GnbLibFindPcieExtendedCapability (
+  IN      UINT32              Address,
+  IN      UINT16              ExtendedCapabilityId,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16  CapabilityPtr;
+  UINT32  ExtendedCapabilityIdBlock;
+  if (GnbLibPciIsPcieDevice (Address, StdHeader)) {
+    GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
+    if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) {
+      do {
+        CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff);
+        if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) {
+          return  CapabilityPtr;
+        }
+        GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
+      } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) !=  0);
+    }
+  }
+  return  0;
+}
+#endif
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Scan range of device on PCI bus.
+ *
+ *
+ *
+ * @param[in] Start           Start address to start scan from
+ * @param[in] End             End address of scan
+ * @param[in] ScanData        Supporting data
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+GnbLibPciScan (
+  IN      PCI_ADDR            Start,
+  IN      PCI_ADDR            End,
+  IN      GNB_PCI_SCAN_DATA   *ScanData
+  )
+{
+  UINTN       Bus;
+  UINTN       Device;
+  UINTN       LastDevice;
+  UINTN       Function;
+  UINTN       LastFunction;
+  PCI_ADDR    PciDevice;
+  SCAN_STATUS Status;
+
+  for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) {
+    Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00;
+    LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F;
+    for ( ; Device <= LastDevice; Device++) {
+      if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) {
+        Function = Start.Address.Function;
+      } else {
+        Function = 0x0;
+      }
+      PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0);
+      if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) {
+        continue;
+      }
+      if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) {
+        if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) {
+          LastFunction = Start.Address.Function;
+        } else {
+          LastFunction = 0x7;
+        }
+      } else {
+        LastFunction = 0x0;
+      }
+      for ( ; Function <= LastFunction; Function++) {
+        PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0);
+        if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) {
+          Status = ScanData->GnbScanCallback (PciDevice, ScanData);
+          if ((Status & SCAN_SKIP_FUNCTIONS) != 0) {
+            Function = LastFunction + 1;
+          }
+          if ((Status & SCAN_SKIP_DEVICES) != 0) {
+            Device = LastDevice + 1;
+          }
+          if ((Status & SCAN_SKIP_BUSES) != 0) {
+            Bus = End.Address.Bus + 1;
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Scan all subordinate buses
+ *
+ *
+ * @param[in]   Bridge            PCI bridge address
+ * @param[in,out] ScanData        Scan configuration data
+ *
+ */
+VOID
+GnbLibPciScanSecondaryBus (
+  IN       PCI_ADDR             Bridge,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  PCI_ADDR  StartRange;
+  PCI_ADDR  EndRange;
+  UINT8     SecondaryBus;
+  GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader);
+  if (SecondaryBus != 0) {
+    StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
+    EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0);
+    GnbLibPciScan (StartRange, EndRange, ScanData);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCIe device type
+ *
+ *
+ *
+ * @param[in] Device      PCI address of device.
+ * @param[in] StdHeader  Northbridge configuration structure pointer.
+ *
+ * @retval    PCIE_DEVICE_TYPE
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+PCIE_DEVICE_TYPE
+GnbLibGetPcieDeviceType (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8       PcieCapPtr;
+  UINT8       Value;
+
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader);
+    return Value >> 4;
+  }
+  return PcieNotPcieDevice;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save config space area
+ *
+ *
+ *
+ * @param[in] Address                 PCI address of device.
+ * @param[in] StartRegisterAddress    Start register address.
+ * @param[in] EndRegisterAddress      End register address.
+ * @param[in] Width                   Acess width.
+ * @param[in] StdHeader               Standard header.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+VOID
+GnbLibS3SaveConfigSpace (
+  IN      UINT32              Address,
+  IN      UINT16              StartRegisterAddress,
+  IN      UINT16              EndRegisterAddress,
+  IN      ACCESS_WIDTH        Width,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16    Index;
+  UINT16    Delta;
+  UINT16    Length;
+  Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress);
+  Delta = LibAmdAccessWidth (Width);
+  for (Index = 0; Index <= Length; Index = Index + Delta) {
+    GnbLibPciRMW (
+      Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)),
+      Width,
+      0xffffffff,
+      0x0,
+      StdHeader
+      );
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h
new file mode 100644
index 0000000000..a0825cfa12
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBLIBPCI_H_
+#define _GNBLIBPCI_H_
+
+#define PCIE_CAP_ID                 0x10
+#define IOMMU_CAP_ID                0x0F
+
+/// PCIe device type
+typedef enum {
+  PcieDeviceEndPoint,                       ///< Endpoint
+  PcieDeviceLegacyEndPoint,                 ///< Legacy endpoint
+  PcieDeviceRootComplex = 4,                ///< Root complex
+  PcieDeviceUpstreamPort,                   ///< Upstream port
+  PcieDeviceDownstreamPort,                 ///< Downstream Port
+  PcieDevicePcieToPcix,                     ///< PCIe to PCI/PCIx bridge
+  PcieDevicePcixToPcie,                     ///< PCI/PCIx to PCIe bridge
+  PcieNotPcieDevice = 0xff                  ///< unknown device
+} PCIE_DEVICE_TYPE;
+
+typedef  UINT32 SCAN_STATUS;
+
+#define SCAN_SKIP_FUNCTIONS         0x1
+#define SCAN_SKIP_DEVICES           0x2
+#define SCAN_SKIP_BUSES             0x4
+#define SCAN_SUCCESS                0x0
+
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA);
+
+typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+///Scan supporting data
+struct _GNB_PCI_SCAN_DATA {
+  GNB_SCAN_CALLBACK     GnbScanCallback;  ///< Callback for each found device
+  AMD_CONFIG_PARAMS     *StdHeader;       ///< Standard configuration header
+};
+
+#define   PCIE_CAP_ID               0x10
+#define   PCIE_LINK_CAP_REGISTER    0x0C
+#define   PCIE_LINK_CTRL_REGISTER   0x10
+#define   PCIE_DEVICE_CAP_REGISTER  0x04
+#define   PCIE_DEVICE_CTRL_REGISTER 0x08
+#define   PCIE_ASPM_L1_SUPPORT_CAP  BIT11
+
+#define MAX_PAYLOAD_128             0x0     ///< Max allowed payload size 128 bytes
+#define MAX_PAYLOAD_256             0x1     ///< Max allowed payload size 256 bytes
+#define MAX_PAYLOAD_512             0x2     ///< Max allowed payload size 512 bytes
+#define MAX_PAYLOAD_1024            0x3     ///< Max allowed payload size 1024 bytes
+#define MAX_PAYLOAD_2048            0x4     ///< Max allowed payload size 2048 bytes
+#define MAX_PAYLOAD_4096            0x5     ///< Max allowed payload size 4096 bytes
+#define MAX_PAYLOAD                 0x5     ///< Max allowed payload size according to spec is 101b (4096 bytes)
+
+BOOLEAN
+GnbLibPciIsDevicePresent (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+BOOLEAN
+GnbLibPciIsBridgeDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+BOOLEAN
+GnbLibPciIsMultiFunctionDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+BOOLEAN
+GnbLibPciIsPcieDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+UINT8
+GnbLibFindPciCapability (
+  IN      UINT32              Address,
+  IN      UINT8               CapabilityId,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLibPciScan (
+  IN      PCI_ADDR            Start,
+  IN      PCI_ADDR            End,
+  IN      GNB_PCI_SCAN_DATA   *ScanData
+ );
+
+VOID
+GnbLibPciScanSecondaryBus (
+  IN       PCI_ADDR             Bridge,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+PCIE_DEVICE_TYPE
+GnbLibGetPcieDeviceType (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLibS3SaveConfigSpace (
+  IN      UINT32              Address,
+  IN      UINT16              StartRegisterAddress,
+  IN      UINT16              EndRegisterAddress,
+  IN      ACCESS_WIDTH        Width,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
new file mode 100644
index 0000000000..ccb2078120
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
@@ -0,0 +1,183 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "amdlib.h"
+#include  "GnbLibPciAcc.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCI registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as presented in PCI_ADDR.AddressValue)
+ * @param[in] Width           Access width
+ * @param[in] Value           Pointer to value
+ * @param[in] StdHeader       Pointer to standard header
+ */
+VOID
+GnbLibPciWrite (
+  IN      UINT32              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      VOID                *Value,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  PciAddress.AddressValue = Address;
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value);
+  }
+  LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCI registers
+ *
+ *
+ *
+ * @param[in]   Address         PCI address (as presented in PCI_ADDR.AddressValue)
+ * @param[in]   Width           Access width
+ * @param[out]  Value           Pointer to value
+ * @param[in]   StdHeader       Pointer to standard header
+ */
+
+VOID
+GnbLibPciRead (
+  IN       UINT32             Address,
+  IN       ACCESS_WIDTH       Width,
+     OUT   VOID               *Value,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  PciAddress.AddressValue = Address;
+  LibAmdPciRead (Width, PciAddress, Value, StdHeader);
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll PCI reg
+ *
+ *
+ *
+ * @param[in] Address       PCI address (as presented in PCI_ADDR.AddressValue)
+ * @param[in] Width         Access width
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      AND mask
+ * @param[in] StdHeader     Standard configuration header
+ */
+
+VOID
+GnbLibPciPoll (
+  IN      UINT32             Address,
+  IN      ACCESS_WIDTH       Width,
+  IN      VOID               *Data,
+  IN      VOID               *DataMask,
+  IN      AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  PciAddress.AddressValue = Address;
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff);
+  }
+  LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h
new file mode 100644
index 0000000000..a921bf13bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBLIBPCIACC_H_
+#define _GNBLIBPCIACC_H_
+
+VOID
+GnbLibPciWrite (
+  IN      UINT32              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      VOID                *Value,
+  IN      AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+GnbLibPciRead (
+  IN       UINT32             Address,
+  IN       ACCESS_WIDTH       Width,
+     OUT   VOID               *Value,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+GnbLibPciPoll (
+  IN      UINT32             Address,
+  IN      ACCESS_WIDTH       Width,
+  IN      VOID               *Data,
+  IN      VOID               *DataMask,
+  IN      AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
new file mode 100644
index 0000000000..d6936d4f24
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -0,0 +1,542 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific function translation
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   No more configuration available for given engine type
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+AGESA_STATUS
+PcieFmConfigureEnginesLaneAllocation (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId);
+  }
+  return  AGESA_ERROR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration value
+ *
+ *
+ *
+ * @param[in]  Wrapper                Pointer to internal configuration data area
+ * @param[in]  CoreId                 Core ID
+ * @param[in]  ConfigurationSignature Configuration signature
+ * @param[out] ConfigurationValue     Configuration value (for core configuration)
+ * @retval     AGESA_SUCCESS          Configuration successfully applied
+ * @retval     AGESA_ERROR            Core configuration value can not be determined
+ */
+AGESA_STATUS
+PcieFmGetCoreConfigurationValue (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_INIT_SERVICES    *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature,  ConfigurationValue);
+  }
+  return  AGESA_ERROR;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if engine can be remapped to Device/function number requested by user
+ * defined engine descriptor
+ *
+ *   Function only called if requested device/function does not much native device/function
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieFmCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
+  }
+  return FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration string
+ *
+ *   Debug function for logging configuration
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @param[in] ConfigurationValue   Configuration value
+ * @retval                         Configuration string
+ */
+
+CONST CHAR8*
+PcieFmDebugGetCoreConfigurationString (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_DEBUG_SERVICES   *PcieDebugService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId,  (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue);
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get wrapper name
+ *
+ *  Debug function for logging wrapper name
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @retval                         Wrapper Name string
+ */
+
+CONST CHAR8*
+PcieFmDebugGetWrapperNameString (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_DEBUG_SERVICES   *PcieDebugService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId,  (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper);
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get register address name
+ *
+ *  Debug function for logging register trace
+ *
+ * @param[in] Silicon              Silicon config descriptor
+ * @param[in] AddressFrame         Address Frame
+ * @retval                         Register address name
+ */
+CONST CHAR8*
+PcieFmDebugGetHostRegAddressSpaceString (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_DEBUG_SERVICES   *PcieDebugService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId,  (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame);
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if the lane can be muxed by link width requested by user
+ * defined engine descriptor
+ *
+ *    Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
+ *    Check Engine StartCoreLane could be aligned by user requested link width x2.
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Lane can be muxed
+ * @retval     FALSE               Lane can NOT be muxed
+ */
+
+BOOLEAN
+PcieFmCheckPortPcieLaneCanBeMuxed (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId,  (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine);
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Map engine to specific PCI device address
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @retval     AGESA_ERROR         Fail to map PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address
+ */
+
+AGESA_STATUS
+PcieFmMapPortPciAddress (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmMapPortPciAddress (Engine);
+  }
+  return  AGESA_ERROR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get total number of silicons/wrappers/engines for this complex
+ *
+ *
+ *
+ * @param[in]  SocketId              Socket ID.
+ * @param[out] Length                Length of configuration info block
+ * @param[out] StdHeader             Standard Configuration Header
+ * @retval     AGESA_SUCCESS         Configuration data length is correct
+ */
+AGESA_STATUS
+PcieFmGetComplexDataLength (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId,  (VOID **)&PcieConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader);
+  }
+  return Status;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build configuration
+ *
+ *
+ * @param[in]  SocketId         Socket ID.
+ * @param[out] Buffer           Pointer to buffer to build internal complex data structure
+ * @param[out] StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieFmBuildComplexConfiguration (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId,  (VOID **)&PcieConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max link speed capability supported by this port
+ *
+ *
+ *
+ * @param[in]  Flags              See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
+ * @param[in]  Engine             Pointer to engine config descriptor
+ * @retval     PcieGen1/PcieGen2  Max supported link gen capability
+ */
+PCIE_LINK_SPEED_CAP
+PcieFmGetLinkSpeedCap (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  PCIe_COMPLEX_CONFIG     *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_INIT_SERVICES  *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine);
+  }
+  return PcieGen1;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Get native PHY lane bitmap
+ *
+ *
+ * @param[in]  PhyLaneBitmap  Package PHY lane bitmap
+ * @param[in]  Engine         Standard configuration header.
+ * @retval     Native PHY lane bitmap
+ */
+UINT32
+PcieFmGetNativePhyLaneBitmap (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  PCIe_COMPLEX_CONFIG     *Complex;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  PCIe_FAM_INIT_SERVICES  *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine);
+  }
+  return 0x0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieFmSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP            LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  )
+{
+  AGESA_STATUS            Status;
+  PCIe_COMPLEX_CONFIG     *Complex;
+  PCIe_FAM_INIT_SERVICES  *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SB port info
+ *
+ *
+ * @param[out] SocketId         Socket ID
+ * @param[out] SbPort           Pointer to SB configuration descriptor
+ * @param[in]  StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    SB configuration determined successfully
+ */
+AGESA_STATUS
+PcieFmGetSbConfigInfo (
+  IN       UINT8                        SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR         *SbPort,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader);
+  }
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
new file mode 100644
index 0000000000..2ac05a2c60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
@@ -0,0 +1,157 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific function translation
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU unit present and enabled
+ *
+ *
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+BOOLEAN
+GnbFmCheckIommuPresent (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_FAM_IOMMU_SERVICES    *GnbIommuConfigService;
+  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader);
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbFmCreateIvrsEntry (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_FAM_IOMMU_SERVICES    *GnbIommuConfigService;
+  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader);
+  }
+  return Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
new file mode 100644
index 0000000000..e142ac7d0d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxConfigLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxConfigEnvInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update GFX config info at ENV
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxConfigEnvInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  AMD_ENV_PARAMS        *EnvParamsPtr;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
+    Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex;
+    Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum;
+    Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate;
+    Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe;
+    Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl;
+    Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon;
+    Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe;
+    Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay;
+    Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon;
+    Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl;
+    Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq;
+    Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue;
+    Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode;
+    Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value;
+    Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum;
+    Gfx->GnbRemoteDisplaySupport = EnvParamsPtr->GnbEnvConfiguration.GnbRemoteDisplaySupport;
+    Gfx->gfxplmcfg0  = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscVoltAdjustment;
+    Gfx->DisplayMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.DisplayMiscControl.Value;
+    GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader);
+  }
+  GNB_DEBUG_CODE (
+    GfxConfigDebugDump (Gfx);
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
new file mode 100644
index 0000000000..cdf477166c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -0,0 +1,259 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GfxConfigLib.h"
+#include  "GnbCommonLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable GMM Access
+ *
+ *
+ *
+ * @param[in,out]   Gfx            Pointer to GFX configuration
+ * @retval          AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxEnableGmmAccess (
+  IN OUT   GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32      Value;
+
+  if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+
+  // Check if base address for GMM allocated
+  GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx));
+  if (Gfx->GmmBase == 0) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+  // Check if base address for FB allocated
+  GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
+  if ((Value & 0xfffffff0) == 0) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+  //Push CPU MMIO pci config to S3 script
+  GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+  // Turn on memory decoding on APC to enable access to GMM register space
+  if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
+    GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
+    //Push APC pci config to S3 script
+    GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+    GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
+  }
+  // Turn on memory decoding on GFX to enable access to GMM register space
+  GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
+  //Push iGPU pci config to S3 script
+  GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+  GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get UMA info
+ *
+ * UMA info stored on heap by memory module
+ *
+ * @param[out] UmaInfo      Pointer to UMA info structure
+ * @param[in]  StdHeader    Standard configuration header
+ */
+
+VOID
+GfxGetUmaInfo (
+     OUT   UMA_INFO          *UmaInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UMA_INFO *MemUmaInfo;
+
+  MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader);
+  if (MemUmaInfo == NULL) {
+    LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader);
+    UmaInfo->UmaMode = UMA_NONE;
+  } else {
+    LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader);
+    if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) {
+      UmaInfo->UmaMode = UMA_NONE;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate UMA configuration data
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @param[in,out] Gfx           Pointer to GFX configuration
+ * @retval        AGESA_STATUS  Data located
+ * @retval        AGESA_FATA    Data not found
+ */
+
+AGESA_STATUS
+GfxLocateConfigData (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   GFX_PLATFORM_CONFIG   **Gfx
+  )
+{
+  *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader);
+  if (*Gfx == NULL) {
+    IDS_ERROR_TRAP;
+    return  AGESA_FATAL;
+  }
+  (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Debug dump
+ *
+ *
+ *
+ * @param[in]     Gfx           Pointer to GFX configuration
+ */
+
+VOID
+GfxConfigDebugDump (
+  IN       GFX_PLATFORM_CONFIG      *Gfx
+  )
+{
+  IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n");
+  IDS_HDT_CONSOLE (GFX_MISC, "  HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled");
+  IDS_HDT_CONSOLE (GFX_MISC, "  DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate);
+  IDS_HDT_CONSOLE (GFX_MISC, "  LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl);
+  IDS_HDT_CONSOLE (GFX_MISC, "  AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled");
+  IDS_HDT_CONSOLE (GFX_MISC, "  GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled");
+  IDS_HDT_CONSOLE (GFX_MISC, "  GmcPowerGating - %s\n",
+    (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : (
+    (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : (
+    (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown"))
+  );
+  IDS_HDT_CONSOLE (GFX_MISC, "  UmaSteering - %s\n",
+    (Gfx->UmaSteering == excel993 ) ? "excel993" : (
+    (Gfx->UmaSteering == excel992 ) ? "excel992" : "Unknown")
+    );
+  IDS_HDT_CONSOLE (GFX_MISC, "  iGpuVgaMode - %s\n",
+    (Gfx->iGpuVgaMode == iGpuVgaAdapter) ? "VGA" : (
+    (Gfx->iGpuVgaMode == iGpuVgaNonAdapter) ? "Non VGA" : "Unknown")
+    );
+  IDS_HDT_CONSOLE (GFX_MISC, "  UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA");
+  if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase);
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize);
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes);
+  }
+  IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n");
+
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h
new file mode 100644
index 0000000000..0c0aef794c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXCONFIGLIB_H_
+#define _GFXCONFIGLIB_H_
+
+VOID
+GfxConfigDebugDump (
+  IN       GFX_PLATFORM_CONFIG      *Gfx
+  );
+
+VOID
+GfxGetUmaInfo (
+     OUT   UMA_INFO          *UmaInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GfxLocateConfigData (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   GFX_PLATFORM_CONFIG   **Gfx
+  );
+
+AGESA_STATUS
+GfxEnableGmmAccess (
+  IN OUT  GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
new file mode 100644
index 0000000000..f2323aa754
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
@@ -0,0 +1,140 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxConfigLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxConfigMidInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update GFX config info at ENV
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxConfigMidInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  AMD_MID_PARAMS        *MidParamsPtr;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
+    Gfx->iGpuVgaMode = MidParamsPtr->GnbMidConfiguration.iGpuVgaMode;
+  }
+  GNB_DEBUG_CODE (
+    GfxConfigDebugDump (Gfx);
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
new file mode 100644
index 0000000000..04efa71a53
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -0,0 +1,163 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GfxConfigLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxConfigPostInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate UMA configuration data
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxConfigPostInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  GFX_PLATFORM_CONFIG       *Gfx;
+  AMD_POST_PARAMS           *PostParamsPtr;
+  AGESA_STATUS              Status;
+  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
+  Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
+  ASSERT (Gfx != NULL);
+  if (Gfx != NULL) {
+    LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
+    if (GnbBuildOptions.IgfxModeAsPcieEp) {
+      Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
+      Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
+    } else {
+      Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
+      Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
+    }
+    Gfx->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+    Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
+    Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
+    Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
+    Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
+    Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
+    Gfx->GmcClockGating = GnbBuildOptions.CfgGmcClockGating;
+    Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGating;
+    Gfx->UmaSteering = excel992 ;
+    GNB_DEBUG_CODE (
+      GfxConfigDebugDump (Gfx);
+      );
+  } else {
+    Status = AGESA_ERROR;
+  }
+  IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h
new file mode 100644
index 0000000000..b94ae4a9f4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBGFXCONFIG_H_
+#define _GNBGFXCONFIG_H_
+
+#include "GfxConfigLib.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
new file mode 100644
index 0000000000..cc16c333a1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
@@ -0,0 +1,211 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Supporting services to collect discrete GFX card info
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include "GnbCommonLib.h"
+#include  "GfxCardInfo.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA     ScanData;
+  GFX_CARD_CARD_INFO    *GfxCardInfo;
+  PCI_ADDR              BaseBridge;
+  UINT8                 BusNumber;
+} GFX_SCAN_DATA;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+SCAN_STATUS
+GfxScanPcieDevice (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get information about all discrete GFX card in system
+ *
+ *
+ *
+ * @param[out] GfxCardInfo     Pointer to GFX card info structure
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+VOID
+GfxGetDiscreteCardInfo (
+     OUT   GFX_CARD_CARD_INFO  *GfxCardInfo,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  GFX_SCAN_DATA GfxScanData;
+  PCI_ADDR      Start;
+  PCI_ADDR      End;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n");
+  Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0);
+  GfxScanData.BusNumber = 5;
+  GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice;
+  GfxScanData.ScanData.StdHeader = StdHeader;
+  GfxScanData.GfxCardInfo = GfxCardInfo;
+  GnbLibPciScan (Start, End, &GfxScanData.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+GfxScanPcieDevice (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  UINT8   ClassCode;
+  UINT32  VendorId;
+
+  IDS_HDT_CONSOLE (GFX_MISC, "  Evaluate device [%d:%d:%d]\n",
+    Device.Address.Bus, Device.Address.Device, Device.Address.Function
+    );
+
+  if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) {
+    UINT32    SaveBusConfiguration;
+    UINT32    Value;
+
+    if (Device.Address.Bus == 0) {
+      ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device;
+    }
+    GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader);
+    Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus;
+    GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader);
+    ((GFX_SCAN_DATA *) ScanData)->BusNumber++;
+
+    GnbLibPciScanSecondaryBus (Device, ScanData);
+
+    ((GFX_SCAN_DATA *) ScanData)->BusNumber--;
+    GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader);
+    return 0;
+  }
+  GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader);
+  if (ClassCode == 3) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Found GFX Card\n"
+      );
+
+    GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader);
+    if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) {
+      IDS_HDT_CONSOLE (GFX_MISC, "  GFX Card is PCI device\n"
+        );
+      ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
+      return 0;
+    }
+    if ((UINT16) VendorId == 0x1002) {
+      IDS_HDT_CONSOLE (GFX_MISC, "  GFX Card is AMD PCIe device\n"
+        );
+      ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
+    }
+    ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
+  }
+  return 0;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h
new file mode 100644
index 0000000000..e90ea23694
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Supporting services to collect discrete GFX card info
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GFXCARDINFO_H_
+#define _GFXCARDINFO_H_
+
+VOID
+GfxGetDiscreteCardInfo (
+  OUT     GFX_CARD_CARD_INFO  *GfxCardInfo,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
new file mode 100644
index 0000000000..1e89d03f19
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -0,0 +1,636 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+typedef struct {
+  PCIE_CONNECTOR_TYPE ConnectorType;
+  UINT8               DisplayDeviceEnum;
+  UINT16              ConnectorEnum;
+  UINT16              EncoderEnum;
+  UINT8               ConnectorIndex;
+} EXT_CONNECTOR_INFO;
+
+typedef struct {
+  UINT8               DisplayDeviceEnum;
+  UINT8               DeviceIndex;
+  UINT16              DeviceTag;
+  UINT16              DeviceAcpiEnum;
+} EXT_DISPLAY_DEVICE_INFO;
+
+typedef struct {
+  AGESA_STATUS        Status;
+  UINT8               DisplayDeviceEnum;
+  UINT8               RequestedPriorityIndex;
+  UINT8               CurrentPriorityIndex;
+  PCIe_ENGINE_CONFIG  *Engine;
+} CONNECTOR_ENUM_INFO;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+GfxIntegratedEnumConnectorsForDevice (
+  IN       UINT8                            DisplayDeviceEnum,
+     OUT   EXT_DISPLAY_PATH                 *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG             *Pcie,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxIntegratedDebugDumpDisplayPath (
+  IN       EXT_DISPLAY_PATH                 *DisplayPath,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+AGESA_STATUS
+GfxIntegratedEnumerateAllConnectors (
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG        *Pcie,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+VOID
+GfxIntegratedCopyDisplayInfo (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPath,
+     OUT   EXT_DISPLAY_PATH            *SecondaryDisplayPath,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+EXT_CONNECTOR_INFO ConnectorInfoTable[] = {
+  {
+    ConnectorTypeDP,
+    DEVICE_DFP,
+    CONNECTOR_DISPLAYPORT_ENUM,
+    ENCODER_NOT_PRESENT,
+    0,
+  },
+  {
+    ConnectorTypeEDP,
+    DEVICE_LCD,
+    CONNECTOR_eDP_ENUM,
+    ENCODER_NOT_PRESENT,
+    1
+  },
+  {
+    ConnectorTypeSingleLinkDVI,
+    DEVICE_DFP,
+    CONNECTOR_SINGLE_LINK_DVI_D_ENUM,
+    ENCODER_NOT_PRESENT,
+    2
+  },
+  {
+    ConnectorTypeDualLinkDVI,
+    DEVICE_DFP,
+    CONNECTOR_DUAL_LINK_DVI_D_ENUM,
+    ENCODER_NOT_PRESENT,
+    3
+  },
+  {
+    ConnectorTypeHDMI,
+    DEVICE_DFP,
+    CONNECTOR_HDMI_TYPE_A_ENUM,
+    ENCODER_NOT_PRESENT,
+    4
+  },
+  {
+    ConnectorTypeTravisDpToVga,
+    DEVICE_CRT,
+    CONNECTOR_VGA_ENUM,
+    ENCODER_TRAVIS_ENUM_ID1,
+    5
+  },
+  {
+    ConnectorTypeTravisDpToLvds,
+    DEVICE_LCD,
+    CONNECTOR_LVDS_ENUM,
+    ENCODER_TRAVIS_ENUM_ID2,
+    6
+  },
+  {
+    ConnectorTypeNutmegDpToVga,
+    DEVICE_CRT,
+    CONNECTOR_VGA_ENUM,
+    ENCODER_ALMOND_ENUM_ID1,
+    5
+  },
+  {
+    ConnectorTypeSingleLinkDviI,
+    DEVICE_DFP,
+    CONNECTOR_SINGLE_LINK_DVI_I_ENUM,
+    ENCODER_NOT_PRESENT,
+    5
+  },
+  {
+    ConnectorTypeCrt,
+    DEVICE_CRT,
+    CONNECTOR_VGA_ENUM,
+    ENCODER_NOT_PRESENT,
+    5
+  },
+  {
+    ConnectorTypeLvds,
+    DEVICE_LCD,
+    CONNECTOR_LVDS_ENUM,
+    ENCODER_NOT_PRESENT,
+    6
+  },
+  {
+    ConnectorTypeEDPToLvds,
+    DEVICE_LCD,
+    CONNECTOR_eDP_ENUM,
+    ENCODER_NOT_PRESENT,
+    1
+  },
+  {
+    ConnectorTypeEDPToRealtecLvds,
+    DEVICE_LCD,
+    CONNECTOR_eDP_ENUM,
+    ENCODER_NOT_PRESENT,
+    1
+  },
+  {
+    ConnectorTypeAutoDetect,
+    DEVICE_LCD,
+    CONNECTOR_LVDS_eDP_ENUM,
+    ENCODER_TRAVIS_ENUM_ID2,
+    7
+  },
+};
+
+UINT8 ConnectorNumerArray[] = {
+//  DP    eDP   SDVI-D  DDVI-D  HDMI   VGA   LVDS   Auto (eDP, LVDS, Travis LVDS)
+    6,    1,    6,      6,      6,     1,    1,     2
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in] ConnectorType   Connector type (see PCIe_DDI_DATA::ConnectorType).
+ * @retval    Pointer to EXT_CONNECTOR_INFO
+ * @retval    NULL if connector type unknown.
+ */
+STATIC EXT_CONNECTOR_INFO*
+GfxIntegratedExtConnectorInfo (
+  IN       UINT8                         ConnectorType
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) {
+    if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) {
+      return &ConnectorInfoTable[Index];
+    }
+  }
+  return NULL;
+}
+
+EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
+  {
+    DEVICE_CRT,
+    1,
+    ATOM_DEVICE_CRT1_SUPPORT,
+    0x100,
+  },
+  {
+    DEVICE_LCD,
+    1,
+    ATOM_DEVICE_LCD1_SUPPORT,
+    0x110,
+  },
+  {
+    DEVICE_DFP,
+    1,
+    ATOM_DEVICE_DFP1_SUPPORT,
+    0x210,
+  },
+  {
+    DEVICE_DFP,
+    2,
+    ATOM_DEVICE_DFP2_SUPPORT,
+    0x220,
+  },
+  {
+    DEVICE_DFP,
+    3,
+    ATOM_DEVICE_DFP3_SUPPORT,
+    0x230,
+  },
+  {
+    DEVICE_DFP,
+    4,
+    ATOM_DEVICE_DFP4_SUPPORT,
+    0x240,
+  },
+  {
+    DEVICE_DFP,
+    5,
+    ATOM_DEVICE_DFP5_SUPPORT,
+    0x250,
+  },
+  {
+    DEVICE_DFP,
+    6,
+    ATOM_DEVICE_DFP6_SUPPORT,
+    0x260,
+  }
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in] DisplayDeviceEnum   Display device enum
+ * @param[in] DisplayDeviceIndex  Display device index
+ * @retval    Pointer to EXT_DISPLAY_DEVICE_INFO
+ * @retval    NULL if can not get display device info
+ */
+STATIC EXT_DISPLAY_DEVICE_INFO*
+GfxIntegratedExtDisplayDeviceInfo (
+  IN       UINT8                         DisplayDeviceEnum,
+  IN       UINT8                         DisplayDeviceIndex
+  )
+{
+  UINT8 Index;
+  UINT8 LastIndex;
+  LastIndex = 0xff;
+  for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) {
+    if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) {
+      LastIndex = Index;
+      if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) {
+        return &DisplayDeviceInfoTable[Index];
+      }
+    }
+  }
+  if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) {
+    return &DisplayDeviceInfoTable[LastIndex];
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors
+ *
+ *
+ *
+ * @param[out]    DisplayPathList   Display path list
+ * @param[in,out] Pcie              PCIe platform configuration info
+ * @param[in]     Gfx               Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAllConnectors (
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG        *Pcie,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  Status;
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n");
+  Status = GfxIntegratedEnumConnectorsForDevice (
+             DEVICE_DFP,
+             DisplayPathList,
+             Pcie,
+             Gfx
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = GfxIntegratedEnumConnectorsForDevice (
+             DEVICE_CRT,
+             DisplayPathList,
+             Pcie,
+             Gfx
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = GfxIntegratedEnumConnectorsForDevice (
+             DEVICE_LCD,
+             DisplayPathList,
+             Pcie,
+             Gfx
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegratedDdiInterfaceCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  CONNECTOR_ENUM_INFO     *ConnectorEnumInfo;
+  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer;
+  ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
+  if (ExtConnectorInfo == NULL) {
+    AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status);
+    PcieConfigDisableEngine (Engine);
+    return;
+  }
+  if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) {
+    //Not device type we are looking for
+    return;
+  }
+  if (Engine->Type.Ddi.DisplayPriorityIndex >=  ConnectorEnumInfo->RequestedPriorityIndex &&
+      Engine->Type.Ddi.DisplayPriorityIndex <  ConnectorEnumInfo->CurrentPriorityIndex) {
+    ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex;
+    ConnectorEnumInfo->Engine = Engine;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in]     DisplayDeviceEnum Display device list
+ * @param[out]    DisplayPathList   Display path list
+ * @param[in,out] Pcie              PCIe configuration info
+ * @param[in]     Gfx               Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumConnectorsForDevice (
+  IN       UINT8                       DisplayDeviceEnum,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG        *Pcie,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  UINT8                   DisplayDeviceIndex;
+  CONNECTOR_ENUM_INFO     ConnectorEnumInfo;
+  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
+  AGESA_STATUS            Status;
+  UINT8                   ConnectorIdArray[sizeof (ConnectorNumerArray)];
+  ConnectorEnumInfo.Status = AGESA_SUCCESS;
+  DisplayDeviceIndex = 1;
+  ConnectorEnumInfo.RequestedPriorityIndex = 0;
+  ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum;
+  LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx));
+  do {
+    ConnectorEnumInfo.Engine = NULL;
+    ConnectorEnumInfo.CurrentPriorityIndex = 0xff;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+      GfxIntegratedDdiInterfaceCallback,
+      &ConnectorEnumInfo,
+      Pcie
+      );
+    if (ConnectorEnumInfo.Engine == NULL) {
+      break;                                  // No more connector support this
+    }
+    ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1;
+    ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType);
+    ASSERT (ExtConnectorInfo != NULL);
+    ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray));
+    if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >=  ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) {
+      //Run out of supported connectors
+      AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
+      PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
+      continue;
+    }
+    ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1;
+    ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex);
+    if (ExtDisplayDeviceInfo == NULL) {
+      //Run out of supported display device types
+      AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
+      Status = AGESA_ERROR;
+      PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
+    }
+
+    if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) {
+      AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
+      Status = AGESA_ERROR;
+      PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
+    }
+
+    ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex;
+
+    Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx);
+    AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status);
+    if (Status != AGESA_SUCCESS) {
+      continue;
+    }
+    ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++;
+    DisplayDeviceIndex++;
+  } while (ConnectorEnumInfo.Engine != NULL);
+  return ConnectorEnumInfo.Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize display path for given engine
+ *
+ *
+ *
+ * @param[in]  Engine            Engine configuration info
+ * @param[out] DisplayPath       Display path list
+ * @param[out] SecondaryDisplayPath Secondary display path list
+ * @param[in] Gfx                Gfx configuration info
+ */
+
+VOID
+GfxIntegratedCopyDisplayInfo (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPath,
+     OUT   EXT_DISPLAY_PATH            *SecondaryDisplayPath,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
+  ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
+  ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId);
+  DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8);
+  DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag;
+  DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum;
+  DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex;
+  DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex;
+  DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask;
+  DisplayPath->usCaps = Engine->Type.Ddi.DdiData.Flags;
+  DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum;
+  if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) {
+    DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B;
+  } else {
+    DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue;
+  }
+  GNB_DEBUG_CODE (
+    GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx);
+    );
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) {
+    if (SecondaryDisplayPath != NULL) {
+      SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector;
+    }
+    GNB_DEBUG_CODE (
+      GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx);
+    );
+
+    if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) {
+      DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B;
+    } else {
+      DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue;
+    }
+  }
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump  display path settings
+ *
+ *
+ *
+ * @param[in] DisplayPath            Display path
+ * @param[in] Gfx                    Gfx configuration
+ */
+
+VOID
+GfxIntegratedDebugDumpDisplayPath (
+  IN       EXT_DISPLAY_PATH            *DisplayPath,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+ IDS_HDT_CONSOLE (GFX_MISC, "     usDeviceConnector = 0x%x\n",
+   DisplayPath->usDeviceConnector
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usDeviceTag = 0x%x\n",
+   DisplayPath->usDeviceTag
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usDeviceACPIEnum = 0x%x\n",
+   DisplayPath->usDeviceACPIEnum
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usExtEncoderObjId = 0x%x\n",
+   DisplayPath->usExtEncoderObjId
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     ucChannelMapping = 0x%x\n",
+   DisplayPath->ChannelMapping.ucChannelMapping
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     ucChPNInvert = 0x%x\n",
+   DisplayPath->ucChPNInvert
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usCaps = 0x%x\n",
+   DisplayPath->usCaps
+   );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h
new file mode 100644
index 0000000000..0527f33bb8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXENUMCONNECTORS_H_
+#define _GFXENUMCONNECTORS_H_
+
+
+VOID
+GfxIntegratedCopyDisplayInfo (
+  IN       PCIe_ENGINE_CONFIG             *Engine,
+     OUT   EXT_DISPLAY_PATH               *DisplayPath,
+     OUT   EXT_DISPLAY_PATH               *SecondaryDisplayPath,
+  IN       GFX_PLATFORM_CONFIG            *Gfx
+  );
+
+AGESA_STATUS
+GfxIntegratedEnumerateAllConnectors (
+     OUT   EXT_DISPLAY_PATH                 *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG             *Pcie,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
new file mode 100644
index 0000000000..462fa72c01
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -0,0 +1,1013 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbFuseTable.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GfxPowerPlayTable.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Software state
+typedef struct {
+  BOOLEAN     Valid;                                  ///< State valid
+  UINT16      Classification;                         ///< State classification
+  UINT32      CapsAndSettings;                        ///< State capability and settings
+  UINT16      Classification2;                        ///< State classification2
+  UINT32      Vclk;                                   ///< UVD VCLK
+  UINT32      Dclk;                                   ///< UVD DCLK
+  UINT8       NumberOfDpmStates;                      ///< Number of DPM states
+  UINT8       DpmSatesArray[MAX_NUM_OF_DPM_STATES];   ///< DPM state index array
+} SW_STATE;
+
+/// DPM state
+typedef struct {
+  BOOLEAN     Valid;                                  ///< State valid
+  UINT32      Sclk;                                   ///< Sclk in kHz
+  UINT8       Vid;                                    ///< VID index
+  UINT16      Tdp;                                    ///< Tdp limit
+} DPM_STATE;
+
+typedef struct {
+  GFX_PLATFORM_CONFIG                       *Gfx;
+  ATOM_PPLIB_POWERPLAYTABLE3                *PpTable;
+  PP_FUSE_ARRAY                             *PpFuses;
+  SW_STATE                                  SwStateArray [MAX_NUM_OF_SW_STATES];          ///< SW state array
+  DPM_STATE                                 DpmStateArray[MAX_NUM_OF_DPM_STATES];         ///< Sclk DPM state array
+  UINT8                                     NumOfClockVoltageLimitEnties;                 ///
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD VceClockVoltageLimitArray[MAX_NUM_OF_VCE_CLK_STATES];
+  UINT8                                     NumOfVceClockEnties;
+  VCECLOCKINFO                              VceClockInfoArray[MAX_NUM_OF_VCE_CLK_STATES];
+  UINT8                                     NumOfVceStateEntries;
+  ATOM_PPLIB_VCE_STATE_RECORD               VceStateArray[MAX_NUM_OF_VCE_STATES];         ///< VCE state array
+} PP_WORKSPACE;
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GfxIntegratedDebugDumpPpTable (
+  IN       ATOM_PPLIB_POWERPLAYTABLE3   *PpTable,
+  IN       GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate existing tdp
+ *
+ *
+ * @param[in     ]  PpFuses          Pointer to  PP_FUSE_ARRAY
+ * @param[in]       Sclk             Sclk in 10kHz
+ * @param[in]       StdHeader        Standard configuration header
+ * @retval                           Tdp limit in DPM state array
+ */
+
+STATIC UINT16
+GfxPowerPlayLocateTdp (
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      UINT32                        Sclk,
+  IN      AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  UINT8   Index;
+  UINT32  DpmIndex;
+  UINT32  DpmSclk;
+  UINT32  DeltaSclk;
+  UINT32  MinDeltaSclk;
+
+  DpmIndex = 0;
+  MinDeltaSclk = 0xFFFFFFFF;
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+    if (PpFuses->SclkDpmDid[Index] != 0) {
+      DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader);
+      DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk);
+      if (DeltaSclk < MinDeltaSclk) {
+        MinDeltaSclk = MinDeltaSclk;
+        DpmIndex = Index;
+      }
+    }
+  }
+  return PpFuses->SclkDpmTdpLimit[DpmIndex];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create new software state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @retval                           Pointer to state entry in SW state array
+ */
+
+STATIC SW_STATE*
+GfxPowerPlayCreateSwState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
+    if (PpWorkspace->SwStateArray[Index].Valid == FALSE) {
+      PpWorkspace->SwStateArray[Index].Valid = TRUE;
+      return  &(PpWorkspace->SwStateArray[Index]);
+    }
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create new DPM state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       Sclk             SCLK in kHz
+ * @param[in]       Vid              Vid index
+ * @param[in]       Tdp              Tdp limit
+ * @retval                           Index of state entry in DPM state array
+ */
+
+STATIC UINT8
+GfxPowerPlayCreateDpmState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT32                        Sclk,
+  IN       UINT8                         Vid,
+  IN       UINT16                        Tdp
+  )
+{
+  UINT8 Index;
+  for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
+    if (PpWorkspace->DpmStateArray[Index].Valid == FALSE) {
+      PpWorkspace->DpmStateArray[Index].Sclk = Sclk;
+      PpWorkspace->DpmStateArray[Index].Vid = Vid;
+      PpWorkspace->DpmStateArray[Index].Valid = TRUE;
+      PpWorkspace->DpmStateArray[Index].Tdp = Tdp;
+      return Index;
+    }
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate existing or Create new DPM state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       Sclk             SCLK in kHz
+ * @param[in]       Vid              Vid index
+ * @param[in]       Tdp              Tdp limit
+ * @retval                           Index of state entry in DPM state array
+ */
+
+STATIC UINT8
+GfxPowerPlayAddDpmState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT32                        Sclk,
+  IN       UINT8                         Vid,
+  IN       UINT16                        Tdp
+  )
+{
+  UINT8 Index;
+  for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
+    if (PpWorkspace->DpmStateArray[Index].Valid && Sclk == PpWorkspace->DpmStateArray[Index].Sclk && Vid == PpWorkspace->DpmStateArray[Index].Vid) {
+      return Index;
+    }
+  }
+  return GfxPowerPlayCreateDpmState (PpWorkspace, Sclk, Vid, Tdp);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Add reference to DPM state for SW state
+ *
+ *
+ * @param[in, out]  SwStateArray     Pointer to SW state array
+ * @param[in]       DpmStateIndex    DPM state index
+ */
+
+STATIC VOID
+GfxPowerPlayAddDpmStateToSwState (
+  IN OUT   SW_STATE                      *SwStateArray,
+  IN       UINT8                         DpmStateIndex
+  )
+{
+  SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy SW state info to PPTable
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+STATIC VOID *
+GfxPowerPlayAttachStateInfoBlock (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINT8                 Index;
+  UINT8                 SwStateIndex;
+  STATE_ARRAY           *StateArray;
+  ATOM_PPLIB_STATE_V2   *States;
+  StateArray = (STATE_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  States = &StateArray->States[0];
+  SwStateIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
+    if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) {
+      States->nonClockInfoIndex  = SwStateIndex;
+      States->ucNumDPMLevels = PpWorkspace->SwStateArray[Index].NumberOfDpmStates;
+      LibAmdMemCopy (
+        &States->ClockInfoIndex[0],
+        PpWorkspace->SwStateArray[Index].DpmSatesArray,
+        PpWorkspace->SwStateArray[Index].NumberOfDpmStates,
+        GnbLibGetHeader (PpWorkspace->Gfx)
+        );
+      States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1));
+      SwStateIndex++;
+    }
+  }
+  StateArray->ucNumEntries = SwStateIndex;
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray);
+  return StateArray;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy clock info to PPTable
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachClockInfoBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  CLOCK_INFO_ARRAY            *ClockInfoArray;
+  UINT8                       Index;
+  UINT8                       ClkStateIndex;
+  ClkStateIndex = 0;
+  ClockInfoArray = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
+    if (PpWorkspace->DpmStateArray[Index].Valid == TRUE) {
+      ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (PpWorkspace->DpmStateArray[Index].Sclk  >> 16);
+      ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (PpWorkspace->DpmStateArray[Index].Sclk);
+      ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = PpWorkspace->DpmStateArray[Index].Vid;
+      ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = PpWorkspace->DpmStateArray[Index].Tdp;
+      ClkStateIndex++;
+    }
+  }
+  ClockInfoArray->ucNumEntries = ClkStateIndex;
+  ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * ClkStateIndex - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
+  return ClockInfoArray;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy non clock info to PPTable
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachNonClockInfoBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  NON_CLOCK_INFO_ARRAY  *NonClockInfoArray;
+  UINT8                 Index;
+  UINT8                 NonClkStateIndex;
+
+  NonClockInfoArray = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  NonClkStateIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
+    if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) {
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = PpWorkspace->SwStateArray[Index].Classification;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = PpWorkspace->SwStateArray[Index].CapsAndSettings;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = PpWorkspace->SwStateArray[Index].Classification2;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = PpWorkspace->SwStateArray[Index].Dclk;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = PpWorkspace->SwStateArray[Index].Vclk;
+      NonClkStateIndex++;
+    }
+  }
+  NonClockInfoArray->ucNumEntries = NonClkStateIndex;
+  NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO);
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO);
+  return NonClockInfoArray;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if fused state valid
+ *
+ *
+ * @param[out]      Index             State index
+ * @param[in]       PpFuses           Pointer to fuse table
+ * @param[in]       Gfx               Gfx configuration info
+ * @retval          TRUE              State is valid
+ */
+STATIC BOOLEAN
+GfxPowerPlayIsFusedStateValid (
+  IN      UINT8                         Index,
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  BOOLEAN Result;
+  Result = FALSE;
+  if (PpFuses->SclkDpmValid[Index] != 0) {
+    Result = TRUE;
+    if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) {
+      Result = FALSE;
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SW state calssification from fuses
+ *
+ *
+ * @param[out]      Index             State index
+ * @param[in]       PpFuses           Pointer to fuse table
+ * @param[in]       Gfx               Gfx configuration info
+ * @retval                            State classification
+ */
+
+STATIC UINT16
+GfxPowerPlayGetClassificationFromFuses (
+  IN      UINT8                         Index,
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  UINT16  Classification;
+  Classification = 0;
+  switch (PpFuses->PolicyFlags[Index]) {
+  case 0x1:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE;
+    break;
+  case 0x2:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE;
+    break;
+  case 0x4:
+    //Possible SD + HD state
+    break;
+  case 0x8:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE;
+    break;
+  case 0x10:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE;
+    break;
+  default:
+    break;
+  }
+  switch (PpFuses->PolicyLabel[Index]) {
+  case POLICY_LABEL_BATTERY:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY;
+    break;
+  case POLICY_LABEL_PERFORMANCE:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE;
+    break;
+  default:
+    break;
+  }
+  return Classification;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SW state calssification2 from fuses
+ *
+ *
+ * @param[out]      Index             State index
+ * @param[in]       PpFuses           Pointer to fuse table
+ * @param[in]       Gfx               Gfx configuration info
+ * @retval                            State classification2
+ */
+
+STATIC UINT16
+GfxPowerPlayGetClassification2FromFuses (
+  IN      UINT8                         Index,
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  UINT16  Classification2;
+  Classification2 = 0;
+
+  switch (PpFuses->PolicyFlags[Index]) {
+
+  case 0x4:
+    Classification2 |= ATOM_PPLIB_CLASSIFICATION2_MVC;
+    break;
+
+  default:
+    break;
+  }
+
+  return Classification2;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build SCLK state info
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID
+GfxPowerPlayBuildSclkStateTable (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINT8                       ClkStateIndex;
+  UINT8                       DpmFuseIndex;
+  UINT8                       Index;
+  UINT32                      Sclk;
+  SW_STATE                    *State;
+  PP_FUSE_ARRAY               *PpFuses;
+
+  PpFuses = PpWorkspace->PpFuses;
+  // Create States from Fuses
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) {
+    if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, PpWorkspace->Gfx)) {
+      //Create new SW State;
+      State = GfxPowerPlayCreateSwState (PpWorkspace);
+      State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, PpWorkspace->Gfx);
+      State->Classification2 = GfxPowerPlayGetClassification2FromFuses (Index, PpFuses, PpWorkspace->Gfx);
+      if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0 ||
+          (State->Classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) != 0) {
+        State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]],  GnbLibGetHeader (PpWorkspace->Gfx)) : 0;
+        State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]],  GnbLibGetHeader (PpWorkspace->Gfx)) : 0;
+      }
+      if (((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
+          ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0)) {
+        if (PpWorkspace->Gfx->AbmSupport != 0) {
+          State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT;
+        }
+        if (PpWorkspace->Gfx->DynamicRefreshRate != 0) {
+          State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR;
+        }
+      }
+      for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) {
+        if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) {
+          Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (PpWorkspace->Gfx)) : 0;
+          if (Sclk != 0) {
+            ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]);
+            GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
+          }
+        }
+      }
+    }
+  }
+  // Create Boot State
+  State = GfxPowerPlayCreateSwState (PpWorkspace);
+  State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT;
+  Sclk = 200 * 100;
+  ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx)));
+  GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
+
+  // Create Thermal State
+  State = GfxPowerPlayCreateSwState (PpWorkspace);
+  State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL;
+  Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (PpWorkspace->Gfx));
+  ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx)));
+  GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Add ECLK state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       Eclk             SCLK in kHz
+ * @retval                           Index of state entry in ECLK clock array
+ */
+
+STATIC UINT8
+GfxPowerPlayAddEclkState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT32                        Eclk
+  )
+{
+  UINT8   Index;
+  USHORT  EclkLow;
+  UCHAR   EclkHigh;
+  EclkLow = (USHORT) (Eclk & 0xffff);
+  EclkHigh = (UCHAR) (Eclk >> 16);
+  for (Index = 0; Index < PpWorkspace->NumOfVceClockEnties; Index++) {
+    if (PpWorkspace->VceClockInfoArray[Index].ucECClkHigh == EclkHigh && PpWorkspace->VceClockInfoArray[Index].usECClkLow == EclkLow) {
+      return Index;
+    }
+  }
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucECClkHigh = EclkHigh;
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usECClkLow = EclkLow;
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucEVClkHigh = EclkHigh;
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usEVClkLow = EclkLow;
+  return PpWorkspace->NumOfVceClockEnties++;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Add ECLK state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       EclkIndex        ECLK index
+  * @param[in]      Vid              Vid index
+ * @retval                           Index of state entry in Eclk Voltage record array
+ */
+
+STATIC UINT8
+GfxPowerPlayAddEclkVoltageRecord (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT8                         EclkIndex,
+  IN       UINT8                         Vid
+  )
+{
+  UINT8   Index;
+  for (Index = 0; Index < PpWorkspace->NumOfClockVoltageLimitEnties; Index++) {
+    if (PpWorkspace->VceClockVoltageLimitArray[Index].ucVCEClockInfoIndex == EclkIndex) {
+      return Index;
+    }
+  }
+  PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].ucVCEClockInfoIndex = EclkIndex;
+  PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].usVoltage = Vid;
+  return PpWorkspace->NumOfClockVoltageLimitEnties++;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach extended header
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceTableRevBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_VCE_TABLE  *VceTable;
+  VceTable = (ATOM_PPLIB_VCE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceTable->revid = 0;
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_VCE_TABLE);
+  return VceTable;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach extended header
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachExtendedHeaderBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader;
+  ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  ExtendedHeader->usSize = sizeof (ATOM_PPLIB_EXTENDEDHEADER);
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_EXTENDEDHEADER);
+  return ExtendedHeader;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach VCE clock info block
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceClockInfoBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  VCECLOCKINFOARRAY   *VceClockInfoArray;
+  VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceClockInfoArray->ucNumEntries = PpWorkspace->NumOfVceClockEnties;
+  LibAmdMemCopy (
+    &VceClockInfoArray->entries[0],
+    &PpWorkspace->VceClockInfoArray[0],
+    VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO),
+    GnbLibGetHeader (PpWorkspace->Gfx)
+    );
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize +
+                                                  sizeof (VCECLOCKINFOARRAY) +
+                                                  VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) -
+                                                  sizeof (VCECLOCKINFO);
+  return VceClockInfoArray;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach VCE voltage limit block
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceVoltageLimitBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE  *VceClockVoltageLimitTable;
+  VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceClockVoltageLimitTable->numEntries = PpWorkspace->NumOfClockVoltageLimitEnties;
+  LibAmdMemCopy (
+    &VceClockVoltageLimitTable->entries[0],
+    &PpWorkspace->VceClockVoltageLimitArray[0],
+    VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD),
+    GnbLibGetHeader (PpWorkspace->Gfx)
+    );
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize +
+                                                  sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) +
+                                                  VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) -
+                                                  sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD);
+  return VceClockVoltageLimitTable;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach VCE state block
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceStateTaleBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_VCE_STATE_TABLE  *VceStateTable;
+  VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceStateTable->numEntries = PpWorkspace->NumOfVceStateEntries;
+  LibAmdMemCopy (
+    &VceStateTable->entries[0],
+    &PpWorkspace->VceStateArray[0],
+    VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD),
+    GnbLibGetHeader (PpWorkspace->Gfx)
+    );
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize +
+                                                  sizeof (ATOM_PPLIB_VCE_STATE_TABLE) +
+                                                  VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD) -
+                                                  sizeof (ATOM_PPLIB_VCE_STATE_RECORD);
+  return VceStateTable;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build VCE state info
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID
+GfxPowerPlayBuildVceStateTable (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINT8                       Index;
+  UINT8                       VceStateIndex;
+  UINT8                       Vid;
+  UINT32                      Eclk;
+  UINT32                      Sclk;
+  UINT8                       UsedStateBitmap;
+  UsedStateBitmap = 0;
+  // build used state
+  for (Index = 0; Index < (sizeof (PpWorkspace->PpFuses->VceFlags) / sizeof (PpWorkspace->PpFuses->VceFlags[0])) ; Index++) {
+    UsedStateBitmap |= PpWorkspace->PpFuses->VceFlags[Index];
+    for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) {
+      if ((PpWorkspace->PpFuses->VceFlags[Index] & (1 << VceStateIndex)) != 0) {
+        Sclk = GfxFmCalculateClock (PpWorkspace->PpFuses->SclkDpmDid[PpWorkspace->PpFuses->VceReqSclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx));
+        Vid = PpWorkspace->PpFuses->SclkDpmVid[PpWorkspace->PpFuses->VceReqSclkSel[Index]];
+        PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, Vid, GfxPowerPlayLocateTdp (PpWorkspace->PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx)));
+        if (PpWorkspace->PpFuses->VceMclk[Index] == 1) {
+          PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex |= (PpWorkspace->PpFuses->VceMclk[Index] << 6);
+        }
+        Eclk = GfxFmCalculateClock (PpWorkspace->PpFuses->EclkDid[Index], GnbLibGetHeader (PpWorkspace->Gfx));
+        PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, Eclk);
+        GfxPowerPlayAddEclkVoltageRecord (PpWorkspace, PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex, Vid);
+        PpWorkspace->NumOfVceStateEntries++;
+      }
+    }
+  }
+  //build unused states
+  for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) {
+    if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) {
+      PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0;
+      PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, 0);
+      PpWorkspace->NumOfVceStateEntries++;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build PP table
+ *
+ *
+ * @param[out] Buffer           Buffer to create PP table
+ * @param[in]  Gfx              Gfx configuration info
+ * @retval     AGESA_SUCCESS
+ * @retval     AGESA_ERROR
+ */
+
+AGESA_STATUS
+GfxPowerPlayBuildTable (
+     OUT   VOID                          *Buffer,
+  IN       GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  PP_WORKSPACE                PpWorkspace;
+  VOID                        *BlockPtr;
+
+  LibAmdMemFill (&PpWorkspace, 0x00, sizeof (PP_WORKSPACE), GnbLibGetHeader (Gfx));
+  PpWorkspace.PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+  ASSERT (PpWorkspace.PpFuses != NULL);
+  if (PpWorkspace.PpFuses == NULL) {
+    return AGESA_ERROR;
+  }
+  PpWorkspace.PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer;
+  PpWorkspace.Gfx = Gfx;
+  //Fill static info
+  PpWorkspace.PpTable->sHeader.ucTableFormatRevision = 6;
+  PpWorkspace.PpTable->sHeader.ucTableContentRevision = 1;
+  PpWorkspace.PpTable->ucDataRevision = PpWorkspace.PpFuses->PPlayTableRev;
+  PpWorkspace.PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO;
+  PpWorkspace.PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN;
+  PpWorkspace.PpTable->sHeader.usStructureSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3);
+  PpWorkspace.PpTable->usTableSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3);
+  PpWorkspace.PpTable->usFormatID = 7;
+  if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) {
+    PpWorkspace.PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY;
+  }
+
+  // Fill Slck SW/DPM state info
+  GfxPowerPlayBuildSclkStateTable (&PpWorkspace);
+  // Fill Eclk state info
+  if (PpWorkspace.PpFuses->VceSateTableSupport) {
+    GfxPowerPlayBuildVceStateTable (&PpWorkspace);
+  }
+
+  //Copy state info to actual PP table
+  BlockPtr = GfxPowerPlayAttachStateInfoBlock (&PpWorkspace);
+  PpWorkspace.PpTable->usStateArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+  BlockPtr = GfxPowerPlayAttachClockInfoBlock (&PpWorkspace);
+  PpWorkspace.PpTable->usClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+  BlockPtr = GfxPowerPlayAttachNonClockInfoBlock (&PpWorkspace);
+  PpWorkspace.PpTable->usNonClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+  if (PpWorkspace.PpFuses->VceSateTableSupport) {
+    ATOM_PPLIB_EXTENDEDHEADER   *ExtendedHeader;
+    ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) GfxPowerPlayAttachExtendedHeaderBlock (&PpWorkspace);
+    PpWorkspace.PpTable->usExtendendedHeaderOffset = (USHORT) ((UINT8 *) ExtendedHeader - (UINT8 *) (PpWorkspace.PpTable));
+    BlockPtr = GfxPowerPlayAttachVceTableRevBlock (&PpWorkspace);
+    ExtendedHeader->usVCETableOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+    GfxPowerPlayAttachVceClockInfoBlock (&PpWorkspace);
+    GfxPowerPlayAttachVceVoltageLimitBlock (&PpWorkspace);
+    GfxPowerPlayAttachVceStateTaleBlock (&PpWorkspace);
+
+  }
+  GNB_DEBUG_CODE (
+    GfxIntegratedDebugDumpPpTable (PpWorkspace.PpTable, Gfx);
+  );
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump PP table
+ *
+ *
+ *
+ * @param[in] PpTable           Power Play table
+ * @param[in] Gfx               Gfx configuration info
+ */
+
+VOID
+GfxIntegratedDebugDumpPpTable (
+  IN       ATOM_PPLIB_POWERPLAYTABLE3   *PpTable,
+  IN       GFX_PLATFORM_CONFIG          *Gfx
+  )
+{
+  UINTN                                     Index;
+  UINTN                                     DpmIndex;
+  STATE_ARRAY                               *StateArray;
+  ATOM_PPLIB_STATE_V2                       *StatesPtr;
+  NON_CLOCK_INFO_ARRAY                      *NonClockInfoArrayPtr;
+  CLOCK_INFO_ARRAY                          *ClockInfoArrayPtr;
+  ATOM_PPLIB_EXTENDEDHEADER                 *ExtendedHeader;
+  ATOM_PPLIB_VCE_STATE_TABLE                *VceStateTable;
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE  *VceClockVoltageLimitTable;
+  VCECLOCKINFOARRAY                         *VceClockInfoArray;
+  UINT8                                     SclkIndex;
+  UINT8                                     EclkIndex;
+
+  IDS_HDT_CONSOLE (GFX_MISC, "  < --- Power Play Table ------ > \n");
+  IDS_HDT_CONSOLE (GFX_MISC, "  Table Revision = %d\n", PpTable->ucDataRevision);
+  StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset);
+  StatesPtr = StateArray->States;
+  NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset);
+  ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
+  IDS_HDT_CONSOLE (GFX_MISC, "  < --- SW State Table ---------> \n");
+  for (Index = 0; Index < StateArray->ucNumEntries; Index++) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  State #%d\n", Index + 1
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    Classification 0x%x\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    Classification2 0x%x\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    VCLK = %dkHz\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    DCLK = %dkHz\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    DPM State Index: ");
+    for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) {
+      IDS_HDT_CONSOLE (GFX_MISC, "%d ",
+        StatesPtr->ClockInfoIndex [DpmIndex]
+        );
+    }
+    IDS_HDT_CONSOLE (GFX_MISC, "\n");
+    StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1);
+  }
+  IDS_HDT_CONSOLE (GFX_MISC, "  < --- SCLK DPM State Table ---> \n");
+  for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) {
+    UINT32  Sclk;
+    Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16);
+    IDS_HDT_CONSOLE (GFX_MISC, "  DPM State #%d\n",
+      Index
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    SCLK = %d\n",
+      ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16)
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    VID index = %d\n",
+      ClockInfoArrayPtr->ClockInfo[Index].vddcIndex
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    tdpLimit  = %d\n",
+      ClockInfoArrayPtr->ClockInfo[Index].tdpLimit
+      );
+  }
+  if (PpTable->usExtendendedHeaderOffset != 0) {
+    ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable + PpTable->usExtendendedHeaderOffset);
+    VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) ExtendedHeader + sizeof (ATOM_PPLIB_EXTENDEDHEADER) + sizeof (ATOM_PPLIB_VCE_TABLE));
+    VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) VceClockInfoArray +
+                                sizeof (VCECLOCKINFOARRAY) +
+                                VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) -
+                                sizeof (VCECLOCKINFO));
+    VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) VceClockVoltageLimitTable +
+                    sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) +
+                    VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) -
+                    sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD));
+
+    IDS_HDT_CONSOLE (GFX_MISC, "  < --- VCE State Table [%d]--> \n", VceStateTable->numEntries);
+    for (Index = 0; Index < VceStateTable->numEntries; Index++) {
+      SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F;
+      EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex;
+      IDS_HDT_CONSOLE (GFX_MISC, "  VCE State #%d\n", Index
+        );
+      if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) {
+        IDS_HDT_CONSOLE (GFX_MISC, "    Disable\n");
+      } else {
+        IDS_HDT_CONSOLE (GFX_MISC, "    SCLK = %d\n",
+          ClockInfoArrayPtr->ClockInfo[SclkIndex].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[SclkIndex].ucEngineClockHigh << 16)
+          );
+        IDS_HDT_CONSOLE (GFX_MISC, "    ECCLK = %d\n",
+          VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)
+          );
+        IDS_HDT_CONSOLE (GFX_MISC, "    EVCLK = %d\n",
+          VceClockInfoArray->entries[EclkIndex].usEVClkLow | (VceClockInfoArray->entries[EclkIndex].ucEVClkHigh << 16)
+          );
+        IDS_HDT_CONSOLE (GFX_MISC, "    MCLK = %d\n",
+          (VceStateTable->entries[Index].ucClockInfoIndex >> 6 ) & 0x3
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GFX_MISC, "  < --- VCE Voltage Record Table ---> \n");
+    for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) {
+      EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex;
+      IDS_HDT_CONSOLE (GFX_MISC, "  VCE Voltage Record #%d\n", Index
+        );
+      IDS_HDT_CONSOLE (GFX_MISC, "    ECLK = %d\n",
+        VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)
+        );
+      IDS_HDT_CONSOLE (GFX_MISC, "    VID index = %d\n",
+        VceClockVoltageLimitTable->entries[Index].usVoltage
+        );
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h
new file mode 100644
index 0000000000..fd19f605d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h
@@ -0,0 +1,278 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Power Play Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXPOWERPLAYTABLE_H_
+#define _GFXPOWERPLAYTABLE_H_
+
+#pragma pack (push, 1)
+
+#define POLICY_LABEL_BATTERY                                0x1
+#define POLICY_LABEL_PERFORMANCE                            0x2
+
+#define MAX_NUM_OF_SW_STATES                                10
+#define MAX_NUM_OF_DPM_STATES                               10
+#define MAX_NUM_OF_VCE_CLK_STATES                           5
+#define MAX_NUM_OF_VCE_STATES                               6
+#define MAX_NUM_OF_FUSED_DPM_STATES                         5
+#define MAX_NUM_OF_FUSED_SW_STATES                          6
+/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
+#define ATOM_PP_PLATFORM_CAP_BACKBIAS                       1
+#define ATOM_PP_PLATFORM_CAP_POWERPLAY                      2
+#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE               4
+#define ATOM_PP_PLATFORM_CAP_ASPM_L0s                       8
+#define ATOM_PP_PLATFORM_CAP_ASPM_L1                        16
+#define ATOM_PP_PLATFORM_CAP_HARDWAREDC                     32
+#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY                  64
+#define ATOM_PP_PLATFORM_CAP_STEPVDDC                       128
+#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL                 256
+#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL                512
+#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1              1024
+#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL                  2048
+#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL                    4096
+#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT             0x2000        // Go to boot state on alerts, e.g. on an AC->DC transition.
+#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT  0x4000        // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
+#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL                  0x8000        // Does
+#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT                  0x00010000ul  // Enable the 'regulator hot' feature.
+#define ATOM_PP_PLATFORM_CAP_BACO                           0x00020000ul  // Does the driver supports BACO state.
+
+
+#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY                1
+#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED               3
+#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE            5
+
+#define ATOM_PPLIB_CLASSIFICATION_BOOT                      0x0008
+#define ATOM_PPLIB_CLASSIFICATION_THERMAL                   0x0010
+#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE        0x0020
+#define ATOM_PPLIB_CLASSIFICATION_REST                      0x0040
+#define ATOM_PPLIB_CLASSIFICATION_FORCED                    0x0080
+#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE             0x0100
+#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE         0x0200
+#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE                  0x0400
+#define ATOM_PPLIB_CLASSIFICATION_3DLOW                     0x0800
+#define ATOM_PPLIB_CLASSIFICATION_ACPI                      0x1000
+#define ATOM_PPLIB_CLASSIFICATION_HD2STATE                  0x2000
+#define ATOM_PPLIB_CLASSIFICATION_HDSTATE                   0x4000
+#define ATOM_PPLIB_CLASSIFICATION_SDSTATE                   0x8000
+#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE               0x0000
+
+#define ATOM_PPLIB_CLASSIFICATION2_MVC                      0x0004       //Multi-View
+
+#define ATOM_PPLIB_ENABLE_VARIBRIGHT                        0x00008000ul
+#define ATOM_PPLIB_ENABLE_DRR                               0x00080000ul
+
+#define ATOM_PP_FANPARAMETERS_NOFAN                         0x80
+#define ATOM_PP_THERMALCONTROLLER_SUMO                      0x0E
+
+/// DPM state info
+typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO {
+  USHORT                      usEngineClockLow;             ///< Sclk [15:0] (Sclk in 10khz)
+  UCHAR                       ucEngineClockHigh;            ///< Sclk [23:16](Sclk in 10khz)
+  UCHAR                       vddcIndex;                    ///< 2-bit VDDC index;
+  USHORT                      tdpLimit;                     ///< TDP Limit
+  USHORT                      rsv1;                         ///< Reserved
+  ULONG                       rsv2[2];                      ///< Reserved
+} ATOM_PPLIB_SUMO_CLOCK_INFO;
+
+/// Non clock info
+typedef struct _ATOM_PPLIB_NONCLOCK_INFO {
+  USHORT                      usClassification;             ///< State classification see ATOM_PPLIB_CLASSIFICATION_*
+  UCHAR                       ucMinTemperature;             ///< Reserved
+  UCHAR                       ucMaxTemperature;             ///< Reserved
+  ULONG                       ulCapsAndSettings;            ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0)
+  UCHAR                       ucRequiredPower;              ///< Reserved
+  USHORT                      usClassification2;            ///< Reserved
+  ULONG                       ulVCLK;                       ///< UVD clocks VCLK unit is in 10KHz
+  ULONG                       ulDCLK;                       ///< UVD clocks DCLK unit is in 10KHz
+  UCHAR                       ucUnused[5];                  ///< Reserved
+} ATOM_PPLIB_NONCLOCK_INFO;
+
+/// Thermal controller info stub
+typedef struct _ATOM_PPLIB_THERMALCONTROLLER {
+  UCHAR                       ucType;                       ///< Reserved. Should be set 0xE
+  UCHAR                       ucI2cLine;                    ///< Reserved. Should be set 0
+  UCHAR                       ucI2cAddress;                 ///< Reserved. Should be set 0
+  UCHAR                       ucFanParameters;              ///< Reserved. Should be set 0x80
+  UCHAR                       ucFanMinRPM;                  ///< Reserved. Should be set 0
+  UCHAR                       ucFanMaxRPM;                  ///< Reserved. Should be set 0
+  UCHAR                       ucReserved;                   ///< Reserved. Should be set 0
+  UCHAR                       ucFlags;                      ///< Reserved. Should be set 0
+} ATOM_PPLIB_THERMALCONTROLLER;
+
+/// SW state info
+typedef struct _ATOM_PPLIB_STATE_V2 {
+  UCHAR                       ucNumDPMLevels;               ///< Number of valid DPM levels in this state
+  UCHAR                       nonClockInfoIndex;            ///< Index to the array of NonClockInfos
+  UCHAR                       ClockInfoIndex[1];            ///< Array of DPM states. Actual number calculated during state enumeration
+} ATOM_PPLIB_STATE_V2;
+
+/// SW state Array
+typedef struct {
+  UCHAR                       ucNumEntries;                 ///< Number of SW states
+  ATOM_PPLIB_STATE_V2         States[1];                    ///< SW state info. Actual number calculated during state enumeration
+} STATE_ARRAY;
+
+/// Clock info Array
+typedef struct {
+  UCHAR                       ucNumEntries;                 ///< Number of ClockInfo entries
+  UCHAR                       ucEntrySize;                  ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO
+  ATOM_PPLIB_SUMO_CLOCK_INFO  ClockInfo[1];                 ///< Clock info array. Size will be determined dynamically base on fuses
+} CLOCK_INFO_ARRAY;
+
+/// Non clock info Array
+typedef struct {
+
+  UCHAR                       ucNumEntries;                 ///< Number of Entries;
+  UCHAR                       ucEntrySize;                  ///< Size of NonClockInfo
+  ATOM_PPLIB_NONCLOCK_INFO    NonClockInfo[1];              ///< Non clock info array
+} NON_CLOCK_INFO_ARRAY;
+
+/// VCE clock info
+typedef struct {
+  USHORT                    usEVClkLow;                   ///< EVCLK low
+  UCHAR                     ucEVClkHigh;                  ///< EVCLK high
+  USHORT                    usECClkLow;                   ///< ECCLK low
+  UCHAR                     ucECClkHigh;                  ///< ECCLK high
+} VCECLOCKINFO;
+
+/// VCE clock info array
+typedef struct {
+  UCHAR                     ucNumEntries;                ///< Number of entries
+  VCECLOCKINFO              entries[1];                  ///< VCE clock arrau
+} VCECLOCKINFOARRAY;
+
+/// VCE voltage limit record
+typedef struct {
+  USHORT                    usVoltage;                    ///< Voltage index
+  UCHAR                     ucVCEClockInfoIndex;          ///< Index of VCE clock state
+} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD;
+
+/// VCE voltage limit table
+typedef struct {
+  UCHAR                                     numEntries;   ///< Number of entries
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD entries[1];   ///< Coltage limit state array
+} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE;
+
+/// VCE state record
+typedef struct {
+  UCHAR                     ucVCEClockInfoIndex;          ///< Index of VCE clock state
+  UCHAR                     ucClockInfoIndex;             ///< Index of SCLK clock state
+} ATOM_PPLIB_VCE_STATE_RECORD;
+
+/// VCE state table
+typedef struct {
+  UCHAR                       numEntries;                 ///< Number of state entries
+  ATOM_PPLIB_VCE_STATE_RECORD entries[1];                 ///< State entries
+} ATOM_PPLIB_VCE_STATE_TABLE;
+
+/// Extended header
+typedef struct {
+  USHORT                      usSize;                     ///< size of header
+  ULONG                       rsv15;                      ///< reserved
+  ULONG                       rsv16;                      ///< reserved
+  USHORT                      usVCETableOffset;           ///< offset of ATOM_PPLIB_VCE_TABLE
+} ATOM_PPLIB_EXTENDEDHEADER;
+
+/// VCE table
+typedef struct {
+  UCHAR                       revid;                      ///< revision ID
+} ATOM_PPLIB_VCE_TABLE;
+
+/// Power Play table
+typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 {
+  ATOM_COMMON_TABLE_HEADER      sHeader;                    ///< Common header
+  UCHAR                         ucDataRevision;             ///< Revision of PP table
+  UCHAR                         Reserved1[4];               ///< Reserved
+  USHORT                        usStateArrayOffset;         ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
+  USHORT                        usClockInfoArrayOffset;     ///< Offset from start of the table to ClockInfoArray
+  USHORT                        usNonClockInfoArrayOffset;  ///< Offset from Start of the table to NonClockInfoArray
+  USHORT                        Reserved2[2];               ///< Reserved
+  USHORT                        usTableSize;                ///< the size of this structure, or the extended structure
+  ULONG                         ulPlatformCaps;             ///< See ATOM_PPLIB_CAPS_*
+  ATOM_PPLIB_THERMALCONTROLLER  sThermalController;         ///< Thermal controller stub.
+  USHORT                        Reserved4[2];               ///< Reserved
+  UCHAR                         Reserved5;                  ///< Reserved
+  USHORT                        Reserved6;                  ///< Reserved
+  USHORT                        usFormatID;                 ///< Format ID
+  USHORT                        Reserved7[1];               ///< Reserved
+  USHORT                        usExtendendedHeaderOffset;  ///< Extended header offset
+} ATOM_PPLIB_POWERPLAYTABLE3;
+
+#pragma pack (pop)
+
+
+AGESA_STATUS
+GfxPowerPlayBuildTable (
+     OUT  VOID                          *Buffer,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
new file mode 100644
index 0000000000..a01e6e7790
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
@@ -0,0 +1,225 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Supporting services to collect discrete GFX card info
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GfxCardInfo.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if GFX controller fused off
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Gfx controller present and available
+ */
+BOOLEAN
+GfxLibIsControllerPresent (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Gfx SSID Registers
+ *
+ *
+ *
+ * @param[in] Gfx           Pointer to global GFX configuration
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxInitSsid (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  AGESA_STATUS    Status;
+  UINT32          TempData;
+  PCI_ADDR        IgpuAddress;
+  PCI_ADDR        HdaudioAddress;
+
+  Status = AGESA_SUCCESS;
+  TempData = 0;
+
+  IgpuAddress = Gfx->GfxPciAddress;
+  HdaudioAddress = Gfx->GfxPciAddress;
+  HdaudioAddress.Address.Function = 1;
+
+  // Set SSID for internal GPU
+  if (UserOptions.CfgGnbIGPUSSID != 0) {
+    GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx));
+  } else {
+    GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx));
+    GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx));
+  }
+
+  // Set SSID for internal HD Audio
+  if (UserOptions.CfgGnbHDAudioSSID != 0) {
+    GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx));
+  } else {
+    GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx));
+    GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx));
+  }
+
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy memory content to FB
+ *
+ *
+ * @param[in] Source       Pointer to source
+ * @param[in] FbOffset     FB offset
+ * @param[in] Length       The length to copy
+ * @param[in] Gfx          Pointer to global GFX configuration
+ *
+ */
+VOID
+GfxLibCopyMemToFb (
+  IN     VOID                   *Source,
+  IN     UINT32                  FbOffset,
+  IN     UINT32                  Length,
+  IN     GFX_PLATFORM_CONFIG    *Gfx
+  )
+{
+  GMMx00_STRUCT GMMx00;
+  GMMx04_STRUCT GMMx04;
+  UINT32        Index;
+  for (Index = 0; Index < Length; Index = Index + 4 ) {
+    GMMx00.Value = 0x80000000 | (FbOffset + Index);
+    GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index);
+    GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &GMMx00.Value, GnbLibGetHeader (Gfx));
+    GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, &GMMx04.Value, GnbLibGetHeader (Gfx));
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set iGpu VGA mode
+ *
+ *
+ * @param[in] Gfx          Pointer to global GFX configuration
+ *
+ */
+VOID
+GfxLibSetiGpuVgaMode (
+  IN     GFX_PLATFORM_CONFIG    *Gfx
+  )
+{
+  GnbLibPciIndirectRMW (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32) ~D0F0x64_x1D_VgaEn_MASK,
+    ((Gfx->iGpuVgaMode == iGpuVgaAdapter) ? 1 : 0) << D0F0x64_x1D_VgaEn_OFFSET,
+    GnbLibGetHeader (Gfx)
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h
new file mode 100644
index 0000000000..eb68a44d85
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Gfx Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GNBGFXINITLIBV1_H_
+#define _GNBGFXINITLIBV1_H_
+
+#include "GnbPcie.h"
+#include "GnbGfx.h"
+#include "GfxEnumConnectors.h"
+#include "GfxPowerPlayTable.h"
+#include "GfxCardInfo.h"
+
+BOOLEAN
+GfxLibIsControllerPresent (
+  IN      AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+AGESA_STATUS
+GfxInitSsid (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+
+VOID
+GfxLibCopyMemToFb (
+  IN     VOID                         *Source,
+  IN     UINT32                       FbOffset,
+  IN     UINT32                       Length,
+  IN     GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+VOID
+GfxLibSetiGpuVgaMode (
+  IN     GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
new file mode 100644
index 0000000000..037eadd02a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
@@ -0,0 +1,493 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbHandleLib.h"
+#include  "GnbTimerLib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA      GfxEnvInitTableTN[];
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Shut Down Disabled SIMDs
+ *
+ * @param[in] Property        GNB property
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxShutDownDisabledSimdsTN (
+  IN      UINT32                Property,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1006_STRUCT  ex1006 ;
+  ex1009_STRUCT   ex1009;
+  D0F0xBC_xE03002F8_STRUCT  D0F0xBC_xE03002F8;
+  D0F0xBC_xE03002FC_STRUCT  D0F0xBC_xE03002FC;
+  D0F0xBC_xE0300054_STRUCT  GfxChainPgfsmConfig;
+  UINT8                     n;
+  UINT32                    Mask;
+  CPU_LOGICAL_ID            LogicalId;
+  GNB_HANDLE                *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Enter\n");
+
+  GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Gfx));
+
+  GfxChainPgfsmConfig.Value = 0;
+  GfxChainPgfsmConfig.Field.PowerDown = 1;
+  GfxChainPgfsmConfig.Field.P2Select = 1;
+  GfxChainPgfsmConfig.Field.FsmAddr = 0xFF;
+
+  //Step 1: Read fuse to see which SIMD(s) have been disabled
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx));
+
+  //Step 2: Check which SIMD has been disabled
+  for (n = 0; n < 6; n++) {
+    if (((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) || ((ex1006.Field.ex1006_0  >> n) & 0x1)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Disable SIMD %d\n", n);
+      //Step 3: Make sure PGFSM has been programmed in GFX Power Island.
+      //Step 4: Make sure SCLK frequency is below 400Mhz
+      //Step 5: Enable PGFSM clock
+      GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+      ex1009.Value |= (0x1 << (0  + n));
+      GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+      //Step 6
+      GnbRegisterWriteTN (TYPE_D0F0xBC, (D0F0xBC_xE0300054_ADDRESS + (n * 0x1C)), &GfxChainPgfsmConfig.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+      //Step 7
+      Mask = (UINT32) (0x1F << (n * 5));
+      do {
+        GnbRegisterReadTN (D0F0xBC_xE03002F8_TYPE, D0F0xBC_xE03002F8_ADDRESS, &D0F0xBC_xE03002F8.Value, 0, GnbLibGetHeader (Gfx));
+      } while ((D0F0xBC_xE03002F8.Value & Mask )!= 0);
+      //Step 8: Restore previous SCLK divider
+      if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
+        do {
+          GnbRegisterReadTN (D0F0xBC_xE03002FC_TYPE, D0F0xBC_xE03002FC_ADDRESS, &D0F0xBC_xE03002FC.Value, 0, GnbLibGetHeader (Gfx));
+        } while ((D0F0xBC_xE03002FC.Value & Mask )!= Mask);
+      } else {
+      }
+      //Step 10: Turn off PGFSM clock
+      GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+      ex1009.Value &= (~ (UINT64) (0x1 << (0  + n)));
+      GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Shut Down Disabled SIMDs
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxShutDownDisabledRbsTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1006_STRUCT  ex1006 ;
+  D0F0xBC_xE0003024_STRUCT  D0F0xBC_xE0003024;
+  D0F0xBC_xE03000FC_STRUCT  D0F0xBC_xE03000FC;
+  D0F0xBC_xE0300100_STRUCT  D0F0xBC_xE0300100;
+  ex1009_STRUCT   ex1009 ;
+  D0F0xBC_xE03002F4_STRUCT  D0F0xBC_xE03002F4;
+  D0F0xBC_xE03002E4_STRUCT  D0F0xBC_xE03002E4;
+  UINT8                     i;
+  UINT8                     RbNumber;
+  UINT32                    Mask1;
+  UINT32                    Mask2;
+
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.WriteOp = 1;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Enter\n");
+
+  //Step 1: Read fuse to see which SIMD(s) have been disabled
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx));
+
+  //Step 2: Power down disabled RB
+  if (ex1006.Field.ex1006_1  == 0x1) {
+    RbNumber = 0;
+    Mask1 = 0x3FFFA;
+    Mask2 = 0x5;
+  } else if (ex1006.Field.ex1006_1  == 0x2) {
+    RbNumber = 1;
+    Mask1 = 0x3FFF5;
+    Mask2 = 0xA;
+  } else {
+    return AGESA_SUCCESS;
+  }
+  //Step 3: Enable PGFSM commands during reset
+  GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE0003024.Value |= 0x1;
+  GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 4: Make sure PGFSM has been programmed before sending power down command.
+  //CB0 = 0, DB0 = 2, CB1 = 1, DB1 = 3
+  for (i = RbNumber; i < 4; i += 2) {
+    D0F0xBC_xE0300100.Value = (5 << 16 ) | (4 << 8 ) | (10 << 0 ); //reg0
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.FsmAddr = i;
+    D0F0xBC_xE03000FC.Field.RegAddr = 2 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+    D0F0xBC_xE0300100.Value = (50 << 0 ) | (50 << 12 ); //reg1
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.RegAddr = 3 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+    D0F0xBC_xE0300100.Value = 0; //control
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.RegAddr = 1 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+  }
+  //Step 5: Make sure SCLK frequency is below 400Mhz
+  //Step 6: Enable PGFSM clock
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+  ex1009.Field.ex1009_1  = 1;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 7
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.PowerDown = 1;
+  D0F0xBC_xE03000FC.Field.P1Select = 1;
+  D0F0xBC_xE03000FC.Field.P2Select = 1;
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 8
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 9: Wait for isolation to be asserted for RB0/RB1
+  do {
+    GnbRegisterReadTN (D0F0xBC_xE03002F4_TYPE, D0F0xBC_xE03002F4_ADDRESS, &D0F0xBC_xE03002F4.Value, 0, GnbLibGetHeader (Gfx));
+  } while ((D0F0xBC_xE03002F4.Value & Mask1 )!= 0);
+  //Step 10: Restore previous SCLK divider
+  //Step 11: Wait for PSO daughter to be asserted for RB0/RB1
+  do {
+    GnbRegisterReadTN (D0F0xBC_xE03002E4_TYPE, D0F0xBC_xE03002E4_ADDRESS, &D0F0xBC_xE03002E4.Value, 0, GnbLibGetHeader (Gfx));
+  } while ((D0F0xBC_xE03002E4.Value & Mask2 )!= Mask2);
+
+  //Step 12: Set PGFSM power up override bits so SMU will not power up disabled RB
+  D0F0xBC_xE0300100.Value = 0x3 << 11;
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.RegAddr = 1 ;
+  GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 13: Turn off PGFSM clock
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+  ex1009.Field.ex1009_1  = 1;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 14: Disable PGFSM commands during reset
+  GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE0003024.Value &= 0xFFFFFFFE;
+  GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Exit\n");
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GFX straps.
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxEnvInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D0F0x64_x1C_STRUCT  D0F0x64_x1C;
+  D0F0x64_x1D_STRUCT  D0F0x64_x1D;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Enter\n");
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0;
+  D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0;
+
+  D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1;
+  D0F0x64_x1C.Field.RcieEn = 0x1;
+
+  D0F0x64_x1D.Field.VgaEn = 0x1;
+
+  D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio;
+  D0F0x64_x1C.Field.F0En = 0x1;
+  D0F0x64_x1C.Field.RegApSize = 0x1;
+
+  if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x1;
+  } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x0;
+  } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x2;
+  } else {
+    D0F0x64_x1C.Field.MemApSize = 0x3;
+  }
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.WriteDis = 0x1;
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Exit\n");
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Env Post.
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS
+  */
+
+
+AGESA_STATUS
+GfxEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  GNB_HANDLE            *GnbHandle;
+  UINT32                Property;
+  BOOLEAN               ShutDownDisabledSimd;
+  BOOLEAN               ShutDownDisabledRb;
+  UINT8                 SclkDid;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Property = TABLE_PROPERTY_DEAFULT;
+  ShutDownDisabledSimd = GnbBuildOptions.CfgUnusedSimdPowerGatingEnable;
+  ShutDownDisabledRb = GnbBuildOptions.CfgUnusedRbPowerGatingEnable;
+
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnvInitTN (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      ASSERT (Status == AGESA_SUCCESS);
+    } else {
+      GfxFmDisableController (StdHeader);
+      Property |= TABLE_PROPERTY_IGFX_DISABLED;
+    }
+  } else {
+    GfxFmDisableController (StdHeader);
+    Property |= TABLE_PROPERTY_IGFX_DISABLED;
+  }
+  //
+  // Set sclk to 100Mhz
+  //
+  SclkDid = GfxRequestSclkTNS3Save (
+              GfxLibCalculateDidTN (98 * 100, StdHeader),
+              StdHeader
+              );
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GfxEnvInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  if (ShutDownDisabledSimd == TRUE) {
+    GfxShutDownDisabledSimdsTN (Property, Gfx);
+  }
+
+  if ((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) {
+    if (ShutDownDisabledRb == TRUE) {
+      GfxShutDownDisabledRbsTN (Gfx);
+    }
+  }
+  //
+  // Restore Sclk
+  //
+  GfxRequestSclkTNS3Save (
+    SclkDid,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
new file mode 100644
index 0000000000..1cd96d3d83
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
@@ -0,0 +1,595 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64152 $   @e \$Date: 2012-01-16 21:38:07 -0600 (Mon, 16 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbRegisterAccTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbRegistersTN.h"
+#include  "GfxLibTN.h"
+#include  "GfxGmcInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [];
+extern GNB_TABLE ROMDATA GfxGmcInitTableTN [];
+extern GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [];
+
+
+#define GNB_GFX_DRAM_CH_0_PRESENT 1
+#define GNB_GFX_DRAM_CH_1_PRESENT 2
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+DCT_REGISTER_ENTRY DctRegisterTable [] = {
+  {
+    TYPE_D18F2_dct0,
+    D18F2x94_dct0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct0)
+  },
+  {
+    TYPE_D18F2_dct1,
+    D18F2x94_dct1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct1)
+  },
+  {
+    TYPE_D18F2_dct0,
+    D18F2x2E0_dct0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct0)
+  },
+  {
+    TYPE_D18F2_dct1,
+    D18F2x2E0_dct1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x200_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x200_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x200_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x200_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x204_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x204_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x204_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x204_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x22C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x22C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x22C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x22C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x21C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x21C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x21C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x21C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x20C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x20C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x20C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x20C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp1)
+  }
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Fb location
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeFbLocationTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx2024_STRUCT   GMMx2024;
+  GMMx2068_STRUCT   GMMx2068;
+  GMMx2C04_STRUCT   GMMx2C04;
+  GMMx5428_STRUCT   GMMx5428;
+  UINT64            FBBase;
+  UINT64            FBTop;
+  FBBase = 0x0F00000000;
+  FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1;
+  GMMx2024.Value = 0;
+  GMMx2C04.Value = 0;
+  GMMx2024.Field.FB_BASE = (UINT16) (FBBase >> 24);
+  GMMx2024.Field.FB_TOP = (UINT16) (FBTop >> 24);
+  GMMx2068.Field.FB_OFFSET = (UINT32) (Gfx->UmaInfo.UmaBase >> 22);
+  GMMx2C04.Field.NONSURF_BASE = (UINT32) (FBBase >> 8);
+  GMMx5428.Field.CONFIG_MEMSIZE = Gfx->UmaInfo.UmaSize >> 20;
+  GnbRegisterWriteTN (GMMx2024_TYPE, GMMx2024_ADDRESS, &GMMx2024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx2068_TYPE, GMMx2068_ADDRESS, &GMMx2068.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx2C04_TYPE, GMMx2C04_ADDRESS, &GMMx2C04.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Sequencer model info
+ *
+ *
+ * @param[out] DctChannelInfo  Various DCT/GMM info
+ * @param[in]  Gfx             Pointer to global GFX configuration
+ */
+
+STATIC VOID
+GfxGmcDctMemoryChannelInfoTN (
+     OUT   DCT_CHANNEL_INFO              *DctChannelInfo,
+  IN       GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+
+  UINT32       Index;
+  UINT32       Value;
+
+  for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) {
+    GnbRegisterReadTN (
+      DctRegisterTable[Index].RegisterSpaceType,
+      DctRegisterTable[Index].Address,
+      &Value,
+      0,
+      GnbLibGetHeader (Gfx)
+    );
+    *(UINT32 *)((UINT8 *) DctChannelInfo + DctRegisterTable[Index].DctChannelInfoTableOffset) = Value;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize sequencer model
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeSequencerTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+
+  UINT32                    memps0_freq;
+  UINT32                    memps1_freq;
+  UINT32                    scale_mp0;
+  UINT32                    scale_mp1;
+  UINT8                     DramChannelPresent;
+  ex1047_STRUCT      ex1047      ;
+  ex1048_STRUCT          ex1048 ;
+  ex1060_STRUCT        ex1060    ;
+  ex1061_STRUCT        ex1061    ;
+  ex1062_STRUCT        ex1062    ;
+  DCT_CHANNEL_INFO          DctChannel;
+  D18F5x170_STRUCT          D18F5x170;
+  ex1012_STRUCT         ex1012  ;
+  ex1034_STRUCT        ex1034    ;
+
+  GfxGmcDctMemoryChannelInfoTN (&DctChannel, Gfx);
+
+  DramChannelPresent = 0;
+  if (!DctChannel.D18F2x94_dct1.Field.DisDramInterface) {
+    DramChannelPresent |= GNB_GFX_DRAM_CH_1_PRESENT;
+  }
+
+  if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface) {
+    //if (channel 0 present)
+    //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[0]>[4:0] encoding
+    //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[0]>[28:24] encoding
+    DramChannelPresent |= GNB_GFX_DRAM_CH_0_PRESENT;
+    memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct0.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+    memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+  } else {
+    //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[1]>[4:0] encoding
+    //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[1]>[28:24] encoding
+    memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct1.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+    memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct1.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+  }
+
+  GnbRegisterReadTN (D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx));
+  if (D18F5x170.Field.MemPstateDis == 1) {
+    memps1_freq = memps0_freq;
+  }
+
+  //scale_mp0 = sclk_max_freq / memps0_freq
+  //scale_mp1 = sclk_max_freq / memps1_freq
+  //Multiply it by 100 to avoid dealing with floating point values
+  scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq;
+  scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq;
+
+  GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x27f0 , &ex1060.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx));
+
+  if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
+    ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd),
+                                     (DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp),
+                                    (DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO),
+                                     (DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd),
+                                     (DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp),
+                                    (DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO),
+                                     (DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100;
+
+  } else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) {
+    ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct0_mp0.Field.Trcd * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct0_mp0.Field.Trc * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct0_mp0.Field.Trp * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct0_mp1.Field.Trcd * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct0_mp1.Field.Trc * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct0_mp1.Field.Trp * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100;
+
+  } else {
+    ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct1_mp0.Field.Trcd * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct1_mp0.Field.Trc * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct1_mp0.Field.Trp * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct1_mp1.Field.Trcd * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct1_mp1.Field.Trc * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct1_mp1.Field.Trp * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100;
+  }
+
+  GnbRegisterWriteTN (TYPE_GMM , 0x2774 , &ex1047.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2778 , &ex1048.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x27f0 , &ex1060.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x27fc , &ex1061.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  ex1062.Field.ex1062_0  = GfxLibGetNumberOfSclkPerDramBurst (scale_mp0, GnbLibGetHeader (Gfx));
+  ex1062.Field.ex1062_1  = GfxLibGetNumberOfSclkPerDramBurst (scale_mp1, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2808 , &ex1062.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+
+  //MC Performance settings base on memory channel configuration
+  //If 1 channel
+  ex1012.Value = 0x210;
+  ex1034.Value = 0x3;
+  if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
+    //If 2 channels
+    ex1012.Value = 0x1210;
+    ex1034.Value = 0xC3;
+  }
+  GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+STATIC VOID
+GfxGmcSecureGarlicAccessTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1064_STRUCT    ex1064 ;
+  ex1065_STRUCT    ex1065 ;
+  GMMx287C_STRUCT   GMMx287C;
+
+  ex1064.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
+  GnbRegisterWriteTN (TYPE_GMM , 0x2868 , &ex1064.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  ex1065.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1);
+  GnbRegisterWriteTN (TYPE_GMM , 0x286c , &ex1065.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  // Areag FB - 32K reserved by VBIOS for SBIOS to use
+  GMMx287C.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12);
+  GnbRegisterWriteTN (GMMx287C_TYPE, GMMx287C_ADDRESS, &GMMx287C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize C6 aperture location
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeC6LocationTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D18F2x118_STRUCT    D18F2x118;
+  D18F1x44_STRUCT     D18F1x44;
+  GMMx2870_STRUCT     GMMx2870;
+  GMMx2874_STRUCT     GMMx2874;
+
+  // From D18F1x[144:140,44:40] DRAM Base/Limit,
+  // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}.
+  GnbRegisterReadTN (D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx));
+  //
+  // base 39:20, base = Dram Limit + 1
+  // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1)
+  // Node DRAM     D18F1x[144:140,44:40]    CC6DRAMRange         D18F4x128   D18F1x120 D18F1x124
+  //    0 256MB    0MB ~ 240 MB - 1        240 MB ~ 256 MB - 1     0           0 MB,    256 MB - 1
+  //
+
+  // base 39:20
+  GMMx2870.Value = ((D18F1x44.Field.DramLimit_39_24_ + 1) << 4);
+  // top 39:20
+  GMMx2874.Value = (((D18F1x44.Field.DramLimit_39_24_ + 1) << 24) + (16 * 0x100000) - 1) >> 20;
+
+  // Check C6 enable,  D18F2x118[CC6SaveEn]
+  GnbRegisterReadTN (TYPE_D18F2 , 0x118 , &D18F2x118.Value, 0, GnbLibGetHeader (Gfx));
+
+  if (D18F2x118.Field.CC6SaveEn) {
+
+    GnbRegisterWriteTN (GMMx2874_TYPE, GMMx2874_ADDRESS, &GMMx2874.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbRegisterWriteTN (GMMx2870_TYPE, GMMx2870_ADDRESS, &GMMx2870.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GMC
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+
+AGESA_STATUS
+GfxGmcInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx28D8_STRUCT   GMMx28D8;
+  ex1017_STRUCT    ex1017 ;
+  GNB_HANDLE        *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Enter\n");
+   GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
+   ASSERT (GnbHandle != NULL);
+   GnbProcessTable (
+     GnbHandle,
+     GfxGmcColockGatingDisableTN,
+     0,
+     GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+     GnbLibGetHeader (Gfx)
+     );
+   GfxGmcInitializeSequencerTN (Gfx);
+   GfxGmcInitializeFbLocationTN (Gfx);
+   GfxGmcSecureGarlicAccessTN (Gfx);
+   GfxGmcInitializeC6LocationTN (Gfx);
+   GnbProcessTable (
+     GnbHandle,
+     GfxGmcInitTableTN,
+     0,
+     GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+     GnbLibGetHeader (Gfx)
+     );
+   if (Gfx->GmcClockGating) {
+     GnbProcessTable (
+       GnbHandle,
+       GfxGmcColockGatingEnableTN,
+       0,
+       GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+       GnbLibGetHeader (Gfx)
+       );
+   }
+   if (Gfx->UmaSteering == excel993 ) {
+     ex1017.Value = 0x2;
+     GnbRegisterWriteTN (TYPE_GMM , 0x206c , &ex1017.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+   }
+   IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx));
+   if (Gfx->GmcLockRegisters) {
+     GnbRegisterReadTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, 0, GnbLibGetHeader (Gfx));
+     GMMx28D8.Field.CRITICAL_REGS_LOCK = 1;
+     GnbRegisterWriteTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+   }
+   if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) {
+   }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Exit\n");
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h
new file mode 100644
index 0000000000..91de2f7475
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXGMCINITTN_H_
+#define _GFXGMCINITTN_H_
+
+#include  "GnbRegistersTN.h"
+
+AGESA_STATUS
+GfxGmcInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+#pragma pack (push, 1)
+
+/// DCT channel information
+typedef struct {
+  D18F2x94_dct0_STRUCT      D18F2x94_dct0;       ///< Register 0x94
+  D18F2x94_dct1_STRUCT      D18F2x94_dct1;       ///< Register 0x94
+  D18F2x2E0_dct0_STRUCT     D18F2x2E0_dct0;      ///< Register 0x2E0
+  D18F2x2E0_dct1_STRUCT     D18F2x2E0_dct1;      ///< Register 0x2E0
+  D18F2x200_dct0_mp0_STRUCT D18F2x200_dct0_mp0;  ///< Register 0x200
+  D18F2x200_dct0_mp1_STRUCT D18F2x200_dct0_mp1;  ///< Register 0x200
+  D18F2x200_dct1_mp0_STRUCT D18F2x200_dct1_mp0;  ///< Register 0x200
+  D18F2x200_dct1_mp1_STRUCT D18F2x200_dct1_mp1;  ///< Register 0x200
+  D18F2x204_dct0_mp0_STRUCT D18F2x204_dct0_mp0;  ///< Register 0x204
+  D18F2x204_dct0_mp1_STRUCT D18F2x204_dct0_mp1;  ///< Register 0x204
+  D18F2x204_dct1_mp0_STRUCT D18F2x204_dct1_mp0;  ///< Register 0x204
+  D18F2x204_dct1_mp1_STRUCT D18F2x204_dct1_mp1;  ///< Register 0x204
+  D18F2x22C_dct0_mp0_STRUCT D18F2x22C_dct0_mp0;  ///< Register 0x22C
+  D18F2x22C_dct0_mp1_STRUCT D18F2x22C_dct0_mp1;  ///< Register 0x22C
+  D18F2x22C_dct1_mp0_STRUCT D18F2x22C_dct1_mp0;  ///< Register 0x22C
+  D18F2x22C_dct1_mp1_STRUCT D18F2x22C_dct1_mp1;  ///< Register 0x22C
+  D18F2x21C_dct0_mp0_STRUCT D18F2x21C_dct0_mp0;  ///< Register 0x21C
+  D18F2x21C_dct0_mp1_STRUCT D18F2x21C_dct0_mp1;  ///< Register 0x21C
+  D18F2x21C_dct1_mp0_STRUCT D18F2x21C_dct1_mp0;  ///< Register 0x21C
+  D18F2x21C_dct1_mp1_STRUCT D18F2x21C_dct1_mp1;  ///< Register 0x21C
+  D18F2x20C_dct0_mp0_STRUCT D18F2x20C_dct0_mp0;  ///< Register 0x20C
+  D18F2x20C_dct0_mp1_STRUCT D18F2x20C_dct0_mp1;  ///< Register 0x20C
+  D18F2x20C_dct1_mp0_STRUCT D18F2x20C_dct1_mp0;  ///< Register 0x20C
+  D18F2x20C_dct1_mp1_STRUCT D18F2x20C_dct1_mp1;  ///< Register 0x20C
+} DCT_CHANNEL_INFO;
+
+/// DCT_CHANNEL_INFO field entry
+typedef struct {
+  UINT8                 RegisterSpaceType;              ///< Register type
+  UINT32                Address;                        ///< Register address
+  UINT16                DctChannelInfoTableOffset;      ///< destination offset in DCT_CHANNEL_INFO table
+} DCT_REGISTER_ENTRY;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
new file mode 100644
index 0000000000..15c0109566
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
@@ -0,0 +1,922 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64730 $   @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "GeneralServices.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GfxConfigLib.h"
+#include  "GfxLibTN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#define GFX_REFCLK                        100     // (in MHz) Reference clock is 100 MHz
+#define GFX_NCLK_MIN                      700     // (in MHz) Minimum value for NCLK is 700 MHz
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxIntInfoTableInterfaceTN (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+CONST UINT8  DdiLaneConfigArrayTN [][4] = {
+  {31, 24, 1, 0},
+  {24, 31, 0, 1},
+  {24, 27, 0, 0},
+  {27, 24, 0, 0},
+  {28, 31, 1, 1},
+  {31, 28, 1, 1},
+  {32, 38, 2, 2},
+  {32, 35, 2, 2},
+  {35, 32, 2, 2},
+  {8 , 15, 3, 3},
+  {15, 8 , 3, 3},
+  {12, 15, 3, 3},
+  {15, 12, 3, 3},
+  {16, 19, 4, 4},
+  {19, 16, 4, 4},
+  {16, 23, 4, 5},
+  {23, 16, 5, 4},
+  {20, 23, 5, 5},
+  {23, 20, 5, 5},
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init TN Support for eDP to Lvds translators
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegrateducEDPToLVDSRxIdCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8    *uceDPToLVDSRxId;
+  uceDPToLVDSRxId = (UINT8*) Buffer;
+  // APU output DP signal to a 3rd party DP translator chip (Analogix, Parade etc),
+  // the chip is handled by the 3rd party DP Rx firmware and it does not require the AMD SW to have a special
+  // initialize/enable/disable sequence to control this chip, the AMD SW just follows the eDP spec
+  // to enable the LVDS panel through this chip.
+
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) {
+    *uceDPToLVDSRxId = eDP_TO_LVDS_COMMON_ID;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found 3rd party common EDPToLvds Connector\n");
+  }
+  // APU output DP signal to a 3rd party DP translator chip which requires a AMD SW one time initialization
+  // to the chip based on the LVDS panel parameters ( such as power sequence time and panel SS parameter etc ).
+  // After that, the AMD SW does not need any specific enable/disable sequences to control this chip and just
+  // follows the eDP spec. to control the panel.
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) {
+    *uceDPToLVDSRxId = eDP_TO_LVDS_REALTEK_ID;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found Realtec EDPToLvds Connector\n");
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN Nb p-State MemclkFreq
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillNbPstateMemclkFreqTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F2x94_dct0_STRUCT            D18F2x94;
+  D18F2x2E0_dct0_STRUCT           D18F2x2E0;
+  D18F5x160_STRUCT                NbPstate;
+  UINT8                           i;
+  UINT8                           Channel;
+  ULONG                           memps0_freq;
+  ULONG                           memps1_freq;
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x94_dct0_TYPE : D18F2x94_dct1_TYPE),
+    ((Channel == 0) ? D18F2x94_dct0_ADDRESS : D18F2x94_dct1_ADDRESS),
+    &D18F2x94.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x2E0_dct0_TYPE : D18F2x2E0_dct1_TYPE),
+    ((Channel == 0) ? D18F2x2E0_dct0_ADDRESS : D18F2x2E0_dct1_ADDRESS),
+    &D18F2x2E0.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  memps0_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+  memps1_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+
+  for (i = 0; i < 4; i++) {
+    NbPstate.Value = 0;
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      (D18F5x160_ADDRESS + (i * 4)),
+      &NbPstate.Value,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    if (NbPstate.Field.NbPstateEn == 1) {
+      IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq;
+    }
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN HTC Data
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillHtcDataTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F3x64_STRUCT  D18F3x64;
+
+  GnbRegisterReadTN (
+    D18F3x64_TYPE,
+    D18F3x64_ADDRESS,
+    &D18F3x64.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  if (D18F3x64.Field.HtcEn == 1) {
+    IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
+    IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
+  } else {
+    IntegratedInfoTable->ucHtcTmpLmt = 0;
+    IntegratedInfoTable->ucHtcHystLmt = 0;
+  }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get TN CSR phy self refresh power down mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    CsrPhySrPllPdMode
+ */
+STATIC UINT32
+GfxLibGetMemPhyPllPdModeTN (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2xA8_dct0_STRUCT     D18F2xA8;
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2xA8_dct0_TYPE : D18F2xA8_dct1_TYPE),
+    ((Channel == 0) ? D18F2xA8_dct0_ADDRESS : D18F2xA8_dct1_ADDRESS),
+    &D18F2xA8.Value,
+    0,
+    StdHeader
+  );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "MemPhyPllPdMode : %x\n", D18F2xA8.Field.MemPhyPllPdMode);
+  return  D18F2xA8.Field.MemPhyPllPdMode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get TN disable DLL shutdown in self-refresh mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    DisDllShutdownSR
+ */
+STATIC UINT32
+GfxLibGetDisDllShutdownSRTN (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2x90_dct0_STRUCT D18F2x90;
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x90_dct0_TYPE : D18F2x90_dct1_TYPE),
+    ((Channel == 0) ? D18F2x90_dct0_ADDRESS : D18F2x90_dct1_ADDRESS),
+    &D18F2x90.Value,
+    0,
+    StdHeader
+  );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "DisDllShutdownSR : %x\n", D18F2x90.Field.DisDllShutdownSR);
+  return  D18F2x90.Field.DisDllShutdownSR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN NbPstateVid
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillNbPStateVidTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  //TN Register Mapping for D18F5x1[6C:60]
+  D18F5x160_STRUCT  NbPstate[4];
+  D0F0xBC_x1F428_STRUCT  D0F0xBC_x1F428;
+  UINT8             MinNclkIndex;
+  UINT8             i;
+
+  MinNclkIndex = 0;
+  IntegratedInfoTable->ucNBDPMEnable = 0;
+
+
+  GnbRegisterReadTN (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    &D0F0xBC_x1F428.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+  );
+  // Check if NbPstate enbale
+  if (D0F0xBC_x1F428.Field.EnableNbDpm == 1) {
+    //1: enable 0: not enable
+    IntegratedInfoTable->ucNBDPMEnable = 1;
+  }
+
+  for (i = 0; i < 4; i++) {
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      (D18F5x160_ADDRESS + (i * 4)),
+      &NbPstate[i].Value,
+      0,
+      GnbLibGetHeader (Gfx)
+    );
+    if (NbPstate[i].Field.NbPstateEn == 1) {
+      MinNclkIndex = i;
+    }
+    IntegratedInfoTable->ulNbpStateNClkFreq[i] = GfxLibGetNclkTN ((UINT8) NbPstate[i].Field.NbFid, (UINT8) NbPstate[i].Field.NbDid);
+  }
+  IntegratedInfoTable->usNBP0Voltage = (USHORT) ((NbPstate[0].Field.NbVid_7_ << 7) | NbPstate[0].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP1Voltage = (USHORT) ((NbPstate[1].Field.NbVid_7_ << 7) | NbPstate[1].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP2Voltage = (USHORT) ((NbPstate[2].Field.NbVid_7_ << 7) | NbPstate[2].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP3Voltage = (USHORT) ((NbPstate[3].Field.NbVid_7_ << 7) | NbPstate[3].Field.NbVid_6_0_);
+
+  IntegratedInfoTable->ulMinimumNClk = GfxLibGetNclkTN ((UINT8) NbPstate[MinNclkIndex].Field.NbFid, (UINT8) NbPstate[MinNclkIndex].Field.NbDid);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize display path for given engine
+ *
+ *
+ *
+ * @param[in]   Engine            Engine configuration info
+ * @param[out]  DisplayPathList   Display path list
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ */
+
+AGESA_STATUS
+GfxFmMapEngineToDisplayPath (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  AGESA_STATUS      Status;
+  UINT8             PrimaryDisplayPathId;
+  UINT8             SecondaryDisplayPathId;
+  UINTN             DisplayPathIndex;
+  PrimaryDisplayPathId = 0xff;
+  SecondaryDisplayPathId = 0xff;
+  for (DisplayPathIndex = 0; DisplayPathIndex <  (sizeof (DdiLaneConfigArrayTN) / 4); DisplayPathIndex++) {
+    if (DdiLaneConfigArrayTN[DisplayPathIndex][0] == Engine->EngineData.StartLane &&
+        DdiLaneConfigArrayTN[DisplayPathIndex][1] == Engine->EngineData.EndLane) {
+      PrimaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][2];
+      SecondaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][3];
+      break;
+    }
+  }
+  if (PrimaryDisplayPathId != 0xff) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
+    Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE;
+    GfxIntegratedCopyDisplayInfo (
+      Engine,
+      &DisplayPathList[PrimaryDisplayPathId],
+      (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL,
+      Gfx
+      );
+    Status = AGESA_SUCCESS;
+  } else {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Error!!! Map DDI lanes %d - %d to display path failed\n",
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane
+      );
+    PutEventLog (
+      AGESA_ERROR,
+      GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION,
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane,
+      0,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    Status = AGESA_ERROR;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy memory content to FB
+ *
+ *
+ * @param[in] SystemInfoTableV2Ptr    Pointer to integrated info table
+ * @param[in] Gfx                     Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxIntInfoTabablePostToFb (
+  IN       ATOM_FUSION_SYSTEM_INFO_V2     *SystemInfoTableV2Ptr,
+  IN       GFX_PLATFORM_CONFIG            *Gfx
+  )
+{
+  UINT32      Index;
+  UINT32      TableOffset;
+  UINT32      FbAddress;
+
+  TableOffset = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V2)) | 0x80000000;
+  for (Index = 0; Index < sizeof (ATOM_FUSION_SYSTEM_INFO_V2); Index = Index + 4 ) {
+    FbAddress = TableOffset + Index;
+    GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &FbAddress, GnbLibGetHeader (Gfx));
+    GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, (UINT8*) SystemInfoTableV2Ptr + Index, GnbLibGetHeader (Gfx));
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Dispclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxIntInfoTableInitDispclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN   Index;
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->DisplclkDid[Index] != 0) {
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxFmCalculateClock (
+                                                                             PpFuseArray->DisplclkDid[Index],
+                                                                             GnbLibGetHeader (Gfx)
+                                                                             );
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index;
+    }
+  }
+  IntegratedInfoTable->ucDPMState0VclkFid = PpFuseArray->VclkDid[0];
+  IntegratedInfoTable->ucDPMState1VclkFid = PpFuseArray->VclkDid[1];
+  IntegratedInfoTable->ucDPMState2VclkFid = PpFuseArray->VclkDid[2];
+  IntegratedInfoTable->ucDPMState3VclkFid = PpFuseArray->VclkDid[3];
+  IntegratedInfoTable->ucDPMState0DclkFid = PpFuseArray->DclkDid[0];
+  IntegratedInfoTable->ucDPMState1DclkFid = PpFuseArray->DclkDid[1];
+  IntegratedInfoTable->ucDPMState2DclkFid = PpFuseArray->DclkDid[2];
+  IntegratedInfoTable->ucDPMState3DclkFid = PpFuseArray->DclkDid[3];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Sclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxIntInfoTableInitSclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN                       Index;
+  UINTN                       AvailSclkIndex;
+  ATOM_AVAILABLE_SCLK_LIST    *AvailSclkList;
+  BOOLEAN                     Sorting;
+  AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0];
+
+  AvailSclkIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+    if (PpFuseArray->SclkDpmDid[Index] != 0) {
+      AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], GnbLibGetHeader (Gfx));
+      AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index];
+      AvailSclkList[AvailSclkIndex].usVoltageID = PpFuseArray->SclkVid[PpFuseArray->SclkDpmVid[Index]];
+      AvailSclkIndex++;
+    }
+  }
+  //Sort by VoltageIndex & ulSupportedSCLK
+  if (AvailSclkIndex > 1) {
+    do {
+      Sorting = FALSE;
+      for (Index = 0; Index < (AvailSclkIndex - 1); Index++) {
+        ATOM_AVAILABLE_SCLK_LIST  Temp;
+        BOOLEAN                   Exchange;
+        Exchange = FALSE;
+        if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) {
+          Exchange = TRUE;
+        }
+        if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) &&
+            (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) {
+          Exchange = TRUE;
+        }
+        if (Exchange) {
+          Sorting = TRUE;
+          LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+        }
+      }
+    } while (Sorting);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Read GFX PGFSM register
+ *
+ *
+ * @param[in]  RegisterAddress     Index of PGFSM register
+ * @param[out] Value               Pointer to value
+ * @param[in]  StdHeader           Standard configuration header
+ */
+
+STATIC VOID
+GfxPgfsmRegisterReadTN (
+  IN       UINT32                 RegisterAddress,
+     OUT   UINT32                 *Value,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32      RegisterWriteValue;
+  UINT32      RegisterReadValue;
+  RegisterWriteValue = (RegisterAddress << D0F0xBC_xE0300000_RegAddr_OFFSET) +
+                       (1 << D0F0xBC_xE0300000_ReadOp_OFFSET) +
+                       (0 << D0F0xBC_xE0300000_FsmAddr_OFFSET);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Read PGFSM Register %d\n", RegisterAddress);
+  GnbRegisterWriteTN (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    &RegisterWriteValue,
+    0,
+    StdHeader);
+  do {
+    GnbRegisterReadTN (
+      D0F0xBC_xE0300008_TYPE,
+      D0F0xBC_xE0300008_ADDRESS,
+      &RegisterReadValue,
+      0,
+      StdHeader);
+  } while ((RegisterReadValue & D0F0xBC_xE0300008_ReadValid_MASK) == 0);
+  *Value = RegisterReadValue & D0F0xBC_xE0300008_ReadValue_MASK;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Calculate ulGMCRestoreResetTime
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxCalculateRestoreResetTimeTN (
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx,
+  IN       PP_FUSE_ARRAY                    *PpFuseArray
+  )
+{
+  UINT8      MaxDid;
+  ULONG      FreqSclk;
+  UINTN      Index;
+  UINT32     TSclk;
+  UINT32     TRefClk;
+  UINT32     TNclkHalf;
+  UINT32     PgfsmDelayReg0;
+  UINT32     PgfsmDelayReg1;
+  UINT32     ResetTime;
+  UINT32     IsoTime;
+  UINT32     MemSd;
+  UINT32     MotherPso;
+  UINT32     DaughterPso;
+  UINT32     THandshake;
+  UINT32     TGmcSync;
+  UINT32     TPuCmd;
+  UINT32     TPgfsmCmdSerialization;
+  UINT32     TReset;
+  UINT32     TMoPso;
+  UINT32     TDaPso;
+  UINT32     TMemSd;
+  UINT32     TIso;
+  UINT32     TRegRestore;
+  UINT32     TPgfsmCleanUp;
+  UINT32     TGmcPu;
+  UINT32     TGmcPd;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Enter\n");
+  // Find FreqSclk = MIN of frequencies SclkDpmDid (0 to 4) and SclkThermDid
+  // First find the highest Did
+  MaxDid = PpFuseArray->SclkThermDid;
+  for (Index = 0; Index < 4; Index++) {
+    // Compare with SclkDpmDid[x] - These are stored in:
+    // IntegratedInfoTable-> sDISPCLK_Voltage[Index].ulMaximumSupportedCLK
+    MaxDid = MAX (MaxDid, PpFuseArray->SclkDpmDid[Index]);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid);
+  FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx));
+  // FreqSclk is in 10KHz units - need calculations in nS
+  // For accuracy, do calculations in .01nS, then convert at the end
+  TSclk = (100 * (1000000000 / 10000)) / FreqSclk;
+  // FreqRefClk frequency of reference clock
+  // Caclculate period in .01 nS
+  TRefClk = (100 * 1000) / GFX_REFCLK;
+  // FreqNclkHalf = half of Minimum NCLK value
+  // Calculate period in .01 nS
+  TNclkHalf = (100 * 1000) / (GFX_NCLK_MIN / 2);
+
+  // Read delay time values from PGFSM registers
+  GfxPgfsmRegisterReadTN (2 , &PgfsmDelayReg0, GnbLibGetHeader (Gfx));
+  GfxPgfsmRegisterReadTN (3 , &PgfsmDelayReg1, GnbLibGetHeader (Gfx));
+  ResetTime = (PgfsmDelayReg0 & 0x000000FF ) >> 0 ;
+  IsoTime = (PgfsmDelayReg0 & 0x0000FF00 ) >> 8 ;
+  MemSd = (PgfsmDelayReg0 & 0x00FF0000 ) >> 16 ;
+  MotherPso = (PgfsmDelayReg1 & 0x00000FFF ) >> 0 ;
+  DaughterPso = (PgfsmDelayReg1 & 0x00FFF000 ) >> 12 ;
+  IDS_HDT_CONSOLE (GNB_TRACE, "ResetTime = %d\n", ResetTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "IsoTime = %d\n", IsoTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "MemSd = %d\n", MemSd);
+  IDS_HDT_CONSOLE (GNB_TRACE, "MotherPso = %d\n", MotherPso);
+  IDS_HDT_CONSOLE (GNB_TRACE, "DaughterPso = %d\n", DaughterPso);
+
+  // Calculate various timing values required for the final calculation
+  // THandshake = 10*1/FreqNclkHalf
+  THandshake = 10 * TNclkHalf;
+  // TGmcSync = 2.5*(1/FreqRefclk+1/FreqSclk)
+  TGmcSync = (25 * (TRefClk + TSclk)) / 10;
+  // TPuCmd =9*1/FreqSclk
+  TPuCmd = 9 * TSclk;
+  // TPgfsmCmdSerialization = 82*1/FreqSclk
+  TPgfsmCmdSerialization = 82 * TSclk;
+  // TReset = (RESET_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TGmcSync
+  TReset = ((ResetTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TMoPso = (MOTHER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TMoPso = ((MotherPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TDaPso = (DAUGHTER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TDaPso = ((DaughterPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TMemSD = (MEM_SD+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TMemSd = ((MemSd + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TIso = (ISO_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TIso = ((IsoTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TRegRestore = 508*1/FreqSclk
+  TRegRestore = 508 * TSclk;
+  // TPgfsmCleanUp = 3*1/FreqSclk
+  TPgfsmCleanUp = 3 * TSclk;
+  // TGmcPu = TPUCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSD + TIso + TRegRestore
+  TGmcPu = TPuCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSd + TIso + TRegRestore;
+  // TGmcPd = THandshake + TPgfsmCmdSerialization + Tiso + TmemSD + TMoPso + TDaPso + TpgfsmCleanUp + 3*TReset
+  TGmcPd = THandshake + TPgfsmCmdSerialization + TIso + TMemSd + TMoPso + TDaPso + TPgfsmCleanUp + (3 * TReset);
+  // ulGMCRestoreResetTime = TGmcPu + TGmcPd
+  // All calculated times are in .01nS for accuracy.  We can now correct that.
+  // By adding 99 and dividing by 100, value is rounded up to next 1 nS
+  IntegratedInfoTable->ulGMCRestoreResetTime = (TGmcPd + TGmcPu + 99) / 100;
+  IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *
+ *
+ *
+ * @param[in] Gfx             Gfx configuration info
+ * @retval    AGESA_STATUS
+ */
+AGESA_STATUS
+STATIC
+GfxIntInfoTableInitTN (
+  IN      GFX_PLATFORM_CONFIG     *Gfx
+  )
+{
+  AGESA_STATUS                    Status;
+  AGESA_STATUS                    AgesaStatus;
+  ATOM_FUSION_SYSTEM_INFO_V2      SystemInfoTableV2;
+  PP_FUSE_ARRAY                   *PpFuseArray;
+  PCIe_PLATFORM_CONFIG            *Pcie;
+  ATOM_PPLIB_POWERPLAYTABLE3      *PpTable;
+  UINT8                           Channel;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n");
+  LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx));
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7);
+  ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512);
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7;
+  SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
+  SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
+  SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3;     //DDR3
+  SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100;    //Set default engine clock to 200MhZ
+  SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
+  SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
+  SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
+  //Locate PCIe configuration data to get definitions of display connectors
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
+  SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo);
+  SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx));
+
+  SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
+
+  SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
+  if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) {
+    SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429  = Gfx->gfxplmcfg0 ;
+    IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 );
+  }
+
+  SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
+
+  // LVDS
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
+  SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
+  SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    Status = GfxIntegratedEnumerateAllConnectors (
+               &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
+               Pcie,
+               Gfx
+               );
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+    GfxIntegrateducEDPToLVDSRxIdCallback,
+    &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
+    Pcie
+    );
+
+  // Build PP table
+  PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable;
+  // Build PP table
+  Status = GfxPowerPlayBuildTable (PpTable,  Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  // Assign usFormatID to 0x000B to represent Trinity
+  PpTable->usFormatID = 0xB;
+  // Build info from fuses
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    // Build Display clock info
+    GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+    // Build Sclk info table
+    GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  } else {
+    Status = AGESA_ERROR;
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  //@todo review if thouse parameters needed
+  // Fill in Nb P-state MemclkFreq Data
+  GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in HTC Data
+  GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in NB P states VID
+  GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in NCLK info
+  //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill in the M3 arbitration control tables
+  //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Family specific data update
+
+  // Determine ulGMCRestoreResetTime
+  Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
+  SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+  if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2;
+  }
+  if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1;
+  }
+  if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0;
+  }
+  SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig);
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
+  //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
+  GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *  GMC FB access requred
+ *
+ *
+ * @param[in]   StdHeader     Standard configuration header
+ * @retval      AGESA_STATUS
+ */
+AGESA_STATUS
+GfxIntInfoTableInterfaceTN (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  AGESA_STATUS                    AgesaStatus;
+  AGESA_STATUS                    Status;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  if (GfxLibIsControllerPresent (StdHeader)) {
+    Status = GfxLocateConfigData (StdHeader, &Gfx);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status != AGESA_FATAL) {
+      Status = GfxIntInfoTableInitTN (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
new file mode 100644
index 0000000000..8aace220c3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
@@ -0,0 +1,478 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GfxLibTN.h"
+#include  "GnbCommonLib.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = {
+{0 ,  0 ,  0 ,  0 ,  333,  0,  400,  0 },
+{0 ,  0 ,  533,  0 ,  0 ,  0 ,  667,  0 },
+{0 ,  0 ,   800,  0 ,  0 ,  0 ,  0 ,  0 },
+{0 , 1050, 1066, 0 , 0,    0 , 0,    1200}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GfxFmDisableController (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable GFX controller
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ */
+
+VOID
+GfxFmDisableController (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GnbLibPciRMW (
+    MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS),
+    AccessS3SaveWidth32,
+    0xffffffff,
+    1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get system PLL COF
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    System PLL COF
+ */
+UINT32
+GfxLibGetSytemPllCofTN (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D0F0xBC_xFF000000_STRUCT  D0F0xBC_xFF000000;
+  GnbRegisterReadTN (D0F0xBC_xFF000000_TYPE,  D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader);
+  return 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 0x10);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate COF for DFS out of Main PLL
+ *
+ *
+ *
+ * @param[in] Did         Did
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                COF in 10khz
+ */
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32  Divider;
+  UINT32  SystemPllCof;
+  SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100;
+  if (Did >= 8 && Did <= 0x3F) {
+    Divider = Did * 25;
+  } else if (Did > 0x3F && Did <= 0x5F) {
+    Divider = (Did - 64) * 50 + 1600;
+  } else if (Did > 0x5F && Did <= 0x7E) {
+    Divider = (Did - 96) * 100 + 3200;
+  } else if (Did == 0x7f) {
+    Divider = 128 * 100;
+  } else {
+    ASSERT (FALSE);
+    return 200 * 100;
+  }
+  ASSERT (Divider != 0);
+  return (((SystemPllCof * 100) + (Divider - 1)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set idle voltage mode for GFX
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32  Value;
+
+  GnbRegisterReadTN (GMMx670_TYPE, GMMx670_ADDRESS, &Value, 0, GnbLibGetHeader (Gfx));
+  return ((Value & BIT16) == 0) ? TRUE : FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Extract DRAM frequency
+ *
+ *
+ *
+ * @param[in] Encoding   Memory Clock Frequency Value Definition
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    Dram fraquency Mhz
+ */
+UINT32
+GfxLibExtractDramFrequency (
+  IN       UINT8                  Encoding,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  if (Encoding >= (sizeof (GfxMemClockFrequencyDefinitionTable) / sizeof (UINT16))) {
+    ASSERT (FALSE);
+    return 0;
+  }
+  return GfxMemClockFrequencyDefinitionTable[Encoding / 8][Encoding % 8];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max SCLK
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Max SCLK in Mhz
+ */
+UINT32
+GfxLibGetMaxSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32                    MaxSclkClk;
+  D0F0xBC_xFF000000_STRUCT  D0F0xBC_xFF000000;
+  D0F0xBC_xE0003048_STRUCT  D0F0xBC_xE0003048;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0003048_ADDRESS, &D0F0xBC_xE0003048.Value, 0, StdHeader);
+  //sclk_max_freq = 100 * (GCLK_PLL_FUSES.MainPllOptFreqIdStartup + 16) /
+  //                (((SCLK_MIN_DIV.INT<<12 + SCLK_MIN_DIV.FRAC)>>12)
+  MaxSclkClk = 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 16);
+  MaxSclkClk /= ((D0F0xBC_xE0003048.Field.Intv << 12) + D0F0xBC_xE0003048.Field.Fracv) >> 12;
+  return MaxSclkClk;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of SCLK Dram burst
+ *
+ *
+ * @param[in] ScaleMp         Scaled number of sclk_max_freq / memps_freq
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    number of sclks (*2) per dram burst, except (0,1,2,3)=(1,1.25,1.5,1.75)
+ */
+UINT32
+GfxLibGetNumberOfSclkPerDramBurst (
+  IN       UINT32                ScaleMp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+
+  if ((2 * ScaleMp)  < 125) {
+    return 0; //STATE0 = 0
+  } else if ((2 * ScaleMp)  < 150) {
+    return 1; //STATE0 = 1
+  } else if ((2 * ScaleMp)  < 175) {
+    return 2; //STATE0 = 2
+  } else if ((2 * ScaleMp)  < 200) {
+    return 3; //STATE0 = 3
+  } else {
+    //STATE0 = floor(4*scale_mp[0] )
+    return ((4 * ScaleMp) / 100);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate TN NCLK clock
+ *
+ *
+ *
+ * @param[in] NbFid         NbFid
+ * @param[in] NbDid         NbDid
+ * @retval                  Clock in 10KHz
+ */
+
+UINT32
+GfxLibGetNclkTN (
+  IN      UINT8                   NbFid,
+  IN      UINT8                   NbDid
+  )
+{
+  UINT32  Divider;
+  //i.e. NBCOF[0] = (100 * (D18F5x160[NbFid] + 4h) / (2^D18F5x160[NbDid])) Mhz
+  if (NbDid == 1) {
+    Divider = 2;
+  } else if (NbDid == 0) {
+    Divider = 1;
+  } else {
+    Divider = 1;
+  }
+  ASSERT (NbDid == 0 || NbDid == 1);
+  return ((10000 * (NbFid + 4)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set VID through CG client
+ *
+ *
+ * @param[in] Vid             VID code
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxRequestVoltageTN (
+  IN       UINT8                 Vid,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  GMMx770_STRUCT  GMMx770;
+  GMMx774_STRUCT  GMMx774;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Enter\n");
+
+  GnbRegisterReadTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, 0, StdHeader);
+  GMMx770.Field.VoltageChangeEn = 1;
+  GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  GMMx770.Field.VoltageLevel = Vid;
+  GMMx770.Field.VoltageChangeReq = ~GMMx770.Field.VoltageChangeReq;
+  GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  do {
+    GnbRegisterReadTN (GMMx774_TYPE, GMMx774_ADDRESS, &GMMx774, 0, StdHeader);
+  } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SCLK
+ *
+ *
+ * @param[in] Did             Devider
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    previous DID
+ */
+
+UINT8
+GfxRequestSclkTNS3Save (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, GfxRequestSclkTNS3Script_ID, sizeof (Did), &Did);
+  return GfxRequestSclkTN (Did, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SCLK
+ *
+ *
+ * @param[in] Did             Devider
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+UINT8
+GfxRequestSclkTN (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  GMMx600_STRUCT  GMMx600;
+  GMMx604_STRUCT  GMMx604;
+  UINT8           OriginalDid;
+  do {
+    GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader);
+  } while (GMMx604.Field.SclkStatus == 0);
+  GnbRegisterReadTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader);
+  OriginalDid = (UINT8) GMMx600.Field.IndClkDiv;
+  GMMx600.Field.IndClkDiv = Did;
+  GnbRegisterWriteTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader);
+  do {
+    GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader);
+  } while (GMMx604.Field.SclkStatus == 0);
+  return OriginalDid;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Sclk in S3 script
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        pointer to UINT32 number of us
+ */
+VOID
+GfxRequestSclkTNS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  )
+{
+  GfxRequestSclkTN (* ((UINT8*) Context), StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate did from main VCO
+ *
+ *
+ *
+ * @param[in] Vco           Vco in 10Khz
+ * @param[in] StdHeader     Standard configuration header
+ * @retval                  DID
+ */
+
+UINT8
+GfxLibCalculateDidTN (
+  IN       UINT32                Vco,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32  Divider;
+  UINT32  SystemPllCof;
+  UINT8   Did;
+  ASSERT (Vco != 0);
+  SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100;
+  Divider = ((SystemPllCof * 100) + (Vco - 1)) / Vco;
+  Did = 0;
+  if (Divider < 200) {
+  } else if (Divider <= 1575) {
+    Did = (UINT8) (Divider / 25);
+  } else if (Divider <= 3150) {
+    Did = (UINT8) ((Divider - 1600) / 50) + 64;
+  } else if (Divider <= 6200) {
+    Did = (UINT8) ((Divider - 3200) / 100) + 96;
+  } else {
+    Did = 0x7f;
+  }
+  return Did;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h
new file mode 100644
index 0000000000..69dd6477eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXLIBTN_H_
+#define _GFXLIBTN_H_
+
+UINT32
+GfxLibGetSytemPllCofTN (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibExtractDramFrequency (
+  IN       UINT8                  Encoding,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibGetMaxSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT32
+GfxLibGetNumberOfSclkPerDramBurst (
+  IN       UINT32                ScaleMp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT32
+GfxLibGetNclkTN (
+  IN      UINT8                  NbFid,
+  IN      UINT8                  NbDid
+  );
+
+AGESA_STATUS
+GfxRequestVoltageTN (
+  IN       UINT8                 Vid,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT8
+GfxRequestSclkTN (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT8
+GfxRequestSclkTNS3Save (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+GfxRequestSclkTNS3Script (
+  IN      AMD_CONFIG_PARAMS      *StdHeader,
+  IN      UINT16                 ContextLength,
+  IN      VOID*                  Context
+  );
+
+UINT8
+GfxLibCalculateDidTN (
+  IN       UINT32                Vco,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
new file mode 100644
index 0000000000..4e3efa5466
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
@@ -0,0 +1,304 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65199 $   @e \$Date: 2012-02-09 21:36:06 -0600 (Thu, 09 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxLibTN.h"
+#include  "GfxGmcInitTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "PcieConfigData.h"
+#include  "PcieConfigLib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbHandleLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAudioConnectors (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+AGESA_STATUS
+GfxMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+VOID
+exec803 /* GfxAzWorkaroundTN */ (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxSetBootUpVoltageTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltageTN Enter\n");
+  GfxRequestVoltageTN (GnbLocateHighestVidCode (GnbLibGetHeader (Gfx)), GnbLibGetHeader (Gfx));
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+exec803 /* GfxAzWorkaroundTN */ (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32                  i;
+  UINT32                  Address;
+  UINT32                  Data;
+
+
+  Data = 0x156;
+  for (i = 0; i < 6; i++) {
+    Address = 0x5E00 + (i * 0x18);
+    GnbLibMemWrite (Gfx->GmmBase + Address, AccessS3SaveWidth32, &Data, GnbLibGetHeader (Gfx));
+    GnbLibMemRMW (Gfx->GmmBase + Address + 4, AccessS3SaveWidth32, 0xFFFFFF00, 0xF0, GnbLibGetHeader (Gfx));
+  }
+
+  return;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Mid Post.
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status =  GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_FATAL) {
+    GfxFmDisableController (StdHeader);
+  } else {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnableGmmAccess (Gfx);
+      ASSERT (Status == AGESA_SUCCESS);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      if (Status != AGESA_SUCCESS) {
+        // Can not initialize GMM registers going to disable GFX controller
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Fail to establish GMM access\n");
+        Gfx->UmaInfo.UmaMode = UMA_NONE;
+        GfxFmDisableController (StdHeader);
+      } else {
+        Status = GfxGmcInitTN (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxSetBootUpVoltageTN (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxInitSsid (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxIntegratedEnumerateAudioConnectors (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        exec803 /* GfxAzWorkaroundTN */ (Gfx);
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine number of audio ports for each connector
+ *
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegratedAudioEnumCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8    *AudioCount;
+  AudioCount = (UINT8*) Buffer;
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found HDMI Connector\n");
+    (*AudioCount)++;
+  } else if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) {
+    if ((Engine->Type.Ddi.DdiData.Flags & DDI_DATA_FLAGS_DP1_1_ONLY) == 0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.2 Connector\n");
+      *AudioCount += 4;
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.1 Connector\n");
+      (*AudioCount)++;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors with audio capability and configure number of ports
+ *
+ *
+ *
+ * @param[in]     Gfx             Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAudioConnectors (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  UINT8                   AudioCount;
+  AGESA_STATUS            Status;
+  GMMx5F50_STRUCT         GMMx5F50;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Enter\n");
+
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) {
+    AudioCount = 0;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+      GfxIntegratedAudioEnumCallback,
+      &AudioCount,
+      Pcie
+      );
+    if (AudioCount > 4) {
+      AudioCount = 4;
+    }
+    GMMx5F50.Value = 0x00;
+    GMMx5F50.Field.PortConnectivity = (7 - AudioCount);
+    GMMx5F50.Field.PortConnectivityOverrideEnable = 1;
+    GnbRegisterWriteTN (GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n");
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
new file mode 100644
index 0000000000..36e013ef3c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
@@ -0,0 +1,155 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbFuseTable.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxPostInterfaceTN (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Post.
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS
+ */
+
+
+AGESA_STATUS
+GfxPostInterfaceTN (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_POST_PARAMS       *PostParamsPtr;
+  GFX_CARD_CARD_INFO    GfxDiscreteCardInfo;
+  AGESA_STATUS          Status;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    if (GfxLibIsControllerPresent (StdHeader)) {
+      if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
+        LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader);
+        GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader);
+        if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) ||
+          (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) ||
+          ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE)  &&
+          ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) {
+          PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+          IDS_HDT_CONSOLE (GFX_MISC, "  GfxDisabled due dGPU policy\n");
+        }
+      }
+    } else {
+      PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+      Gfx->GfxFusedOff = TRUE;
+    }
+  } else {
+    PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
new file mode 100644
index 0000000000..876614e510
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
@@ -0,0 +1,1096 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GFx tables
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64726 $   @e \$Date: 2012-01-30 01:00:01 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbRegistersTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbInitTN.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [] = {
+  //2.1 Disable clock-gating
+  GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00000C80),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00001401),
+  GNB_ENTRY_TERMINATE
+};
+
+
+GNB_TABLE ROMDATA GfxGmcInitTableTN [] = {
+  GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET),
+  //2.2 System memory address translation
+  GNB_ENTRY_COPY (GMMx2814_TYPE, GMMx2814_ADDRESS,  0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2818_TYPE, GMMx2818_ADDRESS,  0, 32, D18F2x40_dct1_TYPE, D18F2x40_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx281C_TYPE, GMMx281C_ADDRESS,  0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2820_TYPE, GMMx2820_ADDRESS,  0, 32, D18F2x44_dct1_TYPE, D18F2x44_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2824_TYPE, GMMx2824_ADDRESS,  0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2828_TYPE, GMMx2828_ADDRESS,  0, 32, D18F2x48_dct1_TYPE, D18F2x48_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx282C_TYPE, GMMx282C_ADDRESS,  0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2830_TYPE, GMMx2830_ADDRESS,  0, 32, D18F2x4C_dct1_TYPE, D18F2x4C_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2834_TYPE, GMMx2834_ADDRESS,  0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2838_TYPE, GMMx2838_ADDRESS,  0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx283C_TYPE, GMMx283C_ADDRESS,  0, 32, D18F2x60_dct1_TYPE, D18F2x60_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2840_TYPE, GMMx2840_ADDRESS,  0, 32, D18F2x64_dct1_TYPE, D18F2x64_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS,  0,  8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS,  0,  8),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 16,  1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22,  1),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 19,  1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20,  1),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS,  0,  8, D18F2x80_dct1_TYPE, D18F2x80_dct1_ADDRESS,  0,  8),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 16,  1, D18F2x94_dct1_TYPE, D18F2x94_dct1_ADDRESS, 22,  1),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 19,  1, D18F2xA8_dct1_TYPE, D18F2xA8_dct1_ADDRESS, 20,  1),
+  GNB_ENTRY_COPY (GMMx284C_TYPE, GMMx284C_ADDRESS,  0, 32, TYPE_D18F2 , 0x110 ,  0, 32),
+  GNB_ENTRY_COPY (GMMx2850_TYPE, GMMx2850_ADDRESS,  0, 32, D18F2x114_TYPE, D18F2x114_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2854_TYPE, GMMx2854_ADDRESS,  0, 32, D18F1xF0_TYPE,  D18F1xF0_ADDRESS,   0, 32),
+  //GNB_ENTRY_COPY (GMMx2858_TYPE, GMMx2858_ADDRESS,  0, 32, ????, ????,  0, 32),
+  GNB_ENTRY_COPY (GMMx285C_TYPE, GMMx285C_ADDRESS,  0, 32, TYPE_D18F2 , 0x10c ,  0, 32),
+  // 2.4 RENG init
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001b0a05),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000001D),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00080500),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000027),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001050c),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x1000051e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010536),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000031),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001053e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000034),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010546),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000037),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a054e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000053),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001056f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000056),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010572),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000059),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020575),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000800),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a0801),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007b),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001082a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0014082d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000094),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00040843),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000009a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00170851),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000b3),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001d086a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d2),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000891),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d4),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000893),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d6),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020895),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000da),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020899),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000de),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0002089d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e2),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000208a1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e6),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x006808cd),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000150),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0016094d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000168),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d096d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000177),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0009097f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000182),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000a098a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000018e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d0998),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000019d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000409a7),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001a3),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x003709cd),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001dc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000f0a21),
+  GNB_ENTRY_WR (GMMx28D4_TYPE, GMMx28D4_ADDRESS, 0x7b1ec000),
+  GNB_ENTRY_WR (GMMx28D8_TYPE, GMMx28D8_ADDRESS, 0x200cf01d),
+  // 2.5
+  GNB_ENTRY_RMW (GMMx5490_TYPE, GMMx5490_ADDRESS, GMMx5490_FB_WRITE_EN_MASK | GMMx5490_FB_READ_EN_MASK, (1 << GMMx5490_FB_READ_EN_OFFSET) | (1 << GMMx5490_FB_WRITE_EN_OFFSET)),
+  // 2.6 Perfromance tuning
+  GNB_ENTRY_WR (TYPE_GMM , 0x27d0 , 0x10734847),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27c0 , 0x00032005),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27c4 , 0x00C12008),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27d4 , 0x00003d3c),
+  GNB_ENTRY_WR (TYPE_GMM , 0x277c , 0x00000007),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2198 , 0x000221b1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080A20),
+  GNB_ENTRY_WR (TYPE_GMM , 0x201c , 0x66660006),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2020 , 0x70770007),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2018 , 0x66070050),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2014 , 0x77550000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2794 , 0xfcfcfdfc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2798 , 0xfcfcfdfc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27a4 , 0x00ffffff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27a8 , 0x00ffffff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x278c , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2790 , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2628 , 0x44111222),
+  GNB_ENTRY_WR (TYPE_GMM , 0x25e0 , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x262c , 0x11222111),
+  GNB_ENTRY_WR (TYPE_GMM , 0x25e4 , 0x00000002),
+  //2.7 Miscellaneous programming
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b4 , 0x00000000),
+  //2.8 Enabling garlic interface
+  GNB_ENTRY_RMW (TYPE_GMM , 0x2878 , 0x1 , 1 << 0 ),
+  // Limit number of garlic credits to 12
+  GNB_ENTRY_WR (TYPE_GMM , 0x276c , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2898 , 0x01800360),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x289c , 0x8000 , 1 << 15 ),
+  GNB_ENTRY_REV_RMW (0x0000000000000100ull , TYPE_GMM , 0x289c , 0x8000 , 0 << 15 ),
+  GNB_ENTRY_RMW (GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 0 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET),
+  GNB_ENTRY_REV_RMW (0x0000000000000100ull , GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 1 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET),
+  //2.10 UVD and VCE latency
+  //These settings are to improve UVD and VCE latency.
+  //They need these settings to get good memory performance.
+  GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080200),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2190 , 0x001EA1A1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2180 , 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x218c , 0x000FA1E1),
+  GNB_ENTRY_WR (GMMx2188_TYPE, GMMx2188_ADDRESS, 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f0 , 0x0000A1F1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21ec , 0x0000A1F1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f8 , 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f4 , 0x0000A1E1),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x690 , 0x20000000 , 1 << 29 ),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x21a8 , 0x4 , 0),
+//MC Performance settings base on memory channel configuration, so, move settings to GfxGmcInitializeSequencerTN()
+//  GNB_ENTRY_WR (TYPE_GMM , 0x2214 , 0x00000003),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2218 , 0x0000000C),
+  GNB_ENTRY_WR (GMMx2888_TYPE, GMMx2888_ADDRESS, 0x000007DE),
+  GNB_ENTRY_WR (GMMx25C8_TYPE, GMMx25C8_ADDRESS, 0x00403932),
+  GNB_ENTRY_WR (GMMx2114_TYPE, GMMx2114_ADDRESS, 0x00000015),
+  //2.11 Remove blackout
+  GNB_ENTRY_WR (GMMx25C0_TYPE, GMMx25C0_ADDRESS, 0x00000000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20ec , 0x000001DC),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20d4 , 0x00000016),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20ac , 0x00000000),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x2760 , 0x3 , 1 << 0 ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [] = {
+  GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00040c80),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00041401),
+  //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
+  //Implement in GnbCgttOverrideTN
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GfxEnvInitTableTN [] = {
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_GMM ,
+    0xe60 ,
+    0x0,
+    (0x1 << 1 ) | (0x1 << 0 ) |
+    (0x1 << 5 )  | (0x1 << 2 ) |
+    (0x1 << 7 ) | (0x1 << 6 ) |
+    (0x1 << 9 ) | (0x1 << 8 ) |
+    (0x1 << 11 )  | (0x1 << 10 ) |
+    (0x1 << 14 ) | (0x1 << 13 ) |
+    (0x1 << 17 ) | (0x1 << 15 ) |
+    (0x1 << 19 ) | (0x1 << 18 ) |
+    (0x1 << 24 ) | (0x1 << 20 )
+    ),
+//---------------------------------------------------------------------------
+// Configure GMC Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    (10 << 0 ) | (4 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    (90 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown GMC if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300000_P1Select_OFFSET) | (1 << D0F0xBC_xE0300000_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300200_TYPE,
+    D0F0xBC_xE0300200_ADDRESS,
+    D0F0xBC_xE0300200_P1IsoN_MASK,
+    0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Configure UVD Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown UVD if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE030003C_P1Select_OFFSET) | (1 << D0F0xBC_xE030003C_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300218_TYPE,
+    D0F0xBC_xE0300218_ADDRESS,
+    D0F0xBC_xE0300218_P1IsoN_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Configure VCE Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown VCE if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300024_P1Select_OFFSET) | (1 << D0F0xBC_xE0300024_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030020C_TYPE,
+    D0F0xBC_xE030020C_ADDRESS,
+    D0F0xBC_xE030020C_P1IsoN_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_VcePgfsmClockEn_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+
+//---------------------------------------------------------------------------
+// Configure DCE Power Island
+  // Step 1: Take control over DC2 PGFSM. By default display sends power up/down commands.
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03002DC_TYPE,
+    D0F0xBC_xE03002DC_ADDRESS,
+    (1 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET)
+    ),
+  //Step 2: Read CC_RCU_FUSES register
+  //If Internal GPU is fused off go to Step 3, ELSE Go to Step 4.
+
+  //Step 3: Enable PGFSM commands during reset
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  //Step 4:
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300030_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300030_WriteOp_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  //Step 5: IF (cc_rcu_fuses.f.gpu_dis == 0x1) Skip Step6 ELSE Go to Step 6
+  //Step 6: Disable PGFSM commands during reset. Move to after shutdown DCE.
+  //Step 7: Release control over DC2 PGFSM. Move to after shutdown DCE.
+
+// Shutdown DCE if integrated GFX disabled
+  //Step 1: Take control over DC2 PGFSM. By default display sends power up down commands.
+  //Step 2: Read CC_RCU_FUSES register
+  //Step 3: Enable PGFSM commands during reset
+  //Step 4: Make sure SCLK frequency is below 400Mhz
+  //Step 5: Enable PGFSM clock
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK,
+    (1 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET)
+    ),
+  //Step 6
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300030_P1Select_OFFSET) | (1 << D0F0xBC_xE0300030_P2Select_OFFSET)
+    ),
+  //Step 7
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300210_TYPE,
+    D0F0xBC_xE0300210_ADDRESS,
+    D0F0xBC_xE0300210_P1IsoN_MASK,
+    (0 << D0F0xBC_xE0300210_P1IsoN_OFFSET)
+    ),
+  //Step 8: Restore previous SCLK divider
+  //Step 9: Wait PSO daughter to be asserted
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300210 ,
+    0x2000 ,
+    (1 << 13 )
+    ),
+  //Step 10: Turn off PGFSM clock
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK,
+    (0 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET)
+    ),
+  //Step 11: Disable PGFSM commands during reset. Same final 2 step as DCE power island
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03002DC_TYPE,
+    D0F0xBC_xE03002DC_ADDRESS,
+    (0 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET)
+    ),
+
+//---------------------------------------------------------------------------
+// Configure GFX Power Island
+
+  //Step 3
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 4
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 5
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 6
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 7
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 8
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 9
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 10
+    GNB_ENTRY_RMW (
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    0x0
+    ),
+  // Step 12
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+// Shutdown Gfx if integrated GFX disabled
+  // Step 2
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  // Step 3: Save current SCLK. Make sure SCLK frequency is below 400Mhz
+  // Step 5
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    (1 << 0 ) | (1 << 1 ) |
+    (1 << 2 ) | (1 << 3 ) |
+    (1 << 4 ) | (1 << 5 ) |
+    (1 << 6 )
+    ),
+  // Step 6
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300054_P1Select_OFFSET) | (1 << D0F0xBC_xE0300054_P2Select_OFFSET)
+    ),
+  // Step 7
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300070_P1Select_OFFSET) | (1 << D0F0xBC_xE0300070_P2Select_OFFSET)
+    ),
+  // Step 8
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE030008C_P1Select_OFFSET) | (1 << D0F0xBC_xE030008C_P2Select_OFFSET)
+    ),
+  // Step 9
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000A8_P1Select_OFFSET) | (1 << D0F0xBC_xE03000A8_P2Select_OFFSET)
+    ),
+  // Step 10
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000C4_P1Select_OFFSET) | (1 << D0F0xBC_xE03000C4_P2Select_OFFSET)
+    ),
+  // Step 11
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000E0_P1Select_OFFSET) | (1 << D0F0xBC_xE03000E0_P2Select_OFFSET)
+    ),
+  // Step 12
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000FC_P1Select_OFFSET) | (1 << D0F0xBC_xE03000FC_P2Select_OFFSET)
+    ),
+  // Step 13
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03002F4_TYPE,
+    D0F0xBC_xE03002F4_ADDRESS,
+    0xFFFFFFFF,
+    0
+    ),
+  // Step 14
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03002F0_TYPE,
+    D0F0xBC_xE03002F0_ADDRESS,
+    0xFFFFFFFF,
+    0
+    ),
+  // Step 15: Restore SCLK that is saved in step 4
+  // Step 16
+  GNB_ENTRY_FULL_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */,
+    D0F0xBC_xE03002FC_TYPE,
+    D0F0xBC_xE03002FC_ADDRESS,
+    0xFFFFFFFF,
+    0x3FFFFFFF
+    ),
+  // Step 17
+  GNB_ENTRY_FULL_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */,
+    D0F0xBC_xE03002E4_TYPE,
+    D0F0xBC_xE03002E4_ADDRESS,
+    0xFFFFFFFF,
+    0x3FFFF
+    ),
+  // Step 18
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    0
+    ),
+  // Step 19
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Isolate DC, SYS and CP tile when Internal Graphics is disabled
+  // Step 2: Reduce SCLK frequency to 100Mhz. Save current SCLK divider.
+  // Step 3
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003034_TYPE,
+    D0F0xBC_xE0003034_ADDRESS,
+    D0F0xBC_xE0003034_SysIso_MASK | D0F0xBC_xE0003034_CpIso_MASK |
+    D0F0xBC_xE0003034_Dc0Iso_MASK | D0F0xBC_xE0003034_Dc1Iso_MASK |
+    D0F0xBC_xE0003034_DciIso_MASK | D0F0xBC_xE0003034_DcipgIso_MASK,
+    (1 << D0F0xBC_xE0003034_SysIso_OFFSET) | (1 << D0F0xBC_xE0003034_CpIso_OFFSET) |
+    (1 << D0F0xBC_xE0003034_Dc0Iso_OFFSET) | (1 << D0F0xBC_xE0003034_Dc1Iso_OFFSET) |
+    (1 << D0F0xBC_xE0003034_DciIso_OFFSET) | (1 << D0F0xBC_xE0003034_DcipgIso_OFFSET)
+    ),
+  //Step 4: Restore pervious SCLK frequency
+
+//---------------------------------------------------------------------------
+// For IOMMU add logic of GfxDis
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F2xF4_x57_TYPE,
+    D0F2xF4_x57_ADDRESS,
+    D0F2xF4_x57_L1ImuIntGfxDis_MASK,
+    (0x1 << D0F2xF4_x57_L1ImuIntGfxDis_OFFSET)
+    ),
+
+  GNB_ENTRY_TERMINATE
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
new file mode 100644
index 0000000000..b8dc935f43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
@@ -0,0 +1,353 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe early post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#define GnbFpLibGetExp(V)  ((INT32) ((*((UINT64*) &Value) >> 52) & 0x7FF) - (1023 + 52))
+#define GnbFpLibGetMnts(V) (INT64) ((*((UINT64*) &Value) & ((1ull << 52) - 1)) | (1ull << 52))
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+INT32 _fltused = 0;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate power of
+ *
+ *
+ * @param[in]  Value    value
+ * @param[in]  Pow      power
+ * @retval  Value^Pow
+ */
+
+STATIC DOUBLE
+GnbBapmPowerOf (
+  IN      DOUBLE    Value,
+  IN      UINTN     Pow
+  )
+{
+  DOUBLE Result;
+  Result = Value;
+  while ( --Pow > 0) {
+    Result *= Value;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode R from fuse
+ *
+ *
+ * @param[in]  FuseR    R fused value
+ * @retval  R
+ */
+STATIC DOUBLE
+GnbBapmDecodeR (
+  IN      UINT32  FuseR
+  )
+{
+  DOUBLE Value;
+  Value = ((DOUBLE) (FuseR & 0x1ff)) / (2 << (8 - 1));
+  Value = GnbBapmPowerOf (Value, 4);
+  return ((FuseR & 0x200) != 0) ? (-1) * Value : Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode Tau from fuse
+ *
+ *
+ * @param[in]  FuseTau    Tau fused value
+ * @retval  Tau
+ */
+STATIC DOUBLE
+GnbBapmDecodeTau (
+  IN      UINT32  FuseTau
+  )
+{
+  DOUBLE  Value;
+  Value = FuseTau;
+  Value = GnbBapmPowerOf (Value / (2 << (9 - 1)), 16);
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calaculate X
+ *
+ *
+ * @param[in]  Ts         Samplig rate
+ * @param[in]  Tau        Tau value
+ * @param[in]  R          R value
+ * @retval  X
+ */
+STATIC DOUBLE
+GnbBapmCalculateX (
+  IN      DOUBLE  Ts,
+  IN      DOUBLE  Tau,
+  IN      DOUBLE  R
+  )
+{
+  //X=(R*Ts)/(2*Tau+Ts);
+  DOUBLE Result;
+  Result = (R * Ts) / (2 * Tau + Ts);
+  return (Result * GnbBapmPowerOf (2, 36)) + 0.5;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calaculate Y
+ *
+ *
+ * @param[in]  Ts         Samplig rate
+ * @param[in]  Tau        Tau value
+ * @retval  Y
+ */
+STATIC DOUBLE
+GnbBapmCalculateY (
+  IN      DOUBLE  Ts,
+  IN      DOUBLE  Tau
+  )
+{
+  //Y=(2*Tau-Ts)/(2*Tau+Ts);
+  DOUBLE Result;
+  Result = (2 * Tau - Ts) / (2 * Tau + Ts);
+  return (Result *  GnbBapmPowerOf (2, 32)) + 0.5;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set X & Y value
+ *
+ *
+ * @param[in]  X          X value
+ * @param[in]  Y          Y value
+ * @param[in]  AddrOffset Offset of address
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmSetYAndX (
+  IN       INT32              X,
+  IN       INT32              Y,
+  IN       UINT32             AddrOffset,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  GnbRegisterWriteTN (
+    D0F0xBC_x1F480_TYPE,
+    D0F0xBC_x1F480_ADDRESS + AddrOffset,
+    &X,
+    0,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "X: 0x%08x\n", X);
+  GnbRegisterWriteTN (
+    D0F0xBC_x1F480_TYPE,
+    D0F0xBC_x1F480_ADDRESS + AddrOffset + 4,
+    &Y,
+    0,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "Y: 0x%08x\n", Y);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Extract INt32 from DOUBLE
+ *
+ *
+ *
+ * @param[in]  Value  Double value
+ * @retval     int32
+ */
+INT32
+GnbFpLibDoubleToInt32 (
+  IN      DOUBLE  Value
+  )
+{
+  INT64   Mantissa;
+  INT32   Exponent;
+  Mantissa = GnbFpLibGetMnts (Value);
+  Exponent = GnbFpLibGetExp (Value);
+  if (Exponent < -64) {
+    Mantissa = 0;
+  } else if (Exponent < 0) {
+    Mantissa >>=  - Exponent;
+  } else {
+    Mantissa <<= Exponent;
+  }
+  return (INT32) ((Value < 0) ? - Mantissa :  Mantissa);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calcuate BAPM coefficient
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+VOID
+GnbBapmCalculateCoeffsTN (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32  RFuse1;
+  UINT32  TauFuse1;
+  UINT32  Index;
+  DOUBLE  R;
+  DOUBLE  Tau;
+  DOUBLE  Ts;
+  INT32   X;
+  INT32   Y;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Enter\n");
+
+  LibAmdFinit ();
+
+  Ts = ((DOUBLE) (D0F0xBC_x1F468_TimerPeriod_Value * D0F0xBC_x1F46C_BapmPeriod_Value) / 100) / 1000000;
+
+  for (Index = 0; Index < 15; Index++) {
+    GnbRegisterReadTN (
+      TYPE_D0F0xBC ,
+      0xe01040c4  + Index * 4,
+      &RFuse1,
+      0,
+      StdHeader
+      );
+    GnbRegisterReadTN (
+      TYPE_D0F0xBC ,
+      0xe01040c4  + (Index + 15) * 4,
+      &TauFuse1,
+      0,
+      StdHeader
+      );
+
+    R = GnbBapmDecodeR (RFuse1 & 0x3FF);
+    Tau = GnbBapmDecodeTau (TauFuse1 & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+    GnbBapmSetYAndX (X, Y, Index * 2 * 4, StdHeader);
+
+    R = GnbBapmDecodeR ((RFuse1 >> 10) & 0x3FF);
+    Tau = GnbBapmDecodeTau ((TauFuse1 >> 10) & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+
+    GnbBapmSetYAndX (X, Y, (Index * 2 + 30) * 4 , StdHeader);
+
+    R = GnbBapmDecodeR ((RFuse1 >> 20) & 0x3FF);
+    Tau = GnbBapmDecodeTau ((TauFuse1 >> 20) & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+
+    GnbBapmSetYAndX (X, Y, (Index * 2 + 60) * 4 , StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Exit\n");
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h
new file mode 100644
index 0000000000..3ed7b4807f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CAC weights table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBBAPMCOEFFCALCTN_H_
+#define _GNBBAPMCOEFFCALCTN_H_
+
+typedef double DOUBLE;
+
+VOID
+GnbBapmCalculateCoeffsTN (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+INT32
+GnbFpLibDoubleToInt32 (
+  IN      DOUBLE  Value
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
new file mode 100644
index 0000000000..bf17ad1601
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
@@ -0,0 +1,175 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CAC weights table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBCACWEIGHTSTABLETN_H_
+#define _GNBCACWEIGHTSTABLETN_H_
+
+UINT32 CacWeightsTN[] = {
+  0xD65,
+  0x289A,
+  0x289A,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x16F,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x16A5,
+  0x592,
+  0x0,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0xEC9,
+  0xEC9,
+  0x41A,
+  0x41A,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0x79,
+  0x79,
+  0x79,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x3F2,
+  0x3F2,
+  0x0,
+  0x0,
+  0x123,
+  0x0,
+  0x0,
+  0x0,
+  0x123,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x195B,
+  0x629,
+  0x0,
+  0x0,
+  0x195B,
+  0x629,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x88B,
+  0x1206,
+  0x0,
+  0x88B,
+  0x1206,
+  0x0,
+  0x0
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
new file mode 100644
index 0000000000..b3b3101072
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
@@ -0,0 +1,888 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe early post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64732 $   @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbTable.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbSmuFirmwareTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GfxLibTN.h"
+#include  "GnbCacWeightsTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbHandleLib.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "GnbInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA      GnbEarlyInitTableTN [];
+extern GNB_TABLE ROMDATA      GnbEarlierInitTableBeforeSmuTN [];
+extern GNB_TABLE ROMDATA      GnbEarlierInitTableAfterSmuTN [];
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern BUILD_OPT_CFG          UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+GnbEarlierInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+);
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
+
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbAdjustSmuVidBeforeSmuTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_xE0001008_STRUCT  D0F0xBC_xE0001008;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+  D0F0xBC_xE0001008.Field.SClkVid3 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid2 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid1 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid0 -= 4;
+  GnbRegisterWriteTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
+
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbAdjustSmuVidAfterSmuTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F88C_STRUCT                   D0F0xBC_x1F88C;
+  D0F0xBC_x1F8DC_STRUCT                   D0F0xBC_x1F8DC;
+  D0F0xBC_x1F8E0_STRUCT                   D0F0xBC_x1F8E0;
+  D0F0xBC_x1F8E4_STRUCT                   D0F0xBC_x1F8E4;
+  D0F0xBC_x1F8E8_STRUCT                   D0F0xBC_x1F8E8;
+  D0F0xBC_x1F400_STRUCT                   D0F0xBC_x1F400;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Enter\n");
+
+  //Adjust SMU VIDs
+  GnbRegisterReadTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader);
+
+  D0F0xBC_x1F88C.Field.NbVid_3 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_2 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_1 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_0 -= 4;
+
+  D0F0xBC_x1F8DC.Field.SClkVid3 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid2 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid1 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid0 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_2 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_1 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_0 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmNbVid_1 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmNbVid_0 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmSclkVid_3 -= 4;
+  D0F0xBC_x1F8E8.Field.BapmNbVid_3 -= 4;
+  D0F0xBC_x1F8E8.Field.BapmNbVid_2 -= 4;
+
+  GnbRegisterWriteTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader);
+
+  //D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV)
+  GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+  D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb SMU LHTC support
+ *
+ * Part of BAPM enablement.
+ * When BAPM is disabled in battery mode firmware will enable LHTC.
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmLhtcInitTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F638_STRUCT            D0F0xBC_x1F638;
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+  D0F0xBC_x1F86C_STRUCT            D0F0xBC_x1F86C;
+  D0F0xBC_x1F628_STRUCT            D0F0xBC_x1F628;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+
+  //1. Set HTC period to 10 in PM_TIMERS_2 register
+  //Still need to keep PM_CONFIG.Enable_HTC_Limit to 0
+  D0F0xBC_x1F428.Field.field_4  = 0;
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F638.Field.HtcPeriod = 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader);
+
+  //2. Read BapmLhtcCap fuse
+  GnbRegisterReadTN (D0F0xBC_x1F86C_TYPE, D0F0xBC_x1F86C_ADDRESS, &D0F0xBC_x1F86C, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader);
+  if (D0F0xBC_x1F86C.Field.BapmLhtcCap == 0) {
+    D0F0xBC_x1F628.Field.HtcActivePstateLimit = 0;
+  } else {
+    D0F0xBC_x1F628.Field.HtcActivePstateLimit = D0F0xBC_xE0104188.Field.LhtcPstateLimit;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Measured temperature with BAPM
+ *
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmMeasuredTempTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+  D0F0xBC_x1F844_STRUCT            D0F0xBC_x1F844;
+  D0F0xBC_x1F848_STRUCT            D0F0xBC_x1F848;
+  D0F0xBC_x1F84C_STRUCT            D0F0xBC_x1F84C;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+
+  //Measured temperature with BAPM
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F428.Field.line180  = 0;
+  if (D0F0xBC_xE0104188.Field.BapmMeasuredTemp == 1) {
+    D0F0xBC_x1F844.Value = 0x38B;
+    GnbRegisterWriteTN (D0F0xBC_x1F844_TYPE, D0F0xBC_x1F844_ADDRESS, &D0F0xBC_x1F844, 0, StdHeader);
+    D0F0xBC_x1F848.Value = 0x38D;
+    GnbRegisterWriteTN (D0F0xBC_x1F848_TYPE, D0F0xBC_x1F848_ADDRESS, &D0F0xBC_x1F848, 0, StdHeader);
+    D0F0xBC_x1F84C.Value = 0x389;
+    GnbRegisterWriteTN (D0F0xBC_x1F84C_TYPE, D0F0xBC_x1F84C_ADDRESS, &D0F0xBC_x1F84C, 0, StdHeader);
+
+    D0F0xBC_x1F428.Field.line180  = 1;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb SMU LHTC Enable
+ *
+ * Part of BAPM enablement.
+ * When BAPM is disabled in battery mode firmware will enable LHTC.
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbLhtcEnableTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F428.Field.field_4  = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Exit\n");
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Update BAPMTI_TjOffset
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbTjOffsetUpdateTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F870_STRUCT             D0F0xBC_x1F870;
+
+  CPU_LOGICAL_ID                    LogicalId;
+  GNB_HANDLE                        *GnbHandle;
+  D0F0xBC_xE0104040_STRUCT          D0F0xBC_xE0104040;
+  D0F0xBC_x1F85C_STRUCT             D0F0xBC_x1F85C;
+  ex1075_STRUCT           ex1075 ;
+  UINT32                            TimerPeriod;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Enter\n");
+
+
+  TimerPeriod = D0F0xBC_x1F468_TimerPeriod_Value;
+  GnbRegisterReadTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe010413c , &ex1075, 0, StdHeader);
+  // Determine desired AgingRate:
+  // PM_FUSES4.TdpAgeRate * Fuse[BAPMTI_Ts] (encoded in us)
+  // Re-encode TdpAgeRate with 1ms BAPM interval
+  D0F0xBC_x1F85C.Field.TdpAgeRate = (D0F0xBC_x1F85C.Field.TdpAgeRate * ex1075.Field.ex1075_0 ) / (TimerPeriod / 100);
+  GnbRegisterWriteTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader);
+  if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision);
+    return;
+  }
+  GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+  //9900h=FS1r2/FP2 Devastator
+  //9903h=FS1r2/FP2 Devastator Lite
+  //9990h=FS1r2/FP2 Scrapper
+  //9901h=FM2 Devastator
+  //9904h=FM2 Devastator Lite
+  //9991h=FM2 Scrapper
+  if ((D0F0xBC_xE0104040.Field.DeviceID == 0x9900) || (D0F0xBC_xE0104040.Field.DeviceID == 0x9903)) {
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x26;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x26;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x26;
+  } else if (D0F0xBC_xE0104040.Field.DeviceID == 0x9990) {
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x2E;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x2E;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x2E;
+  } else {
+    IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Skip DID- %x\n", D0F0xBC_xE0104040.Field.DeviceID);
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * GPU CAC enablement and weights programming
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+STATIC VOID
+GnbCacEnablement (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F464_STRUCT   D0F0xBC_x1F464;
+  ex1071_STRUCT    ex1071 ;
+  ex1072_STRUCT    ex1072 ;
+  PCI_ADDR                PciAddress;
+  UINT8                   Index;
+  ex1073_STRUCT    ex1073 ;
+  D18F5x160_STRUCT        D18F5x160;
+  DOUBLE                  UnbCac;
+  GMMx898_STRUCT          GMMx898;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader);
+  ex1072.Field.ex1072_2  = 0x29;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader);
+
+  //UNB_CAC_VALUE.UNB_CAC = 2.3734E-04 * FNBPS0 (in MHz) * 2^GPU_CAC_AVRG_CNTL.WEIGHT_PREC
+  GnbRegisterReadTN (D18F5x160_TYPE, D18F5x160_ADDRESS, &D18F5x160.Value, 0, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "NBP0 10khz %x (%d)\n", GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid), GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid));
+  UnbCac = 0.00000204831536 * (1 << ex1072.Field.ex1072_0 ) * GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid);
+  ex1073.Field.ex1073_0  = (UINT32) GnbFpLibDoubleToInt32 (UnbCac);
+  IDS_HDT_CONSOLE (GNB_TRACE, "UnbCac %x (%d)\n", ex1073.Field.ex1073_0 , ex1073.Field.ex1073_0 );
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f91c , &ex1073.Value, 0, StdHeader);
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader);
+  ex1071.Field.ex1071_0  = 0x1;
+  ex1071.Field.ex1071_3  = 0x4;
+  ex1071.Field.ex1071_4  = 0x25;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader);
+
+  GnbRegisterReadTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader);
+  GMMx898.Field.Threshold = 0x31;
+  GnbRegisterWriteTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader);
+
+  // Set CAC/TDP interval
+  GnbRegisterReadTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader);
+  D0F0xBC_x1F464.Field.TdpCntl = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader);
+
+  // Program GPU CAC weights
+
+  for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) {
+    GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0  + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader);
+  }
+
+  // Call BIOS service SMC_MSG_CONFIG_TDP_CNTL
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  GnbSmuServiceRequestV4 (
+    PciAddress,
+    SMC_MSG_CONFIG_TDP_CNTL,
+    0,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode power of CPU out of Watt
+ *
+ *
+ *
+ * @param[in] Encode      PwrCpu encode
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                mWatt
+ */
+STATIC INT32
+CpuPowerDecode (
+  IN      UINT8                           Encode,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT32                   Power;
+  ex1002_STRUCT    ex1002 ;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader);
+
+  //TdpWatt = TdpWattEncode / 1024
+  //PwrCpu / TdpWatt = Encode
+  //PwrCpu = Encode * TdpWattEncode / 1024
+
+  Power = (INT32) ((Encode * ex1002.Field.ex1002_0  *1000) / 1024);
+
+  return Power;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Encode the offset of power of CPU
+ *
+ *
+ *
+ * @param[in] NewPower    New power of mWatt
+ * @param[in] OrgPower    Original power of mWatt
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                Encode
+ */
+STATIC UINT8
+CpuPowerOffsetEncode (
+  IN      INT32                           NewPower,
+  IN      INT32                           OrgPower,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT8                    PowerOffsetEncode;
+  INT32                   PowerOffset;
+  ex1002_STRUCT    ex1002 ;
+  BOOLEAN                 Postive;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader);
+  if (NewPower > OrgPower) {
+    PowerOffset = NewPower - OrgPower;
+    Postive = TRUE;
+  } else {
+    PowerOffset = OrgPower - NewPower;
+    Postive = FALSE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu New Pwr %x (%d)\n", NewPower, NewPower);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu org Pwr %x (%d)\n", OrgPower, OrgPower);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Tdp2Watt %x, (%d)\n", ex1002.Field.ex1002_0 , ex1002.Field.ex1002_0 );
+  //Ceil of (mWatt *1024 / TdpWattEncode) / 1000 = Encode in watt
+  PowerOffset = (((PowerOffset * 1024) / ex1002.Field.ex1002_0 ) + 500) / 1000;
+
+  if (Postive) {
+    PowerOffsetEncode = (INT8) PowerOffset;
+  } else {
+    PowerOffsetEncode = 0 - (INT8) PowerOffset;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PowerOffsetEncode %x\n", PowerOffsetEncode);
+  return (UINT8) PowerOffsetEncode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode power of GPU out of Watt
+ *
+ *
+ *
+ * @param[in] Encode      PwrGpu encode
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                mWatt
+ */
+STATIC INT16
+GpuPowerDecode (
+  IN      UINT16                          Encode,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT16                   Power;
+
+  Power = (INT16) Encode;
+
+
+  return Power;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode Max Tj
+ *
+ *
+ *
+ * @param[in] Encode      Tj encode
+ * @retval                100 x Tj
+ */
+STATIC INT16
+TjMaxDecode (
+  IN      UINT8               Encode
+  )
+{
+  INT16    TjMax;
+
+  TjMax = (INT16) Encode;
+
+  return (TjMax * 100);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * for BAPMTI_TjOffset decoding
+ *
+ *
+ *
+ * @param[in] Encode      Tj encode
+ * @retval                100 x Tjoffset
+ */
+STATIC INT16
+TjOffsetDecode (
+  IN      UINT8               Encode
+  )
+{
+  UINT16      Number;
+  UINT8       Floating;
+  BOOLEAN     Postive;
+  UINT8       TjOffsetEncode;
+
+  TjOffsetEncode = Encode;
+  Postive = TRUE;
+
+  if (Encode == 0) {
+    return 0;
+  }
+
+  if ((TjOffsetEncode & 0x80) != 0) {
+    Postive = FALSE;
+    TjOffsetEncode = (UINT8) (~(Encode - 1));
+  }
+
+  Number = ((TjOffsetEncode >> 2) & 0x1F) * 100;
+
+  Floating = (TjOffsetEncode & 0x3);
+  if (Floating == 1) {
+    Number += 25;
+  } else if (Floating == 2) {
+    Number += 50;
+  } else if (Floating == 3) {
+    Number += 75;
+  } else {
+  }
+
+  if (Postive) {
+    return  (INT16) Number;
+  } else {
+    return (INT16) (0 - Number);
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Trinity SMU supports a software-writeable TjOffset (called swTjOffset) that can be programmed to
+ * account for underspec thermal solutions.
+ * There is a mechanism for customers to adjust TjOffset (via BAPM_PARAMETERS3.TjOffset)
+ * for under-performing thermal solutions.
+ * BIOS will adjust NomPow/MidPow/MaxPow based on this software-programmable TjOffset (called swTjOffset).
+ * SMU firmware will add this value to Fuse[TjOffset] for all TE's during BAPM calculations.
+ *
+ * Tj stands for junction temperature of the processor. However, here is a general description of
+ * our software-programmable TjOffset for BAPM (Birdirectional Application Power Management):
+ * "swTjOffset is an adjustable offset for BAPM thermal calculations to account for changes in
+ * junction temperature, TjOffset. For further details, see Thermal Guide."
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbSoftwareTjOffsetTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F860_STRUCT   D0F0xBC_x1F860;
+  D0F0xBC_x1F864_STRUCT   D0F0xBC_x1F864;
+  ex999_STRUCT    ex999 ;
+  D0F0xBC_x1F870_STRUCT   D0F0xBC_x1F870;
+  ex1000_STRUCT    ex1000 ;
+  ex1001_STRUCT    ex1001 ;
+
+  ex996_STRUCT   ex996;
+  ex997_STRUCT    ex997 ;
+  D0F0xBC_x1F6B4_STRUCT   D0F0xBC_x1F6B4;
+  ex998_STRUCT    ex998 ;
+  INT8                    SwTjOffset;
+  INT16                   Delta_T_org;
+  INT16                   Delta_T_new;
+  INT32                   Cpu_New_Pwr;
+  INT32                   Gpu_New_Pwr;
+
+  SwTjOffset = (INT8) UserOptions.CfgGnbSwTjOffset;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Enter\n");
+
+  IDS_OPTION_HOOK (IDS_GNB_PMM_SWTJOFFSET, &SwTjOffset, StdHeader);
+  if (SwTjOffset == 0) {
+    return;
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "User Input Tj Offset %x\n", SwTjOffset);
+  GnbRegisterReadTN (D0F0xBC_x1F860_TYPE, D0F0xBC_x1F860_ADDRESS, &D0F0xBC_x1F860, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F864_TYPE, D0F0xBC_x1F864_ADDRESS, &D0F0xBC_x1F864, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f868 , &ex999, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f898 , &ex1000, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f8c0 , &ex1001, 0, StdHeader);
+
+  //Tjoffset_new = Tjoffset_org + SwTjOffset
+  //Delta_T_org = T_die - Tjoffset_org - 45
+
+  //Delta_T_new = T_die - Tjoffset_new - 45
+  //            = T_die - (Tjoffset_org + SwTjOffset) - 45
+  //            = T_die - Tjoffset_org - SwTjOffset - 45
+
+  //Pwr_new = Pwr_org * (Delta_T_new/Delta_T_org)
+  //        = Pwr_org * (T_org - TjOffset) / T_org
+
+  //Cpu0
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_3 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_2  = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader), StdHeader);
+
+  //Cpu1
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_0 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_1, StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_1  = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader), StdHeader);
+
+  //GPU
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex997.Field.ex997_0  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader));
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex997.Field.ex997_1  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader));
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_0  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader));
+
+  //SwTjOffset
+  D0F0xBC_x1F6B4.Field.TjOffset = SwTjOffset;
+
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6ac , &ex996, 0, StdHeader);
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6b0 , &ex997, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F6B4_TYPE, D0F0xBC_x1F6B4_ADDRESS, &D0F0xBC_x1F6B4, 0, StdHeader);
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1F6B8 , &ex998, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init TDC
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC VOID
+GnbInitTdc (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_EARLY_PARAMS        *EarlyParams;
+  D0F0xBC_x1F62C_STRUCT   D0F0xBC_x1F62C;
+  D0F0xBC_x1F840_STRUCT   D0F0xBC_x1F840;
+
+  EarlyParams = (AMD_EARLY_PARAMS *) StdHeader;
+  D0F0xBC_x1F62C.Field.Idd = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10;
+  D0F0xBC_x1F62C.Field.Iddnb = EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F62C_TYPE, D0F0xBC_x1F62C_ADDRESS, &D0F0xBC_x1F62C, 0, StdHeader);
+
+  D0F0xBC_x1F840.Field.IddspikeOCP = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10;
+  D0F0xBC_x1F840.Field.IddNbspikeOCP = EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F840_TYPE, D0F0xBC_x1F840_ADDRESS, &D0F0xBC_x1F840, 0, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS                     Status;
+  GNB_HANDLE                       *GnbHandle;
+  UINT32                           Property;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Enter\n");
+  Property = TABLE_PROPERTY_DEAFULT;
+
+  //Check fuse to support BAPM disabled.
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+  if (D0F0xBC_xE0104188.Field.BapmDisable == 0) {
+    Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0;
+  }
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  // SMU LHTC support init
+  GnbBapmLhtcInitTN (StdHeader);
+
+  if ((Property & TABLE_PROPERTY_BAPM) == TABLE_PROPERTY_BAPM) {
+    GnbTjOffsetUpdateTN (StdHeader);
+    GnbSoftwareTjOffsetTN (StdHeader);
+    GnbBapmCalculateCoeffsTN (StdHeader);
+    GnbCacEnablement (StdHeader);
+    GnbBapmMeasuredTempTN (StdHeader);
+  } else {
+    //  If BAPM is disabled (either through fusing or CBS option), AGESA should enable LHTC algorithm.
+    //  Right now, LHTC is only enabled in the "DisableBAPM()" firmware routine, so unless Driver specifically calls this message,
+    //  LHTC will never be enabled if BAPM is disabled from the start.
+    GnbLhtcEnableTN (StdHeader);
+  }
+
+  GnbInitTdc (StdHeader);
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlyInitTableTN,
+             Property,
+             0,
+             StdHeader
+             );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEarlierInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_HANDLE                *GnbHandle;
+  D0F0xBC_xE0107060_STRUCT  D0F0xBC_xE0107060;
+  D0F0xBC_xE0001008_STRUCT  D0F0xBC_xE0001008;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Enter\n");
+
+  GnbAdjustSmuVidBeforeSmuTN (StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GnbRegisterReadTN (D0F0xBC_xE0107060_TYPE, D0F0xBC_xE0107060_ADDRESS, &D0F0xBC_xE0107060, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+  GfxRequestVoltageTN ((UINT8) D0F0xBC_xE0001008.Field.SClkVid1, StdHeader);
+  GfxRequestSclkTN ((UINT8) D0F0xBC_xE0107060.Field.SClkDpmDid1, StdHeader);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlierInitTableBeforeSmuTN,
+             0,
+             0,
+             StdHeader
+             );
+  GnbSmuFirmwareLoadV4 (GnbHandle->Address, (FIRMWARE_HEADER_V4*) &FirmwareTN[0], StdHeader);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlierInitTableAfterSmuTN,
+             0,
+             0,
+             StdHeader
+             );
+
+  GnbAdjustSmuVidAfterSmuTN (StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
new file mode 100644
index 0000000000..f98884dcf9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
@@ -0,0 +1,197 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbFuseTableTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "GnbFuseTable.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern GNB_TABLE ROMDATA      GnbEnvInitTableTN [];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS                   Status;
+  AMD_ENV_PARAMS                 *EnvParamsPtr;
+  UINT32                         Property;
+  GNB_HANDLE                     *GnbHandle;
+  D18F5x170_STRUCT               D18F5x170;
+  D0F0xBC_x1F8DC_STRUCT          D0F0xBC_x1F8DC;
+  PP_FUSE_ARRAY                  *PpFuseArray;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n");
+  Property = TABLE_PROPERTY_DEAFULT;
+  EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GnbLoadFuseTableTN (StdHeader);
+  Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader);
+  GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader);
+  GnbClumpUnitIdV4 (GnbHandle, StdHeader);
+  GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader);
+  Property |= GnbBuildOptions.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0;
+  Property |= GnbBuildOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0;
+  if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) {
+    Property |= TABLE_PROPERTY_IOMMU_DISABLED;
+  }
+
+  if (GnbBuildOptions.CfgNbdpmEnable) {
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      D18F5x170_ADDRESS,
+      &D18F5x170.Value,
+      0,
+      StdHeader
+    );
+    // Check if NbPstate enbale
+    if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) {
+      Property |= TABLE_PROPERTY_NBDPM;
+      PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+      if (PpFuseArray != NULL) {
+        // NBDPM is requesting SclkVid0 from the register.
+        // Write them back if SclkVid has been changed in PpFuseArray.
+        GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader);
+        if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) {
+          D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0];
+          D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1];
+          D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2];
+          D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3];
+          GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        }
+      }
+    }
+  }
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEnvInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
new file mode 100644
index 0000000000..c2bb8823ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
@@ -0,0 +1,1000 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Gnb fuse table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFuseTable.h"
+#include  "GnbFuseTableTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbFuseTableDebugDumpTN (
+  IN       PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+
+
+PP_FUSE_ARRAY  ex907  = {
+  0,                              // PP table revision
+  {1,    0,  0,  0,  0, 0},       // Valid DPM states
+  {0x40, 0,  0,  0,  0, 0},       // Sclk DPM DID
+  {0,    0,  0,  0,  0, 0},       // Sclk DPM VID
+  {0,    0,  0,  0,  0},          // Sclk DPM Cac
+  {1,    0,  0,  0,  0,  0},      // State policy flags
+  {2,    0,  0,  0,  0,  0},      // State policy label
+  {0x40, 0,  0,  0},              // VCLK DID
+  {0x40, 0,  0,  0},              // DCLK DID
+  8,                              // Thermal SCLK
+  {0,    0,  0,  0,  0,  0},      // Vclk/Dclk selector
+  {0,    0,  0,  0},              // Valid Lclk DPM states
+  {0x40, 0x40, 0x40, 0},          // Lclk DPM DID
+  {0x40, 0x40, 0x40, 0},          // Lclk DPM VID
+  {0,    0,  0,  0},              // Displclk DID
+  3,                              // Pcie Gen 2 VID
+  0x10,                           // Main PLL id for 3200 VCO
+  0,                              // WRCK SMU clock Divisor
+  {0x24, 0x24, 0x24, 0x24},       // SCLK VID
+  0,                              // GPU boost cap
+  {0, 0, 0, 0, 0, 0},             // Sclk DPM TDP limit
+  0,                              // TDP limit PG
+  0,                              // Boost margin
+  0,                              // Throttle margin
+  TRUE,                           // Support VCE in PP table
+  {0x3, 0xC, 0x30, 0xC0},         // VCE Flags
+  {0, 1, 0, 1},                   // MCLK for VCE
+  {0, 0, 0, 0},                   // SCLK selector for VCE
+  {0x40, 0x40, 0x40, 0x40}        // Eclk DID
+};
+
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104158_TABLE [] = {
+  {
+    D0F0xBC_xE0104158_EClkDid0_OFFSET,
+    D0F0xBC_xE0104158_EClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[0])
+  },
+  {
+    D0F0xBC_xE0104158_EClkDid1_OFFSET,
+    D0F0xBC_xE0104158_EClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[1])
+  },
+  {
+    D0F0xBC_xE0104158_EClkDid2_OFFSET,
+    D0F0xBC_xE0104158_EClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010415B_TABLE [] = {
+  {
+    D0F0xBC_xE010415B_EClkDid3_OFFSET,
+    D0F0xBC_xE010415B_EClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104184_TABLE [] = {
+  {
+    D0F0xBC_xE0104184_VCEFlag0_OFFSET,
+    D0F0xBC_xE0104184_VCEFlag0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[0])
+  },
+  {
+    D0F0xBC_xE0104184_VCEFlag1_OFFSET,
+    D0F0xBC_xE0104184_VCEFlag1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104187_TABLE [] = {
+  {
+    D0F0xBC_xE0104187_VCEFlag2_OFFSET,
+    D0F0xBC_xE0104187_VCEFlag2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104188_TABLE [] = {
+  {
+    D0F0xBC_xE0104188_VCEFlag3_OFFSET,
+    D0F0xBC_xE0104188_VCEFlag3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[3])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel0_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[0])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel1_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[1])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel2_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[2])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel3_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[3])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 0,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[0])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 1,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[1])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 2,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[2])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 3,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[3])
+  },
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106020_TABLE [] = {
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0])
+  },
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1])
+  },
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106023_TABLE [] = {
+  {
+    D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET,
+    D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106024_TABLE [] = {
+  {
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET,
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4])
+  },
+  {
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET,
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705C_TABLE [] = {
+  {
+    D0F0xBC_xE010705C_PowerplayTableRev_OFFSET,
+    D0F0xBC_xE010705C_PowerplayTableRev_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PPlayTableRev)
+  },
+  {
+    D0F0xBC_xE010705C_SClkThermDid_OFFSET,
+    D0F0xBC_xE010705C_SClkThermDid_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkThermDid)
+  },
+  {
+    D0F0xBC_xE010705C_PcieGen2Vid_OFFSET,
+    D0F0xBC_xE010705C_PcieGen2Vid_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PcieGen2Vid)
+  }
+};
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705F_TABLE [] = {
+  {
+    D0F0xBC_xE010705F_SClkDpmVid0_OFFSET,
+    D0F0xBC_xE010705F_SClkDpmVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0])
+  },
+  {
+    D0F0xBC_xE010705F_SClkDpmVid0_OFFSET,
+    D0F0xBC_xE010705F_SClkDpmVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107060_TABLE [] = {
+  {
+    D0F0xBC_xE0107060_SClkDpmVid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[2])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid3_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid4_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid0_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107063_TABLE [] = {
+  {
+    D0F0xBC_xE0107063_SClkDpmDid3_OFFSET,
+    D0F0xBC_xE0107063_SClkDpmDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107064_TABLE [] = {
+  {
+    D0F0xBC_xE0107064_SClkDpmDid4_OFFSET,
+    D0F0xBC_xE0107064_SClkDpmDid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107067_TABLE [] = {
+  {
+    D0F0xBC_xE0107067_DispClkDid0_OFFSET,
+    D0F0xBC_xE0107067_DispClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107068_TABLE [] = {
+  {
+    D0F0xBC_xE0107068_DispClkDid1_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[1])
+  },
+  {
+    D0F0xBC_xE0107068_DispClkDid2_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107068_DispClkDid3_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107068_LClkDpmDid0_OFFSET,
+    D0F0xBC_xE0107068_LClkDpmDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706B_TABLE [] = {
+  {
+    D0F0xBC_xE010706B_LClkDpmDid1_OFFSET,
+    D0F0xBC_xE010706B_LClkDpmDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706C_TABLE [] = {
+  {
+    D0F0xBC_xE010706C_LClkDpmDid2_OFFSET,
+    D0F0xBC_xE010706C_LClkDpmDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmDid3_OFFSET,
+    D0F0xBC_xE010706C_LClkDpmDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 0,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 1,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 2,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 3,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3])
+  },
+  {
+    D0F0xBC_xE010706C_DClkDid0_OFFSET,
+    D0F0xBC_xE010706C_DClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706F_TABLE [] = {
+  {
+    D0F0xBC_xE010706F_DClkDid1_OFFSET,
+    D0F0xBC_xE010706F_DClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107070_TABLE [] = {
+  {
+    D0F0xBC_xE0107070_DClkDid2_OFFSET,
+    D0F0xBC_xE0107070_DClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107070_DClkDid3_OFFSET,
+    D0F0xBC_xE0107070_DClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107070_VClkDid0_OFFSET,
+    D0F0xBC_xE0107070_VClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107073_TABLE [] = {
+  {
+    D0F0xBC_xE0107073_VClkDid1_OFFSET,
+    D0F0xBC_xE0107073_VClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[1])
+  },
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107074_TABLE [] = {
+  {
+    D0F0xBC_xE0107074_VClkDid2_OFFSET,
+    D0F0xBC_xE0107074_VClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107074_VClkDid3_OFFSET,
+    D0F0xBC_xE0107074_VClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107077_TABLE [] = {
+  {
+    D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET,
+    D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107078_TABLE [] = {
+  {
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET,
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET,
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[0])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[1])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[2])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[3])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[4])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707B_TABLE [] = {
+  {
+    D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET,
+    D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707C_TABLE [] = {
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[1])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[2])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[3])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[4])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707F_TABLE [] = {
+  {
+    D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET,
+    D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xFF000000_TABLE [] = {
+  {
+    D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET,
+    D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, MainPllId)
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0001008_TABLE [] = {
+  {
+    D0F0xBC_xE0001008_SClkVid0_OFFSET,
+    D0F0xBC_xE0001008_SClkVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[0])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid1_OFFSET,
+    D0F0xBC_xE0001008_SClkVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[1])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid2_OFFSET,
+    D0F0xBC_xE0001008_SClkVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[2])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid3_OFFSET,
+    D0F0xBC_xE0001008_SClkVid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[3])
+  }
+};
+
+
+FUSE_TABLE_ENTRY_TN  FuseRegisterTableTN [] = {
+  {
+    D0F0xBC_xE0104158_TYPE,
+    D0F0xBC_xE0104158_ADDRESS,
+    sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104158_TABLE
+  },
+  {
+    D0F0xBC_xE010415B_TYPE,
+    D0F0xBC_xE010415B_ADDRESS,
+    sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010415B_TABLE
+  },
+  {
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104184_TABLE
+  },
+  {
+    D0F0xBC_xE0104187_TYPE,
+    D0F0xBC_xE0104187_ADDRESS,
+    sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104187_TABLE
+  },
+  {
+    D0F0xBC_xE0104188_TYPE,
+    D0F0xBC_xE0104188_ADDRESS,
+    sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104188_TABLE
+  },
+  {
+    D0F0xBC_xE0106020_TYPE,
+    D0F0xBC_xE0106020_ADDRESS,
+    sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106020_TABLE
+  },
+  {
+    D0F0xBC_xE0106023_TYPE,
+    D0F0xBC_xE0106023_ADDRESS,
+    sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106023_TABLE
+  },
+  {
+    D0F0xBC_xE0106024_TYPE,
+    D0F0xBC_xE0106024_ADDRESS,
+    sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106024_TABLE
+  },
+  {
+    D0F0xBC_xE010705C_TYPE,
+    D0F0xBC_xE010705C_ADDRESS,
+    sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010705C_TABLE
+  },
+  {
+    D0F0xBC_xE010705F_TYPE,
+    D0F0xBC_xE010705F_ADDRESS,
+    sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010705F_TABLE
+  },
+  {
+    D0F0xBC_xE0107060_TYPE,
+    D0F0xBC_xE0107060_ADDRESS,
+    sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107060_TABLE
+  },
+  {
+    D0F0xBC_xE0107063_TYPE,
+    D0F0xBC_xE0107063_ADDRESS,
+    sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107063_TABLE
+  },
+  {
+    D0F0xBC_xE0107064_TYPE,
+    D0F0xBC_xE0107064_ADDRESS,
+    sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107064_TABLE
+  },
+  {
+    D0F0xBC_xE0107067_TYPE,
+    D0F0xBC_xE0107067_ADDRESS,
+    sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107067_TABLE
+  },
+  {
+    D0F0xBC_xE0107068_TYPE,
+    D0F0xBC_xE0107068_ADDRESS,
+    sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107068_TABLE
+  },
+  {
+    D0F0xBC_xE010706B_TYPE,
+    D0F0xBC_xE010706B_ADDRESS,
+    sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706B_TABLE
+  },
+  {
+    D0F0xBC_xE010706C_TYPE,
+    D0F0xBC_xE010706C_ADDRESS,
+    sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706C_TABLE
+  },
+  {
+    D0F0xBC_xE010706F_TYPE,
+    D0F0xBC_xE010706F_ADDRESS,
+    sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706F_TABLE
+  },
+  {
+    D0F0xBC_xE0107070_TYPE,
+    D0F0xBC_xE0107070_ADDRESS,
+    sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107070_TABLE
+  },
+  {
+    D0F0xBC_xE0107073_TYPE,
+    D0F0xBC_xE0107073_ADDRESS,
+    sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107073_TABLE
+  },
+  {
+    D0F0xBC_xE0107074_TYPE,
+    D0F0xBC_xE0107074_ADDRESS,
+    sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107074_TABLE
+  },
+  {
+    D0F0xBC_xE0107077_TYPE,
+    D0F0xBC_xE0107077_ADDRESS,
+    sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107077_TABLE
+  },
+  {
+    D0F0xBC_xE0107078_TYPE,
+    D0F0xBC_xE0107078_ADDRESS,
+    sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107078_TABLE
+  },
+  {
+    D0F0xBC_xE010707B_TYPE,
+    D0F0xBC_xE010707B_ADDRESS,
+    sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707B_TABLE
+  },
+  {
+    D0F0xBC_xE010707C_TYPE,
+    D0F0xBC_xE010707C_ADDRESS,
+    sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707C_TABLE
+  },
+  {
+    D0F0xBC_xE010707F_TYPE,
+    D0F0xBC_xE010707F_ADDRESS,
+    sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707F_TABLE
+  },
+  {
+    D0F0xBC_xFF000000_TYPE,
+    D0F0xBC_xFF000000_ADDRESS,
+    sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xFF000000_TABLE
+  },
+  {
+    D0F0xBC_xE0001008_TYPE,
+    D0F0xBC_xE0001008_ADDRESS,
+    sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0001008_TABLE
+  }
+};
+
+FUSE_TABLE_TN  FuseTableTN = {
+  sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN),
+  FuseRegisterTableTN
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Load Fuse Table TN
+ *
+ *
+ * @param[out] PpFuseArray      Pointer to save fuse table
+ * @param[in]  StdHeader        Pointer to Standard configuration
+ * @retval     AGESA_STATUS
+ */
+
+STATIC VOID
+NbFuseLoadFuseTableTN (
+     OUT   PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  FUSE_TABLE_TN             *FuseTable;
+  UINTN                     RegisterIndex;
+  FuseTable = &FuseTableTN;
+  for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) {
+    UINTN   FieldIndex;
+    UINTN   FuseRegisterTableLength;
+    UINT32  FuseValue;
+    FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength;
+
+    GnbRegisterReadTN (
+      FuseTable->FuseTable[RegisterIndex].RegisterSpaceType,
+      FuseTable->FuseTable[RegisterIndex].Register,
+      &FuseValue,
+      0,
+      StdHeader
+    );
+    for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength;  FieldIndex++) {
+      FUSE_REGISTER_ENTRY_TN   RegisterEntry;
+      RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex];
+      *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) &
+                                                            ((1 << RegisterEntry.FieldWidth) - 1));
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb load fuse table
+ *
+ *
+ *
+ * @param[in] StdHeader        Pointer to Standard configuration
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbLoadFuseTableTN (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PP_FUSE_ARRAY          *PpFuseArray;
+  AGESA_STATUS           Status;
+  D18F3xA0_STRUCT        D18F3xA0;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Enter\n");
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    //Support for real fuste table
+    GnbRegisterReadTN (D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader);
+    if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealFuseTable)) {
+      NbFuseLoadFuseTableTN (PpFuseArray, StdHeader);
+      PpFuseArray->VceSateTableSupport = TRUE;
+      IDS_HDT_CONSOLE (NB_MISC, "  Processor Fused\n");
+    } else {
+      LibAmdMemCopy (PpFuseArray, &ex907 , sizeof (PP_FUSE_ARRAY), StdHeader);
+      IDS_HDT_CONSOLE (NB_MISC, "  Processor Unfuse\n");
+    }
+  } else {
+    Status = AGESA_ERROR;
+  }
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader);
+  GnbFuseTableDebugDumpTN (PpFuseArray, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Exit [0x%x]\n", Status);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Debug dump fuse table
+ *
+ *
+ * @param[out] PpFuseArray      Pointer to save fuse table
+ * @param[in]  StdHeader        Pointer to Standard configuration
+ */
+
+VOID
+GnbFuseTableDebugDumpTN (
+  IN       PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINTN   Index;
+
+  IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n");
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->LclkDpmValid[Index]  != 0) {
+      IDS_HDT_CONSOLE (
+        NB_MISC,
+        "  LCLK DID[%d] - 0x%02x (%dMHz)\n",
+        Index,
+        PpFuseArray->LclkDpmDid[Index],
+        (PpFuseArray->LclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->LclkDpmDid[Index], StdHeader) / 100) : 0
+        );
+      IDS_HDT_CONSOLE (NB_MISC, "  LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]);
+    }
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->VclkDid[Index],
+      (PpFuseArray->VclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->VclkDid[Index], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  DCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->DclkDid[Index],
+      (PpFuseArray->DclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DclkDid[Index], StdHeader) / 100) : 0
+    );
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  DISPCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->DisplclkDid[Index],
+      (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DisplclkDid[Index], StdHeader) / 100) : 0
+      );
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  ECLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->EclkDid[Index],
+      (PpFuseArray->EclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->EclkDid[Index], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCE SCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]],
+      (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCE Flags[ % d] - 0x % 02x\n",
+      Index,
+      PpFuseArray->VceFlags[Index]
+      );
+  }
+  for (Index = 0; Index < 6; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  SCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->SclkDpmDid[Index],
+      (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], StdHeader) / 100) : 0
+    );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  SCLK TDP[%d] - 0x%x \n",
+      Index,
+      PpFuseArray->SclkDpmTdpLimit[Index]
+    );
+    IDS_HDT_CONSOLE (NB_MISC, "  SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]);
+  }
+  for (Index = 0; Index < 6; Index++) {
+    IDS_HDT_CONSOLE (NB_MISC, "  State #%d\n", Index);
+  }
+  IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h
new file mode 100644
index 0000000000..5d6177f1e0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fuse table initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBFUSETABLETN_H_
+#define _GNBFUSETABLETN_H_
+
+#pragma pack (push, 1)
+
+/// Fuse field entry
+typedef struct {
+  UINT8                    FieldOffset;              ///< Field offset in fuse register
+  UINT8                    FieldWidth;               ///< Width of field
+  UINT16                   FuseOffset;               ///< destination offset in translation table
+} FUSE_REGISTER_ENTRY_TN;
+
+/// Fuse register entry
+typedef struct {
+  UINT8                    RegisterSpaceType;        ///< Register type
+  UINT32                   Register;                 ///< FCR register address
+  UINT8                    FuseRegisterTableLength;  ///< Length of field table for this register
+  FUSE_REGISTER_ENTRY_TN   *FuseRegisterTable;       ///< Pointer to field table
+} FUSE_TABLE_ENTRY_TN;
+
+/// Fuse translation table
+typedef struct {
+  UINT8                    FuseTableLength;          ///< Length of translation table
+  FUSE_TABLE_ENTRY_TN      *FuseTable;               ///< Pointer to register table
+} FUSE_TABLE_TN;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+GnbLoadFuseTableTN (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h
new file mode 100644
index 0000000000..76196f1c08
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various TN definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBINITTN_H_
+#define _GNBINITTN_H_
+
+#define D0F0xBC_x1F468_TimerPeriod_Value  100000
+#define D0F0xBC_x1F46C_BapmPeriod_Value   1
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h
new file mode 100644
index 0000000000..e6ac431378
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h
@@ -0,0 +1,200 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Tn service installation file
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNB_INIT_TN_INSTALL_H_
+#define _GNB_INIT_TN_INSTALL_H_
+
+//-----------------------------------------------------------------------
+// Specify definition used by module services
+//-----------------------------------------------------------------------
+
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbFamServices.h"
+
+//-----------------------------------------------------------------------
+// Export services
+//-----------------------------------------------------------------------
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE)
+  extern F_PCIEFMGETCOMPLEXDATALENGTH             PcieGetComplexDataLengthTN;
+  extern F_PCIEFMBUILDCOMPLEXCONFIGURATION        PcieBuildComplexConfigurationTN;
+  extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION   PcieConfigureEnginesLaneAllocationTN;
+  extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING        PcieCheckPortPciDeviceMappingTN;
+  extern F_PCIEFMMAPPORTPCIADDRESS                PcieMapPortPciAddressTN;
+  extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED      PcieCheckPortPcieLaneCanBeMuxedTN;
+  extern F_PCIEFMGETSBCONFIGINFO                  PcieGetSbConfigInfoTN;
+  PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = {
+    PcieGetComplexDataLengthTN,
+    PcieBuildComplexConfigurationTN,
+    PcieConfigureEnginesLaneAllocationTN,
+    PcieCheckPortPciDeviceMappingTN,
+    PcieMapPortPciAddressTN,
+    PcieCheckPortPcieLaneCanBeMuxedTN,
+    PcieGetSbConfigInfoTN
+  };
+
+  GNB_SERVICE GnbPcieCongigServicesTN = {
+    GnbPcieFamConfigService,
+    AMD_FAMILY_TN,
+    &GnbPcieConfigProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbPcieCongigServicesTN
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  extern F_PCIEFMGETCORECONFIGURATIONVALUE        PcieGetCoreConfigurationValueTN;
+  extern F_PCIEFMGETLINKSPEEDCAP                  PcieGetLinkSpeedCapTN;
+  extern F_PCIEFMGETNATIVEPHYLANEBITMAP           PcieGetNativePhyLaneBitmapTN;
+  extern F_PCIEFMSETLINKSPEEDCAP                  PcieSetLinkSpeedCapV4;
+
+  PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = {
+    PcieGetCoreConfigurationValueTN,
+    PcieGetLinkSpeedCapTN,
+    PcieGetNativePhyLaneBitmapTN,
+    PcieSetLinkSpeedCapV4
+  };
+
+  GNB_SERVICE GnbPcieInitServicesTN = {
+    GnbPcieFamInitService,
+    AMD_FAMILY_TN,
+    &GnbPcieInitProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbPcieInitServicesTN
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  #if IDSOPT_IDS_ENABLED == TRUE
+    #if IDSOPT_TRACING_ENABLED == TRUE
+      extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING  PcieDebugGetHostRegAddressSpaceStringTN;
+      extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING          PcieDebugGetWrapperNameStringTN;
+      extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING    PcieDebugGetCoreConfigurationStringTN;
+
+      PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = {
+        PcieDebugGetHostRegAddressSpaceStringTN,
+        PcieDebugGetWrapperNameStringTN,
+        PcieDebugGetCoreConfigurationStringTN
+      };
+
+      GNB_SERVICE GnbPcieDebugServicesTN = {
+        GnbPcieFamDebugService,
+        AMD_FAMILY_TN,
+        &GnbPcieDebugProtocolTN,
+        SERVICES_POINTER
+      };
+      #undef  SERVICES_POINTER
+      #define SERVICES_POINTER  &GnbPcieDebugServicesTN
+    #endif
+  #endif
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  extern F_GNB_REGISTER_ACCESS  GnbRegisterReadServiceTN;
+  extern F_GNB_REGISTER_ACCESS  GnbRegisterWriteServiceTN;
+
+  GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = {
+    GnbRegisterReadServiceTN,
+    GnbRegisterWriteServiceTN
+  };
+
+  GNB_SERVICE GnbRegisterAccessServicesTN = {
+    GnbRegisterAccessService,
+    AMD_FAMILY_TN,
+    &GnbRegiterAccessProtocol,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbRegisterAccessServicesTN
+
+  extern F_GNBFMCREATEIVRSENTRY    GnbCreateIvrsEntryTN;
+  extern F_GNBFMCHECKIOMMUPRESENT  GnbCheckIommuPresentTN;
+
+  GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = {
+    GnbCheckIommuPresentTN,
+    GnbCreateIvrsEntryTN
+  };
+
+  GNB_SERVICE GnbIommuConfigServicesTN = {
+    GnbIommuService,
+    AMD_FAMILY_TN,
+    &GnbIommuConfigProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbIommuConfigServicesTN
+
+#endif
+#endif  // _GNB_INIT_TN_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
new file mode 100644
index 0000000000..8f176d77b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbIommu.h"
+#include  "GnbIvrsLib.h"
+#include  "GnbSbIommuLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbIommuIvrs.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbCreateIvhdHeaderTN (
+  IN       IVRS_BLOCK_TYPE            Type,
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbCreateIvhdTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbCreateIvhdrTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbCreateIvrsEntryTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GnbCheckIommuPresentTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU unit present and enabled
+ *
+ *
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+BOOLEAN
+GnbCheckIommuPresentTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  if (GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 0, 2, 0), StdHeader)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbCreateIvrsEntryTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  IVRS_IVHD_ENTRY                   *Ivhd;
+  UINT8                             IommuCapabilityOffset;
+  UINT32                            Value;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Entry\n");
+  if (Type == IvrsIvhdBlock || Type == IvrsIvhdrBlock) {
+    // Update IVINFO
+    IommuCapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, IommuCapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
+    ((IOMMU_IVRS_HEADER *) Ivrs)->IvInfo = Value & (IVINFO_HTATSRESV_MASK | IVINFO_VASIZE_MASK | IVINFO_GASIZE_MASK | IVINFO_PASIZE_MASK);
+
+    // Address of IVHD entry
+    Ivhd = (IVRS_IVHD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength);
+    GnbCreateIvhdHeaderTN (Type, Ivhd, StdHeader);
+    if (Type == IvrsIvhdBlock) {
+      GnbCreateIvhdTN (Ivhd, StdHeader);
+    } else {
+      GnbCreateIvhdrTN (Ivhd, StdHeader);
+    }
+    ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength = ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength + Ivhd->Length;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  Type            Block type
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdHeaderTN (
+  IN       IVRS_BLOCK_TYPE            Type,
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32    Value;
+  Ivhd->Type = (UINT8) Type;
+  Ivhd->Flags = IVHD_FLAG_COHERENT | IVHD_FLAG_IOTLBSUP | IVHD_FLAG_ISOC | IVHD_FLAG_RESPASSPW | IVHD_FLAG_PASSPW | IVHD_FLAG_PPRSUB | IVHD_FLAG_PREFSUP;
+  Ivhd->Length = sizeof (IVRS_IVHD_ENTRY);
+  Ivhd->DeviceId = 0x2;
+  Ivhd->CapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
+  Ivhd->PciSegment = 0;
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x4), AccessWidth32, &Ivhd->BaseAddress, StdHeader);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x8), AccessWidth32, (UINT8 *) &Ivhd->BaseAddress + 4, StdHeader);
+  Ivhd->BaseAddress = Ivhd->BaseAddress & 0xfffffffffffffffe;
+  ASSERT (Ivhd->BaseAddress != 0x0);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
+  Ivhd->IommuInfo = (UINT16) (Value & 0x1f) | (0x13 << IVHD_INFO_UNITID_OFFSET);
+  Ivhd->IommuEfr = (0 << IVHD_EFR_XTSUP_OFFSET) | (0 << IVHD_EFR_NXSUP_OFFSET) | (1 << IVHD_EFR_GTSUP_OFFSET) |
+                   (0 << IVHD_EFR_GLXSUP_OFFSET) | (1 << IVHD_EFR_IASUP_OFFSET) | (0 << IVHD_EFR_GASUP_OFFSET) |
+                   (0 << IVHD_EFR_HESUP_OFFSET) | (0x8 << IVHD_EFR_PASMAX_OFFSET) | (0 << IVHD_EFR_MSINUMPPR_OFFSET) |
+                   (4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHD entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Start;
+  PCI_ADDR  End;
+  Start.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, 0xFF, 0x1F, 6, 0);
+  GnbIvhdAddDeviceRangeEntry (Start, End, 0, Ivhd, StdHeader);
+  SbCreateIvhdEntries (Ivhd, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdrTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+
+
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
new file mode 100644
index 0000000000..626f33d3aa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
@@ -0,0 +1,574 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbFuseTable.h"
+#include  "heapManager.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbTable.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "OptionGnb.h"
+#include  "GfxLibTN.h"
+#include  "GnbFamServices.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern GNB_TABLE ROMDATA      GnbMidInitTableTN[];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUM_DPM_STATES 8
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Registers needs to be set if no GFX PCIe ports beeing us
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to PCIe_PLATFORM_CONFIG
+ */
+
+VOID
+STATIC
+GnbIommuMidInitCheckGfxPciePorts (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  BOOLEAN               GfxPciePortUsed;
+  D0F2xF4_x57_STRUCT    D0F2xF4_x57;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n");
+  GfxPciePortUsed = FALSE;
+
+  WrapperList = PcieConfigGetChildWrapper (Pcie);
+  ASSERT (WrapperList != NULL);
+  if (WrapperList->WrapId == GFX_WRAP_ID) {
+    PCIe_ENGINE_CONFIG   *EngineList;
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieConfigIsPcieEngine (EngineList)) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber);
+        if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+           ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) {
+          // GFX PCIe ports beeing used
+          GfxPciePortUsed = TRUE;
+          IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n");
+          break;
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+  }
+
+  if (!GfxPciePortUsed) {
+    //D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set
+    GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie));
+    D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1;
+    GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to for each PCIe port
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+GnbIommuMidInitOnPortCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GNB_TOPOLOGY_INFO           TopologyInfo;
+  D0F2xFC_x07_L1_STRUCT       D0F2xFC_x07_L1;
+  D0F2xFC_x0D_L1_STRUCT       D0F2xFC_x0D_L1;
+  UINT8                       L1cfgSel;
+  TopologyInfo.PhantomFunction = FALSE;
+  TopologyInfo.PcieToPciexBridge = FALSE;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    TopologyInfo.PhantomFunction = TRUE;
+    TopologyInfo.PcieToPciexBridge = TRUE;
+  } else {
+    if (PcieConfigIsSbPcieEngine (Engine)) {
+      PCI_ADDR  StartSbPcieDev;
+      PCI_ADDR  EndSbPcieDev;
+      StartSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 0, 0);
+      EndSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 7, 0);
+      GnbGetTopologyInfoV4 (StartSbPcieDev, EndSbPcieDev, &TopologyInfo, GnbLibGetHeader (Pcie));
+    } else {
+      GnbGetTopologyInfoV4 (Engine->Type.Port.Address, Engine->Type.Port.Address, &TopologyInfo, GnbLibGetHeader (Pcie));
+    }
+  }
+  L1cfgSel = (Engine->Type.Port.CoreId == 1) ? 1 : 0;
+  if (TopologyInfo.PhantomFunction) {
+    GnbRegisterReadTN (
+      D0F2xFC_x07_L1_TYPE,
+      D0F2xFC_x07_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x07_L1.Value,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+    D0F2xFC_x07_L1.Value |= BIT0;
+    GnbRegisterWriteTN (
+      D0F2xFC_x07_L1_TYPE,
+      D0F2xFC_x07_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x07_L1.Value,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  if (TopologyInfo.PcieToPciexBridge) {
+    GnbRegisterReadTN (
+      D0F2xFC_x0D_L1_TYPE,
+      D0F2xFC_x0D_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x0D_L1.Value,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+    D0F2xFC_x0D_L1.Field.VOQPortBits = 0x7;
+    GnbRegisterWriteTN (
+      D0F2xFC_x0D_L1_TYPE,
+      D0F2xFC_x0D_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x0D_L1.Value,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Orb/Ioc Cgtt Override setting
+ *
+ *
+ * @param[in]  Property   Property
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+VOID
+STATIC
+GnbCgttOverrideTN (
+  IN      UINT32                          Property,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  UINT32                          CGINDx0_Value;
+  UINT32                          CGINDx1_Value;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  AGESA_STATUS                    Status;
+  D0F0x64_x23_STRUCT              D0F0x64_x23;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Enter\n");
+
+  CGINDx0_Value = 0xFFFFFFFF;
+  //When orb clock gating is enabled in the BIOS clear CG_ORB_cgtt_lclk_override - bit 13
+  CGINDx1_Value = 0xFFFFFFFF;
+  if ((Property & TABLE_PROPERTY_ORB_CLK_GATING) == TABLE_PROPERTY_ORB_CLK_GATING) {
+    CGINDx1_Value &= 0xFFFFDFFF;
+  }
+  //When ioc clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 15
+  if ((Property & TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) == TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) {
+    CGINDx1_Value &= 0xFFFF7FFF;
+    if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) != TABLE_PROPERTY_IOMMU_DISABLED) {
+      //only IOMMU enabled and IOC clock gating enable
+      GnbRegisterReadTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, 0, StdHeader);
+      D0F0x64_x23.Field.SoftOverrideClk0 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk1 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk3 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk4 = 1;
+      GnbRegisterWriteTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+    }
+  }
+  //When smu sclk clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 18
+  if ((Property & TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) == TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) {
+    CGINDx1_Value &= 0xFFFBFFFF;
+  }
+
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  if (Status != AGESA_FATAL) {
+    if (Gfx->GmcClockGating) {
+      //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
+      // CGINDx0, clear bit 27, bit 28
+      CGINDx0_Value &= 0xE7FFFFFF;
+      GnbRegisterWriteTN (TYPE_CGIND, 0x0, &CGINDx0_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+      // CGINDx1, clear bit 11
+      CGINDx1_Value &= 0xFFFFF7FF;
+    }
+
+  }
+
+  if (CGINDx1_Value != 0xFFFFFFFF) {
+    GnbRegisterWriteTN (TYPE_CGIND, 0x1, &CGINDx1_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Exit\n");
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * IOMMU Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GnbIommuMidInit (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n");
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (Status == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      GnbIommuMidInitOnPortCallback,
+      NULL,
+      Pcie
+      );
+  }
+
+  GnbIommuMidInitCheckGfxPciePorts (Pcie);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * IOMMU Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GnbLclkDpmInitTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PP_FUSE_ARRAY             *PpFuseArray;
+  PCI_ADDR                  GnbPciAddress;
+  UINT32                    Index;
+  UINT8                     LclkDpmMode;
+  D0F0xBC_x1F200_STRUCT     D0F0xBC_x1F200[NUM_DPM_STATES];
+  D0F0xBC_x1F208_STRUCT     D0F0xBC_x1F208[NUM_DPM_STATES];
+  D0F0xBC_x1F210_STRUCT     D0F0xBC_x1F210[NUM_DPM_STATES];
+  D0F0xBC_x1F300_STRUCT     D0F0xBC_x1F300;
+  ex1003_STRUCT      ex1003 [NUM_DPM_STATES];
+  DOUBLE                    PcieCacLut;
+  ex1072_STRUCT      ex1072 ;
+  D0F0xBC_x1FE00_STRUCT     D0F0xBC_x1FE00;
+  D0F0xBC_x1F30C_STRUCT     D0F0xBC_x1F30C;
+  D18F3x64_STRUCT           D18F3x64;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n");
+  Status = AGESA_SUCCESS;
+  LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
+  IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
+  if (LclkDpmMode == LclkDpmRcActivity) {
+    PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+    if (PpFuseArray != NULL) {
+      Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+      if (Status == AGESA_SUCCESS) {
+        GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+        //Clear DPM_EN bit in LCLK_DPM_CNTL register
+        //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM
+        GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
+        D0F0xBC_x1F300.Field.LclkDpmEn = 0x0;
+        GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        GnbSmuServiceRequestV4 (
+          GnbPciAddress,
+          SMC_MSG_CONFIG_LCLK_DPM,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          StdHeader
+          );
+
+        //Initialize LCLK states
+        LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader);
+        LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
+        LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
+
+        D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0];
+        D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]];
+        D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf;
+
+        D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1];
+        D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]];
+        D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32;
+        D0F0xBC_x1F200[5].Field.StateValid = 0x1;
+
+        D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2];
+        D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]];
+        D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32;
+        D0F0xBC_x1F200[6].Field.StateValid = 0x1;
+
+        GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader);
+        PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 );
+        IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
+        D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
+        GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 );
+        ex1003[6].Field.ex1003_0  = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
+        IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
+
+        for (Index = 0; Index < NUM_DPM_STATES; ++Index) {
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F200_TYPE,
+            D0F0xBC_x1F200_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F200[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F208_TYPE,
+            D0F0xBC_x1F208_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F208[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F210_TYPE,
+            D0F0xBC_x1F210_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F210[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            TYPE_D0F0xBC ,
+            0x1f940  + Index * 4,
+            &ex1003[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+        }
+        //Enable LCLK DPM Voltage Scaling
+        GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
+        D0F0xBC_x1F300.Field.VoltageChgEn = 0x1;
+        D0F0xBC_x1F300.Field.LclkDpmEn = 0x1;
+        D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5;
+        GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+
+        //Programming Lclk Thermal Throttling Threshold
+        GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader);
+        GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader);
+        D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8);
+        D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8);
+        GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+
+        GnbSmuServiceRequestV4 (
+          GnbPciAddress,
+          SMC_MSG_CONFIG_LCLK_DPM,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          StdHeader
+          );
+      }
+    } else {
+      Status = AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Mid Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS      Status;
+  UINT32            Property;
+  AGESA_STATUS      AgesaStatus;
+  GNB_HANDLE        *GnbHandle;
+  UINT8             SclkDid;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Enter\n");
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+
+  Property = TABLE_PROPERTY_DEAFULT;
+  Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED;
+  Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0;
+  Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? TABLE_PROPERTY_ORB_CLK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIocLclkClockGatingEnable ? TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING : 0;
+  Property |= GnbFmCheckIommuPresent (GnbHandle, StdHeader) ? 0: TABLE_PROPERTY_IOMMU_DISABLED;
+  Property |= GnbBuildOptions.SmuSclkClockGatingEnable ? TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING : 0;
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) == 0) {
+    Status = GnbEnableIommuMmioV4 (GnbHandle, StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Status = GnbIommuMidInit (StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  //
+  // Set sclk to 100Mhz
+  //
+  SclkDid = GfxRequestSclkTNS3Save (
+              GfxLibCalculateDidTN (98 * 100, StdHeader),
+              StdHeader
+              );
+
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbMidInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  //
+  // Restore Sclk
+  //
+  GfxRequestSclkTNS3Save (
+    SclkDid,
+    StdHeader
+    );
+
+  GnbCgttOverrideTN (Property, StdHeader);
+
+  Status = GnbLclkDpmInitTN (StdHeader);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
new file mode 100644
index 0000000000..efa2af1256
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
@@ -0,0 +1,128 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbNbInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbPostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbPostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS     Status;
+  PCI_ADDR         GnbAddress;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Enter\n");
+  GnbAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  Status = GnbSetTom (GnbAddress, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
new file mode 100644
index 0000000000..8d36a1f620
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
@@ -0,0 +1,1334 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64211 $   @e \$Date: 2012-01-17 23:00:25 -0600 (Tue, 17 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define GNB_IGNORED_PARAM             0xFF
+#define ORB_WRITE_ENABLE              0x100
+#define IOMMU_L1_WRITE_ENABLE         0x80000000ul
+#define IOMMU_L2_WRITE_ENABLE         0x100
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbRegisterWriteTNDump (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value
+  );
+AGESA_STATUS
+GnbRegisterReadServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GnbRegisterWriteServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Config Dct and Mp.
+ *
+ *
+ *
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[in] StdHeader          Standard configuration header
+ *
+ * @return          true - Memory Pstate context has been changed
+ * @return          false - Memory Pstate context has not been changed
+ */
+STATIC BOOLEAN
+GnbDctMpConfigTN (
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // Select DCT and memory P-state, D18F1x10C[DctCfgSel], D18F1x10C[MemPsSel]
+  D18F1x10C_STRUCT      D18F1x10C;
+  BOOLEAN               MemPsChangd;
+  ACCESS_WIDTH          Width;
+
+  MemPsChangd = FALSE;
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS),
+    Width,
+    &D18F1x10C.Value,
+    StdHeader
+  );
+
+  if ((DctCfgSel != 0xFF) && (DctCfgSel < 2)) {
+    D18F1x10C.Field.DctCfgSel = DctCfgSel;
+  }
+
+  if ((MemPsSel != 0xFF) && (MemPsSel < 2) && (D18F1x10C.Field.MemPsSel != MemPsSel)) {
+    //Switches Mem Pstate
+    D18F1x10C.Field.MemPsSel = MemPsSel;
+    MemPsChangd = TRUE;
+  }
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS),
+    Width,
+    &D18F1x10C.Value,
+    StdHeader
+  );
+
+  return MemPsChangd;
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to Read Dct Additional Data.
+ *
+ *
+ *
+ * @param[in] Address            D18F2x9c Register offset
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[out] Value             Read value
+ * @param[in] StdHeader          Standard configuration header
+ */
+STATIC VOID
+GnbDctAdditionalDataReadTN (
+  IN       UINT32              Address,
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+     OUT   VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  D18F2x98_dct0_STRUCT  D18F2x98;
+  BOOLEAN               PstateChanged;
+  ACCESS_WIDTH          Width;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  PstateChanged = GnbDctMpConfigTN (
+                    DctCfgSel,
+                    MemPsSel,
+                    Flags,
+                    StdHeader
+                  );
+
+  // Clear DctAccessWrite
+  D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF;
+  D18F2x98.Field.DctAccessWrite = 0;
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)),
+    Width,
+    &D18F2x98.Value,
+    StdHeader
+  );
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)),
+    Width,
+    Value,
+    StdHeader
+  );
+
+  if (PstateChanged) {
+    GnbDctMpConfigTN (
+      DctCfgSel,
+      ((MemPsSel == 0) ? 1 : 0),
+      Flags,
+      StdHeader
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to Write Dct Additional Data.
+ *
+ *
+ *
+ * @param[in] Address            D18F2x9c Register offset
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[in] Value              Write value
+ * @param[in] StdHeader          Standard configuration header
+ */
+STATIC VOID
+GnbDctAdditionalDataWriteTN (
+  IN       UINT32              Address,
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  D18F2x98_dct0_STRUCT  D18F2x98;
+  BOOLEAN               PstateChanged;
+  ACCESS_WIDTH          Width;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  PstateChanged = GnbDctMpConfigTN (
+                    DctCfgSel,
+                    MemPsSel,
+                    Flags,
+                    StdHeader
+                  );
+
+  // Put write data on
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)),
+    Width,
+    Value,
+    StdHeader
+  );
+
+  // Set DctAccessWrite
+  D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF;
+  D18F2x98.Field.DctAccessWrite = 1;
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)),
+    Width,
+    &D18F2x98.Value,
+    StdHeader
+  );
+
+  if (PstateChanged) {
+    GnbDctMpConfigTN (
+      DctCfgSel,
+      ((MemPsSel == 0) ? 1 : 0),
+      Flags,
+      StdHeader
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to read all register spaces.
+ *
+ *
+ *
+ * @param[in] GnbHandle          GNB handle
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             Return value
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterReadServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return GnbRegisterReadTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to read all register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             Return value
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterReadTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  ACCESS_WIDTH          Width;
+  UINT32                TempValue;
+  UINT32                TempAddress;
+  BOOLEAN               PstateChanged;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+  TempAddress = 0;
+  TempValue = 0;
+
+
+  switch (RegisterSpaceType) {
+  case TYPE_D0F0:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D0F2:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F0:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 1, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F1:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 1, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_DxF0:
+    // Treat it as complete address for ports
+    GnbLibPciRead (
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F1:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F2:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F3:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 3, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F4:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 4, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F5:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 5, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x64:
+    // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00]
+    // Write enable bit7
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x98:
+    // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00]
+    // Write enable bit8
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xBC:
+    {
+    //SMU, access D0F0xBC_x[FFFFFFFF:00000000]
+    // No write enable
+      UINT64  TempData;
+      //ASSERT ((Address < 0xE0100000 || Address > 0xE0108FFFF) && (Address & 0x3) == 0);
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS),
+        (Address & (~0x3ull)),
+        Width,
+        &TempData,
+        StdHeader
+      );
+      if ((Address & 0x3) != 0) {
+        //Non aligned access allowed to fuse block
+        GnbLibPciIndirectRead (
+          MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS),
+          (Address & (~0x3ull)) + 4,
+          Width,
+          ((UINT32 *) &TempData) + 1,
+          StdHeader
+        );
+      }
+      * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8));
+      break;
+    }
+  case TYPE_D0F0xE4:
+    // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000]
+    // No write enable
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xF4:
+    // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00].
+    // Write enable bit8
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xFC:
+    // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0]
+    // Write enable bit31
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_DxF0xE4:
+    // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00]
+    // No write enable
+    TempValue = ((Address >> 16) & 0xFF);
+    TempAddress = Address & 0xFF;
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS
+      TempAddress,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_MSR:
+    LibAmdMsrRead  (Address, Value, StdHeader);
+    break;
+
+  case TYPE_GMM:
+    ASSERT (Address < 0x40000);
+
+    if ((Address >= 0x600) && (Address <= 0x8FF)) {
+      // CG
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0xE0002000 | (Address - 0x600)),
+        Width,
+        Value,
+        StdHeader
+      );
+    } else {
+      // SRBM
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0x80080000 | (Address & 0x3FFFF)),
+        Width,
+        Value,
+        StdHeader
+      );
+    }
+    break;
+
+  case TYPE_D18F2x9C_dct0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0:
+    GnbDctMpConfigTN (
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct0_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1:
+    GnbDctMpConfigTN (
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct1_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_CGIND:
+    // CG index
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8F8 - 0x600)),
+      Width,
+      &Address,
+      StdHeader
+    );
+    // CG data
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8FC - 0x600)),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+
+
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to write all register spaces.
+ *
+ *
+ *
+ * @param[in] GnbHandle          GnbHandle
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             The value to write
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterWriteServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return GnbRegisterWriteTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to write all register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             The value to write
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterWriteTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+
+  ACCESS_WIDTH          Width;
+  UINT32                TempValue;
+  UINT32                TempAddress;
+  PCI_ADDR              PciAddress;
+  BOOLEAN               PstateChanged;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+  TempAddress = 0;
+  TempValue = 0;
+
+  GNB_DEBUG_CODE (
+    GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
+  );
+
+  switch (RegisterSpaceType) {
+  case TYPE_D0F0:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D0F2:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F0:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 1, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F1:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 1, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_DxF0:
+    // Treat it as complete address for ports
+    GnbLibPciWrite (
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F1:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F2:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F3:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 3, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F4:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 4, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F5:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 5, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x64:
+    // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00]
+    // Write enable bit7
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      Address | IOC_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x98:
+    // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00]
+    // Write enable bit8
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS),
+      Address | ORB_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xBC:
+    //SMU, access D0F0xBC_x[FFFFFFFF:00000000]
+    // No write enable
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xE4:
+    // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000]
+    // No write enable
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xF4:
+    // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00].
+    // Write enable bit8
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS
+      Address | IOMMU_L2_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xFC:
+    // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0]
+    // Write enable bit31
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS
+      Address | IOMMU_L1_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_DxF0xE4:
+    // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00]
+    // No write enable
+    TempValue = ((Address >> 16) & 0xFF);
+    TempAddress = Address & 0xFF;
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS
+      TempAddress,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_MSR:
+    LibAmdMsrWrite  (Address, Value, StdHeader);
+    break;
+
+  case TYPE_GMM:
+    ASSERT (Address < 0x40000);
+
+    if ((Address >= 0x600) && (Address <= 0x8FF)) {
+      // CG
+      GnbLibPciIndirectWrite (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0xE0002000 | (Address - 0x600)),
+        Width,
+        Value,
+        StdHeader
+      );
+    } else {
+      // SRBM
+      GnbLibPciIndirectWrite (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0x80080000 | (Address & 0x3FFFF)),
+        Width,
+        Value,
+        StdHeader
+      );
+    }
+    break;
+
+  case TYPE_D18F2x9C_dct0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0:
+    GnbDctMpConfigTN (
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct0_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1:
+    GnbDctMpConfigTN (
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct1_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+      1,
+      1,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_CGIND:
+    // CG index
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8F8 - 0x600)),
+      Width,
+      &Address,
+      StdHeader
+    );
+    // CG data
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8FC - 0x600)),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_SMU_MSG:
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+    GnbSmuServiceRequestV4 (PciAddress, (UINT8) Address, Flags, StdHeader);
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to dump all write register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset
+ * @param[in] Value              The value to write
+ */
+VOID
+GnbRegisterWriteTNDump (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value
+  )
+{
+  IDS_HDT_CONSOLE (NB_MISC, "  R WRITE Space %s  Address 0x%04x, Value 0x%04x\n",
+    (RegisterSpaceType == TYPE_D0F0) ? "TYPE_D0F0" : (
+    (RegisterSpaceType == TYPE_D0F0x64) ? "TYPE_D0F0x64" : (
+    (RegisterSpaceType == TYPE_D0F0x98) ? "TYPE_D0F0x98" : (
+    (RegisterSpaceType == TYPE_D0F0xBC) ? "TYPE_D0F0xBC" : (
+    (RegisterSpaceType == TYPE_D0F0xE4) ? "TYPE_D0F0xE4" : (
+    (RegisterSpaceType == TYPE_DxF0) ? "TYPE_DxF0" : (
+    (RegisterSpaceType == TYPE_DxF0xE4) ? "TYPE_DxF0xE4" : (
+    (RegisterSpaceType == TYPE_D0F2) ? "TYPE_D0F2" : (
+    (RegisterSpaceType == TYPE_D0F2xF4) ? "TYPE_D0F2xF4" : (
+    (RegisterSpaceType == TYPE_D0F2xFC) ? "TYPE_D0F2xFC" : (
+    (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : (
+    (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : (
+    (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : (
+    (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : (
+    (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : (
+    (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : (
+    (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : (
+    (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : (
+    (RegisterSpaceType == TYPE_GMM) ? "TYPE_GMM" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : (
+    (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))))),
+    Address,
+    *((UINT32*)Value)
+  );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h
new file mode 100644
index 0000000000..6de5c469ae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBREGISTERACCTN_H_
+#define _GNBREGISTERACCTN_H_
+
+AGESA_STATUS
+GnbRegisterWriteTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GnbRegisterReadTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+// Marco
+// DxF0 Port space
+#define PORT_SPACE(Dev, Offset) MAKE_SBDFO (0, 0, Dev, 0, Offset)
+
+// DxF0xE4 Port indirect space
+#define PORTINDT_SPACE(Dev , Func, Offset) ((((UINT32) (Dev)) << 16) | (((UINT32) (Func)) << 8) | \
+                                             ((UINT32)(Offset)))
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
new file mode 100644
index 0000000000..8c44a71d89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
@@ -0,0 +1,14126 @@
+/**
+ * @file
+ *
+ * SMU firmware
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65874 $   @e \$Date: 2012-02-26 21:24:59 -0600 (Sun, 26 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBSMUFIRMWARETN_H_
+#define _GNBSMUFIRMWARETN_H_
+
+UINT32  FirmwareTN[] = {
+ 0x000a0004,
+ 0x00000040,
+ 0x000036a1,
+ 0x00010100,
+ 0xeee2b111,
+ 0x724cbe84,
+ 0xf7cde4cd,
+ 0xbf04e85e,
+ 0x9bdebdfc,
+ 0x0001d7f4,
+ 0x0001d904,
+ 0x00000000,
+ 0x0001d925,
+ 0x0001d934,
+ 0x0001d848,
+ 0x0001da6c,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xaa55aa55,
+ 0x98000000,
+ 0x98000000,
+ 0xd0000000,
+ 0x78010001,
+ 0x38210100,
+ 0xd0e10000,
+ 0xd1210000,
+ 0xf8000039,
+ 0x5b9d0000,
+ 0xf8000062,
+ 0xf80033ff,
+ 0xe0000098,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf8000044,
+ 0xf8003456,
+ 0xe000007d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0xf8000052,
+ 0xf800344e,
+ 0xe0000088,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf8000034,
+ 0xf8003458,
+ 0xe000006d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf800002c,
+ 0xf8003462,
+ 0xe0000065,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0xf8000025,
+ 0x34010002,
+ 0xf8003476,
+ 0xe000005d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf800001c,
+ 0xf8003464,
+ 0xe0000055,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x98000000,
+ 0x781c0001,
+ 0x3b9cebfc,
+ 0x781a0002,
+ 0x3b5a5b80,
+ 0x78010001,
+ 0x3821db84,
+ 0x78030001,
+ 0x3863e038,
+ 0x44230004,
+ 0x58200000,
+ 0x34210004,
+ 0xe3fffffd,
+ 0x34010000,
+ 0x34020000,
+ 0x78030001,
+ 0x3863fe80,
+ 0x58610000,
+ 0x58610018,
+ 0x34030000,
+ 0xf80002b5,
+ 0xf800013d,
+ 0x379cff80,
+ 0x5b810004,
+ 0x5b820008,
+ 0x5b83000c,
+ 0x5b840010,
+ 0x5b850014,
+ 0x5b860018,
+ 0x5b87001c,
+ 0x5b880020,
+ 0x5b890024,
+ 0x5b8a0028,
+ 0x5b9e0078,
+ 0x5b9f007c,
+ 0x2b810080,
+ 0x5b810074,
+ 0xbb800800,
+ 0x34210080,
+ 0x5b810070,
+ 0x98210800,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x379cff80,
+ 0x5b810004,
+ 0x5b820008,
+ 0x5b83000c,
+ 0x5b840010,
+ 0x5b850014,
+ 0x5b860018,
+ 0x5b87001c,
+ 0x5b880020,
+ 0x5b890024,
+ 0x5b8a0028,
+ 0x5b8b002c,
+ 0x5b8c0030,
+ 0x5b8d0034,
+ 0x5b8e0038,
+ 0x5b8f003c,
+ 0x5b900040,
+ 0x5b910044,
+ 0x5b920048,
+ 0x5b93004c,
+ 0x5b940050,
+ 0x5b950054,
+ 0x5b960058,
+ 0x5b97005c,
+ 0x5b980060,
+ 0x5b990064,
+ 0x5b9a0068,
+ 0x5b9b006c,
+ 0x5b9e0078,
+ 0x5b9f007c,
+ 0x2b810080,
+ 0x5b810074,
+ 0xbb800800,
+ 0x34210080,
+ 0x5b810070,
+ 0x98210800,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x34010002,
+ 0xd0010000,
+ 0x2b810004,
+ 0x2b820008,
+ 0x2b83000c,
+ 0x2b840010,
+ 0x2b850014,
+ 0x2b860018,
+ 0x2b87001c,
+ 0x2b880020,
+ 0x2b890024,
+ 0x2b8a0028,
+ 0x2b9d0074,
+ 0x2b9e0078,
+ 0x2b9f007c,
+ 0x2b9c0070,
+ 0x34000000,
+ 0xc3c00000,
+ 0x34010002,
+ 0xd0010000,
+ 0x2b810004,
+ 0x2b820008,
+ 0x2b83000c,
+ 0x2b840010,
+ 0x2b850014,
+ 0x2b860018,
+ 0x2b87001c,
+ 0x2b880020,
+ 0x2b890024,
+ 0x2b8a0028,
+ 0x2b8b002c,
+ 0x2b8c0030,
+ 0x2b8d0034,
+ 0x2b8e0038,
+ 0x2b8f003c,
+ 0x2b900040,
+ 0x2b910044,
+ 0x2b920048,
+ 0x2b93004c,
+ 0x2b940050,
+ 0x2b950054,
+ 0x2b960058,
+ 0x2b97005c,
+ 0x2b980060,
+ 0x2b990064,
+ 0x2b9a0068,
+ 0x2b9b006c,
+ 0x2b9d0074,
+ 0x2b9e0078,
+ 0x2b9f007c,
+ 0x2b9c0070,
+ 0x34000000,
+ 0xc3e00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0xf80000cc,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0xf80000cd,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfff4,
+ 0x5b8b000c,
+ 0x5b8c0008,
+ 0x5b9d0004,
+ 0x780c0001,
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+ 0x3401000c,
+ 0xb9601000,
+ 0xfbfffc79,
+ 0x29a20000,
+ 0x3ecc0002,
+ 0x78010001,
+ 0x3821dd8c,
+ 0xb5816000,
+ 0xb5c21000,
+ 0x28410004,
+ 0x378f0054,
+ 0xb9e01800,
+ 0x29820000,
+ 0x3791004c,
+ 0x36d60003,
+ 0xfbfffe7f,
+ 0xb9600800,
+ 0xb9e01000,
+ 0xba201800,
+ 0xfbfffc7a,
+ 0x2b820050,
+ 0x2b81004c,
+ 0x29a30000,
+ 0x0042001f,
+ 0x2e040004,
+ 0xb4220800,
+ 0xb5c31800,
+ 0x59810000,
+ 0x28610008,
+ 0x2e020006,
+ 0xb9601800,
+ 0xb4821000,
+ 0xfbfffe8b,
+ 0x3401000c,
+ 0xb9601000,
+ 0xfbfffc58,
+ 0x29a10000,
+ 0x29820004,
+ 0xb9e01800,
+ 0xb5c10800,
+ 0x2821000c,
+ 0xfbfffe65,
+ 0xb9600800,
+ 0xb9e01000,
+ 0xba201800,
+ 0xfbfffc60,
+ 0x2b820050,
+ 0x2b81004c,
+ 0x29a30000,
+ 0x0042001f,
+ 0x2e04000a,
+ 0xb4220800,
+ 0xb5c31800,
+ 0x59810004,
+ 0x28610010,
+ 0x2e020008,
+ 0xb9601800,
+ 0xb4441000,
+ 0xfbfffe71,
+ 0x3401000c,
+ 0xb9601000,
+ 0xfbfffc3e,
+ 0x29a10000,
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+ 0xb5c17000,
+ 0x29c10014,
+ 0xfbfffe4b,
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+ 0xba201800,
+ 0xfbfffc46,
+ 0x34040005,
+ 0x8e842000,
+ 0x2b810050,
+ 0x29850004,
+ 0x29830000,
+ 0x2b82004c,
+ 0x0021001f,
+ 0x14630004,
+ 0xb4411000,
+ 0x14a50004,
+ 0x14410004,
+ 0xb4651800,
+ 0xb4611800,
+ 0x37810074,
+ 0x59820008,
+ 0x3c840002,
+ 0x36940001,
+ 0xb4812000,
+ 0x2881fff0,
+ 0x7682000e,
+ 0xb4230800,
+ 0x5881fff0,
+ 0x4440ff94,
+ 0x2b830064,
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+ 0x5b820068,
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+ 0x780c0001,
+ 0x2b830064,
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+ 0x2b85006c,
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+ 0x3821dd2c,
+ 0x5825001c,
+ 0x58230014,
+ 0x58240018,
+ 0x2a420010,
+ 0xb9803800,
+ 0x00410018,
+ 0x3c210010,
+ 0x4c61000a,
+ 0x00410008,
+ 0x202100ff,
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+ 0x4c810006,
+ 0x2a410014,
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+ 0x3c210010,
+ 0x4ca10002,
+ 0xe000004b,
+ 0x34010001,
+ 0x32a10001,
+ 0x780c0001,
+ 0xb9800800,
+ 0x3821de44,
+ 0x2823000c,
+ 0x28250018,
+ 0x40240003,
+ 0x2a420028,
+ 0x206300ff,
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+ 0x3821dd2c,
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+ 0x0c25002e,
+ 0x3c630008,
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+ 0x3c420010,
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+ 0x2b810068,
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+ 0x48220002,
+ 0xe000000e,
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+ 0x2824001c,
+ 0x204200ff,
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+ 0xb5662000,
+ 0xb4c92800,
+ 0x2021003f,
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+ 0xb8651800,
+ 0xb8230800,
+ 0x0c410002,
+ 0xc3a00000,
+ 0x780600ff,
+ 0x38c6ffff,
+ 0xbcc24000,
+ 0xb8201800,
+ 0x78070001,
+ 0x74210007,
+ 0x74420017,
+ 0x38e7f6c4,
+ 0x34050000,
+ 0x34040017,
+ 0x5c250002,
+ 0x34050001,
+ 0xb8a20800,
+ 0x64210000,
+ 0x4420000b,
+ 0x50830002,
+ 0xb8801800,
+ 0xc8830800,
+ 0x94c10800,
+ 0x28e20000,
+ 0xa0280800,
+ 0x14210008,
+ 0x2021ffff,
+ 0xb8411000,
+ 0x58e20000,
+ 0xc3a00000,
+ 0x379cfff4,
+ 0x5b8b000c,
+ 0x5b8c0008,
+ 0x5b8d0004,
+ 0x00450010,
+ 0x004b0018,
+ 0xb8404800,
+ 0x780c0001,
+ 0xc80b1000,
+ 0xb8206800,
+ 0x20a500ff,
+ 0x398cf6c8,
+ 0x34420007,
+ 0x34070008,
+ 0x34060000,
+ 0x3cc80003,
+ 0x340a00ff,
+ 0xc8a80800,
+ 0xbd412000,
+ 0xb5a61800,
+ 0x34c60001,
+ 0x74c10004,
+ 0x50a7000a,
+ 0x30640000,
+ 0x30640005,
+ 0x35050008,
+ 0x51670006,
+ 0x95420800,
+ 0xa0810800,
+ 0x30610005,
+ 0x30610000,
+ 0xe0000004,
+ 0x34e70008,
+ 0x34420008,
+ 0x4420ffed,
+ 0x01270001,
+ 0x34060000,
+ 0xb5a61800,
+ 0x21210001,
+ 0x40650000,
+ 0x64240000,
+ 0x44a00012,
+ 0xb5861000,
+ 0x5c800005,
+ 0x40410000,
+ 0xb8250800,
+ 0x30410000,
+ 0xe0000002,
+ 0x30610000,
+ 0x20e20001,
+ 0x64410000,
+ 0xb5862000,
+ 0x5c200006,
+ 0x40620005,
+ 0x40810008,
+ 0xb8220800,
+ 0x30810008,
+ 0xe0000002,
+ 0x30620005,
+ 0x34c60001,
+ 0x74c10004,
+ 0x4420ffe8,
+ 0x2b8b000c,
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+ 0x2b8d0004,
+ 0x379c000c,
+ 0xc3a00000,
+ 0x379cffb4,
+ 0x5b8b0044,
+ 0x5b8c0040,
+ 0x5b8d003c,
+ 0x5b8e0038,
+ 0x5b8f0034,
+ 0x5b900030,
+ 0x5b91002c,
+ 0x5b920028,
+ 0x5b930024,
+ 0x5b940020,
+ 0x5b95001c,
+ 0x5b960018,
+ 0x5b970014,
+ 0x5b980010,
+ 0x5b99000c,
+ 0x5b9b0008,
+ 0x5b9d0004,
+ 0xb820d800,
+ 0x34160000,
+ 0xb7760800,
+ 0x40210000,
+ 0x4420008b,
+ 0x78170001,
+ 0x3ece0002,
+ 0xbae00800,
+ 0x3821d7e0,
+ 0xb5c10800,
+ 0x282b0000,
+ 0x356c0011,
+ 0xb9800800,
+ 0xfbfffc3b,
+ 0xb820c000,
+ 0x356d0001,
+ 0xb9a00800,
+ 0xfbfffc37,
+ 0xb8209800,
+ 0x356b0002,
+ 0xb9600800,
+ 0xfbfffc33,
+ 0xb8209000,
+ 0x7801e000,
+ 0x38211000,
+ 0x28210000,
+ 0x3b0f0009,
+ 0x20214000,
+ 0x4420000b,
+ 0x39ef0010,
+ 0xb9800800,
+ 0xb9e01000,
+ 0xfbfffc23,
+ 0xb9a00800,
+ 0x3a620200,
+ 0xfbfffc20,
+ 0xb9600800,
+ 0x3a420200,
+ 0xe0000003,
+ 0xb9800800,
+ 0xb9e01000,
+ 0xfbfffc1a,
+ 0xbae00800,
+ 0x3821d7e0,
+ 0xb5c10800,
+ 0x282c0000,
+ 0x39e20020,
+ 0x780bffff,
+ 0x35810011,
+ 0xfbfffc12,
+ 0x3a610200,
+ 0x396b1fff,
+ 0xa02b1000,
+ 0xb820a800,
+ 0x3842601f,
+ 0x35810001,
+ 0x3a540200,
+ 0xfbfffc0a,
+ 0xa28b5800,
+ 0x35810002,
+ 0x3962601f,
+ 0xfbfffc06,
+ 0x34100000,
+ 0x3e010002,
+ 0xbae06000,
+ 0x398cd7e0,
+ 0xb42c0800,
+ 0x282b0000,
+ 0x380d8000,
+ 0x37990048,
+ 0xb56d5800,
+ 0xb9600800,
+ 0xfbfffc00,
+ 0xb8207800,
+ 0xb7300800,
+ 0x302f0000,
+ 0x39ef0020,
+ 0x3411fff7,
+ 0xb9600800,
+ 0xa1f11000,
+ 0xfbfffbf3,
+ 0x36100001,
+ 0x76010004,
+ 0x4420ffec,
+ 0xb5cc0800,
+ 0x282b0000,
+ 0x34100000,
+ 0xb56d6000,
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+ 0xfbfffbef,
+ 0x382f0008,
+ 0xb9e01000,
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+ 0xfbfffbe6,
+ 0x340105dc,
+ 0xf80010cb,
+ 0xa1f17800,
+ 0xb9e01000,
+ 0xb9800800,
+ 0xfbfffbe0,
+ 0x356e0001,
+ 0xbaa01000,
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+ 0xfbfffbdc,
+ 0x356d0002,
+ 0xba801000,
+ 0xb9a00800,
+ 0xfbfffbd8,
+ 0x39ef0008,
+ 0xb9800800,
+ 0xb9e01000,
+ 0xfbfffbd4,
+ 0x35610011,
+ 0xbb001000,
+ 0xfbfffbd1,
+ 0xb9c00800,
+ 0xba601000,
+ 0xfbfffbce,
+ 0xb9a00800,
+ 0xba401000,
+ 0xfbfffbcb,
+ 0xb9800800,
+ 0xa1f11000,
+ 0xfbfffbc8,
+ 0x3e010002,
+ 0xbae01000,
+ 0x3842d7e0,
+ 0xb4220800,
+ 0x282b0000,
+ 0x38018000,
+ 0xb5615800,
+ 0xb9600800,
+ 0xfbfffbc4,
+ 0xb7301000,
+ 0x40420000,
+ 0x3403ff00,
+ 0xa0237800,
+ 0xb9600800,
+ 0xb9e21000,
+ 0xfbfffbb8,
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+ 0x76010004,
+ 0x4420ffee,
+ 0x36d60001,
+ 0x76c10004,
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+ 0x2b920028,
+ 0x2b930024,
+ 0x2b940020,
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+ 0x33830034,
+ 0xb8208000,
+ 0x3a52f6c8,
+ 0x5b830040,
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+ 0x5b830038,
+ 0x3383003c,
+ 0x5b830030,
+ 0x20840001,
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+ 0x20490001,
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+ 0x40e10000,
+ 0x34080000,
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+ 0xb64d3000,
+ 0x40c10038,
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+ 0x202100ff,
+ 0x5c200007,
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+ 0x3041fffc,
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+ 0x38210000,
+ 0xb8812000,
+ 0x204100f0,
+ 0x44200004,
+ 0x78010700,
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+ 0xbc610800,
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+ 0x2b920028,
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+ 0x5c2000b6,
+ 0x780eff00,
+ 0xb9c00800,
+ 0x3821ffff,
+ 0xa0410800,
+ 0x442000b1,
+ 0x78020001,
+ 0x3842f604,
+ 0x28410000,
+ 0x38210002,
+ 0x58410000,
+ 0xfbfff5d2,
+ 0x7801e030,
+ 0x38210000,
+ 0x340206ff,
+ 0x5822000c,
+ 0xb8201000,
+ 0x28410204,
+ 0x20210400,
+ 0x4420fffe,
+ 0x7803e030,
+ 0x78020008,
+ 0x38630000,
+ 0x38420000,
+ 0x28610204,
+ 0xa0220800,
+ 0x4420fffe,
+ 0x7810e000,
+ 0xba005800,
+ 0x396b000c,
+ 0x29640000,
+ 0x3402fffb,
+ 0x78010132,
+ 0xa0822000,
+ 0x78022000,
+ 0x7803f000,
+ 0x59640000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff602,
+ 0x29610000,
+ 0x340ffffe,
+ 0x78020001,
+ 0xa02f0800,
+ 0x59610000,
+ 0x3842f3a0,
+ 0x28420000,
+ 0x78010131,
+ 0x3821fff0,
+ 0xfbfff5e0,
+ 0x29a20000,
+ 0x78010111,
+ 0x38210012,
+ 0xfbfff5dc,
+ 0x29a20004,
+ 0x78010111,
+ 0x38210013,
+ 0xfbfff5d8,
+ 0x29a20008,
+ 0x78010211,
+ 0x38210012,
+ 0xfbfff5d4,
+ 0x29a2000c,
+ 0x78010211,
+ 0x38210013,
+ 0xfbfff5d0,
+ 0x78010131,
+ 0x38218040,
+ 0x34020001,
+ 0xfbfff5cc,
+ 0x78010131,
+ 0x38218041,
+ 0x34020001,
+ 0xfbfff5c8,
+ 0x78010131,
+ 0x38218042,
+ 0x34020001,
+ 0xfbfff5c4,
+ 0x78010131,
+ 0x38218043,
+ 0x34020001,
+ 0xfbfff5c0,
+ 0x4182003d,
+ 0x41830045,
+ 0x78010111,
+ 0x38210002,
+ 0xb8431000,
+ 0xa4401000,
+ 0x204200ff,
+ 0xfbfff5c2,
+ 0x4181003d,
+ 0x340d0000,
+ 0x5c2d0003,
+ 0x41810045,
+ 0x442d0006,
+ 0x78010111,
+ 0x34020001,
+ 0x38210010,
+ 0xfbfff5b9,
+ 0xe000000a,
+ 0x78010111,
+ 0x340200ff,
+ 0x38210002,
+ 0xfbfff5b4,
+ 0x78010131,
+ 0x38218070,
+ 0xb9e01000,
+ 0x340d0001,
+ 0xfbfff5b6,
+ 0x4182003e,
+ 0x41830046,
+ 0x78010211,
+ 0x38210002,
+ 0xb8431000,
+ 0xa4401000,
+ 0x204200ff,
+ 0xfbfff5a7,
+ 0x4181003e,
+ 0x5c200008,
+ 0x418b0046,
+ 0x5d600006,
+ 0x78010131,
+ 0x3402fffe,
+ 0x38218074,
+ 0xfbfff5a6,
+ 0xe0000007,
+ 0x78010211,
+ 0x65ab0000,
+ 0x38210010,
+ 0x34020001,
+ 0xfbfff599,
+ 0x5d600005,
+ 0x78010131,
+ 0x38218062,
+ 0x3802a000,
+ 0xfbfff594,
+ 0x78010132,
+ 0x7803f000,
+ 0x38630000,
+ 0x34020000,
+ 0x38218014,
+ 0xfbfff59c,
+ 0x78010130,
+ 0x7803f000,
+ 0x38630000,
+ 0x34020000,
+ 0x38218014,
+ 0xfbfff596,
+ 0xba001000,
+ 0x3842000c,
+ 0x28430000,
+ 0x3404fffd,
+ 0x78010131,
+ 0xa0641800,
+ 0x58430000,
+ 0x38218060,
+ 0x34020004,
+ 0xfbfff595,
+ 0x5d600006,
+ 0x78010131,
+ 0x7802ffff,
+ 0x38218062,
+ 0x38425fff,
+ 0xfbfff57f,
+ 0x78010311,
+ 0x38210011,
+ 0x34020300,
+ 0xfbfff56a,
+ 0x78010131,
+ 0x38218023,
+ 0x34020000,
+ 0xfbfff566,
+ 0x78030001,
+ 0x3863f6c4,
+ 0x28620000,
+ 0x39ceffff,
+ 0x78010001,
+ 0xa04e1000,
+ 0x38210000,
+ 0xb8411000,
+ 0x58620000,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b9d0004,
+ 0x379c001c,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f47c,
+ 0x40230003,
+ 0x78040001,
+ 0x78020001,
+ 0x7c610001,
+ 0x3884f39c,
+ 0x3842f6c4,
+ 0x5c200006,
+ 0x30430000,
+ 0x28810000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbffff22,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cffd0,
+ 0x5b8b0020,
+ 0x5b8c001c,
+ 0x5b8d0018,
+ 0x5b8e0014,
+ 0x5b8f0010,
+ 0x5b90000c,
+ 0x5b910008,
+ 0x5b9d0004,
+ 0x78100001,
+ 0xba000800,
+ 0x3821f6c4,
+ 0x28250000,
+ 0x78070001,
+ 0x38e7f478,
+ 0x34010000,
+ 0x3381002d,
+ 0x33810024,
+ 0x33810025,
+ 0x33810026,
+ 0x33810027,
+ 0x33810028,
+ 0x33810029,
+ 0x3381002a,
+ 0x3381002b,
+ 0x3381002c,
+ 0x28e20000,
+ 0x780f00ff,
+ 0xb9e02000,
+ 0x00410018,
+ 0xb8403000,
+ 0x3c210002,
+ 0x204cffff,
+ 0x34210008,
+ 0x202100ff,
+ 0x38840000,
+ 0x3c220010,
+ 0x7803ff00,
+ 0xa0a42800,
+ 0x3863ffff,
+ 0x00a50010,
+ 0xa1836000,
+ 0x3c210018,
+ 0x00c40010,
+ 0xb9826000,
+ 0x780e0001,
+ 0xb9816000,
+ 0x39cef6c8,
+ 0x20b100ff,
+ 0x208400ff,
+ 0x340b0000,
+ 0x01810010,
+ 0x948b1000,
+ 0x34210001,
+ 0x202100ff,
+ 0x356b0001,
+ 0x20420001,
+ 0x3c210010,
+ 0x75650003,
+ 0x64420000,
+ 0x44400004,
+ 0xa1836000,
+ 0xb9816000,
+ 0x44a0fff4,
+ 0x01820010,
+ 0x01810018,
+ 0x204200ff,
+ 0xc8410800,
+ 0x342b0001,
+ 0x780100ff,
+ 0xb8201800,
+ 0x3c420018,
+ 0x3863ffff,
+ 0xa1836000,
+ 0x75610003,
+ 0xb9826000,
+ 0x5c200010,
+ 0x00c10010,
+ 0xb8602800,
+ 0x202400ff,
+ 0x948b1000,
+ 0x01810018,
+ 0x356b0001,
+ 0x34210001,
+ 0x20420001,
+ 0x3c210018,
+ 0x75630003,
+ 0x64420000,
+ 0x5c400004,
+ 0xa1856000,
+ 0xb9816000,
+ 0x4460fff5,
+ 0x40e10000,
+ 0x68210003,
+ 0x5c20000d,
+ 0x21810007,
+ 0x4420000b,
+ 0x01820010,
+ 0x01810018,
+ 0x204200ff,
+ 0xfbfff82a,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffeb4,
+ 0x21810003,
+ 0x44200038,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210008,
+ 0x5c200033,
+ 0x378d0024,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfff833,
+ 0x340b0001,
+ 0x37850029,
+ 0xb5ab0800,
+ 0xb4ab1000,
+ 0x40210000,
+ 0x40420000,
+ 0xb5cb2000,
+ 0xb8220800,
+ 0x202100ff,
+ 0x202300f0,
+ 0x2021000f,
+ 0x44200005,
+ 0x40810010,
+ 0x202100f0,
+ 0x30810010,
+ 0xe0000006,
+ 0xb5cb1000,
+ 0x44600004,
+ 0x40410010,
+ 0x2021000f,
+ 0x30410010,
+ 0x356b0001,
+ 0x75610004,
+ 0x4420ffeb,
+ 0x78010131,
+ 0x38218014,
+ 0xfbfff4b5,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff4aa,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfffc0e,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfff906,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfff9eb,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff49d,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e200016,
+ 0x3a10f6c4,
+ 0x2a010000,
+ 0x39ef0000,
+ 0xa02f0800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba205800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff487,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff47e,
+ 0x2b8b0020,
+ 0x2b8c001c,
+ 0x2b8d0018,
+ 0x2b8e0014,
+ 0x2b8f0010,
+ 0x2b90000c,
+ 0x2b910008,
+ 0x2b9d0004,
+ 0x379c0030,
+ 0xc3a00000,
+ 0x379cffcc,
+ 0x5b8b0024,
+ 0x5b8c0020,
+ 0x5b8d001c,
+ 0x5b8e0018,
+ 0x5b8f0014,
+ 0x5b900010,
+ 0x5b91000c,
+ 0x5b920008,
+ 0x5b9d0004,
+ 0x78110001,
+ 0xba202000,
+ 0x3884f6c4,
+ 0x28830000,
+ 0x34010000,
+ 0x78020001,
+ 0x33810031,
+ 0x33810028,
+ 0x33810029,
+ 0x3381002a,
+ 0x3381002b,
+ 0x3381002c,
+ 0x3381002d,
+ 0x3381002e,
+ 0x3381002f,
+ 0x33810030,
+ 0x3842f478,
+ 0x40420000,
+ 0x781000ff,
+ 0xba000800,
+ 0x38210000,
+ 0xa0611800,
+ 0x204c00ff,
+ 0x00630010,
+ 0x21810001,
+ 0x780e0001,
+ 0x64210000,
+ 0x39cef6c8,
+ 0x207200ff,
+ 0x5c200003,
+ 0x3581ffff,
+ 0x202c00ff,
+ 0x3d810002,
+ 0x68430003,
+ 0x34210008,
+ 0x202100ff,
+ 0x34220007,
+ 0x3c420018,
+ 0x3c2d0010,
+ 0xb9a26800,
+ 0x5c600009,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x34020001,
+ 0x30820000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffe17,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f39c,
+ 0x28210000,
+ 0x01820001,
+ 0x20210008,
+ 0x344c0001,
+ 0x5c200043,
+ 0xb5cc5800,
+ 0x41610010,
+ 0x642100ff,
+ 0x5c20003f,
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+ 0x31630020,
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+ 0x31c40029,
+ 0xe0000007,
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+ 0x40230000,
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+ 0x30220000,
+ 0x378e0028,
+ 0x39ad0003,
+ 0xb9c00800,
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+ 0xfbfff77c,
+ 0x41610038,
+ 0xb5cc1000,
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+ 0xa4200800,
+ 0x30410000,
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+ 0x40420000,
+ 0xb8220800,
+ 0x202100ff,
+ 0x44200019,
+ 0x78010131,
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+ 0xfbfff409,
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+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff3fe,
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+ 0xfbfff85a,
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+ 0xfbfff93f,
+ 0xb9c00800,
+ 0xfbfff79e,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff3ef,
+ 0x39eff39c,
+ 0x29e10000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e400016,
+ 0x3a31f6c4,
+ 0x2a210000,
+ 0x3a100000,
+ 0xa0300800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba405800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff3da,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff3d1,
+ 0x2b8b0024,
+ 0x2b8c0020,
+ 0x2b8d001c,
+ 0x2b8e0018,
+ 0x2b8f0014,
+ 0x2b900010,
+ 0x2b91000c,
+ 0x2b920008,
+ 0x2b9d0004,
+ 0x379c0034,
+ 0xc3a00000,
+ 0x379cffd4,
+ 0x5b8b001c,
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+ 0x5b8d0014,
+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f6c4,
+ 0x28220000,
+ 0x780e00ff,
+ 0x780d0001,
+ 0x34010000,
+ 0x33810029,
+ 0x33810020,
+ 0x33810021,
+ 0x33810022,
+ 0x33810023,
+ 0x33810024,
+ 0x33810025,
+ 0x33810026,
+ 0x33810027,
+ 0x33810028,
+ 0xb9c00800,
+ 0x38210000,
+ 0x39adf39c,
+ 0xa0411000,
+ 0x29a30000,
+ 0x00420010,
+ 0x20610007,
+ 0x205000ff,
+ 0x44200009,
+ 0x00620010,
+ 0x00610018,
+ 0x204200ff,
+ 0xfbfff6ee,
+ 0x29a10000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffd7a,
+ 0x29a20000,
+ 0x20410003,
+ 0x4420001d,
+ 0x20410008,
+ 0x5c20001b,
+ 0x78010131,
+ 0x38218014,
+ 0xfbfff399,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff38e,
+ 0x29a20000,
+ 0x378c0020,
+ 0xb9800800,
+ 0xfbfff6f2,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfffaee,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfff7e6,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfff8cb,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff37d,
+ 0x29a10000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e000016,
+ 0x39eff6c4,
+ 0x29e10000,
+ 0x39ce0000,
+ 0xa02e0800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba005800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff369,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff360,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b9d0004,
+ 0x379c002c,
+ 0xc3a00000,
+ 0x379cffe8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f6c4,
+ 0x28220000,
+ 0x780d0131,
+ 0x780b0001,
+ 0x780100ff,
+ 0x38210000,
+ 0x39ad8010,
+ 0x396bf688,
+ 0xa0410800,
+ 0x44200084,
+ 0x780eff00,
+ 0xb9c00800,
+ 0x3821ffff,
+ 0xa0410800,
+ 0x5c20007f,
+ 0xb8206000,
+ 0xb5ac0800,
+ 0xfbfff341,
+ 0x59610000,
+ 0x358c0001,
+ 0x75810007,
+ 0x356b0004,
+ 0x4420fffa,
+ 0x78010201,
+ 0x38210011,
+ 0x780b0001,
+ 0xfbfff338,
+ 0x396bf6a8,
+ 0x59610000,
+ 0x78010111,
+ 0x38210012,
+ 0x780b0001,
+ 0xfbfff332,
+ 0x396bdf10,
+ 0x59610000,
+ 0x78010111,
+ 0x38210013,
+ 0xfbfff32d,
+ 0x59610004,
+ 0x78010211,
+ 0x38210012,
+ 0xfbfff329,
+ 0x59610008,
+ 0x78010211,
+ 0x38210013,
+ 0xfbfff325,
+ 0x5961000c,
+ 0x78010321,
+ 0x78028100,
+ 0x38420000,
+ 0x38210009,
+ 0xfbfff324,
+ 0x78010321,
+ 0x78028100,
+ 0x38420000,
+ 0x3821000a,
+ 0xfbfff31f,
+ 0x78010131,
+ 0x34020100,
+ 0x38218011,
+ 0xfbfff31b,
+ 0x78010132,
+ 0x78022000,
+ 0x7803f000,
+ 0x38420000,
+ 0x38630000,
+ 0x38218014,
+ 0xfbfff322,
+ 0x78010130,
+ 0x78021000,
+ 0x7803f000,
+ 0x38420000,
+ 0x38630000,
+ 0x38218014,
+ 0xfbfff31b,
+ 0x78010130,
+ 0x78021000,
+ 0x7803f000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff314,
+ 0x78010111,
+ 0x3402fffe,
+ 0x38210010,
+ 0xfbfff309,
+ 0x78010211,
+ 0x3402fffe,
+ 0x38210010,
+ 0xfbfff305,
+ 0x78010132,
+ 0x78023000,
+ 0x7803f000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff305,
+ 0x78010132,
+ 0x34020001,
+ 0x38218071,
+ 0xfbfff30a,
+ 0x7801e000,
+ 0x38212028,
+ 0x28220000,
+ 0x34010064,
+ 0x204b007f,
+ 0xf80003c1,
+ 0xf80003ac,
+ 0x7804e000,
+ 0xb8801800,
+ 0x3863000c,
+ 0x28610000,
+ 0x7802e030,
+ 0x38420000,
+ 0x38210004,
+ 0x58610000,
+ 0x340105ff,
+ 0x5841000c,
+ 0x28410204,
+ 0x20210400,
+ 0x5c20fffe,
+ 0xb8801800,
+ 0x3863000c,
+ 0x28620000,
+ 0xb9600800,
+ 0x39ceffff,
+ 0x38420003,
+ 0x58620000,
+ 0xf8000397,
+ 0x78020001,
+ 0x3842f604,
+ 0x28410000,
+ 0x3403fffd,
+ 0xa0230800,
+ 0x58410000,
+ 0xfbfff291,
+ 0xb9e01000,
+ 0x3842f6c4,
+ 0x28410000,
+ 0xa02e0800,
+ 0x58410000,
+ 0x2b8b0018,
+ 0x2b8c0014,
+ 0x2b8d0010,
+ 0x2b8e000c,
+ 0x2b8f0008,
+ 0x2b9d0004,
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+ 0xb8a12800,
+ 0x58450004,
+ 0x288f413c,
+ 0x01ee000b,
+ 0x304e0020,
+ 0x288f413c,
+ 0x01ee0013,
+ 0x304e0021,
+ 0x288f413c,
+ 0x28904140,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0022,
+ 0x288f4140,
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+ 0x288f4140,
+ 0x01ee000b,
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+ 0x01ee0013,
+ 0x304e0011,
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+ 0x28904144,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0013,
+ 0x288f4144,
+ 0x01ee0003,
+ 0x304e0014,
+ 0x288f4144,
+ 0x01ee000b,
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+ 0x01ee000b,
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+ 0x288f4148,
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+ 0x304e0051,
+ 0x288f4148,
+ 0x2890414c,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0052,
+ 0x288f414c,
+ 0x01ee0003,
+ 0x21ce0fff,
+ 0x0c4e0054,
+ 0x288f414c,
+ 0x01ee000f,
+ 0x21ce0fff,
+ 0x0c4e0056,
+ 0x288f414c,
+ 0x28904150,
+ 0x01e3001b,
+ 0x3e010005,
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+ 0x21ce0fff,
+ 0x0c4e0058,
+ 0x288f4150,
+ 0x01ee0007,
+ 0x21ce0fff,
+ 0x0c4e005a,
+ 0x288f4150,
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+ 0x21ce0fff,
+ 0x0c4e005c,
+ 0x288f4150,
+ 0x28904154,
+ 0x01e3001f,
+ 0x3e010001,
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+ 0x21ce0fff,
+ 0x0c4e005e,
+ 0x288f4154,
+ 0x3401c000,
+ 0x01ee000b,
+ 0x304e004c,
+ 0x288f4154,
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+ 0x304e004d,
+ 0x288f4154,
+ 0x28904158,
+ 0x2843004c,
+ 0x01e6001b,
+ 0x3e050005,
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+ 0xb8c57000,
+ 0x21c13fff,
+ 0xb8611800,
+ 0x5843004c,
+ 0x288f4158,
+ 0x01ee0009,
+ 0x21c10001,
+ 0x3c210017,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f415c,
+ 0xa0ed3800,
+ 0x01ee0006,
+ 0x21ce003f,
+ 0x304e0060,
+ 0x288f415c,
+ 0x01ee000c,
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+ 0x304e0061,
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+ 0x21ce003f,
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+ 0x21ce003f,
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+ 0x288f415c,
+ 0x28904160,
+ 0x01e3001e,
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+ 0x01e3001c,
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+ 0x01ee001a,
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+ 0x01ee000e,
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+ 0x78028001,
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+ 0x5c200068,
+ 0x780b8001,
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+ 0xd8200000,
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+ 0x78020001,
+ 0x3842db74,
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+ 0xd0450000,
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+ 0xd0010000,
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+ 0xb5470800,
+ 0x28210000,
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+ 0x5c20001a,
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+ 0x28820000,
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+ 0x00010e64,
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+ 0x00000000,
+ 0x0000715c,
+ 0x00000000,
+ 0x0000715d,
+ 0x00000000,
+ 0x00007162,
+ 0x00000000,
+ 0x00007117,
+ 0x00000000,
+ 0x00007157,
+ 0x00000000,
+ 0x00007106,
+ 0x00000000,
+ 0x0001ab20,
+ 0x00010788,
+ 0x0001a8d8,
+ 0x00019fec,
+ 0x0001a4a0,
+ 0x00019a00,
+ 0x0001a450,
+ 0x000199b4,
+ 0x0001a420,
+ 0x00011d94,
+ 0x00010418,
+ 0x00010430,
+ 0x00013138,
+ 0x00013d5c,
+ 0x00012398,
+ 0x00015970,
+ 0x0001244c,
+ 0x0001bb5c,
+ 0x0001b864,
+ 0x00012c48,
+ 0x00012300,
+ 0x00012354,
+ 0x00016834,
+ 0x00012530,
+ 0x00016e2c,
+ 0x0001a984,
+ 0x0001396c,
+ 0x0001aa60,
+ 0x00011e80,
+ 0x0001d380,
+ 0x00011bf8,
+ 0x00011b58,
+ 0x00014c0c,
+ 0x00014e28,
+ 0x0001a704,
+ 0x00019d34,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001c1a8,
+ 0x0001c1e0,
+ 0x00012f3c,
+ 0x0001724c,
+ 0x0001aab8,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001af7c,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001adb4,
+ 0x00012f34,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001d7ac,
+ 0x0001d7b0,
+ 0x00010788,
+ 0x000121b8,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00013340,
+ 0x0001420c,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
new file mode 100644
index 0000000000..75f8c9cb56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
@@ -0,0 +1,1121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "cpuFamRegisters.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = {
+  GNB_ENTRY_RMW (
+    D0F0x98_x07_TYPE,
+    D0F0x98_x07_ADDRESS,
+    D0F0x98_x07_SMUCsrIsocEn_MASK,
+    (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x1E_TYPE,
+    D0F0x98_x1E_ADDRESS,
+    D0F0x98_x1E_HiPriEn_MASK,
+    (1 << D0F0x98_x1E_HiPriEn_OFFSET)
+    ),
+
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = {
+ // Config GFX to legacy mode initially
+  GNB_ENTRY_RMW (
+    D0F0x64_x1D_TYPE,
+    D0F0x64_x1D_ADDRESS,
+    D0F0x64_x1D_IntGfxAsPcieEn_MASK,
+    0
+    ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F87C_TYPE,
+    D0F0xBC_x1F87C_ADDRESS,
+    D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK | D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F880_TYPE,
+    D0F0xBC_x1F880_ADDRESS,
+    D0F0xBC_x1F880_LL_VCE_LoadStep_MASK | D0F0xBC_x1F880_LL_UVD_LoadStep_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F884_TYPE,
+    D0F0xBC_x1F884_ADDRESS,
+    D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK | D0F0xBC_x1F884_LL_DCE_LoadStep_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F888_TYPE,
+    D0F0xBC_x1F888_ADDRESS,
+    D0F0xBC_x1F888_LL_GPU_LoadStep_MASK,
+    0
+  ),
+ // Configure load line VID
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F3D8_TYPE,
+    D0F0xBC_x1F3D8_ADDRESS,
+    (0x00 << D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET) |
+    (0xFE << D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET) |
+    (0xFC << D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET) |
+    (0xF6 << D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F3DC_TYPE,
+    D0F0xBC_x1F3DC_ADDRESS,
+    (0x08 << D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET) |
+    (0x06 << D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET) |
+    (0x04 << D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET) |
+    (0x02 << D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F404_TYPE,
+    D0F0xBC_x1F404_ADDRESS,
+    (0x19 << D0F0xBC_x1F404_LoadLineOffset3_OFFSET) |
+    (0x00 << D0F0xBC_x1F404_LoadLineOffset2_OFFSET) |
+    (0xE7 << D0F0xBC_x1F404_LoadLineOffset1_OFFSET) |
+    (0x00 << D0F0xBC_x1F404_LoadLineOffset0_OFFSET)
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH,
+    D0F0xBC_xE01040A8_TYPE,
+    D0F0xBC_xE01040A8_ADDRESS,
+    D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH,
+    D0F0xBC_xE01040A8_TYPE,
+    D0F0xBC_xE01040A8_ADDRESS,
+    D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH
+  ),
+ GNB_ENTRY_COPY (
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D18F5x188_TYPE,
+    D18F5x188_ADDRESS,
+    D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH
+  ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F3FC_TYPE,
+    D0F0xBC_x1F3FC_ADDRESS,
+    D0F0xBC_x1F3FC_SviVidStepBase_MASK | D0F0xBC_x1F3FC_SviVidStep_MASK,
+    (0x1838 << D0F0xBC_x1F3FC_SviVidStepBase_OFFSET) | (0x19 << D0F0xBC_x1F3FC_SviVidStep_OFFSET)
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK | D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK,
+    (2 << D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET) | (2 << D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET)
+  ),
+//  GNB_ENTRY_COPY (
+//    D18F5x188_TYPE,
+//    D18F5x188_ADDRESS,
+//    D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH,
+//    D0F0xBC_xE0104184_TYPE,
+//    D0F0xBC_xE0104184_ADDRESS,
+//    D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH
+//  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D18F5x188_TYPE,
+    D18F5x188_ADDRESS,
+    D18F5x188_NbLoadLineTrim_MASK,// | D18F5x188_NbOffsetTrim_MASK,
+    (3 << D18F5x188_NbLoadLineTrim_OFFSET)// | (2 << D18F5x188_NbOffsetTrim_OFFSET)
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreLoadLineTrim_MASK | D18F5x12C_CoreOffsetTrim_MASK,
+    (3 << D18F5x12C_CoreLoadLineTrim_OFFSET) | (2 << D18F5x12C_CoreOffsetTrim_OFFSET)
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVdd_MASK | D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK,
+    (3 << D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET) | (3 << D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET)
+  ),
+  // Enable SVI2
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_SviMode_MASK,
+    (1 << D0F0xBC_x1F428_SviMode_OFFSET)
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = {
+  GNB_ENTRY_WR (
+    D0F0x04_TYPE,
+    D0F0x04_ADDRESS,
+    (0x1 << D0F0x04_MemAccessEn_OFFSET) | (0x1 << D0F0x04_BusMasterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x4C_TYPE,
+    D0F0x4C_ADDRESS,
+    D0F0x4C_CfgRdTime_MASK,
+    0x2 << D0F0x4C_CfgRdTime_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x84_TYPE,
+    D0F0x84_ADDRESS,
+    D0F0x84_Ev6Mode_MASK,
+    0x1 << D0F0x84_Ev6Mode_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x64_x46_TYPE,
+    D0F0x64_x46_ADDRESS,
+    0x6 ,
+    1 << D0F0x64_x46_Msi64bitEn_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x0C_TYPE,
+    D0F0x98_x0C_ADDRESS,
+    D0F0x98_x0C_StrictSelWinnerEn_MASK,
+    1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET
+    ),
+  // Configure PM timer
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F468_TYPE,
+    D0F0xBC_x1F468_ADDRESS,
+    D0F0xBC_x1F468_TimerPeriod_MASK,
+    D0F0xBC_x1F468_TimerPeriod_Value << D0F0xBC_x1F468_TimerPeriod_OFFSET
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_EN_PM_CNTL,
+    0
+    ),
+  //Enable voltage controller
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_VoltageCntl_MASK,
+    1 << D0F0xBC_x1F460_VoltageCntl_OFFSET
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F384_TYPE,
+    D0F0xBC_x1F384_ADDRESS,
+    D0F0xBC_x1F384_FirmwareVid_OFFSET,
+    D0F0xBC_x1F384_FirmwareVid_WIDTH,
+    D0F0xBC_xE0001008_TYPE ,
+    D0F0xBC_xE0001008_ADDRESS,
+    D0F0xBC_xE0001008_SClkVid0_OFFSET,
+    D0F0xBC_xE0001008_SClkVid0_WIDTH
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_VOLTAGE_CNTL,
+    0
+    ),
+  GNB_ENTRY_POLL (
+    GMMx7B0_TYPE,
+    GMMx7B0_ADDRESS,
+    GMMx7B0_SMU_VOLTAGE_EN_MASK,
+    0x1 << GMMx7B0_SMU_VOLTAGE_EN_OFFSET
+    ),
+  // Enable thermal controller
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_ThermalCntl_MASK,
+    30 << D0F0xBC_x1F460_ThermalCntl_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F388_TYPE,
+    D0F0xBC_x1F388_ADDRESS,
+    D0F0xBC_x1F388_CsrAddr_MASK | D0F0xBC_x1F388_TcenId_MASK,
+    (0x9 << D0F0xBC_x1F388_CsrAddr_OFFSET) | (0xE << D0F0xBC_x1F388_TcenId_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_THERMAL_CNTL,
+    0
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_PstateMax_OFFSET,
+    D0F0xBC_x1F400_PstateMax_WIDTH,
+    TYPE_D18F3 ,
+    0xdc ,
+    8 ,
+    3
+    ),
+  // Configure VPC
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableVpcAccumulators_MASK,
+    (1 << D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_PstateAllCpusIdle_MASK | D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK,
+    (1 << D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_VpcPeriod_MASK,
+    (0x1B58 << D0F0xBC_x1F46C_VpcPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_VPC_ACCUMULATOR,
+    0
+    ),
+ // Enable TDC
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableTdcLimit_MASK,
+    (1 << D0F0xBC_x1F428_EnableTdcLimit_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F638_TYPE,
+    D0F0xBC_x1F638_ADDRESS,
+    D0F0xBC_x1F638_TdcPeriod_MASK,
+    (0x1 << D0F0xBC_x1F638_TdcPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_TDC_LIMIT,
+    0
+    ),
+
+  // Enable LPMx
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableLpmx_MASK,
+    (1 << D0F0xBC_x1F428_EnableLpmx_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_LpmxPeriod_MASK,
+    (1 << D0F0xBC_x1F46C_LpmxPeriod_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_LPMx,
+    0
+    ),
+  // Enable BAPM
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_BapmCoeffOverride_MASK,
+    (0x1 << D0F0xBC_x1F428_BapmCoeffOverride_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableBapm_MASK,
+    (1 << D0F0xBC_x1F428_EnableBapm_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_BapmPeriod_MASK,
+    (D0F0xBC_x1F46C_BapmPeriod_Value << D0F0xBC_x1F46C_BapmPeriod_OFFSET)
+    ),
+ // Config BAPM
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_BAPM,
+    0
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEnvInitTableTN [] = {
+//---------------------------------------------------------------------------
+// ORB Init
+//D0F0x98_x07[IocBwOptEn]
+//D0F0x98_x07[DropZeroMaskWrEn]
+//D0F0x98_x28[ForceCoherentIntr] = 1
+//D0F0x98_x07[UnadjustThrottlingStpclk ] = 1
+//D0F0x98_x07[MSIHTIntConversionEn] = 0
+//D0F0x98_x07[IommuBwOptEn] = 1
+//D0F0x98_x07[IommuIsocPassPWMode] = 1
+//D0F0x98_x08[NpWrrLenC] = 1
+//D0F0x98_x28[ForceCoherentIntr] = 1
+//D0F0x98_x2C[NBOutbWakeMask] = 1
+//D0F0x98_x2C[OrbRxIdlesMask] = 1
+
+  GNB_ENTRY_RMW (
+    D0F0x98_x07_TYPE,
+    D0F0x98_x07_ADDRESS,
+    D0F0x98_x07_UnadjustThrottlingStpclk_MASK | D0F0x98_x07_MSIHTIntConversionEn_MASK |
+    D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK |
+    D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK,
+    (0x1 << D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET) | (0x0 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) |
+    (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) |
+    (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x08_TYPE,
+    D0F0x98_x08_ADDRESS,
+    D0F0x98_x08_NpWrrLenC_MASK,
+    0x1 << D0F0x98_x08_NpWrrLenC_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x28_TYPE,
+    D0F0x98_x28_ADDRESS,
+    D0F0x98_x28_ForceCoherentIntr_MASK,
+    0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x2C_TYPE,
+    D0F0x98_x2C_ADDRESS,
+    D0F0x98_x2C_NBOutbWakeMask_MASK | D0F0x98_x2C_OrbRxIdlesMask_MASK,
+    (0x1 << D0F0x98_x2C_NBOutbWakeMask_OFFSET) | (0x1 << D0F0x98_x2C_OrbRxIdlesMask_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+//IOMMU L2 Initialization
+  GNB_ENTRY_RMW (
+    D0F2xF4_x10_TYPE,
+    D0F2xF4_x10_ADDRESS,
+    D0F2xF4_x10_DTCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x10_DTCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x11_TYPE,
+    D0F2xF4_x11_ADDRESS,
+    D0F2xF4_x11_DtcAddressMask_MASK | D0F2xF4_x11_DtcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x11_DtcAddressMask_OFFSET) | (0x1 << D0F2xF4_x11_DtcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x14_TYPE,
+    D0F2xF4_x14_ADDRESS,
+    D0F2xF4_x14_ITCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x14_ITCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x15_TYPE,
+    D0F2xF4_x15_ADDRESS,
+    D0F2xF4_x15_ITCAddressMask_MASK | D0F2xF4_x15_ItcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x15_ITCAddressMask_OFFSET) | (1 << D0F2xF4_x15_ItcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x18_TYPE,
+    D0F2xF4_x18_ADDRESS,
+    D0F2xF4_x18_PTCAInvalidationSel_MASK,
+    0x2 << D0F2xF4_x18_PTCAInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x19_TYPE,
+    D0F2xF4_x19_ADDRESS,
+    D0F2xF4_x19_PTCAAddressMask_MASK | D0F2xF4_x19_PtcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x19_PTCAAddressMask_OFFSET) | (1 << D0F2xF4_x19_PtcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x30_TYPE,
+    D0F2xF4_x30_ADDRESS,
+    D0F2xF4_x30_ERRRuleLock1_MASK,
+    0x1 << D0F2xF4_x30_ERRRuleLock1_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x34_TYPE,
+    D0F2xF4_x34_ADDRESS,
+    D0F2xF4_x34_L2aregHostPgsize_MASK | D0F2xF4_x34_L2aregGstPgsize_MASK,
+    (0x2 << D0F2xF4_x34_L2aregHostPgsize_OFFSET) | (0x2 <<  D0F2xF4_x34_L2aregGstPgsize_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x47_TYPE,
+    D0F2xF4_x47_ADDRESS,
+    D0F2xF4_x47_TwAtomicFilterEn_MASK | D0F2xF4_x47_TwNwEn_MASK,
+    (0x1 << D0F2xF4_x47_TwAtomicFilterEn_OFFSET) | (1 << D0F2xF4_x47_TwNwEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x4C_TYPE,
+    D0F2xF4_x4C_ADDRESS,
+    D0F2xF4_x4C_GstPartialPtcCntrl_MASK,
+    0x3 << D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x50_TYPE,
+    D0F2xF4_x50_ADDRESS,
+    D0F2xF4_x50_PDCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x50_PDCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x51_TYPE,
+    D0F2xF4_x51_ADDRESS,
+    D0F2xF4_x51_PDCAddressMask_MASK | D0F2xF4_x51_PdcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x51_PDCAddressMask_OFFSET) | (1 << D0F2xF4_x51_PdcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x56_TYPE,
+    D0F2xF4_x56_ADDRESS,
+    D0F2xF4_x56_CPFlushOnInv_MASK | D0F2xF4_x56_CPFlushOnWait_MASK,
+    (0x0 << D0F2xF4_x56_CPFlushOnInv_OFFSET) | (1 << D0F2xF4_x56_CPFlushOnWait_OFFSET)
+    ),
+
+  GNB_ENTRY_RMW (
+    D0F2xF4_x80_TYPE,
+    D0F2xF4_x80_ADDRESS,
+    D0F2xF4_x80_ERRRuleLock0_MASK,
+    0x1 << D0F2xF4_x80_ERRRuleLock0_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x90_TYPE,
+    D0F2xF4_x90_ADDRESS,
+    D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK,
+    (0x1 << D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x92_TYPE,
+    D0F2xF4_x92_ADDRESS,
+    D0F2xF4_x92_PprIntcoallesceEn_MASK | D0F2xF4_x92_PprIntreqdelay_MASK | D0F2xF4_x92_PprInttimedelay_MASK,
+    (0x0 << D0F2xF4_x92_PprIntcoallesceEn_OFFSET) | (0x20 << D0F2xF4_x92_PprIntreqdelay_OFFSET) | (0x15 << D0F2xF4_x92_PprInttimedelay_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x94_TYPE,
+    D0F2xF4_x94_ADDRESS,
+    D0F2xF4_x94_L2bregHostPgsize_MASK | D0F2xF4_x94_L2bregGstPgsize_MASK,
+    (0x2 << D0F2xF4_x94_L2bregHostPgsize_OFFSET) | (0x2ull << D0F2xF4_x94_L2bregGstPgsize_OFFSET)
+    ),
+//IOMMU L1 Initialization
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// IOMMU Initialization
+  GNB_ENTRY_RMW (
+    D0F2x70_TYPE,
+    D0F2x70_ADDRESS,
+    D0F2x70_PcSupW_MASK,
+    (0x0 << D0F2x70_PcSupW_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x64_x0D_TYPE,
+    D0F0x64_x0D_ADDRESS,
+    D0F0x64_x0D_PciDev0Fn2RegEn_MASK,
+    (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET)
+    ),
+// IOMMU L2 clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING,
+    D0F2xF4_x33_TYPE,
+    D0F2xF4_x33_ADDRESS,
+    D0F2xF4_x33_CKGateL2ARegsDisable_MASK | D0F2xF4_x33_CKGateL2ADynamicDisable_MASK | D0F2xF4_x33_CKGateL2ACacheDisable_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING,
+    D0F2xF4_x90_TYPE,
+    D0F2xF4_x90_ADDRESS,
+    D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK,
+    0x0
+    ),
+// IOMMU L1 clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// Configure IOMMU Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    0x0
+    ),
+// Hide IOMMU function if disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0x64_x0D_TYPE,
+    D0F0x64_x0D_ADDRESS,
+    D0F0x64_x0D_PciDev0Fn2RegEn_MASK,
+    0x0
+    ),
+  //NB P-state Configuration for Runtime
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_NBDPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableNbDpm_MASK,
+    (1 << D0F0xBC_x1F428_EnableNbDpm_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F638_TYPE,
+    D0F0xBC_x1F638_ADDRESS,
+    D0F0xBC_x1F638_NbdpmPeriod_MASK | D0F0xBC_x1F638_PginterlockPeriod_MASK,
+    (1 << D0F0xBC_x1F638_NbdpmPeriod_OFFSET) | (1 << D0F0xBC_x1F638_PginterlockPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH
+  ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Hysteresis_MASK | D0F0xBC_x1F5F8_SkipDPM0_MASK |
+    D0F0xBC_x1F5F8_SkipPG_MASK | D0F0xBC_x1F5F8_EnableNbPsi1_MASK | D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK,
+    (10 << D0F0xBC_x1F5F8_Hysteresis_OFFSET) | (1 << D0F0xBC_x1F5F8_SkipDPM0_OFFSET) |
+    (1 << D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET) | (1 << D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F6E4_TYPE,
+    D0F0xBC_x1F6E4_ADDRESS,
+    D0F0xBC_x1F6E4_DdrVoltFloor_MASK | D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK,
+    (0xFF << D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET) | (0xFF << D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_NBDPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_NBDPM,
+    0
+    ),
+
+//---------------------------------------------------------------------------
+// Configure PCIe Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LOADLINE_ENABLE,
+    TYPE_D0F0xBC ,
+    0x1f428 ,
+    0x40 ,
+    (1 << 6 )
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_LOADLINE_ENABLE,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_LOADLINE,
+    0
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbMidInitTableTN [] = {
+//---------------------------------------------------------------------------
+// Enable LCLK Deep Sleep
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LCLK_DEEP_SLEEP,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_DivId_MASK | GMMx7A0_RampDis_MASK | GMMx7A0_Hysteresis_MASK | GMMx7A0_SclkRunningMask_MASK | GMMx7A0_SmuBusyMask_MASK | GMMx7A0_PcieLclkIdle1Mask_MASK | GMMx7A0_PcieLclkIdle2Mask_MASK | GMMx7A0_L1imugfxIdleMask_MASK | GMMx7A0_L1imugppsbIdleMask_MASK | GMMx7A0_L1imubifIdleMask_MASK | GMMx7A0_L1imuintgenIdleMask_MASK | GMMx7A0_L2imuIdleMask_MASK | GMMx7A0_OrbIdleMask_MASK | GMMx7A0_OnInbWakeMask_MASK | GMMx7A0_OnInbWakeAckMask_MASK | GMMx7A0_OnOutbWakeMask_MASK | GMMx7A0_OnOutbWakeAckMask_MASK | GMMx7A0_DmaactiveMask_MASK,
+    (0x5 << GMMx7A0_DivId_OFFSET) | (0x0 << GMMx7A0_RampDis_OFFSET) | (0xF << GMMx7A0_Hysteresis_OFFSET) | (0x1 << GMMx7A0_SclkRunningMask_OFFSET) | (0x1 << GMMx7A0_SmuBusyMask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle1Mask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle2Mask_OFFSET) | (0x1 << GMMx7A0_L1imugfxIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imugppsbIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imubifIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imuintgenIdleMask_OFFSET) | (0x1 << GMMx7A0_L2imuIdleMask_OFFSET) | (0x1 << GMMx7A0_OrbIdleMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_DmaactiveMask_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_SclkRunningMask_MASK,
+    0x0
+    ),
+// Reset : 0, Enable : 1
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LCLK_DEEP_SLEEP,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_EnableDs_MASK,
+    (0x1 << GMMx7A0_EnableDs_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// LCLK DPM init
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0000120_TYPE,
+    D0F0xBC_xE0000120_ADDRESS,
+    D0F0xBC_xE0000120_BusyCntSel_MASK | D0F0xBC_xE0000120_ActivityCntRst_MASK |
+    D0F0xBC_xE0000120_PeriodCntRst_MASK | D0F0xBC_xE0000120_EnOrbUsCnt_MASK |
+    D0F0xBC_xE0000120_EnOrbDsCnt_MASK,
+    (0x3 << D0F0xBC_xE0000120_BusyCntSel_OFFSET) | (0 << D0F0xBC_xE0000120_ActivityCntRst_OFFSET) |
+    (0x0 << D0F0xBC_xE0000120_PeriodCntRst_OFFSET) | (0x1 << D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET) |
+    (0x1 << D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET)
+    ),
+  //Programming Lclk Thermal Throttling Threshold in GnbLclkDpmInitTN()
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F308_TYPE,
+    D0F0xBC_x1F308_ADDRESS,
+    D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK,
+    (0x1 << D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_LclkDpm_MASK,
+    (0x1 << D0F0xBC_x1F460_LclkDpm_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// ORB clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_ORB_CLK_GATING,
+    D0F0x98_x49_TYPE,
+    D0F0x98_x49_ADDRESS,
+    D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_ORB_CLK_GATING,
+    D0F0x98_x4A_TYPE,
+    D0F0x98_x4A_ADDRESS,
+    D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK,
+    (1 << D0F0x98_x4A_SoftOverrideClk0_OFFSET)
+    ),
+
+//---------------------------------------------------------------------------
+// IOC clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING,
+    D0F0x64_x22_TYPE,
+    D0F0x64_x22_ADDRESS,
+    D0F0x64_x22_SoftOverrideClk4_MASK | D0F0x64_x22_SoftOverrideClk3_MASK | D0F0x64_x22_SoftOverrideClk2_MASK | D0F0x64_x22_SoftOverrideClk1_MASK | D0F0x64_x22_SoftOverrideClk0_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING,
+    D0F0x64_x23_TYPE,
+    D0F0x64_x23_ADDRESS,
+    D0F0x64_x23_SoftOverrideClk4_MASK | D0F0x64_x23_SoftOverrideClk3_MASK | D0F0x64_x23_SoftOverrideClk2_MASK | D0F0x64_x23_SoftOverrideClk1_MASK | D0F0x64_x23_SoftOverrideClk0_MASK,
+    0x0
+    ),
+
+//---------------------------------------------------------------------------
+// Shutdown IOMMU if disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    1 << D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300018_P1Select_OFFSET) | (1 << D0F0xBC_xE0300018_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300208_TYPE,
+    0xe0300208 ,
+    D0F0xBC_xE0300208_P1IsoN_MASK,
+    0 << D0F0xBC_xE0300208_P1IsoN_OFFSET
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300208 ,
+    0x2000 ,
+    1 << 13
+    ),
+  GNB_ENTRY_STALL (10),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+  GNB_ENTRY_TERMINATE
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
new file mode 100644
index 0000000000..f3bf14af5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
@@ -0,0 +1,242 @@
+/**
+ * @file
+ *
+ * ALIB SSDT table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63659 $   @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBSSDTTNFM2_H_
+#define _PCIEALIBSSDTTNFM2_H_
+
+UINT8  AlibSsdtTNFM2[] = {
+  0x53, 0x53, 0x44, 0x54, 0x1F, 0x05, 0x00, 0x00,
+  0x02, 0xE2, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+  0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
+  0x00, 0x00, 0x00, 0x04, 0x10, 0x4A, 0x4F, 0x5C,
+  0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30,
+  0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31,
+  0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, 0x44,
+  0x30, 0x31, 0x41, 0x30, 0x31, 0x33, 0x14, 0x31,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x72, 0x41, 0x30,
+  0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60,
+  0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, 0x30,
+  0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, 0x81,
+  0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, 0x41, 0x30,
+  0x31, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x31, 0x35,
+  0x14, 0x32, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x72,
+  0x41, 0x30, 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C,
+  0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80,
+  0x41, 0x30, 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04,
+  0x5B, 0x81, 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03,
+  0x41, 0x30, 0x31, 0x35, 0x20, 0x70, 0x6A, 0x41,
+  0x30, 0x31, 0x35, 0x14, 0x1C, 0x41, 0x30, 0x31,
+  0x36, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x36, 0x68,
+  0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B,
+  0x60, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60,
+  0x5B, 0x01, 0x41, 0x30, 0x31, 0x37, 0x00, 0x14,
+  0x32, 0x41, 0x30, 0x31, 0x38, 0x02, 0x5B, 0x23,
+  0x41, 0x30, 0x31, 0x37, 0xFF, 0xFF, 0x70, 0x79,
+  0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00,
+  0x60, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE0,
+  0x69, 0x70, 0x41, 0x30, 0x30, 0x36, 0x60, 0x0A,
+  0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x31, 0x37,
+  0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x31, 0x39,
+  0x03, 0x5B, 0x23, 0x41, 0x30, 0x31, 0x37, 0xFF,
+  0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00,
+  0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, 0x37,
+  0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, 0x37,
+  0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, 0x30,
+  0x31, 0x37, 0x14, 0x1C, 0x41, 0x30, 0x32, 0x30,
+  0x04, 0x70, 0x41, 0x30, 0x31, 0x38, 0x68, 0x69,
+  0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, 0x60,
+  0x41, 0x30, 0x31, 0x39, 0x68, 0x69, 0x60, 0x5B,
+  0x01, 0x41, 0x30, 0x32, 0x31, 0x00, 0x14, 0x29,
+  0x41, 0x30, 0x30, 0x38, 0x03, 0x5B, 0x23, 0x41,
+  0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, 0x30, 0x30,
+  0x37, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, 0x60,
+  0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0xA4, 0x60,
+  0x14, 0x26, 0x41, 0x30, 0x31, 0x32, 0x04, 0x5B,
+  0x23, 0x41, 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41,
+  0x30, 0x30, 0x37, 0x68, 0x69, 0x6A, 0x41, 0x30,
+  0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00,
+  0x6B, 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0x14,
+  0x1E, 0x41, 0x30, 0x32, 0x32, 0x05, 0x70, 0x41,
+  0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x60, 0x7D,
+  0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, 0x30,
+  0x31, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x42,
+  0x05, 0x41, 0x30, 0x32, 0x33, 0x02, 0x70, 0x0A,
+  0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60,
+  0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, 0x7B,
+  0x41, 0x30, 0x30, 0x36, 0x68, 0x61, 0x0A, 0xFF,
+  0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, 0x00,
+  0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70,
+  0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4,
+  0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x32, 0x34,
+  0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01,
+  0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10,
+  0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52,
+  0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, 0x5B,
+  0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, 0x4D,
+  0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, 0x42,
+  0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, 0x46,
+  0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, 0x08,
+  0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, 0x03,
+  0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, 0x44,
+  0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, 0x17,
+  0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, 0x00,
+  0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, 0x41,
+  0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, 0x22,
+  0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, 0x42,
+  0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, 0x60,
+  0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF,
+  0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44,
+  0x41, 0x08, 0x41, 0x30, 0x32, 0x35, 0x11, 0x04,
+  0x0B, 0x00, 0x01, 0x14, 0x46, 0x08, 0x41, 0x30,
+  0x30, 0x39, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B,
+  0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00,
+  0x0A, 0x02, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x00, 0x30, 0x00, 0xE0,
+  0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0xFE,
+  0xFF, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0A, 0x01,
+  0x00, 0x00, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60,
+  0x79, 0x68, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30,
+  0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00,
+  0x30, 0x00, 0xE0, 0x60, 0xA2, 0x16, 0x92, 0x93,
+  0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x01,
+  0x00, 0x0A, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B,
+  0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00,
+  0x0A, 0x02, 0x08, 0x41, 0x30, 0x30, 0x32, 0x0A,
+  0x00, 0x08, 0x41, 0x30, 0x30, 0x33, 0x0A, 0x00,
+  0x08, 0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x14,
+  0x46, 0x0B, 0x41, 0x30, 0x30, 0x35, 0x01, 0x70,
+  0x7D, 0x79, 0x0A, 0x18, 0x0A, 0x03, 0x00, 0x0A,
+  0x04, 0x00, 0x62, 0xA0, 0x1C, 0x93, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x62, 0x0B, 0x24, 0x01, 0x41, 0x30, 0x30,
+  0x33, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x34,
+  0x70, 0x41, 0x30, 0x30, 0x36, 0x62, 0x0B, 0x24,
+  0x01, 0x63, 0xA0, 0x13, 0x93, 0x68, 0x0A, 0x00,
+  0x7D, 0x63, 0x7B, 0x41, 0x30, 0x30, 0x33, 0x0C,
+  0x00, 0x00, 0x40, 0x00, 0x00, 0x63, 0xA1, 0x09,
+  0x7B, 0x63, 0x0C, 0xFF, 0xFF, 0xBF, 0xFF, 0x63,
+  0x41, 0x30, 0x30, 0x37, 0x62, 0x0B, 0x24, 0x01,
+  0x63, 0xA0, 0x36, 0x93, 0x41, 0x30, 0x30, 0x32,
+  0x0A, 0x00, 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x08, 0x0A, 0x00, 0x0C, 0xFF, 0xFF,
+  0xFF, 0xFF, 0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00,
+  0x0A, 0x02, 0x61, 0xA0, 0x0C, 0x93, 0x61, 0x0A,
+  0x02, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x32,
+  0xA0, 0x1D, 0x93, 0x41, 0x30, 0x30, 0x32, 0x0A,
+  0x01, 0xA0, 0x09, 0x93, 0x68, 0x0A, 0x00, 0x70,
+  0x0A, 0x20, 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x21,
+  0x60, 0x41, 0x30, 0x30, 0x39, 0x60, 0x08, 0x41,
+  0x30, 0x31, 0x30, 0x0A, 0x00, 0x08, 0x41, 0x30,
+  0x31, 0x31, 0x0A, 0x00, 0x14, 0x48, 0x07, 0x41,
+  0x57, 0x41, 0x4B, 0x01, 0xA0, 0x40, 0x07, 0x93,
+  0x68, 0x0A, 0x03, 0xA0, 0x2E, 0x93, 0x41, 0x30,
+  0x31, 0x30, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x60, 0x41,
+  0x30, 0x30, 0x37, 0x0A, 0xC5, 0x0B, 0x70, 0x01,
+  0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01, 0x0A, 0x0E,
+  0x00, 0x00, 0x00, 0x70, 0x0A, 0x00, 0x41, 0x30,
+  0x31, 0x30, 0xA0, 0x3A, 0x93, 0x41, 0x30, 0x31,
+  0x31, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01,
+  0x00, 0x60, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00, 0x7D,
+  0x60, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00,
+  0x41, 0x30, 0x30, 0x39, 0x0A, 0x16, 0x70, 0x0A,
+  0x00, 0x41, 0x30, 0x31, 0x31, 0x14, 0x49, 0x08,
+  0x41, 0x50, 0x54, 0x53, 0x01, 0xA0, 0x41, 0x08,
+  0x93, 0x68, 0x0A, 0x03, 0x41, 0x30, 0x30, 0x35,
+  0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00,
+  0x60, 0xA0, 0x33, 0x92, 0x93, 0x7B, 0x60, 0x79,
+  0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x28, 0xF4, 0x01, 0x00, 0x7B, 0x60, 0x80,
+  0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00, 0x00,
+  0x41, 0x30, 0x30, 0x39, 0x0A, 0x16, 0x70, 0x0A,
+  0x01, 0x41, 0x30, 0x31, 0x31, 0x70, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x60,
+  0xA0, 0x26, 0x93, 0x7B, 0x60, 0x79, 0x0A, 0x01,
+  0x0A, 0x0E, 0x00, 0x00, 0x0A, 0x00, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x7D,
+  0x60, 0x79, 0x0A, 0x01, 0x0A, 0x0E, 0x00, 0x00,
+  0x70, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x30
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
new file mode 100644
index 0000000000..e9776d0be3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
@@ -0,0 +1,1065 @@
+/**
+ * @file
+ *
+ * ALIB SSDT table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBSSDTTNFS1_H_
+#define _PCIEALIBSSDTTNFS1_H_
+
+UINT8  AlibSsdtTNFS1[] = {
+  0x53, 0x53, 0x44, 0x54, 0xD4, 0x1E, 0x00, 0x00,
+  0x02, 0x5C, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+  0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
+  0x00, 0x00, 0x00, 0x04, 0x10, 0x8F, 0xEA, 0x01,
+  0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30,
+  0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30,
+  0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x32,
+  0x41, 0x30, 0x32, 0x39, 0x08, 0x41, 0x44, 0x30,
+  0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x33,
+  0x41, 0x30, 0x33, 0x30, 0x08, 0x41, 0x44, 0x30,
+  0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x34,
+  0x41, 0x30, 0x33, 0x31, 0x08, 0x41, 0x44, 0x30,
+  0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x35,
+  0x41, 0x30, 0x33, 0x32, 0x08, 0x41, 0x44, 0x30,
+  0x36, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
+  0x36, 0x41, 0x30, 0x33, 0x33, 0x08, 0x41, 0x44,
+  0x30, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44,
+  0x30, 0x38, 0x41, 0x30, 0x33, 0x34, 0x08, 0x41,
+  0x30, 0x33, 0x35, 0x0A, 0x00, 0x08, 0x41, 0x30,
+  0x33, 0x36, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33,
+  0x37, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x33, 0x38,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33, 0x39,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x30,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x30, 0x39,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x39,
+  0x41, 0x30, 0x31, 0x39, 0x08, 0x41, 0x30, 0x34,
+  0x31, 0x12, 0x12, 0x08, 0x0A, 0x01, 0x0A, 0x01,
+  0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01,
+  0x0A, 0x01, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x34,
+  0x32, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31,
+  0x37, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x31, 0x30,
+  0x12, 0x0A, 0x04, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x31, 0x30,
+  0x41, 0x30, 0x34, 0x34, 0x14, 0x44, 0x09, 0x41,
+  0x30, 0x34, 0x35, 0x09, 0x70, 0x83, 0x88, 0x68,
+  0x0A, 0x02, 0x00, 0x61, 0x70, 0x41, 0x30, 0x30,
+  0x33, 0x60, 0x70, 0x61, 0x41, 0x30, 0x33, 0x36,
+  0x7D, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x79,
+  0x0A, 0x01, 0x0A, 0x06, 0x00, 0x62, 0x7D, 0x79,
+  0x41, 0x30, 0x33, 0x36, 0x0A, 0x05, 0x00, 0x79,
+  0x41, 0x30, 0x33, 0x37, 0x0A, 0x06, 0x00, 0x63,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0x60,
+  0x0A, 0xF4, 0x80, 0x62, 0x00, 0x7B, 0x62, 0x63,
+  0x00, 0xA0, 0x07, 0x93, 0x61, 0x60, 0xA4, 0x0A,
+  0x00, 0x41, 0x30, 0x31, 0x33, 0x41, 0x30, 0x33,
+  0x36, 0xA0, 0x0E, 0x93, 0x41, 0x30, 0x32, 0x39,
+  0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01,
+  0xA0, 0x15, 0x91, 0x92, 0x94, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x04, 0xA4, 0x0A, 0x00, 0xA0, 0x0B,
+  0x93, 0x41, 0x30, 0x33, 0x35, 0x0A, 0x00, 0xA4,
+  0x0A, 0x00, 0x41, 0x30, 0x34, 0x36, 0xA4, 0x0A,
+  0x00, 0x14, 0x24, 0x41, 0x30, 0x34, 0x37, 0x01,
+  0x70, 0x41, 0x30, 0x34, 0x38, 0x68, 0x67, 0x70,
+  0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x60, 0xA0,
+  0x08, 0x92, 0x93, 0x60, 0x0A, 0x02, 0xA4, 0x67,
+  0x41, 0x30, 0x34, 0x36, 0xA4, 0x67, 0x14, 0x4E,
+  0x1B, 0x41, 0x30, 0x34, 0x38, 0x01, 0x08, 0x41,
+  0x30, 0x34, 0x39, 0x0A, 0x00, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x37, 0x70, 0x11, 0x03, 0x0A,
+  0x0A, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30,
+  0x35, 0x30, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x35,
+  0x30, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x35,
+  0x31, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x35, 0x31,
+  0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, 0x93,
+  0x41, 0x30, 0x33, 0x35, 0x0A, 0x00, 0xA4, 0x67,
+  0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x35, 0x32,
+  0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x35, 0x33,
+  0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, 0x34,
+  0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x35, 0x35,
+  0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x35, 0x36,
+  0x7B, 0x7A, 0x41, 0x30, 0x35, 0x32, 0x0A, 0x08,
+  0x00, 0x0A, 0xFF, 0x41, 0x30, 0x34, 0x39, 0xA2,
+  0x47, 0x05, 0x92, 0x94, 0x41, 0x30, 0x31, 0x37,
+  0x41, 0x30, 0x30, 0x31, 0xA0, 0x45, 0x04, 0x93,
+  0x41, 0x30, 0x31, 0x38, 0x41, 0x30, 0x31, 0x37,
+  0x0A, 0x01, 0x70, 0x41, 0x30, 0x31, 0x34, 0x79,
+  0x72, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x02, 0x00,
+  0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, 0x7A,
+  0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, 0x7B,
+  0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x61,
+  0xA0, 0x11, 0x90, 0x92, 0x95, 0x41, 0x30, 0x34,
+  0x39, 0x61, 0x92, 0x94, 0x41, 0x30, 0x34, 0x39,
+  0x62, 0xA5, 0x75, 0x41, 0x30, 0x31, 0x37, 0xA0,
+  0x0C, 0x94, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30,
+  0x30, 0x31, 0xA4, 0x67, 0xA0, 0x1E, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x38, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x35,
+  0x32, 0x88, 0x41, 0x30, 0x33, 0x38, 0x41, 0x30,
+  0x31, 0x37, 0x00, 0xA1, 0x16, 0xA0, 0x14, 0x92,
+  0x93, 0x83, 0x88, 0x41, 0x30, 0x33, 0x38, 0x41,
+  0x30, 0x31, 0x37, 0x00, 0x41, 0x30, 0x35, 0x32,
+  0xA4, 0x67, 0x70, 0x0A, 0x00, 0x88, 0x41, 0x30,
+  0x34, 0x32, 0x41, 0x30, 0x31, 0x37, 0x00, 0xA0,
+  0x15, 0x93, 0x41, 0x30, 0x35, 0x36, 0x0A, 0x00,
+  0x70, 0x0A, 0x00, 0x88, 0x41, 0x30, 0x33, 0x38,
+  0x41, 0x30, 0x31, 0x37, 0x00, 0xA0, 0x15, 0x93,
+  0x41, 0x30, 0x35, 0x36, 0x0A, 0x01, 0x70, 0x0A,
+  0x01, 0x88, 0x41, 0x30, 0x34, 0x32, 0x41, 0x30,
+  0x31, 0x37, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30,
+  0x35, 0x36, 0x0A, 0x02, 0x70, 0x0A, 0x01, 0x88,
+  0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x31, 0x37,
+  0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x35, 0x36,
+  0x0A, 0x03, 0x70, 0x0A, 0x02, 0x88, 0x41, 0x30,
+  0x34, 0x30, 0x41, 0x30, 0x31, 0x37, 0x00, 0xA0,
+  0x24, 0x93, 0x7B, 0x41, 0x30, 0x35, 0x33, 0x41,
+  0x30, 0x35, 0x34, 0x00, 0x0A, 0x01, 0x70, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x33, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x88, 0x41, 0x30, 0x34, 0x30, 0x41,
+  0x30, 0x31, 0x37, 0x00, 0x70, 0x0A, 0x02, 0x41,
+  0x30, 0x35, 0x31, 0xA4, 0x67, 0x14, 0x19, 0x41,
+  0x30, 0x31, 0x38, 0x09, 0xA0, 0x0F, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x33, 0x68, 0x00, 0x0A,
+  0x00, 0xA4, 0x0A, 0x00, 0xA4, 0x0A, 0x01, 0x14,
+  0x4F, 0x13, 0x41, 0x30, 0x35, 0x37, 0x09, 0x70,
+  0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x70, 0x0A,
+  0x03, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x70, 0x0A,
+  0x00, 0x88, 0x67, 0x0A, 0x01, 0x00, 0x70, 0x0A,
+  0x00, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x70, 0x83,
+  0x88, 0x68, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x33,
+  0x35, 0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00,
+  0x0A, 0x60, 0x0A, 0xF4, 0x60, 0xA0, 0x19, 0x93,
+  0x41, 0x30, 0x33, 0x35, 0x0A, 0x01, 0xA0, 0x0B,
+  0x93, 0x7B, 0x60, 0x0A, 0x01, 0x00, 0x0A, 0x01,
+  0xA4, 0x67, 0x7D, 0x60, 0x0A, 0x01, 0x60, 0xA0,
+  0x1B, 0x93, 0x41, 0x30, 0x33, 0x35, 0x0A, 0x00,
+  0xA0, 0x0B, 0x93, 0x7B, 0x60, 0x0A, 0x01, 0x00,
+  0x0A, 0x00, 0xA4, 0x67, 0x7B, 0x60, 0x80, 0x0A,
+  0x01, 0x00, 0x60, 0x7D, 0x60, 0x79, 0x41, 0x30,
+  0x32, 0x39, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xF4,
+  0x60, 0x41, 0x30, 0x35, 0x38, 0x71, 0x41, 0x30,
+  0x33, 0x39, 0x71, 0x41, 0x30, 0x33, 0x38, 0x41,
+  0x30, 0x31, 0x33, 0x41, 0x30, 0x33, 0x36, 0xA0,
+  0x0E, 0x93, 0x41, 0x30, 0x32, 0x39, 0x0A, 0x04,
+  0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, 0xA0, 0x4E,
+  0x08, 0x90, 0x94, 0x41, 0x30, 0x32, 0x39, 0x0A,
+  0x01, 0x95, 0x41, 0x30, 0x32, 0x39, 0x0A, 0x04,
+  0xA0, 0x46, 0x05, 0x93, 0x41, 0x30, 0x32, 0x39,
+  0x0A, 0x02, 0x41, 0x30, 0x35, 0x38, 0x71, 0x41,
+  0x30, 0x33, 0x33, 0x71, 0x41, 0x30, 0x31, 0x39,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0xA2,
+  0x37, 0x92, 0x94, 0x41, 0x30, 0x31, 0x37, 0x41,
+  0x30, 0x30, 0x31, 0xA0, 0x26, 0x92, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x34, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41,
+  0x30, 0x33, 0x34, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x88, 0x41, 0x30, 0x31, 0x39, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x75, 0x41, 0x30, 0x31, 0x37, 0xA1,
+  0x21, 0x41, 0x30, 0x35, 0x38, 0x71, 0x41, 0x30,
+  0x34, 0x31, 0x71, 0x41, 0x30, 0x31, 0x39, 0x70,
+  0x83, 0x88, 0x41, 0x30, 0x33, 0x33, 0x0A, 0x06,
+  0x00, 0x88, 0x41, 0x30, 0x31, 0x39, 0x0A, 0x06,
+  0x00, 0x41, 0x30, 0x34, 0x36, 0xA4, 0x67, 0x08,
+  0x41, 0x30, 0x35, 0x39, 0x12, 0x12, 0x08, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x14,
+  0x46, 0x11, 0x41, 0x30, 0x34, 0x36, 0x08, 0x70,
+  0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30,
+  0x35, 0x38, 0x71, 0x41, 0x30, 0x34, 0x31, 0x71,
+  0x41, 0x30, 0x35, 0x39, 0xA2, 0x30, 0x92, 0x94,
+  0x41, 0x30, 0x31, 0x37, 0x41, 0x30, 0x30, 0x31,
+  0xA0, 0x1F, 0x93, 0x41, 0x30, 0x31, 0x38, 0x41,
+  0x30, 0x31, 0x37, 0x0A, 0x01, 0x70, 0x41, 0x30,
+  0x36, 0x30, 0x41, 0x30, 0x31, 0x37, 0x88, 0x41,
+  0x30, 0x35, 0x39, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x75, 0x41, 0x30, 0x31, 0x37, 0xA0, 0x1F, 0x92,
+  0x93, 0x89, 0x41, 0x30, 0x34, 0x32, 0x01, 0x0A,
+  0x01, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41,
+  0x30, 0x35, 0x38, 0x71, 0x41, 0x30, 0x34, 0x31,
+  0x71, 0x41, 0x30, 0x35, 0x39, 0xA0, 0x1F, 0x92,
+  0x93, 0x89, 0x41, 0x30, 0x35, 0x39, 0x01, 0x0A,
+  0x02, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41,
+  0x30, 0x36, 0x31, 0x0A, 0x02, 0x0A, 0x01, 0x41,
+  0x30, 0x30, 0x32, 0x0A, 0x02, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x37, 0xA2, 0x4E, 0x05, 0x92,
+  0x94, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30, 0x30,
+  0x31, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x31, 0x38,
+  0x41, 0x30, 0x31, 0x37, 0x0A, 0x00, 0x75, 0x41,
+  0x30, 0x31, 0x37, 0x9F, 0x70, 0x83, 0x88, 0x41,
+  0x30, 0x31, 0x39, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x60, 0x70, 0x83, 0x88, 0x41, 0x30, 0x35, 0x39,
+  0x41, 0x30, 0x31, 0x37, 0x00, 0x62, 0xA0, 0x0A,
+  0x93, 0x60, 0x62, 0x75, 0x41, 0x30, 0x31, 0x37,
+  0x9F, 0x70, 0x62, 0x88, 0x41, 0x30, 0x31, 0x39,
+  0x41, 0x30, 0x31, 0x37, 0x00, 0x41, 0x30, 0x36,
+  0x32, 0x41, 0x30, 0x31, 0x37, 0x62, 0x75, 0x41,
+  0x30, 0x31, 0x37, 0xA0, 0x1E, 0x93, 0x89, 0x41,
+  0x30, 0x35, 0x39, 0x01, 0x0A, 0x02, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x30, 0x32,
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+  0x00, 0xE0, 0x61, 0xA0, 0x0D, 0x93, 0x68, 0x0A,
+  0x01, 0x7B, 0x61, 0x0C, 0xFD, 0xFF, 0xFF, 0xFF,
+  0x61, 0xA1, 0x06, 0x7D, 0x61, 0x0A, 0x02, 0x61,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8,
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+  0x80, 0x79, 0x0A, 0xFF, 0x0A, 0x08, 0x00, 0x00,
+  0x61, 0x7D, 0x61, 0x79, 0x63, 0x0A, 0x08, 0x00,
+  0x61, 0x7B, 0x80, 0x61, 0x00, 0x0A, 0x04, 0x62,
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+  0xA0, 0x21, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2,
+  0x1A, 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00,
+  0x62, 0x7B, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x40, 0x20, 0x00, 0xE0, 0x0A,
+  0x01, 0x61, 0x14, 0x42, 0x14, 0x41, 0x30, 0x30,
+  0x32, 0x01, 0x70, 0x41, 0x30, 0x30, 0x33, 0x61,
+  0x70, 0x0A, 0x00, 0x65, 0x41, 0x30, 0x30, 0x34,
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+  0x41, 0x30, 0x30, 0x35, 0x0A, 0x09, 0xA0, 0x48,
+  0x05, 0x93, 0x61, 0x0A, 0x00, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x54, 0xF9,
+  0x01, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x00,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF,
+  0xFF, 0xFF, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x70, 0x0C, 0x01, 0x00, 0x05, 0x00, 0x66, 0xA1,
+  0x44, 0x0A, 0xA0, 0x4F, 0x05, 0x93, 0x68, 0x0A,
+  0x01, 0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x00, 0xFE, 0x01, 0x00, 0x65,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x54, 0xF9, 0x01, 0x00, 0x65, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00,
+  0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF,
+  0x0A, 0x01, 0x41, 0x30, 0x30, 0x34, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C,
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+  0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0,
+  0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF,
+  0x0A, 0x00, 0xA1, 0x3D, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF,
+  0xFF, 0xFF, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x70, 0x0A, 0x01, 0x66, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF3, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0x00, 0xFF, 0x66, 0x41,
+  0x30, 0x30, 0x35, 0x0A, 0x09, 0x14, 0x47, 0x07,
+  0x41, 0x30, 0x30, 0x38, 0x03, 0xA0, 0x0A, 0x94,
+  0x68, 0x69, 0x70, 0x69, 0x63, 0x70, 0x68, 0x64,
+  0xA1, 0x07, 0x70, 0x68, 0x63, 0x70, 0x69, 0x64,
+  0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x9C, 0xF3, 0x01, 0x00, 0x60, 0x7B,
+  0x60, 0x0A, 0x18, 0x60, 0xA0, 0x18, 0x93, 0x6A,
+  0x0A, 0x00, 0x7D, 0x7D, 0x79, 0x64, 0x0A, 0x18,
+  0x00, 0x79, 0x63, 0x0A, 0x10, 0x00, 0x00, 0x7D,
+  0x60, 0x0A, 0x03, 0x00, 0x60, 0xA0, 0x18, 0x93,
+  0x6A, 0x0A, 0x01, 0x7D, 0x7D, 0x79, 0x64, 0x0A,
+  0x18, 0x00, 0x79, 0x63, 0x0A, 0x10, 0x00, 0x00,
+  0x7D, 0x60, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x9C,
+  0xF3, 0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x35,
+  0x74, 0x0A, 0x03, 0x6A, 0x00, 0x14, 0x06, 0x41,
+  0x30, 0x30, 0x39, 0x01, 0x08, 0x41, 0x30, 0x31,
+  0x30, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x31,
+  0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x32, 0x0A,
+  0x00, 0x14, 0x46, 0x0B, 0x41, 0x30, 0x31, 0x33,
+  0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, 0x0A, 0x03,
+  0x00, 0x0A, 0x04, 0x00, 0x62, 0xA0, 0x1C, 0x93,
+  0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0x70, 0x41,
+  0x30, 0x31, 0x34, 0x62, 0x0B, 0x24, 0x01, 0x41,
+  0x30, 0x31, 0x31, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x31, 0x32, 0x70, 0x41, 0x30, 0x31, 0x34, 0x62,
+  0x0B, 0x24, 0x01, 0x63, 0xA0, 0x13, 0x93, 0x68,
+  0x0A, 0x00, 0x7D, 0x63, 0x7B, 0x41, 0x30, 0x31,
+  0x31, 0x0C, 0x00, 0x00, 0x40, 0x00, 0x00, 0x63,
+  0xA1, 0x09, 0x7B, 0x63, 0x0C, 0xFF, 0xFF, 0xBF,
+  0xFF, 0x63, 0x41, 0x30, 0x31, 0x35, 0x62, 0x0B,
+  0x24, 0x01, 0x63, 0xA0, 0x36, 0x93, 0x41, 0x30,
+  0x31, 0x30, 0x0A, 0x00, 0xA0, 0x2D, 0x93, 0x41,
+  0x30, 0x31, 0x34, 0x0A, 0x08, 0x0A, 0x00, 0x0C,
+  0xFF, 0xFF, 0xFF, 0xFF, 0x7B, 0x41, 0x30, 0x30,
+  0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4,
+  0x01, 0x00, 0x0A, 0x02, 0x61, 0xA0, 0x0C, 0x93,
+  0x61, 0x0A, 0x02, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x31, 0x30, 0xA0, 0x1D, 0x93, 0x41, 0x30, 0x31,
+  0x30, 0x0A, 0x01, 0xA0, 0x09, 0x93, 0x68, 0x0A,
+  0x00, 0x70, 0x0A, 0x20, 0x60, 0xA1, 0x05, 0x70,
+  0x0A, 0x21, 0x60, 0x41, 0x30, 0x30, 0x35, 0x60,
+  0x14, 0x48, 0x08, 0x41, 0x30, 0x31, 0x36, 0x00,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x70,
+  0x0A, 0x00, 0x61, 0xA2, 0x3E, 0x92, 0x94, 0x41,
+  0x30, 0x31, 0x37, 0x41, 0x30, 0x30, 0x31, 0xA0,
+  0x12, 0x93, 0x41, 0x30, 0x31, 0x38, 0x41, 0x30,
+  0x31, 0x37, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x31,
+  0x37, 0x9F, 0xA0, 0x1A, 0x93, 0x83, 0x88, 0x41,
+  0x30, 0x31, 0x39, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x0A, 0x02, 0x7D, 0x41, 0x30, 0x32, 0x30, 0x41,
+  0x30, 0x31, 0x37, 0x61, 0x61, 0x75, 0x41, 0x30,
+  0x31, 0x37, 0x70, 0x79, 0x61, 0x0A, 0x18, 0x00,
+  0x62, 0x7D, 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00,
+  0x0B, 0x00, 0xFF, 0x00, 0x62, 0x62, 0x7D, 0x7B,
+  0x79, 0x61, 0x0A, 0x08, 0x00, 0x0C, 0x00, 0x00,
+  0xFF, 0x00, 0x00, 0x62, 0x62, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x10, 0xF6,
+  0x01, 0x00, 0x62, 0x41, 0x30, 0x30, 0x35, 0x0A,
+  0x08, 0x14, 0x4E, 0x0E, 0x41, 0x30, 0x32, 0x30,
+  0x01, 0x70, 0x41, 0x30, 0x32, 0x31, 0x68, 0x67,
+  0x70, 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41,
+  0x30, 0x32, 0x32, 0x70, 0x83, 0x88, 0x67, 0x0A,
+  0x01, 0x00, 0x41, 0x30, 0x32, 0x33, 0x70, 0x83,
+  0x88, 0x67, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x32,
+  0x34, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x03, 0x00,
+  0x41, 0x30, 0x32, 0x35, 0x70, 0x7D, 0x79, 0x83,
+  0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, 0x00,
+  0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, 0x0A,
+  0x05, 0x00, 0x00, 0x41, 0x30, 0x32, 0x36, 0x70,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xE0,
+  0x7D, 0x79, 0x41, 0x30, 0x32, 0x36, 0x0A, 0x10,
+  0x00, 0x0B, 0x23, 0x80, 0x00, 0x65, 0x7A, 0x65,
+  0x41, 0x30, 0x32, 0x34, 0x65, 0x79, 0x0A, 0x01,
+  0x72, 0x74, 0x41, 0x30, 0x32, 0x35, 0x41, 0x30,
+  0x32, 0x34, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x74,
+  0x62, 0x0A, 0x01, 0x62, 0x7B, 0x65, 0x62, 0x65,
+  0xA0, 0x26, 0x94, 0x41, 0x30, 0x32, 0x32, 0x41,
+  0x30, 0x32, 0x33, 0x70, 0x41, 0x30, 0x32, 0x33,
+  0x63, 0x70, 0x41, 0x30, 0x32, 0x32, 0x64, 0x74,
+  0x74, 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x32,
+  0x34, 0x00, 0x74, 0x64, 0x63, 0x00, 0x61, 0xA1,
+  0x11, 0x70, 0x41, 0x30, 0x32, 0x33, 0x64, 0x70,
+  0x41, 0x30, 0x32, 0x32, 0x63, 0x70, 0x0A, 0x00,
+  0x61, 0x79, 0x0A, 0x01, 0x72, 0x74, 0x64, 0x63,
+  0x00, 0x0A, 0x01, 0x00, 0x62, 0x79, 0x74, 0x62,
+  0x0A, 0x01, 0x00, 0x61, 0x62, 0x7B, 0x62, 0x80,
+  0x65, 0x00, 0x62, 0x79, 0x74, 0x62, 0x0A, 0x01,
+  0x00, 0x74, 0x63, 0x61, 0x00, 0x62, 0xA4, 0x62,
+  0x08, 0x41, 0x30, 0x32, 0x37, 0x0A, 0x00, 0x08,
+  0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x14, 0x43,
+  0x08, 0x41, 0x57, 0x41, 0x4B, 0x01, 0xA0, 0x40,
+  0x07, 0x93, 0x68, 0x0A, 0x03, 0xA0, 0x2E, 0x93,
+  0x41, 0x30, 0x32, 0x37, 0x0A, 0x01, 0x70, 0x41,
+  0x30, 0x31, 0x34, 0x0A, 0xC5, 0x0B, 0x70, 0x01,
+  0x60, 0x41, 0x30, 0x31, 0x35, 0x0A, 0xC5, 0x0B,
+  0x70, 0x01, 0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01,
+  0x0A, 0x0E, 0x00, 0x00, 0x00, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x32, 0x37, 0xA0, 0x3A, 0x93, 0x41,
+  0x30, 0x32, 0x38, 0x0A, 0x01, 0x70, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28,
+  0xF4, 0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x36,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01,
+  0x00, 0x7D, 0x60, 0x79, 0x0A, 0x01, 0x0A, 0x05,
+  0x00, 0x00, 0x41, 0x30, 0x30, 0x35, 0x0A, 0x16,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x38, 0x70,
+  0x41, 0x30, 0x30, 0x33, 0x61, 0x41, 0x30, 0x31,
+  0x33, 0x61, 0x14, 0x49, 0x08, 0x41, 0x50, 0x54,
+  0x53, 0x01, 0xA0, 0x41, 0x08, 0x93, 0x68, 0x0A,
+  0x03, 0x41, 0x30, 0x31, 0x33, 0x0A, 0x01, 0x70,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x28, 0xF4, 0x01, 0x00, 0x60, 0xA0, 0x33,
+  0x92, 0x93, 0x7B, 0x60, 0x79, 0x0A, 0x01, 0x0A,
+  0x05, 0x00, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4,
+  0x01, 0x00, 0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01,
+  0x0A, 0x05, 0x00, 0x00, 0x00, 0x41, 0x30, 0x30,
+  0x35, 0x0A, 0x16, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x32, 0x38, 0x70, 0x41, 0x30, 0x31, 0x34, 0x0A,
+  0xC5, 0x0B, 0x70, 0x01, 0x60, 0xA0, 0x26, 0x93,
+  0x7B, 0x60, 0x79, 0x0A, 0x01, 0x0A, 0x0E, 0x00,
+  0x00, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x35, 0x0A,
+  0xC5, 0x0B, 0x70, 0x01, 0x7D, 0x60, 0x79, 0x0A,
+  0x01, 0x0A, 0x0E, 0x00, 0x00, 0x70, 0x0A, 0x01,
+  0x41, 0x30, 0x32, 0x37
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
new file mode 100644
index 0000000000..862909513e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "PcieAlibSsdtTNFM2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID *
+PcieAlibGetBaseTableTNFM2 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get base SSDT table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        pointer to SSTD table
+ */
+VOID *
+PcieAlibGetBaseTableTNFM2 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  return &AlibSsdtTNFM2[0];
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
new file mode 100644
index 0000000000..49bae5f302
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
@@ -0,0 +1,196 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63659 $   @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+DefinitionBlock (
+  "PcieAlibSsdtTN.aml",
+  "SSDT",
+  2,
+  "AMD",
+  "ALIB",
+  0x1
+  )
+{
+  Scope(\_SB) {
+
+    Name (varMaxPortIndexNumber, 6)
+
+    include ("PcieAlibMmioData.asl")
+    include ("PcieAlibPciLib.asl")
+    include ("PcieAlibDebugLib.asl")
+    include ("PcieSmuServiceV4.asl")
+
+
+    Name (varBapmControl, 0)
+    Name (varCstateIntControlState, 0)
+    Name (varIsStateInitialized, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  APM/PDM stub
+     *
+     *  Arg0 - AC/DC state
+     *
+     */
+    Method (procApmPdmActivate, 1, NotSerialized) {
+      Store (Or(ShiftLeft (0x18, 3), 4), Local2)
+      if (LEqual (varIsStateInitialized, 0)) {
+        Store (procPciDwordRead (Local2, 0x124), varCstateIntControlState)
+        Store (1, varIsStateInitialized)
+      }
+
+      Store (procPciDwordRead (Local2, 0x124), Local3)
+      if (LEqual (Arg0,DEF_PSPP_STATE_AC)) {
+        // Disable PC6 on AC
+        Or (Local3, And (varCstateIntControlState, 0x00400000), Local3)
+      } else {
+        // Enable PC6 on DC
+        And (Local3, 0xFFBFFFFF, Local3)
+      }
+      procPciDwordWrite (Local2, 0x124, Local3)
+
+      if (LEqual (varBapmControl, 0)) {
+        // If GFX present driver manage BAPM if not ALIB manage BAPM
+        if (LEqual (procPciDwordRead (0x08, 0x00), 0xffffffff)) {
+          And (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), 0x2, Local1);
+          // check if BAPM was enable during BIOS post
+          if (LEqual (Local1, 0x2)) {
+            Store (1, varBapmControl)
+          }
+        }
+      }
+      if (LEqual (varBapmControl,1)) {
+        if (LEqual (Arg0,DEF_PSPP_STATE_AC)) {
+          // Enable BAPM on AC
+          Store (32, Local0)
+        } else {
+          // Disable BAPM on DC
+          Store (33, Local0)
+        }
+        procNbSmuServiceRequest (Local0);
+      }
+    }
+
+    Name (varRestoreNbps, 0)
+    Name (varRestoreNbDpmState, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  _WAK
+     *
+     *
+     *
+     */
+    Method (AWAK, 1) {
+      if (LEqual (Arg0, 3)) {
+        // Clear D18F5x170 [SwNbPstateLoDis] only if it was 0 in APTS
+        if (LEqual (varRestoreNbps, 1)) {
+          Store (procPciDwordRead (0xC5, 0x170), Local0)
+          procPciDwordWrite (0xC5, 0x170, And (Local0, Not (ShiftLeft (1, 14))))
+           Store (0, varRestoreNbps);
+        }
+        if (LEqual (varRestoreNbDpmState, 1)) {
+          Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0)
+          procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, Or (Local0, ShiftLeft (1, 5)))
+          procNbSmuServiceRequest (22);
+          Store (0, varRestoreNbDpmState)
+        }
+      }
+    }
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  _PTS
+     *
+     *
+     *
+     */
+    Method (APTS, 1) {
+      if (LEqual (Arg0, 3)) {
+         procApmPdmActivate (DEF_PSPP_STATE_DC);
+         // Disable NBDPM
+         Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0)
+         if (LNotEqual (And (Local0, ShiftLeft (1, 5)), 0)) {
+           // NBDPM enabled lets disable it
+           procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, And (Local0, Not (ShiftLeft (1, 5))))
+           procNbSmuServiceRequest (22);
+           // Indicate needs to restore NBDPM
+           Store (1, varRestoreNbDpmState);
+         }
+         // Save state of D18F5x170 [SwNbPstateLoDis]
+         Store (procPciDwordRead (0xC5, 0x170), Local0)
+         if (LEqual (And (Local0, ShiftLeft (1, 14)), 0)) {
+          // Set D18F5x170 [SwNbPstateLoDis] = 1
+          procPciDwordWrite (0xC5, 0x170, Or (Local0, ShiftLeft (1, 14)))
+           Store (1, varRestoreNbps);
+         }
+      }
+    }
+  } //End of Scope(\_SB)
+}   //End of DefinitionBlock
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
new file mode 100644
index 0000000000..baa0f85ac1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "PcieAlibSsdtTNFS1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID *
+PcieAlibGetBaseTableTNFS1 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get base SSDT table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        pointer to SSTD table
+ */
+VOID *
+PcieAlibGetBaseTableTNFS1 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  return &AlibSsdtTNFS1[0];
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
new file mode 100644
index 0000000000..9c55714b93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
@@ -0,0 +1,491 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe configuration data definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECOMPLEXDATATN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+TN_COMPLEX_CONFIG ComplexDataTN = {
+  //Silicon
+  {
+    {
+      DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      0,
+      0,
+      offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon)
+    },
+    0,
+    0
+  },
+  //Gfx Wrapper
+  {
+    {
+      DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper)
+    },
+
+    GFX_WRAP_ID,
+    GFX_NUMBER_OF_PIFs,
+    GFX_START_PHY_LANE,
+    GFX_END_PHY_LANE,
+    GFX_CORE_ID,
+    GFX_CORE_ID,
+    16,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      1,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //Gpp Wrapper
+  {
+    {
+      DESCRIPTOR_PCIE_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper)
+    },
+    GPP_WRAP_ID,
+    GPP_NUMBER_OF_PIFs,
+    GPP_START_PHY_LANE,
+    GPP_END_PHY_LANE,
+    GPP_CORE_ID,
+    GPP_CORE_ID,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      1,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //DDI Wrapper
+  {
+    {
+      DESCRIPTOR_DDI_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper)
+    },
+    DDI_WRAP_ID,
+    DDI_NUMBER_OF_PIFs,
+    DDI_START_PHY_LANE,
+    DDI_END_PHY_LANE,
+    0xf,
+    0x0,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      0,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //DDI2 Wrapper
+  {
+    {
+      DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      0,
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper)
+    },
+    DDI2_WRAP_ID,
+    DDI2_NUMBER_OF_PIFs,
+    DDI2_START_PHY_LANE,
+    DDI2_END_PHY_LANE,
+    0xf,
+    0x0,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      0,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //Port 2
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, Port2),
+      0
+    },
+    { PciePortEngine, 8, 23},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        0,
+        15,
+        2,
+        0,
+        GFX_CORE_ID,
+        0,
+        {0},
+        LinkStateResetExit,
+        0,
+        2,
+        1
+      },
+    },
+  },
+  //Port 3
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, Port3),
+      0
+    },
+    { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        UNUSED_LANE_ID,
+        UNUSED_LANE_ID,
+        3,
+        0,
+        GFX_CORE_ID,
+        1,
+        {0},
+        LinkStateResetExit,
+        1,
+        3,
+        1
+      },
+    },
+  },
+  //DdiB
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, DpB),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DdiC
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, DpC),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                               //Initialization Status
+    0xFF                                             //Scratch
+  },
+  //DdiD
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, DpD),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                               //Initialization Status
+    0xFF                                             //Scratch
+  },
+
+  //Port 4
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, Port4),
+      0
+    },
+    { PciePortEngine, 4, 4},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        4,
+        4,
+        4,
+        0,
+        GPP_CORE_ID,
+        1,
+        {0},
+        LinkStateResetExit,
+        2,
+        0,
+        0
+      },
+    },
+  },
+  //Port 5
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, Port5),
+      0
+    },
+    { PciePortEngine, 5, 5},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        5,
+        5,
+        5,
+        0,
+        GPP_CORE_ID,
+        2,
+        {0},
+        LinkStateResetExit,
+        3,
+        0,
+        0
+      },
+    },
+  },
+  //Port 6
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, Port6),
+      0
+    },
+    { PciePortEngine, 6, 6 },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        6,
+        6,
+        6,
+        0,
+        GPP_CORE_ID,
+        3,
+        {0},
+        LinkStateResetExit,
+        4,
+        0,
+        0
+      },
+    },
+  },
+  //Port 7
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, Port7),
+      0
+    },
+    { PciePortEngine, 7, 7 },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        7,
+        7,
+        7,
+        0,
+        GPP_CORE_ID,
+        4,
+        {0},
+        LinkStateResetExit,
+        5,
+        0,
+        0
+      },
+    },
+  },
+  //Port 8
+  {
+    {
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, Port8),
+      0
+    },
+    { PciePortEngine, 0, 3 },
+    INIT_STATUS_PCIE_TRAINING_SUCCESS,            //Initialization Status
+    0xFF,                                         //Scratch
+    {
+      {
+        {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}},
+        0,
+        3,
+        8,
+        0,
+        GPP_CORE_ID,
+        0,
+        {MAKE_SBDFO (0, 0, 8, 0, 0)},
+        LinkStateTrainingSuccess,
+        6,
+        0,
+        0
+      },
+    },
+  },
+  //DpE
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DpE),
+      0
+    },
+   {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DpF
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, DpF),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DpA
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper),
+      0,
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //F12 specific Silicon
+  {
+    OscFuses,
+    {0, 0, 0, 0, 0, 0}
+  }
+};
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h
new file mode 100644
index 0000000000..623636cc06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIECOMPLEXDATATN_H_
+#define _PCIECOMPLEXDATATN_H_
+
+#define SOCKET_ID             0
+
+#define MAX_NUM_PHYs          2
+#define MAX_NUM_LANE_PER_PHY  8
+
+#define NUMBER_OF_PORTS     8
+#define NUMBER_OF_GPP_PORTS 5
+#define NUMBER_OF_GFX_PORTS 2
+#define NUMBER_OF_GFX_DDIS  3
+#define NUMBER_OF_DDIS      2
+#define NUMBER_OF_DDIS2     1
+#define NUMBER_OF_WRAPPERS  3
+#define NUMBER_OF_SILICONS  1
+
+#define GFX_WRAP_ID         1
+#define GFX_NUMBER_OF_PIFs  2
+#define GFX_START_PHY_LANE  8
+#define GFX_END_PHY_LANE    23
+#define GFX_CORE_ID         2
+
+#define GFX_CORE_x16        ((16 << 8) | 0)
+#define GFX_CORE_x8x8       ((8 << 8) | 8)
+
+#define GPP_WRAP_ID         0
+#define GPP_NUMBER_OF_PIFs  1
+#define GPP_START_PHY_LANE  0
+#define GPP_END_PHY_LANE    7
+#define GPP_CORE_ID         1
+
+#define GPP_CORE_x4x1x1x1x1   ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x1x1     ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x1x1_ST  ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x2       ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x2_ST    ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x4         ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
+
+#define DDI_WRAP_ID           2
+#define DDI_NUMBER_OF_PIFs    1
+#define DDI_START_PHY_LANE    24
+#define DDI_END_PHY_LANE      31
+
+#define DDI2_WRAP_ID          3
+#define DDI2_NUMBER_OF_PIFs   1
+#define DDI2_START_PHY_LANE   32
+#define DDI2_END_PHY_LANE     38
+
+///Gen2 capability
+typedef enum {
+  OscFuses,                   ///< Not capable
+  OscRO,                      ///< Gen2 with RO
+  OscLC,                      ///< Gen2 with LC
+  OscDefault,                 ///< Skip initialization of OSC
+} OSC_MODE;
+
+///Family specific silicon configuration
+typedef struct {
+  OSC_MODE  OscMode;          ///<OSC mode
+  UINT8     PortDevMap[6];    ///< Device number that has beed allocated already
+} TN_PCIe_SILICON_CONFIG;
+
+
+/// Complex Configuration
+typedef struct {
+  PCIe_SILICON_CONFIG     Silicon;                ///< Silicon
+  PCIe_WRAPPER_CONFIG     GfxWrapper;             ///< Graphics Wrapper
+  PCIe_WRAPPER_CONFIG     GppWrapper;             ///< General Purpose Port
+  PCIe_WRAPPER_CONFIG     DdiWrapper;             ///< DDI
+  PCIe_WRAPPER_CONFIG     Ddi2Wrapper;            ///< DDI
+  PCIe_ENGINE_CONFIG      Port2;                  ///< Port 2
+  PCIe_ENGINE_CONFIG      Port3;                  ///< Port 3
+  PCIe_ENGINE_CONFIG      DpB;                    ///< DPB
+  PCIe_ENGINE_CONFIG      DpC;                    ///< DPC
+  PCIe_ENGINE_CONFIG      DpD;                    ///< DPD
+  PCIe_ENGINE_CONFIG      Port4;                  ///< Port 4
+  PCIe_ENGINE_CONFIG      Port5;                  ///< Port 5
+  PCIe_ENGINE_CONFIG      Port6;                  ///< Port 6
+  PCIe_ENGINE_CONFIG      Port7;                  ///< Port 7
+  PCIe_ENGINE_CONFIG      Port8;                  ///< Port 8
+  PCIe_ENGINE_CONFIG      DpE;                    ///< DPE
+  PCIe_ENGINE_CONFIG      DpF;                    ///< DPF
+  PCIe_ENGINE_CONFIG      DpA;                    ///< DPA
+  TN_PCIe_SILICON_CONFIG  FmSilicon;               ///< Fm Silicon
+} TN_COMPLEX_CONFIG;
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
new file mode 100644
index 0000000000..8d687d910a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
@@ -0,0 +1,1002 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe wrapper configuration services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern TN_COMPLEX_CONFIG      ComplexDataTN;
+extern PCIe_PORT_DESCRIPTOR   DefaultSbPort;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+PcieConfigureEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureGppEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdi2EnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+PcieGetCoreConfigurationValueTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  );
+
+BOOLEAN
+PcieCheckPortPciDeviceMappingTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  );
+
+CONST CHAR8*
+PcieDebugGetCoreConfigurationStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  );
+
+CONST CHAR8*
+PcieDebugGetWrapperNameStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  );
+
+CONST CHAR8*
+PcieDebugGetHostRegAddressSpaceStringTN (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  );
+
+BOOLEAN
+PcieCheckPortPcieLaneCanBeMuxedTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  );
+
+AGESA_STATUS
+PcieMapPortPciAddressTN (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  );
+
+AGESA_STATUS
+PcieGetComplexDataLengthTN (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieBuildComplexConfigurationTN (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+UINT32
+PcieGetNativePhyLaneBitmapTN (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+AGESA_STATUS
+PcieGetSbConfigInfoTN (
+  IN       UINT8                         SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR          *SbPort,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   No more configuration available for given engine type
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+AGESA_STATUS
+PcieConfigureEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_ERROR;
+  switch (Wrapper->WrapId) {
+  case GFX_WRAP_ID:
+    Status = PcieConfigureGfxEnginesLaneAllocationTN (Wrapper, EngineType, ConfigurationId);
+    break;
+  case GPP_WRAP_ID:
+    if (EngineType != PciePortEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureGppEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case DDI_WRAP_ID:
+    if (EngineType != PcieDdiEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case DDI2_WRAP_ID:
+    if (EngineType != PcieDdiEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureDdi2EnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return Status;
+}
+
+CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = {
+{0,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+{0,   7, 8,              15}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxPortEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  UINTN               CoreLaneIndex;
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  CoreLaneIndex = 0;
+  while (EnginesList != NULL) {
+    if (PcieLibIsPcieEngine (EnginesList)) {
+      PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+      EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+      EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    }
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = {
+  {0,   7, 8,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+  {4,   7, 8,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+  {0,   7, 8,  11, 12,             15},
+  {4,   7, 8,  11, 12,             15}
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  UINTN               LaneIndex;
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  while (EnginesList != NULL) {
+    if (PcieLibIsDdiEngine (EnginesList)) {
+      PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+      EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+      EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    }
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   Configuration not applicable
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS  Status;
+
+  switch (EngineType) {
+  case PciePortEngine:
+    Status = PcieConfigureGfxPortEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case PcieDdiEngine:
+    Status = PcieConfigureGfxDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  default:
+    Status = AGESA_UNSUPPORTED;
+  }
+  return Status;
+}
+
+
+
+CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
+//4     5                                6                               7                                8 (SB)
+  {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID,  UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, 6,              7,               UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID,  6,              7,              UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, 6,              6,               7,              7,              UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID,  6,              6,              7,              7,               0, 3},
+  {4, 4, 5,              5,               6,              6,              7,              7,               0, 3}
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureGppEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               CoreLaneIndex;
+  UINTN               PortIdIndex;
+  if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  CoreLaneIndex = 0;
+  PortIdIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
+  {0,  3,   4,              7},
+  {0,  7,   UNUSED_LANE_ID, UNUSED_LANE_ID}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure DDI engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               LaneIndex;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+CONST UINT8 Ddi2LaneConfigurationTable [][NUMBER_OF_DDIS2 * 2] = {
+  {0,  6},
+  {0,  3}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure DDI engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdi2EnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               LaneIndex;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  if (ConfigurationId > ((sizeof (Ddi2LaneConfigurationTable) / (NUMBER_OF_DDIS2 * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->EngineData.StartLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList->EngineData.EndLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get configuration Value for GFX wrapper
+ *
+ *
+ *
+ * @param[in]   ConfigurationSignature  Configuration signature
+ * @param[out]  ConfigurationValue      Configuration value
+ * @retval     AGESA_SUCCESS            Correct core configuration value returned by in *ConfigurationValue
+ * @retval     AGESA_ERROR              ConfigurationSignature is incorrect.
+ */
+STATIC AGESA_STATUS
+PcieGetGfxConfigurationValueTN (
+  IN       UINT64    ConfigurationSignature,
+     OUT   UINT8     *ConfigurationValue
+  )
+{
+  switch (ConfigurationSignature) {
+  case GFX_CORE_x16:
+    *ConfigurationValue = 0;
+    break;
+  case GFX_CORE_x8x8:
+    *ConfigurationValue = 0x5;
+    break;
+  default:
+    ASSERT (FALSE);
+    return  AGESA_ERROR;
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get configuration Value for GPP wrapper
+ *
+ *
+ *
+ * @param[in]   ConfigurationSignature  Configuration signature
+ * @param[out]  ConfigurationValue      Configuration value
+ * @retval      AGESA_SUCCESS           Correct core configuration value returned by in *ConfigurationValue
+ * @retval      AGESA_ERROR             ConfigurationSignature is incorrect
+ */
+STATIC AGESA_STATUS
+PcieGetGppConfigurationValueTN (
+  IN       UINT64    ConfigurationSignature,
+     OUT   UINT8     *ConfigurationValue
+  )
+{
+  switch (ConfigurationSignature) {
+  case GPP_CORE_x4x1x1x1x1:
+    *ConfigurationValue = 0x4;
+    break;
+  case GPP_CORE_x4x2x1x1:
+    *ConfigurationValue = 0x3;
+    break;
+  case GPP_CORE_x4x2x2:
+    *ConfigurationValue = 0x2;
+    break;
+  case GPP_CORE_x4x4:
+    *ConfigurationValue = 0x1;
+    break;
+  default:
+    ASSERT (FALSE);
+    return  AGESA_ERROR;
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration value
+ *
+ *
+ *
+ * @param[in]  Wrapper                Pointer to internal configuration data area
+ * @param[in]  CoreId                 Core ID
+ * @param[in]  ConfigurationSignature Configuration signature
+ * @param[out] ConfigurationValue     Configuration value (for core configuration)
+ * @retval     AGESA_SUCCESS          Configuration successfully applied
+ * @retval     AGESA_ERROR            Core configuration value can not be determined
+ */
+AGESA_STATUS
+PcieGetCoreConfigurationValueTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  )
+{
+  AGESA_STATUS  Status;
+
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+    Status = PcieGetGfxConfigurationValueTN (ConfigurationSignature, ConfigurationValue);
+  } else if (Wrapper->WrapId == GPP_WRAP_ID) {
+    Status = PcieGetGppConfigurationValueTN (ConfigurationSignature, ConfigurationValue);
+  } else {
+    Status = AGESA_ERROR;
+  }
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if engine can be remapped to Device/function number requested by user
+ * defined engine descriptor
+ *
+ *   Function only called if requested device/function does not much native device/function
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckPortPciDeviceMappingTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  BOOLEAN   Result;
+  if (PortDescriptor->Port.DeviceNumber >= 2 && PortDescriptor->Port.DeviceNumber <= 7 && PortDescriptor->Port.FunctionNumber == 0 && !PcieConfigIsSbPcieEngine (Engine)) {
+    Result = TRUE;
+  } else {
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration string
+ *
+ *   Debug function for logging configuration
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @param[in] ConfigurationValue   Configuration value
+ * @retval                         Configuration string
+ */
+
+CONST CHAR8*
+PcieDebugGetCoreConfigurationStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  )
+{
+  switch (ConfigurationValue) {
+  case 0:
+    return "1x16";
+  case 5:
+    return "2x8";
+  case 4:
+    return "1x4, 4x1";
+  case 3:
+    return "1x4, 1x2, 2x1";
+  case 2:
+    return "1x4, 2x2";
+  case 1:
+    return "1x4, 1x4";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get wrapper name
+ *
+ *  Debug function for logging wrapper name
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @retval                         Wrapper Name string
+ */
+
+CONST CHAR8*
+PcieDebugGetWrapperNameStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  )
+{
+  switch (Wrapper->WrapId) {
+  case  GPP_WRAP_ID:
+    return "GPPSB";
+  case  GFX_WRAP_ID:
+    return "GFX";
+  case  DDI_WRAP_ID:
+    return "DDI";
+  case  DDI2_WRAP_ID:
+    return "DDI2";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get register address name
+ *
+ *  Debug function for logging register trace
+ *
+ * @param[in] Silicon              Silicon config descriptor
+ * @param[in] AddressFrame         Address Frame
+ * @retval                         Register address name
+ */
+CONST CHAR8*
+PcieDebugGetHostRegAddressSpaceStringTN (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  )
+{
+  switch (AddressFrame) {
+  case  0x130:
+    return "GPP  WRAP";
+  case  0x131:
+    return "GFX  WRAP";
+  case  0x132:
+    return "DDI  WRAP";
+  case  0x133:
+    return "DDI2 WRAP";
+  case  0x110:
+    return "GPP  PIF0";
+  case  0x111:
+    return "GFX  PIF0";
+  case  0x211:
+    return "GFX  PIF1";
+  case  0x112:
+    return "DDI  PIF0";
+  case  0x113:
+    return "DDI2 PIF0";
+  case  0x120:
+    return "GPP  PHY0";
+  case  0x121:
+    return "GFX  PHY0";
+  case  0x221:
+    return "GFX  PHY1";
+  case  0x122:
+    return "DDI  PHY0";
+  case  0x123:
+    return "DDI2 PHY0";
+  case  0x101:
+    return "GPP  CORE";
+  case  0x201:
+    return "GFX  CORE";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if the lane can be muxed by link width requested by user
+ * defined engine descriptor
+ *
+ *    Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
+ *    Check Engine StartCoreLane could be aligned by user requested link width x2.
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Lane can be muxed
+ * @retval     FALSE               Lane can NOT be muxed
+ */
+
+BOOLEAN
+PcieCheckPortPcieLaneCanBeMuxedTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  UINT16                DescriptorHiLane;
+  UINT16                DescriptorLoLane;
+  UINT16                DescriptorNumberOfLanes;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+  UINT16                NormalizedLoPhyLane;
+  BOOLEAN               Result;
+
+  Result  = FALSE;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+
+  NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane;
+
+  if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) {
+    Result = TRUE;
+  } else {
+    if (((PortDescriptor->Port.MiscControls.SbLink == 0x0) && ((Engine->Type.Port.StartCoreLane % 2) == 0)) || (Engine->Type.Port.StartCoreLane == 0)) {
+      if (NormalizedLoPhyLane == 0) {
+        Result = TRUE;
+      } else {
+        if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) {
+          Result = TRUE;
+        }
+      }
+    }
+  }
+  return Result;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Map engine to specific PCI device address
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @retval     AGESA_ERROR         Fail to map PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address
+ */
+
+AGESA_STATUS
+PcieMapPortPciAddressTN (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  TN_COMPLEX_CONFIG       *ComplexConfig;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  UINT8                   PortDevMap[6];
+  UINT8                   FreeDevMap[6];
+  UINT8                   PortIndex;
+  UINT8                   EnginePortIndex;
+  UINT8                   FreeIndex;
+  D0F0x64_x20_STRUCT      D0F0x64_x20;
+  D0F0x64_x21_STRUCT      D0F0x64_x21;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Enter\n");
+  if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
+    Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
+    Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
+  }
+  if (!PcieConfigIsSbPcieEngine (Engine)) {
+    ComplexConfig = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
+    Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+    LibAmdMemFill (&FreeDevMap[0], 0x0, sizeof (FreeDevMap), GnbLibGetHeader (Pcie));
+    LibAmdMemCopy (&PortDevMap[0], &ComplexConfig->FmSilicon.PortDevMap, sizeof (PortDevMap), GnbLibGetHeader (Pcie));
+    for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
+      if (PortDevMap[PortIndex] != 0) {
+        FreeDevMap[PortDevMap[PortIndex] - 2] = 1;
+      }
+    }
+    EnginePortIndex = Engine->Type.Port.PortData.DeviceNumber - 2;
+    if (FreeDevMap[EnginePortIndex] == 0) {
+      // Dev number not yet allocated
+      ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
+      FreeDevMap[EnginePortIndex] = 1;
+      PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
+      for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
+        if (PortDevMap[PortIndex] == 0) {
+          for (FreeIndex = 0; FreeIndex < sizeof (FreeDevMap); FreeIndex++) {
+            if (FreeDevMap[FreeIndex] == 0) {
+              FreeDevMap[FreeIndex] = 1;
+              break;
+            }
+          }
+          PortDevMap[PortIndex] = FreeIndex + 2;
+        }
+      }
+
+      GnbRegisterReadTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x20.Field.ProgDevMapEn = 0;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      GnbRegisterReadTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x21.Field.GfxPortADevmap = PortDevMap[2 - 2];
+      D0F0x64_x21.Field.GfxPortBDevmap = PortDevMap[3 - 2];
+      D0F0x64_x20.Field.GppPortBDevmap = PortDevMap[4 - 2];
+      D0F0x64_x20.Field.GppPortCDevmap = PortDevMap[5 - 2];
+      D0F0x64_x20.Field.GppPortDDevmap = PortDevMap[6 - 2];
+      D0F0x64_x20.Field.GppPortEDevmap = PortDevMap[7 - 2];
+      D0F0x64_x20.Field.ProgDevMapEn = 0x1;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      GnbRegisterWriteTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x20.Field.ProgDevMapEn = 1;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Fail device %d to port %d\n", Engine->Type.Port.PortData.DeviceNumber, Engine->Type.Port.NativeDevNumber);
+      Status = AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get total number of silicons/wrappers/engines for this complex
+ *
+ *
+ *
+ * @param[in]  SocketId              Socket ID.
+ * @param[out] Length                Length of configuration info block
+ * @param[out] StdHeader             Standard configuration header
+ * @retval     AGESA_SUCCESS         Configuration data length is correct
+ */
+AGESA_STATUS
+PcieGetComplexDataLengthTN (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  *Length = sizeof (TN_COMPLEX_CONFIG);
+  return  AGESA_SUCCESS;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build configuration
+ *
+ *
+ *
+ * @param[in]  SocketId         Socket ID.
+ * @param[out] Buffer           Pointer to buffer to build internal complex data structure
+ * @param[out] StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieBuildComplexConfigurationTN (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  LibAmdMemCopy (Buffer, &ComplexDataTN, sizeof (TN_COMPLEX_CONFIG), StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  get native PHY lane bitmap
+ *
+ *
+ * @param[in]  PhyLaneBitmap  Package PHY lane bitmap
+ * @param[in]  Engine         Standard configuration header.
+ * @retval     Native PHY lane bitmap
+ */
+UINT32
+PcieGetNativePhyLaneBitmapTN (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  )
+{
+  return PhyLaneBitmap;
+}
+
+STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = {
+  0,
+  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0)
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build default SB configuration descriptor
+ *
+ *
+ * @param[in]  SocketId         Socket Id
+ * @param[out] SbPort           Pointer to SB configuration descriptor
+ * @param[in]  StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieGetSbConfigInfoTN (
+  IN       UINT8                         SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR          *SbPort,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader);
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
new file mode 100644
index 0000000000..642f41ff89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
@@ -0,0 +1,810 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64781 $   @e \$Date: 2012-01-30 21:19:50 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbNbInitLibV4.h"
+#include  "PcieLibTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuFamRegisters.h"
+#include  "F15TnPackageType.h"
+#include  "GeneralServices.h"
+#include  "Filecode.h"
+
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN;
+extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN;
+extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY lane parameter Init
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PciePhyLaneInitInitCallbackTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      VOID                  *Buffer,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   Phy;
+  UINT8   PhyLaneIndex;
+  UINT8   Lane;
+  UINT32  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper);
+  for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) {
+    if ((LaneBitmap & (1 << Lane)) != 0) {
+      Phy = Lane / MAX_NUM_LANE_PER_PHY;
+      PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY;
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80),
+        D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK,
+        (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET),
+        FALSE,
+        Pcie
+        );
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80),
+        D0F0xE4_PHY_4002_LfcMax_MASK,
+        (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET),
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Satic init for various registers.
+ *
+ *
+ *
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+STATIC
+PcieEarlyStaticInitTN (
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINTN Index;
+
+  for (Index = 0; Index < PcieInitEarlyTableTN.Length; Index++) {
+    GnbLibPciIndirectRMW (
+      MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS),
+      PcieInitEarlyTableTN.Table[Index].Reg,
+      AccessWidth32,
+      (UINT32)~PcieInitEarlyTableTN.Table[Index].Mask,
+      PcieInitEarlyTableTN.Table[Index].Data,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init core registers.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+STATIC
+PcieEarlyCoreInitTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINT8   CoreId;
+  UINTN   Index;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n");
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      for (Index = 0; Index < CoreInitTableTN.Length; Index++) {
+        UINT32 Value;
+        Value = PcieRegisterRead (
+                  Wrapper,
+                  CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
+                  Pcie
+                  );
+        Value &= (~CoreInitTableTN.Table[Index].Mask);
+        Value |= CoreInitTableTN.Table[Index].Data;
+        PcieRegisterWrite (
+          Wrapper,
+          CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
+          Value,
+          FALSE,
+          Pcie
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Dll Cap based on fuses
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper configuration data area
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+STATIC VOID
+PcieSetDllCapTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D18F3x1FC_STRUCT           D18F3x1FC;
+  D0F0xE4_PHY_500F_STRUCT    D0F0xE4_PHY_500F;
+  D0F0xE4_PHY_4010_STRUCT    D0F0xE4_PHY_4010;
+  D0F0xE4_PHY_4011_STRUCT    D0F0xE4_PHY_4011;
+  UINT32                     Gen1Index;
+  UINT32                     Gen2Index;
+  CPU_LOGICAL_ID             LogicalId;
+  GNB_HANDLE                 *GnbHandle;
+
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n");
+
+  D0F0xE4_PHY_500F.Value = 0;
+  GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie));
+
+  //Read SWDllCapTableEn
+  GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie));
+  IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value);
+
+  if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull  )) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n");
+    // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0])
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS));
+    D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value);
+    // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0])
+    IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS));
+    D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value);
+
+    // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0
+    // Else...
+    // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical
+    // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast
+    // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow
+    IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl);
+    if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp);
+      Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1;
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case...");
+      switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) {
+      case 0:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n");
+        Gen1Index = 0xd;
+        break;
+      case 1:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n");
+        Gen1Index = 0xf;
+        break;
+      case 2:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n");
+        Gen1Index = 0xa;
+        break;
+      default:
+        IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n");
+        Gen1Index = 0xd; //Use typical for default case
+        break;
+      }
+    }
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index);
+    // Bits  3:0 = Gen1Index[3:0]
+    // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0]
+    if (D18F3x1FC.Field.SWDllCapTableEn != 0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50);
+      Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50;
+    } else {
+      Gen2Index = 0x03; // Hard coded default
+    }
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index);
+    PcieRegisterWrite (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
+      D0F0xE4_PHY_500F.Value,
+      FALSE,
+      Pcie
+      );
+    // Set DllProcessFreqCtlOverride on second write
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
+    PcieRegisterWrite (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
+      D0F0xE4_PHY_500F.Value,
+      FALSE,
+      Pcie
+      );
+    if (Wrapper->WrapId == 1) {
+      // For Wrapper 1, configure PHY0 and PHY1
+      D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0;
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
+        D0F0xE4_PHY_500F.Value,
+        FALSE,
+        Pcie
+        );
+      // Set DllProcessFreqCtlOverride on second write
+      D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
+        D0F0xE4_PHY_500F.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * TN FP2 PCIE allocation x8 check
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+
+STATIC AGESA_STATUS
+PcieFP2x8CheckCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINT32                    LaneBitmap;
+  AGESA_STATUS              Status;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n");
+
+  Status = AGESA_SUCCESS;
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap);
+
+    if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n");
+      Status = AGESA_ERROR;
+      PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_LANES_CONFIGURATION,
+        (LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane),
+        (LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane),
+        0,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+
+      ASSERT (FALSE);
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * TN FP2 PCIE critera check
+ *
+ *
+ *
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+STATIC AGESA_STATUS
+PcieFP2CriteriaTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS              Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Enter\n");
+
+  // PACKAGE_TYPE_FP2    1
+  // PACKAGE_TYPE_FS1r2  2
+  // PACKAGE_TYPE_FM2    4
+  if (LibAmdGetPackageType (GnbLibGetHeader (Pcie)) != PACKAGE_TYPE_FP2) {
+    return AGESA_SUCCESS;
+  }
+  // FP2 force gen1
+  Pcie->PsppPolicy = PsppPowerSaving;
+  // FP2 only use x8 on the same PHY
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieFP2x8CheckCallbackTN, NULL, Pcie);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Exit\n");
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RX offset cancellation enablement
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper configuration data area
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+STATIC VOID
+PcieOffsetCancelCalibration (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32                LaneBitmap;
+  D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C;
+
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
+  if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) {
+    return;
+  }
+
+  if (LaneBitmap != 0) {
+    D0F0xBC_x1F39C.Value = 0;
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane;
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Wrapper)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Wrapper)->Address,
+      SMC_MSG_PHY_LN_ON,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PcieInitSrbmCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+  PcieOffsetCancelCalibration (Wrapper, Pcie);
+  PciePifApplyGanging (Wrapper, Pcie);
+  PciePhyApplyGanging (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY Pll Personality Init Callback
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PciePhyLetPllPersonalityInitCallbackTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      VOID                  *Buffer,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n");
+  PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie);
+  PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieSetPhyPersonalityTN (Wrapper, Pcie);
+  PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Init prior training.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+AGESA_STATUS
+STATIC
+PcieEarlyInitCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  BOOLEAN       CoreConfigChanged;
+  BOOLEAN       PllConfigChanged;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n");
+  CoreConfigChanged = FALSE;
+  PllConfigChanged = FALSE;
+  PcieTopologyPrepareForReconfig (Wrapper, Pcie);
+  Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  PcieTopologyApplyLaneMux (Wrapper, Pcie);
+  PciePifSetRxDetectPowerMode (Wrapper, Pcie);
+  PciePifSetLs2ExitTime (Wrapper, Pcie);
+  PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie);
+  if (CoreConfigChanged || PllConfigChanged) {
+    PcieTopologyExecuteReconfigV4 (Wrapper, Pcie);
+  }
+  PcieTopologyCleanUpReconfig (Wrapper, Pcie);
+  PcieTopologySetLinkReversalV4 (Wrapper, Pcie);
+
+  if (Wrapper->Features.PowerOffUnusedPlls != 0) {
+    PciePifPllPowerDown (
+      PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper),
+      Wrapper,
+      Pcie
+      );
+    PciePifPllInitForDdi (Wrapper, Pcie);
+    PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie);
+  }
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieSetDdiOwnPhyV4 (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePhyAvertClockPickers (Wrapper, Pcie);
+  PcieEarlyCoreInitTN (Wrapper, Pcie);
+  PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie);
+  if (PcieConfigIsPcieWrapper (Wrapper)) {
+    PcieSetDllCapTN (Wrapper, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Init
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PcieEarlyInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS        Status;
+  AGESA_STATUS        AgesaStatus;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieFP2CriteriaTN (Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieEarlyStaticInitTN (Pcie);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieOscInitTN (Pcie);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieSetVoltageTN (PcieGen1, Pcie);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieEarlyPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n");
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie);
+  PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
+  PcieSetLinkWidthCap (Engine, Pcie);
+  PcieCompletionTimeout (Engine, Pcie);
+  PcieLinkSetSlotCap (Engine, Pcie);
+  PcieLinkInitHotplug (Engine, Pcie);
+  //PciePhyChannelCharacteristic (Engine, Pcie);
+  if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
+      (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
+       Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
+       Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
+    ASSERT (!PcieConfigIsSbPcieEngine (Engine));
+    //
+    //  Pass endpoint tstaus in scratch
+    //
+    PciePortRegisterRMW (
+      Engine,
+      DxF0xE4_x01_ADDRESS,
+      0x1,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
+  }
+  if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PcieEarlyPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
+  if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+    Pcie->TrainingExitState = LinkStateResetExit;
+  }
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieEarlyPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Enter\n");
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PcieEarlyInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieEarlyPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
new file mode 100644
index 0000000000..f0cf287a7f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Env Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PcieEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreTNS3Script_ID, 0, NULL);
+  return  AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
new file mode 100644
index 0000000000..3d00bdb6e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
@@ -0,0 +1,639 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * TN specific PCIe configuration data services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbSbLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbNbInitLibV1.h"
+#include  "PcieComplexDataTN.h"
+#include  "PcieLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+PCIE_LINK_SPEED_CAP
+PcieGetLinkSpeedCapTN (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Control port visibility in PCI config space
+ *
+ *
+ * @param[in]  Control         Make port Hide/Unhide ports
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PciePortsVisibilityControlTN (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG *Silicon;
+  Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  ASSERT (Silicon != NULL);
+  switch (Control) {
+  case UnhidePorts:
+    PcieSiliconUnHidePorts (Silicon, Pcie);
+    break;
+  case HidePorts:
+    PcieSiliconHidePorts (Silicon, Pcie);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down inactive lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePowerDownPllInL1TN (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+
+  UINT32              LaneBitmapForPllOffInL1;
+  UINT32              ActiveLaneBitmap;
+  UINT8               PllPowerUpLatency;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Enter\n");
+  ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper);
+  if (ActiveLaneBitmap != 0) {
+    PllPowerUpLatency = PciePifGetPllPowerUpLatencyTN (Wrapper, Pcie);
+    LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie);
+    if ((LaneBitmapForPllOffInL1 != 0) && ((ActiveLaneBitmap & LaneBitmapForPllOffInL1) == ActiveLaneBitmap)) {
+      LaneBitmapForPllOffInL1 &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper);
+      LaneBitmapForPllOffInL1 |= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, 0, Wrapper);
+      PciePifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Exit\n");
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request boot up voltage
+ *
+ *
+ *
+ * @param[in]  LinkCap             Global GEN capability
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+VOID
+PcieSetVoltageTN (
+  IN      PCIE_LINK_SPEED_CAP   LinkCap,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                      TargetVid;
+  D0F0xBC_xE010705C_STRUCT   D0F0xBC_xE010705C;
+  GMMx63C_STRUCT             GMMx63C;
+  GMMx640_STRUCT             GMMx640;
+  UINT8                      MinVidIndex;
+  D0F0xBC_xE0001008_STRUCT   D0F0xBC_xE0001008;
+  UINT8                      SclkVid[4];
+  UINT8                      Index;
+  PP_FUSE_ARRAY              *PpFuseArray;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Enter\n");
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie));
+  if (PpFuseArray == NULL) {
+    GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, GnbLibGetHeader (Pcie));
+    SclkVid[0] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid0;
+    SclkVid[1] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid1;
+    SclkVid[2] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid2;
+    SclkVid[3] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid3;
+    GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010705C_ADDRESS, &D0F0xBC_xE010705C, 0, GnbLibGetHeader (Pcie));
+    Index = (UINT8) D0F0xBC_xE010705C.Field.PcieGen2Vid;
+  } else {
+    SclkVid[0] = PpFuseArray->SclkVid[0];
+    SclkVid[1] = PpFuseArray->SclkVid[1];
+    SclkVid[2] = PpFuseArray->SclkVid[2];
+    SclkVid[3] = PpFuseArray->SclkVid[3];
+    Index = PpFuseArray->PcieGen2Vid;
+  }
+  if (LinkCap > PcieGen1) {
+    ASSERT (SclkVid[Index] != 0);
+    TargetVid = SclkVid[Index];
+  } else {
+
+    MinVidIndex = 0;
+    for (Index = 0; Index < 4; Index++) {
+      if (SclkVid[Index] > SclkVid[MinVidIndex]) {
+        MinVidIndex = (UINT8) Index;
+      }
+    }
+    ASSERT (SclkVid[MinVidIndex] != 0);
+    TargetVid = SclkVid[MinVidIndex];
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid);
+
+  GnbRegisterReadTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, 0, GnbLibGetHeader (Pcie));
+  //Wait for voltage change to complete before it can issue next voltage change request
+  do {
+    GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie));
+  } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq);
+  //Enable voltage client
+  if (LinkCap == PcieGen1) {
+    GMMx63C.Field.VoltageChangeEn = 0;
+  } else {
+    GMMx63C.Field.VoltageChangeEn = 1;
+  }
+  GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  //Program level and toggle request
+  GMMx63C.Field.VoltageLevel = TargetVid;
+  GMMx63C.Field.VoltageChangeReq = !GMMx63C.Field.VoltageChangeReq;
+  GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  //Wait for voltage change to complete before it can issue next voltage change request
+  do {
+    GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie));
+  } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL power up latency
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ * @retval                 Pll wake up latency in us
+ */
+UINT8
+PciePifGetPllPowerUpLatencyTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  return 35;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max link speed capability supported by this port
+ *
+ *
+ *
+ * @param[in]  Flags              See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
+ * @param[in]  Engine             Pointer to engine config descriptor
+ * @retval     PcieGen1/PcieGen2  Max supported link gen capability
+ */
+PCIE_LINK_SPEED_CAP
+PcieGetLinkSpeedCapTN (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  PCIE_LINK_SPEED_CAP   LinkSpeedCapability;
+  TN_COMPLEX_CONFIG     *ComplexData;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+
+  ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+  LinkSpeedCapability = PcieGen2;
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
+  if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) {
+    LinkSpeedCapability = PcieGen2;
+  } else {
+    LinkSpeedCapability = PcieGen1;
+  }
+  if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) {
+    Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability;
+  }
+  if (Pcie->PsppPolicy == PsppPowerSaving) {
+    LinkSpeedCapability = PcieGen1;
+  }
+  if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) {
+    LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
+  }
+  if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
+    if ((Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) {
+      LinkSpeedCapability = PcieGen1;
+    }
+  }
+  return LinkSpeedCapability;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PLL personality
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieSetPhyPersonalityTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Phy;
+  UINT8                   Mode;
+  if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID || Wrapper->WrapId == DDI2_WRAP_ID) {
+    for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+      if (Wrapper->WrapId == GFX_WRAP_ID) {
+        Mode = (Phy == 0)? 0x1 : 0;
+      } else {
+        Mode = 0x2;
+      }
+      PcieRegisterWriteField (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS),
+        D0F0xE4_PHY_2005_PllMode_OFFSET,
+        D0F0xE4_PHY_2005_PllMode_WIDTH,
+        Mode,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DCC recalibration
+ *
+ *
+ *
+ * @param[in]     Wrapper           Pointer to internal configuration data area
+ * @param[in,out] Buffer            Pointer to buffer
+ * @param[in]     Pcie              Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieForceDccRecalibrationCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePhyForceDccRecalibration (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare for Osc switch
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscPifInitPrePowerdownCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PciePifSetPllRampTime (LongRampup, Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Do Osc switch
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscInitPllModeCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  TN_COMPLEX_CONFIG         *ComplexData;
+  TN_PCIe_SILICON_CONFIG    *FmSilicon;
+  UINT8                     Phy;
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Wrapper);
+  ASSERT (ComplexData != NULL);
+  FmSilicon = &ComplexData->FmSilicon;
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+    Phy = 1;
+  } else if (Wrapper->WrapId == GPP_WRAP_ID) {
+    Phy = 0;
+  } else {
+    ASSERT (FALSE);
+    return AGESA_ERROR;
+  }
+  switch (FmSilicon->OscMode) {
+  case  OscLC:
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_IsLc_OFFSET,
+      D0F0xE4_PHY_2002_IsLc_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    break;
+  case  OscRO:
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_RoCalEn_OFFSET,
+      D0F0xE4_PHY_2002_RoCalEn_WIDTH,
+      0x0,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_RoCalEn_OFFSET,
+      D0F0xE4_PHY_2002_RoCalEn_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post Osc init
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscPifInitPostPowerdownCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
+  PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare PHY for Gen2
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieOscInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  TN_COMPLEX_CONFIG         *ComplexData;
+  TN_PCIe_SILICON_CONFIG    *FmSilicon;
+  D0F0xE4_WRAP_FFF1_STRUCT  D0F0xE4_WRAP_FFF1;
+  AGESA_STATUS              Status;
+  UINT8                     SaveSbLinkAspm;
+  UINT32                    Value;
+
+  Value = 0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Enter\n");
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  ASSERT (ComplexData != NULL);
+  FmSilicon = &ComplexData->FmSilicon;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "  OSC Mode - %s\n",
+    (FmSilicon->OscMode == OscFuses) ? "Fuses" : (
+    (FmSilicon->OscMode == OscRO) ? "RO" : (
+    (FmSilicon->OscMode == OscLC) ? "LC" : (
+    (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown")))
+    );
+
+  if (FmSilicon->OscMode == OscFuses) {
+    D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead (
+                                &ComplexData->GppWrapper,
+                                WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS),
+                                Pcie
+                                );
+
+    if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) {
+      FmSilicon->OscMode = OscRO;
+    } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) {
+      FmSilicon->OscMode = OscLC;
+    } else {
+      FmSilicon->OscMode = OscDefault;
+    }
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "  OSC Mode From Fuses - %s\n",
+      (FmSilicon->OscMode == OscFuses) ? "Fuses" : (
+      (FmSilicon->OscMode == OscRO) ? "RO" : (
+      (FmSilicon->OscMode == OscLC) ? "LC" : (
+      (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown")))
+      );
+  }
+  if (FmSilicon->OscMode != OscDefault) {
+
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscPifInitPrePowerdownCallback,
+      NULL,
+      Pcie
+      );
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscInitPllModeCallback,
+      NULL,
+      Pcie
+      );
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieForceDccRecalibrationCallbackTN,
+      NULL,
+      Pcie
+      );
+
+    SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm;
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1;
+
+    Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie);
+    ASSERT (Status == AGESA_SUCCESS);
+#ifdef  USE_L1_POLLING
+    //Use L1 Entry pooling
+    PciePollLinkForL1Entry (&ComplexData->Port8, Pcie);
+#else
+    {
+      D0F0xBC_x1F630_STRUCT  D0F0xBC_x1F630;
+
+      GnbRegisterReadTN (D0F0xBC_x1F630_TYPE,  D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie));
+      D0F0xBC_x1F630.Field.RECONF_WAIT = 60;
+      GnbRegisterWriteTN (D0F0xBC_x1F630_TYPE,  D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie));
+
+      GnbSmuServiceRequestV4 (
+        ComplexData->Silicon.Address,
+        SMC_MSG_PCIE_PLLSWITCH,
+        0,
+        GnbLibGetHeader (Pcie)
+      );
+    }
+#endif
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled;
+
+    SbPcieLinkAspmControl (&ComplexData->Port8, Pcie);
+    PciePollLinkForL0Exit (&ComplexData->Port8, Pcie);
+
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm;
+
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscPifInitPostPowerdownCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Exit\n");
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h
new file mode 100644
index 0000000000..1f65ce2ecf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * TN specific PCIe configuration data services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIELIBTN_H_
+#define _PCIELIBTN_H_
+
+VOID
+PciePortsVisibilityControlTN (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PciePowerDownPllInL1TN (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieSetVoltageTN (
+  IN      PCIE_LINK_SPEED_CAP   LinkCap,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT8
+PciePifGetPllPowerUpLatencyTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetPhyPersonalityTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieOscInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
new file mode 100644
index 0000000000..2a751be1b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
@@ -0,0 +1,283 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbFamServices.h"
+#include  "PcieLibTN.h"
+#include  "PciePowerGateTN.h"
+#include  "PciePortServicesV4.h"
+#include  "PcieMaxPayloadV4.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieMidPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie);
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    PcieEnableSlotPowerLimit (Engine, Pcie);
+    if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
+      PcieInitPortForIommuV4 (Engine, Pcie);
+    }
+  }
+  PcieEnableAspm (Engine,  Pcie);
+  if (GnbBuildOptions.CfgMaxPayloadEnable) {
+    PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PcieMidPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS         Status;
+  PCIE_LINK_SPEED_CAP  GlobalSpeedCap;
+
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieMidPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+
+  GlobalSpeedCap = PcieUtilGlobalGenCapability (
+                     PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
+                     Pcie
+                     );
+
+
+  PcieSetVoltageTN (GlobalSpeedCap, Pcie);
+
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Late Init.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+AGESA_STATUS
+STATIC
+PcieMidInitCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  PciePwrPowerDownUnusedLanes (Wrapper, Pcie);
+  PciePowerDownPllInL1TN (Wrapper, Pcie);
+  PciePwrClockGatingV4 (Wrapper, Pcie);
+  PcieLockRegisters (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Late Init
+ *
+ *   Late PCIe initialization
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PcieMidInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = PciePowerGateTN (Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PcieMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PcieMidPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieMidInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
new file mode 100644
index 0000000000..b30e92b437
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
@@ -0,0 +1,498 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63818 $   @e \$Date: 2012-01-09 03:02:03 -0600 (Mon, 09 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "PcieLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PciePostEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PciePostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PciePostS3InterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+VOID
+PcieLateRestoreInitTNS3Script (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  IN      UINT16                          ContextLength,
+  IN      VOID*                           Context
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePostPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP LinkSpeedCapability;
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+    PcieLinkSafeMode (Engine, Pcie);
+  }
+  LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
+  PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) {
+    PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie);
+    PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+  }
+  if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    PcieForceCompliance (Engine, Pcie);
+    PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePostS3PortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP       LinkSpeedCapability;
+  PCIE_LINK_TRAINING_STATE  State;
+
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+
+  LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
+  PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
+
+  if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+    PcieLinkSafeMode (Engine, Pcie);
+  }
+
+  if (!PcieConfigIsSbPcieEngine (Engine)) {
+    //
+    // General Port
+    //
+    State = LinkStateDeviceNotPresent;
+    if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) {
+      //
+      // Non hotplug device: we only check status from previous boot
+      //
+      if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        State = LinkStateResetExit;
+      }
+    } else {
+      UINT32  PcieScratch;
+      //
+      //  Get endpoint staus from scratch
+      //
+      PcieScratch = PciePortRegisterRead (Engine, DxF0xE4_x01_ADDRESS, Pcie);
+      //
+      // Hotplug device: we check ep status if reported
+      //
+      if ((PcieScratch & 0x1) == 0) {
+        State = LinkStateResetExit;
+      }
+    }
+    //
+    // For compialnce we always leave link in enabled state
+    //
+    if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) {
+      State = LinkStateResetExit;
+    }
+    PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+  } else {
+    //
+    // SB port
+    //
+    State = LinkStateTrainingSuccess;
+  }
+  PcieTrainingSetPortState (Engine, State, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostEarlyPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  // Distributed Training started at PciePortInit complete it now to get access to PCIe devices
+  if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+    Pcie->TrainingExitState = LinkStateTrainingCompleted;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PciePostPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostS3PortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PciePostS3PortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Init
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PciePostInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP  GlobalSpeedCap;
+
+  GlobalSpeedCap = PcieUtilGlobalGenCapability (
+                     PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
+                     Pcie
+                     );
+
+
+  PcieSetVoltageTN (GlobalSpeedCap, Pcie);
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostEarlyPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PciePostPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostS3InterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+      Status = PciePostS3PortInitTN (Pcie);
+    } else {
+      Status = PciePostPortInitTN (Pcie);
+    }
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe S3 restore
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        Context pointer (not used)
+ */
+VOID
+PcieLateRestoreInitTNS3Script (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  IN      UINT16                          ContextLength,
+  IN      VOID*                           Context
+  )
+{
+  PciePostS3InterfaceTN (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
new file mode 100644
index 0000000000..4197fd842c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
@@ -0,0 +1,383 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe power gate initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "OptionGnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Report used lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePowerGateReportActiveLanesCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  UINT32                  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Engine);
+  if (LaneBitmap != 0) {
+    D0F0xBC_x1F39C.Value = 0;
+    D0F0xBC_x1F39C.Field.Tx = 0;
+    D0F0xBC_x1F39C.Field.Rx = 0;
+    D0F0xBC_x1F39C.Field.Core = 0;
+    D0F0xBC_x1F39C.Field.SkipPhy = 1;
+    D0F0xBC_x1F39C.Field.SkipCore = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    if (PcieConfigIsPcieEngine (Engine) && PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine) == PcieGen2) {
+      D0F0xBC_x1F610_STRUCT  D0F0xBC_x1F610;
+      UINT32                 Gen2LaneBitmap;
+      Gen2LaneBitmap = ((1 << (D0F0xBC_x1F39C.Field.UpperLaneID - D0F0xBC_x1F39C.Field.LowerLaneID + 1)) - 1) << D0F0xBC_x1F39C.Field.LowerLaneID;
+      GnbRegisterReadTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, 0, GnbLibGetHeader (Pcie));
+      D0F0xBC_x1F610.Field.GFXH |= (Gen2LaneBitmap >> 16) & 0xFF;
+      D0F0xBC_x1F610.Field.GFXL |= (Gen2LaneBitmap >> 8) & 0xFF;
+      D0F0xBC_x1F610.Field.GPPSB |= (Gen2LaneBitmap  & 0xFF );
+      GnbRegisterWriteTN (D0F0xBC_x1F610_TYPE,  D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    }
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_ON,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Wrapper         Pointer to wrapper configuration
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ * @retval          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePowerGatePowerDownUnusedLanesCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Index;
+  UINTN                   State;
+  UINT32                  LaneBitmap;
+  UINT16                  StartLane;
+  UINT16                  EndLane;
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Enter\n");
+
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (
+                 LANE_TYPE_PHY_NATIVE_ALL,
+                 LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG,
+                 Wrapper
+                 );
+  IDS_HDT_CONSOLE (GNB_TRACE, " Lane Bitmap 0x%x\n", LaneBitmap);
+  if (LaneBitmap != 0) {
+    State = 0;
+    StartLane = 0;
+    EndLane = 0;
+    for (Index = 0; Index <= (LibAmdBitScanReverse (LaneBitmap) + 1); Index++) {
+      if ((State == 0) && ((LaneBitmap & (1 << Index)) != 0)) {
+        StartLane = Index;
+        State = 1;
+      } else if ((State == 1) && ((LaneBitmap & (1 << Index)) == 0)) {
+        EndLane = Index - 1;
+        State = 0;
+        GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+        D0F0xBC_x1F39C.Field.Tx = 1;
+        D0F0xBC_x1F39C.Field.Rx = 1;
+        D0F0xBC_x1F39C.Field.Core = 1;
+        D0F0xBC_x1F39C.Field.LowerLaneID = StartLane + Wrapper->StartPhyLane;
+        D0F0xBC_x1F39C.Field.UpperLaneID = EndLane + Wrapper->StartPhyLane;
+        IDS_HDT_CONSOLE (
+          PCIE_MISC,
+          "  LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+          D0F0xBC_x1F39C.Field.LowerLaneID,
+          D0F0xBC_x1F39C.Field.UpperLaneID,
+          D0F0xBC_x1F39C.Field.Tx,
+          D0F0xBC_x1F39C.Field.Rx,
+          D0F0xBC_x1F39C.Field.Core
+          );
+        GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+        GnbSmuServiceRequestV4 (
+          PcieConfigGetParentSilicon (Wrapper)->Address,
+          SMC_MSG_PHY_LN_OFF,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          GnbLibGetHeader (Pcie)
+          );
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePowerGatePowerDownLanesCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  UINT32                  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Engine);
+  if (LaneBitmap != 0) {
+    GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.Core = 0;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  PCIe Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Engine);
+  if (LaneBitmap != 0) {
+    GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.Core = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  DDI Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Power gate init
+ *
+ *   Late PCIe initialization
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ */
+
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   PowerGatingFlags;
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Enter\n");
+  PowerGatingFlags = GnbBuildOptions.CfgPciePowerGatingFlags;
+  // Report used lanes
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE,
+    PciePowerGateReportActiveLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+
+  IDS_OPTION_HOOK (IDS_GNB_PCIE_POWER_GATING, &PowerGatingFlags, GnbLibGetHeader (Pcie));
+
+  // Update flags
+  GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+  if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_CORE) == 0) {
+    D0F0xBC_x1F39C.Field.SkipCore = 0;
+  }
+  if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_PHY) == 0) {
+    D0F0xBC_x1F39C.Field.SkipPhy = 0;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  // Power down unused lanes
+  PcieConfigRunProcForAllWrappers (
+    DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER,
+    PciePowerGatePowerDownUnusedLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+  //Power down hotplug lanes
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE,
+    PciePowerGatePowerDownLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Exit\n");
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
new file mode 100644
index 0000000000..b8d2116a96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe power gate initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERGATETN_H_
+#define _PCIEPOWERGATETN_H_
+
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
new file mode 100644
index 0000000000..faa2fa8f80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
@@ -0,0 +1,258 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65061 $   @e \$Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "PcieComplexDataTN.h"
+#include  "GnbRegistersTN.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
+  {
+    WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS),
+    D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
+    0
+  },
+  {
+    PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  }
+ };
+
+CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN  = {
+  &PcieInitEarlyTable[0],
+  sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
+};
+
+STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
+  {
+    D0F0xE4_CORE_0020_ADDRESS,
+    D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
+    D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK,
+    (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0010_ADDRESS,
+    D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK,
+    (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_001C_ADDRESS,
+    D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
+    D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
+    D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
+    (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
+    (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
+    (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0040_ADDRESS,
+    D0F0xE4_CORE_0040_PElecIdleMode_MASK,
+    (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0002_ADDRESS,
+    D0F0xE4_CORE_0002_HwDebug_0__MASK,
+    (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET)
+  },
+  {
+    D0F0xE4_CORE_00C1_ADDRESS,
+    D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
+    D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
+    (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
+    (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_00B0_ADDRESS,
+    D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK,
+    (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
+  }
+};
+
+CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN  = {
+  &CoreInitTable[0],
+  sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
+};
+
+
+STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
+  {
+    DxF0xE4_x02_ADDRESS,
+    DxF0xE4_x02_RegsLcAllowTxL1Control_MASK,
+    (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET)
+  },
+  {
+    DxF0xE4_x70_ADDRESS,
+    DxF0xE4_x70_RxRcbCplTimeoutMode_MASK,
+    (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET)
+  },
+  {
+    DxF0xE4_xA0_ADDRESS,
+    DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK,
+    (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) |
+    (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) |
+    (0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET)
+  },
+  {
+    DxF0xE4_xA1_ADDRESS,
+    DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK,
+    (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET)
+  },
+  {
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK,
+    (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) |
+    (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET)
+  },
+  {
+    DxF0xE4_xA3_ADDRESS,
+    DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK,
+    (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET)
+  },
+  {
+    DxF0xE4_xB1_ADDRESS,
+    DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK,
+    (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) |
+    (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET)
+  }
+};
+
+CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN  = {
+  &PortInitEarlyTable[0],
+  sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
+};
+
+
+STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
+  {
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcDynLanesPwrState_MASK,
+    (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET)
+  },
+  {
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK,
+    (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET)
+  }
+};
+
+CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN  = {
+  &PortInitMidTable[0],
+  sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
new file mode 100644
index 0000000000..fb44d8328e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -0,0 +1,361 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbIvrsLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define IVRS_TABLE_LENGTH 8 * 1024
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+GnbBuildIvmdList (
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbIommuIvrsTableDump (
+  IN       VOID                 *Ivrs,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+AGESA_STATUS
+GnbIommuIvrsTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+IOMMU_IVRS_HEADER IvrsHeader = {
+  {'I', 'V', 'R', 'S'},
+  sizeof (IOMMU_IVRS_HEADER),
+  2,
+  0,
+  {'A', 'M', 'D', ' ', ' ', 0},
+  {'A', 'M', 'D', 'I', 'O', 'M', 'M', 'U'},
+  1,
+  {'A','M','D',' '},
+  0,
+  0,
+  0
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build IVRS table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        AGESA_SUCCESS
+ * @retval        AGESA_ERROR
+ */
+
+AGESA_STATUS
+GnbIommuIvrsTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AGESA_STATUS            Status;
+  AMD_LATE_PARAMS         *LateParamsPtr;
+  VOID                    *Ivrs;
+  BOOLEAN                 IvrsSupport;
+  GNB_HANDLE              *GnbHandle;
+
+  Status = AGESA_SUCCESS;
+  LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader;
+  IvrsSupport = FALSE;
+  Ivrs = LateParamsPtr->AcpiIvrs;
+  if (Ivrs == NULL) {
+    Ivrs = GnbAllocateHeapBuffer (
+             AMD_ACPI_IVRS_BUFFER_HANDLE,
+             IVRS_TABLE_LENGTH,
+             StdHeader
+             );
+    ASSERT (Ivrs != NULL);
+    if (Ivrs == NULL) {
+      return  AGESA_ERROR;
+    }
+    LateParamsPtr->AcpiIvrs = Ivrs;
+  }
+  LibAmdMemFill (Ivrs, 0x0, IVRS_TABLE_LENGTH, StdHeader);
+  LibAmdMemCopy (Ivrs, &IvrsHeader, sizeof (IvrsHeader), StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  while (GnbHandle != NULL) {
+    if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Build IVRS for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      IvrsSupport = TRUE;
+      GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdBlock, Ivrs, StdHeader);
+      GnbBuildIvmdList (IvrsIvmdBlock, Ivrs, StdHeader);
+      if (GnbBuildOptions.IvrsRelativeAddrNamesSupport) {
+        GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdrBlock, Ivrs, StdHeader);
+        GnbBuildIvmdList (IvrsIvmdrBlock, Ivrs, StdHeader);
+      }
+    }
+    GnbHandle = GnbGetNextHandle (GnbHandle);
+  }
+  if (IvrsSupport == TRUE) {
+    ChecksumAcpiTable ((ACPI_TABLE_HEADER*) Ivrs, StdHeader);
+    GNB_DEBUG_CODE (GnbIommuIvrsTableDump (Ivrs, StdHeader));
+  } else {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  IVRS table not generated\n");
+    LateParamsPtr->AcpiIvrs = NULL;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build IVMD list
+ *
+ *
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbBuildIvmdList (
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  IOMMU_EXCLUSION_RANGE_DESCRIPTOR  *IvrsExclusionRangeList;
+  IVRS_IVMD_ENTRY                   *Ivmd;
+  UINT16                            StartId;
+  UINT16                            EndId;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Entry\n");
+  IvrsExclusionRangeList = ((AMD_LATE_PARAMS*)StdHeader)->IvrsExclusionRangeList;
+  if (IvrsExclusionRangeList != NULL) {
+    // Process the entire IvrsExclusionRangeList here and create an IVMD for eache entry
+    IDS_HDT_CONSOLE (GNB_TRACE, "Process Exclusion Range List\n");
+    while ((IvrsExclusionRangeList->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) {
+      if ((IvrsExclusionRangeList->Flags & DESCRIPTOR_IGNORE) == 0) {
+        // Address of IVMD entry
+        Ivmd = (IVRS_IVMD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength);
+        StartId =
+          (IvrsExclusionRangeList->RequestorIdStart.Bus << 8) +
+          (IvrsExclusionRangeList->RequestorIdStart.Device << 3) +
+          (IvrsExclusionRangeList->RequestorIdStart.Function);
+        EndId =
+          (IvrsExclusionRangeList->RequestorIdEnd.Bus << 8) +
+          (IvrsExclusionRangeList->RequestorIdEnd.Device << 3) +
+          (IvrsExclusionRangeList->RequestorIdEnd.Function);
+        GnbIvmdAddEntry (
+          Type,
+          StartId,
+          EndId,
+          IvrsExclusionRangeList->RangeBaseAddress,
+          IvrsExclusionRangeList->RangeLength,
+          Ivmd,
+          StdHeader);
+        // Add entry size to existing table length
+        ((IOMMU_IVRS_HEADER *)Ivrs)->TableLength += sizeof (IVRS_IVMD_ENTRY);
+      }
+      // Point to next entry in IvrsExclusionRangeList
+      IvrsExclusionRangeList++;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump IVRS table
+ *
+ *
+ * @param[in]     Ivrs            Pointer to IVRS table
+ * @param[in]     StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbIommuIvrsTableDump (
+  IN       VOID                 *Ivrs,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8   *Block;
+  UINT8   *Entry;
+  Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER);
+  IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table Start -----------> \n");
+  IDS_HDT_CONSOLE (GNB_TRACE, "  IVInfo           = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo);
+  while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) {
+    if (*Block == IvrsIvhdBlock) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block Start -------->\n");
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Flags            = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->Flags);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  DeviceId         = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->DeviceId);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  CapabilityOffset = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->CapabilityOffset);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  BaseAddress      = 0x%08x%08x\n", (UINT32) (((IVRS_IVHD_ENTRY *) Block)->BaseAddress >> 32), (UINT32) ((IVRS_IVHD_ENTRY *) Block)->BaseAddress);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  PCI Segment      = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->PciSegment);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  IommuInfo        = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuInfo);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  IommuEfr         = 0x%08x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuEfr);
+      Entry = Block + sizeof (IVRS_IVHD_ENTRY);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block Device Entries Start -------->\n");
+      while (Entry < (Block + ((IVRS_IVHD_ENTRY *) Block)->Length)) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "  ");
+        switch (*Entry) {
+        case IvhdEntrySelect:
+        case IvhdEntryEndRange:
+          GnbLibDebugDumpBuffer (Entry, 4, 1, 4);
+          Entry = Entry + 4;
+          break;
+        case IvhdEntryStartRange:
+          GnbLibDebugDumpBuffer (Entry, 8, 1, 8);
+          Entry = Entry + 8;
+          break;
+        case IvhdEntryAliasStartRange:
+          GnbLibDebugDumpBuffer (Entry, 12, 1, 12);
+          Entry = Entry + 12;
+          break;
+        case IvhdEntryAliasSelect:
+        case IvhdEntryExtendedSelect:
+        case IvhdEntrySpecialDevice:
+          GnbLibDebugDumpBuffer (Entry, 8, 1, 8);
+          Entry = Entry + 8;
+          break;
+        case IvhdEntryPadding:
+          Entry = Entry + 4;
+          break;
+        default:
+          IDS_HDT_CONSOLE (GNB_TRACE, "  Unsupported entry type [%d]\n");
+          ASSERT (FALSE);
+        }
+      }
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block Device Entries End -------->\n");
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block End ---------->\n");
+      Block = Block + ((IVRS_IVHD_ENTRY *) Block)->Length;
+    } else if (
+        (*Block == IvrsIvmdBlock) ||
+        (*Block == IvrsIvmdBlockRange) ||
+        (*Block == IvrsIvmdBlockSingle) ||
+        (*Block == IvrsIvmdrBlock) ||
+        (*Block == IvrsIvmdrBlockSingle)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVMD Block Start -------->\n");
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Flags            = 0x%02x\n", ((IVRS_IVMD_ENTRY *) Block)->Flags);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  DeviceId         = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->DeviceId);
+      switch (*Block) {
+      case IvrsIvmdBlock:
+      case IvrsIvmdrBlock:
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Applies to all devices\n");
+        break;
+      case IvrsIvmdBlockSingle:
+      case IvrsIvmdrBlockSingle:
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Applies to a single device\n");
+        break;
+      default:
+        IDS_HDT_CONSOLE (GNB_TRACE, "  DeviceId End   = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->AuxiliaryData);
+      }
+      IDS_HDT_CONSOLE (GNB_TRACE, "  StartAddress     = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockStart >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockStart);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  BockLength       = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockLength >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockLength);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVMD Block End ---------->\n");
+      Block = Block + ((IVRS_IVMD_ENTRY *) Block)->Length;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table Raw Data --------> \n");
+  GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16);
+  IDS_HDT_CONSOLE (GNB_TRACE, "\n");
+  IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table End -------------> \n");
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h
new file mode 100644
index 0000000000..c48224f970
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBIOMMUIVRS_H_
+#define _GNBIOMMUIVRS_H_
+
+AGESA_STATUS
+GnbIommuIvrsTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c
new file mode 100644
index 0000000000..b5eb7ed124
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFamServices.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Iommu Scratch Memory Range
+ * 1) code needs to be executed at Late Init
+ * 2) Allocate heap using  heap type HEAP_RUNTIME_SYSTEM_MEM
+ * 3) Allocate enough memory to be able to get address aligned required by register
+ * 4) Assign same address to all Gnb in system
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+AGESA_STATUS
+GnbIommuScratchMemoryRangeInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+  UINT32                AddressLow;
+  UINT32                AddressHigh;
+  GNB_HANDLE            *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Enter\n");
+
+  AllocHeapParams.RequestedBufferSize = 128;
+  AllocHeapParams.BufferHandle = AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE;
+  AllocHeapParams.Persist = HEAP_RUNTIME_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  Iommu Scratch Memory not allocated.\n");
+    ASSERT (FALSE);
+    return AGESA_FATAL;
+  }
+
+  AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK;
+  AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK;
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  while (GnbHandle != NULL) {
+    if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Set Iommu Scratch Memory for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      GnbLibPciIndirectWrite (
+        GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+        D0F0x98_x27_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        &AddressLow,
+        StdHeader);
+
+      GnbLibPciIndirectWrite (
+        GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+        D0F0x98_x26_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        &AddressHigh,
+        StdHeader);
+    }
+    GnbHandle = GnbGetNextHandle (GnbHandle);
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Exit\n");
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
new file mode 100644
index 0000000000..d18493eb09
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
@@ -0,0 +1,267 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64895 $   @e \$Date: 2012-02-02 01:01:48 -0600 (Thu, 02 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbIommu.h"
+#include  "GnbFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbIommuIvrs.h"
+#include  "GnbIvrsLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry for device range
+ *
+ *
+ * @param[in]  StartRange      Address of start range
+ * @param[in]  EndRange        Address of end range
+ * @param[in]  DataSetting     Data setting
+ * @param[in]  Ivhd            Pointer to IVHD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvhdAddDeviceRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  IVHD_GENERIC_ENTRY  *Entry;
+  Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
+  Entry->Type = IvhdEntryStartRange;
+  Entry->DeviceId = DEVICE_ID (StartRange);
+  Entry->DataSetting = DataSetting;
+  Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
+  Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
+  Entry->Type = IvhdEntryEndRange;
+  Entry->DeviceId = DEVICE_ID (EndRange);
+  Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry for aliased range
+ *
+ *
+ * @param[in]  StartRange      Address of start range
+ * @param[in]  EndRange        Address of end range
+ * @param[in]  Alias           Address of alias requestor ID for range
+ * @param[in]  DataSetting     Data setting
+ * @param[in]  Ivhd            Pointer to IVHD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvhdAddDeviceAliasRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       PCI_ADDR             Alias,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  IVHD_ALIAS_ENTRY    *RangeEntry;
+  IVHD_GENERIC_ENTRY  *Entry;
+  UINT16              Offset;
+  Offset = (Ivhd->Length + 0x7) & (~ 0x7);
+  RangeEntry = (IVHD_ALIAS_ENTRY *) ((UINT8 *) Ivhd + Offset);
+  RangeEntry->Type = IvhdEntryAliasStartRange;
+  RangeEntry->DeviceId = DEVICE_ID (StartRange);
+  RangeEntry->AliasDeviceId = DEVICE_ID (Alias);
+  RangeEntry->DataSetting = DataSetting;
+  Ivhd->Length = sizeof (IVHD_ALIAS_ENTRY) + Offset;
+  Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
+  Entry->Type = IvhdEntryEndRange;
+  Entry->DeviceId = DEVICE_ID (EndRange);
+  Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry for special device
+ *
+ *
+ * @param[in]  SpecialDevice   Special device Type
+ * @param[in]  Device          Address of requestor ID for special device
+ * @param[in]  Id              Apic ID/ Hpet ID
+ * @param[in]  DataSetting     Data setting
+ * @param[in]  Ivhd            Pointer to IVHD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvhdAddSpecialDeviceEntry (
+  IN       IVHD_SPECIAL_DEVICE  SpecialDevice,
+  IN       PCI_ADDR             Device,
+  IN       UINT8                Id,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  IVHD_SPECIAL_ENTRY  *SpecialEntry;
+  UINT16               Offset;
+  Offset = (Ivhd->Length + 0x7) & (~ 0x7);
+  SpecialEntry = (IVHD_SPECIAL_ENTRY *) ((UINT8 *) Ivhd + Offset);
+  SpecialEntry->Type = IvhdEntrySpecialDevice;
+  SpecialEntry->AliasDeviceId = DEVICE_ID (Device);
+  SpecialEntry->Variety = (UINT8) SpecialDevice;
+  SpecialEntry->Handle = Id;
+  SpecialEntry->DataSetting = DataSetting;
+  Ivhd->Length = sizeof (IVHD_SPECIAL_ENTRY) + Offset;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVMD entry
+ *
+ *
+ * @param[in]  Type            Root type for IVMD (IvrsIvmdBlock or IvrsIvmdrBlock)
+ * @param[in]  StartDevice     Device ID of start device range
+ *                             Use 0x0000 for ALL
+ * @param[in]  EndDevice       Device ID of end device range
+ *                             Use 0xFFFF for ALL
+ *                             Use == StartDevice for specific device
+ * @param[in]  BlockAddress    Address of memory block to be excluded
+ * @param[in]  BlockLength     Length of memory block go be excluded
+ * @param[in]  Ivmd            Pointer to IVMD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvmdAddEntry (
+  IN       IVRS_BLOCK_TYPE      Type,
+  IN       UINT16               StartDevice,
+  IN       UINT16               EndDevice,
+  IN       UINT64               BlockAddress,
+  IN       UINT64               BlockLength,
+  IN       IVRS_IVMD_ENTRY      *Ivmd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  Ivmd->Flags = IVMD_FLAG_EXCLUSION_RANGE;
+  Ivmd->Length = sizeof (IVRS_IVMD_ENTRY);
+  Ivmd->DeviceId = StartDevice;
+  Ivmd->AuxiliaryData = 0x0;
+  Ivmd->Reserved = 0x0000000000000000;
+  Ivmd->BlockStart = BlockAddress;
+  Ivmd->BlockLength = BlockLength;
+  if (Type == IvrsIvmdBlock) {
+    if (StartDevice == EndDevice) {
+      Ivmd->Type = IvrsIvmdBlockSingle;
+    } else if ((StartDevice == 0x0000) && (EndDevice == 0xFFFF)) {
+      Ivmd->Type = IvrsIvmdBlock;
+    } else {
+      Ivmd->Type = IvrsIvmdBlockRange;
+      Ivmd->AuxiliaryData = EndDevice;
+    }
+  } else {
+    if (StartDevice == EndDevice) {
+      Ivmd->Type = IvrsIvmdrBlockSingle;
+    } else {
+      Ivmd->Type = IvrsIvmdrBlock;
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h
new file mode 100644
index 0000000000..5291d34f1b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBIVRSLIB_H_
+#define _GNBIVRSLIB_H_
+
+
+VOID
+GnbIvhdAddDeviceRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+GnbIvhdAddDeviceAliasRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       PCI_ADDR             Alias,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+GnbIvhdAddSpecialDeviceEntry (
+  IN       IVHD_SPECIAL_DEVICE  SpecialDevice,
+  IN       PCI_ADDR             Device,
+  IN       UINT8                Id,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+GnbIvmdAddEntry (
+  IN       IVRS_BLOCK_TYPE      Type,
+  IN       UINT16               StartDevice,
+  IN       UINT16               EndDevice,
+  IN       UINT64               BlockAddress,
+  IN       UINT64               BlockLength,
+  IN       IVRS_IVMD_ENTRY      *Ivmd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
new file mode 100644
index 0000000000..f160e8bcb1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
@@ -0,0 +1,203 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB UNB library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuServices.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFamServices.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Host bridge PCI Address
+ *
+ *
+ *
+ * @param[in]   GnbHandle      Socket ID
+ * @param[in]   StdHeader      Standard configuration header
+ * @retval                     PCI address of GNB for a given socket/silicon.
+ */
+
+PCI_ADDR
+GnbFmGetPciAddress (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  GnbPciAddress;
+  UINT8     NodeId;
+  UINT8     Register;
+  UINT32    Value;
+  GnbPciAddress.AddressValue = ILLEGAL_SBDFO;
+  NodeId = GnbGetNodeId (GnbHandle);
+  for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) {
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader);
+    if (((Value >> 4) & 0x7) == NodeId) {
+      GnbPciAddress.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0, 0, 0);
+      break;
+    }
+  }
+  ASSERT (GnbPciAddress.AddressValue != ILLEGAL_SBDFO);
+  return GnbPciAddress;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bus range decoded by GNB
+ *
+ * Final bus allocation can not be assumed until AmdInitMid
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  StartBusNumber  Beggining of the Bus Range
+ * @param[out]  EndBusNumber    End of the Bus Range
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+AGESA_STATUS
+GnbFmGetBusDecodeRange (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *StartBusNumber,
+     OUT   UINT8                      *EndBusNumber,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT8         NodeId;
+  UINT8         Register;
+  UINT32        Value;
+  AGESA_STATUS  Status;
+  Status = AGESA_ERROR;
+  NodeId = GnbGetNodeId (GnbHandle);
+  for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) {
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader);
+    if (((Value >> 4) & 0x7) == NodeId) {
+      *StartBusNumber = (UINT8) ((Value >> 16) & 0xff);
+      *EndBusNumber = (UINT8) ((Value >> 24) & 0xff);
+      Status = AGESA_SUCCESS;
+      break;
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link to which GNB connected to
+ *
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  LinkId          Link to which GNB connected to
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+
+AGESA_STATUS
+GnbFmGetLinkId (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *LinkId,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32  Value;
+  ASSERT (GnbHandle->NodeId != 0xFF);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18 + GnbHandle->NodeId, 0, 0x1A0), AccessWidth32, &Value, StdHeader);
+  *LinkId = LibAmdBitScanForward (Value & 0xAAAA) / 2;
+  ASSERT (*LinkId < 8);
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
new file mode 100644
index 0000000000..942d34d539
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -0,0 +1,432 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init NB set top of memory
+ *
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+AGESA_STATUS
+GnbSetTom (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS  Status;
+  UINT64        MsrData;
+  UINT32        Value;
+  Status = AGESA_SUCCESS;
+  //Read memory size below 4G from MSR C001_001A
+  LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader);
+  //Write to NB register 0x90
+  Value = (UINT32)MsrData & 0xFF800000;     //Keep bits 31:23
+  GnbLibPciRMW (
+    NbPciAddress.AddressValue | D0F0x90_ADDRESS,
+    AccessS3SaveWidth32,
+    0x007FFFFF,
+    Value,
+    StdHeader
+    );
+  if (Value == 0) {
+    Status = AGESA_WARNING;
+  }
+
+  LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
+  if ((MsrData & BIT21) != 0) {
+    //Read memory size above 4G from MSR C001_001D
+    LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader);
+    // Write memory size[39:32] to indirect register 1A[7:0]
+    Value = (UINT32) ((MsrData >> 32) & 0xFF);
+    GnbLibPciIndirectRMW (
+      NbPciAddress.AddressValue | D0F0x60_ADDRESS,
+      D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      0xFFFFFF00,
+      Value,
+      StdHeader
+    );
+
+    // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0
+    Value = (UINT32)MsrData & 0xFF800000;     //Keep bits 31:23
+    Value |= BIT0;                            // Enable top of memory
+    GnbLibPciIndirectRMW (
+      NbPciAddress.AddressValue | D0F0x60_ADDRESS,
+      D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      0x007FFFFF,
+      Value,
+      StdHeader
+    );
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Avoid LPC DMA transaction deadlock
+ *
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbLpcDmaDeadlockPrevention (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // For GPP Link core, enable special NP memory write protocol on the  processor side PCIE controller
+  GnbLibPciIndirectRMW (
+    NbPciAddress.AddressValue | D0F0xE0_ADDRESS,
+    CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS),
+    AccessWidth32,
+    0xFFFFFFFF,
+    1 << 9 ,
+    StdHeader
+  );
+
+  //Enable special NP memory write protocol in ORB
+  GnbLibPciIndirectRMW (
+    NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+    D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessS3SaveWidth32,
+    0xFFFFFFFF,
+    1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET,
+    StdHeader
+  );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Dynamic Wake
+ * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
+ *   that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high).
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbOrbDynamicWake (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+
+  ex495_STRUCT     ex495  ;
+
+  GnbLibPciIndirectRead (
+    NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+    0x2c  | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessWidth32,
+    &ex495.Value,
+    StdHeader
+    );
+
+  // Enable Dynamic wake
+  // Wake Hysteresis timer value.  Specifies the number of SMU pulses to count.
+  if (GnbBuildOptions.CfgOrbDynWakeEnable) {
+    ex495.Field.ex495_1  = 1;
+  } else {
+    ex495.Field.ex495_1  = 0;
+  }
+  ex495.Field.ex495_3  = 0x64;
+
+  IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &ex495, StdHeader);
+
+  GnbLibPciIndirectWrite (
+    NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+    0x2c  | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessS3SaveWidth32,
+    &ex495.Value,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lock NB registers
+ *
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbLock (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  GnbLibPciIndirectWriteField (
+    NbPciAddress.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
+    D0F0x64_x00_HwInitWrLock_OFFSET,
+    D0F0x64_x00_HwInitWrLock_WIDTH,
+    0x1,
+    TRUE,
+    StdHeader
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * UnitID Clumping
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbClumpUnitID (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32  Value;
+  GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 2, 0, 0), AccessWidth32, &Value, StdHeader);
+  if (Value != 0xFFFFFFFF) {
+    GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 3, 0, 0), AccessWidth32, &Value, StdHeader);
+    if (Value == 0xFFFFFFFF) {
+      GnbLibPciIndirectRMW (
+        NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+        0x3a  | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        0xFFFFFFFF,
+        1 << 3 /* D0F0x98_x3A_ClumpingEn_OFFSET*/,
+        StdHeader
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the index of highest SCLK VID
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID index
+ */
+UINT8
+GnbLocateHighestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8             MaxVid;
+  UINT8             MaxVidIndex;
+  UINTN             Index;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray == NULL) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  ERROR!!! Heap Location\n");
+    return 0;
+  }
+
+  MaxVidIndex = 0;
+  MaxVid = 0xff;
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->SclkVid[Index] != 0 && PpFuseArray->SclkVid[Index] < MaxVid) {
+      MaxVid = PpFuseArray->SclkVid[Index];
+      MaxVidIndex = (UINT8) Index;
+    }
+  }
+  ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0);
+  return MaxVidIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the index of lowest SCLK VID
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID index
+ */
+UINT8
+GnbLocateLowestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8             MinVidIndex;
+  UINTN             Index;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray == NULL) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  ERROR!!! Heap Location\n");
+    return 0;
+  }
+
+  MinVidIndex = 0;
+
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->SclkVid[Index] > PpFuseArray->SclkVid[MinVidIndex]) {
+      MinVidIndex = (UINT8) Index;
+    }
+  }
+  ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0);
+  return MinVidIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the highest SCLK VID (high voltage)
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID
+ */
+UINT8
+GnbLocateHighestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                         MaxVidIndex;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+
+  MaxVidIndex = GnbLocateHighestVidIndex (StdHeader);
+  ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0);
+  return PpFuseArray->SclkVid[MaxVidIndex];
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the lowest SCLK VID (low voltage)
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID
+ */
+UINT8
+GnbLocateLowestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                         MinVidIndex;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  MinVidIndex = GnbLocateLowestVidIndex (StdHeader);
+  ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0);
+  return PpFuseArray->SclkVid[MinVidIndex];
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
new file mode 100644
index 0000000000..948ee4c404
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBNBINITLIBV1_H_
+#define _GNBNBINITLIBV1_H_
+
+
+AGESA_STATUS
+GnbSetTom (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLpcDmaDeadlockPrevention (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbOrbDynamicWake (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLock (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbClumpUnitID (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+UINT8
+GnbLocateHighestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+UINT8
+GnbLocateLowestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+UINT8
+GnbLocateHighestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+UINT8
+GnbLocateLowestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
new file mode 100644
index 0000000000..faf72986d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -0,0 +1,620 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "GnbFamServices.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define SMC_RAM_START_ADDR 0x10000ul
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA     ScanData;
+  GNB_TOPOLOGY_INFO     *TopologyInfo;
+} GNB_TOPOLOGY_INFO_DATA;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GnbSmuServiceRequestV4S3Script (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      UINT16                ContextLength,
+  IN      VOID                  *Context
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check a PCIE device to see if it supports phantom functions
+ *
+ * @param[in] Device      Device pci address
+ * @param[in] StdHeader   Standard configuration header
+ * @return    TRUE        Current device supports phantom functions
+ */
+STATIC BOOLEAN
+GnbCheckPhantomFuncSupport (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  UINT8   PcieCapPtr;
+  UINT32  Value;
+  Value = 0;
+
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 4), AccessWidth32, &Value, StdHeader);
+  }
+  return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status
+ */
+
+SCAN_STATUS
+STATIC
+GnbTopologyInfoScanCallback (
+  IN       PCI_ADDR                 Device,
+  IN OUT   GNB_PCI_SCAN_DATA        *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  GNB_TOPOLOGY_INFO_DATA  *GnbTopologyInfo;
+  PCIE_DEVICE_TYPE        DeviceType;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  GnbIommuInfoScanCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  GnbTopologyInfo = (GNB_TOPOLOGY_INFO_DATA *)ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData);
+    break;
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDevicePcieToPcix:
+    GnbTopologyInfo->TopologyInfo->PcieToPciexBridge = TRUE;
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    if (GnbCheckPhantomFuncSupport (Device, ScanData->StdHeader)) {
+      GnbTopologyInfo->TopologyInfo->PhantomFunction = TRUE;
+    }
+    ScanStatus = SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  default:
+    break;
+  }
+  return ScanStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get IOMMU topology info
+ *
+ *
+ *
+ * @param[in] StartPciAddress   Start PCI address
+ * @param[in] EndPciAddress     End PCI address
+ * @param[in] TopologyInfo      Topology info structure
+ * @param[in] StdHeader         Standard Configuration Header
+ */
+
+AGESA_STATUS
+GnbGetTopologyInfoV4 (
+  IN       PCI_ADDR                  StartPciAddress,
+  IN       PCI_ADDR                  EndPciAddress,
+     OUT   GNB_TOPOLOGY_INFO         *TopologyInfo,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  GNB_TOPOLOGY_INFO_DATA  GnbTopologyInfo;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Enter\n");
+  GnbTopologyInfo.ScanData.GnbScanCallback = GnbTopologyInfoScanCallback;
+  GnbTopologyInfo.ScanData.StdHeader = StdHeader;
+  GnbTopologyInfo.TopologyInfo = TopologyInfo;
+  GnbLibPciScan (StartPciAddress, EndPciAddress, &GnbTopologyInfo.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SMU service request
+ *
+ *
+ * @param[in]  GnbPciAddress   GNB PCI address
+ * @param[in]  RequestId       Request ID
+ * @param[in]  AccessFlags     See GNB_ACCESS_FLAGS_* definitions
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+VOID
+GnbSmuServiceRequestV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       UINT8                    RequestId,
+  IN       UINT32                   AccessFlags,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  D0F0xBC_xE0003004_STRUCT  D0F0xBC_xE0003004;
+  D0F0xBC_xE0003000_STRUCT  D0F0xBC_xE0003000;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Enter\n");
+  IDS_HDT_CONSOLE (NB_MISC, "  Service Request %d\n", RequestId);
+
+  if ((AccessFlags & GNB_REG_ACC_FLAG_S3SAVE) != 0) {
+    SMU_MSG_CONTEXT SmuMsgContext;
+    SmuMsgContext.GnbPciAddress.AddressValue = GnbPciAddress.AddressValue;
+    SmuMsgContext.RequestId = RequestId;
+    S3_SAVE_DISPATCH (StdHeader, GnbSmuServiceRequestV4S3Script_ID, sizeof (SmuMsgContext), &SmuMsgContext);
+  }
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader);
+  } while (D0F0xBC_xE0003004.Field.IntDone == 0x0);
+  GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader);
+  D0F0xBC_xE0003000.Field.IntToggle = ~D0F0xBC_xE0003000.Field.IntToggle;
+  D0F0xBC_xE0003000.Field.ServiceIndex = RequestId;
+  GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader);
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader);
+  } while (D0F0xBC_xE0003004.Field.IntAck == 0x0);
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader);
+  } while (D0F0xBC_xE0003004.Field.IntDone == 0x0);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Exit\n");
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SMU service request for S3 script
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @param[in]  ContextLength   Context length
+ * @param[in]  Context         Pointer to Context
+ */
+
+VOID
+GnbSmuServiceRequestV4S3Script (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      UINT16                ContextLength,
+  IN      VOID                  *Context
+  )
+{
+  SMU_MSG_CONTEXT   *SmuMsgContext;
+  SmuMsgContext =  (SMU_MSG_CONTEXT *) Context;
+  GnbSmuServiceRequestV4 (SmuMsgContext->GnbPciAddress, SmuMsgContext->RequestId, 0, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SMU firmware download
+ *
+ *
+ * @param[in]  GnbPciAddress   GNB Pci Address
+ * @param[in]  Firmware        Pointer tp firmware
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+AGESA_STATUS
+GnbSmuFirmwareLoadV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       FIRMWARE_HEADER_V4       *Firmware,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  UINT32                     Index;
+  D0F0xBC_xE00030A4_STRUCT  D0F0xBC_xE00030A4;
+  D0F0xBC_xE0000004_STRUCT  D0F0xBC_xE0000004;
+  D0F0xBC_xE0003088_STRUCT  D0F0xBC_xE0003088;
+  ex1005_STRUCT   ex1005 ;
+  D0F0xBC_x1F380_STRUCT      D0F0xBC_x1F380;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Enter\n");
+  IDS_HDT_CONSOLE (NB_MISC, "  Firmware version 0x%x\n", Firmware->Version);
+  // Step 2, 10, make sure Rom firmware sequance is done
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0000004_ADDRESS, AccessWidth32, &D0F0xBC_xE0000004.Value, StdHeader);
+  } while (D0F0xBC_xE0000004.Field.boot_seq_done == 0);
+  // Step 1, check if firmware running in protected mode
+  GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE00030A4_ADDRESS, AccessWidth32, &D0F0xBC_xE00030A4.Value, StdHeader);
+  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {
+    // Step3, Clear firmware interrupt flags
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_x1F380_ADDRESS,
+      AccessWidth32,
+      0x0,
+      0x0,
+      StdHeader
+      );
+  }
+  //Step 4, 11, Assert LM32 reset
+  GnbLibPciIndirectRMW (
+    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+    0x80000000 ,
+    AccessWidth32,
+    (UINT32) ~(0x1 ),
+    1 << 0 ,
+    StdHeader
+    );
+  // Step5, 12, Load firmware
+  for (Index = 0; Index < (Firmware->FirmwareLength + Firmware->HeaderLength); Index++) {
+    GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, SMC_RAM_START_ADDR + (Index * 4), AccessWidth32, &((UINT32 *) Firmware)[Index], StdHeader);
+  }
+  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {
+    //Step 6, Write jmp to RAM firmware
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      0x0,
+      AccessWidth32,
+      0x0,
+      0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderLength * 4) >> 2),
+      StdHeader
+      );
+  } else {
+    //Step 13, Clear autentification done
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_xE0003088_ADDRESS,
+      AccessWidth32,
+      0x0,
+      0x0,
+      StdHeader
+      );
+  }
+  // Step 7, 14 Enable LM32 clock
+  GnbLibPciIndirectRMW (
+    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+    0x80000004 ,
+    AccessWidth32,
+    (UINT32) ~(0x1 ),
+    0 << 0 ,
+    StdHeader
+    );
+
+  //Step 8, 15, Deassert LM32 reset
+  GnbLibPciIndirectRMW (
+    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+    0x80000000 ,
+    AccessWidth32,
+    (UINT32) ~(0x1 ),
+    0 << 0 ,
+    StdHeader
+    );
+
+  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 1) {
+    IDS_HDT_CONSOLE (NB_MISC, "  Protected mode: poll init autehtication vector\n");
+    // Step 16, Wait for rom firmware init autehtication vector
+    do {
+      GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, 0x80010000 , AccessWidth32, &ex1005.Value, StdHeader);
+    } while (ex1005.Value != 0x400);
+    // Call Authentication service
+    GnbSmuServiceRequestV4 (GnbPciAddress, SMC_MSG_FIRMWARE_AUTH, 0, StdHeader);
+    IDS_HDT_CONSOLE (NB_MISC, "  Protected mode: poll init autehtication done\n");
+    // Wait for autehtication done
+    do {
+      GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003088_ADDRESS, AccessWidth32, &D0F0xBC_xE0003088.Value, StdHeader);
+    } while (D0F0xBC_xE0003088.Field.SmuAuthDone == 0x0);
+    //Step 17, Check Authentication results
+    if (D0F0xBC_xE0003088.Field.SmuAuthPass == 0) {
+      IDS_HDT_CONSOLE (NB_MISC, "  ERROR!!!Autehtication fail!!!\n");
+      ASSERT (FALSE);
+      return AGESA_FATAL;
+    }
+    // Step 18, Clear firmware interrupt enable flag
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_x1F380_ADDRESS,
+      AccessWidth32,
+      0x0,
+      0x0,
+      StdHeader
+      );
+    //Step 19, Assert LM32 reset
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      0x80000000 ,
+      AccessWidth32,
+      (UINT32) ~(0x1 ),
+      1 << 0 ,
+      StdHeader
+      );
+    //Step 20, Deassert LM32 reset
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      0x80000000 ,
+      AccessWidth32,
+      (UINT32) ~(0x1 ),
+      0 << 0 ,
+      StdHeader
+      );
+  }
+//Step 9, 21 Wait firmware to initialize
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_x1F380_ADDRESS, AccessWidth32, &D0F0xBC_x1F380.Value, StdHeader);
+  } while (D0F0xBC_x1F380.Field.InterruptsEnabled == 0);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get IOMMU PCI address
+ *
+ *
+ * @param[in]  GnbHandle       GNB handle
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+PCI_ADDR
+GnbGetIommuPciAddressV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PCI_ADDR  GnbIommuPciAddress;
+  GnbIommuPciAddress = GnbGetHostPciAddress (GnbHandle);
+  GnbIommuPciAddress.Address.Function = 0x2;
+  return  GnbIommuPciAddress;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * UnitID Clumping
+ *
+ *
+ * @param[in]  GnbHandle       GNB handle
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+VOID
+GnbClumpUnitIdV4 (
+  IN      GNB_HANDLE                *GnbHandle,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT32              Value;
+
+  Value = 0;
+  EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_ENGINE, &GnbHandle->Header);
+  while (EngineList != NULL) {
+    if (EngineList->Type.Port.NumberOfUnitId != 0) {
+      if (!PcieConfigIsActivePcieEngine (EngineList)) {
+        Value |= (((1 << EngineList->Type.Port.NumberOfUnitId) - 1) << EngineList->Type.Port.UnitId);
+      } else {
+        if (EngineList->Type.Port.NumberOfUnitId > 1) {
+          Value |= (((1 << (EngineList->Type.Port.NumberOfUnitId - 1)) - 1) << (EngineList->Type.Port.UnitId + 1));
+        }
+      }
+    }
+    EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
+  }
+  // Set GNB
+  GnbLibPciIndirectRMW (
+    GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+    D0F0x98_x3A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessS3SaveWidth32,
+    (UINT32) ~Value,
+    Value,
+    StdHeader
+    );
+  //Set UNB
+  GnbLibPciRMW (
+    MAKE_SBDFO (0, 0, GnbHandle->NodeId + 0x18, 0, D18F0x110_ADDRESS + GnbHandle->LinkId * 4),
+    AccessS3SaveWidth32,
+    (UINT32) ~Value,
+    Value,
+    StdHeader
+    );
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Config GNB to prevent LPC deadlock scenario
+ *
+ *
+ * @param[in]  GnbHandle       GNB handle
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLpcDmaDeadlockPreventionV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  PCIe_ENGINE_CONFIG    *EngineList;
+
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &GnbHandle->Header);
+  EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &GnbHandle->Header);
+  while (EngineList != NULL) {
+    if (PcieConfigIsPcieEngine (EngineList) && PcieConfigIsSbPcieEngine (EngineList)) {
+      PcieRegisterRMW (
+        PcieConfigGetParentWrapper (EngineList),
+        CORE_SPACE (EngineList->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
+        D0F0xE4_CORE_0010_UmiNpMemWrite_MASK,
+        1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET,
+        TRUE,
+        Pcie
+        );
+      //Enable special NP memory write protocol in ORB
+      GnbLibPciIndirectRMW (
+        GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+        D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        0xFFFFFFFF,
+        1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET,
+        StdHeader
+        );
+      break;
+    }
+    EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable IOMMU base address. (MMIO space )
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        AGESA_SUCCESS
+ * @retval        AGESA_ERROR
+ */
+
+AGESA_STATUS
+GnbEnableIommuMmioV4 (
+  IN       GNB_HANDLE           *GnbHandle,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AGESA_STATUS            Status;
+  UINT16                  CapabilityOffset;
+  UINT64                  BaseAddress;
+  UINT32                  Value;
+  PCI_ADDR                GnbIommuPciAddress;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Enter\n");
+
+  if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) {
+    GnbIommuPciAddress = GnbGetIommuPciAddressV4 (GnbHandle, StdHeader);
+    CapabilityOffset = GnbLibFindPciCapability (GnbIommuPciAddress.AddressValue, IOMMU_CAP_ID, StdHeader);
+
+    GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessWidth32, &Value, StdHeader);
+    BaseAddress = (UINT64) Value << 32;
+    GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessWidth32, &Value, StdHeader);
+    BaseAddress |= Value;
+
+    if ((BaseAddress & 0xfffffffffffffffe) != 0x0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader);
+      GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader);
+    } else {
+      ASSERT (FALSE);
+      Status = AGESA_ERROR;
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n");
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h
new file mode 100644
index 0000000000..95d97df935
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h
@@ -0,0 +1,149 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBNBINITLIBV4_H_
+#define _GNBNBINITLIBV4_H_
+
+#pragma pack (push, 1)
+
+/// Firmware header
+typedef struct {
+  UINT32  Version;                  ///< Version
+  UINT32  HeaderLength;             ///< Header length
+  UINT32  FirmwareLength;           ///< Firmware length
+  UINT32  EntryPoint;               ///< Entry point
+  UINT32  MessageDigest[5];         ///< Message digest
+  UINT32  Reserved_A[3];            ///< Reserved
+  UINT32  CurrentSystemState;       ///< Current system state
+  UINT32  DpmCacHistory;            ///< DpmCac History
+  UINT32  DpmResidencyCounters;     ///< DPM recidency counters
+  UINT32  Reserved_B[16];           ///< Reserved
+  UINT32  Reserved_C[16];           ///< Reserved
+  UINT32  Reserved_D[16];           ///< Reserved
+  UINT32  HeaderEnd;                ///< Header end signature
+} FIRMWARE_HEADER_V4;
+
+/// SMU service request contect
+typedef struct {
+  PCI_ADDR          GnbPciAddress;   ///< PCIe address of GNB
+  UINT8             RequestId;       ///< Request/Msg ID
+} SMU_MSG_CONTEXT;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+GnbGetTopologyInfoV4 (
+  IN       PCI_ADDR                  StartPciAddress,
+  IN       PCI_ADDR                  EndPciAddress,
+     OUT   GNB_TOPOLOGY_INFO         *TopologyInfo,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+VOID
+GnbSmuServiceRequestV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       UINT8                    RequestId,
+  IN       UINT32                   AccessFlags,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbSmuFirmwareLoadV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       FIRMWARE_HEADER_V4       *Firmware,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+PCI_ADDR
+GnbGetIommuPciAddressV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+VOID
+GnbClumpUnitIdV4 (
+  IN      GNB_HANDLE                *GnbHandle,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+VOID
+GnbLpcDmaDeadlockPreventionV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbEnableIommuMmioV4 (
+  IN       GNB_HANDLE           *GnbHandle,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
new file mode 100644
index 0000000000..1b3742da7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -0,0 +1,578 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "cpuLateInit.h"
+#include  "cpuRegisters.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "OptionGnb.h"
+#include  "PcieAlib.h"
+#include  "GnbFuseTable.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern  F_ALIB_GET    *AlibGetBaseTable;
+extern  F_ALIB_UPDATE *AlibDispatchTable[];
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieAlibUpdatePcieMmioInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+PcieAlibUpdateVoltageInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+PcieAlibUpdatePcieInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+PcieAlibSetPortMaxSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+STATIC
+PcieAlibSetPortOverrideSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+STATIC
+PcieAlibSetPortInfoCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PcieAlibBuildAcpiTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+     OUT   VOID                 **AlibSsdtPtr
+  );
+
+VOID
+STATIC
+PcieAlibSetSclkVid (
+  IN OUT   VOID                  *Buffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create ACPI ALIB SSDT table
+ *
+ *
+ *
+ * @param[in] StdHeader           Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieAlibFeature (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AMD_LATE_PARAMS *LateParamsPtr;
+  LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader;
+  return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build ALIB ACPI table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @param[in,out] AlibSsdtPtr     Pointer to pointer to ALIB SSDT table
+ * @retval        AGESA_SUCCESS
+ * @retval        AGESA_ERROR
+ */
+
+AGESA_STATUS
+PcieAlibBuildAcpiTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+     OUT   VOID                 **AlibSsdtPtr
+  )
+{
+  AGESA_STATUS            Status;
+  AGESA_STATUS            AgesaStatus;
+  UINTN                   Index;
+  VOID                    *AlibSsdtBuffer;
+  VOID                    *AlibSsdtTable;
+  UINTN                   AlibSsdtlength;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  AlibSsdtTable = AlibGetBaseTable (StdHeader);
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength;
+  if (*AlibSsdtPtr == NULL) {
+    AlibSsdtBuffer = GnbAllocateHeapBuffer (
+                       AMD_ACPI_ALIB_BUFFER_HANDLE,
+                       AlibSsdtlength,
+                       StdHeader
+                       );
+    ASSERT (AlibSsdtBuffer != NULL);
+    if (AlibSsdtBuffer == NULL) {
+      return  AGESA_ERROR;
+    }
+    *AlibSsdtPtr = AlibSsdtBuffer;
+  } else {
+    AlibSsdtBuffer = *AlibSsdtPtr;
+  }
+  // Copy template to buffer
+  LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader);
+  // Disaptch fucntion form table
+  Index = 0;
+  while (AlibDispatchTable[Index] != NULL) {
+    Status = AlibDispatchTable[Index] (AlibSsdtBuffer, StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Index++;
+  }
+  if (AgesaStatus != AGESA_SUCCESS) {
+    //Shrink table length to size of the header
+    ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
+  }
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update MMIO info
+ *
+ *
+ *
+ *
+ * @param[in] AlibSsdtBuffer      Ponter to SSDT table
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+AGESA_STATUS
+PcieAlibUpdatePcieMmioInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32        AmlObjName;
+  UINT32        AlibSsdtlength;
+  VOID          *AmlObjPtr;
+  AGESA_STATUS  Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Enter\n");
+  Status = AGESA_SUCCESS;
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength;
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '1');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    UINT64  LocalMsrRegister;
+    LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader);
+    if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000) == 0) {
+      *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000);
+    } else {
+      Status = AGESA_FATAL;
+    }
+  } else {
+    Status = AGESA_FATAL;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Exit\n");
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update MMIO info
+ *
+ *
+ *
+ *
+ * @param[in] AlibSsdtBuffer      Ponter to SSDT table
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+AGESA_STATUS
+PcieAlibUpdateVoltageInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32          AmlObjName;
+  UINT32          AlibSsdtlength;
+  VOID            *AmlObjPtr;
+  UINT8           BootUpVidIndex;
+  UINT8           Gen1VidIndex;
+  PP_FUSE_ARRAY   *PpFuseArray;
+  AGESA_STATUS    Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Enter\n");
+  Status = AGESA_SUCCESS;
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength;
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '3');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid;
+    } else {
+      Status = AGESA_FATAL;
+    }
+  } else {
+    Status = AGESA_FATAL;
+  }
+
+  Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader);
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '4');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex;
+  } else {
+    Status = AGESA_FATAL;
+  }
+
+  BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader);
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '5');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex;
+  } else {
+    Status = AGESA_FATAL;
+  }
+
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '1', '0');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader);
+  } else {
+    Status = AGESA_FATAL;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update PCIe info
+ *
+ *
+ *
+ *
+ * @param[in] AlibSsdtBuffer      Ponter to SSDT table
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+AGESA_STATUS
+PcieAlibUpdatePcieInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  UINT32                AmlObjName;
+  UINT32                AlibSsdtlength;
+  VOID                  *AmlObjPtr;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Enter\n");
+  Status = AGESA_SUCCESS;
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength;
+  if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '2');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy;
+    } else {
+      Status = AGESA_FATAL;
+    }
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '6');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      PcieConfigRunProcForAllEngines (
+        DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+        PcieAlibSetPortMaxSpeedCallback,
+        (UINT8*)((UINT8*) AmlObjPtr + 7),
+        Pcie
+        );
+    } else {
+      Status = AGESA_FATAL;
+    }
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '8');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      PcieConfigRunProcForAllEngines (
+        DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+        PcieAlibSetPortOverrideSpeedCallback,
+        (UINT8*)((UINT8*) AmlObjPtr + 7),
+        Pcie
+        );
+    } else {
+      Status = AGESA_FATAL;
+    }
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '7');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      PcieConfigRunProcForAllEngines (
+        DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+        PcieAlibSetPortInfoCallback,
+        (UINT8*)((UINT8*) AmlObjPtr + 4),
+        Pcie
+        );
+    } else {
+      Status = AGESA_FATAL;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init max port speed capability
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortMaxSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   *PsppMaxPortSpeedPackage;
+  PsppMaxPortSpeedPackage = (UINT8*) Buffer;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init max port speed capability
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortOverrideSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   *PsppOverridePortSpeedPackage;
+  PsppOverridePortSpeedPackage = (UINT8*) Buffer;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode;
+  }
+  if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init port info
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortInfoCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ALIB_PORT_INFO_PACKAGE  *PortInfoPackage;
+  UINT8                   PortIndex;
+  PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer;
+  PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2;
+  PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane;
+  PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane;
+  PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane;
+  PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane;
+  PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId;
+  PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieConfigGetParentWrapper (Engine)->WrapId);
+  PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
+  PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine);
+  PortInfoPackage->PortInfo[PortIndex].ClkPmSupport = Engine->Type.Port.PortData.MiscControls.ClkPmSupport;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init port info
+ *
+ *
+ *
+ *
+ * @param[in, out]  Buffer          Asl buffer
+ * @param[in]       StdHeader       Standard configuration header
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetSclkVid (
+  IN OUT   VOID                  *Buffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8             *SclkVid;
+  PP_FUSE_ARRAY     *PpFuseArray;
+  UINT8             Index;
+
+  SclkVid = (UINT8*) Buffer;
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray == NULL) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  ERROR!!! Heap Location\n");
+    return;
+  }
+
+  for (Index = 0; Index < 4; Index++) {
+    SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index];
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h
new file mode 100644
index 0000000000..63a06e1ab2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIB_H_
+#define _PCIEALIB_H_
+
+#pragma pack (push, 1)
+///Port info asl buffer
+typedef struct {
+  UINT8                   BufferOp;           ///< Opcode
+  UINT8                   PkgLength;          ///< Package length
+  UINT8                   BufferSize;         ///< Buffer size
+  UINT8                   ByteList;           ///< Byte lisy
+  UINT8                   StartPhyLane;       ///< Port Start PHY lane
+  UINT8                   EndPhyLane;         ///< Port End PHY lane
+  UINT8                   StartCoreLane;      ///< Port Start Core lane
+  UINT8                   EndCoreLane;        ///< Port End Core lane
+  UINT8                   PortId;             ///< Port ID
+  UINT16                  WrapperId;          ///< Wrapper ID
+  UINT8                   LinkHotplug;        ///< Link hotplug type
+  UINT8                   MaxSpeedCap;        ///< Max port speed capability
+  UINT8                   ClkPmSupport;       ///< ClkPmSupport
+} ALIB_PORT_INFO_BUFFER;
+///Ports info asl package
+typedef struct {
+  UINT8                   PackageOp;          ///< Opcode
+  UINT8                   PkgLength;          ///< Package length
+  UINT8                   NumElements;        ///< number of elements
+  UINT8                   PackageElementList; ///< package element list
+  ALIB_PORT_INFO_BUFFER   PortInfo[7];        ///< Array of port info buffers
+} ALIB_PORT_INFO_PACKAGE;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+PcieAlibFeature (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
new file mode 100644
index 0000000000..5c53c6b870
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * ALIB PSPP config
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBCONFIG_H_
+#define _PCIEALIBCONFIG_H_
+
+//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT
+// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK
+
+#define DEF_OFFSET_START_CORE_LANE              2
+#define DEF_OFFSET_END_CORE_LANE                3
+#define DEF_OFFSET_START_PHY_LANE               0
+#define DEF_OFFSET_END_PHY_LANE                 1
+#define DEF_OFFSET_PORT_ID                      4
+#define DEF_OFFSET_WRAPPER_ID                   5
+#define DEF_OFFSET_LINK_HOTPLUG                 7
+#define DEF_OFFSET_GEN2_CAP                     8
+#define DEF_OFFSET_CLK_PM_SUPPORT               9
+
+#define DEF_BASIC_HOTPLUG                       1
+
+#define DEF_PSPP_POLICY_START                   1
+#define DEF_PSPP_POLICY_STOP                    0
+#define DEF_PSPP_POLICY_PERFORMANCE             1
+#define DEF_PSPP_POLICY_BALANCEHIGH             2
+#define DEF_PSPP_POLICY_BALANCELOW              3
+#define DEF_PSPP_POLICY_POWERSAVING             4
+#define DEF_PSPP_STATE_AC                       0
+#define DEF_PSPP_STATE_DC                       1
+
+#define DEF_TRAINING_STATE_COMPLETE             0
+#define DEF_TRAINING_STATE_DETECT_PRESENCE      1
+#define DEF_TRAINING_STATE_PRESENCE_DETECTED    2
+#define DEF_TRAINING_GEN2_WORKAROUND            3
+#define DEF_TRAINING_STATE_NOT_PRESENT          4
+#define DEF_TRAINING_DEVICE_PRESENT             5
+#define DEF_TRAINING_STATE_RELEASE_TRAINING     6
+#define DEF_TRAINING_STATE_REQUEST_RESET        7
+#define DEF_TRAINING_STATE_EXIT                 8
+
+#define DEF_LINK_SPEED_GEN1                     1
+#define DEF_LINK_SPEED_GEN2                     2
+
+#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT   0
+#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT       1
+
+#define DEF_PORT_NOT_ALLOCATED                  0
+#define DEF_PORT_ALLOCATED                      1
+
+#define DEF_PCIE_LANE_POWERON                   1
+#define DEF_PCIE_LANE_POWEROFF                  0
+#define DEF_PCIE_LANE_POWEROFFUNUSED            2
+
+#define DEF_SCARTCH_PSPP_START_OFFSET           0
+#define DEF_SCARTCH_PSPP_POLICY_OFFSET          1
+#define DEF_SCARTCH_PSPP_ACDC_OFFSET            5
+#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET        6
+#define DEF_SCARTCH_PSPP_REQ_OFFSET             16
+
+#define DEF_LINKWIDTH_ACTIVE                    0
+#define DEF_LINKWIDTH_MAX_PHY                   1
+
+#define DEF_SB_PORT_INDEX                       6
+
+#define TRUE                                    1
+#define FALSE                                   0
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
new file mode 100644
index 0000000000..bc1f70db88
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
@@ -0,0 +1,111 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Master control method
+   *
+   *  Arg0 - Function ID
+   *  Arg1 - Function specific data buffer
+   */
+  Method (ALIB, 2, NotSerialized) {
+    If (Lequal (Arg0, 0x1)) {
+      return (procPsppReportAcDsState (Arg1))
+    }
+    If (LEqual (Arg0, 0x2)) {
+      return (procPsppPerformanceRequest (Arg1))
+    }
+    If (LEqual (Arg0, 0x3)) {
+      return (procPsppControl (Arg1))
+    }
+    If (LEqual (Arg0, 0x4)) {
+      return (procPcieSetBusWidth (Arg1))
+    }
+    If (LEqual (Arg0, 0x5)) {
+      return (procAlibInit ())
+    }
+    If (LEqual (Arg0, 0x6)) {
+      return (procPciePortHotplug (Arg1))
+    }
+    return (0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Alib Init
+   *
+   *
+   */
+  Method (procAlibInit, 0, Serialized) {
+
+    return (0)
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
new file mode 100644
index 0000000000..e8820cf502
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+  Name (varStringBuffer, Buffer (256) {})
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
new file mode 100644
index 0000000000..951193a57b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
@@ -0,0 +1,787 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+   External(\_SB.ALIC,  MethodObj)
+   External(P80H)
+
+  Name (varStartPhyLane, 0)
+  Name (varEndPhyLane, 0)
+  Name (varStartCoreLane, 0)
+  Name (varEndCoreLane, 0)
+  Name (varWrapperId, 0)
+  Name (varPortId, 0)
+  Name (varMaxPhyLinkWidth, 0)
+
+  Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16})
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Set PCIe Bus Width
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPcieSetBusWidth, 1, NotSerialized) {
+    Store ("procPcieSetBusWidth Enter", Debug)
+
+    Name (varClientBus, 0)
+    Name (varArgBusWidth, 0)
+    Store (0, varPortIndex)
+    Store (Buffer (10) {}, Local7)
+
+    //ClientId: WORD
+    //Bits  2-0: Function number.
+    //Bits  7-3: Device number.
+    //Bits 15-8: Bus number.
+    Store (DerefOf (Index (Arg0, 0x3)), varClientBus)
+    Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth)
+    Store (Concatenate ("  Client Bus   : ", ToHexString (varClientBus), varStringBuffer), Debug)
+    Store (Concatenate ("  Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug)
+
+    Store (3, Index (Local7, 0x0)) // Return Buffer Length
+    Store (0, Index (Local7, 0x1)) // Return Buffer Length
+    Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth
+    // disable interface
+    return (Local7)
+
+    //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes
+
+    // determine port index base on "Client ID"
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) {
+        Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
+        And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2)             //Local2 Port Subordinate Bus number
+        And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1)                //Local1 Port Secondary Bus number
+        if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) {
+          break
+        }
+      }
+      Increment (varPortIndex)
+    }
+    if (LGreater (varPortIndex, varMaxPortIndexNumber)) {
+      Store ("procPcieSetBusWidth Exit -- over max port index", Debug)
+      return (Local7)
+    }
+
+    Store (Concatenate ("  Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug)
+
+    // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16,
+    // make sure that number of lanes requested to be powered on less or equal mx port link width
+    if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) {
+      // Active link equal max link width, nothing needs to be done
+      Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug)
+      return (Local7)
+    }
+    Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1)
+
+
+    // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0)
+    procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0)
+
+    // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width)
+    procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1)
+
+#ifdef PHY_SPEED_REPORT_SUPPORT
+    procReportPhySpeedCap ()
+#endif
+    Store (Local1, Index (Local7, 0x2)) // Return BusWidth
+
+    Store ("procPcieSetBusWidth Exit", Debug)
+    return (Local7)
+  }
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe port hotplug
+   *
+   *  Arg0   - Data Buffer
+   *  Retval - Return buffer
+   */
+  Method (procPciePortHotplug, 1, Serialized) {
+    Store ("PciePortHotplug Enter", Debug)
+    Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0)
+    Store (DerefOf (Index (Arg0, 2)), varPortBdfLocal1)
+
+    Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal4)
+    if (LEqual(varHotplugStateLocal0, 1)) {
+      // Enable port
+      Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2)
+    } else {
+      // Disable port
+      Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2)
+    }
+
+    //Disable ASPM
+    Store (procPciDwordRead (varPortBdfLocal1, 0x68), Local3)
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00)
+
+    Store (procPciePortTraining (varPortIndexLocal4, Local2), varHotplugStateLocal0)
+
+    //Restore ASPM
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (Local3, 0x3))
+
+#ifdef PHY_SPEED_REPORT_SUPPORT
+    procReportPhySpeedCap ()
+#endif
+
+    Store (Buffer (10) {}, Local7)
+    CreateWordField (Local7, 0x0, varReturnBufferLength)
+    CreateByteField (Local7, 0x2, varReturnStatus)
+    CreateByteField (Local7, 0x3, varReturnDeviceStatus)
+    Store (0x4, varReturnBufferLength)
+    Store (0x0, varReturnStatus)
+    Store (varHotplugStateLocal0, varReturnDeviceStatus)
+    Store ("PciePortHotplug Exit", Debug)
+    return (Local7)
+  }
+
+  Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0})
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Train PCIe port
+   *
+   *
+   *  Arg0  - Port Index
+   *  Arg1  - Initial state
+   */
+  Method (procPciePortTraining, 2, Serialized) {
+    Store ("PciePortTraining Enter", Debug)
+    Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+    // Check if port supports basic hotplug
+    Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1)
+    if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) {
+      Store ("  No action.[Hotplug type]", Debug)
+      Store ("procPciePortTraining Exit", Debug)
+      return (varResultLocal4)
+    }
+    Store (Arg1, varStateLocal2)
+    while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) {
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) {
+        Store (" State: Release training", Debug)
+        // Remove link speed override
+        Store (0, Index (varOverrideLinkSpeed, Arg0))
+        // Enable link width upconfigure
+        procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000)
+        if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+          // Request Max link speed for hotplug by going to AC state
+          Store (0, varPsppAcDcOverride)
+          procApplyPsppState ()
+        } else {
+          procPcieSetLinkSpeed (Arg0, DeRefOf (Index (varMaxLinkSpeed, Arg0)))
+        }
+        // Power on/enable port lanes
+        procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0)
+        // Release training
+        procPcieTrainingControl (Arg0, 0)
+        // Move to next state to check presence detection
+        Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2)
+        // Initialize retry count
+        Store(0, varCountLocal3)
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) {
+        Store (" State: Detect presence", Debug)
+        And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1)
+        if (LGreater (varTempLocal1, 0x4)) {
+          // device connection detected move to next state
+          Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2)
+          // reset retry counter
+          Store(0, varCountLocal3)
+          continue
+        }
+        if (LLess (varCountLocal3, 80)) {
+          Sleep (1)
+          Increment (varCountLocal3)
+        } else {
+          // detection time expired move to device not present state
+          Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+        }
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) {
+        Store (" State: Device detected", Debug)
+        Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1)
+        And (varTempLocal1, 0x3f, varTempLocal1)
+        if (LAnd (LGreaterEqual (varTempLocal1, 0x10), LLessEqual (varTempLocal1, 0x13))) {
+          Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2)
+          continue
+        }
+        if (LLess (varCountLocal3, 80)) {
+          Sleep (1)
+          Increment (varCountLocal3)
+          continue
+        }
+        Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+        if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) {
+          // GEN2 workaround already applied but device not trained successfully move device not present state
+          continue
+        }
+
+        if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) {
+          Store (" Request Gen2 workaround", Debug)
+          procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000)
+          Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0))
+          procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1)
+          Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2)
+        }
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) {
+        Store (" State: Device not present", Debug)
+        procPcieTrainingControl (Arg0, 1)
+        procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0)
+#ifdef  PCIE_MAX_PAYLOAD_SUPPORT
+        procPcieClearMaxPayload (Arg0)
+#endif
+
+        // Find device on secondary bus
+        Store (ShiftLeft (Add( Arg0, 2), 3), varTempBdfLocal0)
+        Store (procPciDwordRead (varTempBdfLocal0, 0x18), varTempLocal1)
+        And (ShiftRight (varTempLocal1, 8), 0xFF,  varTempLocal1)
+        Store (Concatenate ("  Remove device from Bus   : ", ToHexString (varTempLocal1), varStringBuffer), Debug)
+        ShiftLeft (varTempLocal1, 8, varTempBdfLocal0)
+        Store (procPciDwordRead (varTempBdfLocal0, 0x0), varTempLocal0)
+        if (LEqual (varTempLocal0, 0xFFFFFFFF)) {
+          Store ("  Device has been un-pluged!! ", Debug)
+        }
+        // Exclude device from PSPP managment since it is not present
+        Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0))
+        Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2)
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) {
+        Store (" State: Request Reset", Debug)
+        if (CondRefOf (\_SB.ALIC, Local6)) {
+          Store (" Call ALIC method", Debug)
+          //varTempLocal1  contain port BDF
+          Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1)
+          \_SB.ALIC (varTempLocal1, 0)
+          Sleep (2)
+          \_SB.ALIC (varTempLocal1, 1)
+          Store (0, varCountLocal3)
+          Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2)
+          continue
+        }
+        Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) {
+        Store (" State: Device present", Debug)
+        Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4)
+        Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2)
+#ifdef  PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK
+        procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0)
+#endif
+#ifdef  PCIE_MAX_PAYLOAD_SUPPORT
+        procPcieSetMaxPayload (Arg0)
+#endif
+#ifdef  PCIE_CLKPM_SUPPORT
+        procPcieClkPmConfigure (Arg0)
+#endif
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) {
+        if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+          Store (1, varPsppAcDcOverride)
+          procApplyPsppState ()
+        }
+        Store (DEF_TRAINING_STATE_EXIT, varStateLocal2)
+      }
+    }
+    Store ("PciePortTraining Exit", Debug)
+    return (varResultLocal4)
+  }
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Lane control
+   *
+   *  Arg0   - Port Index
+   *  Arg1   - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes
+   *  Arg2   - link width
+   */
+
+  Method (procPcieLaneControl, 3, Serialized) {
+    Store ("PcieLaneControl Enter", Debug)
+    Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+    Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+#endif
+    Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane)
+
+    Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varMaxPhyLinkWidth)
+
+    if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) {
+      procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 1)
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+      procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1)
+#endif
+    }
+    if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) {
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+      procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0)
+#endif
+      procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 0)
+    }
+    if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) {
+      return (0)
+    }
+
+    //  Local2 should have link width (active lanes)
+    //  Local3 should have first non active lanes
+    //  Local4 should have last non active lanes
+
+    if (LEqual(Arg2, 0)) {
+      Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2)
+    } else {
+      Store ( Arg2 , varActiveLinkWidthLocal2)
+    }
+    // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case
+    // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14
+
+    if (LLessEqual (varMaxPhyLinkWidth, varActiveLinkWidthLocal2)) {
+      // Active link equal max link width, nothing needs to be done
+      return (0)
+    }
+
+    Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1)
+    //There is unused lanes after device plugged
+    if (LEqual(varIsReversedLocal1, FALSE)) {
+      Store (" Port Not Reversed", Debug)
+      // Link not reversed
+      Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3)
+      Store (varEndCoreLane, Local4)
+    } else {
+      // Link reversed
+      Store (" Port Reversed", Debug)
+      Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4)
+      Store (varStartCoreLane, Local3)
+    }
+    procPcieLaneEnableControl (Arg0, Local3, Local4, 1)
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+    if (LGreater (varStartPhyLane, varEndPhyLane)) {
+      Store (varEndPhyLane, Local3)
+      Store (varStartPhyLane, Local4)
+    } else {
+      Store (varEndPhyLane, Local4)
+      Store (varStartPhyLane, Local3)
+    }
+    if (LEqual(varIsReversedLocal1, FALSE)) {
+      // Not reversed
+      Add (Local3, varActiveLinkWidthLocal2, Local3)
+    } else {
+      // Link reversed
+      Subtract (Local4, varActiveLinkWidthLocal2, Local4)
+    }
+    procPcieLanePowerControl (Local3, Local4, 1)
+#endif
+    return (0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Check if GEN2 workaround applicable
+   *
+   *  Arg0   - Port Index
+   *  Retval - TRUE / FALSE
+   */
+
+  Method (procPcieCheckForGen2Workaround, 1, NotSerialized) {
+    Store (Buffer (16) {}, Local1)
+    Store (0x0, Local0)
+    while (LLessEqual (Local0, 0x3)) {
+      Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2)
+      Store (Local2,  Index (Local1, Multiply (Local0, 4)))
+      Store (ShiftRight (Local2, 8),   Index (Local1, Add (Multiply (Local0, 4), 1)))
+      Store (ShiftRight (Local2, 16),  Index (Local1, Add (Multiply (Local0, 4), 2)))
+      Store (ShiftRight (Local2, 24),  Index (Local1, Add (Multiply (Local0, 4), 3)))
+      Increment (Local0)
+    }
+    Store (0, Local0)
+    while (LLess (Local0, 15)) {
+      if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a),  LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) {
+        return (TRUE)
+      }
+      Increment (Local0)
+    }
+    return (FALSE)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Is port reversed
+   *
+   *  Arg0   - Port Index
+   *  Retval - 0 - Not reversed / !=0 - Reversed
+   */
+  Method (procPcieIsPortReversed , 1, Serialized) {
+    Store (procPcieGetPortInfo (Arg0), Local7)
+
+    Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+    Store (0, Local0)
+    if (LGreater (varStartPhyLane, varEndPhyLane)) {
+      Store (1, Local0)
+    }
+    And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1)
+    return (And (Xor (Local0, Local1), 0x1))
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Training Control
+   *
+   *  Arg0  - Port Index
+   *  Arg1  - Hold Training (1) / Release Training (0)
+   */
+  Method (procPcieTrainingControl , 2, NotSerialized) {
+    Store ("PcieTrainingControl Enter", Debug)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId)
+    Store (
+      Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))),
+      varWrapperId
+    )
+    procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1);
+    Store ("PcieTrainingControl Exit", Debug)
+  }
+
+
+Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Get actual negotiated/PHY or core link width
+   *
+   *  Arg0   - Port Index
+   *  Arg1   - 0/1 Negotiated/Phy
+   *  Retval - Link Width
+   */
+  Method (procPcieGetLinkWidth, 2, NotSerialized) {
+    Store ("PcieGetLinkWidth Enter", Debug)
+    Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+
+    if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){
+       //Get negotiated length
+      And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0)
+      Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1)
+      Store (Concatenate ("  Active Link Width :", ToHexString (Local1), varStringBuffer), Debug)
+    } else {
+       //Get phy length
+      Store (procPcieGetPortInfo (Arg0), Local7)
+      Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+      Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+      if (LGreater (varStartPhyLane, varEndPhyLane)) {
+        Subtract (varStartPhyLane, varEndPhyLane, Local1)
+      } else {
+        Subtract (varEndPhyLane, varStartPhyLane, Local1)
+      }
+      Increment (Local1)
+      Store (Concatenate ("  PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug)
+    }
+    Store ("PcieGetLinkWidth Exit", Debug)
+    return (Local1)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe lane mux lane enable control (hotplug support)
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Start Lane
+   *  Arg2 - End Lane
+   *  Arg3 - Enable(0) / Disable(1)
+   */
+  Method (procPcieLaneEnableControl, 4, Serialized) {
+    Store ("PcieLaneEnableControl Enter", Debug)
+    Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+    Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug)
+    Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+    Store (Arg1, varStartCoreLane)
+    Store (Arg2, varEndCoreLane)
+    Store (
+      Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))),
+      varWrapperId
+    )
+    if (LGreater (varStartCoreLane, varEndCoreLane)) {
+      Subtract (varStartCoreLane, varEndCoreLane, Local1)
+      Store (varEndCoreLane, Local2)
+    } else {
+      Subtract (varEndCoreLane, varStartCoreLane, Local1)
+      Store (varStartCoreLane, Local2)
+    }
+    ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3)
+    Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4)
+    Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug)
+    if (Lequal (Arg3, 1)) {
+      Store (0, varLaneBitmapOrMaskLocal3)
+    }
+    procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3);
+    Stall (10)
+    Store ("PcieLaneEnableControl Exit", Debug)
+  }
+
+#ifdef  PCIE_MAX_PAYLOAD_SUPPORT
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Max_Payload_Size Blacklist
+   *
+   *  Entry 1 = Vendor & Device ID
+   *  Entry 2 = Max_Payload_Size for this device
+   */
+  Name (varPayloadBlacklist, Package () {
+    Package() {0x10831969, 0}
+  })
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Set Max_Payload_Size
+   *
+   *  Arg0 - Port Index
+   */
+   Method (procPcieSetMaxPayload, 1, Serialized) {
+
+   // Local variable usage
+   // varTempLocal0 - Temporary storage
+   // varBdfLocal1 - Address of port config space
+   // varCapLocal2 - Offset of port PCIe Capabilities
+   // varMaxPayloadLocal3 - Largest common value of Max_Payload_Size capability
+   // varMaxFunctionLocal4 - Max function number
+   // varFunctionLocal5 - Current function number
+   // varDeviceIDLocal6 - Root port BDF and Vendor and device ID for blacklist workaround
+   // varIndexLocal7 - Package index for blacklist workaround
+
+    Store ("PcieSetMaxPayload Enter", Debug)
+
+    // Get Port BDF from Port Index
+    Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6)
+    Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2)
+    if (LNotEqual (varCapLocal2, 0)) {
+
+      // Find device on secondary bus
+      Store (procPciDwordRead (varDeviceIDLocal6, 0x18), varTempLocal0)
+      And (ShiftRight (varTempLocal0, 8), 0xFF,  varTempLocal0)
+
+      Store (Concatenate ("  EP on SecondaryBus : ", ToHexString (varTempLocal0), varStringBuffer), Debug)
+
+      ShiftLeft (varTempLocal0, 8, varBdfLocal1)
+
+      Store (procPciDwordRead (varBdfLocal1, 0xC), varTempLocal0)
+      Store (And (ShiftRight (varTempLocal0, 16), 0xFF),  varTempLocal0)
+      if (LNotEqual (And (varTempLocal0, 0x80), 0)) {
+        Store (0x7, varMaxFunctionLocal4)
+      } else {
+        Store (0x0, varMaxFunctionLocal4)
+      }
+      // Start with illegal value so we will know if a device is foudn
+      Store (0x08, varMaxPayloadLocal3)
+      // Search all functions and find smallest Max_Payload_Size
+      Store (0x0, varFunctionLocal5)
+      while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) {
+        Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2)
+        if (LNotEqual (varCapLocal2, 0)) {
+          And (procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), Add (varCapLocal2, 0x04)), 0x07, varTempLocal0)
+          // Scan blacklist package for workaround
+          Store(procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), 0), varDeviceIDLocal6)
+          Store (0, varIndexLocal7)
+          while (LLess (varIndexLocal7, SizeOf (varPayloadBlacklist))) {
+            if (LEqual (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 0)), varDeviceIDLocal6)) {
+              Store (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 1)), varTempLocal0)
+            }
+            Increment (varIndexLocal7)
+          }
+          if (LLess (varTempLocal0, varMaxPayloadLocal3)) {
+            Store (varTempLocal0, varMaxPayloadLocal3)
+          }
+        }
+        Increment(varFunctionLocal5)
+      }
+
+      // We will only set Max_Payload_Size if PCIe capabilties were found on the downstream side
+      if (LNotEqual (varMaxPayloadLocal3, 0x08)) {
+        // Read root port Max_Payload_Size and compare with device supported value
+        Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6)
+        Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2)
+        And (procPciDwordRead (varDeviceIDLocal6, Add (varCapLocal2, 0x04)), 0x07, varTempLocal0)
+        if (LLess (varTempLocal0, varMaxPayloadLocal3)) {
+          Store (varTempLocal0, varMaxPayloadLocal3)
+        }
+        // Search all functions and set smallest Max_Payload_Size to all functions
+        // Relocate Max_Payload_Size data to bits 7-5
+        Store (Concatenate ("  Setting Max_Payload_Size : ", ToHexString (varMaxPayloadLocal3), varStringBuffer), Debug)
+        ShiftLeft (varMaxPayloadLocal3, 5, varMaxPayloadLocal3)
+        // Set the root port Max_Payload_Size
+        procPciDwordRMW (varDeviceIDLocal6, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3)
+        //Set the Max_Payload_Size in each function that has PCIe Capabilities
+        Store (0x0, varFunctionLocal5)
+        while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) {
+          Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2)
+          if (LNotEqual (varCapLocal2, 0)) {
+            procPciDwordRMW (varBdfLocal1, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3)
+          }
+          Increment(varFunctionLocal5)
+        }
+      }
+    }
+    Store ("PcieSetMaxPayload Exit", Debug)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Clear Max_Payload_Size
+   *
+   *  Arg0 - Port Index
+   */
+   Method (procPcieClearMaxPayload, 1, Serialized) {
+
+   // Local variable usage
+   // varPortBdfLocal0 - Address of root port config space
+   // varPortCapLocal1 - Offset of root port PCIe Capabilities
+
+    Store ("PcieClearMaxPayload Enter", Debug)
+
+    // Get Port BDF from Port Index
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal0)
+    Store (procFindPciCapability (varPortBdfLocal0, 0x10), varPortCapLocal1)
+    if (LNotEqual (varPortCapLocal1, 0)) {
+      // Set the root port Max_Payload_Size to default = 0x0
+      procPciDwordRMW (varPortBdfLocal0, Add (varPortCapLocal1, 0x08), Not (0x000000E0), 0x0)
+
+    }
+    Store ("PcieClearMaxPayload Exit", Debug)
+  }
+#endif
+
+#ifdef  PCIE_CLKPM_SUPPORT
+    Method  (procPcieClkPmConfigure, 1, Serialized) {
+      Store ("PcieClkPmConfigure Enter", Debug)
+      Store (procPcieGetPortInfo (Arg0), Local7)
+      Store (DerefOf (Index (Local7, DEF_OFFSET_CLK_PM_SUPPORT)), varTempLocal0)
+      if (LEqual (varTempLocal0, 0)) {
+        Store ("PcieClkPmConfigure Exit", Debug)
+        return (0)
+      }
+      // Get Port PCI address
+      Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+      Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal0)
+      // Get device BDf on secondary bus
+      And (varTempLocal0, 0xFF00,  varEndpointBdfLocal2)
+
+      Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal0)
+      Store (And (ShiftRight (varTempLocal0, 16), 0xFF),  varTempLocal0)
+      if (LNotEqual (And (varTempLocal0, 0x80), 0)) {
+        Store (0x7, varMaxFunctionLocal3)
+      } else {
+        Store (0x0, varMaxFunctionLocal3)
+      }
+      Store (0, varFunctionLocal4)
+      Store (0, varIsClkPmSupportedLocal5)
+      while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) {
+        //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+        Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6)
+        if (LEqual (varPcieCapabilityOffsetLocal6, 0)) {
+          Increment (varFunctionLocal4)
+          continue
+        }
+        // Found PCI capability
+        if (LNotEqual (And (procPciDwordRead (Or (varEndpointBdfLocal2, varFunctionLocal4), Add (varPcieCapabilityOffsetLocal6, 0xC)), ShiftLeft (1,18)), 0)) {
+          Store (1, varIsClkPmSupportedLocal5)
+        } else {
+          Store (0, varIsClkPmSupportedLocal5)
+          break
+        }
+        Increment (varFunctionLocal4)
+      }
+      if (LEqual (varIsClkPmSupportedLocal5, 0)) {
+        Store ("PcieClkPmConfigure Exit", Debug)
+        return (0)
+      }
+      Store (0, varFunctionLocal4)
+
+      while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) {
+        //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+        Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6)
+        if (LEqual (varPcieCapabilityOffsetLocal6, 0)) {
+          Increment (varFunctionLocal4)
+          continue
+        }
+        // Enable CLK PM Capability
+        procPciDwordRMW (Or (varEndpointBdfLocal2, varFunctionLocal4),  Add (varPcieCapabilityOffsetLocal6, 0x10), 0xffffffff, ShiftLeft (1, 8))
+        Increment (varFunctionLocal4)
+      }
+      Store ("PcieClkPmConfigure Exit", Debug)
+    }
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
new file mode 100644
index 0000000000..abe0cdd459
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe MMIO Base address
+   *
+   */
+
+  Name (
+    AD01,
+    0xE0000000
+  )
+
+  Alias (
+    AD01,
+    varPcieBase
+  )
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
new file mode 100644
index 0000000000..378c0392ef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
@@ -0,0 +1,289 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCI config register through MMIO
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Register offset
+   */
+  Method (procPciDwordRead, 2, Serialized) {
+    Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
+    Add (Arg1, Local0, Local0)
+    OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
+      Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
+      Offset (0x0),
+      varPciReg32, 32,
+      }
+    return (varPciReg32)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCI config register through MMIO
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Register offset
+   *  Arg2 - Value
+   */
+  Method (procPciDwordWrite, 3, Serialized) {
+    Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
+    Add (Arg1, Local0, Local0)
+    OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
+      Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
+      Offset (0x0),
+      varPciReg32, 32,
+      }
+    Store (Arg2, varPciReg32)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCI config register through MMIO
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Register offset
+   *  Arg2 - AND mask
+   *  Arg3 - OR mask
+   */
+  Method (procPciDwordRMW, 4, Serialized) {
+    Store (procPciDwordRead (Arg0, Arg1), Local0)
+    Or (And (Local0, Arg2), Arg3, Local0)
+    procPciDwordWrite (Arg0, Arg1, Local0)
+  }
+
+  Mutex(varPciePortAccessMutex, 0)
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Register offset
+   *
+   */
+  Method (procPciePortIndirectRegisterRead, 2, NotSerialized) {
+    Acquire(varPciePortAccessMutex, 0xFFFF)
+    Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+    procPciDwordWrite (Local0, 0xe0, Arg1)
+    Store (procPciDwordRead (Local0, 0xe4), Local0)
+    Release (varPciePortAccessMutex)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCIe port indirect register
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Register offset
+   *  Arg2 - Value
+   */
+  Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) {
+    Acquire(varPciePortAccessMutex, 0xFFFF)
+    Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+    procPciDwordWrite (Local0, 0xe0, Arg1)
+    procPciDwordWrite (Local0, 0xe4, Arg2)
+    Release (varPciePortAccessMutex)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Register offset
+   *  Arg2 - AND Mask
+   *  Arg3 - OR Mask
+   *
+   */
+  Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) {
+    Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0)
+    Or (And (Local0, Arg2), Arg3, Local0)
+    procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0)
+  }
+  Mutex(varHostAccessMutex, 0)
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - BDF
+   *  Arg1 - Register offset
+   *  Arg2 - Register address
+   *
+   */
+  Method (procIndirectRegisterRead, 3, NotSerialized) {
+    Acquire(varHostAccessMutex, 0xFFFF)
+    procPciDwordWrite (Arg0, Arg1, Arg2)
+    Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0)
+    Release(varHostAccessMutex)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCIe port indirect register
+   *
+   *  Arg0 - BDF
+   *  Arg1 - Register offset
+   *  Arg2 - Register address
+   *  Arg3 - Value
+   */
+  Method (procIndirectRegisterWrite, 4, NotSerialized) {
+    Acquire(varHostAccessMutex, 0xFFFF)
+    procPciDwordWrite (Arg0, Arg1, Arg2)
+    procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3)
+    Release(varHostAccessMutex)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read Modify Write indirect registers
+   *
+   *  Arg0 - BDF
+   *  Arg1 - Register Offset
+   *  Arg2 - Register Address
+   *  Arg3 - AND Mask
+   *  Arg4 - OR Mask
+   *
+   */
+  Method (procIndirectRegisterRMW, 5, NotSerialized) {
+    Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0)
+    Or (And (Local0, Arg3), Arg4, Local0)
+    procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Find Pci Capability
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Capability id
+   */
+  Method (procFindPciCapability, 2, NotSerialized) {
+    Store (0x34, Local1)
+    if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) {
+      // Device not present
+      return  (0)
+    }
+    Store (1, Local0)
+    while (LEqual (Local0, 1)) {
+      Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1)
+      if (LEqual (Local1, 0)) {
+        break
+      }
+      if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) {
+        Store (0, Local0)
+      } else {
+        Increment (Local1)
+      }
+    }
+    return (Local1)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *
+   *
+   *  Arg0  - Aspm
+   *  Arg1  - 0: Read, 1: Write
+   */
+  Method (procPcieSbAspmControl, 2, Serialized) {
+      // Create an opregion for PM IO Registers
+      OperationRegion (PMIO, SystemIO, 0xCD6, 0x2)
+      Field (PMIO, ByteAcc, NoLock, Preserve)
+      {
+        PMRI, 8,
+        PMRD, 8
+      }
+      IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve)
+      {
+        Offset(0xE0),               // IO Base address of A-Link Express/ A-Link Bridge register
+        ABAR, 32,
+      }
+    OperationRegion (ACFG, SystemIO, ABAR, 0x8)
+      Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA
+      {
+        ABIX, 32,
+        ABDA, 32
+      }
+
+    Store (0, Local0)
+    if (LEqual (Arg1, 0)) {
+      Store (0x80000068, ABIX)
+      Store (ABDA, Local0)
+      return (Local0)
+    } else {
+      Store (0x80000068, ABIX)
+      Store (ABDA, Local0)
+      Or (And (Local0, 0xfffffffc), Arg0, Local0)
+      Store (Local0, ABDA)
+    }
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
new file mode 100644
index 0000000000..228c839b3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
@@ -0,0 +1,109 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe port info
+   *
+   */
+
+  Name (
+    AD07,
+    Package () {
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev2
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev3
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev4
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev5
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev6
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev7
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev8
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev9
+    }
+  )
+
+  Alias (
+    AD07,
+    varPortInfo
+  )
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *
+   *
+   *  Arg0 	- Port ID
+   *  Retval	- buffer that represent port data set
+   */
+  Method (procPcieGetPortInfo, 1, NotSerialized) {
+    return (DeRefOf (Index (varPortInfo, Arg0)))
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
new file mode 100644
index 0000000000..bedd41cddd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
@@ -0,0 +1,825 @@
+/**
+* @file
+*
+* ALIB PSPP ASL library
+*
+*
+*
+* @xrefitem bom "File Content Label" "Release Content"
+* @e project:     AGESA
+* @e sub-project: GNB
+* @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+*
+*/
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe Performance Policy
+   *
+   *  varPsppPolicy - 0 Disabled
+   *                  1 Performance
+   *                  2 Balance Hight
+   *                  3 Balance Low
+   *                  4 Power Saving
+   */
+  Name (
+    AD02,
+    0x0
+  )
+
+  Alias (
+    AD02,
+    varPsppPolicy
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  GEN2 VID
+   *
+   */
+
+  Name (
+    AD03,
+    0x0
+  )
+
+  Alias (
+    AD03,
+    varGen2Vid
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  GEN1 VID
+   *
+   */
+  Name (
+    AD04,
+    0x0
+  )
+
+  Alias (
+    AD04,
+    varGen1Vid
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Boot VID
+   *
+   */
+
+  Name (
+    AD05,
+    0x0
+  )
+
+  Alias (
+    AD05,
+    varBootVid
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Max Port link speed
+   *
+   */
+  Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  Alias (AD06, varMaxLinkSpeed)
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Max link speed that was changed during runtime (hotplug for instance)
+   *
+   */
+
+  Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  Alias (AD08,  varOverrideLinkSpeed)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Policy service status
+   *
+   *  varPsppPolicyService - 0 (Stopped)
+   *                         1 (Started)
+   */
+
+  Name (varPsppPolicyService, 0x0 )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  AC DC state
+   *
+   *  varPsppAcDcState - 0 (AC)
+   *                     1 (DC)
+   */
+
+  Name (varPsppAcDcState, 0x0)
+  Name (varPsppAcDcOverride, 0x1)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Client ID array
+   *
+   */
+
+  Name (varPsppClientIdArray,
+    Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+    )
+
+  Name (varDefaultPsppClientIdArray,
+    Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+    )
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  LInk speed requested by device driver
+   *
+   */
+
+  Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Current link speed
+   *
+   */
+  Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+  Alias (AD09,  varCurrentLinkSpeed)
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Template link speed
+   *
+   */
+  Name (
+    varGen1LinkSpeedTemplate,
+    Package () {
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1
+    })
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Template link speed
+   *
+   */
+  Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 })
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Global varuable
+   *
+   */
+  Name (varPortIndex, 0)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Sclk VID that was changed during runtime
+   *
+   */
+
+  Name (AD10, Package () {0x00, 0x00, 0x00, 0x00})
+
+  Alias (AD10,  varSclkVid)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Report AC/DC state
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppReportAcDsState, 1, Serialized) {
+    Store ("PsppReportAcDsState Enter", Debug)
+
+    Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1)
+    Store (Concatenate ("  AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug)
+
+    Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0)
+    Store (varArgAcDcStateLocal1, varPsppAcDcState)
+
+    Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2)
+    Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3)
+    procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3))
+
+
+    if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) {
+      Store ("  No action. [AC/DC state not changed]", Debug)
+      Store ("PsppReportAcDsState Exit", Debug)
+      return (0)
+    }
+
+    // Disable both APM (boost) and PDM flow on DC event enable it on AC.
+    procApmPdmActivate(varPsppAcDcState)
+
+    // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service.
+    if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN1)
+#endif
+    }
+    if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+      Store ("  No action. [Policy type]", Debug)
+      Store ("PsppReportAcDsState Exit", Debug)
+      return (0)
+    }
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+      Store ("  No action. [Policy not started]", Debug)
+      Store ("PsppReportAcDsState Exit", Debug)
+      return (0)
+    }
+    procApplyPsppState ()
+    Store ("PsppReportAcDsState Exit", Debug)
+    return (0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe Performance Request
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppPerformanceRequest, 1, NotSerialized) {
+    Store (procPsppProcessPerformanceRequest (Arg0), Local7)
+    Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0)
+    if (LNotEqual (varReturnStatusLocal0, 2)) {
+      return (Local7)
+    }
+    procApplyPsppState ()
+    return (Local7)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe Performance Request
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppProcessPerformanceRequest, 1, NotSerialized) {
+    Store ("PsppProcessPerformanceRequest Enter", Debug)
+    Name (varClientBus, 0)
+    Store (0, varPortIndex)
+    Store (Buffer (10) {}, Local7)
+    CreateWordField (Local7, 0x0, varReturnBufferLength)
+    Store (3, varReturnBufferLength)
+    CreateByteField (Local7, 0x2, varReturnStatus)
+    Store (1, varReturnStatus)
+
+    if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+      Store ("  No action. [Policy type]", Debug)
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+      Store ("  No action. [Policy not started]", Debug)
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+    CreateWordField (Arg0, 0x2, varClientId)
+    CreateWordField (Arg0, 0x4, varValidFlag)
+    CreateWordField (Arg0, 0x6, varFlag)
+    CreateByteField (Arg0, 0x8, varRequestType)
+    CreateByteField (Arg0, 0x9, varRequestData)
+
+    Store (Concatenate ("  Client ID   : ", ToHexString (varClientId), varStringBuffer), Debug)
+    Store (Concatenate ("  Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug)
+    Store (Concatenate ("  Flags       : ", ToHexString (varFlag), varStringBuffer), Debug)
+    Store (Concatenate ("  Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug)
+    Store (Concatenate ("  Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug)
+
+
+    And (ShiftRight (varClientId, 8), 0xff, varClientBus)
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) {
+        Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
+        And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2)             //Local2 Port Subordinate Bus number
+        And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1)                //Local1 Port Secondary Bus number
+        if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) {
+          break
+        }
+      }
+      Increment (varPortIndex)
+    }
+    if (LGreater (varPortIndex, varMaxPortIndexNumber)) {
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+
+    Store (Concatenate ("  Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug)
+
+    if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) {
+      Store (varClientId, Index (varPsppClientIdArray, varPortIndex))
+    } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) {
+      // We already have registered client
+      Store ("  No action. [Unsupported request]", Debug)
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+    Store (0, Index (varLowVoltageRequest, varPortIndex))
+    if (LEqual (varRequestData, 0)) {
+      Store (0x0000, Index (varPsppClientIdArray, varPortIndex))
+    }
+    if (LEqual (varRequestData, 1)) {
+      Store (1, Index (varLowVoltageRequest, varPortIndex))
+    }
+    if (LEqual (varRequestData, 2)) {
+      Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex))
+    }
+    if (LEqual (varRequestData, 3)) {
+      Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex))
+    }
+    if (LEqual (And (varValidFlag, varFlag), 0x1)) {
+      Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex))
+    }
+    Store (2, varReturnStatus)
+    Store ("PsppProcessPerformanceRequest Exit", Debug)
+    return (Local7)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PSPP Start/Stop Management Request
+   *
+   *  Arg0 - Data Buffer
+   */
+
+  Method (procChecPortAllocated, 1, Serialized) {
+    if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) {
+      return (DEF_PORT_NOT_ALLOCATED)
+    }
+    return (DEF_PORT_ALLOCATED)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PSPP Start/Stop Management Request
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppControl, 1, Serialized) {
+    Store ("PsppControl Enter", Debug)
+    Store (Buffer (256) {}, Local7)
+    Store (3, Index (Local7, 0x0)) // Return Buffer Length
+    Store (0, Index (Local7, 0x1)) // Return Buffer Length
+    Store (0, Index (Local7, 0x2)) // Return Status
+
+    Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService)
+
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0)
+
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) {
+      if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) {
+      // Policy already started
+        Store (" No action. [Policy already started]", Debug)
+        Store ("PsppControl Exit", Debug)
+        return (Local7)
+      }
+      Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0)
+    }
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+      if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) {
+        // Policy already stopped
+        Store ("  No action. [Policy already stopped]", Debug)
+        Store ("PsppControl Exit", Debug)
+        return (Local7)
+      }
+      And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0)
+    }
+    Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0)
+    procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0)
+
+    procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray))
+
+    // Reevaluate APM/PDM state here on S3 resume while staying on DC.
+    procApmPdmActivate(varPsppAcDcState)
+
+    // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service.
+    if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN1)
+#endif
+    }
+    //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage
+    if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+      // Load default speed capability state
+      if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) {
+        procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed))
+        Store (0, varPortIndex)
+        while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+          if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) {
+            Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex))
+          }
+          Increment (varPortIndex)
+        }
+      } else {
+        procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed))
+#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT
+       Store (DeRefOf (Index (varMaxLinkSpeed, DEF_SB_PORT_INDEX)),Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX))
+       //Store (DEF_LINK_SPEED_GEN2, Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX))
+#endif
+
+      }
+      procApplyPsppState ()
+    }
+    Store ("PsppControl Exit", Debug)
+    return (Local7)
+  }
+
+  Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Evaluate PCIe speed on all links according to PSPP state and client requests
+   *
+   *
+   *
+   */
+  Method (procApplyPsppState, 0, Serialized) {
+    Store ("ApplyPsppState Enter", Debug)
+    Store (0, varPortIndex)
+
+    procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed))
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) {
+        Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex))
+      }
+      Increment (varPortIndex)
+    }
+    if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) {
+      procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed))
+    }
+    if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) {
+      // Set GEN2 voltage
+      Store ("Set GEN2 VID", Debug)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN2)
+#endif
+      procPcieSetVoltage (DEF_LINK_SPEED_GEN2, 1)
+//      procPcieAdjustPll (DEF_LINK_SPEED_GEN2)
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2)
+    }
+    Store (0, varPortIndex)
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) {
+        Increment (varPortIndex)
+        continue
+      }
+      Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0)
+      Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2)
+      if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) {
+        Increment (varPortIndex)
+        continue
+      }
+      Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex))
+      procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2)
+      Increment (varPortIndex)
+    }
+    if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) {
+      // Set GEN1 voltage
+      Store ("Set GEN1 VID", Debug)
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1)
+//      procPcieAdjustPll (DEF_LINK_SPEED_GEN1)
+      procPcieSetVoltage (DEF_LINK_SPEED_GEN1, 0)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN1)
+#endif
+    }
+#ifdef PHY_SPEED_REPORT_SUPPORT
+    procReportPhySpeedCap ()
+#endif
+    Store ("ApplyPsppState Exit", Debug)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCI config register
+   *
+   *  Arg0 - Port Index
+   *
+   */
+  Method (procGetPortRequestedCapability, 1) {
+    Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0)
+    Store (procPsppGetAcDcState(), varAcDcStateLocal1)
+    if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
+      if (LOr (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
+        // Default policy cap to GEN1
+        Store (DEF_LINK_SPEED_GEN1, varCurrentSpeedLocal0)
+      }
+#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT
+      if (LAnd (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
+        if (LEqual (Arg0, DEF_SB_PORT_INDEX)) {
+          Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0)
+        }
+      }
+#endif
+      if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) {
+        Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), varCurrentSpeedLocal0)
+      }
+    } else {
+      Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), varCurrentSpeedLocal0)
+    }
+    Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)),varMaxLinkSpeedLocal2)
+    if (LLess (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0)) {
+      Store (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0)
+    }
+
+
+    return (varCurrentSpeedLocal0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Set capability and speed
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Link speed
+   */
+  Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) {
+    Store ("SetPortCapabilityAndSpeed Enter", Debug)
+    Store (Concatenate ("  Port Index : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate ("  Speed      : ", ToHexString (Arg1), varStringBuffer), Debug)
+
+    //UnHide UMI port
+    if (LEqual (Arg0, 6)) {
+      procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40);
+    }
+
+    procPcieSetLinkSpeed (Arg0, Arg1)
+
+    // Programming for LcInitSpdChgWithCsrEn
+    if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
+      // Registered port, LcInitSpdChgWithCsrEn = 0.
+      procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0)
+    } else {
+      procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000)
+    }
+
+    // Determine port PCI address and check port present
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+    And (procPciePortIndirectRegisterRead (Arg0, 0xA5), 0x3f, varPortPresentLocal3)
+    procPciePortIndirectRegisterWrite (Arg0, 0x1, varPortPresentLocal3)
+    if (LGreaterEqual (varPortPresentLocal3, 0x10)) {
+      procDisableAndSaveAspm (Arg0)
+      Store (1, Local2)
+      while (Local2) {
+        //retrain port
+        procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20)
+        Sleep (30)
+        while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) {
+          Sleep (10)
+        }
+        Store (0, Local2)
+        if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) {
+          //Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentLinkSpeedLocal4)
+          if (LNotEqual (procPciePortGetCurrentLinkSpeed (Arg0), DEF_LINK_SPEED_GEN1)) {
+            Store (1, Local2)
+          }
+        }
+      }
+      procRestoreAspm (Arg0)
+    } else {
+      Store ("  Device not present. Set capability and speed only", Debug)
+    }
+    //Hide UMI port
+    if (LEqual (Arg0, 6)) {
+      procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00);
+    }
+    Store ("SetPortCapabilityAndSpeed Exit", Debug)
+  }
+
+  Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
+  Name (varPcieLinkControlOffset, 0)
+  Name (varPcieLinkControlData, 0)
+  Name (varPcieRcControlData, 0)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Disable and save ASPM state
+   *
+   *  Arg0 - Port Index
+   */
+  Method (procDisableAndSaveAspm, 1, Serialized) {
+    Store (0, varPcieLinkControlOffset)
+    Store (0, varPcieLinkControlData)
+
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+    if (LEqual (Arg0, 6)) {
+      Store ("  Disable SB ASPM", Debug)
+      Store (procPcieSbAspmControl (0, 0),  Index (varPcieLinkControlArray, 0))
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug)
+      procPcieSbAspmControl (0, 1)
+      return (0)
+    }
+
+    Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 8), 0xFF),  varTempLocal3)
+
+    Store (Concatenate ("  Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2)
+    Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 16), 0xFF),  varTempLocal3)
+
+    Store (Concatenate ("  EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    if (LNotEqual (And (varTempLocal3, 0x80), 0)) {
+      Store (0x7, varMaxFunctionLocal0)
+    } else {
+      Store (0x0, varMaxFunctionLocal0)
+    }
+    Store (0, varFunctionLocal4)
+    while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) {
+      //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+      Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset)
+      if (LEqual (varPcieLinkControlOffset, 0)) {
+        Increment (varFunctionLocal4)
+        continue
+      }
+      Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
+
+      Store (Concatenate ("  Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug)
+      Store (Concatenate ("  PcieLinkControl register offset  : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug)
+      // Save ASPM on EP
+      Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData)
+      Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4))
+
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug)
+
+      procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00)
+      Store ("Disable ASPM on EP Complete!!", Debug)
+      Increment (varFunctionLocal4)
+    }
+    //Disable ASPM on RC
+    Store (procPciDwordRead (varPortBdfLocal1, 0x68), varPcieRcControlData)
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Restore ASPM
+   *
+   *  Arg0 - Port Index
+   */
+   Method (procRestoreAspm, 1, Serialized) {
+
+    Store (0, varPcieLinkControlOffset)
+    Store (0, varPcieLinkControlData)
+
+
+    // Restore SB ASPM
+    if (LEqual (Arg0, 6)) {
+      Store ("  Restore SB ASPM", Debug)
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug)
+      procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1)
+      return (0)
+    }
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+    // Restore EP ASPM
+    Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 8), 0xFF),  varTempLocal3)
+    // Restore ASPM on RC
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (varPcieRcControlData, 0x3))
+
+    Store (Concatenate ("  Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2)
+    Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 16), 0xFF),  varTempLocal3)
+
+    Store (Concatenate ("  EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    if (LNotEqual (And (varTempLocal3, 0x80), 0)) {
+      Store (0x7, varMaxFunctionLocal0)
+    } else {
+      Store (0x0, varMaxFunctionLocal0)
+    }
+    Store (0, varFunctionLocal4)
+    while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) {
+      //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+      Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset)
+      if (LEqual (varPcieLinkControlOffset, 0)) {
+        Increment (varFunctionLocal4)
+        continue
+      }
+      Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
+
+      Store (Concatenate ("  Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug)
+      Store (Concatenate ("  Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug)
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug)
+
+      procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4)))
+      Increment (varFunctionLocal4)
+    }
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Request VID
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - PCIe speed
+   */
+
+  Method (procPcieSetLinkSpeed, 2) {
+    Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+    if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) {
+      procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21)
+      procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0)
+    } else {
+      procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001)
+      procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2)
+    }
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Ref Source Pckage
+   *  Arg1 - Ref to Destination Package
+   *
+   */
+  Method (procCopyPackage, 2, NotSerialized) {
+
+    Store (SizeOf (Arg0), Local1)
+    Store (0, Local0)
+    While (LLess (Local0, Local1)) {
+      Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0))
+      Increment (Local0)
+    }
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Ref Source Pckage
+   *  Arg1 - Ref to Destination Package
+   *
+   */
+  Method (procPsppGetAcDcState, 0 , NotSerialized) {
+    Return (And (varPsppAcDcState, varPsppAcDcOverride))
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
new file mode 100644
index 0000000000..a88b5d9e7a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
@@ -0,0 +1,445 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe link ASPM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "OptionGnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "PcieAspmBlackList.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS GnbBuildOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  PCIE_ASPM_TYPE          Aspm;
+  PCI_ADDR                DownstreamPort;
+} PCIE_ASPM_DATA;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieAspmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+
+SCAN_STATUS
+PcieAspmCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+VOID
+PcieAspmEnableOnLink (
+  IN       PCI_ADDR                 Downstream,
+  IN       PCI_ADDR                 Upstream,
+  IN       PCIE_ASPM_TYPE           Aspm,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+PCIE_ASPM_TYPE
+PcieAspmGetPmCapability (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable PCIE Advance state power management
+ *
+ *
+ *
+ * @param[in] DownstreamPort      PCI Address of the downstream port
+ * @param[in] Aspm                ASPM type
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+VOID
+PcieLinkAspmEnable (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       PCIE_ASPM_TYPE          Aspm,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_ASPM_DATA PcieAspmData;
+  PcieAspmData.Aspm = Aspm;
+  PcieAspmData.ScanData.StdHeader = StdHeader;
+  PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieAspmCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_ASPM_DATA          *PcieAspmData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieAspmCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  PcieAspmData = (PCIE_ASPM_DATA *) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    PcieAspmData->DownstreamPort = Device;
+    //PcieExitLatencyData->LinkCount++;
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
+    //PcieExitLatencyData->LinkCount--;
+    break;
+  case  PcieDeviceUpstreamPort:
+    PcieAspmEnableOnLink (
+      PcieAspmData->DownstreamPort,
+      Device,
+      PcieAspmData->Aspm,
+      ScanData->StdHeader
+      );
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    PcieAspmEnableOnLink (
+      PcieAspmData->DownstreamPort,
+      Device,
+      PcieAspmData->Aspm,
+      ScanData->StdHeader
+      );
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  default:
+    break;
+  }
+  return ScanStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set  ASMP State on PCIe device function
+ *
+ *
+ *
+ * @param[in] Function    PCI address of function.
+ * @param[in] Aspm                Aspm capability to enable
+ * @param[in] StdHeader           Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmEnableOnFunction (
+  IN       PCI_ADDR             Function,
+  IN       PCIE_ASPM_TYPE       Aspm,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8       PcieCapPtr;
+  PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
+      AccessS3SaveWidth8,
+      (UINT32)~(BIT0 | BIT1),
+      Aspm,
+      StdHeader
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set ASMP State on all function of PCI device
+ *
+ *
+ *
+ * @param[in] Device    PCI address of device.
+ * @param[in] Aspm                Aspm capability to enable
+ * @param[in] StdHeader           Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC VOID
+PcieAspmEnableOnDevice (
+  IN       PCI_ADDR             Device,
+  IN       PCIE_ASPM_TYPE       Aspm,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8 MaxFunc;
+  UINT8 CurrentFunc;
+  MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
+  for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+    Device.Address.Function = CurrentFunc;
+    if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
+      PcieAspmEnableOnFunction (Device, Aspm, StdHeader);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Enable ASPM on link
+ *
+ *
+ *
+ * @param[in] Downstream          PCI Address of downstrteam port
+ * @param[in] Upstream            PCI Address of upstream port
+ * @param[in] Aspm                Aspm capability to enable
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+VOID
+PcieAspmEnableOnLink (
+  IN       PCI_ADDR                 Downstream,
+  IN       PCI_ADDR                 Upstream,
+  IN       PCIE_ASPM_TYPE           Aspm,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PCIe_LINK_ASPM  LinkAsmp;
+  PCIE_ASPM_TYPE  DownstreamCap;
+  PCIE_ASPM_TYPE  UpstreamCap;
+  LinkAsmp.DownstreamPort = Downstream;
+  DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader);
+  LinkAsmp.UpstreamPort = Upstream;
+  UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader);
+  LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1;
+  LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm;
+  LinkAsmp.RequestedAspm = Aspm;
+  if ((UpstreamCap & Aspm & AspmL0s) != 0) {
+    LinkAsmp.UpstreamAspm |= AspmL0s;
+  }
+  if ((DownstreamCap & Aspm & AspmL0s) != 0) {
+    LinkAsmp.DownstreamAspm |= AspmL0s;
+  }
+  if (GnbBuildOptions.PcieAspmBlackListEnable == 1) {
+    PcieAspmBlackListFeature (&LinkAsmp, StdHeader);
+  }
+  //AgesaPcieLinkAspm (&LinkAsmp, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  Set ASPM [%d]  for Device = %d:%d:%d\n",
+    (LinkAsmp.UpstreamAspm) ,
+    LinkAsmp.UpstreamPort.Address.Bus,
+    LinkAsmp.UpstreamPort.Address.Device,
+    LinkAsmp.UpstreamPort.Address.Function
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "  Set ASPM [%d]  for Device = %d:%d:%d\n",
+    (LinkAsmp.DownstreamAspm) ,
+    LinkAsmp.DownstreamPort.Address.Bus,
+    LinkAsmp.DownstreamPort.Address.Device,
+    LinkAsmp.DownstreamPort.Address.Function
+    );
+  // Disable ASPM  Upstream component
+  PcieAspmEnableOnDevice (Upstream, AspmDisabled, StdHeader);
+  // Enable  ASPM  Donstream component
+  PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader);
+  // Enable  ASPM  Upstream component
+  PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader);
+}
+
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Port/Endpoint ASMP capability
+ *
+ *
+ *
+ * @param[in] Device      PCI address of downstream port
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    PCIE_ASPM_TYPE
+ */
+ /*----------------------------------------------------------------------------------------*/
+PCIE_ASPM_TYPE
+PcieAspmGetPmCapability (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  UINT8   PcieCapPtr;
+  UINT32  Value;
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr == 0) {
+    return 0;
+  }
+  GnbLibPciRead (
+    Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
+    AccessWidth32,
+    &Value,
+    StdHeader
+    );
+  return (Value >> 10) & 3;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAspmPortInitCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled &&
+      !PcieConfigIsSbPcieEngine (Engine) &&
+      PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PcieLinkAspmEnable (
+      Engine->Type.Port.Address,
+      Engine->Type.Port.PortData.LinkAspm,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Interface to enable Clock Power Managment
+ *
+ *
+ *
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    AGESA_STATUS
+ */
+ /*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieAspmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Enter\n");
+  AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieAspmPortInitCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h
new file mode 100644
index 0000000000..16bf03ec4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe link ASPM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPM_H_
+#define _PCIEASPM_H_
+
+VOID
+PcieLinkAspmEnable (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       PCIE_ASPM_TYPE          Aspm,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+VOID
+PcieAspmEnableOnFunction (
+  IN       PCI_ADDR                Function,
+  IN       PCIE_ASPM_TYPE          Aspm,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
new file mode 100644
index 0000000000..d268915b5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
@@ -0,0 +1,353 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Clock Power Managment
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "PcieClkPm.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable Clock Power Managment on function of the device
+ *
+ *
+ *
+ * @param[in] Function     PCI address of function.
+ * @param[in] StdHeader    Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC VOID
+PcieClkPmEnableOnFunction (
+  IN       PCI_ADDR             Function,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8       PcieCapPtr;
+  PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
+      AccessS3SaveWidth32,
+      (UINT32)~(BIT8),
+      BIT8,
+      StdHeader
+      );
+  }
+}
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * check capability of intire device including its functions
+ *
+ *
+ *
+ * @param[in] Device      PCI address of downstream port
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    TRUE - Device support Clock Power Managment
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC BOOLEAN
+PcieClkPmCheckDeviceCapability (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  UINT8   MaxFunc;
+  UINT8   CurrentFunc;
+  UINT8   PcieCapPtr;
+  UINT32  Value;
+
+  MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
+
+  for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+    Device.Address.Function = CurrentFunc;
+    if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
+      PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+      if (PcieCapPtr == 0) {
+        return FALSE;
+      }
+      GnbLibPciRead (
+        Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
+        AccessWidth32,
+        &Value,
+        StdHeader
+        );
+      if ((Value & BIT18) == 0) {
+        return FALSE;
+      }
+    }
+  }
+  return TRUE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Clock power managment on device
+ *
+ *
+ *
+ * @param[in] Device        PCI address of device.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC VOID
+PcieClkPmEnableOnDevice (
+  IN       PCI_ADDR             Device,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8 MaxFunc;
+  UINT8 CurrentFunc;
+  if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) {
+    MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
+    for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+      Device.Address.Function = CurrentFunc;
+      if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
+       IDS_HDT_CONSOLE (GNB_TRACE, "  Enable Clock Power Managment for Device = %d:%d:%d\n",
+        Device.Address.Bus,
+        Device.Address.Device,
+        Device.Address.Function
+        );
+        PcieClkPmEnableOnFunction (Device, StdHeader);
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+STATIC SCAN_STATUS
+PcieClkPmCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_DEVICE_TYPE        DeviceType;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieClkPmCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, ScanData);
+    break;
+  case  PcieDeviceUpstreamPort:
+    PcieClkPmEnableOnDevice (Device, ScanData->StdHeader);
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, ScanData);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    PcieClkPmEnableOnDevice (Device, ScanData->StdHeader);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  default:
+    break;
+  }
+  return ScanStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Confiugure Clock Power Managment
+ *
+ *
+ *
+ *
+ * @param[in]       DownstreamPort       Downstream port PCI address
+ * @param[in]       StdHeader            Standard configuration header
+ *
+ */
+
+VOID
+STATIC
+PcieClkPmPortInitConfigure (
+  IN       PCI_ADDR               DownstreamPort,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GNB_PCI_SCAN_DATA  ScanData;
+  ScanData.StdHeader = StdHeader;
+  ScanData.GnbScanCallback = PcieClkPmCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &ScanData);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieClkPmPortInitCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.MiscControls.ClkPmSupport == 0x1 &&
+      !PcieConfigIsSbPcieEngine (Engine) &&
+      PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PcieClkPmPortInitConfigure (
+      Engine->Type.Port.Address,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Interface to enable Clock Power Managment
+ *
+ *
+ *
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    AGESA_STATUS
+ */
+ /*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieClkPmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Enter\n");
+  AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieClkPmPortInitCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h
new file mode 100644
index 0000000000..3d14ac8abc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe link ASPM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIECLKPM_H_
+#define _PCIECLKPM_H_
+
+AGESA_STATUS
+PcieClkPmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
new file mode 100644
index 0000000000..4b354caba4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
@@ -0,0 +1,162 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate/manes GNB/PCIe configuration
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get GNB handle
+ *
+ *
+ * @param[in]       StdHeader       Standard configuration header
+ */
+GNB_HANDLE *
+GnbGetHandle (
+  IN      AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  GNB_HANDLE            *GnbHandle;
+  AGESA_STATUS          Status;
+  GnbHandle = NULL;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    GnbHandle = (GNB_HANDLE *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  }
+  return GnbHandle;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get GNB socket ID
+ *
+ *
+ * @param[in]       GnbHandle       Gnb handle
+ */
+UINT8
+GnbGetSocketId (
+  IN      GNB_HANDLE                        *GnbHandle
+  )
+{
+  return PcieConfigGetParentComplex (GnbHandle)->SocketId;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Get PCI_ADDR of GNB
+ *
+ *
+ * @param[in] Handle          Pointer to GNB_HANDLE
+ * @retval    PCI_ADDR        PCI_ADDR of device
+ */
+
+PCI_ADDR
+GnbGetHostPciAddress (
+  IN      GNB_HANDLE          *Handle
+  )
+{
+  ASSERT (Handle != NULL);
+  return Handle->Address;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
new file mode 100644
index 0000000000..affaa8c0ab
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBHANDLELIB_H_
+#define _GNBHANDLELIB_H_
+
+
+GNB_HANDLE *
+GnbGetHandle (
+  IN      AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+UINT8
+GnbGetSocketId (
+  IN      GNB_HANDLE                        *GnbHandle
+  );
+
+PCI_ADDR
+GnbGetHostPciAddress (
+  IN      GNB_HANDLE          *Handle
+ );
+
+
+#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY)
+
+#define GnbGetSiliconId(Handle) (Handle != NULL ? (Handle)->SiliconId : 0)
+#define GnbGetNodeId(Handle) (Handle != NULL ? (Handle)->NodeId : 0)
+
+#define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE)
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h
new file mode 100644
index 0000000000..9074aba624
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe configuration
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBPCIECONFIG_H_
+#define _GNBPCIECONFIG_H_
+
+#include "GnbPcie.h"
+#include "PcieConfigData.h"
+#include "PcieConfigLib.h"
+#include "GnbHandleLib.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
new file mode 100644
index 0000000000..febae7f986
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -0,0 +1,561 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "OptionGnb.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbFamServices.h"
+#include  "cpuServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "PcieMapTopology.h"
+#include  "PcieInputParser.h"
+#include  "PcieConfigLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PcieConfigAttachChild(P, C)  (P)->Child = (UINT16) ((UINT8 *) C - (UINT8 *) P);
+#define PcieConfigAttachParent(P, C) (C)->Parent = (UINT16) ((UINT8 *) C - (UINT8 *) P);
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+PcieConfigAttachComplexes (
+  IN  OUT   PCIe_COMPLEX_CONFIG             *Base,
+  IN  OUT   PCIe_COMPLEX_CONFIG             *New
+  );
+
+AGESA_STATUS
+PcieUpdateConfigurationData (
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+PCIe_COMPLEX_DESCRIPTOR *
+PcieConfigProcessUserConfig (
+  IN       PCIe_COMPLEX_DESCRIPTOR         *PcieComplexList,
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PcieConfigurationInit (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PcieConfigurationMap (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create internal PCIe configuration topology
+ *
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     AGESA_SUCCESS   Configuration data successfully allocated.
+ * @retval     AGESA_FATAL     Configuration data allocation failed.
+ */
+
+AGESA_STATUS
+PcieConfigurationInit (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  PCIe_SILICON_CONFIG   *Silicon;
+  UINT8                 SocketId;
+  UINTN                 CurrentComplexesDataLength;
+  UINTN                 ComplexesDataLength;
+  UINT8                 ComplexIndex;
+  VOID                  *Buffer;
+  ComplexesDataLength = 0;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n");
+  for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
+    if (IsProcessorPresent (SocketId, StdHeader)) {
+      Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
+      ASSERT (Status == AGESA_SUCCESS);
+      ComplexesDataLength += CurrentComplexesDataLength;
+    }
+  }
+  ComplexIndex = 0;
+  Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
+  ASSERT (Pcie != NULL);
+  if (Pcie != NULL) {
+    PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
+    PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY);
+    Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
+    for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
+      if (IsProcessorPresent (SocketId, StdHeader)) {
+        Pcie->ComplexList[ComplexIndex].SocketId = SocketId;
+        //Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration
+        PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header);
+        //Attach Comples to Pcie
+        PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
+        PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY);
+        PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
+        Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]);
+        while (Silicon != NULL) {
+          PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header);
+          GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader);
+          GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader);
+          Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY);
+        }
+
+        if (ComplexIndex > 0) {
+          PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]);
+        }
+        PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
+        Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength);
+        ComplexIndex++;
+      }
+    }
+  } else {
+    Status = AGESA_FATAL;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create internal PCIe configuration topology
+ *
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     AGESA_SUCCESS   Configuration data successfully allocated.
+ * @retval     AGESA_FATAL     Configuration data allocation failed.
+ */
+
+AGESA_STATUS
+PcieConfigurationMap (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_EARLY_PARAMS            *EarlyParamsPtr;
+  PCIe_COMPLEX_DESCRIPTOR     *PcieComplexList;
+  PCIe_PLATFORM_CONFIG        *Pcie;
+  PCIe_COMPLEX_CONFIG         *Complex;
+  PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor;
+  AGESA_STATUS                Status;
+  AGESA_STATUS                AgesaStatus;
+  UINTN                       Index;
+  UINTN                       NumberOfComplexes;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationMap Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader;
+  PcieComplexList = PcieConfigProcessUserConfig (EarlyParamsPtr->GnbConfig.PcieComplexList, StdHeader);
+  GNB_DEBUG_CODE (
+    if (PcieComplexList != NULL) {
+      PcieUserConfigConfigDump (PcieComplexList);
+    }
+  );
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
+    NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList);
+    while (Complex != NULL) {
+      for (Index = 0; Index < NumberOfComplexes; Index++) {
+        ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index);
+        if (ComplexDescriptor->SocketId == Complex->SocketId) {
+          Status = PcieMapTopologyOnComplex (ComplexDescriptor, Complex, Pcie);
+          AGESA_STATUS_UPDATE (Status, AgesaStatus);
+        }
+      }
+      Complex = PcieLibGetNextDescriptor (Complex);
+    }
+  }
+  Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling;
+  Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling;
+  Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime;
+  Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime;
+  Pcie->GfxCardWorkaround = GfxWorkaroundEnable;
+  Pcie->TrainingExitState = LinkStateTrainingCompleted;
+  Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm;
+  if ((UserOptions.CfgAmdPlatformType  & AMD_PLATFORM_MOBILE) != 0) {
+    Pcie->GfxCardWorkaround = GfxWorkaroundDisable;
+  }
+  Pcie->PsppPolicy =  EarlyParamsPtr->GnbConfig.PsppPolicy;
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader);
+  GNB_DEBUG_CODE (
+    PcieConfigDebugDump (Pcie);
+    );
+  HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate global PCIe configuration data
+ *
+ *
+ *
+ * @param[in]  PcieComplexList User PCIe topology configuration
+ * @param[out] StdHeader       Standard configuration header
+ * @retval     Updated topology configuration
+ */
+PCIe_COMPLEX_DESCRIPTOR *
+PcieConfigProcessUserConfig (
+  IN       PCIe_COMPLEX_DESCRIPTOR         *PcieComplexList,
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  UINT32                    Node0SocketId;
+  UINT32                    Node0SiliconId;
+  UINTN                     NumberOfComplexes;
+  UINTN                     NumberOfPorts;
+  UINTN                     Index;
+  UINT16                    DescriptorLoLane;
+  UINT16                    DescriptorHiLane;
+  PCIe_COMPLEX_DESCRIPTOR   *ResultComplexConfig;
+  PCIe_COMPLEX_DESCRIPTOR   *SbComplexDescriptor;
+  PCIe_PORT_DESCRIPTOR      *SbPortDescriptor;
+  PCIe_PORT_DESCRIPTOR      DefaultSbPortDescriptor;
+  PCIe_ENGINE_DESCRIPTOR    *EngineDescriptor;
+  AGESA_STATUS              Status;
+  SbPortDescriptor = NULL;
+  GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader);
+  Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader);
+  if (Status == AGESA_UNSUPPORTED) {
+    return PcieComplexList;
+  }
+  if (PcieComplexList == NULL) {
+    // No complex descriptor for any silicon was provided
+    // 1. Create complex descriptor
+    // 2. Create SB port descriptor
+    // 3. Attach SB descriptor to complex descriptor created in step #1
+    ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear (
+                                                        AMD_GNB_TEMP_DATA_HANDLE,
+                                                        sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR),
+                                                        StdHeader
+                                                        );
+    SbComplexDescriptor = ResultComplexConfig;
+    SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR));
+    LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
+    SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+    // Attach post array to complex descriptor
+    SbComplexDescriptor->PciePortList = SbPortDescriptor;
+    SbComplexDescriptor->SocketId = Node0SocketId;
+    SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+  } else {
+    NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList);
+    SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId);
+    if (SbComplexDescriptor == NULL) {
+      // No complex descriptor for silicon that have SB attached.
+      // 1. Create complex descriptor. Will be first one in the list
+      // 2. Create SB port descriptor
+      // 3. Attach SB descriptor to complex descriptor created in step #1
+      ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear (
+                                                          AMD_GNB_TEMP_DATA_HANDLE,
+                                                          (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR),
+                                                          StdHeader
+                                                          );
+      SbComplexDescriptor = ResultComplexConfig;
+      SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR));
+      LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
+      SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+      // Attach post array to complex descriptor
+      SbComplexDescriptor->PciePortList = SbPortDescriptor;
+      SbComplexDescriptor->SocketId = Node0SocketId;
+      SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+      LibAmdMemCopy (
+        (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR),
+        PcieComplexList,
+        NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR),
+        StdHeader
+        );
+
+    } else {
+      // Complex descriptor that represent silicon that have SB attached exist
+      // 1. Determine if complex have descriptor for SB
+      // 2. Create new descriptor for SB if needed
+      NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor);
+      ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer (
+                                                          AMD_GNB_TEMP_DATA_HANDLE,
+                                                          NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR),
+                                                          StdHeader
+                                                          );
+      // Copy complex descriptor array
+      LibAmdMemCopy (
+        ResultComplexConfig,
+        PcieComplexList,
+        NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR),
+        StdHeader
+        );
+      if (NumberOfPorts != 0) {
+        // Copy port descriptor array associated with complex with SB attached
+        LibAmdMemCopy (
+          (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR),
+          SbComplexDescriptor->PciePortList,
+          NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR),
+          StdHeader
+          );
+        // Update SB complex pointer on in memory list
+        SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId);
+        // Attach port descriptor array to complex
+        SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR));
+        for (Index = 0; Index < NumberOfPorts; ++Index) {
+          EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index);
+          if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+            DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+            DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+            if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) {
+              SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor;
+            }
+          }
+        }
+      }
+      if (SbPortDescriptor == NULL) {
+        // No descriptor that represent SB where found, create new one, will be first one in list
+        SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR));
+        // Copy default config info
+        LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
+        // Reattach descriptor list to complex
+        SbComplexDescriptor->PciePortList = SbPortDescriptor;
+      } else {
+        // Move SB descriptor to be first one in array
+        LibAmdMemCopy (
+          (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR),
+          SbPortDescriptor,
+          sizeof (PCIe_PORT_DESCRIPTOR),
+          StdHeader
+          );
+        // Disable original SB descriptor
+        SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine;
+        //Update pointer to new SB descriptor
+        SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR));
+        //It is no longer a descriptor that terminates list
+        SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST);
+        // Reattach descriptor list to complex
+        SbComplexDescriptor->PciePortList = SbPortDescriptor;
+      }
+    }
+  }
+  // Mark descriptor as SB link
+  SbPortDescriptor->Port.MiscControls.SbLink = 0x1;
+  return ResultComplexConfig;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate global PCIe configuration data
+ *
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @param[out] Pcie            Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS   Configuration data successfully located
+ * @retval     AGESA_FATAL     Configuration can not be located.
+ */
+AGESA_STATUS
+PcieLocateConfigurationData (
+  IN       AMD_CONFIG_PARAMS               *StdHeader,
+     OUT   PCIe_PLATFORM_CONFIG            **Pcie
+  )
+{
+  *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader);
+  if (*Pcie == NULL) {
+    IDS_ERROR_TRAP;
+    return AGESA_FATAL;
+  }
+  (*Pcie)->StdHeader = /* (PVOID) */ (UINT32)StdHeader;
+  PcieUpdateConfigurationData (*Pcie);
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attache descriptors
+ *
+ *
+ * @param[in]      Type       Descriptor type
+ * @param[in,out]  Base       Base descriptor
+ * @param[in,out]  New      New  descriptor
+ */
+VOID
+STATIC
+PcieConfigAttachDescriptors (
+  IN       UINT32                         Type,
+  IN OUT   PCIe_DESCRIPTOR_HEADER         *Base,
+  IN OUT   PCIe_DESCRIPTOR_HEADER         *New
+  )
+{
+  PCIe_DESCRIPTOR_HEADER  *Left;
+  PCIe_DESCRIPTOR_HEADER  *Right;
+
+  Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base));
+  ASSERT (Left != NULL);
+  Right = PcieConfigGetChild (Type, New);
+  Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left);
+  PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach configurations of two GNB to each other.
+ *
+ * Function will link all data structure to linked lists
+ *
+ * @param[in,out]  Base       Base complex descriptor
+ * @param[in,out]  New        New complex descriptor
+ */
+VOID
+STATIC
+PcieConfigAttachComplexes (
+  IN OUT   PCIe_COMPLEX_CONFIG            *Base,
+  IN OUT   PCIe_COMPLEX_CONFIG            *New
+  )
+{
+  // Connect Complex
+  Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base);
+  PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  // Connect Silicon
+  PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header);
+  // Connect Wrappers
+  PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header);
+  // Connect Engines
+  PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update configuration data
+ *
+ * Puprouse of this structure to update config data that base on programming of
+ * other silicon compoments. For instance PCI address of GNB and PCIe ports
+ * can change by AGESA or external agent
+ *
+ *
+ * @param[in,out]   Pcie        Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS    Configuration data successfully update
+ * @retval     AGESA_FATAL      Failt to update configuration
+ */
+AGESA_STATUS
+PcieUpdateConfigurationData (
+  IN       PCIe_PLATFORM_CONFIG            *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG   *Silicon;
+  PCIe_ENGINE_CONFIG    *Engine;
+  PCI_ADDR              NewAddress;
+  // Update silicon configuration
+  Silicon = PcieConfigGetChildSilicon (Pcie);
+  while (Silicon != NULL) {
+    NewAddress = GnbFmGetPciAddress ((GNB_HANDLE *) PcieConfigGetParentComplex (Silicon), GnbLibGetHeader (Pcie));
+    if (Silicon->Address.AddressValue != NewAddress.AddressValue) {
+      Silicon->Address.AddressValue = NewAddress.AddressValue;
+      Engine = PcieConfigGetChildEngine (Silicon);
+      while (Engine != NULL) {
+        if (PcieConfigIsPcieEngine (Engine)) {
+          Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus;
+        }
+        Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB);
+      }
+    }
+    Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
new file mode 100644
index 0000000000..063d408245
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIECONFIGDATA_H_
+#define _PCIECONFIGDATA_H_
+
+
+AGESA_STATUS
+PcieLocateConfigurationData (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  OUT     PCIe_PLATFORM_CONFIG            **Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
new file mode 100644
index 0000000000..0083e80ad9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -0,0 +1,827 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65589 $   @e \$Date: 2012-02-19 20:32:29 -0600 (Sun, 19 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "PcieMapTopology.h"
+#include  "PcieInputParser.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * get Master Lane of PCIe port engine
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine descriptor
+ * @retval                 Master Engine Lane Number
+ */
+UINT8
+PcieConfigGetPcieEngineMasterLane (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT8                 MasterLane;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+  ASSERT (PcieConfigIsPcieEngine (Engine));
+
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) {
+    MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane);
+  } else {
+    MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane);
+  }
+  return MasterLane;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of core lanes
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine descriptor
+ * @retval                 Number of core lane
+ */
+UINT8
+PcieConfigGetNumberOfCoreLane (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) {
+    return 0;
+  }
+  return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable engine
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ */
+VOID
+PcieConfigDisableEngine (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  if (PcieConfigIsSbPcieEngine (Engine)) {
+    return;
+  }
+  PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable all engines on wrapper
+ *
+ *
+ *
+ * @param[in]  EngineTypeMask Engine type bitmap.
+ * @param[in]  Wrapper        Pointer to wrapper config descriptor
+ */
+VOID
+PcieConfigDisableAllEngines (
+  IN      UINTN                          EngineTypeMask,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) {
+      PcieConfigDisableEngine (EngineList);
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get engine PHY lanes bitmap
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ */
+UINT32
+PcieConfigGetEnginePhyLaneBitMap (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitMap;
+  LaneBitMap = 0;
+  if (PcieLibIsEngineAllocated (Engine)) {
+    LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) <<  (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane);
+  }
+  return LaneBitMap;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of phy lanes
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine config descriptor
+ * @retval                 Number of Phy lane
+ */
+UINT8
+PcieConfigGetNumberOfPhyLane (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+    return 0;
+  }
+  if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
+    return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1);
+  } else {
+    return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get port configuration signature for given wrapper and core
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper config descriptor
+ * @param[in]  CoreId      Core ID
+ * @retval                 Configuration Signature
+ */
+UINT64
+PcieConfigGetConfigurationSignature (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper,
+  IN      UINT8                          CoreId
+  )
+{
+  UINT64              ConfigurationSignature;
+  PCIe_ENGINE_CONFIG  *EngineList;
+  ConfigurationSignature = 0;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsPcieEngine (EngineList) && EngineList->Type.Port.CoreId == CoreId) {
+      ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList);
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  return ConfigurationSignature;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check Port Status
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  PortStatus      Check if status asserted for port
+ * @retval                     TRUE if status asserted
+ */
+BOOLEAN
+PcieConfigCheckPortStatus (
+  IN       PCIe_ENGINE_CONFIG            *Engine,
+  IN       UINT32                        PortStatus
+  )
+{
+  return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set/Reset port status
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  SetStatus       SetStatus
+ * @param[in]  ResetStatus     ResetStatus
+ *
+ */
+UINT16
+PcieConfigUpdatePortStatus (
+  IN       PCIe_ENGINE_CONFIG               *Engine,
+  IN       PCIe_ENGINE_INIT_STATUS          SetStatus,
+  IN       PCIe_ENGINE_INIT_STATUS          ResetStatus
+  )
+{
+  Engine->InitStatus |= SetStatus;
+  Engine->InitStatus &= (~ResetStatus);
+  return Engine->InitStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute callback on all descriptor of specific type
+ *
+ *
+ * @param[in]       InDescriptorFlags    Include descriptor flags
+ * @param[in]       OutDescriptorFlags   Exlude descriptor flags
+ * @param[in]       TerminationFlags     Termination flags
+ * @param[in]       Callback             Pointer to callback function
+ * @param[in, out]  Buffer               Pointer to buffer to pass information to callback
+ * @param[in]       Pcie                 Pointer to global PCIe configuration
+ */
+
+AGESA_STATUS
+PcieConfigRunProcForAllDescriptors (
+  IN       UINT32                           InDescriptorFlags,
+  IN       UINT32                           OutDescriptorFlags,
+  IN       UINT32                           TerminationFlags,
+  IN       PCIe_RUN_ON_DESCRIPTOR_CALLBACK  Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  )
+{
+  AGESA_STATUS            AgesaStatus;
+  AGESA_STATUS            Status;
+  PCIe_DESCRIPTOR_HEADER  *Descriptor;
+
+  AgesaStatus = AGESA_SUCCESS;
+  Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header);
+  while (Descriptor != NULL) {
+    if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) {
+      Status = Callback (Descriptor, Buffer, Pcie);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+    Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags);
+  }
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute callback on all wrappers in topology
+ *
+ *
+ * @param[in]       DescriptorFlags   Wrapper Flags
+ * @param[in]       Callback          Pointer to callback function
+ * @param[in, out]  Buffer            Pointer to buffer to pass information to callback
+ * @param[in]       Pcie              Pointer to global PCIe configuration
+ */
+
+AGESA_STATUS
+PcieConfigRunProcForAllWrappers (
+  IN       UINT32                        DescriptorFlags,
+  IN       PCIe_RUN_ON_WRAPPER_CALLBACK  Callback,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+
+  AgesaStatus = AGESA_SUCCESS;
+  Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header);
+  while (Wrapper != NULL) {
+    if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
+      if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) {
+        Status = Callback (Wrapper, Buffer, Pcie);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      }
+    }
+    Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute callback on all engine in topology
+ *
+ *
+ * @param[in]       DescriptorFlags Engine flags.
+ * @param[in]       Callback        Pointer to callback function
+ * @param[in, out]  Buffer          Pointer to buffer to pass information to callback
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PcieConfigRunProcForAllEngines (
+  IN       UINT32                        DescriptorFlags,
+  IN       PCIe_RUN_ON_ENGINE_CALLBACK   Callback,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+
+  PCIe_ENGINE_CONFIG  *Engine;
+  Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header);
+  while (Engine != NULL) {
+    if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
+      if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) {
+        if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) {
+          Callback (Engine, Buffer, Pcie);
+        }
+      }
+    }
+    Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get parent descriptor of specific type
+ *
+ *
+ * @param[in]       Type            Descriptor type
+ * @param[in]       Descriptor      Pointer to buffer to pass information to callback
+ */
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetParent (
+  IN       UINT32                        Type,
+  IN       PCIe_DESCRIPTOR_HEADER        *Descriptor
+  )
+{
+  while ((Descriptor->DescriptorFlags & Type) == 0) {
+    if (Descriptor->Parent != 0) {
+      Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent);
+    } else {
+      return NULL;
+    }
+  }
+  return Descriptor;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get child descriptor of specific type
+ *
+ *
+ * @param[in]       Type            Descriptor type
+ * @param[in]       Descriptor      Pointer to buffer to pass information to callback
+ */
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetChild (
+  IN       UINT32                        Type,
+  IN       PCIe_DESCRIPTOR_HEADER        *Descriptor
+  )
+{
+  while ((Descriptor->DescriptorFlags & Type) == 0) {
+    if (Descriptor->Child != 0) {
+      Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child);
+    } else {
+      return NULL;
+    }
+  }
+  return Descriptor;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get peer descriptor of specific type
+ *
+ *
+ * @param[in]       Type            Descriptor type
+ * @param[in]       Descriptor      Pointer to buffer to pass information to callback
+ */
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetPeer (
+  IN       UINT32                        Type,
+  IN       PCIe_DESCRIPTOR_HEADER        *Descriptor
+  )
+{
+  ASSERT (Descriptor != NULL);
+  while ((Descriptor->DescriptorFlags & Type) == 0) {
+    if (Descriptor->Peer != 0) {
+      Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer);
+    } else {
+      return NULL;
+    }
+  }
+  return Descriptor;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check is engine is active or potentially active
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine descriptor
+ * @retval                 TRUE  - engine active
+ * @retval                 FALSE - engine not active
+ */
+BOOLEAN
+PcieConfigIsActivePcieEngine (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  BOOLEAN Result;
+  ASSERT (PcieConfigIsPcieEngine (Engine));
+  Result = FALSE;
+  if (PcieConfigIsEngineAllocated (Engine)) {
+    if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+      (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate SB engine on wrapper
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to wrapper config descriptor
+ * @retval                 SB engine pointer or NULL
+ */
+PCIe_ENGINE_CONFIG *
+PcieConfigLocateSbEngine (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsSbPcieEngine (EngineList)) {
+      return EngineList;
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  return NULL;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump engine configuration
+ *
+ *
+ * @param[in]  EngineList           Engine Configuration
+ */
+VOID
+PcieConfigEngineDebugDump (
+  IN      PCIe_ENGINE_CONFIG        *EngineList
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Engine Type - %s\n        Start Phy Lane - %d\n        End   Phy Lane - %d\n",
+    ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"),
+    EngineList->EngineData.StartLane,
+    EngineList->EngineData.EndLane
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Scrath         - %d\n", EngineList->Scratch);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Init Status    - 0x%08x\n", EngineList->InitStatus);
+  if (PcieLibIsPcieEngine (EngineList)) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "        PCIe port configuration:\n");
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Port Training - %s\n",
+      (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled"
+      );
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          End Core Lane   - %d\n", EngineList->Type.Port.EndCoreLane);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Requested PCI Dev Number   - %d\n",EngineList->Type.Port.PortData.DeviceNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Requested PCI Func Number  - %d\n",EngineList->Type.Port.PortData.FunctionNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          PCI Address - %d:%d:%d\n",
+      EngineList->Type.Port.Address.Address.Bus,
+      EngineList->Type.Port.Address.Address.Device,
+      EngineList->Type.Port.Address.Address.Function
+      );
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Misc Control  - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Native PCI Dev Number  - %d\n", EngineList->Type.Port.NativeDevNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Hotplug - %s\n",
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown"))))
+      );
+    ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          ASPM    - %s\n",
+      (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : (
+      (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : (
+      (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" :  (
+      (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown")))
+      );
+    ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Speed   - %d\n",
+      EngineList->Type.Port.PortData.LinkSpeedCapability
+      );
+  } else {
+    IDS_HDT_CONSOLE (PCIE_MISC, "        DDI configuration:\n");
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Connector - %s\n",
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) ? "eDP To Lvds" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) ? "Realtec eDP To Lvds" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown")))))))))))))
+      );
+    ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1);
+    ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1);
+    ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump wrapper configuration
+ *
+ *
+ * @param[in]  WrapperList           Wrapper Configuration
+ */
+VOID
+PcieConfigWrapperDebugDump (
+  IN      PCIe_WRAPPER_CONFIG        *WrapperList
+  )
+{
+  PCIe_ENGINE_CONFIG    *EngineList;
+  IDS_HDT_CONSOLE (PCIE_MISC, "      <---------Wrapper - %s Config -------->\n",
+    PcieFmDebugGetWrapperNameString (WrapperList)
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Start PHY lane - %02d\n", WrapperList->StartPhyLane);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        End   PHY lane - %02d\n", WrapperList->EndPhyLane);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        PowerOffUnusedLanes - %x\n        PowerOffUnusedPlls - %x\n        ClkGating - %x\n"
+                              "        LclkGating - %x\n        TxclkGatingPllPowerDown - %x\n        PllOffInL1 - %x\n",
+    WrapperList->Features.PowerOffUnusedLanes,
+    WrapperList->Features.PowerOffUnusedPlls,
+    WrapperList->Features.ClkGating,
+    WrapperList->Features.LclkGating,
+    WrapperList->Features.TxclkGatingPllPowerDown,
+    WrapperList->Features.PllOffInL1
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "      <---------Wrapper - %s Config End----->\n",
+    PcieFmDebugGetWrapperNameString (WrapperList)
+    );
+  EngineList = PcieConfigGetChildEngine (WrapperList);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      PcieConfigEngineDebugDump (EngineList);
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump configuration to debug out
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieConfigDebugDump (
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG   *SiliconList;
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  PCIe_COMPLEX_CONFIG   *ComplexList;
+  ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
+  IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n");
+  IDS_HDT_CONSOLE (PCIE_MISC, "  PSPP Policy - %s\n",
+   (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" :
+   (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : (
+   (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : (
+   (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : (
+   (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown")))
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  GFX Workaround - %s\n",
+   (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled"
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  LinkL0Pooling - %dus\n",
+   Pcie->LinkL0Pooling
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  LinkGpioResetAssertionTime - %dus\n",
+   Pcie->LinkGpioResetAssertionTime
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  LinkReceiverDetectionPooling - %dus\n",
+   Pcie->LinkReceiverDetectionPooling
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Training Algorythm - %s\n",
+    (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : (
+    (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown")
+    );
+  while (ComplexList != NULL) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "  <---------- Complex Config Start ---------->\n");
+    IDS_HDT_CONSOLE (PCIE_MISC, "    Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags);
+    IDS_HDT_CONSOLE (PCIE_MISC, "    Socket ID - %d\n", ComplexList->SocketId);
+    SiliconList = PcieConfigGetChildSilicon (ComplexList);
+    while (SiliconList != NULL) {
+      IDS_HDT_CONSOLE (PCIE_MISC, "    <---------- Silicon Config Start -------->\n");
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags);
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Silicon ID - %d\n", SiliconList->SiliconId);
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Node ID - %d\n", SiliconList->NodeId);
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Host PCI Address - %d:%d:%d\n",
+        SiliconList->Address.Address.Bus,
+        SiliconList->Address.Address.Device,
+        SiliconList->Address.Address.Function
+        );
+      WrapperList = PcieConfigGetChildWrapper (SiliconList);
+      while (WrapperList != NULL) {
+        PcieConfigWrapperDebugDump (WrapperList);
+        WrapperList = PcieLibGetNextDescriptor (WrapperList);
+      }
+      IDS_HDT_CONSOLE (PCIE_MISC, "    <---------- Silicon Config End ---------->\n");
+      SiliconList = PcieLibGetNextDescriptor (SiliconList);
+    }
+    IDS_HDT_CONSOLE (PCIE_MISC, "  <---------- Complex Config End ------------>\n");
+    ComplexList = PcieLibGetNextDescriptor (ComplexList);
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump input configuration to user engine descriptor
+ *
+ *
+ * @param[in]  EngineDescriptor   Pointer to engine descriptor
+ */
+VOID
+PcieUserDescriptorConfigDump (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor
+  )
+{
+
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Engine Type - %s\n",
+    (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : (
+    (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : (
+    (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid"))
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "    Start Phy Lane - %d\n    End   Phy Lane - %d\n",
+    EngineDescriptor->EngineData.StartLane,
+    EngineDescriptor->EngineData.EndLane
+  );
+  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "    PortPresent - %d\n    ChannelType  - %d\n    DeviceNumber - %d\n    FunctionNumber - %d\n    LinkSpeedCapability - %d\n    LinkAspm - %d\n    LinkHotplug - %d\n    ResetId - %d\n    SB link - %d\n    MiscControls - 0x%02x\n" ,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls
+    );
+  }
+  if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "    ConnectorType - %d\n    AuxIndex  - %d\n    HdpIndex - %d\n" ,
+      ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType,
+      ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex,
+      ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex
+    );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump input configuration to debug out
+ *
+ *
+ * @param[in]  ComplexDescriptor   Pointer to user defined complex descriptor
+ */
+VOID
+PcieUserConfigConfigDump (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor
+  )
+{
+  PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor;
+  PCIe_COMPLEX_DESCRIPTOR     *CurrentComplexDescriptor;
+  UINTN                       ComplexIndex;
+  UINTN                       Index;
+  UINTN                       NumberOfEngines;
+  UINTN                       NumberOfComplexes;
+
+  IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n");
+
+  NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor);
+  for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) {
+    CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex);
+    NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor);
+    IDS_HDT_CONSOLE (PCIE_MISC, "  ComplexDescriptor SocketId - %d\n  NumberOfEngines - %d\n",
+        ComplexDescriptor->SocketId,
+        NumberOfEngines
+      );
+
+    for (Index = 0; Index < NumberOfEngines; Index++) {
+      EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
+      PcieUserDescriptorConfigDump (EngineDescriptor);
+    }
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
new file mode 100644
index 0000000000..4a732dce78
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -0,0 +1,248 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIECONFIGLIB_H_
+#define _PCIECONFIGLIB_H_
+
+typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) (
+  IN      PCIe_ENGINE_CONFIG                *Engine,
+  IN OUT  VOID                              *Buffer,
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) (
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper,
+  IN OUT  VOID                              *Buffer,
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) (
+  IN      PCIe_DESCRIPTOR_HEADER            *Descriptor,
+  IN OUT  VOID                              *Buffer,
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+UINT8
+PcieConfigGetPcieEngineMasterLane (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT8
+PcieConfigGetNumberOfCoreLane (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+VOID
+PcieConfigDisableAllEngines (
+  IN      UINTN                             EngineTypeMask,
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper
+  );
+
+VOID
+PcieConfigDisableEngine (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT32
+PcieConfigGetEnginePhyLaneBitMap (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT8
+PcieConfigGetNumberOfPhyLane (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT64
+PcieConfigGetConfigurationSignature (
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper,
+  IN      UINT8                             CoreId
+  );
+
+BOOLEAN
+PcieConfigCheckPortStatus (
+  IN       PCIe_ENGINE_CONFIG               *Engine,
+  IN       UINT32                           PortStatus
+  );
+
+UINT16
+PcieConfigUpdatePortStatus (
+  IN       PCIe_ENGINE_CONFIG               *Engine,
+  IN       PCIe_ENGINE_INIT_STATUS          SetStatus,
+  IN       PCIe_ENGINE_INIT_STATUS          ResetStatus
+  );
+
+VOID
+PcieConfigRunProcForAllEngines (
+  IN       UINT32                           DescriptorFlags,
+  IN       PCIe_RUN_ON_ENGINE_CALLBACK      Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+AGESA_STATUS
+PcieConfigRunProcForAllWrappers (
+  IN       UINT32                           DescriptorFlags,
+  IN       PCIe_RUN_ON_WRAPPER_CALLBACK     Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+AGESA_STATUS
+PcieConfigRunProcForAllDescriptors (
+  IN       UINT32                           InDescriptorFlags,
+  IN       UINT32                           OutDescriptorFlags,
+  IN       UINT32                           TerminationFlags,
+  IN       PCIe_RUN_ON_DESCRIPTOR_CALLBACK  Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetParent (
+  IN       UINT32                           Type,
+  IN       PCIe_DESCRIPTOR_HEADER           *Descriptor
+  );
+
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetChild (
+  IN       UINT32                           Type,
+  IN       PCIe_DESCRIPTOR_HEADER           *Descriptor
+  );
+
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetPeer (
+  IN       UINT32                           Type,
+  IN       PCIe_DESCRIPTOR_HEADER           *Descriptor
+ );
+
+BOOLEAN
+PcieConfigIsActivePcieEngine (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+PCIe_ENGINE_CONFIG *
+PcieConfigLocateSbEngine (
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper
+  );
+
+VOID
+PcieConfigDebugDump (
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+VOID
+PcieConfigWrapperDebugDump (
+  IN      PCIe_WRAPPER_CONFIG               *WrapperList
+  );
+
+VOID
+PcieConfigEngineDebugDump (
+  IN      PCIe_ENGINE_CONFIG                *EngineList
+  );
+
+VOID
+PcieUserConfigConfigDump (
+  IN      PCIe_COMPLEX_DESCRIPTOR           *ComplexDescriptor
+  );
+
+VOID
+PcieUserDescriptorConfigDump (
+  IN      PCIe_ENGINE_DESCRIPTOR            *EngineDescriptor
+  );
+
+#define PcieConfigGetParentWrapper(Descriptor)    ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header)))
+#define PcieConfigGetParentSilicon(Descriptor)    ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header)))
+#define PcieConfigGetParentComplex(Descriptor)    ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header)))
+#define PcieConfigGetPlatform(Descriptor)         ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))
+#define PcieConfigGetChildWrapper(Descriptor)     ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header)))
+#define PcieConfigGetChildEngine(Descriptor)      ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header)))
+#define PcieConfigGetChildSilicon(Descriptor)     ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header)))
+#define PcieConfigGetNextDescriptor(Descriptor)   ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor)))
+#define PcieConfigIsPcieEngine(Descriptor)        (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE)
+#define PcieConfigIsDdiEngine(Descriptor)         (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE)
+#define PcieConfigIsPcieWrapper(Descriptor)       (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE)
+#define PcieConfigIsSbPcieEngine(Engine)          (Engine != NULL ? ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) : FALSE)
+#define PcieConfigIsDdiWrapper(Descriptor)        (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE)
+#define PcieConfigIsEngineAllocated(Descriptor)   (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE)
+#define PcieConfigIsVirtualDesciptor(Descriptor)  (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE)
+#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags)   if (Descriptor != NULL) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags
+#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) if (Descriptor != NULL) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags))
+#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL)
+#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (Descriptor != NULL ? (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) : NULL)
+#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY)
+#define PcieConfigGetNextDataDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0 ? NULL : ++Descriptor)
+
+#define PcieConfigGetStdHeader(Descriptor)         ((AMD_CONFIG_PARAMS *)((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))->StdHeader)
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
new file mode 100644
index 0000000000..b4b6106772
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -0,0 +1,275 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Procedure to parse PCIe input configuration data
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "PcieInputParser.h"
+#include  "PcieConfigLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of complexes in platform topology configuration
+ *
+ *
+ *
+ * @param[in] ComplexList  First complex configuration in complex configuration array
+ * @retval                 Number of Complexes
+ *
+ */
+UINTN
+PcieInputParserGetNumberOfComplexes (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList
+  )
+{
+  UINTN                Result;
+  Result = 0;
+  while (ComplexList != NULL) {
+    Result++;
+    ComplexList = PcieInputParsetGetNextDescriptor (ComplexList);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of PCIe engines in given complex
+ *
+ *
+ *
+ * @param[in] Complex     Complex configuration
+ * @retval                Number of Engines
+ */
+UINTN
+PcieInputParserGetLengthOfPcieEnginesList (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+  )
+{
+  UINTN                 Result;
+  PCIe_PORT_DESCRIPTOR  *PciePortList;
+  Result = 0;
+  PciePortList = Complex->PciePortList;
+  while (PciePortList != NULL) {
+    Result++;
+    PciePortList = PcieInputParsetGetNextDescriptor (PciePortList);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of DDI engines in given complex
+ *
+ *
+ *
+ * @param[in] Complex     Complex configuration
+ * @retval                Number of Engines
+ */
+STATIC UINTN
+PcieInputParserGetLengthOfDdiEnginesList (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+  )
+{
+  UINTN                 Result;
+  PCIe_DDI_DESCRIPTOR  *DdiLinkList;
+  Result = 0;
+  DdiLinkList = Complex->DdiLinkList;
+  while (DdiLinkList != NULL) {
+    Result++;
+    DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList);
+  }
+  return Result;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of engines in given complex
+ *
+ *
+ *
+ * @param[in] Complex     Complex configuration header
+ * @retval                Number of Engines
+ */
+UINTN
+PcieInputParserGetNumberOfEngines (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *Complex
+  )
+{
+  UINTN                     Result;
+
+  Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) +
+           PcieInputParserGetLengthOfPcieEnginesList (Complex);
+  return Result;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Complex descriptor by index from given Platform configuration
+ *
+ *
+ *
+ * @param[in] ComplexList Platform topology configuration
+ * @param[in] Index       Complex descriptor Index
+ * @retval                Pointer to Complex Descriptor
+ */
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *ComplexList,
+  IN      UINTN                           Index
+  )
+{
+  ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList)));
+  return &ComplexList[Index];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Complex descriptor by index from given Platform configuration
+ *
+ *
+ *
+ * @param[in] ComplexList  Platform topology configuration
+ * @param[in] SocketId     Socket Id
+ * @retval                Pointer to Complex Descriptor
+ */
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptorOfSocket (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *ComplexList,
+  IN      UINT32                          SocketId
+  )
+{
+  PCIe_COMPLEX_DESCRIPTOR *Result;
+  Result = NULL;
+  while (ComplexList != NULL) {
+    if (ComplexList->SocketId == SocketId) {
+      Result = ComplexList;
+      break;
+    }
+    ComplexList = PcieInputParsetGetNextDescriptor (ComplexList);
+  }
+  return Result;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Engine descriptor from given complex by index
+ *
+ *
+ *
+ * @param[in] Complex     Complex descriptor
+ * @param[in] Index       Engine descriptor index
+ * @retval                Pointer to Engine Descriptor
+ */
+PCIe_ENGINE_DESCRIPTOR*
+PcieInputParserGetEngineDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *Complex,
+  IN      UINTN                           Index
+  )
+{
+  UINTN PcieListlength;
+  ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex)));
+  PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex);
+  if (Index < PcieListlength) {
+    return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]);
+  } else {
+    return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
new file mode 100644
index 0000000000..630f9ae187
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Procedure to parse PCIe input configuration data
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEINPUTPARSER_H_
+#define _PCIEINPUTPARSER_H_
+
+
+UINTN
+PcieInputParserGetNumberOfComplexes (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList
+ );
+
+UINTN
+PcieInputParserGetNumberOfEngines (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+ );
+
+
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList,
+  IN      UINTN                         Index
+ );
+
+PCIe_ENGINE_DESCRIPTOR*
+PcieInputParserGetEngineDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex,
+  IN      UINTN                         Index
+ );
+
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptorOfSocket (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList,
+  IN      UINT32                        SocketId
+  );
+
+UINTN
+PcieInputParserGetLengthOfPcieEnginesList (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+  );
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
new file mode 100644
index 0000000000..f1fc4b8ac5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -0,0 +1,672 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Procedure to map user define topology to processor configuration
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GeneralServices.h"
+#include  "PcieInputParser.h"
+#include  "PcieMapTopology.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieMapPortsPciAddresses (
+  IN      PCIe_SILICON_CONFIG         *Silicon,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  );
+
+AGESA_STATUS
+PcieMapTopologyOnWrapper (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT  PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+ );
+
+VOID
+PcieMapInitializeEngineData (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT  PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+ );
+
+BOOLEAN
+PcieCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR        *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  );
+
+BOOLEAN
+PcieIsDescriptorLinkWidthValid (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor
+  );
+
+BOOLEAN
+PcieCheckLanesMatch (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  );
+
+BOOLEAN
+PcieCheckDescriptorMapsToWrapper (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_WRAPPER_CONFIG         *Wrapper
+  );
+
+VOID
+PcieAllocateEngine (
+  IN      UINT8                       DescriptorIndex,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  ComplexDescriptor   Pointer to used define complex descriptor
+ * @param[in]  Complex             Pointer to complex descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+PcieMapTopologyOnComplex (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN      PCIe_COMPLEX_CONFIG         *Complex,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG *Silicon;
+  PCIe_WRAPPER_CONFIG *Wrapper;
+  AGESA_STATUS        AgesaStatus;
+  AGESA_STATUS        Status;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
+  Silicon = PcieConfigGetChildSilicon (Complex);
+  while (Silicon != NULL) {
+    Wrapper = PcieConfigGetChildWrapper (Silicon);
+    while (Wrapper != NULL) {
+      Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      if (Status == AGESA_ERROR) {
+        PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Fail to map topology on %s Wrapper\n",
+          PcieFmDebugGetWrapperNameString (Wrapper)
+          );
+        ASSERT (FALSE);
+      }
+      Wrapper = PcieLibGetNextDescriptor (Wrapper);
+    }
+    Status = PcieMapPortsPciAddresses (Silicon, Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Silicon = PcieLibGetNextDescriptor (Silicon);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  EngineType          Engine type
+ * @param[in]  ComplexDescriptor   Pointer to used define complex descriptor
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+STATIC AGESA_STATUS
+PcieEnginesToWrapper (
+  IN      PCIE_ENGINE_TYPE            EngineType,
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN      PCIe_WRAPPER_CONFIG         *Wrapper
+  )
+{
+  AGESA_STATUS                Status;
+  PCIe_ENGINE_CONFIG          *EngineList;
+  PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor;
+  UINT8                       ConfigurationId;
+  UINT8                       Allocations;
+  UINTN                       Index;
+  UINTN                       NumberOfDescriptors;
+
+  ConfigurationId = 0;
+  Allocations = 0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n");
+  NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor);
+  do {
+    Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++);
+    if (Status == AGESA_SUCCESS) {
+      Allocations = 0;
+      for (Index = 0; Index < NumberOfDescriptors; Index++) {
+        EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
+        if (EngineDescriptor->EngineData.EngineType == EngineType) {
+          // Step 1, belongs to wrapper check.
+          if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) {
+            ++Allocations;
+            EngineList = PcieConfigGetChildEngine (Wrapper);
+            while (EngineList != NULL) {
+              if (!PcieLibIsEngineAllocated (EngineList)) {
+                // Step 2.user descriptor less or equal to link width of engine
+                if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) {
+                  // Step 3, Check if link width is correct.x1, x2, x4, x8, x16.
+                  if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) {
+                    PcieConfigDisableEngine (EngineList);
+                    return AGESA_ERROR;
+                  }
+                  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+                    // Step 4, Family specifc, port device number match engine device
+                    if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
+                      //Step 5, Family specifc, lanes can be muxed.
+                      if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
+                        PcieAllocateEngine ((UINT8) Index, EngineList);
+                        --Allocations;
+                        break;
+                      }
+                    }
+                  } else {
+                    PcieAllocateEngine ((UINT8) Index, EngineList);
+                    --Allocations;
+                    break;
+                  }
+                }
+              } //end if PcieLibIsEngineAllocated
+              EngineList = PcieLibGetNextDescriptor (EngineList);
+            }
+          } //end if PcieCheckDescriptorMapsToWrapper
+        } // end if EngineType
+      } //end for
+    }
+  } while (Status == AGESA_SUCCESS && Allocations != 0);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if lane from  user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
+ *
+ *
+ * @param[in]  EngineDescriptor    Pointer to used define engine descriptor
+ * @param[in]  Wrapper             Pointer to PCIe_WRAPPER_CONFIG
+ * @retval     TRUE                Belongs to wrapper
+ * @retval     FALSE               Not belongs to wrapper
+ */
+BOOLEAN
+PcieCheckDescriptorMapsToWrapper (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_WRAPPER_CONFIG         *Wrapper
+  )
+{
+  BOOLEAN Result;
+  UINT16  DescriptorHiLane;
+  UINT16  DescriptorLoLane;
+  UINT16  DescriptorNumberOfLanes;
+
+  DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+  Result = FALSE;
+
+  if (Wrapper->StartPhyLane <= DescriptorLoLane && DescriptorHiLane <= Wrapper->EndPhyLane) {
+    // Lanes of descriptor belongs to wrapper
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Engine to be allocated.
+ *
+ *
+ * @param[in]  DescriptorIndex    UINT8 index
+ * @param[in]  Engine             Pointer to engine config
+ */
+VOID
+PcieAllocateEngine (
+  IN      UINT8                       DescriptorIndex,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  )
+{
+  PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED);
+  Engine->Scratch = DescriptorIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ * PCIE port
+ *
+ *
+ * 1 Check if lane from  user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
+ * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
+ * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
+ * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG)
+ * 5 Check if lane can be muxed
+ *
+ *
+ * DDI Link
+ *
+ * 1 Check if lane from  user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
+ * 2 Check lane from  (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
+ *
+ *
+ *
+ * @param[in]     ComplexDescriptor   Pointer to used define complex descriptor
+ * @param[in,out] Wrapper             Pointer to wrapper config descriptor
+ * @param[in]     Pcie                Pointer to global PCIe configuration
+ * @retval        AGESA_SUCCESS       Topology successfully mapped
+ * @retval        AGESA_ERROR         Topology can not be mapped
+ */
+AGESA_STATUS
+PcieMapTopologyOnWrapper (
+  IN       PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT   PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  AGESA_STATUS                AgesaStatus;
+  AGESA_STATUS                Status;
+  PCIe_ENGINE_CONFIG          *EngineList;
+  UINT32                      WrapperPhyLaneBitMap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status == AGESA_ERROR) {
+      // If we can not map topology on wrapper we can not enable any engines.
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION,
+        Wrapper->WrapId,
+        Wrapper->StartPhyLane,
+        Wrapper->EndPhyLane,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+      PcieConfigDisableAllEngines (PciePortEngine, Wrapper);
+    }
+  }
+  if (PcieLibIsDdiWrapper (Wrapper)) {
+    Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status == AGESA_ERROR) {
+      // If we can not map topology on wrapper we can not enable any engines.
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION,
+        Wrapper->WrapId,
+        Wrapper->StartPhyLane,
+        Wrapper->EndPhyLane,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+      PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper);
+    }
+  }
+  // Copy engine data
+  PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie);
+
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  // Verify if we oversubscribe lanes and PHY link width
+  WrapperPhyLaneBitMap = 0;
+  while (EngineList != NULL) {
+    UINT32  EnginePhyLaneBitMap;
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList);
+      if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n",
+          EngineList->EngineData.StartLane,
+          EngineList->EngineData.EndLane
+          );
+        PutEventLog (
+          AGESA_ERROR,
+          GNB_EVENT_INVALID_LANES_CONFIGURATION,
+          EngineList->EngineData.StartLane,
+          EngineList->EngineData.EndLane,
+          0,
+          0,
+          GnbLibGetHeader (Pcie)
+          );
+        PcieConfigDisableEngine (EngineList);
+        Status = AGESA_ERROR;
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      } else {
+        WrapperPhyLaneBitMap |= EnginePhyLaneBitMap;
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize engine data
+ *
+ *
+ *
+ * @param[in]     ComplexDescriptor   Pointer to user defined complex descriptor
+ * @param[in,out] Wrapper             Pointer to wrapper config descriptor
+ * @param[in]     Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieMapInitializeEngineData (
+  IN       PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT   PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  PCIe_ENGINE_DESCRIPTOR    *EngineDescriptor;
+
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (EngineList->Scratch != 0xFF) {
+        EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch);
+        LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie));
+        if (PcieLibIsDdiEngine (EngineList)) {
+          LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie));
+          EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch;
+        } else if (PcieLibIsPcieEngine (EngineList)) {
+          LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie));
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate PCI addresses for all PCIe engines on silicon
+ *
+ *
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  BOOLEAN Result;
+
+  if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
+    PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) ||
+    (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) {
+    Result = TRUE;
+  } else {
+    Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
+  }
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate PCI addresses for all PCIe engines on silicon
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configurration
+ * @param[in]  Pcie                Pointer PCIe configuration
+ * @retval     AGESA_ERROR         Fail to allocate PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address for all PCIe ports
+ */
+
+AGESA_STATUS
+STATIC
+PcieMapPortsPciAddresses (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  AGESA_STATUS        Status;
+  AGESA_STATUS        AgesaStatus;
+  PCIe_WRAPPER_CONFIG *WrapperList;
+  PCIe_ENGINE_CONFIG  *EngineList;
+  AgesaStatus = AGESA_SUCCESS;
+  WrapperList = PcieConfigGetChildWrapper (Silicon);
+  while (WrapperList != NULL) {
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
+        Status = PcieFmMapPortPciAddress (EngineList);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+        if (Status == AGESA_SUCCESS) {
+          EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
+                                                         0,
+                                                         Silicon->Address.Address.Bus,
+                                                         EngineList->Type.Port.PortData.DeviceNumber,
+                                                         EngineList->Type.Port.PortData.FunctionNumber,
+                                                         0
+                                                         );
+        } else {
+          EngineList->Type.Port.PortData.PortPresent = OFF;
+          IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Fail to allocate PCI address for PCIe port\n"
+            );
+          //Report error
+          PutEventLog (
+            AGESA_ERROR,
+            GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
+            EngineList->Type.Port.PortData.DeviceNumber,
+            0,
+            0,
+            0,
+            GnbLibGetHeader (Pcie)
+            );
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    WrapperList = PcieLibGetNextDescriptor (WrapperList);
+  }
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * If link width from user descriptor less or equal to link width of engine
+ *
+ *
+ * @param[in]  EngineDescriptor    Pointer to used define engine descriptor
+ * @param[in]  Engine              Pointer to engine config
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckLanesMatch (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  )
+{
+  BOOLEAN Result;
+  UINT16  DescriptorHiLane;
+  UINT16  DescriptorLoLane;
+  UINT16  DescriptorNumberOfLanes;
+
+  DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+  Result = FALSE;
+
+  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+    //
+    // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
+    //
+    if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) {
+      Result = TRUE;
+    }
+  } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
+    //
+    //For Ddi, check lane from  (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
+    //
+    if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) {
+      Result = TRUE;
+    }
+  }
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
+ *
+ *
+ * @param[in]  EngineDescriptor    A pointer of PCIe_ENGINE_DESCRIPTOR
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieIsDescriptorLinkWidthValid (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor
+  )
+{
+  BOOLEAN   Result;
+  UINT16    DescriptorHiLane;
+  UINT16    DescriptorLoLane;
+  UINT16    DescriptorNumberOfLanes;
+
+  Result = FALSE;
+  DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+
+  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+    if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 ||
+        DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) {
+      Result = TRUE;
+    }
+  } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
+    if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) {
+      Result = TRUE;
+    }
+  }
+
+  GNB_DEBUG_CODE (
+    if (!Result) {
+      IDS_HDT_CONSOLE (PCIE_MISC, "  Invalid Link width [Engine Lanes %d..%d]\n",
+        DescriptorLoLane,
+        DescriptorHiLane
+      );
+    }
+  );
+
+  return Result;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
new file mode 100644
index 0000000000..7f69aeab85
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Procedure to map user define topology to processor configuration
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEMAPTOPOLOGY_H_
+#define _PCIEMAPTOPOLOGY_H_
+
+AGESA_STATUS
+PcieMapTopologyOnComplex (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN      PCIe_COMPLEX_CONFIG         *Complex,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+ );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
new file mode 100644
index 0000000000..d92559cca9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Init Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEINITLIBV1_H_
+#define _PCIEINITLIBV1_H_
+
+#include "PciePifServices.h"
+#include "PciePortRegAcc.h"
+#include "PciePowerMgmt.h"
+#include "PcieTimer.h"
+#include "PcieTopologyServices.h"
+#include "PcieUtilityLib.h"
+#include "PcieWrapperRegAcc.h"
+#include "PcieAspmExitLatency.h"
+#include "PcieSiliconServices.h"
+#include "PciePortServices.h"
+#include "PcieAspm.h"
+#include "PciePhyServices.h"
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
new file mode 100644
index 0000000000..4642b7fa24
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -0,0 +1,179 @@
+/**
+ * @file
+ *
+ * PCIe link ASPM Black List
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "PcieAspmBlackList.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+UINT16  AspmBrDeviceTable[] = {
+ 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x168C, 0xFFFF, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x9123, (UINT16) ~(AspmL0s),
+ 0x1969, 0x1083, (UINT16) ~(AspmL0s)
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie ASPM Black List
+ *
+ *
+ *
+ * @param[in] LinkAsmp            PCie ASPM black list
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieAspmBlackListFeature (
+  IN       PCIe_LINK_ASPM         *LinkAsmp,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  UpstreamDeviceId;
+  UINT32  DownstreamDeviceId;
+  UINTN   i;
+  UINT32  DeviceId;
+  UINT32  VendorId;
+
+  GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader);
+  GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader);
+  for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    VendorId = AspmBrDeviceTable[i];
+    DeviceId = AspmBrDeviceTable[i + 1];
+    if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) {
+      if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) {
+        LinkAsmp->UpstreamAspm &= AspmBrDeviceTable[i + 2];
+        LinkAsmp->DownstreamAspm &= AspmBrDeviceTable[i + 2];
+      }
+    }
+  }
+  if ((UINT16)UpstreamDeviceId == 0x168c) {
+    LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL1;
+    LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm;
+    GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader);
+
+    DeviceId = UpstreamDeviceId >> 16;
+    if ((DeviceId == 0x002C) || (DeviceId == 0x002B) || (DeviceId == 0x002E)) {
+      LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL0sL1;
+      LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm & AspmL1;
+    }
+  }
+  if (UpstreamDeviceId == 0x10831969) {
+    GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x12F8, AccessS3SaveWidth32, 0xFFF7F7FF, 0, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
new file mode 100644
index 0000000000..2857a70f29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * PCIe ASPM Black List
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPMBLACKLIST_H_
+#define _PCIEASPMBLACKLIST_H_
+
+///PCIe ASPM Black List
+
+AGESA_STATUS
+PcieAspmBlackListFeature (
+  IN       PCIe_LINK_ASPM         *LinkAsmp,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
new file mode 100644
index 0000000000..744c88b53b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -0,0 +1,218 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to calculate PCIe topology segment maximum exit latency
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo;
+  PCI_ADDR                DownstreamPort;
+  UINT8                   LinkCount;
+} PCIE_EXIT_LATENCY_DATA;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+SCAN_STATUS
+PcieAspmGetMaxExitLatencyCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine ASPM L-state maximum exit latency for PCIe segment
+ *
+ *  Scan through all link in segment to determine maxim exit latency requirement by EPs.
+ *
+ * @param[in]   DownstreamPort    PCI address of PCIe port
+ * @param[out]  AspmLatencyInfo   Latency info
+ * @param[in]   StdHeader         Standard configuration header
+ *
+ */
+
+VOID
+PcieAspmGetMaxExitLatency (
+  IN       PCI_ADDR                DownstreamPort,
+     OUT   PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_EXIT_LATENCY_DATA  PcieExitLatencyData;
+  PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo;
+  PcieExitLatencyData.ScanData.StdHeader = StdHeader;
+  PcieExitLatencyData.LinkCount = 0;
+  PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieAspmGetMaxExitLatencyCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_EXIT_LATENCY_DATA  *PcieExitLatencyData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT32                  Value;
+  UINT8                   PcieCapPtr;
+  UINT8                   L1AcceptableLatency;
+
+  PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    PcieExitLatencyData->DownstreamPort = Device;
+    PcieExitLatencyData->LinkCount++;
+    GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData);
+    PcieExitLatencyData->LinkCount--;
+    break;
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+    ASSERT (PcieCapPtr != 0);
+    GnbLibPciRead (
+      Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
+      AccessWidth32,
+      &Value,
+      ScanData->StdHeader
+      );
+    if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) {
+      GnbLibPciRead (
+        Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER),
+        AccessWidth32,
+        &Value,
+        ScanData->StdHeader
+        );
+      L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7));
+      if (PcieExitLatencyData->LinkCount > 1) {
+        L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount;
+      }
+      if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency <  L1AcceptableLatency) {
+        PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency;
+      }
+      IDS_HDT_CONSOLE (PCIE_MISC, "  Device max exit latency  L1 - %d us\n",
+        L1AcceptableLatency
+        );
+    }
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
new file mode 100644
index 0000000000..12c16e5a69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to calculate PCIe topology segment maximum exit latency
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPMEXITLATENCY_H_
+#define _PCIEASPMEXITLATENCY_H_
+
+VOID
+PcieAspmGetMaxExitLatency (
+  IN       PCI_ADDR                DownstreamPort,
+     OUT   PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
new file mode 100644
index 0000000000..77def5281c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
@@ -0,0 +1,334 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MAX_NUM_PHYs          2
+#define MAX_NUM_LANE_PER_PHY  8
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+//Channel Type:              LowLoss / HighLoss / Mob0db / Mob3db / Ext6db / Ext8db
+INT8  chtype_0 /* DeemphasisSel */ [] = {      1,         0,        1,      1,       0,        0};
+INT8  chtype_1 /* DeemphGen1Nom */ [] = {      42,        42,       0,      0,       42,       42};
+INT8  chtype_2 /* DeemPh35Gen2Nom */ [] = {    42,        64,       0,      42,      64,       77};
+INT8  chtype_3 /* Deemph60Gen2NOm */ [] = {    42,        64,       0,      42,      64,       77};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY lane ganging
+ *
+ *
+ *
+ * @param[out] Wrapper             Pointer to internal configuration data area
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT8               GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY];
+  UINT8               MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY];
+  UINT16              LoPhylane;
+  UINT16              HiPhylane;
+  UINT8               Phy;
+  UINT16              Lane;
+  UINT16              PhyLinkWidth;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n");
+  LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie));
+  LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie));
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      HiPhylane = PcieLibGetHiPhyLane (EngineList) - Wrapper->StartPhyLane;
+      LoPhylane = PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
+      PhyLinkWidth = HiPhylane - LoPhylane + 1;
+
+      if (PhyLinkWidth >= 8) {
+        for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) {
+          ((UINT8 *) GangMatrix)[Lane] = 1;
+        }
+      } else {
+        if (PhyLinkWidth > 0 && PhyLinkWidth < 4) {
+          for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) {
+            ((UINT8 *) MasterMatrix)[Lane] = 1;
+          }
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+    for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) {
+      D0F0xE4_PHY_6005_STRUCT  D0F0xE4_PHY_6005;
+      D0F0xE4_PHY_6005.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80),
+                                 Pcie
+                                 );
+      D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane];
+      D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane];
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80),
+        D0F0xE4_PHY_6005.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Point "virtual" PLL clock picker away from PCIe
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to internal configuration data area
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyAvertClockPickers (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  DdiLanes;
+  UINT8   Nibble;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n");
+  DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (DdiLanes & (0xf << (Nibble * 4))) {
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PHY_0009_PCIePllSel_MASK,
+        0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET,
+        FALSE,
+        Pcie
+        );
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK,
+        (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET),
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PHY channel characteristic
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyChannelCharacteristic (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG         *Wrapper;
+  UINT16                      StartLane;
+  UINT16                      EndLane;
+  UINT16                      Lane;
+  UINT8                       ChannelType;
+
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  ChannelType = Engine->Type.Port.PortData.ChannelType;
+  StartLane = MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane;
+  EndLane = MAX (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane;
+
+  PcieRegisterRMW (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0803_ADDRESS + (Engine->Type.Port.PortId) * 0x100),
+    D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK,
+    chtype_0 /* DeemphasisSel */[ChannelType] << D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET,
+    FALSE,
+    Pcie
+    );
+  for (Lane = StartLane; Lane <= EndLane; Lane++) {
+    UINT16 PhyLane;
+    UINT16 Phy;
+    if (Lane < MAX_NUM_LANE_PER_PHY ) {
+      Phy = 0;
+      PhyLane = Lane;
+    } else {
+      Phy = 1;
+      PhyLane = Lane - MAX_NUM_LANE_PER_PHY;
+    }
+    PcieRegisterRMW (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80),
+      D0F0xE4_PHY_6006_DeemphGen1Nom_MASK,
+      chtype_1 /* DeemphGen1Nom */[ChannelType] << D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterRMW (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80),
+      D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK,
+      chtype_2 /* DeemPh35Gen2Nom */[ChannelType] << D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterRMW (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80),
+      D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK,
+      chtype_3 /* Deemph60Gen2NOm */[ChannelType] << D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DCC recalibration
+ *
+ *
+ *
+ * @param[in]     Wrapper           Pointer to internal configuration data area
+ * @param[in]     Pcie              Pointer to global PCIe configuration
+ */
+
+AGESA_STATUS
+PciePhyForceDccRecalibration (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   Phy;
+  UINT8   PhyLane;
+  for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+    for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4001_ADDRESS + PhyLane * 0x80),
+        D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET,
+        D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH,
+        0x1,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
new file mode 100644
index 0000000000..946de59030
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEPHYSERVICES_H_
+#define _PCIEPHYSERVICES_H_
+
+VOID
+PciePhyApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyAvertClockPickers (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyChannelCharacteristic (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PciePhyForceDccRecalibration (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
new file mode 100644
index 0000000000..8973820082
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -0,0 +1,654 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PIF_GANG_0to1  0x1
+#define PIF_GANG_2to3  (0x1 << 1)
+#define PIF_GANG_4to5  (0x1 << 2)
+#define PIF_GANG_6to7  (0x1 << 3)
+#define PIF_GANG_0to3  (0x1 << 4)
+#define PIF_GANG_4to7  (0x1 << 8)
+#define PIF_GANG_0to7  (0x1 << 9)
+#define PIF_GANG_ALL   (0x1 << 25)
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply PIF ganging for all lanes for given wrapper
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG      *EngineList;
+  UINT32                  LaneBitmap;
+  UINT8                   Pif;
+  D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2];
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n");
+  LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie));
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, EngineList);
+      switch (LaneBitmap) {
+      case  0x0003:
+        D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1;
+        break;
+      case  0x000c:
+        D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1;
+        break;
+      case  0x0030:
+        D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1;
+        break;
+      case  0x00c0:
+        D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1;
+        break;
+      case  0x000f:
+        D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1;
+        break;
+      case  0x00f0:
+        D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1;
+        break;
+      case  0x00ff:
+        D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1;
+        break;
+      case  0x0300:
+        D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1;
+        break;
+      case  0x0c00:
+        D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1;
+        break;
+      case  0x3000:
+        D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1;
+        break;
+      case  0xc000:
+        D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1;
+        break;
+      case  0x0f00:
+        D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1;
+        break;
+      case  0xf000:
+        D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1;
+        break;
+      case  0xff00:
+        D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1;
+        break;
+      case  0xffff:
+        D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1;
+        D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1;
+        break;
+      default:
+        break;
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS),
+        D0F0xE4_PIF_0011[Pif].Value,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL powerdown
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllPowerDown (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT16                  NibbleBitmap;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n");
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    NibbleBitmap = (0xF << (Nibble * 4));
+    if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL init for DDI
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllInitForDdi (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT32                  LaneBitmap;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n");
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (LaneBitmap & (0xF << (Nibble * 4))) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for on PIF to indicate action completion
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollPifForCompeletion (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  //UINT32                  TimeStamp;
+  UINT8                   Pif;
+  D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015;
+  //TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    do {
+      D0F0xE4_PIF_0015.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS),
+                                 Pcie
+                                 );
+      //if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) {
+      //  break;
+      //}
+    } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable fifo reset
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifDisableFifoReset (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET,
+      D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program LS2 exit time
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetLs2ExitTime (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET,
+        D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH,
+        0x0,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PLL mode for L1
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifSetPllModeForL1 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (LaneBitmap & (0xF << (Nibble * 4))) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program receiver detection power mode
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetRxDetectPowerMode (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET,
+        D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH,
+        0x1,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pll ramp up time
+ *
+ *
+ *
+ * @param[in]  Rampup              Ramp up time
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifSetPllRampTime (
+  IN      PCIE_PLL_RAMPUP_TIME  Rampup,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Pif;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
+  D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0013.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0010.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+                               Pcie
+                               );
+    if (Rampup == NormalRampup) {
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
+      D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1;
+      D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0;
+    } else {
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3;
+      D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3;
+      D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010.Value,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down PIFs
+ *
+ *
+ *
+ * @param[in]  Control             Power up or Power down control
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifPllPowerControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8   Pif;
+  UINT8   PllPowerStateInOff;
+  PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET,
+      D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH,
+      PllPowerStateInOff,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET,
+      D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH,
+      PllPowerStateInOff,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down PIFs
+ *
+ *
+ *
+ * @param[in]  Control             Power up/Down control
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifFullPowerStateControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8                   Pif;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0013.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+                               Pcie
+                               );
+    if (Control == PowerDownPifs) {
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+    } else {
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013.Value,
+      FALSE,
+      Pcie
+      );
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
new file mode 100644
index 0000000000..d0c2a81b73
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEPIFSERVICES_H_
+#define _PCIEPIFSERVICES_H_
+
+VOID
+PciePifApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerDown (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllInitForDdi (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollPifForCompeletion (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifDisableFifoReset (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetLs2ExitTime (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetPllModeForL1 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetRxDetectPowerMode (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetPllRampTime (
+  IN      PCIE_PLL_RAMPUP_TIME  Rampup,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PciePifFullPowerStateControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
new file mode 100644
index 0000000000..d02fbf6a06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -0,0 +1,257 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe port indirect register
+ * space.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "PciePortRegAcc.h"
+#include  "GnbCommonLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe port indirect register.
+ *
+ * Support for unify register access through index/data pair on PCIe port
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Register Value
+ */
+
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  Value       New register value
+ * @param[in]  S3Save      Save for S3 flag
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ */
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ASSERT (S3Save == TRUE || S3Save == FALSE);
+
+  IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, "    *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n",
+    Engine->Type.Port.Address.Address.Bus,
+    Engine->Type.Port.Address.Address.Device,
+    Engine->Type.Port.Address.Address.Function,
+    Address,
+    Value
+    );
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  S3Save      Save for S3 flag
+ * @param[in]  Value       New register value
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ */
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Data;
+  UINT32  Mask;
+  Data = PciePortRegisterRead (Engine, Address, Pcie);
+  Mask = (1 << FieldWidth) - 1;
+  Value &= Mask;
+  Data &= (~(Mask << FieldOffset));
+  PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Register Field Value.
+ */
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PciePortRegisterRead (Engine, Address, Pcie);
+  Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1);
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe port register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PciePortRegisterRead (Engine, Address, Pcie);
+  Value = (Value & (~AndMask)) | OrMask;
+  PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
new file mode 100644
index 0000000000..426f3b8cba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe port indirect register space.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTREGACC_H_
+#define _PCIEPORTREGACC_H_
+
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
new file mode 100644
index 0000000000..456b2552cd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -0,0 +1,533 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set completion timeout
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS,
+    AccessWidth32,
+    0xffffffff,
+    0x6 << DxF0x80_CplTimeoutValue_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_x20_ADDRESS,
+      DxF0xE4_x20_TxFlushTlpDis_OFFSET,
+      DxF0xE4_x20_TxFlushTlpDis_WIDTH,
+      0x0,
+      TRUE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init hotplug port
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  DxF0xE4_xB5_STRUCT  DxF0xE4_xB5;
+  if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
+    DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
+    DxF0xE4_xB5.Field.line521  = 0x3;
+    DxF0xE4_xB5.Field.line522  = 0x3;
+    DxF0xE4_xB5.Field.line519  = 0x1;
+    PciePortRegisterWrite (
+      Engine,
+      DxF0xE4_xB5_ADDRESS,
+      DxF0xE4_xB5.Value,
+      TRUE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
+      D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
+      D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
+      0x5,
+      TRUE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, 0x8011 ),
+      16 ,
+      1 ,
+      0x1,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << DxF0x6C_HotplugCapable_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_x20_ADDRESS,
+      DxF0xE4_x20_TxFlushTlpDis_OFFSET,
+      DxF0xE4_x20_TxFlushTlpDis_WIDTH,
+      0x0,
+      TRUE,
+      Pcie
+      );
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_x70_ADDRESS,
+      DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
+      DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set misc slot capability
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS,
+    AccessWidth32,
+    0xffffffff,
+    1 << DxF0x58_SlotImplemented_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS,
+    AccessWidth32,
+    0xffffffff,
+    1 << DxF0x3C_IntPin_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Safe mode to force link advertize Gen1 only capability in TS
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  //Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1;
+  PcieFmSetLinkSpeedCap (PcieGen1, Engine, Pcie);
+  PciePortRegisterRMW (
+    Engine,
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcUpconfigureDis_MASK,
+    (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET),
+    FALSE,
+    Pcie
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterRMW (
+    Engine,
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcUpconfigureDis_MASK,
+    0,
+    FALSE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ex548_STRUCT   ex548 ;
+  DxF0xE4_xC0_STRUCT  DxF0xE4_xC0;
+  DxF0x88_STRUCT      DxF0x88;
+  GnbLibPciRead (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+  ex548.Value = PciePortRegisterRead (
+                        Engine,
+                        0xa4 ,
+                        Pcie
+                        );
+  DxF0xE4_xC0.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xC0_ADDRESS,
+                        Pcie
+                        );
+
+  switch (LinkSpeedCapability) {
+  case PcieGen2:
+    ex548.Field.LcGen2EnStrap = 0x1;
+    ex548.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
+    DxF0x88.Field.TargetLinkSpeed = 0x2;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
+    break;
+  case PcieGen1:
+    ex548.Field.LcGen2EnStrap = 0x0;
+    ex548.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
+    DxF0x88.Field.TargetLinkSpeed = 0x1;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+  PciePortRegisterWrite (
+    Engine,
+    0xa4 ,
+    ex548.Value,
+    FALSE,
+    Pcie
+    );
+  PciePortRegisterWrite (
+    Engine,
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0.Value,
+    FALSE,
+    Pcie
+    );
+  GnbLibPciWrite (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Force compliance
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) {
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+      AccessWidth32,
+      0xffffffff,
+      0x1 << DxF0x88_EnterCompliance_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+  } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) {
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_xC0_ADDRESS,
+      DxF0xE4_xC0_StrapForceCompliance_OFFSET,
+      DxF0xE4_xC0_StrapForceCompliance_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set slot power limit
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @param[in]  Pcie                Pointer to PCIe configuration
+ */
+
+
+VOID
+PcieEnableSlotPowerLimit (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "   Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
+    GnbLibPciIndirectRMW (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      (0x51  + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << 20 ,
+      GnbLibGetHeader (Pcie)
+    );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable ASPM on SB link
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) {
+    if (PcieConfigIsSbPcieEngine (Engine)) {
+      SbPcieLinkAspmControl (Engine, Pcie);
+    }
+  }
+}
+
+
+UINT8 L1State = 0x1b;
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for link to get into L1
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkHwStateHistory[8];
+  do {
+    PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie);
+  } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for link to get into L1
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkHwStateHistory[4];
+  do {
+    PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie);
+  } while (LinkHwStateHistory[0] != 0x10);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
new file mode 100644
index 0000000000..9ac8ce8346
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTSERVICES_H_
+#define _PCIEPORTSERVICES_H_
+
+
+VOID
+PcieSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieEnableSlotPowerLimit (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
new file mode 100644
index 0000000000..f15a582b5b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -0,0 +1,424 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes and plls
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrPowerDownUnusedLanes (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT32              UnusedLanes;
+  UINT32              AllLanes;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n");
+  if (Wrapper->Features.PowerOffUnusedPlls != 0) {
+    AllLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper);
+    UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Wrapper);
+    if (AllLanes != UnusedLanes) {
+      //Some lanes end up beeing used. We should keep master PLL powered up
+      UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, Wrapper);
+    }
+    PciePifPllPowerDown (
+      UnusedLanes,
+      Wrapper,
+      Pcie
+      );
+  }
+  if (Wrapper->Features.PowerOffUnusedLanes != 0) {
+    UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper);
+    PcieTopologyLaneControl (
+      DisableLanes,
+      UnusedLanes,
+      Wrapper,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lane bitmam to enable PLL power down in L1
+ *
+ *
+ * @param[in]  PllPowerUpLatency  Pointer to wrapper config descriptor
+ * @param[in]  Wrapper            Pointer to wrapper config descriptor
+ * @param[in]  Pcie               Pointer to global PCIe configuration
+ * @retval     Lane bitmap for which PLL can be powered down in L1
+ */
+
+UINT32
+PcieLanesToPowerDownPllInL1 (
+  IN       UINT8                  PllPowerUpLatency,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT8               LaneGroupExitLatency [4];
+  UINT32              LaneBitmapForPllOffInL1;
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINTN               Index;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n");
+  LaneBitmapForPllOffInL1 = 0;
+  if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) {
+    if (Wrapper->Features.PllOffInL1 != 0) {
+      LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie));
+      EngineList = PcieConfigGetChildEngine (Wrapper);
+      while (EngineList != NULL) {
+        PCIe_ASPM_LATENCY_INFO  LinkLatencyInfo;
+        UINT32                  ActiveLanesBitmap;
+        UINT32                  HotplugLanesBitmap;
+        if (EngineList->EngineData.EngineType == PciePortEngine) {
+          LinkLatencyInfo.MaxL1ExitLatency = 0;
+          LinkLatencyInfo.MaxL0sExitLatency = 0;
+          ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList);
+          HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList);
+          if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) {
+            PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
+          }
+          if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) {
+            LinkLatencyInfo.MaxL1ExitLatency = 0xff;
+          }
+          IDS_HDT_CONSOLE (GNB_TRACE, "  Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap);
+          for (Index = 0; Index < 4; Index++) {
+            if ((ActiveLanesBitmap  & (0xF << (Index * 4))) != 0) {
+              if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) {
+                IDS_HDT_CONSOLE (GNB_TRACE, "  Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
+                LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency;
+              }
+            }
+          }
+        }
+        EngineList = PcieLibGetNextDescriptor (EngineList);
+      }
+      LaneBitmapForPllOffInL1 = 0;
+      for (Index = 0; Index < 4; Index++) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
+        if (LaneGroupExitLatency[Index] > PllPowerUpLatency) {
+          LaneBitmapForPllOffInL1 |= (0xF << (Index * 4));
+        }
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "  Lane bitmap %04x\n", LaneBitmapForPllOffInL1);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n");
+  return LaneBitmapForPllOffInL1;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Auto-Power Down electrical Idle detector
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrAutoPowerDownElectricalIdleDetector (
+  IN       PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8   Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
+      D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
+      0x0,
+      TRUE,
+      Pcie
+      );
+
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, 0x10 ),
+      20 ,
+      3 /*D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH*/,
+      0x2,
+      TRUE,
+      Pcie
+      );
+
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
+      D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
+      0x1,
+      TRUE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clock gating
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrClockGating (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  ex501_STRUCT   ex501 ;
+  D0F0xE4_WRAP_8012_STRUCT  D0F0xE4_WRAP_8012;
+  D0F0xE4_WRAP_8014_STRUCT  D0F0xE4_WRAP_8014;
+  D0F0xE4_WRAP_8015_STRUCT  D0F0xE4_WRAP_8015;
+  ex688_STRUCT   ex688 ;
+  UINT8                     CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
+  D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+                              Pcie
+                              );
+
+  D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+                              Pcie
+                              );
+
+  ex501.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, 0x8011 ),
+                              Pcie
+                              );
+
+  if (Wrapper->Features.ClkGating == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
+
+
+    ex501.Field.TxclkDynGateEnable = 0x1;
+    ex501.Field.TxclkRegsGateEnable = 0x1;
+    ex501.Field.TxclkLcntGateEnable = 0x1;
+    ex501.Field.RcvrDetClkEnable = 0x1;
+    ex501.Field.TxclkPermGateEven = 0x1;
+    ex501.Field.TxclkDynGateLatency = 0x3f;
+    ex501.Field.TxclkRegsGateLatency = 0x3f;
+    ex501.Field.TxclkPermGateLatency = 0x3f;
+
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
+
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
+
+    D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
+  }
+  if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+    D0F0xE4_WRAP_8014.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+    D0F0xE4_WRAP_8015.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+    D0F0xE4_WRAP_8012.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, 0x8011 ),
+    ex501.Value,
+    TRUE,
+    Pcie
+    );
+  for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      CORE_SPACE (CoreId, 0x11 ),
+      0 ,
+      4 ,
+      0xf,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Wrapper->Features.LclkGating == 0x1) {
+    ex688.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, 0x8016 ),
+                                Pcie
+                                );
+    ex688.Field.LclkDynGateEnable = 0x1;
+    ex688.Field.LclkGateFree = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, 0x8016 ),
+      ex688.Value,
+      TRUE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
new file mode 100644
index 0000000000..3d237e0e81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERSAVINGFEATURES_H_
+#define _PCIEPOWERSAVINGFEATURES_H_
+
+
+VOID
+PciePwrPowerDownUnusedLanes (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieLanesToPowerDownPllInL1 (
+  IN       UINT8                  PllPowerUpLatency,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PciePwrAutoPowerDownElectricalIdleDetector (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePwrClockGating (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
new file mode 100644
index 0000000000..56b4aa71a0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 49911 $   @e \$Date: 2011-03-30 02:43:29 -0700 (Wed, 30 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Get current link speed
+   *
+   *  Arg0 - Port Index
+   *
+   */
+
+
+  Method (procPciePortGetCurrentLinkSpeed, 1, NotSerialized) {
+    Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcLinkCtrlLocal1)
+    ShiftRight (varLcLinkCtrlLocal1, 11, varCurrenLinkSpeedLocal2)
+    And (varCurrenLinkSpeedLocal2, 0x1, varCurrenLinkSpeedLocal2)
+    Increment (varCurrenLinkSpeedLocal2)
+    return (varCurrenLinkSpeedLocal2)
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
new file mode 100644
index 0000000000..010aae492c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -0,0 +1,284 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe complex initialization services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Gen1 voltage Index
+ *
+ *
+ *
+ *
+ * @param[in]  StdHeader           Standard configuration header
+ */
+UINT8
+PcieSiliconGetGen1VoltageIndex (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8   Index;
+  UINT8   Gen1VidIndex;
+  UINT8   SclkVidArray[4];
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, 0x15c ),
+    AccessWidth32,
+    &SclkVidArray[0],
+    StdHeader
+    );
+  Gen1VidIndex = 0;
+  for (Index = 0; Index < 4; Index++) {
+    if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
+      Gen1VidIndex = Index;
+    }
+  }
+  return Gen1VidIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request Pcie voltage change
+ *
+ *
+ *
+ * @param[in]  VidIndex            The request VID index
+ * @param[in]  StdHeader           Standard configuration header
+ */
+VOID
+PcieSiliconRequestVoltage (
+  IN      UINT8                 VidIndex,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  ex488_STRUCT     ex488 ;
+  ex489_STRUCT     ex489 ;
+
+  //Enable voltage client
+  GnbLibPciIndirectRead (
+    MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+    0x6a  | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &ex488.Value,
+    StdHeader
+  );
+
+  ex488.Field.VoltageChangeEn = 0x1;
+
+  GnbLibPciIndirectWrite (
+    MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+    0x6a  | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &ex488.Value,
+    StdHeader
+  );
+
+  ex488.Field.VoltageLevel = VidIndex;
+  ex488.Field.VoltageChangeReq = !ex488.Field.VoltageChangeReq;
+
+  GnbLibPciIndirectWrite (
+    MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+    0x6a  | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &ex488.Value,
+    StdHeader
+    );
+  do {
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      0x6b  | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      &ex489.Value,
+      StdHeader
+    );
+  } while (ex488.Field.VoltageChangeReq != ex489.Field.VoltageChangeAck);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Unhide all ports
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configuration descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieSiliconUnHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
+    0x0,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~BIT6,
+    BIT6,
+    GnbLibGetHeader (Pcie)
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Hide unused ports
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configuration data area
+ * @param[in]  Pcie                Pointer to data area up to 256 byte
+ */
+
+VOID
+PcieSiliconHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0x64_x0C_STRUCT    D0F0x64_x0C;
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  D0F0x64_x0C.Value =  0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Enter\n");
+
+  D0F0x64_x0C.Value =  BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7;
+  WrapperList = PcieConfigGetChildWrapper (Silicon);
+  while (WrapperList != NULL) {
+    PCIe_ENGINE_CONFIG   *EngineList;
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieConfigIsPcieEngine (EngineList)) {
+        if (PcieConfigIsActivePcieEngine (EngineList) && !PcieConfigIsSbPcieEngine (EngineList)) {
+          D0F0x64_x0C.Value &= ~(1 << EngineList->Type.Port.Address.Address.Device);
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    WrapperList = PcieLibGetNextDescriptor (WrapperList);
+  }
+
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
+    D0F0x64_x0C.Value,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~BIT6,
+    0x0,
+    GnbLibGetHeader (Pcie)
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n");
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
new file mode 100644
index 0000000000..22d07a113d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
@@ -0,0 +1,99 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Complex Services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIESILICONSERVICES_H_
+#define _PCIESILICONSERVICES_H_
+
+UINT8
+PcieSiliconGetGen1VoltageIndex (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+PcieSiliconRequestVoltage (
+  IN      UINT8                 VidIndex,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+PcieSiliconUnHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
new file mode 100644
index 0000000000..3c46ef675b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
@@ -0,0 +1,244 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU indirect register read
+   *
+   *  Arg0 - Smu register offset
+   *
+   */
+  Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) {
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
+    // Access 32 bit width
+    Increment (Arg0)
+    // Reverse ReqToggle
+    Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
+    // Assign Address and ReqType = 0
+    Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0)
+
+    procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
+
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU indirect register Write
+   *
+   *  Arg0 - Smu register offset
+   *  Arg1 - Value
+   *  Arg2 - Width, 0 = 16, 1 = 32
+   *
+   */
+  Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) {
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
+    // Get low 16 bit value
+    Store (And (Arg1, 0xFFFF), Local1)
+    // Reverse ReqToggle
+    Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
+    // Assign Address
+    Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0)
+    // ReqType = 1
+    Or (Local0, 0x02000000, Local0)
+    // Assign Low 16 bit value
+    Or (Local0, Local1, Local0)
+
+    procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
+
+    if (LEqual (Arg2, 1)) {
+      // Get high 16 bit value
+      Store (ShiftRight (Arg1, 16), Local1)
+      // Reverse ReqToggle
+      Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
+      // Assign Address
+      Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0)
+      // Assign High 16 bit value
+      Or (Local0, Local1, Local0)
+
+      procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
+    }
+
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU Service request
+   *
+   *  Arg0 - Smu service id
+   *  Arg1 - Flags - Poll Ack = 1, Poll down = 2
+   *
+   */
+  Method (procNbSmuServiceRequest, 2, NotSerialized) {
+    Store ("NbSmuServiceRequest Enter", Debug)
+    Store ("Request id =", Debug)
+    Store (Arg0, Debug)
+
+    Or (ShiftLeft (Arg0, 3), 0x1, Local0)
+    procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
+
+    if (LAnd (Arg1, 1)) {
+      while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
+        Store ("--Wait Ack--", Debug)
+      }
+    }
+    if (LAnd (Arg1, 2)) {
+      while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) {
+        Store ("--Wait Done--", Debug)
+      }
+    }
+    // Clear IRQ register
+    procNbSmuIndirectRegisterWrite (0x3, 0, 1)
+    Store ("NbSmuServiceRequest Exit", Debug)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write RCU register
+   *
+   *  Arg0 - Register Address
+   *  Arg1 - Register Data
+   *
+   */
+  Method (procSmuRcuWrite, 2, NotSerialized) {
+     procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
+     procNbSmuIndirectRegisterWrite (0x5, Arg1, 1)
+
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read RCU register
+   *
+   *  Arg0  - Register Address
+   *  Retval    - RCU register value
+   */
+  Method (procSmuRcuRead, 1, NotSerialized) {
+    procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
+    Store (procNbSmuIndirectRegisterRead (0x5), Local0)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU SRBM Register Read
+   *
+   *  Arg0 - FCR register address
+   *
+   */
+  Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) {
+    //SMUx0B_x8600
+    Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
+    //SMUx0B_x8604
+    Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
+    //SMUx0B_x8608
+    Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
+    //Write SMU RCU
+    procSmuRcuWrite (0x8600, Local0)
+    procSmuRcuWrite (0x8604, Local1)
+    procSmuRcuWrite (0x8608, Local2)
+    // ServiceId
+    if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) {
+      procNbSmuServiceRequest (0xD, 0x3)
+    }
+    if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) {
+      procNbSmuServiceRequest (0xB, 0x3)
+    }
+    return (procSmuRcuRead(0x8650))
+  }
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU SRBM Register Write
+   *
+   *  Arg0 - FCR register address
+   *  Arg1 - Value
+   *
+   */
+  Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) {
+    //SMUx0B_x8600
+    Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
+    //SMUx0B_x8604
+    Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
+    //SMUx0B_x8608
+    Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
+    Or (Local2, ShiftLeft (1, 16), Local2)
+    //Write SMU RCU
+    procSmuRcuWrite (0x8600, Local0)
+    procSmuRcuWrite (0x8604, Local1)
+    procSmuRcuWrite (0x8608, Local2)
+    //Write Data
+    procSmuRcuWrite (0x8650, Arg1)
+    // ServiceId
+    procNbSmuServiceRequest (0xB, 0x3)
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl
new file mode 100644
index 0000000000..14a474d0e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl
@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 61048 $   @e \$Date: 2011-10-31 12:20:41 +0800 (Mon, 31 Oct 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Request VID
+   *
+   *  Arg0 - 1 - GEN1 2 - GEN2
+   *  Arg1 - 0 = do not wait intil voltage is set
+   *         1 = wait until voltage is set
+   */
+  Method (procPcieSetVoltage, 2, Serialized) {
+    Store ("PcieSetVoltage Enter", Debug)
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1)
+    //Enable voltage change
+    Or (Local1, 0x2, Local1)
+    procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
+    //Clear voltage index
+    And (Local1, Not (ShiftLeft (0x3, 3)), Local1)
+
+    if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) {
+      Store (varGen1Vid, Local3)
+    } else {
+      Store (varGen2Vid, Local3)
+    }
+
+    Store (Concatenate ("  Voltage Index:", ToHexString (Local3), Local6), Debug)
+    //Set new voltage index
+    Or (Local1, ShiftLeft (Local3, 3), Local1)
+    //Togle request
+    And (Not (Local1), 0x4, Local2)
+    Or (And (Local1, Not (0x4)), Local2, Local1)
+    procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
+    if (LNotEqual (Arg1, 0)) {
+      while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
+        And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1)
+      }
+    }
+    Store ("PcieSetVoltage Exit", Debug)
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
new file mode 100644
index 0000000000..49cea04a02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe timer access procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbTimerLib.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCIe timer timestamp
+ *
+ *
+ *
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Time stamp value
+ */
+
+UINT32
+PcieTimerGetTimeStamp (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  return GnbLibTimeStamp (GnbLibGetHeader (Pcie));
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
new file mode 100644
index 0000000000..dfdf414f71
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe timer access procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETIMER_H_
+#define _PCIETIMER_H_
+
+UINT32
+PcieTimerGetTimeStamp (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2))
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
new file mode 100644
index 0000000000..0a9c7b3fed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -0,0 +1,804 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 66529 $   @e \$Date: 2012-03-09 08:32:22 -0600 (Fri, 09 Mar 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Cleanup reconfig
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyCleanUpReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062_ConfigXferMode_MASK,
+      1 << D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare for reconfiguration
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyPrepareForReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  UINT8                     CoreId;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        CORE_SPACE (CoreId, 0x11 ),
+        0 ,
+        4 ,
+        0xf,
+        FALSE,
+        Pcie
+        );
+    }
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                 Pcie
+                                 );
+
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
+    D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate mux array index
+ *
+ *
+ *
+ * @param[in, out]  LaneMuxSelectorArrayPtr     Pointer to mux selector array
+ * @param[in]       LaneMuxValue                The value that match to array
+ * @retval          Index                       Index successfully mapped
+ */
+STATIC UINT8
+PcieTopologyLocateMuxIndex (
+  IN OUT   UINT8 *LaneMuxSelectorArrayPtr,
+  IN       UINT8  LaneMuxValue
+  )
+{
+  UINT8  Index;
+  for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) {
+    if (LaneMuxSelectorArrayPtr [Index] ==  LaneMuxValue) {
+      return Index;
+    }
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply lane mux
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieTopologyApplyLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT8               CurrentPhyLane;
+  UINT8               CurrentCoreLane;
+  UINT8               CoreLaneIndex;
+  UINT8               PhyLaneIndex;
+  UINT8               NumberOfPhyLane;
+  UINT8               TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
+  UINT8               RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
+  UINT8               Index;
+  UINT32              TxMaxSelectorValue;
+  UINT32              RxMaxSelectorValue;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n");
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    EngineList = PcieConfigGetChildEngine (Wrapper);
+    LibAmdMemCopy (
+      &TxLaneMuxSelectorArray[0],
+      &LaneMuxSelectorTable[0],
+      sizeof (LaneMuxSelectorTable),
+      GnbLibGetHeader (Pcie)
+      );
+    LibAmdMemCopy (
+      &RxLaneMuxSelectorArray[0],
+      &LaneMuxSelectorTable[0],
+      sizeof (LaneMuxSelectorTable),
+      GnbLibGetHeader (Pcie)
+      );
+    while (EngineList != NULL) {
+      if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
+        CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
+        NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
+        CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
+        if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
+          CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane;
+        }
+        for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) {
+          CoreLaneIndex = (CurrentCoreLane + Index) / 2;
+          PhyLaneIndex = (CurrentPhyLane + Index) / 2;
+
+          if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) {
+            RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex];
+            RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex;
+          }
+          if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) {
+            TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] =  TxLaneMuxSelectorArray [PhyLaneIndex];
+            TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex;
+          }
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    RxMaxSelectorValue = 0;
+    TxMaxSelectorValue = 0;
+    for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) {
+      RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4));
+      TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4));
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS),
+      TxMaxSelectorValue,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS),
+      RxMaxSelectorValue,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Select master PLL
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[out] ConfigChanged       Pointer to boolean indicator that configuration was changed
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieTopologySelectMasterPll (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  UINT16                    MasterLane;
+  UINT16                    MasterHotplugLane;
+  D0F0xE4_WRAP_8013_STRUCT  D0F0xE4_WRAP_8013;
+  D0F0xE4_WRAP_8013_STRUCT  D0F0xE4_WRAP_8013_BASE;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
+  MasterLane = 0xFFFF;
+  MasterHotplugLane = 0xFFFF;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) {
+      if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+        MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList);
+      } else {
+        MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList);
+        if (PcieConfigIsSbPcieEngine (EngineList)) {
+          break;
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+
+  if (MasterLane == 0xffff) {
+    if (MasterHotplugLane != 0xffff) {
+      MasterLane = MasterHotplugLane;
+    } else {
+      MasterLane = 0x0;
+    }
+  }
+
+  D0F0xE4_WRAP_8013.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value;
+  if ( MasterLane <= 3 ) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xA;
+  } else if (MasterLane <= 7) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xB;
+  } else if (MasterLane <= 11) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xC;
+  } else {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1;
+    Wrapper->MasterPll = 0xD;
+  }
+  if (ConfigChanged != NULL) {
+    *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
+    D0F0xE4_WRAP_8013.Value,
+    FALSE,
+    Pcie
+    );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute/clean up reconfiguration
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyExecuteReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  D0F0xE4_WRAP_8060_STRUCT  D0F0xE4_WRAP_8060;
+
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n");
+
+    PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+                                Pcie
+                                );
+
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+      D0F0xE4_WRAP_8060.Value,
+      FALSE,
+      Pcie
+      );
+    do {
+      D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
+                                  Wrapper,
+                                  WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+                                  Pcie
+                                  );
+
+    } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1);
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable lane reversal
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologySetLinkReversal (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n");
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (PcieLibIsPcieEngine (EngineList)) {
+        if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) {
+            PciePortRegisterWriteField (
+              EngineList,
+              0xc1 ,
+              4 ,
+              1 ,
+              0x1,
+              FALSE,
+              Pcie
+              );
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Reduce link width
+ *
+ *
+ * @param[in]  LinkWidth           Link width
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyReduceLinkWidth (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG       *Wrapper;
+  UINT32                    LinkReversed;
+  UINT8                     DeltaLinkWidthBitmap;
+  UINT32                    LanesToDisable;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
+
+  DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
+  LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane +  LinkWidth)));
+
+  PcieTopologyLaneControl (
+    DisableLanes,
+    LanesToDisable,
+    Wrapper,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lanes enable/disable control
+ *
+ * @param[in]   Control             Lane control action
+ * @param[in]   LaneBitMap          Core lanes bitmap
+ * @param[in]   Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyLaneControl (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+    )
+{
+  D0F0xE4_WRAP_8023_STRUCT  D0F0xE4_WRAP_8023;
+  D0F0xE4_WRAP_8023.Value = PcieRegisterRead (
+                            Wrapper,
+                            WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
+                            Pcie
+                            );
+
+  if (Control == EnableLanes) {
+    D0F0xE4_WRAP_8023.Value |= LaneBitMap;
+  } else if (Control == DisableLanes) {
+    D0F0xE4_WRAP_8023.Value &= (~LaneBitMap);
+  }
+  D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1);
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
+    D0F0xE4_WRAP_8023.Value,
+    TRUE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SRBM reset
+ *
+ * @param[in]  SrbmResetEnable     SRBM reset enable flag.
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyInitSrbmReset (
+  IN      BOOLEAN               SrbmResetEnable,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8063_STRUCT  D0F0xE4_WRAP_8063;
+  D0F0xE4_WRAP_8063.Value = PcieRegisterRead (
+                               Wrapper,
+                               WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS),
+                               Pcie
+                               );
+  if (SrbmResetEnable) {
+    D0F0xE4_WRAP_8063.Field.line331  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line332  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line338  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line339  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line340  = 0x1;
+  } else {
+    D0F0xE4_WRAP_8063.Field.line331  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line332  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line338  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line339  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line340  = 0x0;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS),
+    D0F0xE4_WRAP_8063.Value,
+    FALSE,
+    Pcie
+    );
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set core configuration according to PCIe port topology
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[out] ConfigChanged       Pointer to boolean indicator that configuration was changed
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+PcieTopologySetCoreConfig (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                     CoreId;
+  AGESA_STATUS              Status;
+  D0F0xE4_WRAP_0080_STRUCT  D0F0xE4_WRAP_0080;
+
+  Status = AGESA_SUCCESS;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      UINT64  ConfigurationSignature;
+      UINT8   NewConfigurationValue;
+      ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
+      Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
+      if (Status == AGESA_SUCCESS) {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
+          PcieFmDebugGetWrapperNameString (Wrapper),
+          CoreId,
+          PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
+          );
+        D0F0xE4_WRAP_0080.Value = PcieRegisterRead (
+                                    Wrapper,
+                                    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
+                                    Pcie
+                                    );
+        if (ConfigChanged != NULL) {
+          if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) {
+            *ConfigChanged = TRUE;
+          }
+        }
+        D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue;
+        PcieRegisterWrite (
+          Wrapper,
+          WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
+          D0F0xE4_WRAP_0080.Value,
+          FALSE,
+          Pcie
+          );
+      } else {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
+          PcieFmDebugGetWrapperNameString (Wrapper),
+          ((UINT32*)&ConfigurationSignature)[1],
+          ((UINT32*)&ConfigurationSignature)[0]
+          );
+        PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+      }
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Relinquish control to DDI for specific lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PcieSetDdiOwnPhy (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ex502_STRUCT   ex502 ;
+  UINT32                    LaneBitmap;
+
+  if (PcieLibIsDdiWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n");
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    ex502.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, 0x8040 ),
+                                Pcie
+                                );
+    if ((LaneBitmap & BIT0) != 0) {
+      ex502.Field.OwnPhyA = 0x1;
+    }
+    if ((LaneBitmap & BIT4) != 0) {
+      ex502.Field.OwnPhyB = 0x1;
+    }
+    if ((LaneBitmap & BIT8) != 0) {
+      ex502.Field.OwnPhyC = 0x1;
+    }
+    if ((LaneBitmap & BIT12) != 0) {
+      ex502.Field.OwnPhyD = 0x1;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, 0x8040 ),
+      ex502.Value,
+      FALSE,
+      Pcie
+      );
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set TX control for PCIe lanes
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieWrapSetTxS1CtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8025_STRUCT  D0F0xE4_WRAP_8025;
+  UINT32                    LaneBitmap;
+  UINTN                     Index;
+  D0F0xE4_WRAP_8025.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+                              Pcie
+                              );
+  Index = 0;
+  LaneBitmap =  PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
+  while (LaneBitmap != 0) {
+    if ((LaneBitmap & 0xf) != 0) {
+      D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8)));
+      D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8));
+    }
+    LaneBitmap >>= 4;
+    ++Index;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+    D0F0xE4_WRAP_8025.Value,
+    FALSE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set TX control for lane muxes
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieWrapSetTxOffCtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+    0x1f1f1f1f,
+    FALSE,
+    Pcie
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
new file mode 100644
index 0000000000..59c4ffcd94
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETOPOLOGYSERVICES_H_
+#define _PCIETOPOLOGYSERVICES_H_
+
+/// Lane Control
+typedef enum {
+  EnableLanes,              ///< Enable Lanes
+  DisableLanes              ///< Disable Lanes
+} LANE_CONTROL;
+
+VOID
+PcieTopologyCleanUpReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyPrepareForReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PcieTopologySetCoreConfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT  BOOLEAN               *ConfigChanged,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyApplyLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+ );
+
+VOID
+PcieTopologySelectMasterPll (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyExecuteReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologySetLinkReversal (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+
+VOID
+PcieTopologyReduceLinkWidth (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyLaneControl (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyInitSrbmReset (
+  IN      BOOLEAN               SrbmResetEnable,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetDdiOwnPhy (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieWrapSetTxS1CtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieWrapSetTxOffCtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
new file mode 100644
index 0000000000..29dc02473b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -0,0 +1,688 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe utility. Various supporting functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/// Lane type
+typedef enum {
+  LaneTypeCore,         ///< Core Lane
+  LaneTypePhy,          ///< Package Phy Lane
+  LaneTypeNativePhy     ///< Native Phy Lane
+} LANE_TYPE;
+
+/// Lane Property
+typedef enum {
+  LanePropertyConfig,   ///< Configuration
+  LanePropertyActive,   ///< Active
+  LanePropertyAllocated ///< Allocated
+} LANE_PROPERTY;
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct {
+  UINT32               Flags;
+  PCIE_LINK_SPEED_CAP  LinkSpeedCapability;
+} PCIE_GLOBAL_GEN_CAP_WORKSPACE;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link state history from HW state machine
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @param[out]  History             Buffer to save history
+ * @param[in]   Length              Buffer length
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieUtilGetLinkHwStateHistory (
+  IN       PCIe_ENGINE_CONFIG        *Engine,
+     OUT   UINT8                     *History,
+  IN       UINT8                     Length,
+  IN       PCIe_PLATFORM_CONFIG      *Pcie
+  )
+{
+  UINT8   ReadLength;
+  UINT32  LocalHistory [6];
+  UINT16  Index;
+  ASSERT (Length <= 16);
+  ASSERT (Length > 0);
+  if (Length > 6*4) {
+    Length = 6*4;
+  }
+  ReadLength = (Length + 3) / 4;
+  for (Index = 0; Index < ReadLength; Index++) {
+    LocalHistory[Index] = PciePortRegisterRead (
+                            Engine,
+                            DxF0xE4_xA5_ADDRESS + Index,
+                            Pcie
+                            );
+  }
+  LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Search array for specific pattern
+ *
+ *
+ * @param[in]  Buf1           Pointer to source buffer which will be subject of search
+ * @param[in]  Buf1Length     Length of the source buffer
+ * @param[in]  Buf2           Pointer to pattern buffer
+ * @param[in]  Buf2Length     Length of the pattern buffer
+ * @retval     TRUE           Pattern found
+ * @retval     TRUE           Pattern not found
+ */
+
+BOOLEAN
+PcieUtilSearchArray (
+  IN      UINT8                         *Buf1,
+  IN      UINTN                         Buf1Length,
+  IN      UINT8                         *Buf2,
+  IN      UINTN                         Buf2Length
+  )
+{
+  UINT8 *CurrentBuf1Ptr;
+  CurrentBuf1Ptr = Buf1;
+  while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
+    UINT8 *SourceBufPtr;
+    UINT8 *PatternBufPtr;
+    UINTN PatternBufLength;
+    SourceBufPtr = CurrentBuf1Ptr;
+    PatternBufPtr = Buf2;
+    PatternBufLength = Buf2Length;
+    while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
+    if (PatternBufLength == 0) {
+      return TRUE;
+    }
+    CurrentBuf1Ptr++;
+  }
+  return FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link reversed
+ *
+ *
+ * @param[in]  HwLinkState  Check for HW auto link reversal
+ * @param[in]  Engine       Pointer to engine config descriptor
+ * @param[in]  Pcie         Pointer to PCIe config descriptor
+ * @retval                 TRUE if link reversed
+ */
+BOOLEAN
+PcieUtilIsLinkReversed (
+  IN      BOOLEAN               HwLinkState,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 LinkReversal;
+
+  LinkReversal  = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0;
+  if (HwLinkState)  {
+    DxF0xE4_x50_STRUCT  DxF0xE4_x50;
+    DxF0xE4_x50.Value = PciePortRegisterRead (
+                          Engine,
+                          DxF0xE4_x50_ADDRESS,
+                          Pcie
+                          );
+    LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal;
+  }
+  return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link width detected during training
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ * @retval                          Link width
+ */
+UINT8
+PcieUtilGetLinkWidth (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8               LinkWidth;
+  DxF0xE4_xA2_STRUCT  DxF0xE4_xA2;
+  DxF0xE4_xA2.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xA2_ADDRESS,
+                        Pcie
+                        );
+  switch (DxF0xE4_xA2.Field.LcLinkWidthRd) {
+  case 0x6:
+    LinkWidth = 16;
+    break;
+  case 0x5:
+    LinkWidth = 12;
+    break;
+  case 0x4:
+    LinkWidth = 8;
+    break;
+  case 0x3:
+    LinkWidth = 4;
+    break;
+  case 0x2:
+    LinkWidth = 2;
+    break;
+  case 0x1:
+    LinkWidth = 1;
+    break;
+  default:
+    LinkWidth = 0;
+  }
+  return LinkWidth;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of PCIE engine lane of requested type
+ *
+ *
+ * @param[in]   LaneType            Lane type
+ * @param[in]   LaneProperty        Lane Property
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetPcieEngineLaneBitMap (
+  IN      LANE_TYPE                      LaneType,
+  IN      LANE_PROPERTY                  LaneProperty,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32                LaneBitmap;
+  UINT8                 Width;
+  UINT16                Offset;
+  UINT16                LoPhylane;
+  UINT16                HiPhylane;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+
+  Width = 0;
+  Offset = 0;
+  LaneBitmap = 0;
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+
+  if (PcieConfigIsPcieEngine (Engine)) {
+    if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) {
+      Width = PcieConfigGetNumberOfCoreLane (Engine);
+      Offset = Engine->Type.Port.StartCoreLane;
+      LaneBitmap = ((1 << Width) - 1) << Offset;
+    } else if (PcieConfigIsEngineAllocated (Engine)) {
+      if (LaneType == LaneTypeNativePhy) {
+        LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
+        LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
+      } else {
+        if (LaneType == LaneTypeCore) {
+          if (LaneProperty == LanePropertyActive) {
+            Width = PcieUtilGetLinkWidth (Engine, Pcie);
+            Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
+          } else if (LaneProperty == LanePropertyAllocated) {
+            Width = PcieConfigGetNumberOfPhyLane (Engine);
+            Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
+          }
+        }
+        if (LaneType == LaneTypePhy) {
+          LoPhylane = PcieLibGetLoPhyLane (Engine);
+          HiPhylane = PcieLibGetHiPhyLane (Engine);
+          if (LaneProperty == LanePropertyActive) {
+            Width = PcieUtilGetLinkWidth (Engine, Pcie);
+            Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+          } else if (LaneProperty == LanePropertyAllocated) {
+            Width = PcieConfigGetNumberOfPhyLane (Engine);
+            Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+          }
+        }
+        LaneBitmap = ((1 << Width) - 1) << Offset;
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of PCIE engine lane of requested type
+ *
+ *
+ * @param[in]   LaneType            Lane type
+ * @param[in]   LaneProperty        Lane Property
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetDdiEngineLaneBitMap (
+  IN      LANE_TYPE                      LaneType,
+  IN      LANE_PROPERTY                  LaneProperty,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitmap;
+  UINT8   Width;
+  UINT16  Offset;
+  Width = 0;
+  Offset = 0;
+  LaneBitmap = 0;
+  if (PcieConfigIsDdiEngine (Engine)) {
+    if (PcieConfigIsEngineAllocated (Engine)) {
+      if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) {
+        Width = PcieConfigGetNumberOfPhyLane (Engine);
+        Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+        LaneBitmap = ((1 << Width) - 1) << Offset;
+      }
+      if (LaneType == LaneTypeNativePhy) {
+        LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
+        LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get  bitmap of engine lane of requested type
+ *
+ *
+ * @param[in]   IncludeLaneType     Include Lane type
+ * @param[in]   ExcludeLaneType     Exclude Lane type
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+UINT32
+PcieUtilGetEngineLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitmap;
+  LaneBitmap = 0;
+  if (IncludeLaneType & LANE_TYPE_PCIE_LANES) {
+    if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) {
+      if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
+        LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+      } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+        } else {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine);
+        }
+      }
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_PHY) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) {
+      if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
+        LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+      } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+        } else {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
+        }
+      }
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+  }
+  if (IncludeLaneType & LANE_TYPE_DDI_LANES) {
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
+    }
+  }
+  if (ExcludeLaneType != 0) {
+    LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine));
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of phy lane confugred for master pll
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @retval     Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetMasterPllLaneBitMap (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  if (Wrapper->MasterPll != 0) {
+    return 0xf << (Wrapper->MasterPll - 0xA) * 4;
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of Wrapper lane of requested type
+ *
+ *
+ * @param[in]  IncludeLaneType Include Lane type
+ * @param[in]  ExcludeLaneType Exclude Lane type
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @retval     Lane bitmap
+ */
+
+UINT32
+PcieUtilGetWrapperLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  UINT32                    LaneBitmap;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  LaneBitmap = 0;
+  if ((IncludeLaneType | ExcludeLaneType) != 0) {
+    if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) {
+      LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1;
+      if (ExcludeLaneType != 0) {
+        LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper));
+      }
+    } else {
+      while (EngineList != NULL) {
+        LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList);
+        EngineList = PcieLibGetNextDescriptor (EngineList);
+      }
+      if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
+        LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper);
+      }
+      if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
+        LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper));
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program port register table
+ *
+ *
+ *
+ * @param[in]  Table           Pointer to table
+ * @param[in]  Length          number of entries
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  S3Save          Save for S3 flag
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PciePortProgramRegisterTable (
+  IN      PCIE_PORT_REGISTER_ENTRY    *Table,
+  IN      UINTN                       Length,
+  IN      PCIe_ENGINE_CONFIG          *Engine,
+  IN      BOOLEAN                     S3Save,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  UINTN   Index;
+  UINT32  Value;
+  for (Index = 0; Index < Length; Index++) {
+    Value = PciePortRegisterRead (
+              Engine,
+              Table[Index].Reg,
+              Pcie
+              );
+    Value &= (~Table[Index].Mask);
+    Value |= Table[Index].Data;
+    PciePortRegisterWrite (
+      Engine,
+      Table[Index].Reg,
+      Value,
+      S3Save,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lock registers
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PcieLockRegisters (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT8   CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
+        D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
+        D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
+        0x1,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training state handling
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Indicate if engine in non final state
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieUtilGlobalGenCapabilityCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability;
+  PCIE_LINK_SPEED_CAP           LinkSpeedCapability;
+  PCIE_HOTPLUG_TYPE             HotPlugType;
+  UINT32                        Flags;
+
+  Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS;
+  GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer;
+  LinkSpeedCapability = PcieGen1;
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS;
+  }
+  HotPlugType = Engine->Type.Port.PortData.LinkHotplug;
+  if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) {
+    Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS;
+  }
+  if ((GlobalGenCapability->Flags & Flags) != 0) {
+    ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0);
+    LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine);
+    if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) {
+      GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine global GEN capability
+ *
+ *
+ * @param[in]  Flags           global GEN capability flags
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+PCIE_LINK_SPEED_CAP
+PcieUtilGlobalGenCapability (
+  IN      UINT32                         Flags,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP             GlobalCapability;
+  PCIE_GLOBAL_GEN_CAP_WORKSPACE   GlobalGenCap;
+
+  GlobalGenCap.LinkSpeedCapability = PcieGen1;
+  GlobalGenCap.Flags = Flags;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieUtilGlobalGenCapabilityCallback,
+    &GlobalGenCap,
+    Pcie
+    );
+
+  GlobalCapability = GlobalGenCap.LinkSpeedCapability;
+
+  return GlobalCapability;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
new file mode 100644
index 0000000000..207aeb6efe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
@@ -0,0 +1,158 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe utility. Various supporting functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEUTILLIB_H_
+#define _PCIEUTILLIB_H_
+
+/// Core lanes
+typedef enum {
+  AllCoreLanes,           ///< All core lanes
+  AllocatedCoreLanes,     ///< Allocated core lanes
+  ActiveCoreLanes,        ///< Active core lanes
+  HotplugCoreLanes,       ///< Hot plug core lanes
+  SbCoreLanes,            ///< South bridge core lanes
+} CORE_LANES;
+
+/// DDI lanes
+typedef enum {
+  DdiAllLanes,            ///< All DDI Lanes
+  DdiActiveLanes          ///< Active DDI Lanes
+} DDI_LANES;
+
+BOOLEAN
+PcieUtilSearchArray (
+  IN      UINT8                         *Buf1,
+  IN      UINTN                         Buf1Length,
+  IN      UINT8                         *Buf2,
+  IN      UINTN                         Buf2Length
+  );
+
+VOID
+PcieUtilGetLinkHwStateHistory (
+  IN       PCIe_ENGINE_CONFIG            *Engine,
+     OUT   UINT8                         *History,
+  IN       UINT8                         Length,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+
+BOOLEAN
+PcieUtilIsLinkReversed (
+  IN      BOOLEAN                        HwLinkState,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+
+UINT8
+PcieUtilGetLinkWidth (
+  IN      PCIe_ENGINE_CONFIG            *Engine,
+  IN      PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+
+UINT32
+PcieUtilGetEngineLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+UINT32
+PcieUtilGetWrapperLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  );
+
+VOID
+PciePortProgramRegisterTable (
+  IN      PCIE_PORT_REGISTER_ENTRY       *Table,
+  IN      UINTN                          Length,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      BOOLEAN                        S3Save,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+VOID
+PcieLockRegisters (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+PCIE_LINK_SPEED_CAP
+PcieUtilGlobalGenCapability (
+  IN      UINT32                         Flags,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
new file mode 100644
index 0000000000..a76bc5e0f5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -0,0 +1,324 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register Value
+ */
+UINT32
+PcieRegisterRead (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Silicon     Pointer to silicon descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register Value
+ */
+
+UINT32
+PcieSiliconRegisterRead (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32              Value;
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]   Wrapper     Pointer to wrapper descriptor
+ * @param[in]   Address     Register address
+ * @param[in]   Value       New register value
+ * @param[in]   S3Save      Save register for S3 (True/False)
+ * @param[in]   Pcie        Pointer to global PCIe configuration
+ */
+VOID
+PcieRegisterWrite (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  PcieSiliconRegisterWrite (
+     PcieConfigGetParentSilicon (Wrapper),
+     Address,
+     Value,
+     S3Save,
+     Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]   Silicon     Pointer to silicon descriptor
+ * @param[in]   Address     Register address
+ * @param[in]   Value       New register value
+ * @param[in]   S3Save      Save register for S3 (True/False)
+ * @param[in]   Pcie        Pointer to global PCIe configuration
+ */
+VOID
+PcieSiliconRegisterWrite (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, "    *WR %s (%d:%d:%d):0x%08x = 0x%08x\n",
+    PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)),
+    Silicon->Address.Address.Bus,
+    Silicon->Address.Address.Device,
+    Silicon->Address.Address.Function,
+    Address,
+    Value
+    );
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register field value
+ */
+
+UINT32
+PcieRegisterReadField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PcieRegisterRead (Wrapper, Address, Pcie);
+  Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth));
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Value       Value to write
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+
+VOID
+PcieRegisterWriteField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  TempValue;
+  UINT32  Mask;
+  TempValue = PcieRegisterRead (Wrapper, Address, Pcie);
+  Mask = (~(0xFFFFFFFF << FieldWidth));
+  Value &= Mask;
+  TempValue &= (~(Mask << FieldOffset));
+  PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PcieRegisterRMW (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieSiliconRegisterRMW (
+    PcieConfigGetParentSilicon (Wrapper),
+    Address,
+    AndMask,
+    OrMask,
+    S3Save,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Silicon     Pointer to silicon descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PcieSiliconRegisterRMW (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PcieSiliconRegisterRead (Silicon, Address, Pcie);
+  Value = (Value & (~AndMask)) | OrMask;
+  PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
new file mode 100644
index 0000000000..c0e4e2ff60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
@@ -0,0 +1,154 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEWRAPPERREGACC_H_
+#define _PCIEWRAPPERREGACC_H_
+
+//#define WRAP_SPACE(w, x)   (0x01300000ul | (w << 16) | (x))
+//#define CORE_SPACE(c, x)   (0x00010000ul | (c << 24) | (x))
+//#define PHY_SPACE(w, p, x) (0x00200000ul | ((p + 1) << 24) | (w << 16) | (x))
+//#define PIF_SPACE(w, p, x) (0x00100000ul | ((p + 1) << 24) | (w << 16) | (x))
+#define IMP_SPACE(x) (0x01080000ul | (x))
+
+UINT32
+PcieRegisterRead (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterWrite (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieRegisterReadField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterWriteField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterRMW (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieSiliconRegisterRead (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconRegisterWrite (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconRegisterRMW (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h
new file mode 100644
index 0000000000..6b156fe300
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h
@@ -0,0 +1,79 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Init Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIEINITLIBV4_H_
+#define _GNBPCIEINITLIBV4_H_
+
+#include "PcieWrapperServicesV4.h"
+#include "PciePowerMgmtV4.h"
+#include "PciePortServicesV4.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
new file mode 100644
index 0000000000..fe5430672e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
@@ -0,0 +1,322 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Configure Max Payload
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision:
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "PcieMaxPayloadV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEMAXPAYLOADV4_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  UINT8                   MaxPayload;
+} PCIE_MAX_PAYLOAD_DATA;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+SCAN_STATUS
+PcieGetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+SCAN_STATUS
+PcieSetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+AGESA_STATUS
+PciePayloadBlackListFeature (
+  IN       PCI_ADDR               Device,
+  IN       UINT8                  *MaxPayload,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine maximum payload size for PCIe segment
+ *
+ *  Scan through all link in segment to determine maximum payload by EPs.
+ *
+ * @param[in]   DownstreamPort    PCI address of PCIe port
+ * @param[in]   StdHeader         Standard configuration header
+ *
+ */
+
+VOID
+PcieSetMaxPayload (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_MAX_PAYLOAD_DATA  PcieMaxPayloadData;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayload for Device = %d:%d:%d\n",
+    DownstreamPort.Address.Bus,
+    DownstreamPort.Address.Device,
+    DownstreamPort.Address.Function
+    );
+  PcieMaxPayloadData.MaxPayload = MAX_PAYLOAD;
+  PcieMaxPayloadData.ScanData.StdHeader = StdHeader;
+  PcieMaxPayloadData.ScanData.GnbScanCallback = PcieGetMaxPayloadCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData);
+  PcieMaxPayloadData.ScanData.GnbScanCallback = PcieSetMaxPayloadCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayloadExit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieGetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_MAX_PAYLOAD_DATA   *PcieMaxPayloadData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT32                  Value;
+  UINT8                   PcieCapPtr;
+  UINT8                   DeviceMaxPayload;
+
+  PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieGetMaxPayloadCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (
+      Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER),
+      AccessWidth32,
+      &Value,
+      ScanData->StdHeader
+    );
+    DeviceMaxPayload = (UINT8) (Value & 0x7);
+    PciePayloadBlackListFeature (Device, &DeviceMaxPayload, ScanData->StdHeader);
+    IDS_HDT_CONSOLE (GNB_TRACE, "  Found DeviceMaxPayload as %d (Value = %x\n", DeviceMaxPayload, Value);
+    if (DeviceMaxPayload < PcieMaxPayloadData->MaxPayload) {
+      PcieMaxPayloadData->MaxPayload = DeviceMaxPayload;
+    }
+  }
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure the Max Payload setting to all devices in the PCIe Segment
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieSetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_MAX_PAYLOAD_DATA   *PcieMaxPayloadData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT8                   PcieCapPtr;
+
+  PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayloadCallback for Device = %d:%d:%d to %d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function,
+    PcieMaxPayloadData->MaxPayload
+    );
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CTRL_REGISTER),
+      AccessWidth32,
+      ~(UINT32) (0x7 << 5),
+      ((UINT32)PcieMaxPayloadData->MaxPayload << 5),
+      ScanData->StdHeader
+    );
+  }
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
+UINT16  PayloadBlacklistDeviceTable[] = {
+  0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Max_Payload_Size Black List
+ *
+ *
+ *
+ * @param[in] Device              PCI_ADDR of PCIe Device to evaluate
+ * @param[in] MaxPayload          Pointer to Max_Payload_Size value
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PciePayloadBlackListFeature (
+  IN       PCI_ADDR               Device,
+  IN       UINT8                  *MaxPayload,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  TargetDeviceId;
+  UINTN   i;
+  UINT32  DeviceId;
+  UINT32  VendorId;
+
+  GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader);
+  for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    VendorId = PayloadBlacklistDeviceTable[i];
+    DeviceId = PayloadBlacklistDeviceTable[i + 1];
+    if (VendorId == (UINT16)TargetDeviceId) {
+      if (DeviceId == 0xFFFF || DeviceId == (TargetDeviceId >> 16)) {
+        *MaxPayload = (UINT8) PayloadBlacklistDeviceTable[i + 2];
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h
new file mode 100644
index 0000000000..470235e4cc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Configure Max Payload
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEMAXPAYLOADV4_H_
+#define _PCIEMAXPAYLOADV4_H_
+
+VOID
+PcieSetMaxPayload (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
new file mode 100644
index 0000000000..d90d6cdce7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
@@ -0,0 +1,215 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "PciePortServicesV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkSpeedCapV4 (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  DxF0xE4_xA4_STRUCT  DxF0xE4_xA4;
+  DxF0xE4_xC0_STRUCT  DxF0xE4_xC0;
+  DxF0x88_STRUCT      DxF0x88;
+  GnbLibPciRead (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+  DxF0xE4_xA4.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xA4_ADDRESS,
+                        Pcie
+                        );
+  DxF0xE4_xC0.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xC0_ADDRESS,
+                        Pcie
+                        );
+
+  switch (LinkSpeedCapability) {
+  case PcieGen2:
+    DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
+    DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
+    DxF0x88.Field.TargetLinkSpeed = 0x2;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
+    break;
+  case PcieGen1:
+    DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0;
+    DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
+    DxF0x88.Field.TargetLinkSpeed = 0x1;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+  PciePortRegisterWrite (
+    Engine,
+    DxF0xE4_xA4_ADDRESS,
+    DxF0xE4_xA4.Value,
+    FALSE,
+    Pcie
+    );
+  PciePortRegisterWrite (
+    Engine,
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0.Value,
+    FALSE,
+    Pcie
+    );
+  GnbLibPciWrite (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable passing TLP prefix to IOMMU if IOMMU enabled
+ *
+ *
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieInitPortForIommuV4 (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterRMW (
+    Engine,
+    DxF0xE4_xC1_ADDRESS,
+    DxF0xE4_xC1_StrapE2EPrefixEn_MASK | DxF0xE4_xC1_StrapExtendedFmtSupported_MASK,
+    (1 << DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET),
+    TRUE,
+    Pcie
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
new file mode 100644
index 0000000000..1420e4712b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTSERVICESV4_H_
+#define _PCIEPORTSERVICESV4_H_
+
+
+VOID
+PcieSetLinkSpeedCapV4 (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieInitPortForIommuV4 (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
new file mode 100644
index 0000000000..30a901191f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
@@ -0,0 +1,328 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clock gating
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrClockGatingV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  D0F0xE4_WRAP_8011_STRUCT  D0F0xE4_WRAP_8011;
+  D0F0xE4_WRAP_8012_STRUCT  D0F0xE4_WRAP_8012;
+  D0F0xE4_WRAP_8014_STRUCT  D0F0xE4_WRAP_8014;
+  D0F0xE4_WRAP_8015_STRUCT  D0F0xE4_WRAP_8015;
+  D0F0xE4_WRAP_8016_STRUCT  D0F0xE4_WRAP_8016;
+  UINT8                     CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Enter\n");
+  D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+                              Pcie
+                              );
+
+  D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+                              Pcie
+                              );
+
+  D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
+                              Pcie
+                              );
+
+  if (Wrapper->Features.ClkGating == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
+
+
+    D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
+    D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
+    D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
+
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
+
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
+    D0F0xE4_WRAP_8015.Field.line477  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line478  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line479  = 0x3;
+    D0F0xE4_WRAP_8015.Field.line480  = 0x1;
+    D0F0xE4_WRAP_8015.Field.line482  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line483  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line484  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line485  = 0x1;
+    D0F0xE4_WRAP_8015.Field.line486  = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigCEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigDEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
+  }
+  if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+    D0F0xE4_WRAP_8014.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+    D0F0xE4_WRAP_8015.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+    D0F0xE4_WRAP_8012.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
+    D0F0xE4_WRAP_8011.Value,
+    TRUE,
+    Pcie
+    );
+  for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
+      D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
+      D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
+      0xf,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Wrapper->Features.LclkGating == 0x1) {
+    D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
+    D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
+      D0F0xE4_WRAP_8016.Value,
+      TRUE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down DDI plls
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrPowerDownDdiPllsV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Enter\n");
+  if (PcieConfigIsDdiWrapper (Wrapper) && !PcieConfigIsPcieWrapper (Wrapper)) {
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS),
+      D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK,
+      0x1 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET,
+      FALSE,
+      Pcie
+      );
+    PciePollPifForCompeletion (Wrapper, Pcie);
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+      D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK,
+      (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET),
+      FALSE,
+      Pcie
+      );
+    PciePollPifForCompeletion (Wrapper, Pcie);
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+      D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK,
+      (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET),
+      FALSE,
+      Pcie
+      );
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS),
+      D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK,
+      0x0 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h
new file mode 100644
index 0000000000..447571edbb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERSAVINGFEATURESV4_H_
+#define _PCIEPOWERSAVINGFEATURESV4_H_
+
+VOID
+PciePwrClockGatingV4 (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePwrPowerDownDdiPllsV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl
new file mode 100644
index 0000000000..d7ea99ffbc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 55681 $   @e \$Date: 2011-06-24 14:34:00 -0700 (Fri, 24 Jun 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+
+/*----------------------------------------------------------------------------------------*/
+  /**
+   *  Get current link speed
+   *
+   *  Arg0 - Port Index
+   *
+   */
+
+
+  Method (procPciePortGetCurrentLinkSpeed, 1, NotSerialized) {
+    Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcLinkCtrlLocal1)
+    ShiftRight (varLcLinkCtrlLocal1, 13, varCurrenLinkSpeedLocal2)
+    And (varCurrenLinkSpeedLocal2, 0x3, varCurrenLinkSpeedLocal2);
+    Increment (varCurrenLinkSpeedLocal2)
+    return (varCurrenLinkSpeedLocal2)
+  }
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
new file mode 100644
index 0000000000..5486edbc97
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
@@ -0,0 +1,105 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU Service request
+   *
+   *  Arg0 - Smu service id
+   *
+   */
+  Method (procNbSmuServiceRequest, 1, NotSerialized) {
+    Store ("NbSmuServiceRequest Enter", Debug)
+    Store (Concatenate ("  Request id = ", ToHexString (Arg0), Local6), Debug)
+
+    while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x2), 0x2)) {
+      Store ("--Wait Init Done--", Debug)
+    }
+
+    Store (procIndirectRegisterRead (0x0, 0xB8, 0xE0003000), Local0)
+    // Reverse IntToggle[0], clean ServiceIndex[16:1]
+    Or (And (Local0, 0xFFFE0000), And (Not (And (Local0, 0x00000001)), 0x1), Local0)
+    // Assign ID
+    Or (Local0, ShiftLeft (Arg0, 1), Local0)
+    procIndirectRegisterWrite (0x0, 0xB8, 0xE0003000, Local0)
+
+    while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x1), 0x1)) {
+      Store ("--Wait Init Ack--", Debug)
+    }
+
+    while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x2), 0x2)) {
+      Store ("--Wait Init Done--", Debug)
+    }
+
+    Store ("NbSmuServiceRequest Exit", Debug)
+  }
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl
new file mode 100644
index 0000000000..b91ea6c028
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Request VID
+   *
+   *  Arg0 - 1 - GEN1 2 - GEN2
+   *  Arg1 - 0 = do not wait intil voltage is set
+   *         1 = wait until voltage is set
+   */
+  Method (procPcieSetVoltage, 2, Serialized) {
+    Store ("PcieSetVoltage Enter", Debug)
+    // Get real vid by index
+    if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) {
+      Store (DeRefOf (Index (varSclkVid, varGen1Vid)), local3)
+    } else {
+      Store (DeRefOf (Index (varSclkVid, varGen2Vid)), local3)
+    }
+
+    // GMMx63C/GMMx640 -- CG_Reg = reg - 0x600
+    // Store REQ in local2
+    And (procIndirectRegisterRead (0x0, 0xB8, 0xE000203C), 0x4, Local2)
+    // Store ACK in local1
+    And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1)
+    // Compare REQ with ACK
+    while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
+      And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1)
+    }
+    Store (procIndirectRegisterRead (0x0, 0xB8, 0xE000203C), Local1)
+    //Enable voltage change
+    if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) {
+      And (Local1, 0xFFFFFFFD, Local1)
+    } else {
+      Or (Local1, 0x2, Local1)
+    }
+    procIndirectRegisterWrite (0x0, 0xB8, 0xE000203C, Local1)
+    //Clear voltage index
+    And (Local1, Not (ShiftLeft (0xFF, 8)), Local1)
+
+    Store (Concatenate ("  Voltage Index:", ToHexString (local3), Local6), Debug)
+    //Set new voltage index
+    Or (Local1, ShiftLeft (local3, 8), Local1)
+    //Togle request
+    And (Not (Local1), 0x4, Local2)
+    Or (And (Local1, Not (0x4)), Local2, Local1)
+    procIndirectRegisterWrite (0x0, 0xB8, 0xE000203C, Local1)
+    if (LNotEqual (Arg1, 0)) {
+      while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
+        And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1)
+      }
+    }
+    Store ("PcieSetVoltage Exit", Debug)
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
new file mode 100644
index 0000000000..15cabc76d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
@@ -0,0 +1,277 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe wrapper services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "PcieWrapperServicesV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Relinquish control to DDI for specific lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PcieSetDdiOwnPhyV4 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+
+  UINT32  LaneBitmap;
+  UINT8   Slice;
+  if (PcieLibIsDdiWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n");
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    for (Slice = 0; Slice < 4; Slice++) {
+      if ((LaneBitmap & (1 << (Slice * 4))) != 0) {
+        PcieRegisterRMW (
+          Wrapper,
+          WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice),
+          D0F0xE4_WRAP_8040_OwnSlice_MASK,
+          1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET,
+          FALSE,
+          Pcie
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute/clean up reconfiguration
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyExecuteReconfigV4 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  PCIe_SILICON_CONFIG       *Silicon;
+
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n");
+
+    PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+
+    Silicon = PcieConfigGetParentSilicon (Wrapper);
+
+    GnbLibPciIndirectRMW (
+      Silicon->Address.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_x1F630_ADDRESS,
+      AccessWidth32,
+      (UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK,
+      Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+
+    GnbSmuServiceRequestV4 (
+      Silicon->Address,
+      SMC_MSG_RECONFIGURE,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SSID
+ *
+ *
+ * @param[in]  Ssid            SSID
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PcieSetSsidV4 (
+  IN       UINT32                        Ssid,
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0046_ADDRESS),
+      Ssid,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable lane reversal
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologySetLinkReversalV4 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n");
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (PcieLibIsPcieEngine (EngineList)) {
+        if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) {
+            PciePortRegisterWriteField (
+              EngineList,
+              DxF0xE4_xC1_ADDRESS,
+              DxF0xE4_xC1_StrapReverseLanes_OFFSET,
+              DxF0xE4_xC1_StrapReverseLanes_WIDTH,
+              0x1,
+              FALSE,
+              Pcie
+              );
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
new file mode 100644
index 0000000000..533f80b906
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe wrapper services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEWRAPPERSERVICESV4_H_
+#define _PCIEWRAPPERSERVICESV4_H_
+
+
+VOID
+PcieSetDdiOwnPhyV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+
+VOID
+PcieTopologyExecuteReconfigV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieSetSsidV4 (
+  IN       UINT32                 Ssid,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieTopologySetLinkReversalV4 (
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h
new file mode 100644
index 0000000000..71d852fbb3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe training library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIETRAININGV1_H_
+#define _GNBPCIETRAININGV1_H_
+
+#include "PcieTraining.h"
+#include "PcieWorkarounds.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
new file mode 100644
index 0000000000..8f7cbdaaf2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
@@ -0,0 +1,907 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  PCIe link training
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "GeneralServices.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "PcieWorkarounds.h"
+#include  "PcieTraining.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+PcieSetResetStateOnEngines (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingCheckResetDuration (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingDeassertReset (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingBrokenLine (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingGen2Fail (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+GNB_DEBUG_CODE (
+VOID
+STATIC
+PcieTrainingDebugDumpPortState (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+);
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set link State
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  State               State to set
+ * @param[in]  UpdateTimeStamp     Update time stamp
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieTrainingSetPortState (
+  IN      PCIe_ENGINE_CONFIG        *CurrentEngine,
+  IN      PCIE_LINK_TRAINING_STATE  State,
+  IN      BOOLEAN                   UpdateTimeStamp,
+  IN      PCIe_PLATFORM_CONFIG      *Pcie
+  )
+{
+  UINT32 TimeStamp;
+  CurrentEngine->Type.Port.State = (UINT8) State;
+  if (UpdateTimeStamp) {
+    TimeStamp = PcieTimerGetTimeStamp (Pcie);
+    CurrentEngine->Type.Port.TimeStamp = TimeStamp;
+  }
+  GNB_DEBUG_CODE (
+    PcieTrainingDebugDumpPortState (CurrentEngine, Pcie)
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set state for all engines connected to same reset ID
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Pointer to Reset Id
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetResetStateOnEngines (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 ResetId;
+  ResetId = *(UINT8 *)Buffer;
+  if (Engine->Type.Port.PortData.ResetId == ResetId && !PcieConfigIsSbPcieEngine (Engine)) {
+    PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie);
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | DxF0x68_ADDRESS,
+      AccessWidth32,
+      (UINT32) ~DxF0x68_LinkDis_MASK,
+      1 << DxF0x68_LinkDis_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Assert GPIO port reset.
+ *
+ *  Transition to LinkStateResetDuration state
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingAssertReset (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_SLOT_RESET_INFO ResetInfo;
+  ResetInfo.ResetControl = AssertSlotReset;
+  ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
+  LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieSetResetStateOnEngines,
+    (VOID *)&CurrentEngine->Type.Port.PortData.ResetId,
+    Pcie
+    );
+  AgesaPcieSlotResetControl (0, &ResetInfo);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check for reset duration
+ *
+ *  Transition to LinkStateResetDuration state
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieTrainingCheckResetDuration (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 TimeStamp;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Deassert GPIO port reset.
+ *
+ *  Transition to LinkStateResetDuration state
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Platform configuration
+ *
+ */
+VOID
+PcieTrainingDeassertReset (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_SLOT_RESET_INFO ResetInfo;
+  ResetInfo.ResetControl = DeassertSlotReset;
+  ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
+  LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
+  AgesaPcieSlotResetControl (0, &ResetInfo);
+  GnbLibPciRMW (
+    CurrentEngine->Type.Port.Address.AddressValue | DxF0x68_ADDRESS,
+    AccessWidth32,
+    (UINT32) ~DxF0x68_LinkDis_MASK,
+    0 << DxF0x68_LinkDis_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check for after reset deassertion timeout
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCheckResetTimeout (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 TimeStamp;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Release training
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingRelease (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   LinkTrainingState;
+  PcieRegisterWriteField (
+    PcieConfigGetParentWrapper (CurrentEngine),
+    WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
+    D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
+    D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
+    0,
+    FALSE,
+    Pcie
+    );
+  if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    LinkTrainingState = LinkStateCompliance;
+  } else {
+    LinkTrainingState = LinkStateDetectPresence;
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Detect presence of any EP on the link
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingDetectPresence (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   LinkHwStateHistory[4];
+  UINT32  TimeStamp;
+  PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie);
+  if (LinkHwStateHistory[0] > 4) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
+    return;
+  }
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
+  }
+}
+
+UINT8 FailPattern1 [] = {0x2a, 0x6};
+UINT8 FailPattern2 [] = {0x2a, 0x9};
+UINT8 FailPattern3 [] = {0x2a, 0xb};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Detect Link State
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingDetectLinkState (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   LinkHwStateHistory[16];
+  UINT32  TimeStamp;
+  UINT8   LinkTrainingState;
+  PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie);
+  if (LinkHwStateHistory[0] == 0x10) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie);
+    return;
+  };
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) {
+    LinkTrainingState = LinkStateTrainingFail;
+    PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie);
+    if (LinkHwStateHistory[0] == 0x7) {
+      LinkTrainingState = LinkStateCompliance;
+    } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) {
+      LinkTrainingState = LinkStateBrokenLane;
+    } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) {
+      LinkTrainingState = LinkStateGen2Fail;
+    } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern3, sizeof (FailPattern3))) {
+      LinkTrainingState = LinkStateGen2Fail;
+    }
+    PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Broken Lane
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieTrainingBrokenLine (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 CurrentLinkWidth;
+  UINT8 LinkTrainingState;
+  CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie);
+  if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) {
+    CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY;
+    PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie);
+    LinkTrainingState = LinkStateResetAssert;
+    PutEventLog (
+      AGESA_WARNING,
+      GNB_EVENT_BROKEN_LANE_RECOVERY,
+      CurrentEngine->Type.Port.Address.AddressValue,
+      0,
+      0,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+  } else {
+    LinkTrainingState = LinkStateGen2Fail;
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link fail because device does not support Gen2
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieTrainingGen2Fail (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkTrainingState;
+  if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) {
+    PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0);
+    CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1;
+    PcieLinkSafeMode (CurrentEngine, Pcie);
+    LinkTrainingState = LinkStateResetAssert;
+    PutEventLog (
+      AGESA_WARNING,
+      GNB_EVENT_BROKEN_LANE_RECOVERY,
+      CurrentEngine->Type.Port.Address.AddressValue,
+      0,
+      0,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+  } else {
+    LinkTrainingState = LinkStateTrainingFail;
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Link in L0
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieCheckLinkL0 (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link fail because device does not support Gen X
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCheckVcoNegotiation (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32          TimeStamp;
+  DxF0x128_STRUCT DxF0x128;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie));
+  if (DxF0x128.Field.VcNegotiationPending == 0) {
+    UINT16  NumberOfPhyLane;
+    NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine);
+    if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) {
+      // Limit exposure of workaround to x8 and x16 port.
+      PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie);
+    } else {
+      PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie);
+    }
+    return;
+  }
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if for GFX workaround condition
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingGfxWorkaround (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32                TimeStamp;
+  GFX_WORKAROUND_STATUS GfxWorkaroundStatus;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+
+  GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie));
+  switch (GfxWorkaroundStatus) {
+  case GFX_WORKAROUND_DEVICE_NOT_READY:
+    if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= (3 * 1000000)) {
+      PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie);
+    }
+    break;
+  case GFX_WORKAROUND_SUCCESS:
+    PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie);
+    break;
+  case GFX_WORKAROUND_RESET_DEVICE:
+    if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) {
+      CurrentEngine->Type.Port.GfxWrkRetryCount++;
+      PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie);
+    } else {
+      PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie);
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Retrain link
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingRetrainLink (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterWriteField (
+    CurrentEngine,
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcReconfigNow_OFFSET,
+    DxF0xE4_xA2_LcReconfigNow_WIDTH,
+    1,
+    FALSE,
+    Pcie
+    );
+  PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training fail on this port
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingFail (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0);
+  PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Links training success
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingSuccess (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0);
+  PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Links in compliance
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCompliance (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieConfigUpdatePortStatus (CurrentEngine,  INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0);
+  PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCie EP not present
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingNotPresent (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) {
+  } else {
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (CurrentEngine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
+      D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
+      D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
+      1,
+      FALSE,
+      Pcie
+      );
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Final state. Port training completed.
+ *
+ * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCompleted (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training state handling
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Indicate if engine in non final state
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingPortCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  BOOLEAN *TrainingComplete;
+  TrainingComplete = (BOOLEAN *) Buffer;
+  if (Engine->Type.Port.State < Pcie->TrainingExitState) {
+    *TrainingComplete = FALSE;
+  } else {
+    return;
+  }
+  switch (Engine->Type.Port.State) {
+  case LinkStateResetAssert:
+    PcieTrainingAssertReset (Engine, Pcie);
+    break;
+  case LinkStateResetDuration:
+    PcieTrainingCheckResetDuration (Engine, Pcie);
+    break;
+  case LinkStateResetExit:
+    PcieTrainingDeassertReset (Engine, Pcie);
+    break;
+  case LinkTrainingResetTimeout:
+    PcieTrainingCheckResetTimeout (Engine, Pcie);
+    break;
+  case LinkStateReleaseTraining:
+    PcieTrainingRelease (Engine, Pcie);
+    break;
+  case LinkStateDetectPresence:
+    PcieTrainingDetectPresence (Engine, Pcie);
+    break;
+  case LinkStateDetecting:
+    PcieTrainingDetectLinkState (Engine, Pcie);
+    break;
+  case LinkStateBrokenLane:
+    PcieTrainingBrokenLine (Engine, Pcie);
+    break;
+  case LinkStateGen2Fail:
+    PcieTrainingGen2Fail (Engine, Pcie);
+    break;
+  case LinkStateL0:
+    PcieCheckLinkL0 (Engine, Pcie);
+    break;
+  case LinkStateVcoNegotiation:
+    PcieTrainingCheckVcoNegotiation (Engine, Pcie);
+    break;
+  case LinkStateRetrain:
+    PcieTrainingRetrainLink (Engine, Pcie);
+    break;
+  case LinkStateTrainingFail:
+    PcieTrainingFail (Engine, Pcie);
+    break;
+  case LinkStateGfxWorkaround:
+    PcieTrainingGfxWorkaround (Engine, Pcie);
+    break;
+  case LinkStateTrainingSuccess:
+    PcieTrainingSuccess (Engine, Pcie);
+    break;
+  case LinkStateCompliance:
+    PcieTrainingCompliance (Engine, Pcie);
+    break;
+  case LinkStateDeviceNotPresent:
+    PcieTrainingNotPresent (Engine, Pcie);
+    break;
+  case LinkStateTrainingCompleted:
+    PcieTrainingCompleted (Engine, Pcie);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Main link training procedure
+ *
+ *  Port end up in three possible state  LinkStateTrainingNotPresent/LinkStateCompliance/
+ *                                       LinkStateTrainingSuccess
+ *
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+PcieTraining (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  BOOLEAN       TrainingComplete;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n");
+  do {
+    TrainingComplete = TRUE;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieTrainingPortCallback,
+      &TrainingComplete,
+      Pcie
+      );
+  } while (!TrainingComplete);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump port state on state transition
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+GNB_DEBUG_CODE (
+VOID
+STATIC
+PcieTrainingDebugDumpPortState (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Port %d:%d:%d State [%s] Time Stamp [%d]\n",
+    CurrentEngine->Type.Port.Address.Address.Bus,
+    CurrentEngine->Type.Port.Address.Address.Device,
+    CurrentEngine->Type.Port.Address.Address.Function,
+    (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail    " : (
+    (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : (
+    (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance      " : (
+    (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" :  (
+    (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert     " :  (
+    (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration   " :  (
+    (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit       " :  (
+    (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " :  (
+    (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " :  (
+    (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence  " :  (
+    (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting       " :  (
+    (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane      " :  (
+    (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail        " :  (
+    (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0              " :  (
+    (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation  " :  (
+    (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround   " : (
+    (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : (
+    (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain         " : (
+    (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit       " : "Unknown")))))))))))))))))),
+    CurrentEngine->Type.Port.TimeStamp
+    );
+}
+)
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
new file mode 100644
index 0000000000..c84b522d7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  PCIe link training
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETRAINING_H_
+#define _PCIETRAINING_H_
+
+
+AGESA_STATUS
+PcieTraining (
+  IN     PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingSetPortState (
+  IN      PCIe_ENGINE_CONFIG        *CurrentEngine,
+  IN      PCIE_LINK_TRAINING_STATE  State,
+  IN      BOOLEAN                   UpdateTimeStamp,
+  IN      PCIe_PLATFORM_CONFIG      *Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
new file mode 100644
index 0000000000..858dcbe4e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -0,0 +1,402 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various workarounds
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbRegistersLN.h"
+#include  "PcieWorkarounds.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieConfigureBridgeResources (
+  IN      PCI_ADDR             Port,
+  IN      AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+PcieFreeBridgeResources (
+  IN      PCI_ADDR             Port,
+  IN      AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+GFX_WORKAROUND_STATUS
+PcieDeskewWorkaround (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+GFX_WORKAROUND_STATUS
+PcieNvWorkaround (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+PcieProgramCpuMmio (
+  OUT    UINT32              *SaveValues,
+  IN     AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+PcieRestoreCpuMmio (
+  IN     UINT32              *RestoreValues,
+  IN     AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+BOOLEAN
+PcieIsDeskewCardDetected (
+  IN      UINT16             DeviceId
+  );
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ATI RV370/RV380 card workaround
+ *
+ *
+ *
+ * @param[in]  Port        PCI addreses of the port
+ * @param[in]  StdHeader   Standard configuration header
+ * @retval     GFX_WORKAROUND_STATUS   Return the GFX Card Workaround status
+ */
+GFX_WORKAROUND_STATUS
+PcieGfxCardWorkaround (
+  IN     PCI_ADDR               Port,
+  IN     AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GFX_WORKAROUND_STATUS   Status;
+  UINT16                  DeviceId;
+  UINT16                  VendorId;
+  UINT8                   DevClassCode;
+  UINT32                  SaveValueData[2];
+  PCI_ADDR                Ep;
+
+  Status = GFX_WORKAROUND_SUCCESS;
+
+  Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0);
+  if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) {
+    GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader);
+    Status = GFX_WORKAROUND_DEVICE_NOT_READY;
+    if (DeviceId != 0xffff) {
+      GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader);
+      if (VendorId != 0xffff) {
+        GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader);
+        Status = GFX_WORKAROUND_SUCCESS;
+        if (DevClassCode == 3) {
+          PcieProgramCpuMmio (SaveValueData, StdHeader);
+          if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) {
+            Status = PcieDeskewWorkaround (Ep, StdHeader);
+          } else if (VendorId == 0x10DE) {
+            Status = PcieNvWorkaround (Ep, StdHeader);
+          }
+          PcieRestoreCpuMmio (SaveValueData, StdHeader);
+        }
+      }
+    }
+    PcieFreeBridgeResources (Port, StdHeader);
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RV370/RV380 Deskew workaround
+ *
+ *
+ *
+ * @param[in] Device     Pcie Address of ATI RV370/RV380 card.
+ * @param[in] StdHeader  Standard configuration header
+ */
+GFX_WORKAROUND_STATUS
+PcieDeskewWorkaround (
+  IN      PCI_ADDR              Device,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINTN       MmioBase;
+  UINT16      MmioData1;
+  UINT32      MmioData2;
+
+  MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
+  if (MmioBase == 0) {
+    return GFX_WORKAROUND_SUCCESS;
+  }
+  GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , (UINT32)~BIT1, (UINT32)BIT1, StdHeader);
+  GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader);
+  GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader);
+  if (MmioData1 == 0xb700) {
+    GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader);
+    GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader);
+    if (MmioData2 == 0x13) {
+      GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader);
+      if (MmioData2 & BIT8) {
+        return  GFX_WORKAROUND_RESET_DEVICE;
+      }
+    }
+  }
+  GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, (UINT32)~BIT1, 0x0, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader);
+
+  return GFX_WORKAROUND_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  NV43 card workaround (lost SSID)
+ *
+ *
+ *
+ * @param[in] Device     Pcie Address of NV43 card.
+ * @param[in] StdHeader  Standard configuration header
+ */
+GFX_WORKAROUND_STATUS
+PcieNvWorkaround (
+  IN     PCI_ADDR              Device,
+  IN     AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32      DeviceSSID;
+  UINTN       MmioBase;
+  UINT32      MmioData3;
+
+  MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
+  if (MmioBase == 0) {
+    return GFX_WORKAROUND_SUCCESS;
+  }
+  GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader);
+  GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader);
+  GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader);
+  if (DeviceSSID != MmioData3) {
+    GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader);
+  }
+  GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader);
+  return GFX_WORKAROUND_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Allocate temporary resources for Pcie P2P bridge
+ *
+ *
+ *
+ * @param[in] Port         Pci Address of Port to initialize.
+ * @param[in] StdHeader    Standard configuration header
+ */
+AGESA_STATUS
+PcieConfigureBridgeResources (
+  IN      PCI_ADDR              Port,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32      Value;
+  UINT32      MmioBase;
+
+  MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
+  if (MmioBase == 0) {
+    return AGESA_WARNING;
+  }
+  Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16);
+  GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader);
+  Value = MmioBase + (MmioBase >> 16);
+  GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader);
+  Value = 0x000fff0;
+  GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader);
+  Value = 0x2;
+  GnbLibPciWrite (Port.AddressValue | 0x4 , AccessWidth8, &Value, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Free temporary resources for Pcie P2P bridge
+ *
+ *
+ *
+ * @param[in] Port       Pci Address of Port to clear resource allocation.
+ * @param[in] StdHeader  Standard configuration header
+ */
+VOID
+PcieFreeBridgeResources (
+  IN      PCI_ADDR            Port,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 Value;
+
+  Value = 0;
+  GnbLibPciWrite (Port.AddressValue | 0x4 , AccessWidth8,  &Value, StdHeader);
+  GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader);
+  GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader);
+  GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader);
+
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Save CPU MMIO register
+ *
+ *
+ *
+ * @param[out] UINT32        SaveValues
+ * @param[in]  StdHeader     Standard configuration header
+ *
+ */
+VOID
+PcieProgramCpuMmio (
+     OUT   UINT32             *SaveValues,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  //Save CPU MMIO Register
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader);
+
+  //Write Temp Pcie MMIO to CPU
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader);
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Restore CPU MMIO register
+ *
+ *
+ *
+ * @param[in] PCIe_PLATFORM_CONFIG    Pcie
+ * @param[in] StdHeader               Standard configuration header
+ */
+VOID
+PcieRestoreCpuMmio (
+  IN      UINT32                *RestoreValues,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  //Restore CPU MMIO Register
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader);
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if card required test for deskew workaround
+ *
+ *
+ *
+ * @param[in] DeviceId    Device ID
+ */
+
+BOOLEAN
+PcieIsDeskewCardDetected (
+  IN      UINT16    DeviceId
+  )
+{
+  if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) ||
+     (DeviceId == 0x3E50) || (DeviceId == 0x3E54) ||
+     ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8)  == 0x5B60)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h
new file mode 100644
index 0000000000..3f67635c20
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various workarounds
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEWORKAROUNDS_H_
+#define _PCIEWORKAROUNDS_H_
+
+GFX_WORKAROUND_STATUS
+PcieGfxCardWorkaround (
+  IN     PCI_ADDR               Port,
+  IN     AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
new file mode 100644
index 0000000000..64f8df5576
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
@@ -0,0 +1,178 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CNB library.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuServices.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbLib.h"
+#include  "GnbLibPciAcc.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Host bridge PCI Address
+ *
+ *
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      PCI address of GNB for a given socket/silicon.
+ */
+
+PCI_ADDR
+GnbFmGetPciAddress (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Gnb;
+  Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  return Gnb;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bus range decoded by GNB
+ *
+ * Final bus allocation can not be assumed until AmdInitMid
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  StartBusNumber  Beggining of the Bus Range
+ * @param[out]  EndBusNumber    End of the Bus Range
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+
+AGESA_STATUS
+GnbFmGetBusDecodeRange (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *StartBusNumber,
+     OUT   UINT8                      *EndBusNumber,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  *StartBusNumber = 0x0;
+  *EndBusNumber = 0xff;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link to which GNB connected to
+ *
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  LinkId          Link to which GNB connected to
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+
+AGESA_STATUS
+GnbFmGetLinkId (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *LinkId,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+
+  *LinkId = 0x00;
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
new file mode 100644
index 0000000000..5a1db75fd9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
@@ -0,0 +1,146 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbIommu.h"
+#include  "GnbCommonLib.h"
+#include  "GnbIvrsLib.h"
+#include  "GnbSbIommuLib.h"
+#include  "GnbSbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHD entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+SbCreateIvhdEntries (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Start;
+  PCI_ADDR  End;
+  PCI_ADDR  PciAddress;
+  UINT32    Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Entry\n");
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 4, 0);
+// P2P alias entry
+  GnbLibPciRead (PciAddress.AddressValue | 0x18, AccessWidth32, &Value, StdHeader);
+  Start.AddressValue = MAKE_SBDFO (0, (Value >> 8) & 0xff, 0, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0x1f, 0x7, 0);
+  GnbIvhdAddDeviceAliasRangeEntry (Start, End, PciAddress, 0, Ivhd, StdHeader);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
+// HPET
+  GnbIvhdAddSpecialDeviceEntry (IvhdSpecialDeviceHpet, PciAddress, 0, 0, Ivhd, StdHeader);
+// APIC
+  GnbIvhdAddSpecialDeviceEntry (
+    IvhdSpecialDeviceIoapic,
+    PciAddress,
+    GnbLiGetIoapicId (SbGetSbIoApicBaseAddress (StdHeader), StdHeader),
+    0xD7,
+    Ivhd,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h
new file mode 100644
index 0000000000..264c48e74f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBSBIOMMULIB_H_
+#define _GNBSBIOMMULIB_H_
+
+
+VOID
+SbCreateIvhdEntries (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
new file mode 100644
index 0000000000..15da5f28ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
@@ -0,0 +1,159 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbSbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Get SB IOAPIC Base Address
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     APIC base address
+ */
+UINT32
+SbGetSbIoApicBaseAddress (
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT32 ApicBaseAddress;
+  GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x34, 4, &ApicBaseAddress, StdHeader);
+  return ApicBaseAddress & 0xfffffff8;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Get SB MMIO Base Address
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     MMIO base address
+ */
+UINT32
+SbGetSbMmioBaseAddress (
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT32 MmioBaseAddress;
+  GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x24, 4, &MmioBaseAddress, StdHeader);
+  return MmioBaseAddress & 0xfffffffc;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Alink config address
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     Alink base address
+ */
+/*----------------------------------------------------------------------------------------*/
+
+UINT16
+SbGetAlinkIoAddress (
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+
+  UINT16 AlinkPortAddress;
+  GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0xE0, 2, &AlinkPortAddress, StdHeader);
+  return  AlinkPortAddress;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h
new file mode 100644
index 0000000000..3ba80d462e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBSBLIB_H_
+#define _GNBSBLIB_H_
+
+#include "GnbPcie.h"
+
+UINT32
+SbGetSbIoApicBaseAddress (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+UINT32
+SbGetSbMmioBaseAddress (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+UINT16
+SbGetAlinkIoAddress (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+SbPcieInitAspm (
+  IN      PCIE_ASPM_TYPE            Aspm,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+SbPcieLinkAspmControl (
+  IN      PCIe_ENGINE_CONFIG        *Engine,
+  IN      PCIe_PLATFORM_CONFIG      *Pcie
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
new file mode 100644
index 0000000000..a592041fe5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -0,0 +1,169 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB-SB link procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbSbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable/Disable ASPM on GNB-SB link
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+AGESA_STATUS
+SbPcieLinkAspmControl (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS    Status;
+  PCIE_ASPM_TYPE  Aspm;
+
+  Aspm = Engine->Type.Port.PortData.LinkAspm;
+
+  Status = SbPcieInitAspm (Aspm, GnbLibGetHeader (Pcie));
+  if (Status != AGESA_SUCCESS) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PcieAspmEnableOnFunction (Engine->Type.Port.Address, Aspm, GnbLibGetHeader (Pcie));
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SB ASPM.
+ * Enable ASPM states on SB
+ *
+ *
+ * @param[in] Aspm       ASPM bitmap.
+ * @param[in] StdHeader  Standard configuration header
+ */
+/*----------------------------------------------------------------------------------------*/
+
+AGESA_STATUS
+SbPcieInitAspm (
+  IN      PCIE_ASPM_TYPE       Aspm,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16        AlinkPort;
+
+  AlinkPort = SbGetAlinkIoAddress (StdHeader);
+  ASSERT (AlinkPort != 0);
+  if (AlinkPort == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader);
+  GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader);
+  GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader);
+  GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader);
+  GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader);
+  GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
new file mode 100644
index 0000000000..bb0a47ca40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
@@ -0,0 +1,155 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at mid POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+GfxInitSview (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SVIEW configuration
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxInitSview (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status =  GfxLocateConfigData (StdHeader, &Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    if (GfxLibIsControllerPresent (StdHeader)) {
+      if (!GfxFmIsVbiosPosted (Gfx)) {
+        GFX_VBIOS_IMAGE_INFO  VbiosImageInfo;
+        LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+        VbiosImageInfo.ImagePtr = NULL;
+        VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress;
+        VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST;
+        GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader);
+        Status = AgesaGetVbiosImage (0, &VbiosImageInfo);
+        if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) {
+          GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx);
+        } else {
+          GfxFmDisableController (StdHeader);
+          AgesaStatus = AGESA_ERROR;
+        }
+        GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xf8, BIT1 | BIT2, StdHeader);
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
new file mode 100644
index 0000000000..8d7d5dbb02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
@@ -0,0 +1,384 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbLib.h"
+#include  "GnbTimerLib.h"
+#include  "GnbFamServices.h"
+#include  "GnbTable.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+GnbProcessTableRegisterRmw (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_REGISTER_SERVICE  *GnbRegisterAccessProtocol,
+  IN      GNB_RMW_BLOCK         *Data,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process table
+ *
+ * @param[in] GnbHandle       Gnb handle
+ * @param[in] Table           Table pointer
+ * @param[in] Property        Property
+ * @param[in] Flags           Flags
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+AGESA_STATUS
+GnbProcessTable (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_TABLE             *Table,
+  IN      UINT32                Property,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8                   *EntryPointer;
+  UINT64                  Data;
+  UINT64                  Temp;
+  UINT64                  Mask;
+  UINT32                  WriteAccFlags;
+  GNB_REGISTER_SERVICE    *GnbRegisterAccessProtocol;
+  CPU_LOGICAL_ID          LogicalId;
+  AGESA_STATUS            Status;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Enter\n");
+  IDS_HDT_CONSOLE (GNB_TRACE, " Property - 0x%08x\n", Property);
+
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader);
+  EntryPointer = (UINT8 *) Table;
+  WriteAccFlags = 0;
+  if ((Flags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) {
+    WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE;
+  }
+
+  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+
+  while (*EntryPointer != GnbEntryTerminate) {
+    Data = 0;
+    Temp = 0;
+    switch (*EntryPointer) {
+    case GnbEntryWr:
+      GnbRegisterAccessProtocol->Write (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_WR*) EntryPointer)->RegisterSpaceType,
+        ((GNB_TABLE_ENTRY_WR*) EntryPointer)->Address,
+        &((GNB_TABLE_ENTRY_WR*) EntryPointer)->Value,
+        WriteAccFlags,
+        StdHeader
+        );
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_WR);
+      break;
+    case GnbEntryPropertyWr:
+      if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Property) != 0) {
+        GnbRegisterAccessProtocol->Write (
+          GnbHandle,
+          ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->RegisterSpaceType,
+          ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Address,
+          &((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Value,
+          WriteAccFlags,
+          StdHeader
+          );
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_WR);
+      break;
+    case GnbEntryFullWr:
+      if ((Property & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Property) != 0) {
+        if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Revision) != 0) {
+          GnbRegisterAccessProtocol->Write (
+            GnbHandle,
+            ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->RegisterSpaceType,
+            ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Address,
+            &((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Value,
+            WriteAccFlags,
+            StdHeader
+            );
+        }
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_WR);
+      break;
+    case GnbEntryRmw:
+      GnbProcessTableRegisterRmw (
+        GnbHandle,
+        GnbRegisterAccessProtocol,
+        &((GNB_TABLE_ENTRY_RMW *) EntryPointer)->Data,
+        WriteAccFlags,
+        StdHeader
+        );
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_RMW);
+      break;
+    case GnbEntryPropertyRmw:
+      if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Property) != 0) {
+        GnbProcessTableRegisterRmw (
+          GnbHandle,
+          GnbRegisterAccessProtocol,
+          &((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Data,
+          WriteAccFlags,
+          StdHeader
+          );
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_RMW);
+      break;
+    case GnbEntryRevRmw:
+      if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Revision) != 0) {
+        GnbProcessTableRegisterRmw (
+          GnbHandle,
+          GnbRegisterAccessProtocol,
+          &((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Data,
+          WriteAccFlags,
+          StdHeader
+          );
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_REV_RMW);
+      break;
+    case GnbEntryFullRmw:
+      if ((Property & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Property) != 0) {
+        if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) {
+          GnbProcessTableRegisterRmw (
+            GnbHandle,
+            GnbRegisterAccessProtocol,
+            &((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Data,
+            WriteAccFlags,
+            StdHeader
+            );
+        }
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_RMW);
+      break;
+    case GnbEntryPoll:
+      do {
+        GnbRegisterAccessProtocol->Read (
+          GnbHandle,
+          ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->RegisterSpaceType,
+          ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->Address,
+          &Data,
+          0,
+          StdHeader
+          );
+      } while ((Data & ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->CompareValue);
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_POLL);
+      break;
+    case GnbEntryPropertyPoll:
+      if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Property) != 0) {
+        do {
+          GnbRegisterAccessProtocol->Read (
+            GnbHandle,
+            ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->RegisterSpaceType,
+            ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Address,
+            &Data,
+            0,
+            StdHeader
+            );
+        } while ((Data & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->CompareValue);
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_POLL);
+      break;
+    case GnbEntryFullPoll:
+      if ((Property & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Property) != 0) {
+        if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) {
+          do {
+            GnbRegisterAccessProtocol->Read (
+              GnbHandle,
+              ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->RegisterSpaceType,
+              ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Address,
+              &Data,
+              0,
+              StdHeader
+              );
+          } while ((Data & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->CompareValue);
+        }
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_POLL);
+      break;
+    case GnbEntryCopy:
+      GnbRegisterAccessProtocol->Read (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcRegisterSpaceType,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcAddress,
+        &Data,
+        0,
+        StdHeader
+        );
+      Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldWidth) - 1;
+      Data = (Data >> ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldOffset) & Mask;
+      GnbRegisterAccessProtocol->Read (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress,
+        &Temp,
+        0,
+        StdHeader
+        );
+      Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldWidth) - 1;
+      Temp = Temp & ( ~ (Mask << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset));
+      Temp = Temp | ((Data & Mask) << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset);
+      GnbRegisterAccessProtocol->Write (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress,
+        &Temp,
+        WriteAccFlags,
+        StdHeader
+        );
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_COPY);
+      break;
+    case GnbEntryStall:
+      if ((WriteAccFlags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) {
+        GnbLibStallS3Save (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader);
+      } else {
+        GnbLibStall (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader);
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_STALL);
+      break;
+    default:
+      ASSERT (FALSE);
+      IDS_HDT_CONSOLE (NB_MISC, "  ERROR!!! Regiter table parse\n");
+      return AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Supporting function for register read modify write
+ *
+ * @param[in] GnbHandle                 Gnb handle
+ * @param[in] GnbRegisterAccessProtocol Register access protocol
+ * @param[in] Data                      Data pointer
+ * @param[in] Flags                     Flags
+ * @param[in] StdHeader                 Standard configuration header
+ */
+
+VOID
+STATIC
+GnbProcessTableRegisterRmw (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_REGISTER_SERVICE  *GnbRegisterAccessProtocol,
+  IN      GNB_RMW_BLOCK         *Data,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT64  Value;
+  Value = 0;
+  GnbRegisterAccessProtocol->Read (
+    GnbHandle,
+    Data->RegisterSpaceType,
+    Data->Address,
+    &Value,
+    0,
+    StdHeader
+    );
+  Value = (Value & (~ (UINT64) Data->AndMask)) | Data->OrMask;
+  GnbRegisterAccessProtocol->Write (
+    GnbHandle,
+    Data->RegisterSpaceType,
+    Data->Address,
+    &Value,
+    Flags,
+    StdHeader
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h
new file mode 100644
index 0000000000..02b0f52b46
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h
@@ -0,0 +1,265 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBTABLE_H_
+#define _GNBTABLE_H_
+
+#include "GnbPcie.h"
+
+#pragma pack (push, 1)
+
+#define GNB_TABLE_FLAGS_FORCE_S3_SAVE  0x00000001ul
+
+typedef UINT8 GNB_TABLE;
+
+#define __DATA(x) x
+
+#define _DATA32(Data) (__DATA(Data)) & 0xFF, ((__DATA(Data)) >> 8) & 0xFF, ((__DATA(Data)) >> 16) & 0xFF, ((__DATA(Data)) >> 24) & 0xFF
+#define _DATA64(Data) _DATA32(Data & 0xfffffffful) , _DATA32(Data >> 32)
+
+/// Entry type
+typedef enum {
+  GnbEntryWr,                     ///< Write register
+  GnbEntryPropertyWr,             ///< Write register check property
+  GnbEntryFullWr,                 ///< Write Rgister check revision and property
+  GnbEntryRmw,                    ///< Read Modify Write register
+  GnbEntryPropertyRmw,            ///< Read Modify Write register check property
+  GnbEntryRevRmw,                 ///< Read Modify Write register check revision
+  GnbEntryFullRmw,                ///< Read Modify Write register check revision and property
+  GnbEntryPoll,                   ///< Poll register
+  GnbEntryPropertyPoll,           ///< Poll register check property
+  GnbEntryFullPoll,               ///< Poll register check property
+  GnbEntryCopy,                   ///< Copy field from one register to another
+  GnbEntryStall,                  ///< Copy field from one register to another
+  GnbEntryTerminate = 0xFF        ///< Terminate table
+} GNB_TABLE_ENTRY_TYPE;
+
+#define GNB_ENTRY_WR(RegisterSpaceType, Address, Value) \
+  GnbEntryWr, RegisterSpaceType, _DATA32 (Address), _DATA32 (Value)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  Value;                  ///< Value
+} GNB_TABLE_ENTRY_WR;
+
+#define GNB_ENTRY_PROPERTY_WR(Property, RegisterSpaceType, Address, Value) \
+  GnbEntryPropertyWr, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  Value;                  ///< Value
+} GNB_TABLE_ENTRY_PROPERTY_WR;
+
+
+#define GNB_ENTRY_RMW(RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryRmw, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+///Read Modify Write data Block
+typedef struct {
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< And Mask
+  UINT32  OrMask;                 ///< Or Mask
+} GNB_RMW_BLOCK;
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_RMW;
+
+#define GNB_ENTRY_FULL_WR(Property, Revision, RegisterSpaceType, Address, Value) \
+   GnbEntryFullWr, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT64  Revision;               ///< Revision
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  Value;                  ///< Value
+} GNB_TABLE_ENTRY_FULL_WR;
+
+
+#define GNB_ENTRY_PROPERTY_RMW(Property,  RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryPropertyRmw, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  UINT32          Property;       ///< Property
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_PROPERTY_RMW;
+
+#define GNB_ENTRY_REV_RMW(Rev,  RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryRevRmw, _DATA64 (Rev), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  UINT64          Revision;       ///< revision
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_REV_RMW;
+
+#define GNB_ENTRY_FULL_RMW(Property, Revision, RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryFullRmw, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  UINT32          Property;       ///< Property
+  UINT64          Revision;       ///< Revision
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_FULL_RMW;
+
+#define GNB_ENTRY_POLL(RegisterSpaceType, Address, AndMask, CompareValue) \
+  GnbEntryPoll, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue)
+/// Poll register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< End mask
+  UINT32  CompareValue;           ///< Compare value
+} GNB_TABLE_ENTRY_POLL;
+
+#define GNB_ENTRY_PROPERTY_POLL(Property, RegisterSpaceType, Address, AndMask, CompareValue) \
+  GnbEntryPropertyPoll, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue)
+/// Poll register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< End mask
+  UINT32  CompareValue;           ///< Compare value
+} GNB_TABLE_ENTRY_PROPERTY_POLL;
+
+#define GNB_ENTRY_FULL_POLL(Property, Revision, RegisterSpaceType, Address, AndMask, CompareValue) \
+  GnbEntryFullPoll, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue)
+/// Poll register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT64  Revision;               ///< Revision
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< End mask
+  UINT32  CompareValue;           ///< Compare value
+} GNB_TABLE_ENTRY_FULL_POLL;
+
+#define GNB_ENTRY_COPY(DestRegSpaceType, DestAddress, DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, SrcAddress, SrcFieldOffset, SrcFieldWidth) \
+  GnbEntryCopy, DestRegSpaceType, _DATA32 (DestAddress), DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, _DATA32 (SrcAddress), SrcFieldOffset, SrcFieldWidth
+
+/// Copy regster entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT8   DestRegisterSpaceType;  ///< Register space
+  UINT32  DestAddress;            ///< Register address
+  UINT8   DestFieldOffset;        ///< Field Offset
+  UINT8   DestFieldWidth;         ///< Field Width
+  UINT8   SrcRegisterSpaceType;   ///< Register space
+  UINT32  SrcAddress;             ///< Register address
+  UINT8   SrcFieldOffset;         ///< Field Offset
+  UINT8   SrcFieldWidth;          ///< Field Width
+} GNB_TABLE_ENTRY_COPY;
+
+#define GNB_ENTRY_STALL(Microsecond) \
+  GnbEntryStall, _DATA32 (Microsecond)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;               ///< Entry type
+  UINT32  Microsecond;             ///< Value
+} GNB_TABLE_ENTRY_STALL;
+
+#define GNB_ENTRY_TERMINATE GnbEntryTerminate
+
+AGESA_STATUS
+GnbProcessTable (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_TABLE             *Table,
+  IN      UINT32                Property,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c
new file mode 100644
index 0000000000..a38379fd80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c
@@ -0,0 +1,173 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * The initializer for Family 15h Mode 10h-1Fh northbridge support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "CommonReturns.h"
+#include "htNbUtilitiesFam15Mod1x.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+
+/**
+ * Initial construction data for no HT Northbridge.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam15Mod1xNb =
+{
+  1,
+  (PF_WRITE_ROUTING_TABLE)CommonVoid,
+  (PF_WRITE_NODEID)CommonVoid,
+  (PF_READ_DEFAULT_LINK)CommonReturnZero8,
+  (PF_ENABLE_ROUTING_TABLES)CommonVoid,
+  (PF_DISABLE_ROUTING_TABLES)CommonVoid,
+  (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
+  (PF_READ_TOKEN)CommonReturnZero8,
+  (PF_WRITE_TOKEN)CommonVoid,
+  (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
+  (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
+  (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
+  (PF_STOP_LINK)CommonVoid,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
+  (PF_READ_SB_LINK)CommonReturnZero8,
+  (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse,
+  (PF_SET_CONFIG_ADDR_MAP)CommonVoid,
+  (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32,
+  (PF_GATHER_LINK_FEATURES)CommonVoid,
+  (PF_SET_LINK_REGANG)CommonVoid,
+  (PF_SET_LINK_FREQUENCY)CommonVoid,
+  (PF_SET_LINK_UNITID_CLUMPING)CommonVoid,
+  (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid,
+  (PF_BUFFER_OPTIMIZATIONS)CommonVoid,
+  Fam15Mod1xGetNumCoresOnNode,
+  Fam15Mod1xSetTotalCores,
+  Fam15Mod1xGetNodeCount,
+  (PF_LIMIT_NODES)CommonVoid,
+  (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse,
+  (PF_GET_NEXT_LINK)CommonReturnZero32,
+  (PF_GET_PACKAGE_LINK)CommonReturnZero8,
+  (PF_MAKE_LINK_BASE)CommonReturnZero32,
+  (PF_GET_MODULE_INFO)CommonVoid,
+  (PF_POST_MAILBOX)CommonVoid,
+  (PF_RETRIEVE_MAILBOX)CommonReturnZero32,
+  (PF_GET_SOCKET)CommonReturnZero8,
+  (PF_GET_ENABLED_COMPUTE_UNITS)Fam15Mod1xGetEnabledComputeUnits,
+  (PF_GET_DUALCORE_COMPUTE_UNITS)Fam15Mod1xGetDualcoreComputeUnits,
+  0,
+  0,
+  0,
+  TRUE,
+  TRUE,
+  AMD_FAMILY_TN ,
+  NULL,
+  0,
+  NULL,
+  (PF_MAKE_KEY)CommonReturnZero64,
+  NULL
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
new file mode 100644
index 0000000000..29fc5bb82c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
@@ -0,0 +1,265 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * These routines are needed for support of more than one feature area.
+ * Collect them in this file so build options don't remove them.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbCommonHardware.h"
+#include "htNbUtilitiesFam15Mod1x.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write the total number of cores to the Node
+ *
+ * @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES}
+ *
+ * @param[in]     Node         the Node that will be examined
+ * @param[in]     TotalNodes   the total number of Nodes
+ * @param[in]     TotalCores   the total number of cores
+ * @param[in]     Nb           this northbridge
+ */
+VOID
+Fam15Mod1xSetTotalCores (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR NodeIDReg;
+  UINT32 Temp;
+
+  NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                       MakePciBusFromNode (Node),
+                                       MakePciDeviceFromNode (Node),
+                                       CPU_HTNB_FUNC_00,
+                                       REG_NODE_ID_0X60);
+
+  Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0);
+  LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+UINT8
+Fam15Mod1xGetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Result;
+  UINT32 Leveling;
+  UINT32 Cores;
+  UINT8 i;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Read CmpCap
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_05,
+                                 REG_NB_CAPABILITY_2_5X84);
+
+  LibAmdPciReadBits (Reg, 7, 0, &Result, Nb->ConfigHandle);
+
+  // Support Downcoring
+  Cores = Result;
+  Cores++;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_DOWNCORE_3X190);
+  LibAmdPciReadBits (Reg, 31, 0, &Leveling, Nb->ConfigHandle);
+  for (i = 0; i < Cores; i++) {
+    if ((Leveling & ((UINT32) 1 << i)) != 0) {
+      Result--;
+    }
+  }
+  return (UINT8) (Result + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Count (1 based) of Nodes in the system.
+ *
+ * @HtNbMethod{::F_GET_NODE_COUNT}
+ *
+ * This is intended to support AP Core HT init, since the Discovery State data is not
+ * available (State->NodesDiscovered), there needs to be this way to find the number
+ * of Nodes, which is just one.
+ *
+ * @param[in]     Nb           this northbridge
+ *
+ * @return        The number of nodes
+ */
+UINT8
+Fam15Mod1xGetNodeCount (
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  ASSERT (Nb != NULL);
+  return (1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the enable compute unit status for this node.
+ *
+ * @HtNbMethod{::F_GET_ENABLED_COMPUTE_UNITS}
+ *
+ * @param[in]   Node    The node for which we want the enabled compute units.
+ * @param[in]   Nb      Our Northbridge.
+ *
+ * @return      The Enabled Compute Unit value
+ */
+UINT8
+Fam15Mod1xGetEnabledComputeUnits (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Enabled;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_05,
+                                 REG_NB_COMPUTE_UNIT_5X80);
+  LibAmdPciReadBits (Reg, 1, 0, &Enabled, Nb->ConfigHandle);
+  return ((UINT8) Enabled);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the dual core compute unit status for this node.
+ *
+ * @HtNbMethod{::PF_GET_DUALCORE_COMPUTE_UNITS}
+ *
+ * @param[in]   Node    The node for which we want the dual core status
+ * @param[in]   Nb      Our Northbridge.
+ *
+ * @return      The dual core compute unit status.
+ */
+UINT8
+Fam15Mod1xGetDualcoreComputeUnits (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Dual;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_05,
+                                 REG_NB_COMPUTE_UNIT_5X80);
+  LibAmdPciReadBits (Reg, 17, 16, &Dual, Nb->ConfigHandle);
+  return ((UINT8) Dual);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.h
new file mode 100644
index 0000000000..1ed304af10
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.h
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NB_UTILITIES_FAM15MOD1X_H_
+#define _HT_NB_UTILITIES_FAM15MOD1X_H_
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ */
+UINT8
+Fam15Mod1xGetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+UINT8
+Fam15Mod1xGetNodeCount (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the enable compute unit status for this node.
+ */
+UINT8
+Fam15Mod1xGetEnabledComputeUnits (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the dual core compute unit status for this node.
+ */
+UINT8
+Fam15Mod1xGetDualcoreComputeUnits (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Write the total number of cores to the Node
+ *
+ */
+VOID
+Fam15Mod1xSetTotalCores (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  );
+
+#endif // _HT_NB_UTILITIES_FAM15MOD1X_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c
new file mode 100644
index 0000000000..8942fd7271
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c
@@ -0,0 +1,138 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HyperTransport features constructor.
+ *
+ * Initialize the set of available features.
+ * This file implements build options using conditional compilation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTFEAT_FILECODE
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/**
+ * A no features Initializer.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesNone =
+{
+  (PF_COHERENT_DISCOVERY)CommonVoid,
+  (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
+  (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
+  (PF_PROCESS_LINK)CommonVoid,
+  (PF_GATHER_LINK_DATA)CommonVoid,
+  (PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY)CommonVoid,
+  (PF_REGANG_LINKS)CommonVoid,
+  (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
+  (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
+  (PF_SET_LINK_DATA)CommonVoid,
+  (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_SET_HT_CONTROL_REGISTER_BITS)CommonVoid,
+  (PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Provide the current Feature set implementation.
+ *
+ * Initialize using the installed initializer.
+ *
+ * @param[in]   HtFeatures      A feature object to initialize
+ * @param[in]   StdHeader       Opaque handle to standard config header
+*/
+VOID
+NewHtFeatures (
+     OUT   HT_FEATURES         *HtFeatures,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) HtFeatures,
+    (VOID *) OptionHtConfiguration.HtOptionInternalFeatures ,
+    (UINT32) (sizeof (HT_FEATURES)),
+    StdHeader
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.h
new file mode 100644
index 0000000000..229dc815f4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.h
@@ -0,0 +1,588 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HT Features.
+ *
+ * This file provides definitions used in common by HT internal modules.  The
+ * data is private and not for external client access.
+ * Definitions include the HT global internal state data structures, and
+ * access to the available HT features from the main HT entry point.
+ *
+ * This file includes the feature constructor and feature support which is not
+ * removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $        @e  \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_H_
+#define _HT_FEAT_H_
+
+/**
+ * @page htimplfeat HT Features Implementation Guide
+ *
+ * HT Features provides access to the HT Feature set, in a manner that isolates
+ * calling code from knowledge about the Feature set implementation or which
+ * features are supported in the current build.  In the case of feature sets, this
+ * is mostly used for build options to reduce code size by removing unneeded features.
+ *
+ * @par Adding a Method to HT Features
+ *
+ * To add a new method to the HT Features, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
+ *   </ul>
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtFeatInstances.
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the _HT_FEATURES struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an HT Features Instance of the method.
+ *
+ * To implement an instance of a method for a specific feature follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the method typedef.
+ *
+ * - Name the function MethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtFeatMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other Ht feature routines or data as part of the method implementation, the function
+ *   must use HtFeatures->OtherMethod().  Do not directly access other HT feature
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple configurations.
+ *
+ * - Add the instance to the HT_FEATURES instances.
+ *
+ * - If a configuration does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking HT Features Methods.
+ *
+ * The first step is carried out only once by the top level HT entry point.
+ * @n @code
+ * HT_FEATURES HtFeatures;
+ *   // Get the current HT Feature Set
+ *   NewHtFeatures (&HtFeatures);
+ *   State->HtFeatures = &HtFeatures;
+ * @endcode
+ *
+ * The following example shows how to invoke a HT Features method.
+ * @n @code
+ *    State->HtFeatures->MethodName ();
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MAX_PLATFORM_LINKS 64
+#define MAX_LINK_PAIRS 4
+
+/* These following are internal definitions */
+#define ROUTE_TO_SELF 0x0F
+#define INVALID_LINK 0xCC     /* Used in port list data structure to mark unused data entries.
+                                 Can also be used for no Link found in a port list search */
+
+/* definitions for working with the port list structure */
+#define PORTLIST_TYPE_CPU 0
+#define PORTLIST_TYPE_IO  1
+
+/*
+ * Hypertransport Capability definitions and macros
+ *
+ */
+
+#define HT_INTERFACE_CAP_SUBTYPE_MASK        ((UINT32)0xE00000FFul)
+#define HT_CAP_SUBTYPE_MASK                  ((UINT32)0xF80000FFul)
+
+/* HT Host Capability */
+#define HT_HOST_CAPABILITY                    1
+#define HT_HOST_CAP_SIZE                      0x20
+
+/* Host CapabilityRegisters */
+#define HTHOST_LINK_CAPABILITY_REG            0x00
+#define HTHOST_LINK_CONTROL_REG               0x04
+#define HTHOST_FREQ_REV_REG                   0x08
+#define HTHOST_REV_REV3                       0x60
+#define HTHOST_FEATURE_CAP_REG                0x0C
+#define HTHOST_BUFFER_COUNT_REG               0x10
+#define HTHOST_ISOC_REG                       0x14
+#define HTHOST_LINK_TYPE_REG                  0x18
+#define HTHOST_FREQ_EXTENSION                 0x1C
+#define HTHOST_TYPE_COHERENT                  3
+#define HTHOST_TYPE_NONCOHERENT               7
+#define HTHOST_TYPE_MASK                      0x1F
+
+/* HT Slave Capability (HT1 compat) */
+#define HT_SLAVE_CAPABILITY                   0
+#define HTSLAVE_LINK01_OFFSET                 4
+#define HTSLAVE_LINK_CONTROL_0_REG            4
+#define HTSLAVE_FREQ_REV_0_REG                0xC
+#define HTSLAVE_FEATURECAP_REG                0x10
+#define HT_CONTROL_CLEAR_CRC                  (~(3 << 8))
+#define HT_FREQUENCY_CLEAR_LINK_ERRORS        (~(0x7 << 12))
+#define MAX_BUID                              31
+
+/* HT3 gen Capability */
+#define HT_GEN3_CAPABILITY                    (0xD << 1)
+#define HTGEN3_LINK01_OFFSET                  0x10
+#define HTGEN3_LINK_TRAINING_0_REG            0x10
+
+/* HT3 Retry Capability */
+#define HT_RETRY_CAPABILITY                   (0xC << 1)
+#define HTRETRY_CONTROL_REG                   4
+
+/* Unit ID Clumping Capability */
+#define HT_UNITID_CAPABILITY                  (0x9 << 1)
+#define HTUNIT_SUPPORT_REG                    4
+#define HTUNIT_ENABLE_REG                     8
+#define HT_CLUMPING_PASSIVE                   1
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// Forward declarations.
+/// Used for forward reference.
+typedef struct _NORTHBRIDGE NORTHBRIDGE;
+/// Used for forward reference.
+typedef struct _HT_FEATURES HT_FEATURES;
+/// Used for forward reference.
+typedef struct _HT_INTERFACE HT_INTERFACE;
+
+/**
+ * Coherent Init Data.
+ *
+ * Metrics representing the coherent fabric which was discovered:  Degree of nodes, adjacency,
+ * node numbering permutations, and the topology which it matched.
+ */
+typedef struct {
+  /** The number of coherent Links connected on each Node (the 'Degree' of the Node) */
+  UINT8 SysDegree[MAX_NODES];
+  /** The systems adjacency (sysMatrix[i][j] is true if Node_i has a Link to Node_j) */
+  BOOLEAN SysMatrix[MAX_NODES][MAX_NODES];
+
+  UINT8 DbDegree[MAX_NODES];               /**< Like sysDegree, but for the current database topology */
+  BOOLEAN DbMatrix[MAX_NODES][MAX_NODES];  /**< Like sysMatrix, but for the current database topology */
+
+  UINT8 Perm[MAX_NODES];           /**< The Node mapping from the system to the database */
+  UINT8 ReversePerm[MAX_NODES];    /**< The Node mapping from the database to the system */
+  UINT8 *MatchedTopology;          /**< The topology that matched the current system or NULL */
+} COHERENT_FABRIC;
+
+/**
+ * Represent the system as Links of matched port pairs.
+ * A pair consists of a source Node, a Link to the destination Node, the
+ * destination Node, and its Link back to source Node.  The even indices are
+ * the source Nodes and Links, and the odd indices are for the destination
+ * Nodes and Links.
+ * @note The Port pair 2*N and 2*N+1 are connected together to form a Link
+ * (e.g. 0,1 and 8,9 are ports on either end of an HT Link) The lower number
+ * port (2*N) is the source port.  The device that owns the source port is
+ * always the device closer to the BSP. (i.e. nearer the CPU in a
+ * non-coherent chain, or the CPU with the lower NodeID).
+ */
+typedef struct {
+  /* This section is where the Link is in the system and how to find it */
+  UINT8 Type;              /**< 0 = CPU, 1 = Device, all others reserved */
+  UINT8 Link;              /**< 0-1 for devices, 0-7 for CPUs */
+  UINT8 NodeID;            /**< The Node, or a pointer to the devices parent Node */
+  UINT8 HostLink;          /**< For Devices, the root CPU's Link to the chain */
+  UINT8 HostDepth;         /**< Link Depth in chain, only used by devices */
+  PCI_ADDR Pointer;        /**< A pointer to the device's slave HT capability, so we don't have to keep searching */
+
+  /* This section is for the final settings, which are written to hardware */
+  BOOLEAN SelRegang;          /**< Indicates to software regang Link, only used for CPU->CPU Links */
+  UINT8 SelWidthIn;           /**< Width in setting */
+  UINT8 SelWidthOut;          /**< Width out setting */
+  UINT8 SelFrequency;         /**< Frequency setting */
+
+  /* This section is for keeping track of capabilities and possible configurations */
+  BOOLEAN RegangCap;            /**< Is the port capable of reganging? CPUs only */
+  UINT32 PrvFrequencyCap;       /**< Possible frequency settings */
+  UINT8 PrvWidthInCap;          /**< Possible Width setting */
+  UINT8 PrvWidthOutCap;         /**< Possible Width setting */
+  UINT32 CompositeFrequencyCap; /**< Possible Link frequency setting */
+  UINT32 ClumpingSupport;       /**< Unit ID Clumping value (bit 0 = passive support) */
+} PORT_DESCRIPTOR;
+
+/// Reference to a set of PORT_DESCRIPTORs.
+typedef PORT_DESCRIPTOR (*PORT_LIST)[MAX_PLATFORM_LINKS*2];
+
+/**
+ * Our global state data structure
+ */
+typedef struct {
+  AMD_HT_INTERFACE *HtBlock;  /**< The input data structure. */
+
+  UINT8 NodesDiscovered;      /**< One less than the number of Nodes found in the system */
+  UINT8 TotalLinks;           /**< How many HT Links have we discovered so far. */
+  UINT8 SysMpCap;             /**< The maximum number of Nodes that all processors are capable of */
+  AGESA_STATUS MaxEventClass; /**< The event class of the highest severity event generated */
+
+  PORT_LIST PortList;         /**< Represent the system as a set of Links, each two Ports. */
+  COHERENT_FABRIC *Fabric;                        /**< Describe metrics about the coherent fabric.
+                                                   * Limited scope to CoherentInit().  */
+  /* Data interface to other Agesa Modules */
+  SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap;      /**< For each Socket, Die the Node ids */
+  NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap;      /**< For each Node id, Socket and Die */
+  HOP_COUNT_TABLE *HopCountTable;                 /**< Table of hops between nodes */
+
+  /* Data for non-coherent initialization */
+  UINT8 AutoBusCurrent;                      /**< The next bus number available */
+  UINT8 UsedCfgMapEntries;                   /**< The next Config address Map set available, Limit 4 (F1X[EC:E0]) */
+  BOOLEAN IsUsingRecoveryHt;                 /**< Manual BUID Swap List processing should assume that HT Recovery was used */
+  BOOLEAN IsSetHtCrcFlood;                   /**< Enable setting of HT CRC Flood */
+  BOOLEAN IsUsingUnitIdClumping;             /**< Enable automatic Unit Id Clumping configuration. */
+
+  HT_INTERFACE *HtInterface;   /**< Interface for feature code to external parameters */
+  HT_FEATURES *HtFeatures;     /**< The current feature implementations */
+  NORTHBRIDGE *Nb;             /**< The current northbridge */
+
+  PLATFORM_CONFIGURATION *PlatformConfiguration;     /**< The platform specific configuration customizations */
+  VOID *ConfigHandle;          /**< Config Pointer, opaque handle for passing to lib */
+} STATE_DATA;
+
+//
+// Feature Method types
+//
+
+/**
+ * Discover all coherent devices in the system.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out] State     our global state
+ *
+ */
+typedef VOID F_COHERENT_DISCOVERY (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_COHERENT_DISCOVERY *PF_COHERENT_DISCOVERY;
+
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]    State    the discovered fabric, degree matrix, permutation
+ *
+ */
+typedef VOID F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES *PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES;
+
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]   State    access topology, permutation, update hop table
+ *
+ */
+typedef VOID F_MAKE_HOP_COUNT_TABLE (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_MAKE_HOP_COUNT_TABLE *PF_MAKE_HOP_COUNT_TABLE;
+
+/**
+ * Process a non-coherent Link.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Node          Node on which to process nc init
+ * @param[in]     Link          The non-coherent Link on that Node
+ * @param[in]     IsCompatChain Is this the chain with the southbridge? TRUE if yes.
+ * @param[in,out] State         our global state
+ */
+typedef VOID F_PROCESS_LINK (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_PROCESS_LINK *PF_PROCESS_LINK;
+
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     State our global state, port list
+ */
+typedef VOID F_GATHER_LINK_DATA (
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GATHER_LINK_DATA *PF_GATHER_LINK_DATA;
+
+/**
+ * Optimize Links.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]    State         Process and update portlist
+ */
+typedef VOID F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY (
+  IN OUT   STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY *PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     State   our global state, port list
+ */
+typedef VOID F_SET_LINK_DATA (
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_SET_LINK_DATA *PF_SET_LINK_DATA;
+
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]   State       global state, port frequency settings.
+ *
+ * @retval          TRUE        Fixup occurred, all coherent links HT1
+ * @retval          FALSE       No changes
+ */
+typedef BOOLEAN F_IS_COHERENT_RETRY_FIXUP (
+  IN       STATE_DATA       *State
+  );
+/// Reference to a method.
+typedef F_IS_COHERENT_RETRY_FIXUP *PF_IS_COHERENT_RETRY_FIXUP;
+
+
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out] State          Our global state
+ */
+typedef VOID F_REGANG_LINKS (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_REGANG_LINKS *PF_REGANG_LINKS;
+
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]     State     Link state and port list
+ *
+ */
+typedef VOID F_SUBLINK_RATIO_FIXUP (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_SUBLINK_RATIO_FIXUP *PF_SUBLINK_RATIO_FIXUP;
+
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]   State   port list data
+ */
+typedef VOID F_TRAFFIC_DISTRIBUTION (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_TRAFFIC_DISTRIBUTION *PF_TRAFFIC_DISTRIBUTION;
+
+/**
+ * Access HT Link Control Register.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Reg      the PCI config address the control register
+ * @param[in]     HiBit    the high bit number
+ * @param[in]     LoBit    the low bit number
+ * @param[in]     Value    the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]     State    Our state, config handle for lib
+ */
+typedef VOID F_SET_HT_CONTROL_REGISTER_BITS (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  );
+/// Reference to a method.
+typedef F_SET_HT_CONTROL_REGISTER_BITS *PF_SET_HT_CONTROL_REGISTER_BITS;
+
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Value   the width Value
+ *
+ * @return The bits for the register
+ */
+typedef UINT8 F_CONVERT_WIDTH_TO_BITS (
+  IN       UINT8       Value
+  );
+/// Reference to a method.
+typedef F_CONVERT_WIDTH_TO_BITS *PF_CONVERT_WIDTH_TO_BITS;
+
+/**
+ * HT Feature Methods.
+ *
+ * Provides abstract methods which are bound to specific feature implementations.
+ */
+struct _HT_FEATURES {
+  PF_COHERENT_DISCOVERY CoherentDiscovery;    /**< Method: Coherent Discovery. */
+  PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES LookupComputeAndLoadRoutingTables;
+                                              /**< Method: Route the discovered system */
+  PF_MAKE_HOP_COUNT_TABLE MakeHopCountTable;  /**< Method: Compute slit hop counts */
+  PF_PROCESS_LINK ProcessLink;                /**< Method: Process a non-coherent Link. */
+  PF_GATHER_LINK_DATA GatherLinkData;         /**< Method: Gather Link Capabilities and data. */
+  PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY SelectOptimalWidthAndFrequency;
+                                              /**< Method: Optimize link features. */
+  PF_REGANG_LINKS RegangLinks;                /**< Method: Regang Sublinks. */
+  PF_SUBLINK_RATIO_FIXUP SubLinkRatioFixup;   /**< Method: Fix Sublink Frequency ratios */
+  PF_IS_COHERENT_RETRY_FIXUP IsCoherentRetryFixup;
+                                              /**< Method: Fix Retry mixed on coherent links. */
+  PF_SET_LINK_DATA SetLinkData;               /**< Method: Set optimized values. */
+  PF_TRAFFIC_DISTRIBUTION TrafficDistribution; /**< Method: Detect and Initialize Traffic Distribution */
+  PF_SET_HT_CONTROL_REGISTER_BITS SetHtControlRegisterBits; /**< Method: Access HT Link Control Reg. */
+  PF_CONVERT_WIDTH_TO_BITS ConvertWidthToBits; /**< Method: Convert a bit width to the value used for register setting. */
+} ;
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Provide the current Feature set implementation.
+ *
+ * Add an implementation reference for the constructor, just to make sure the page is created.
+ * @HtFeatMethod{_HT_FEATURES}.
+ *
+ */
+VOID
+NewHtFeatures (
+     OUT   HT_FEATURES          *HtFeatures,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+
+#endif  /* _HT_FEAT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h
new file mode 100644
index 0000000000..14745fc2ba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h
@@ -0,0 +1,170 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Topology Interface.
+ *
+ * Contains interface to the topology data.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_GRAPH_H_
+#define _HT_GRAPH_H_
+
+/**
+ * @page htgraphdesign Graph Support routines
+ *
+ * These routines provide support for dealing with the graph representation
+ * of the topologies, along with the routing table information for that topology.
+ * The routing information is compressed and these routines currently decompress
+ * 'on the fly'.  A graph is represented as a set of routes. All the edges in the
+ * graph are routes; a direct route from Node i to Node j exists in the graph IFF
+ * there is an edge directly connecting Node i to Node j.  All other routes designate
+ * the edge which the route to that Node initially takes, by designating a Node
+ * to which a direct connection exists.  That is, the route to non-adjacent Node j
+ * from Node i specifies Node k where Node i directly connects to Node k.
+ *
+ *@code
+ * pseudo definition of compressed graph:
+ * typedef struct
+ * {
+ *     // First byte
+ *     UINT8 broadcast[8]:1;   // that is, 8 1-bit values
+ *     // Second byte
+ *     UINT8 requestRoute:4;   // [3:0]
+ *     UINT8 responseRoute:4;  // [7:4]
+ * } sRoute;
+ * typedef struct
+ * {
+ *     UINT8 size;
+ *     sRoute graph[size][size];
+ * } sGraph;
+ *@endcode
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+GetAmdTopolist (
+  OUT   UINT8    ***List
+  );
+
+UINT8
+GraphHowManyNodes (
+  IN       UINT8    *Graph
+  );
+
+BOOLEAN
+GraphIsAdjacent (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetRsp (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetReq (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetBc (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+#endif  /* _HT_GRAPH_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c
new file mode 100644
index 0000000000..70da5a2689
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * External Interface implementation.
+ *
+ * Contains routines for implementing the interface to the client BIOS.
+ * This file includes the interface access constructor.
+ * This file implements build options using conditional compilation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "CommonReturns.h"
+#include "htInterfaceGeneral.h"
+#include "htInterfaceCoherent.h"
+#include "htInterfaceNonCoherent.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTINTERFACE_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * The default initializer for the HT internal interface, full features.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceDefault =
+{
+  GetCpu2CpuPcbLimits,
+  GetSkipRegang,
+  NewHopCountTable,
+  GetOverrideBusNumbers,
+  GetManualBuidSwapList,
+  GetDeviceCapOverride,
+  GetIoPcbLimits,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  CleanMapsAfterError,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * The initializer for the HT internal interface, coherent only features.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceCoherentOnly =
+{
+  GetCpu2CpuPcbLimits,
+  GetSkipRegang,
+  NewHopCountTable,
+  GetOverrideBusNumbers,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  CleanMapsAfterError,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * The non-coherent only build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceNonCoherentOnly =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  GetOverrideBusNumbers,
+  GetManualBuidSwapList,
+  GetDeviceCapOverride,
+  GetIoPcbLimits,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * Topology Maps only feature build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceMapsOnly =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
+  (PF_GET_IGNORE_LINK)CommonReturnFalse,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  SetNodeToSocketMap,
+  (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
+};
+
+/**
+ * No features build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceNone =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
+  (PF_GET_IGNORE_LINK)CommonReturnFalse,
+  (PF_POST_MAP_TO_AP)CommonVoid,
+  (PF_NEW_NODE_AND_SOCKET_TABLES)CommonVoid,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  (PF_SET_NODE_TO_SOCKET_MAP)CommonVoid,
+  (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
+};
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * A constructor for the internal Ht Interface.
+ *
+ * The install has a reference to the initializer appropriate to the user selected build
+ * options.  Use the selected initializer to construct the internal interface.
+ *
+ * @param[in,out]   HtInterface    Contains pointer to HT Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header
+ *
+*/
+VOID
+NewHtInterface (
+     OUT   HT_INTERFACE         *HtInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) HtInterface,
+    (VOID *) OptionHtConfiguration.HtOptionInternalInterface,
+    (sizeof (HT_INTERFACE)),
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * A "constructor" for the HyperTransport external interface.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * Copy the initial default values from the build options tables to the interface struct.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) AmdHtInterface,
+    (VOID *) OptionHtConfiguration.HtOptionPlatformDefaults,
+    (UINT32) (sizeof (AMD_HT_INTERFACE)),
+    StdHeader
+    );
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.h
new file mode 100644
index 0000000000..c20c294706
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.h
@@ -0,0 +1,516 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Internal access to HT Interface.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * This file includes the interface access constructor and interface
+ * support which is not removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $        @e  \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_H_
+#define _HT_INTERFACE_H_
+
+/**
+ * @page htimplintf HT Internal Interface Implementation Guide
+ *
+ * HT Internal Interface provides access to the HT Component external interface (see AGESA.h),
+ * in a manner that isolates calling code from knowledge about the external interface or which
+ * interfaces are supported in the current build.
+ *
+ * @par Adding a Method to HT Internal Interface
+ *
+ * To add a new method to the HT Internal Interface, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME  </tt> @n
+ *   </ul>
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtInterfaceInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the HT_INTERFACE struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an HT Internal Interface Instance of the method.
+ *
+ * To implement an instance of a method for a specific interface  follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the method typedef.
+ *
+ * - Name the function MethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtInterfaceMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other Ht internal interface routines or data as part of the method implementation, the function
+ *   must use HtInterface->OtherMethod().  Do not directly access other HT internal interface
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple families.
+ *
+ * - Add the instance to the HT_INTERFACE instances.
+ *
+ * - If a configuration does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking HT Internal Interface Methods.
+ *
+ * The first step is carried out only once by the top level HT entry point.
+ * @n @code
+ *   HT_INTERFACE HtInterface;
+ *   // Get the current HT internal interface (to HtBlock data)
+ *   NewHtInterface (&HtInterface);
+ *   State->HtInterface = &HtInterface;
+ * @endcode
+ *
+ * The following example shows how to invoke a HT Internal Interface method.
+ * @n @code
+ *    State->HtInterface->MethodName ();
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     NodeA            One Node on which this Link is located
+ * @param[in]     LinkA            The Link on this Node
+ * @param[in]     NodeB            The other Node on which this Link is located
+ * @param[in]     LinkB            The Link on that Node
+ * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
+ * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap       modify to change the Link's frequency capability
+ * @param[in]     State            the input data
+ *
+ */
+typedef VOID F_GET_CPU_2_CPU_PCB_LIMITS (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_CPU_2_CPU_PCB_LIMITS *PF_GET_CPU_2_CPU_PCB_LIMITS;
+
+/**
+ * Skip reganging of subLinks.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     NodeA    One Node on which this Link is located
+ * @param[in]     LinkA    The Link on this Node
+ * @param[in]     NodeB    The other Node on which this Link is located
+ * @param[in]     LinkB    The Link on that Node
+ * @param[in]     State    the input data
+ *
+ * @retval        MATCHED      leave Link unganged
+ * @retval        POWERED_OFF  leave link unganged and power off the paired sublink
+ * @retval        UNMATCHED    regang Link automatically
+ */
+typedef FINAL_LINK_STATE F_GET_SKIP_REGANG (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_SKIP_REGANG *PF_GET_SKIP_REGANG;
+
+/**
+ * Manually control bus number assignment.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node      The Node on which this chain is located
+ * @param[in]     Link      The Link on the host for this chain
+ * @param[out]    SecBus    Secondary Bus number for this non-coherent chain
+ * @param[out]    SubBus    Subordinate Bus number
+ * @param[in]     State     the input data
+ *
+ * @retval        TRUE      this routine is supplying the bus numbers
+ * @retval        FALSE     use auto Bus numbering
+ */
+typedef BOOLEAN F_GET_OVERRIDE_BUS_NUMBERS (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_OVERRIDE_BUS_NUMBERS *PF_GET_OVERRIDE_BUS_NUMBERS;
+
+/**
+ * Get Manual BUID assignment list.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]    Node    The Node on which this chain is located
+ * @param[in]    Link    The Link on the host for this chain
+ * @param[out]   List    a pointer to a list, if returns TRUE
+ * @param[in]    State   the input data
+ *
+ * @retval      TRUE     use manual List
+ * @retval      FALSE    initialize the Link automatically. List not valid.
+ */
+typedef BOOLEAN F_GET_MANUAL_BUID_SWAP_LIST (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  );
+/// Reference to a method.
+typedef F_GET_MANUAL_BUID_SWAP_LIST *PF_GET_MANUAL_BUID_SWAP_LIST;
+
+/**
+ * Override capabilities of a device.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     HostNode      The Node on which this chain is located
+ * @param[in]     HostLink      The Link on the host for this chain
+ * @param[in]     Depth         The Depth in the I/O chain from the Host
+ * @param[in]     PciAddress    The Device's PCI config address (for callout)
+ * @param[in]     DevVenId      The Device's PCI Vendor + Device ID (offset 0x00)
+ * @param[in]     Revision      The Device's PCI Revision
+ * @param[in]     Link          The Device's Link number (0 or 1)
+ * @param[in,out] LinkWidthIn   modify to change the Link Width In
+ * @param[in,out] LinkWidthOut  modify to change the Link Width Out
+ * @param[in,out] FreqCap       modify to change the Link's frequency capability
+ * @param[in,out] Clumping      modify to change unit id clumping capability
+ * @param[in]     State         the input data
+ *
+ */
+typedef VOID F_GET_DEVICE_CAP_OVERRIDE (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  );
+/// Reference to a method.
+typedef F_GET_DEVICE_CAP_OVERRIDE *PF_GET_DEVICE_CAP_OVERRIDE;
+
+/**
+ * Get limits for non-coherent Links.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     HostNode                   The Node on which this Link is located
+ * @param[in]     HostLink                   The Link about to be initialized
+ * @param[in]     Depth                      The Depth in the I/O chain from the Host
+ * @param[in,out] DownstreamLinkWidthLimit   modify to change the Link Width In
+ * @param[in,out] UpstreamLinkWidthLimit     modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap                 modify to change the Link's frequency capability
+ * @param[in]     State                      the input data
+ */
+typedef VOID F_GET_IO_PCB_LIMITS (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_IO_PCB_LIMITS *PF_GET_IO_PCB_LIMITS;
+
+/**
+ * Get the Socket number for a given Node number.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node    Node discovered event data.
+ * @param[in]     State   reference to Node to socket map
+ *
+ * @return the socket id
+ *
+ */
+typedef UINT8 F_GET_SOCKET_FROM_MAP (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_GET_SOCKET_FROM_MAP *PF_GET_SOCKET_FROM_MAP;
+
+/**
+ * Ignore a Link.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node   The Node on which this Link is located
+ * @param[in]     Link   The Link about to be initialized
+ * @param[in]     NbList The northbridge default ignore link list
+ * @param[in]     State   the input data
+ *
+ * @retval        MATCHED     ignore this Link and skip it
+ * @retval        POWERED_OFF ignore this link and power it off.
+ * @retval        UNMATCHED   initialize the Link normally
+ */
+typedef FINAL_LINK_STATE F_GET_IGNORE_LINK (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       IGNORE_LINK  *NbIgnoreLinkList,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_IGNORE_LINK *PF_GET_IGNORE_LINK;
+
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] State Our state
+ */
+typedef VOID F_POST_MAP_TO_AP (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_POST_MAP_TO_AP *PF_POST_MAP_TO_AP;
+
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] State Our state
+ */
+typedef VOID F_CLEAN_MAPS_AFTER_ERROR (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_CLEAN_MAPS_AFTER_ERROR *PF_CLEAN_MAPS_AFTER_ERROR;
+
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in,out] State global state
+ */
+typedef VOID F_NEW_NODE_AND_SOCKET_TABLES (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_NEW_NODE_AND_SOCKET_TABLES *PF_NEW_NODE_AND_SOCKET_TABLES;
+
+/**
+ * Fill in the socket's Node id when a processor is discovered in that socket.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] Node                Node from which a new node was discovered
+ * @param[in] CurrentNodeModule   The current node's module id in it's processor.
+ * @param[in] PackageLink         The package level link from Node to NewNode.
+ * @param[in] NewNode             The new node's id
+ * @param[in] HardwareSocket      If we use the hardware method (preferred), this is the socket of new node.
+ * @param[in] Module              The new node's module id in it's processor.
+ * @param[in] State               our State
+ */
+typedef VOID F_SET_NODE_TO_SOCKET_MAP (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_SET_NODE_TO_SOCKET_MAP *PF_SET_NODE_TO_SOCKET_MAP;
+
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in,out]   State    Keep our buffer handle.
+ *
+ */
+typedef VOID F_NEW_HOP_COUNT_TABLE (
+  IN OUT   STATE_DATA     *State
+  );
+/// Reference to a method.
+typedef F_NEW_HOP_COUNT_TABLE *PF_NEW_HOP_COUNT_TABLE;
+
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ * @HtInterfaceInstances.
+ *
+ * Invoke the CPU component power mgt interface.
+ *
+ * @param[in]    PlatformConfig   Platform profile/build option config structure.
+ * @param[in]    StdHeader        Config for library and services.
+ *
+ * @return Frequency in MHz.
+ *
+ */
+typedef UINT32 F_GET_MIN_NB_CORE_FREQ (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_MIN_NB_CORE_FREQ *PF_GET_MIN_NB_CORE_FREQ;
+
+/**
+ * The HT Interface, feature code uses these methods to get interface parameters.
+ */
+struct _HT_INTERFACE {                                // See Forward Declaration in HtFeates.h
+  PF_GET_CPU_2_CPU_PCB_LIMITS GetCpu2CpuPcbLimits;    /**< Method: Get link limits for coherent links. */
+  PF_GET_SKIP_REGANG GetSkipRegang;                   /**< Method: Skip reganging for coherent links. */
+  PF_NEW_HOP_COUNT_TABLE NewHopCountTable;            /**< Method: Get a new hop count table. */
+  PF_GET_OVERRIDE_BUS_NUMBERS GetOverrideBusNumbers;  /**< Method: Control Bus number assignment. */
+  PF_GET_MANUAL_BUID_SWAP_LIST GetManualBuidSwapList; /**< Method: Assign device IDs. */
+  PF_GET_DEVICE_CAP_OVERRIDE GetDeviceCapOverride;    /**< Method: Override Device capabilities. */
+  PF_GET_IO_PCB_LIMITS GetIoPcbLimits;                /**< Method: Get link limits for noncoherent links. */
+  PF_GET_SOCKET_FROM_MAP GetSocketFromMap;            /**< Method: Get the Socket for a node id. */
+  PF_GET_IGNORE_LINK GetIgnoreLink;                   /**< Method: Ignore a link. */
+  PF_POST_MAP_TO_AP PostMapToAp;                      /**< Method: Post Socket and other info to AP cores. */
+  PF_NEW_NODE_AND_SOCKET_TABLES NewNodeAndSocketTables; /**< Method: Get new socket and node maps. */
+  PF_CLEAN_MAPS_AFTER_ERROR CleanMapsAfterError;       /**< Method: Clean up maps for forced 1P on error fall back. */
+  PF_SET_NODE_TO_SOCKET_MAP SetNodeToSocketMap;       /**< Method: Associate a node id with a socket. */
+  PF_GET_MIN_NB_CORE_FREQ GetMinNbCoreFreq;           /**< Method: Get the minimum northbridge frequency */
+} ;
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the internal Ht Interface.
+ *
+*/
+VOID
+NewHtInterface (
+     OUT   HT_INTERFACE         *HtInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif  /* _HT_INTERFACE_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c
new file mode 100644
index 0000000000..c8b7f239b3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c
@@ -0,0 +1,290 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * External Interface implementation for coherent features.
+ *
+ * Contains routines for accessing the interface to the client BIOS,
+ * for support only required for coherent features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htInterfaceCoherent.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS}
+ *
+ * For each coherent connection this routine is called once.  Update the frequency
+ * and width if needed for this Link (usually based on board restriction).  This is
+ * used with CPU device capabilities and northbridge limits to compute the default
+ * settings.  The input width and frequency are valid, but do not necessarily reflect
+ * the minimum setting that will be chosen.
+ *
+ * @param[in]     NodeA One Node on which this Link is located
+ * @param[in]     LinkA The Link on this Node
+ * @param[in]     NodeB The other Node on which this Link is located
+ * @param[in]     LinkB The Link on that Node
+ * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
+ * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
+ * @param[in]     State the input data
+ *
+ */
+VOID
+GetCpu2CpuPcbLimits (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  )
+{
+  CPU_TO_CPU_PCB_LIMITS *p;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+
+  ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
+  ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
+
+  SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
+  PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
+  SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
+  PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
+
+  if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) {
+    p = State->HtBlock->CpuToCpuPcbLimitsList;
+
+    while (p->SocketA != HT_LIST_TERMINAL) {
+      if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
+          ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
+           ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
+        // Found a match, update width and frequency
+        *ABLinkWidthLimit = p->ABLinkWidthLimit;
+        *BALinkWidthLimit = p->BALinkWidthLimit;
+        *PcbFreqCap = p->PcbFreqCap;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Skip reganging of subLinks.
+ *
+ * @HtInterfaceMethod{::F_GET_SKIP_REGANG}
+ *
+ * This routine is called whenever two subLinks are both connected to the same CPUs.
+ * Normally, unganged sublinks between the same two CPUs are reganged.  Return true
+ * from this routine to leave the Links unganged.
+ *
+ * @param[in]     NodeA    One Node on which this Link is located
+ * @param[in]     LinkA    The Link on this Node
+ * @param[in]     NodeB    The other Node on which this Link is located
+ * @param[in]     LinkB    The Link on that Node
+ * @param[in]     State     the input data
+ *
+ * @retval        MATCHED      leave Link unganged
+ * @retval        POWERED_OFF  leave link unganged and power off the paired sublink
+ * @retval        UNMATCHED    regang Link automatically
+ */
+FINAL_LINK_STATE
+GetSkipRegang (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  )
+{
+  SKIP_REGANG *p;
+  FINAL_LINK_STATE Result;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+
+  ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
+  ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
+
+  Result = UNMATCHED;
+  SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
+  PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
+  SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
+  PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
+
+  if (State->HtBlock->SkipRegangList != NULL) {
+    p = State->HtBlock->SkipRegangList;
+
+    while (p->SocketA != HT_LIST_TERMINAL) {
+      if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+            ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
+          ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
+            ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
+        // Found a match return final link state
+        Result = p->LinkState;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE}
+ *
+ * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a
+ * known signature.
+ *
+ * @param[in,out]   State    Keep our buffer handle.
+ *
+ */
+VOID
+NewHopCountTable (
+  IN OUT   STATE_DATA     *State
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE);
+  AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr;
+  } else {
+    State->HopCountTable = NULL;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.h
new file mode 100644
index 0000000000..c6fed06cf1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.h
@@ -0,0 +1,141 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Internal access to HT Interface for coherent features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $        @e  \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_COHERENT_H_
+#define _HT_INTERFACE_COHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ */
+VOID
+GetCpu2CpuPcbLimits (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Skip reganging of subLinks.
+ *
+ */
+FINAL_LINK_STATE
+GetSkipRegang (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ */
+VOID
+NewHopCountTable (
+  IN OUT   STATE_DATA     *State
+  );
+
+#endif  /* _HT_INTERFACE_COHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c
new file mode 100644
index 0000000000..7055bfa6b9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c
@@ -0,0 +1,565 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * External Interface implementation, general purpose features.
+ *
+ * Contains routines for implementing the interface to the client BIOS.  This file
+ * includes the interface support which is not removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMultiSocket.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNb.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTINTERFACEGENERAL_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is PackageLink an Internal Link?
+ *
+ * This is a test for the logical link match codes in the user interface, not a test for
+ * the actual northbridge links.
+ *
+ * @param[in]    PackageLink   The link
+ *
+ * @retval       TRUE          This is an internal link
+ * @retval       FALSE         This is not an internal link
+ */
+BOOLEAN
+IsPackageLinkInternal (
+  IN       UINT8  PackageLink
+  )
+{
+  return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Ignore a Link.
+ *
+ * @HtInterfaceMethod{::F_GET_IGNORE_LINK}
+ *
+ * This routine is called every time a coherent Link is found and then every time a
+ * non-coherent Link from a CPU is found.  Any coherent or non-coherent Link from a
+ * CPU can be ignored and not used for discovery or initialization.  Useful for
+ * connection based systems.
+ *
+ * @note not called for IO device to IO Device Links.
+ *
+ * @param[in]     Node             The Node on which this Link is located
+ * @param[in]     Link             The Link about to be initialized
+ * @param[in]     NbIgnoreLinkList The northbridge default ignore link list
+ * @param[in]     State            the input data
+ *
+ * @retval        MATCHED     ignore this Link and skip it
+ * @retval        POWERED_OFF ignore this link and power it off.
+ * @retval        UNMATCHED   initialize the Link normally
+ */
+FINAL_LINK_STATE
+GetIgnoreLink (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+  IN       IGNORE_LINK     *NbIgnoreLinkList,
+  IN       STATE_DATA      *State
+  )
+{
+  IGNORE_LINK *p;
+  FINAL_LINK_STATE Result;
+  BOOLEAN IsFound;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  Result = UNMATCHED;
+  IsFound = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->IgnoreLinkList != NULL) {
+    p = State->HtBlock->IgnoreLinkList;
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
+        // Found a match return the desired link state.
+        ASSERT (Result < MaxFinalLinkState);
+        Result = p->LinkState;
+        IsFound = TRUE;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // If there wasn't a match in the user interface, see if the northbridge provides one.
+  if (!IsFound && (NbIgnoreLinkList != NULL)) {
+    p = NbIgnoreLinkList;
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
+        // Found a match return the desired link state.
+        ASSERT (Result < MaxFinalLinkState);
+        Result = p->LinkState;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Socket number for a given Node number.
+ *
+ * @HtInterfaceMethod{::F_GET_SOCKET_FROM_MAP}
+ *
+ * Return the id.
+ *
+ * @param[in]     Node    The Node to translate
+ * @param[in]     State   reference to Node to socket map
+ *
+ * @return the socket id
+ *
+ */
+UINT8
+GetSocketFromMap (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  )
+{
+  UINT8 Socket;
+
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  Socket = (*State->NodeToSocketDieMap)[Node].Socket;
+  return Socket;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ * @HtInterfaceMethod{::F_NEW_NODE_AND_SOCKET_TABLES}
+ *
+ * Put the Socket Die Table in heap with a known handle.  Content will be generated as
+ * each node is discovered.
+ *
+ * @param[in,out] State global state
+ */
+VOID
+NewNodeAndSocketTables (
+  IN OUT   STATE_DATA *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  // Allocate heap for the table
+  State->SocketDieToNodeMap = NULL;
+  AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM));
+  AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr;
+    // Initialize shared data structures
+    for (i = 0; i < MAX_SOCKETS; i++) {
+      for (j = 0; j < MAX_DIES; j++) {
+        (*State->SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Allocate heap for the table
+  State->NodeToSocketDieMap = NULL;
+  AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM));
+  AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr;
+    // Initialize shared data structures
+    for (i = 0; i < MAX_NODES; i++) {
+      (*State->NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL;
+      (*State->NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ * @HtInterfaceMethod{::F_GET_MIN_NB_CORE_FREQ}
+ *
+ * Invoke the CPU component power mgt interface.
+ *
+ * @param[in]    PlatformConfig   Platform profile/build option config structure.
+ * @param[in]    StdHeader        Config for library and services.
+ *
+ * @return Frequency in MHz.
+ *
+ */
+UINT32
+GetMinNbCoreFreq (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 MinSysNbFreq;
+  UINT32 MinP0NbFreq;
+
+  OptionMultiSocketConfiguration.GetMinNbCof (PlatformConfig, &MinSysNbFreq, &MinP0NbFreq, StdHeader);
+
+  ASSERT (MinSysNbFreq != 0);
+
+  return MinSysNbFreq;
+}
+
+/**
+ * @page physicalsockethowto Physical Socket Map, How To Create
+ *
+ *  To create a physical system socket map for a platform:
+ *
+ *  - Start at the Node which will be the BSP.
+ *
+ *  - Begin a breadth first enumeration of all the coherent Links between sockets
+ *  by creating a socket structure for each socket connection from the BSP.
+ *  For example, if the BSP is in socket zero and Link one connects to socket two,
+ *  create socket {0, 1, 2}.
+ *
+ *  - When all Links from the BSP are described, go to the first socket connected
+ *  to the BSP and continue the breadth first enumeration.
+ *
+ *  - It should not be necessary to describe the back Links; in the example above, there
+ *  should be no need to create {2, 1, 0} (assuming socket two connects back to
+ *  socket zero on its Link one).
+ *
+ *  - When completed:
+ *
+ *     - Every socket except the BSP's (usually zero) must be listed as a targetSocket,
+ *     at least once.  Some sockets may be listed more than once.
+ *
+ *     - There usually should be at least as many entries as Links. An exception is a
+ *     fully connected system, only the Links from the BSP are needed.
+ *
+ *     - Every socket but the last one in the breadth first order should usually have one
+ *     or more entries listing it as a currentSocket. (The last one has only back Links.)
+ *
+ *  There are no strict assumptions about the ordering of the socket structures.
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update maps between Sockets and Nodes for a specific newly discovered node.
+ *
+ * @HtInterfaceMethod{::F_SET_NODE_TO_SOCKET_MAP}
+ *
+ * There are two methods for providing socket naming of nodes.
+ *
+ * Hardware Method (preferred):  A value strapped in hardware by the board is read and
+ * passed to this routine.
+ *
+ * Software Method:  The current node's socket is looked up, since it was
+ * previously a new node and went through this process. The link is converted to
+ * a package level link.  A user data structure describing the package level
+ * layout of the system is searched for the current node's socket and package link,
+ * and now we know the new node's socket.
+ *
+ * In either case, the Socket, Module to Node map and the Node to Socket, Module
+ * map are updated with the new node, socket, and module.
+ *
+ * Data needed to do this is passed in to the routine as arguments rather than read by this routine,
+ * so that it is not necessary to know a valid temporary route to either node at the time this code runs.
+ *
+ * @param[in] Node           Node from which a new node was discovered
+ * @param[in] CurrentNodeModule  The current node's module id in it's processor.
+ * @param[in] PackageLink    The package link for the current node's link.
+ * @param[in] NewNode        The new node's id
+ * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node.
+ * @param[in] Module         The new node's module id in it's processor.
+ * @param[in] State          our State
+ */
+VOID
+SetNodeToSocketMap (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 SourceSocket;
+  UINT8 TargetSocket;
+  SYSTEM_PHYSICAL_SOCKET_MAP *Map;
+
+  // While this code could be written to recover from a NULL socket map, AGESA cannot function without one.
+  ASSERT (State->SocketDieToNodeMap != NULL);
+
+  if (State->HtBlock->SystemPhysicalSocketMap != NULL) {
+    if (NewNode != 0) {
+      // Find the logical Node from which a new Node was discovered in the Node field of
+      // some socket.  It must already be there, Nodes are assigned ascending.
+      //
+      for (SourceSocket = 0; SourceSocket < MAX_SOCKETS; SourceSocket++) {
+        if ((*State->SocketDieToNodeMap)[SourceSocket][CurrentNodeModule].Node == Node) {
+          break;
+        }
+      }
+      // This ASSERT should be understood as "the Node did not have a match", not as a limit check on SourceSocket.
+      ASSERT (SourceSocket != MAX_SOCKETS);
+
+      // Find the sourceSocket in the CurrentSocket field, for the Link on which a new Node
+      // was discovered.  When we find an entry with that socket and Link number, update the
+      // Node for that socket.
+      //
+      if (IsPackageLinkInternal (PackageLink)) {
+        // Internal Nodes are in the same socket, don't search the physical system map.
+        TargetSocket = SourceSocket;
+      } else {
+        // Find the target socket in the physical system map.
+        Map = State->HtBlock->SystemPhysicalSocketMap;
+        while ((Map->CurrentSocket != 0xFF) &&
+               ((Map->CurrentSocket != SourceSocket) || (Map->CurrentLink != PackageLink))) {
+          Map++;
+        }
+        ASSERT (Map->CurrentSocket != 0xFF);
+        TargetSocket = Map->TargetSocket;
+      }
+    } else {
+      // The BSP (BSN, if you will) has no predecessor node from which it is discovered.
+      TargetSocket = 0;
+    }
+  } else {
+    // Use the hardware method
+    // The hardware strapped socket id is passed to us in this case.
+    TargetSocket = HardwareSocket;
+  }
+  // If the target socket, module is already mapped to something, that's not good.  Socket labeling conflict.
+    // Check that the board is strapped correctly. If not you need a SystemPhysicalSocketMap.  If you have one,
+    // check it for correctness.
+  ASSERT ((*State->SocketDieToNodeMap)[TargetSocket][Module].Node == 0xFF);
+  // Update the map for the rest of agesa
+  (*State->SocketDieToNodeMap)[TargetSocket][Module].Node = NewNode;
+  // and the node to socket map
+  ASSERT (State->NodeToSocketDieMap != NULL);
+  (*State->NodeToSocketDieMap)[NewNode].Socket = TargetSocket;
+  (*State->NodeToSocketDieMap)[NewNode].Die = Module;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ * @HtInterfaceMethod{::F_CLEAN_MAPS_AFTER_ERROR}
+ *
+ * @param[in] State Our state, access to socket, node maps
+ *
+ */
+VOID
+CleanMapsAfterError (
+  IN       STATE_DATA *State
+  )
+{
+  UINTN  Socket;
+  UINTN  Module;
+  UINTN  Node;
+
+  ASSERT (State->NodeToSocketDieMap != NULL);
+  ASSERT (State->SocketDieToNodeMap != NULL);
+
+  // Clear all the socket, module items except for the socket and module containing node zero.
+  for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
+    for (Module = 0; Module < MAX_DIES; Module++) {
+      if (((*State->NodeToSocketDieMap)[0].Socket != Socket) || ((*State->NodeToSocketDieMap)[0].Die != Module)) {
+        (*State->SocketDieToNodeMap)[Socket][Module].Node = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[Socket][Module].LowCore = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[Socket][Module].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Clear all the node items except for node zero.
+  for (Node = 1; Node < MAX_NODES; Node++) {
+    (*State->NodeToSocketDieMap)[Node].Socket = HT_LIST_TERMINAL;
+    (*State->NodeToSocketDieMap)[Node].Die = HT_LIST_TERMINAL;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ * @HtInterfaceMethod{::F_POST_MAP_TO_AP}
+ *
+ * Since Ap's can not view map until after mp communication is established,
+ * provide them with initial context info via a mailbox register. A mailbox
+ * register is one that can be written in PCI space and read in MSR space.
+ *
+ * @param[in] State Our state, access to socket, node maps
+ */
+VOID
+PostMapToAp (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 ModuleType;
+  UINT8 Module;
+  AP_MAILBOXES ApMailboxes;
+  UINT8 Node;
+  UINT32 Degree;
+  AGESA_STATUS CalledStatus;
+
+  // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed.
+  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features after HT discovery\n");
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle);
+
+  ASSERT (State->Fabric != NULL);
+  Degree = 0;
+  // Compute the degree of the system by finding the maximum degree of any node.
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    if (State->Fabric->SysDegree[Node] > Degree) {
+      Degree = State->Fabric->SysDegree[Node];
+    }
+  }
+  // Post the information on all nodes.
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    ModuleType = 0;
+    Module = 0;
+    State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb);
+    ApMailboxes.ApMailInfo.Info = 0;
+    ApMailboxes.ApMailInfo.Fields.Node = Node;
+    ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State);
+    ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType;
+    ApMailboxes.ApMailInfo.Fields.Module = Module;
+    ApMailboxes.ApMailExtInfo.Info = 0;
+    ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree;
+    // other fields of the extended info are used during ap init, and will be initialized at that time.
+    State->Nb->PostMailbox (Node, ApMailboxes, State->Nb);
+  }
+  // Now that the mailboxes have been initialized, cache the info on the BSC.  The APs
+  // will cache during heap initialization.
+  CacheApMailbox (State->ConfigHandle);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.h
new file mode 100644
index 0000000000..96fee5a9d7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.h
@@ -0,0 +1,188 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Internal access to HT Interface, general purpose features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * external interface.
+ *
+ * This file includes the interface support which is not removed with
+ * various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $        @e  \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_GENERAL_H_
+#define _HT_INTERFACE_GENERAL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Is PackageLink an Internal Link?
+ */
+BOOLEAN
+IsPackageLinkInternal (
+  IN       UINT8  PackageLink
+  );
+
+/**
+ * Get the Socket number for a given Node number.
+ *
+ */
+UINT8
+GetSocketFromMap (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  );
+
+/**
+ * Ignore a Link.
+ *
+ */
+FINAL_LINK_STATE
+GetIgnoreLink (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       IGNORE_LINK  *NbIgnoreLinkList,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ */
+VOID
+NewNodeAndSocketTables (
+  IN OUT   STATE_DATA *State
+  );
+
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ */
+UINT32
+GetMinNbCoreFreq (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Fill in the socket's Node id when a processor is discovered in that socket.
+ *
+ */
+VOID
+SetNodeToSocketMap (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  );
+
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ */
+VOID
+CleanMapsAfterError (
+  IN       STATE_DATA *State
+  );
+
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ */
+VOID
+PostMapToAp (
+  IN       STATE_DATA *State
+  );
+
+#endif  /* _HT_INTERFACE_GENERAL_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
new file mode 100644
index 0000000000..8a34a25f99
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
@@ -0,0 +1,420 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * External Interface implementation for non-coherent features.
+ *
+ * Contains routines for accessing the interface to the client BIOS,
+ * for non-coherent features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceNonCoherent.h"
+#include "htNb.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTINTERFACENONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_ZERO_32 ((UINT32)0)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Manual BUID assignment list.
+ *
+ * @HtInterfaceMethod{::F_GET_MANUAL_BUID_SWAP_LIST}
+ *
+ * This routine is called every time a non-coherent chain is processed.  BUID
+ * assignment may be controlled explicitly on a non-coherent chain. Swaps controls
+ * the BUID assignment and FinalIds provides the device to device Linking.  Device
+ * orientation can be detected automatically, or explicitly.  See documentation for
+ * more details.
+ *
+ * If a manual swap list is not supplied, automatic non-coherent init assigns BUIDs
+ * starting at 1 and incrementing sequentially based on each device's unit count.
+ *
+ * @param[in]    Node    The Node on which this chain is located
+ * @param[in]    Link    The Link on the host for this chain
+ * @param[out]   List    supply a pointer to a list.
+ *                       List is NOT valid unless routine returns TRUE.
+ * @param[in]    State   the input data
+ *
+ * @retval      TRUE     use a manual list
+ * @retval      FALSE    initialize the Link automatically
+ */
+BOOLEAN
+GetManualBuidSwapList (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  )
+{
+  MANUAL_BUID_SWAP_LIST *p;
+  BOOLEAN result;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (List != NULL));
+
+  result = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->ManualBuidSwapList != NULL) {
+    p = State->HtBlock->ManualBuidSwapList;
+
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
+        // Found a match implies TRUE, ignore the Link
+        result = TRUE;
+        *List = &(p->SwapList);
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // List is not valid if Result is FALSE.
+  return result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Override capabilities of a device.
+ *
+ * @HtInterfaceMethod{::F_GET_DEVICE_CAP_OVERRIDE}
+ *
+ * This routine is called once for every Link on every IO device.  Update the width
+ * and frequency capability if needed for this device.  This is used along with
+ * device capabilities, the limit call backs, and northbridge limits to compute the
+ * default settings.  The components of the device's PCI config address are provided,
+ * so its settings can be consulted if need be. The input width and frequency are the
+ * reported device capabilities.
+ *
+ * @param[in]     HostNode      The Node on which this chain is located
+ * @param[in]     HostLink      The Link on the host for this chain
+ * @param[in]     Depth         The Depth in the I/O chain from the Host
+ * @param[in]     PciAddress    The Device's PCI config address (for callout)
+ * @param[in]     DevVenId      The Device's PCI Vendor + Device ID (offset 0x00)
+ * @param[in]     Revision      The Device's PCI Revision
+ * @param[in]     Link          The Device's Link number (0 or 1)
+ * @param[in,out] LinkWidthIn   modify to change the Link Width In
+ * @param[in,out] LinkWidthOut  modify to change the Link Width Out
+ * @param[in,out] FreqCap       modify to change the Link's frequency capability
+ * @param[in,out] Clumping      modify to change unit id clumping capability
+ * @param[in]     State         the input data and config header
+ *
+ */
+VOID
+GetDeviceCapOverride (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  )
+{
+  DEVICE_CAP_OVERRIDE *p;
+  UINT8 HostSocket;
+  UINT8 PackageLink;
+  DEVICE_CAP_CALLOUT_PARAMS CalloutParams;
+  AGESA_STATUS CalloutStatus;
+
+  ASSERT ((HostNode < MAX_NODES) && (Depth < 32) && ((Link == 0) || (Link == 1)));
+
+  HostSocket = State->HtInterface->GetSocketFromMap (HostNode, State);
+  PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
+
+  if (State->HtBlock->DeviceCapOverrideList != NULL) {
+    p = State->HtBlock->DeviceCapOverrideList;
+
+    while (p->HostSocket != HT_LIST_TERMINAL) {
+      if (((p->HostSocket == HostSocket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
+          ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
+          ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == Link) || (p->Link == HT_LIST_MATCH_ANY)) &&
+          // Found a potential match. Check the additional optional matches.
+          ((p->Options.IsCheckDevVenId == 0) || (p->DevVenId == DevVenId)) &&
+          ((p->Options.IsCheckRevision == 0) || (p->Revision == Revision))) {
+        //
+        // Found a match.  Check what override actions are desired.
+        // Unlike the PCB limit routines, which handle the info returned,
+        // deviceCapOverride is actually overriding the settings, so we need
+        // to check that the field actually has an update.
+        // The Callout is a catch all for situations the data is not up to handling.
+        // It is expected, but not enforced, that either the data overrides are used,
+        // or the callout is used, rather than both.
+        //
+        if (p->Options.IsOverrideWidthIn != 0) {
+          *LinkWidthIn = p->LinkWidthIn;
+        }
+        if (p->Options.IsOverrideWidthOut != 0) {
+          *LinkWidthOut = p->LinkWidthOut;
+        }
+        if (p->Options.IsOverrideFreq != 0) {
+          *FreqCap = p->FreqCap;
+        }
+        if (p->Options.IsOverrideClumping != 0) {
+          *Clumping = p->Clumping;
+        }
+        if (p->Options.IsDoCallout != 0) {
+          //
+          // Pass the actual info being matched, not the matched struct data.
+          // This callout is expected to be built in as part of the options file, and does not use the
+          // callout interface, even though we use the consistent interface declaration for the routine.
+          // So, the first two int parameters have no meaning in this case.
+          // It is not meaningful for the callout to have any status but Success.
+          //
+          CalloutParams.HostSocket = HostSocket;
+          CalloutParams.HostLink = PackageLink;
+          CalloutParams.Depth = Depth;
+          CalloutParams.DevVenId = DevVenId;
+          CalloutParams.Revision = Revision;
+          CalloutParams.Link = Link;
+          CalloutParams.PciAddress = PciAddress;
+          CalloutParams.LinkWidthIn = LinkWidthIn;
+          CalloutParams.LinkWidthOut = LinkWidthOut;
+          CalloutParams.FreqCap = FreqCap;
+          CalloutParams.Clumping = Clumping;
+          CalloutParams.StdHeader = *((AMD_CONFIG_PARAMS *) (State->ConfigHandle));
+          CalloutStatus = p->Callout (UNUSED_ZERO_32, UNUSED_ZERO_32, (VOID *) &CalloutParams);
+          ASSERT (CalloutStatus == AGESA_SUCCESS);
+        }
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get limits for non-coherent Links.
+ *
+ * @HtInterfaceMethod{::F_GET_IO_PCB_LIMITS}
+ *
+ * For each non-coherent connection this routine is called once.  Update the
+ * frequency and width if needed for this Link (usually based on board restriction).
+ * This is used with device capabilities, device overrides, and northbridge limits to
+ * compute the default settings. The input width and frequency are valid, but do not
+ * necessarily reflect the minimum setting that will be chosen.
+ *
+ * @param[in]     HostNode                   The Node on which this Link is located
+ * @param[in]     HostLink                   The Link about to be initialized
+ * @param[in]     Depth                      The Depth in the I/O chain from the Host
+ * @param[in,out] DownstreamLinkWidthLimit   modify to change the Link Width In
+ * @param[in,out] UpstreamLinkWidthLimit     modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap                 modify to change the Link's frequency capability
+ * @param[in]     State                      the input data
+ */
+VOID
+GetIoPcbLimits (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  )
+{
+  IO_PCB_LIMITS *p;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((HostNode < MAX_NODES) && (HostLink < MAX_NODES));
+
+  Socket = State->HtInterface->GetSocketFromMap (HostNode, State);
+  PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
+
+  if (State->HtBlock->IoPcbLimitsList != NULL) {
+    p = State->HtBlock->IoPcbLimitsList;
+
+    while (p->HostSocket != HT_LIST_TERMINAL) {
+      if (((p->HostSocket == Socket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
+          ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
+          ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY))) {
+        // Found a match, return the override info
+        *DownstreamLinkWidthLimit = p->DownstreamLinkWidthLimit;
+        *UpstreamLinkWidthLimit = p->UpstreamLinkWidthLimit;
+        *PcbFreqCap = p->PcbFreqCap;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Manually control bus number assignment.
+ *
+ * @HtInterfaceMethod{::F_GET_OVERRIDE_BUS_NUMBERS}
+ *
+ * This routine is called every time a non-coherent chain is processed.  If a system
+ * can not use the auto Bus numbering feature for non-coherent chain bus assignments,
+ * this routine can provide explicit control.  For each chain, provide the bus number
+ * range to use.
+ *
+ * The outputs SecBus and SubBus are not valid unless this routine returns TRUE
+ *
+ * @param[in]     Node      The Node on which this chain is located
+ * @param[in]     Link      The Link on the host for this chain
+ * @param[out]    SecBus    Secondary Bus number for this non-coherent chain
+ * @param[out]    SubBus    Subordinate Bus number
+ * @param[in]     State     the input data
+ *
+ * @retval        TRUE      this routine is supplying the bus numbers.
+ * @retval        FALSE     use auto Bus numbering, bus outputs not valid.
+ */
+BOOLEAN
+GetOverrideBusNumbers (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  )
+{
+  OVERRIDE_BUS_NUMBERS *p;
+  BOOLEAN result;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  result = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->OverrideBusNumbersList != NULL) {
+    p = State->HtBlock->OverrideBusNumbersList;
+
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
+        // Found a match, return the bus overrides
+        *SecBus = p->SecBus;
+        *SubBus = p->SubBus;
+        ASSERT (*SubBus > *SecBus);
+        result = TRUE;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // SecBus, SubBus are not valid if Result is FALSE.
+  return result;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.h
new file mode 100644
index 0000000000..98f4f06f7f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.h
@@ -0,0 +1,164 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Internal access to HT Interface, for non-coherent features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $        @e  \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_NONCOHERENT_H_
+#define _HT_INTERFACE_NONCOHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Manually control bus number assignment.
+ *
+ */
+BOOLEAN
+GetOverrideBusNumbers (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get Manual BUID assignment list.
+ *
+ */
+BOOLEAN
+GetManualBuidSwapList (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  );
+
+/**
+ * Override capabilities of a device.
+ *
+ */
+
+VOID
+GetDeviceCapOverride (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  );
+
+/**
+ * Get limits for non-coherent Links.
+ *
+ */
+VOID
+GetIoPcbLimits (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+
+#endif  /* _HT_INTERFACE_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c
new file mode 100644
index 0000000000..73fc6b4f12
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c
@@ -0,0 +1,605 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTMAIN_FILECODE
+#define APIC_Base_BSP    8
+#define APIC_Base        0x1b
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+BOOLEAN
+STATIC
+IsBootCore (
+  IN       STATE_DATA    *State
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update maps with the core range for each module.
+ *
+ * Cores are numbered relative to a Processor, but sometimes there is a need to know the
+ * starting and ending core ids on a particular node.  This same info is also useful for
+ * supporting the Core count on a node other than the one currently executing.
+ *
+ * For each Processor, get the core count of each node using the family specific PCI core count
+ * interface. The order of cores in a processor, and whether it is special for the BSP is family
+ * specific.  But whether the processor orders core ids by module or node, iterate in the right
+ * order and use the counts to determine each start and end range.
+ *
+ * Update compute unit status for each node.
+ *
+ * @param[in]   State    number of Nodes discovered.
+*/
+VOID
+STATIC
+UpdateCoreRanges (
+  IN       STATE_DATA    *State
+    )
+{
+  UINT8 Node;
+  UINT8 ProcessorCores;
+  UINT8 ModuleCoreCount[MAX_DIES];
+  UINT8 Socket;
+  UINT8 Module;
+
+  ASSERT (State->SocketDieToNodeMap != NULL);
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
+    // Is a Processor present in Socket?
+    if ((*State->SocketDieToNodeMap)[Socket][0].Node != HT_LIST_TERMINAL) {
+      // Get all the Module core counts for this processor
+      // Note that the core counts are 1 based counts.
+      // Since Compute Unit info is not module ordering dependent, write it now.
+      for (Module = 0; Module < MAX_DIES; Module++) {
+        if ((*State->SocketDieToNodeMap)[Socket][Module].Node != HT_LIST_TERMINAL) {
+          ModuleCoreCount[Module] = State->Nb->GetNumCoresOnNode ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
+          (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits =
+            State->Nb->GetEnabledComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
+          (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits =
+            State->Nb->GetDualCoreComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
+        } else {
+          ModuleCoreCount[Module] = 0;
+        }
+      }
+      // Determine the core ordering rule for this processor.
+      if ((((*State->NodeToSocketDieMap)[0].Socket == Socket) && State->Nb->IsOrderBSPCoresByNode) ||
+          (!State->Nb->IsOrderCoresByModule)) {
+        // Order core ranges on this processor by Node Id.
+        ProcessorCores = 0;
+        for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
+          // Is this node a module in this processor?
+          if ((*State->NodeToSocketDieMap)[Node].Socket == Socket) {
+            Module = (*State->NodeToSocketDieMap)[Node].Die;
+            if (ModuleCoreCount[Module] != 0) {
+              (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
+              (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
+              IDS_HDT_CONSOLE (
+                HT_TRACE,
+                (IsBootCore (State) ?
+                 "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" :
+                 ""),
+                Socket,
+                Module,
+                Node,
+                (*State->SocketDieToNodeMap)[Socket][Module].LowCore,
+                (*State->SocketDieToNodeMap)[Socket][Module].HighCore,
+                (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits,
+                (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits
+                );
+              ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
+            }
+          }
+        }
+      } else {
+        // Order core ranges in this processor by Module Id.
+        ProcessorCores = 0;
+        for (Module = 0; Module < MAX_DIES; Module++) {
+          if (ModuleCoreCount[Module] != 0) {
+            (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
+            (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
+              IDS_HDT_CONSOLE (
+                HT_TRACE,
+                (IsBootCore (State) ?
+                 "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" :
+                 ""),
+                Socket,
+                Module,
+                (*State->SocketDieToNodeMap)[Socket][Module].Node,
+                (*State->SocketDieToNodeMap)[Socket][Module].LowCore,
+                (*State->SocketDieToNodeMap)[Socket][Module].HighCore,
+                (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits,
+                (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits
+                );
+            ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Complete the coherent init with any system level initialization.
+ *
+ * Find the total number of cores and update the number of Nodes and cores in all cpus.
+ * Limit cpu config access to installed cpus.
+ *
+ * @param[in]   State    number of Nodes discovered.
+*/
+VOID
+STATIC
+FinalizeCoherentInit (
+  IN       STATE_DATA    *State
+    )
+{
+  UINT8 Node;
+  UINT8 TotalCores;
+
+  TotalCores = 0;
+
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    TotalCores = TotalCores + State->Nb->GetNumCoresOnNode (Node, State->Nb);
+  }
+
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->SetTotalNodesAndCores (Node, State->NodesDiscovered + 1, TotalCores, State->Nb);
+  }
+
+  // Set all nodes to limit config space based on node count, after all nodes have a valid count.
+  // (just being cautious, probably we could combine the loops.)
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->LimitNodes (Node, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the coherent fabric.
+ *
+ * Perform discovery and initialization of the coherent fabric, for builds including
+ * support for multiple coherent nodes.
+ *
+ * @param[in]   State   global state
+ */
+VOID
+STATIC
+CoherentInit (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 ModuleType;
+  UINT8 Module;
+  UINT8 HardwareSocket;
+  COHERENT_FABRIC Fabric;
+
+  // Because Node 0, the BSP, is not discovered, initialize info about it specially here.
+  // Allocate Socket Die Map.
+  // While the BSP is always capable of being the only processor in the system, call the
+  // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system
+  // capability. We don't care to check the return value.
+  //
+  State->Fabric = &Fabric;
+  State->NodesDiscovered = 0;
+  State->TotalLinks = 0;
+  State->SysMpCap = MAX_NODES;
+  State->Nb->IsExceededCapable (0, State, State->Nb);
+  HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
+  ModuleType = 0;
+  Module = 0;
+  State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb);
+  // No predecessor info for BSP, so pass 0xFF for those parameters.
+  State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State);
+
+  // Initialize system state data structures
+  for (i = 0; i < MAX_NODES; i++) {
+    State->Fabric->SysDegree[i] = 0;
+    for (j = 0; j < MAX_NODES; j++) {
+      State->Fabric->SysMatrix[i][j] = 0;
+    }
+  }
+
+  //
+  // Call the coherent init features
+  //
+
+  // Discovery
+  State->HtFeatures->CoherentDiscovery (State);
+  State->HtInterface->PostMapToAp (State);
+  // Topology matching and Routing
+  AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle);
+  State->HtFeatures->LookupComputeAndLoadRoutingTables (State);
+  State->HtFeatures->MakeHopCountTable (State);
+
+  // UpdateCoreRanges requires the other maps to be initialized, and the node count set.
+  FinalizeCoherentInit (State);
+  UpdateCoreRanges (State);
+  State->Fabric = NULL;
+}
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                             Algorithms                              ***
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the non-coherent fabric.
+ *
+ * Begin with the Compat Link on the BSP, then find and initialize all other
+ * non-coherent chains.
+ *
+ * @param[in]   State    our global state
+ */
+VOID
+STATIC
+NcInit (
+  IN       STATE_DATA    *State
+  )
+{
+  UINT8 Node;
+  UINT8 Link;
+  UINT8 CompatLink;
+  FINAL_LINK_STATE FinalLinkState;
+
+  // Initialize the southbridge chain.
+  State->AutoBusCurrent = State->HtBlock->AutoBusStart;
+  State->UsedCfgMapEntries = 0;
+  CompatLink = State->Nb->ReadSouthbridgeLink (State->Nb);
+  State->HtFeatures->ProcessLink (0, CompatLink, TRUE, State);
+
+  // Find and initialize all other non-coherent chains.
+  for (Node = 0; Node <= State->NodesDiscovered; Node++) {
+    for (Link = 0; Link < State->Nb->MaxLinks; Link++) {
+      // Skip the Link, if any of these tests indicate
+      FinalLinkState = State->HtInterface->GetIgnoreLink (Node, Link, State->Nb->DefaultIgnoreLinkList, State);
+      if (FinalLinkState == UNMATCHED) {
+        if ( !((Node == 0) && (Link == CompatLink))) {
+          if ( !(State->Nb->ReadTrueLinkFailStatus (Node, Link, State, State->Nb))) {
+            if (State->Nb->VerifyLinkIsNonCoherent (Node, Link, State->Nb)) {
+              State->HtFeatures->ProcessLink (Node, Link, FALSE, State);
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Optimize Link Features.
+ *
+ * Based on Link capabilities, apply optimization rules to come up with the best
+ * settings, including several external limit decision from the interface. This includes
+ * handling of subLinks.  Finally, after the port list data is updated, set the hardware
+ * state for all Links.
+ *
+ * @param[in] State our global state
+ */
+VOID
+STATIC
+LinkOptimization (
+  IN       STATE_DATA *State
+  )
+{
+  AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle);
+  State->HtFeatures->GatherLinkData (State);
+
+  AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle);
+  State->HtFeatures->RegangLinks (State);
+
+  AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle);
+  State->HtFeatures->SelectOptimalWidthAndFrequency (State);
+
+  // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing
+  // so check this after doing the sublinks.
+  AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle);
+  State->HtFeatures->SubLinkRatioFixup (State);
+  if (State->HtFeatures->IsCoherentRetryFixup (State)) {
+    // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again.
+    State->HtFeatures->SubLinkRatioFixup (State);
+  }
+
+  AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle);
+  State->HtFeatures->SetLinkData (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Handle system and performance tunings.
+ *
+ * Including traffic distribution, fifo and
+ * buffer tuning that can't be placed in the register table,
+ * and special config tunings.
+ *
+ * @param[in] State    Total Nodes, port list data
+ */
+VOID
+STATIC
+Tuning (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 Node;
+
+  // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table.
+  //
+  AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle);
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->BufferOptimizations (Node, State, State->Nb);
+  }
+
+  // See if traffic distribution can be done and do it if so.
+  //
+  AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle);
+  State->HtFeatures->TrafficDistribution (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map.
+ * The mapping is filled in by reading the AP Mailboxes from PCI config on each node.
+ *
+ * @param[in]    State    global state, input data
+ *
+ */
+VOID
+STATIC
+InitApMaps (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 Node;
+  AP_MAIL_INFO NodeApMailBox;
+
+  // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug.
+  ASSERT (State->SocketDieToNodeMap != NULL);
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
+    /* NodeApMailBox = State->Nb->RetrieveMailbox (Node, State->Nb); */ *(UINT32 *)(&NodeApMailBox) = 0;
+    (*State->SocketDieToNodeMap)[NodeApMailBox.Fields.Socket][NodeApMailBox.Fields.Module].Node = Node;
+    (*State->NodeToSocketDieMap)[Node].Socket = (UINT8)NodeApMailBox.Fields.Socket;
+    (*State->NodeToSocketDieMap)[Node].Die = (UINT8)NodeApMailBox.Fields.Module;
+  }
+  // This requires the other maps to be initialized.
+  UpdateCoreRanges (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is the currently running core the BSC?
+ *
+ * Determine whether the init steps for BSC or AP core should be run.
+ *
+ * @param[in]    State    global state, input data
+ *
+ * @retval       TRUE    This is the boot core.
+ * @retval       FALSE   This is not the boot core.
+ */
+BOOLEAN
+STATIC
+IsBootCore (
+  IN       STATE_DATA    *State
+  )
+{
+  UINT64 Value;
+
+  LibAmdMsrRead (APIC_Base, &Value, State->ConfigHandle);
+
+  return ((BOOLEAN) (((UINT32) (Value & 0xFFFFFFFF) & ((UINT32)1 << APIC_Base_BSP)) != 0));
+}
+
+/***************************************************************************
+ ***                            HT Initialize                             ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  )
+{
+  STATE_DATA State;
+  NORTHBRIDGE Nb;
+  HT_FEATURES HtFeatures;
+  HT_INTERFACE HtInterface;
+  AGESA_STATUS DeallocateStatus;
+  AP_MAIL_INFO ApMailboxInfo;
+  UINT8 ApNode;
+
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  State.HtBlock = AmdHtInterface;
+  State.ConfigHandle = StdHeader;
+  State.PlatformConfiguration = PlatformConfiguration;
+
+  // Get the current HT internal interface (to HtBlock data)
+  NewHtInterface (&HtInterface, State.ConfigHandle);
+  State.HtInterface = &HtInterface;
+
+  // Get the current HT Feature Set
+  NewHtFeatures (&HtFeatures, State.ConfigHandle);
+  State.HtFeatures = &HtFeatures;
+
+  // Initialize from static options
+  State.IsUsingRecoveryHt = OptionHtConfiguration.IsUsingRecoveryHt;
+  State.IsSetHtCrcFlood = OptionHtConfiguration.IsSetHtCrcFlood;
+  State.IsUsingUnitIdClumping = OptionHtConfiguration.IsUsingUnitIdClumping;
+
+  // Initialize for status and event output
+  State.MaxEventClass = AGESA_SUCCESS;
+
+  // Allocate permanent heap structs that are interfaces to other AGESA services.
+  State.HtInterface->NewNodeAndSocketTables (&State);
+
+  if (IsBootCore (&State)) {
+    AGESA_TESTPOINT (TpProcHtEntry, State.ConfigHandle);
+    // Allocate Bsp only interface heap structs.
+    State.HtInterface->NewHopCountTable (&State);
+    // Allocate heap for our temporary working space.
+    AllocHeapParams.RequestedBufferSize = (sizeof (PORT_DESCRIPTOR) * (MAX_PLATFORM_LINKS * 2));
+    AllocHeapParams.BufferHandle = HT_STATE_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, State.ConfigHandle) == AGESA_SUCCESS) {
+      State.PortList = (PORT_LIST)AllocHeapParams.BufferPtr;
+      // Create the BSP's northbridge.
+      NewNorthBridge (0, &State, &Nb);
+      State.Nb = &Nb;
+
+      CoherentInit (&State);
+      NcInit (&State);
+      LinkOptimization (&State);
+      Tuning (&State);
+
+      DeallocateStatus = HeapDeallocateBuffer (HT_STATE_DATA_HANDLE, State.ConfigHandle);
+      ASSERT (DeallocateStatus == AGESA_SUCCESS);
+      AGESA_TESTPOINT (TpProcHtDone, State.ConfigHandle);
+    } else {
+      ASSERT (FALSE);
+      State.MaxEventClass = AGESA_ERROR;
+      // Cannot Log entry due to heap allocate failed.
+    }
+  } else {
+    // Do the AP HT Init, which produces Node and Socket Maps for the AP's use.
+    AGESA_TESTPOINT (TpProcHtApMapEntry, State.ConfigHandle);
+    GetApMailbox (&ApMailboxInfo.Info, State.ConfigHandle);
+    ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
+    ApNode = (UINT8)ApMailboxInfo.Fields.Node;
+    NewNorthBridge (ApNode, &State, &Nb);
+    State.Nb = &Nb;
+    InitApMaps (&State);
+    AGESA_TESTPOINT (TpProcHtApMapDone, State.ConfigHandle);
+  }
+  return State.MaxEventClass;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
new file mode 100644
index 0000000000..bbba43ed6e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
@@ -0,0 +1,274 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Construct a northbridge interface for a Node.
+ *
+ * Handle build options and run-time detection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbCommonHardware.h"
+#include "CommonReturns.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#include "Filecode.h"
+
+#define FILECODE PROC_HT_HTNB_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+
+/**
+ * Initial construction data for no HT Northbridge.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
+{
+  1,
+  (PF_WRITE_ROUTING_TABLE)CommonVoid,
+  (PF_WRITE_NODEID)CommonVoid,
+  (PF_READ_DEFAULT_LINK)CommonReturnZero8,
+  (PF_ENABLE_ROUTING_TABLES)CommonVoid,
+  (PF_DISABLE_ROUTING_TABLES)CommonVoid,
+  (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
+  (PF_READ_TOKEN)CommonReturnZero8,
+  (PF_WRITE_TOKEN)CommonVoid,
+  (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
+  (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
+  (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
+  (PF_STOP_LINK)CommonVoid,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
+  (PF_READ_SB_LINK)CommonReturnZero8,
+  (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse,
+  (PF_SET_CONFIG_ADDR_MAP)CommonVoid,
+  (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32,
+  (PF_GATHER_LINK_FEATURES)CommonVoid,
+  (PF_SET_LINK_REGANG)CommonVoid,
+  (PF_SET_LINK_FREQUENCY)CommonVoid,
+  (PF_SET_LINK_UNITID_CLUMPING)CommonVoid,
+  (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid,
+  (PF_BUFFER_OPTIMIZATIONS)CommonVoid,
+  (PF_GET_NUM_CORES_ON_NODE)CommonReturnZero8,
+  (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid,
+  (PF_GET_NODE_COUNT)CommonReturnZero8,
+  (PF_LIMIT_NODES)CommonVoid,
+  (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse,
+  (PF_GET_NEXT_LINK)CommonReturnZero32,
+  (PF_GET_PACKAGE_LINK)CommonReturnZero8,
+  (PF_MAKE_LINK_BASE)CommonReturnZero32,
+  (PF_GET_MODULE_INFO)CommonVoid,
+  (PF_POST_MAILBOX)CommonVoid,
+  (PF_RETRIEVE_MAILBOX)CommonReturnZero32,
+  (PF_GET_SOCKET)CommonReturnZero8,
+  (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
+  (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
+  0,
+  0,
+  0,
+  TRUE,
+  TRUE,
+  0,
+  NULL,
+  0,
+  NULL,
+  (PF_MAKE_KEY)CommonReturnZero64,
+  NULL
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make a compatibility key.
+ *
+ * @HtNbMethod{::F_MAKE_KEY}
+ *
+ * Private routine to northbridge code.
+ * Create a key which can be used to determine whether a Node is compatible with
+ * the discovered configuration so far.  Currently, that means the family,
+ * extended family of the new Node are the same as the BSP's.  Family specific
+ * implementations can add whatever else is necessary.
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @return the key
+ */
+UINT64
+MakeKey (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+  UINT32 RawCpuId;
+  PCI_ADDR Reg;
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CPUID_3XFC);
+
+  LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, Nb->ConfigHandle);
+  GetLogicalIdFromCpuid (RawCpuId, &LogicalId, Nb->ConfigHandle);
+  return LogicalId.Family;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Construct a new northbridge.
+ *
+ * This routine encapsulates knowledge of how to tell significant differences between
+ * families of supported northbridges and what routines can be used in common and
+ * which are unique.  A fully populated northbridge interface is provided by Nb.
+ *
+ * @param[in]     Node    create a northbridge interface for this Node.
+ * @param[in]     State   global state
+ * @param[out]    Nb      the caller's northbridge structure to initialize.
+ */
+VOID
+NewNorthBridge (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+     OUT   NORTHBRIDGE *Nb
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+  UINT64  Match;
+  UINT32 RawCpuId;
+  PCI_ADDR Reg;
+  NORTHBRIDGE **InitializerInstance;
+
+  // Start with enough of the key to identify the northbridge interface
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CPUID_3XFC);
+  LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle);
+  IDS_HDT_CONSOLE (HT_TRACE, "AMD Processor at Node %d has raw CPUID=%x.\n", Node, RawCpuId);
+  GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle);
+  Match = LogicalId.Family;
+
+  // Test each Northbridge interface in turn looking for a match.
+  // Use it to Init the Nb struct if a match is found.
+  //
+  ASSERT (OptionHtConfiguration.HtOptionFamilyNorthbridgeList != NULL);
+  InitializerInstance = (NORTHBRIDGE **) (OptionHtConfiguration.HtOptionFamilyNorthbridgeList);
+  while (*InitializerInstance != NULL) {
+    if ((Match & (*InitializerInstance)->CompatibleKey) != 0) {
+      LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle);
+      break;
+    }
+    InitializerInstance++;
+  }
+  // There must be an available northbridge implementation.
+  ASSERT (*InitializerInstance != NULL);
+
+  // Set the config handle for passing to the library.
+  Nb->ConfigHandle = State->ConfigHandle;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.h
new file mode 100644
index 0000000000..ecf1ff55d7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.h
@@ -0,0 +1,1160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HT NorthBridge header
+ *
+ * Defines the interface to the HT NorthBridge module for use by other internal
+ * HT modules.  This is not a wrapper or external interface, "public" in the
+ * comments below is used in the class definition style and refers to HT client
+ * modules only ("private" being for use only by the HT NB module itself).
+ *
+ * It is expected that there will be multiple northbridge implementation files all
+ * conforming to this common interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NB_H_
+#define _HT_NB_H_
+
+/**
+ * @page htimplnb HT Northbridge Implementation Guide
+ *
+ * The HT Northbridge provides access to the Northbridge hardware, in a manner that
+ * isolates calling code from knowledge about the hardware implementation or which
+ * features are supported in the current build.  This is the mechanism in the HT code for
+ * supporting new Family or Model northbridges, as well as the means for supporting
+ * multiple northbridges in a single build or mixed revision northbridge sets.
+ *
+ * @par Adding a Method to the Northbridge
+ *
+ * To add a new method to the Northbridge, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same
+ *     name as the method table item, but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
+ *   </ul>
+ *
+ * <li> One of the parameters to @b all northbridge Methods is @b required to be a
+ *   reference to its current northbridge object.  By convention, this is the
+ *   last parameter.
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtNbInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the NORTHBRIDGE struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an Instance of a Northbridge method.
+ *
+ * To implement an instance of a method for a specific feature follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the Method typedef.
+ *   - If the Method implementation is common to all families, use the northbridge file
+ *   for the function area, for example, add a new coherent initialization support method to the
+ *   coherent northbridge file.
+ *   - If the Method implementation is unique to each supported northbridge, use the
+ *   family specific file for that function area (create it, if it doesn't already exist).
+ *   The family specific files have the same name as the common one suffixed with "FamNN",
+ *   or "FamNNRevX" if for a model or revision.
+ *
+ * - Name the function MethodName().  If Family specific, FamNNMethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtNbMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other northbridge routines or data as part of the method implementation,
+ *   the function must use Nb->OtherMethod().  Do not directly access other northbridge
+ *   routines, because in the table there may be overrides or this routine may be shared by
+ *   multiple configurations.
+ *
+ * - Add the instance, or the correct family specific instance, to the NORTHBRIDGE instances
+ *   used by the northbridge constructor.
+ *
+ * - If a northbridge does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Making common Northbridge Methods.
+ *
+ * In some cases, Northbridge methods can easily have a common implementation because the hardware
+ * is very compatible or is even standard.  In other cases, where processor family northbridges
+ * differ in their implementation, it may be possible to provide a single, common method
+ * implementation.  This can be accomplished by adding Northbridge data members.
+ *
+ * For example, a bit position or bit field mask can be used to accommodate different bit placement or size.
+ * Another example, a small table can be used to translate index values from a common set
+ * to specific sets.
+ *
+ * The Northbridge Method Instance must use its NORTHBRIDGE reference parameter to access
+ * private data members.
+ *
+ * @par Invoking HT Northbridge Methods.
+ *
+ * Each unique northbridge is constructed based on matching the current northbridge.
+ * @n @code
+ *   NORTHBRIDGE Nb;
+ *   // Create the BSP's northbridge.
+ *   NewNorthBridge (0, State, &Nb);
+ *   State->Nb = &Nb;
+ * @endcode
+ *
+ * The following example shows how to invoke a Northbridge method.
+ * @n @code
+ *   State->Nb->MethodName (State->Nb);
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/** Use a macro to convert a Node number to a PCI device.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 makePCIDeviceFromNode(UINT8 Node);
+ */
+#define MakePciDeviceFromNode(Node)             \
+  ((UINT8) (24 + (Node)))
+
+/** Use a macro to convert a Node number to a PCI bus.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 MakePciBusFromNode(UINT8 Node);
+ */
+#define MakePciBusFromNode(Node)                \
+  ((UINT8) (0))
+
+/** Use a macro to convert a Node number to a PCI Segment.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 MakePciSegmentFromNode(UINT8 Node);
+ */
+#define MakePciSegmentFromNode(Node)            \
+  ((UINT8) (0))
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Status for iterating through internal (if supported) and external links.
+ */
+typedef enum {
+  LinkIteratorEnd,         ///< This is the end of all links, no valid link.
+  LinkIteratorExternal,    ///< The next link (the one we got on this call) is an external link.
+  LinkIteratorInternal,    ///< The next link (the one we got on this call) is an internal link.
+  LinkIteratorMax          ///< For bounds checking and limit only.
+} LINK_ITERATOR_STATUS;
+
+#define LINK_ITERATOR_BEGIN 0xFF
+
+/**
+ * Write a temporary Route.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node The node on which to set a temporary route
+ * @param[in] Target A route to this node, which route table entry is to be set
+ * @param[in] Link The link which routes to the target node
+ * @param[in] Nb This northbridge
+ */
+typedef VOID F_WRITE_ROUTING_TABLE (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_ROUTING_TABLE *PF_WRITE_ROUTING_TABLE;
+
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     NodeID the new value for NodeID
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_WRITE_NODEID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_NODEID *PF_WRITE_NODEID;
+
+/**
+ * Read the Default Link
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     Nb     this northbridge
+ *
+ * @return The HyperTransport Link where the request to
+ *        read the default Link came from.  Since this code is running on the BSP,
+ *        this should be the Link pointing back towards the BSP.
+ */
+typedef UINT8 F_READ_DEFAULT_LINK (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_DEFAULT_LINK *PF_READ_DEFAULT_LINK;
+
+/**
+ * Turns routing tables on for a given Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node that will have it's routing tables enabled
+ * @param[in] Nb this northbridge
+ */
+typedef VOID F_ENABLE_ROUTING_TABLES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_ENABLE_ROUTING_TABLES *PF_ENABLE_ROUTING_TABLES;
+
+/**
+ * Turns routing tables off for a given Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node that will have it's routing tables disabled
+ * @param[in] Nb this northbridge
+ */
+typedef VOID F_DISABLE_ROUTING_TABLES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_DISABLE_ROUTING_TABLES *PF_DISABLE_ROUTING_TABLES;
+
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link is coherent
+ *  @retval       FALSE   The Link has some other status
+*/
+typedef BOOLEAN F_VERIFY_LINK_IS_COHERENT (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_VERIFY_LINK_IS_COHERENT *PF_VERIFY_LINK_IS_COHERENT;
+
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ *
+ * @return        the Token read from the Node
+ */
+typedef UINT8 F_READ_TOKEN (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_TOKEN *PF_READ_TOKEN;
+
+/**
+ * Write the token stored in the scratchpad register
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node the Node that marked with token
+ * @param[in]     Value the token Value
+ * @param[in]     Nb this northbridge
+ */
+typedef VOID F_WRITE_TOKEN (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_TOKEN *PF_WRITE_TOKEN;
+
+/**
+ * Full Routing Table Register initialization
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node            the Node that will be examined
+ * @param[in]     Target          the Target Node for these routes
+ * @param[in]     ReqLink         the Link for requests to Target
+ * @param[in]     RspLink         the Link for responses to Target
+ * @param[in]     BroadcastLinks  the broadcast Links
+ * @param[in]     Nb              this northbridge
+ */
+typedef VOID F_WRITE_FULL_ROUTING_TABLE (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_FULL_ROUTING_TABLE *PF_WRITE_FULL_ROUTING_TABLE;
+
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb this northbridge
+ *
+ * @retval   TRUE    the node is not compatible
+ * @retval   FALSE   the node is compatible
+ */
+typedef BOOLEAN F_IS_ILLEGAL_TYPE_MIX (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_IS_ILLEGAL_TYPE_MIX *PF_IS_ILLEGAL_TYPE_MIX;
+
+/**
+ * Return whether the current configuration exceeds the capability
+ * of the nodes detected.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node
+ * @param[in]     State    sysMpCap (updated) and NodesDiscovered
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE     system is not capable of current config.
+ * @retval        FALSE    system is capable of current config.
+ */
+typedef BOOLEAN F_IS_EXCEEDED_CAPABLE (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_IS_EXCEEDED_CAPABLE *PF_IS_EXCEEDED_CAPABLE;
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ *
+ * @HtNbInstances
+ *
+ * Use is for fatal incompatible configurations.
+ * While XMIT and RCV off are HT standard, the use of these bits
+ * is generally family specific.
+ *
+ * @param[in] Node   the node to stop a link on.
+ * @param[in] Link   the link to stop.
+ * @param[in] State  access to special routine for writing link control register
+ * @param[in] Nb     this northbridge.
+ */
+typedef VOID F_STOP_LINK (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_STOP_LINK *PF_STOP_LINK;
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbInstances
+ *
+ * This routine is expected to be unimplemented for most families.
+ * Some configurations may require that links be processed specially to prevent
+ * serious problems, like hangs.  Check for that condition in this routine,
+ * handle the link both for hardware and for adding to port list, if appropriate.
+ * If this routine adds the link to port list or the link should not be added, return TRUE.
+ *
+ * @param[in] Node  The Node which has this link
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This link received special handling.
+ * @retval    FALSE This link was not handled specially, handle it normally.
+ *
+ */
+typedef BOOLEAN F_HANDLE_SPECIAL_LINK_CASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_HANDLE_SPECIAL_LINK_CASE *PF_HANDLE_SPECIAL_LINK_CASE;
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbInstances
+ *
+ * This routine is expected to be unimplemented for most families.
+ * Some configurations may require that nodes be processed specially to prevent
+ * serious problems, like hangs.  Check for that condition in this routine,
+ * handle the node both for hardware and for adding to port list, if appropriate.
+ * If this routine adds the node to port list or the node should not be added, return TRUE.
+ *
+ * @param[in] Node  The Node which need to be checked.
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This node received special handling.
+ * @retval    FALSE This node was not handled specially, handle it normally.
+ *
+ */
+typedef BOOLEAN F_HANDLE_SPECIAL_NODE_CASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_HANDLE_SPECIAL_NODE_CASE *PF_HANDLE_SPECIAL_NODE_CASE;
+
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node                the Node
+ * @param[out]    ModuleType          0 for Single, 1 for Multi
+ * @param[out]    Module              The module number of this node (0 if Single)
+ * @param[in]     Nb                  this northbridge
+ *
+ */
+typedef VOID F_GET_MODULE_INFO (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_GET_MODULE_INFO *PF_GET_MODULE_INFO;
+
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailInfo    The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+typedef VOID F_POST_MAILBOX (
+  IN       UINT8        Node,
+  IN       AP_MAILBOXES ApMailInfo,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_POST_MAILBOX *PF_POST_MAILBOX;
+
+/**
+ * Retrieve info from a node's AP mailbox.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailInfo    The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+typedef AP_MAIL_INFO F_RETRIEVE_MAILBOX (
+  IN       UINT8        Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_RETRIEVE_MAILBOX *PF_RETRIEVE_MAILBOX;
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node     The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb       Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+typedef UINT8 F_GET_SOCKET (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_SOCKET *PF_GET_SOCKET;
+
+/**
+ * Get the enabled Compute Units.
+ *
+ * Processors which don't support compute units return zero.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node     The node for which we want the socket id.
+ * @param[in]   Nb       Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+typedef UINT8 F_GET_ENABLED_COMPUTE_UNITS (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_ENABLED_COMPUTE_UNITS *PF_GET_ENABLED_COMPUTE_UNITS;
+
+/**
+ * Get the dual core Compute Units.
+ *
+ * Processors which don't support compute units return zero.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node     The node for which we want the socket id.
+ * @param[in]   Nb       Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+typedef UINT8 F_GET_DUALCORE_COMPUTE_UNITS (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_DUALCORE_COMPUTE_UNITS *PF_GET_DUALCORE_COMPUTE_UNITS;
+
+/**
+ * Return the Link to the Southbridge
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Nb this northbridge
+ *
+ * @return the Link to the southbridge
+ */
+typedef UINT8 F_READ_SB_LINK (
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_SB_LINK *PF_READ_SB_LINK;
+
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link is non-coherent.
+ * @retval        FALSE   The Link has some other status
+ */
+typedef BOOLEAN F_VERIFY_LINK_IS_NON_COHERENT (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_VERIFY_LINK_IS_NON_COHERENT *PF_VERIFY_LINK_IS_NON_COHERENT;
+
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     ConfigMapIndex the map entry to set
+ * @param[in]     SecBus         The secondary bus number to use
+ * @param[in]     SubBus         The subordinate bus number to use
+ * @param[in]     TargetNode     The Node  that shall be the recipient of the traffic
+ * @param[in]     TargetLink     The Link that shall be the recipient of the traffic
+ * @param[in]     State          our global state
+ * @param[in]     Nb             this northbridge
+ */
+typedef VOID F_SET_CONFIG_ADDR_MAP (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_CONFIG_ADDR_MAP *PF_SET_CONFIG_ADDR_MAP;
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbInstances
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node             Result could (later) be for a specific Node
+ * @param[in]     Interface        Access to non-HT support functions.
+ * @param[in]     PlatformConfig   Platform profile/build option config structure.
+ * @param[in]     Nb               this northbridge
+ *
+ * @return Frequency mask
+ */
+typedef UINT32 F_NORTH_BRIDGE_FREQ_MASK (
+  IN       UINT8                  Node,
+  IN       HT_INTERFACE           *Interface,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       NORTHBRIDGE            *Nb
+  );
+/// Reference to a method.
+typedef F_NORTH_BRIDGE_FREQ_MASK *PF_NORTH_BRIDGE_FREQ_MASK;
+
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in,out] ThisPort         The PortList structure entry for this link's port
+ * @param[in]     Interface        Access to non-HT support functions.
+ * @param[in]     PlatformConfig   Platform profile/build option config structure.
+ * @param[in]     Nb               this northbridge
+ */
+typedef VOID F_GATHER_LINK_FEATURES (
+  IN OUT   PORT_DESCRIPTOR        *ThisPort,
+  IN       HT_INTERFACE           *Interface,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       NORTHBRIDGE            *Nb
+  );
+/// Reference to a method.
+typedef F_GATHER_LINK_FEATURES *PF_GATHER_LINK_FEATURES;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the node on which to regang a link
+ * @param[in]     Link   the sublink 0 of the sublink pair to regang
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_SET_LINK_REGANG (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_REGANG *PF_SET_LINK_REGANG;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node        the node on which to set frequency for a link
+ * @param[in]     Link        the link to set frequency
+ * @param[in]     Frequency   the frequency to set
+ * @param[in]     Nb          this northbridge
+ */
+typedef VOID F_SET_LINK_FREQUENCY (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_FREQUENCY *PF_SET_LINK_FREQUENCY;
+
+/**
+ * Set the link's Unit Id Clumping enable.
+ *
+ * @HtNbInstances
+ *
+ * This applies to the host root of a non-coherent chain.
+ *
+ * @param[in]     Node              the node on which to set frequency for a link
+ * @param[in]     Link              the link to set frequency
+ * @param[in]     ClumpingEnables   the unit id clumping enables to set
+ * @param[in]     Nb                this northbridge
+ */
+typedef VOID F_SET_LINK_UNITID_CLUMPING (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT32         ClumpingEnables,
+  IN       NORTHBRIDGE    *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_UNITID_CLUMPING *PF_SET_LINK_UNITID_CLUMPING;
+
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Links01   coherent Links from Node 0 to 1
+ * @param[in]     Links10   coherent Links from Node 1 to 0
+ * @param[in]     Nb        this northbridge
+ */
+typedef VOID F_WRITE_TRAFFIC_DISTRIBUTION (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_TRAFFIC_DISTRIBUTION *PF_WRITE_TRAFFIC_DISTRIBUTION;
+
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     NodeA                          Source Node from Node A To Node B and DstNode from Node A To Node B
+ * @param[in]     NodeB                          Source Node from Node B To Node A and DstNode from Node A To Node B
+ * @param[in]     VictimedLinkFromNodeAToNodeB   Victimed Link from Node A To Node B
+ * @param[in]     VictimedLinkFromNodeBToNodeA   Victimed Link from Node B To Node A
+ * @param[in]     Nb        this northbridge
+ */
+typedef VOID F_WRITE_VICTIM_DISTRIBUTION (
+  IN       UINT8        NodeA,
+  IN       UINT8        NodeB,
+  IN       UINT32       VictimedLinkFromNodeAToNodeB,
+  IN       UINT32       VictimedLinkFromNodeBToNodeA,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_VICTIM_DISTRIBUTION *PF_WRITE_VICTIM_DISTRIBUTION;
+
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]    Node           Set the pair on this node
+ * @param[in]    ConnectedNode  The Node to which this link pair directly connects.
+ * @param[in]    Pair           Using this pair set in the register
+ * @param[in]    Asymmetric     True if different widths
+ * @param[in]    MasterLink     Set this as the master link and in the route
+ * @param[in]    AlternateLink  Set this as the alternate link
+ * @param[in]    Nb             this northbridge
+ *
+ */
+typedef VOID F_WRITE_LINK_PAIR_DISTRIBUTION (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Pointer to method WriteLinkPairDistribution
+typedef F_WRITE_LINK_PAIR_DISTRIBUTION *PF_WRITE_LINK_PAIR_DISTRIBUTION;
+
+/**
+ * Family specific tunings.
+ *
+ * @HtNbInstances
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State   global state
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_BUFFER_OPTIMIZATIONS (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_BUFFER_OPTIMIZATIONS *PF_BUFFER_OPTIMIZATIONS;
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+typedef UINT8 F_GET_NUM_CORES_ON_NODE (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_GET_NUM_CORES_ON_NODE *PF_GET_NUM_CORES_ON_NODE;
+
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node         the Node that will be examined
+ * @param[in]     TotalNodes   the total number of Nodes
+ * @param[in]     TotalCores   the total number of cores
+ * @param[in]     Nb           this northbridge
+ */
+typedef VOID F_SET_TOTAL_NODES_AND_CORES (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_TOTAL_NODES_AND_CORES *PF_SET_TOTAL_NODES_AND_CORES;
+
+/**
+ * Get the Count of Nodes in the system.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Nb    This Northbridge.
+ *
+ * @return    The Count (1 based) of Nodes in the system.
+ */
+typedef UINT8 F_GET_NODE_COUNT (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_NODE_COUNT *PF_GET_NODE_COUNT;
+
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ */
+typedef VOID F_LIMIT_NODES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_LIMIT_NODES *PF_LIMIT_NODES;
+
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node  the Node that will be examined
+ * @param[in]     Link  the Link on that Node to examine
+ * @param[in]     State  access to call back routine
+ * @param[in]     Nb    this northbridge
+ *
+ * @retval        TRUE   the Link is not connected or has hard error
+ * @retval        FALSE  the Link is connected
+ */
+typedef BOOLEAN F_READ_TRUE_LINK_FAIL_STATUS (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_TRUE_LINK_FAIL_STATUS *PF_READ_TRUE_LINK_FAIL_STATUS;
+
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node The node on which to iterate links.
+ * @param[in,out] Link IN: the current iteration context, OUT: the next link.
+ * @param[in]     Nb   This Northbridge, access to config pointer.
+ *
+ * @retval LinkIteratorEnd         There is no next link (Link is back to BEGIN).
+ * @retval LinkIteratorExternal    The next Link is an external link.
+ * @retval LinkIteratorInternal    The next Link is an internal link.
+ */
+typedef LINK_ITERATOR_STATUS F_GET_NEXT_LINK (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Pointer to method GetNextLink
+typedef F_GET_NEXT_LINK *PF_GET_NEXT_LINK;
+
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node       the node which has this link
+ * @param[in]   Link       the link on that node
+ * @param[in]   Nb         this northbridge
+ *
+ * @return                 the Package Link
+ *
+ */
+typedef UINT8 F_GET_PACKAGE_LINK (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method
+typedef F_GET_PACKAGE_LINK *PF_GET_PACKAGE_LINK;
+
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node this Link is on
+ * @param[in]     Link    the Link
+ * @param[in]     Nb      this northbridge
+ *
+ * @return  the pci config address
+ */
+typedef PCI_ADDR F_MAKE_LINK_BASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_MAKE_LINK_BASE *PF_MAKE_LINK_BASE;
+
+/**
+ * Make a compatibility key.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @return the key
+ */
+typedef UINT64 F_MAKE_KEY (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_MAKE_KEY *PF_MAKE_KEY;
+
+/**
+ * The northbridge interface.
+ *
+ * Abstract the hardware implementation of the processor northbridge.  Feature code does
+ * not need to be tailored to specific families.  Also, more than a single family (or
+ * model in some cases) can be supported at once.  Multiple family support can be for
+ * mixed revisions or for incompatible revisions where only one is used at a time.
+ *
+ * The northbridge object contains both HT component public and northbridge private
+ * members.  These sets are grouped together.  Within each group, members are grouped
+ * according to the function area they support.
+ *
+ */
+struct _NORTHBRIDGE {               // See forward declaration in HtFeats.h
+  /* Public data, clients of northbridge can access */
+  UINT8 MaxLinks;               /**< The maximum number of Links implemented by the northbridge */
+
+  /* Public Interfaces for northbridge clients, coherent init*/
+  PF_WRITE_ROUTING_TABLE WriteRoutingTable;    /**< Method: Write a Temporary route for discovery */
+  PF_WRITE_NODEID WriteNodeID;    /**< Method: Assign a Node ID*/
+  PF_READ_DEFAULT_LINK ReadDefaultLink;    /**< Method: Which link are we connected to on a remote node? */
+  PF_ENABLE_ROUTING_TABLES EnableRoutingTables;    /**< Method: Make the routing table active */
+  PF_DISABLE_ROUTING_TABLES DisableRoutingTables;    /**< Method: Put a node back in discoverable state (deflnk) */
+  PF_VERIFY_LINK_IS_COHERENT VerifyLinkIsCoherent;    /**< Method: is a link connected and coherent? */
+  PF_READ_TOKEN ReadToken;    /**< Method: Read the enumeration token from a node */
+  PF_WRITE_TOKEN WriteToken;    /**< Method: Assign an enumeration token to a node */
+  PF_WRITE_FULL_ROUTING_TABLE WriteFullRoutingTable;    /**< Method: Set a complete routing table entry on a node */
+  PF_IS_ILLEGAL_TYPE_MIX IsIllegalTypeMix;    /**< Method: Is this node compatible with the system */
+  PF_IS_EXCEEDED_CAPABLE IsExceededCapable;    /**< Method: Is this node capable of working in this system */
+  PF_STOP_LINK StopLink;    /**< Method: stop a link which must be unused */
+  PF_HANDLE_SPECIAL_LINK_CASE HandleSpecialLinkCase;    /**< Method: Fix broken configuration designs */
+  PF_HANDLE_SPECIAL_NODE_CASE HandleSpecialNodeCase;    /**< Method: Fix broken configuration designs */
+
+  /* Public Interfaces for northbridge clients, noncoherent init */
+  PF_READ_SB_LINK ReadSouthbridgeLink;    /**< Method: Which link goes to the southbridge? */
+  PF_VERIFY_LINK_IS_NON_COHERENT VerifyLinkIsNonCoherent;    /**< Method: is a link connected and non-coherent? */
+  PF_SET_CONFIG_ADDR_MAP SetConfigAddrMap;    /**< Method: Add a non-coherent chain to the PCI Config Bus Address Map */
+
+  /* Public Interfaces for northbridge clients, Optimization */
+  PF_NORTH_BRIDGE_FREQ_MASK NorthBridgeFreqMask;    /**< Method: Check for frequency limits other than HT */
+  PF_GATHER_LINK_FEATURES GatherLinkFeatures;        /**< Method: Get frequency and link features */
+  PF_SET_LINK_REGANG SetLinkRegang;              /**< Method: Set a Link to regang */
+  PF_SET_LINK_FREQUENCY SetLinkFrequency;        /**< Method: Set the link Frequency */
+  PF_SET_LINK_UNITID_CLUMPING SetLinkUnitIdClumping;   /**< Method: Set the link's Unit Id Clumping register */
+
+  /* Public Interfaces for northbridge clients, System and performance Tuning. */
+  PF_WRITE_TRAFFIC_DISTRIBUTION WriteTrafficDistribution;    /**< Method: traffic distribution setting */
+  PF_WRITE_LINK_PAIR_DISTRIBUTION WriteLinkPairDistribution;    /**< Method: Link Pair setting and fix up */
+  PF_WRITE_VICTIM_DISTRIBUTION WriteVictimDistribution;    /**< Method: victim distribution setting */
+  PF_BUFFER_OPTIMIZATIONS BufferOptimizations;    /**< Method: system tunings which can not be
+                                                   * done using register table */
+
+  /* Public Interfaces for northbridge clients, utility routines */
+  PF_GET_NUM_CORES_ON_NODE GetNumCoresOnNode;    /**< Method: Count cores */
+  PF_SET_TOTAL_NODES_AND_CORES SetTotalNodesAndCores;    /**< Method: Set Node and Core counts */
+  PF_GET_NODE_COUNT GetNodeCount;    /**< Method: Get the Count (1 based) of Nodes in the system. */
+  PF_LIMIT_NODES LimitNodes;    /**< Method: Set the Limit Config Space feature */
+  PF_READ_TRUE_LINK_FAIL_STATUS ReadTrueLinkFailStatus;    /**< Method: Get Fault status and connectivity of a link */
+  PF_GET_NEXT_LINK GetNextLink;    /**< Method: Iterate over a node's Internal, then External links. */
+  PF_GET_PACKAGE_LINK GetPackageLink;    /**< Method: the package link corresponding to a node's link */
+  PF_MAKE_LINK_BASE MakeLinkBase;    /**< Method: Provide the PCI Config Base register offset of a CPU link */
+  PF_GET_MODULE_INFO GetModuleInfo;    /**< Method: Get Module Type and internal Module number */
+  PF_POST_MAILBOX PostMailbox;     /**< Method: Post info to the mailbox register */
+  PF_RETRIEVE_MAILBOX RetrieveMailbox;     /**< Method: Retrieve info from the mailbox register */
+  PF_GET_SOCKET GetSocket;    /**< Method: Get a node's Socket, using the hardware naming method. */
+  PF_GET_ENABLED_COMPUTE_UNITS GetEnabledComputeUnits; /**< Method: Get the Enabled Compute Units */
+  PF_GET_DUALCORE_COMPUTE_UNITS GetDualCoreComputeUnits; /**< Method: Get which Compute Units have two cores. */
+
+  /* Private Data for northbridge implementation use only */
+  UINT32 SelfRouteRequestMask;  /**< Bit pattern for route request to self in routing table register */
+  UINT32 SelfRouteResponseMask; /**< Bit pattern for route response to self in routing table register */
+  UINT8 BroadcastSelfBit;       /**< Bit offset of broadcast self bit in routing table register */
+  BOOLEAN IsOrderBSPCoresByNode; /**< This processor orders Cores by Node id on the BSP, if TRUE. */
+  BOOLEAN IsOrderCoresByModule;  /**< Processors other than the BSP order Cores by Module, if TRUE. */
+  UINT64 CompatibleKey;         /**< Used for checking compatibility of northbridges in the system */
+  PACKAGE_HTLINK_MAP PackageLinkMap;    /**< Tell GetPackageLink() how to assign link names */
+  UINT32 CoreFrequency;           /**< Cache the northbridge core frequency, so repeated interface calls are avoided.
+                                   *   A value of zero, means no value yet. */
+  IGNORE_LINK *DefaultIgnoreLinkList;   /**< After processing the user interface ignore link, process this list. */
+
+  /* Private Interfaces for northbridge implementation. */
+  PF_MAKE_KEY MakeKey;    /**< Method: make the compatibility key for this node */
+
+  /** Config Pointer, opaque handle for passing to lib */
+  VOID *ConfigHandle;
+};
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Make a compatibility key.
+ *
+ */
+UINT64
+MakeKey (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+VOID
+NewNorthBridge (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+     OUT   NORTHBRIDGE *Nb
+  );
+
+#endif  /* _HT_NB_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNbCommonHardware.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNbCommonHardware.h
new file mode 100644
index 0000000000..d8059b1c2e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNbCommonHardware.h
@@ -0,0 +1,149 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Northbridge hardware definitions for Family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _HT_NB_HARDWARE_FAM10_H_
+#define _HT_NB_HARDWARE_FAM10_H_
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* CPU Northbridge Functions */
+#define CPU_HTNB_FUNC_00                  0
+#define CPU_HTNB_FUNC_04                  4
+#define CPU_ADDR_FUNC_01                  1
+#define CPU_NB_FUNC_03                    3
+#define CPU_NB_FUNC_05                    5
+
+/* Function 0 registers */
+#define REG_ROUTE0_0X40                   0x40
+#define REG_ROUTE1_0X44                   0x44
+#define REG_NODE_ID_0X60                  0x60
+#define REG_UNIT_ID_0X64                  0x64
+#define REG_LINK_TRANS_CONTROL_0X68       0x68
+#define REG_LINK_INIT_CONTROL_0X6C        0x6C
+#define REG_HT_CAP_BASE_0X80              0x80
+#define REG_HT_LINK_CLUMPING0_0X110       0x110
+#define REG_HT_LINK_RETRY0_0X130          0x130
+#define REG_HT_EXTENDED_NODE_ID_F0X160    0x160
+#define HTREG_NODE_CPUCNT_4_0             0x1F
+#define HTREG_EXTNODE_CPUCNT_7_5          0xE0
+#define REG_HT_TRAFFIC_DIST_0X164         0x164
+#define REG_LINK_GLOBAL_EXT_CONTROL_0x16C 0x16C
+#define REG_HT_LINK_EXT_CONTROL0_0X170    0x170
+#define REG_HT_LINK_INITIALIZATION_0X1A0  0x1A0
+#define PAIR_SELECT_OFFSET                8
+#define REG_HT_LINK_PAIR_DIST_0X1E0       0x1E0
+
+/* Function 1 registers */
+#define REG_ADDR_CONFIG_MAP0_1XE0         0xE0
+#define CPU_ADDR_NUM_CONFIG_MAPS          4
+
+/* Function 3 registers */
+#define REG_NB_SRI_XBAR_BUF_3X70          0x70
+#define REG_NB_MCT_XBAR_BUF_3X78          0x78
+#define REG_NB_FIFOPTR_3XDC               0xDC
+#define REG_NB_CAPABILITY_3XE8            0xE8
+#define REG_NB_CPUID_3XFC                 0xFC
+#define REG_NB_LINK_XCS_TOKEN0_3X148      0x148
+#define REG_NB_MCA_LINK_THRESHOLD_3X168   0x168
+#define REG_NB_MCA_L3_THRESHOLD_3X170     0x170
+#define REG_NB_DOWNCORE_3X190             0x190
+#define REG_NB_SBI_CONTROL_3X1E4          0x1E4
+
+/* Function 4 registers */
+
+/* Function 5 registers */
+#define REG_NB_COMPUTE_UNIT_5X80            0x80
+#define REG_NB_CAPABILITY_2_5X84            0x84
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif /* _HT_NB_HARDWARE_FAM10_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c
new file mode 100644
index 0000000000..2a11028f98
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c
@@ -0,0 +1,696 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Code for detailed notification of events and status.
+ *
+ * Routines for logging and reporting details and summary status.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNotify.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_HT_HTNOTIFY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Log an event.
+ *
+ * Errors, events, faults, warnings, and useful information are provided by
+ * calling this routine as often as necessary, once for each notification.
+ * @sa AGESA.h for class, and event definitions.
+ * @sa htNotify.h for event data definitions.
+ *
+ * @param[in]     EvtClass      What level event is this
+ * @param[in]     Event         A unique ID of this event
+ * @param[in]     EventData     useful data associated with the event.
+ * @param[in]     State         the log area and remaining free space
+ */
+VOID
+STATIC
+setEventNotify (
+  IN       AGESA_STATUS  EvtClass,
+  IN       UINT32        Event,
+  IN       CONST UINT8  *EventData,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT32 DataParam[NUMBER_OF_EVENT_DATA_PARAMS];
+
+  // Remember the highest event class notified, that becomes our return code.
+  if (State->MaxEventClass < EvtClass) {
+    State->MaxEventClass = EvtClass;
+  }
+
+  // Copy the event data to the log data
+  LibAmdMemCopy (
+    DataParam,
+    (VOID *)EventData,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  // Log the event
+  PutEventLog (
+    EvtClass,
+    Event,
+    DataParam[0],
+    DataParam[1],
+    DataParam[2],
+    DataParam[3],
+    State->ConfigHandle
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_HW_SYNCFLOOD
+ *
+ * @param[in] Node      The node on which the fault is reported
+ * @param[in] Link      The link from that node
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyAlertHwSyncFlood (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       STATE_DATA   *State
+  )
+{
+  HT_EVENT_DATA_HW_SYNCFLOOD Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  IDS_HDT_CONSOLE (HT_TRACE, "Sync Flood on Node %d Link %d.\n", Node, Link);
+  Evt.Node = Node;
+  Evt.Link = Link;
+  setEventNotify (AGESA_ALERT,
+                 HT_EVENT_HW_SYNCFLOOD,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_HW_HTCRC
+ *
+ * @param[in] Node      The node on which the error is reported
+ * @param[in] Link      The link from that node
+ * @param[in] LaneMask  The lanes which had CRC
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyAlertHwHtCrc (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      LaneMask,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_HW_HT_CRC Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  IDS_HDT_CONSOLE (HT_TRACE, "CRC Error on Node %d Link %d lanes %x.\n", Node, Link, LaneMask);
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.LaneMask = LaneMask;
+  setEventNotify (AGESA_ALERT,
+                 HT_EVENT_HW_HTCRC,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_BUS_MAX_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Bus       The bus number to assign
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohBusMaxExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Bus,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Bus = Bus;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_BUS_MAX_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_CFG_MAP_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohCfgMapExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_CFG_MAP_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_BUID_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] Id        The Id which was attempted to assigned
+ * @param[in] Units     The number of units in this device
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohBuidExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       UINT8      Units,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_BUID_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  Evt.CurrentBuid = Id;
+  Evt.UnitCount = Units;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_BUID_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_DEVICE_FAILED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] Id        The Id which was attempted to assigned
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohDeviceFailed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  Evt.AttemptedBuid = Id;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_DEVICE_FAILED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_AUTO_DEPTH
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyInfoNcohAutoDepth (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_AUTO_DEPTH Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_SUCCESS,
+                 HT_EVENT_NCOH_AUTO_DEPTH,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyWarningOptRequiredCapRetry (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_REQUIRED_CAP_RETRY,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyWarningOptRequiredCapGen3 (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_REQUIRED_CAP_GEN3,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_UNUSED_LINKS
+ *
+ * @param[in]  NodeA    One of the nodes connected
+ * @param[in]  NodeB    The other connected node
+ * @param[in]  LinkA    its unusable link
+ * @param[in]  LinkB    its unusable link
+ * @param[in]  State    our State
+ *
+ */
+VOID
+NotifyWarningOptUnusedLinks (
+  IN       UINT32    NodeA,
+  IN       UINT32    LinkA,
+  IN       UINT32    NodeB,
+  IN       UINT32    LinkB,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_UNUSED_LINKS Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.NodeA = NodeA;
+  Evt.LinkA = LinkA;
+  Evt.NodeB = NodeB;
+  Evt.LinkB = LinkB;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_UNUSED_LINKS,
+                 (UINT8 *)&Evt, State);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_LINK_PAIR_EXCEED
+ *
+ * @param[in]  NodeA      One of the nodes connected
+ * @param[in]  NodeB      The other connected node
+ * @param[in]  MasterLink its unusable Masterlink
+ * @param[in]  AltLink    its unusable Alternate link
+ * @param[in]  State      our State
+ *
+ */
+VOID
+NotifyWarningOptLinkPairExceed (
+  IN       UINT32    NodeA,
+  IN       UINT32    NodeB,
+  IN       UINT32    MasterLink,
+  IN       UINT32    AltLink,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.NodeA = NodeA;
+  Evt.MasterLink = MasterLink;
+  Evt.NodeB = NodeB;
+  Evt.AltLink = AltLink;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_LINK_PAIR_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_NO_TOPOLOGY
+ *
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorCohNoTopology (
+  IN       UINT8 Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_NO_TOPOLOGY Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  IDS_HDT_CONSOLE (HT_TRACE, "No Topology Matched system with %d nodes found.\n", Nodes);
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_COH_NO_TOPOLOGY,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
+ *
+ * @param[in] Node      The node from which a new node was discovered
+ * @param[in] Link      The link from that node
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyFatalCohProcessorTypeMix (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  IDS_HDT_CONSOLE (HT_TRACE, "Illegal Processor Type Mix.\n");
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_CRITICAL,
+                 HT_EVENT_COH_PROCESSOR_TYPE_MIX,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_NODE_DISCOVERED
+ *
+ * @param[in] Node       Node from which a new node was discovered
+ * @param[in] Link       The link to that new node
+ * @param[in] NewNode    The new node's id
+ * @param[in] TempRoute  Temporarily, during discovery, the new node is accessed at this id.
+ * @param[in] State      our State
+ *
+ */
+VOID
+NotifyInfoCohNodeDiscovered (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 NewNode,
+  IN       UINT8 TempRoute,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_NODE_DISCOVERED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  IDS_HDT_CONSOLE (HT_TRACE, "Adding Node %d.\n", NewNode);
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.NewNode = NewNode;
+  Evt.TempRoute = TempRoute;
+  setEventNotify (AGESA_SUCCESS,
+                 HT_EVENT_COH_NODE_DISCOVERED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_MPCAP_MISMATCH
+ *
+ * @param[in] Node      The node from which a new node was discovered
+ * @param[in] Link      The link from that node
+ * @param[in] Cap       The aggregate system MP Capability
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyFatalCohMpCapMismatch (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Cap,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  IDS_HDT_CONSOLE (HT_TRACE, "Mp Capability Mismatch.\n");
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.SysMpCap = Cap;
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_CRITICAL,
+                 HT_EVENT_COH_MPCAP_MISMATCH,
+                 (UINT8 *)&Evt, State);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
new file mode 100644
index 0000000000..2eb8f6a532
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
@@ -0,0 +1,324 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HT Notify interface.
+ *
+ * This file provides internal interface to event and status
+ * notification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $        @e  \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NOTIFY_H_
+#define _HT_NOTIFY_H_
+
+/*----------------------------------------------------------------------------------------*/
+/* Event specific event data definitions.
+ * All structures must be 4 UINT32's in size, no more, no less.
+ */
+
+/// For event ::HT_EVENT_HW_SYNCFLOOD
+typedef struct {
+  UINT32 Node;                   ///< The Node on which observed
+  UINT32 Link;                   ///< The Link on that Node which reported synch flood
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+} HT_EVENT_DATA_HW_SYNCFLOOD;
+
+/// For event ::HT_EVENT_HW_HTCRC
+typedef struct {
+  UINT32 Node;                   ///< The Node on which event is observed
+  UINT32 Link;                   ///< The Link on that Node which reported CRC error
+  UINT32 LaneMask;               ///< The CRC lane mask for the Link
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_HW_HT_CRC;
+
+/// For event ::HT_EVENT_NCOH_BUS_MAX_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Bus;                    ///< the current bus number
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_CFG_MAP_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_BUID_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT16 CurrentBuid;            ///< the current available BUID
+  UINT16 UnitCount;              ///< the number of ids which would be consumed by this device
+} HT_EVENT_DATA_NCOH_BUID_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_DEVICE_FAILED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT32 AttemptedBuid;          ///< the BUID we tried to assign to that device
+} HT_EVENT_DATA_NCOH_DEVICE_FAILED;
+
+/// For event ::HT_EVENT_NCOH_AUTO_DEPTH
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain of the last device, zero is CPU host
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_AUTO_DEPTH;
+
+/// For event ::HT_EVENT_OPT_REQUIRED_CAP_RETRY,
+///           ::HT_EVENT_OPT_REQUIRED_CAP_GEN3.
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_OPT_REQUIRED_CAP;
+
+/// For event ::HT_EVENT_OPT_UNUSED_LINKS
+typedef struct {
+  UINT32 NodeA;                  ///< One of the nodes connected
+  UINT32 LinkA;                  ///< its unusable link
+  UINT32 NodeB;                  ///< The other connected node
+  UINT32 LinkB;                  ///< its unusable link
+} HT_EVENT_DATA_OPT_UNUSED_LINKS;
+
+/// For event ::HT_EVENT_OPT_LINK_PAIR_EXCEED
+typedef struct {
+  UINT32 NodeA;                  ///< One of the nodes connected
+  UINT32 NodeB;                  ///< The other connected node
+  UINT32 MasterLink;             ///< NodeA's unusable Master link
+  UINT32 AltLink;                ///< NodeA's unusable Alternatelink
+} HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED;
+
+/// For event ::HT_EVENT_COH_NO_TOPOLOGY.
+/// There is no routing for this system's topology.
+typedef struct {
+  UINT32 TotalNodes;             ///< the number of Nodes in the unmatched topology
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+  UINT32 Reserved3;              ///< Reserved.
+} HT_EVENT_DATA_COH_NO_TOPOLOGY;
+
+/// For event ::HT_EVENT_COH_PROCESSOR_TYPE_MIX
+typedef struct {
+  UINT32 Node;                   ///< the Node from which the incompatible family was found
+  UINT32 Link;                   ///< the Link to the incompatible Node
+  UINT32 TotalNodes;             ///< the number of Nodes found at that point
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX;
+
+/// For event ::HT_EVENT_COH_NODE_DISCOVERED
+typedef struct {
+  UINT32 Node;                   ///< the Node from which the new Node was found
+  UINT32 Link;                   ///< the Link to the new Node
+  UINT32 NewNode;                ///< the Node id of the newly discovered Node
+  UINT32 TempRoute;              ///< the new Node is temporarily at this id
+} HT_EVENT_DATA_COH_NODE_DISCOVERED;
+
+/// For event ::HT_EVENT_COH_MPCAP_MISMATCH
+typedef struct {
+  UINT32 Node;                   ///< the Node from which condition was observed
+  UINT32 Link;                   ///< the Link on the current Node
+  UINT32 SysMpCap;               ///< the current aggregate system capability (the minimum found so far)
+  UINT32 TotalNodes;             ///< the number of Nodes found, before this was observed
+} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
+
+/*----------------------------------------------------------------------------------------*/
+/* Event specific Notify functions.
+ */
+
+VOID
+NotifyAlertHwSyncFlood (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       STATE_DATA   *State
+  );
+
+VOID
+NotifyAlertHwHtCrc (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      LaneMask,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohBusMaxExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Bus,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohCfgMapExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohBuidExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       UINT8      Units,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohDeviceFailed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyInfoNcohAutoDepth (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptRequiredCapRetry (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptRequiredCapGen3 (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptUnusedLinks (
+  IN       UINT32    NodeA,
+  IN       UINT32    LinkA,
+  IN       UINT32    NodeB,
+  IN       UINT32    LinkB,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptLinkPairExceed (
+  IN       UINT32    NodeA,
+  IN       UINT32    NodeB,
+  IN       UINT32    MasterLink,
+  IN       UINT32    AltLink,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorCohNoTopology (
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyFatalCohProcessorTypeMix (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyInfoCohNodeDiscovered (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      NewNode,
+  IN       UINT8      TempRoute,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyFatalCohMpCapMismatch (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Cap,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+#endif /* _HT_NOTIFY_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htPage.h
new file mode 100644
index 0000000000..9386d46349
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htPage.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for HyperTransport Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/**
+ * @page htmain HyperTransport Component Documentation
+ *
+ * Additional documentation for the HyperTransport component consists of
+ *
+ * - Member Cross References
+ *   - @subpage instanceshtnb "HT Northbridge Method Instances"
+ * - Maintenance Guides:
+ *   - @subpage htimplintf "HT Internal Interface Implementation Guide"
+ *   - @subpage htimplfeat "HT Feature Implementation Guide"
+ *   - @subpage htimplnb   "HT Northbridge Implementation Guide"
+ *   - add here >>>
+ * - Design Guides:
+ *   - @subpage htgraphdesign "Graph Support Design"
+ *   - @subpage physicalsockethowto "How to Create a Physical System Socket Map"
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htTopologies.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htTopologies.h
new file mode 100644
index 0000000000..c1488feca8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htTopologies.h
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Provide selection of available topologies.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _HT_TOPOLOGIES_H_
+#define _HT_TOPOLOGIES_H_
+
+extern CONST UINT8 ROMDATA amdHtTopologySingleNode[];
+extern CONST UINT8 ROMDATA amdHtTopologyDualNode[];
+extern CONST UINT8 ROMDATA amdHtTopologyThreeLine[];
+extern CONST UINT8 ROMDATA amdHtTopologyTriangle[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourLine[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourStar[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourSquare[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourKite[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyFiveFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySixFully[];
+extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[];
+extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[];
+extern CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySevenFully[];
+extern CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[];
+
+#endif // _HT_TOPOLOGIES_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c
new file mode 100644
index 0000000000..c0e0cbcac4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c
@@ -0,0 +1,855 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Backend Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "cpuRegisters.h"
+#include "heapManager.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "IdsLib.h"
+#include "IdsNvToCmos.h"
+#include "Filecode.h"
+#ifdef __IDS_EXTENDED__
+  #include IDS_EXT_INCLUDE (IdsInternalLib)
+#endif
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_CONTROL_IDSCTRL_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+extern CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[];
+
+
+/**
+ * IDS option hooking function dispatcher.
+ *
+ * This is the top level interface for IDS option Backend code.
+ *
+ * @param[in]     IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION
+ * @param[in,out] DataPtr   Data pointer.
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_NV_ITEM *IdsNvPtr;
+  IDS_STATUS   ReturnFlag;
+  IDS_STATUS ExtendedFlag;
+
+  IdsNvPtr  = NULL;
+  ReturnFlag = IDS_SUCCESS;
+
+  ASSERT (StdHeader != NULL);
+  if (AmdGetIdsNvTable ((VOID **) &IdsNvPtr, StdHeader) != AGESA_SUCCESS) {
+    IDS_HDT_CONSOLE (IDS_TRACE , "IDS initialize\n");
+    AmdIdsCtrlInitialize (StdHeader);
+    AmdGetIdsNvTable ((VOID **) &IdsNvPtr, StdHeader);
+  }
+
+  if (IdsNvPtr != NULL) {
+    ReturnFlag = IdsParseFeatTbl (IdsOption, IdsContorlFeats, DataPtr, IdsNvPtr, StdHeader);
+    ExtendedFlag = IDS_EXTENDED_HOOK (IdsOption, DataPtr, IdsNvPtr, StdHeader);
+    if (ExtendedFlag != IDS_SUCCESS) {
+      ReturnFlag = IDS_UNSUPPORTED;
+    }
+  }
+  return ReturnFlag;
+}
+
+/**
+ * Ids code for parse IDS feat table.
+ *
+ * Feat table in IDS is used to decribe the IDS support feat and its according family,handler.
+ *
+ * @param[in]     PIdsFeatTbl point to Ids Feat table
+ * @param[in]     IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION
+ * @param[in,out] DataPtr   Data pointer.
+ * @param[in]     IdsNvPtr   Ids Nvram pointer.
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+IdsParseFeatTbl (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN       CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[],
+  IN OUT   VOID *DataPtr,
+  IN       IDS_NV_ITEM *IdsNvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 i;
+  AGESA_STATUS Tmpsts;
+  CPU_LOGICAL_ID CpuLogicalId;
+  BOOLEAN No_Check_Bsp;
+  CONST IDS_FAMILY_FEAT_STRUCT *PIdsFeat;
+  IDS_STATUS ReturnFlag;
+
+  ReturnFlag = IDS_SUCCESS;
+
+  for (i = 0; PIdsFeatTbl[i] != NULL; i++) {
+    PIdsFeat = PIdsFeatTbl[i];
+    //Does specified IdsOption reached
+    if (PIdsFeat->IdsOption == IdsOption) {
+      //check if bsp only
+      if (PIdsFeat->IsBsp) {
+        No_Check_Bsp = 0;
+      } else {
+        No_Check_Bsp = 1;
+      }
+      if (No_Check_Bsp || IsBsp (StdHeader, &Tmpsts)) {
+        //Does Family Match required
+        GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+        if ((CpuLogicalId.Family) & (PIdsFeat->CpuFamily)) {
+          //Excute the code for specific Ids Feat
+          IDS_HDT_CONSOLE (IDS_TRACE, "\tIDS Excute HookPoint [%x] Start\n", IdsOption);
+          ReturnFlag = PIdsFeat->pf_idsoption (DataPtr, StdHeader, IdsNvPtr);
+          IDS_HDT_CONSOLE (IDS_TRACE, "\tIDS Excute HookPoint [%x] End\n", IdsOption);
+        }
+      }
+    }
+  }
+  return ReturnFlag;
+}
+
+/**
+ *
+ *  IDS Object Initialization
+ *
+ *  Initializer routine that will be invoked by the wrapper to initialize
+ *  the data buffer in heap for the IDS object. It includes IDS control
+ *  structure, IDS mem table and IDS GRA table.
+ *
+ *  @param[in,out] StdHeader    The Pointer of IDS Initial Parameter
+ *
+ *  @retval AGESA_SUCCESS       Success to init IDS Object.
+ *  @retval AGESA_ERROR         Fail to init IDS Object.
+ *
+ **/
+
+#ifdef IDS_HEAP_2STAGES
+  #define IDS_HEAP_PERSIST_EARLY  HEAP_LOCAL_CACHE
+  #define IDS_HEAP_ASSERTION_LATE
+#else
+  #define IDS_HEAP_PERSIST_EARLY  HEAP_SYSTEM_MEM
+  #define IDS_HEAP_ASSERTION_LATE ASSERT(FALSE)
+#endif
+
+AGESA_STATUS
+AmdIdsCtrlInitialize (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  AGESA_STATUS IgnoreStatus;
+  UINT16 NvTblSize;
+  UINT16 i;
+  IDS_NV_ITEM IdsNvTable[IDS_NUM_NV_ITEM];
+  IDS_NV_ITEM *NvTable;
+  IDS_NV_ITEM *NvPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+  IDS_CALLOUT_STRUCT IdsCalloutData;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT16 MemTblSize;
+  UINT8 HeapPersist;
+
+  NvTblSize = 0;
+  MemTblSize = 0;
+  HeapPersist = HEAP_SYSTEM_MEM;
+  //Heap status with HEAP_LOCAL_CACHE, will allocate heap with HEAP_LOCAL_CACHE
+  //with HEAP_TEMP_MEM  HEAP_SYSTEM_MEM  HEAP_DO_NOT_EXIST_ANYMORE  HEAP_S3_RESUME
+  // with allocate with HEAP_SYSTEM_MEM
+  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
+    MemTblSize = IDS_MAX_MEM_ITEMS;
+    HeapPersist = IDS_HEAP_PERSIST_EARLY;
+  } else if ((StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_YET) || (StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_ANYMORE)) {
+    return AGESA_ERROR;
+  } else {
+    IDS_HEAP_ASSERTION_LATE;
+  }
+
+  IdsCalloutData.IdsNvPtr = IdsNvTable;
+  IdsCalloutData.StdHeader = *StdHeader;
+  IdsCalloutData.Reserved = FALSE;
+//init IDS_CALLOUT_STRUCT before calling out, give NVITEM default value
+  for (i = AGESA_IDS_EXT_ID_START; i < IDS_NUM_NV_ITEM; i++) {
+    IdsNvTable[i].IdsNvId = i;
+    IdsNvTable[i].IdsNvValue = AGESA_IDS_DFT_VAL;
+  }
+
+  AGESA_TESTPOINT (TpIfBeforeGetIdsData, StdHeader);
+  if (AgesaGetIdsData (IDS_CALLOUT_INIT, &IdsCalloutData) == AGESA_SUCCESS) {
+    IDS_HDT_CONSOLE (IDS_TRACE , "Get IDS options from CBS Done\n");
+    NvTable = IdsCalloutData.IdsNvPtr;
+    NvPtr = NvTable;
+    while (NvPtr->IdsNvId != AGESA_IDS_NV_END) {
+      IDS_HDT_CONSOLE (IDS_TRACE , "\tIDS_ID (%X) = %X\n", NvPtr->IdsNvId, NvPtr->IdsNvValue);
+      NvTblSize  ++;
+      NvPtr ++;
+    }
+    NvTblSize  ++;
+
+    AllocHeapParams.RequestedBufferSize = sizeof (IDS_CONTROL_STRUCT);
+    AllocHeapParams.RequestedBufferSize += NvTblSize  * sizeof (IDS_NV_ITEM);
+    AllocHeapParams.RequestedBufferSize += MemTblSize * sizeof (MEM_TABLE_ALIAS);
+    AllocHeapParams.RequestedBufferSize += IDS_EXTENDED_HEAP_SIZE;
+    AllocHeapParams.BufferHandle = IDS_CONTROL_HANDLE;
+    AllocHeapParams.Persist = HeapPersist;
+
+    //
+    // Allocate data buffer in heap
+    //
+    if (HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader) == AGESA_SUCCESS) {
+      //
+      // Initialize IDS Date Buffer
+      //
+      IdsCtrlPtr = (IDS_CONTROL_STRUCT *) AllocHeapParams.BufferPtr;
+      IdsCtrlPtr->IgnoreIdsDefault = (BOOLEAN) IdsCalloutData.Reserved;
+      IdsCtrlPtr->IdsHeapMemSize = AllocHeapParams.RequestedBufferSize;
+      IdsCtrlPtr->IdsNvTableOffset = sizeof (IDS_CONTROL_STRUCT);
+      IdsCtrlPtr->IdsMemTableOffset = IdsCtrlPtr->IdsNvTableOffset + NvTblSize  * sizeof (IDS_NV_ITEM);
+      IdsCtrlPtr->IdsExtendOffset = IdsCtrlPtr->IdsMemTableOffset + MemTblSize * sizeof (MEM_TABLE_ALIAS);
+
+      NvPtr = (IDS_NV_ITEM *) (AllocHeapParams.BufferPtr + IdsCtrlPtr->IdsNvTableOffset);
+      for (i = 0; i < NvTblSize ; i++) {
+        NvPtr->IdsNvId = NvTable->IdsNvId;
+        NvPtr->IdsNvValue = NvTable->IdsNvValue;
+        NvPtr ++;
+        NvTable ++;
+      }
+      status = AGESA_SUCCESS;
+    } else {
+      status = AGESA_ERROR;
+    }
+  } else {
+    if (!IsBsp (StdHeader, &IgnoreStatus)) {
+      status = IDS_AP_GET_NV_FROM_CMOS (StdHeader);
+    } else {
+      IDS_HDT_CONSOLE (IDS_TRACE , "Get IDS options from CBS Fail\n");
+      status = AGESA_ERROR;
+    }
+  }
+  AGESA_TESTPOINT (TpIfAfterGetIdsData, StdHeader);
+
+  return status;
+}
+/**
+ *  IDS Backend Function for Target Pstate
+ *
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubTargetPstate (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS tarpst;
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+
+  IDS_NV_READ_SKIP (tarpst, AGESA_IDS_NV_TARGET_PSTATE, IdsNvPtr, StdHeader) {
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) tarpst, (BOOLEAN) FALSE, StdHeader);
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for HdtOut
+ *
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubHdtOut (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS idsvalue;
+
+//set HDTOUT En/Dis
+  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_HDTOUT, IdsNvPtr, StdHeader) {
+//if HDTOUT set to enable, set the corresponding DR2 flag to 0x99cc
+    if (idsvalue == 1) {
+      LibAmdWriteCpuReg (DR2_REG, 0x99cc);
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Power down mode
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubPowerDownCtrl (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_POST_PARAMS *PostParamsPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  IDS_STATUS idsvalue;
+  MEM_DATA_STRUCT * memdataptr;
+
+  PostParamsPtr = (AMD_POST_PARAMS *)DataPtr;
+  memdataptr = PostParamsPtr->MemConfig.MemData;
+  RefPtr = memdataptr->ParameterListPtr;
+
+  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_MEMORY_POWER_DOWN, IdsNvPtr, StdHeader) {
+    //if the idsvalue isn't auto do the override
+    if (idsvalue < (IDS_STATUS)0x2) {
+      RefPtr->EnablePowerDown = (BOOLEAN) idsvalue;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  Backend Function for IDS Option Hook Point: IDS_UCODE
+ *
+ *  This function is used to disable UCode Installation if IDS Option disables ucode.
+ *  The method is to force the number of total patches to ZERO.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of Data to Override.
+ *  @param[in,out]   StdHeader    The Pointer of AGESA Header.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubUCode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS status;
+  IDS_STATUS NvValue;
+  UINT8 ** pUcodeptr;
+
+  pUcodeptr = (UINT8 **) DataPtr;
+  status = IDS_SUCCESS;
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_UCODE, IdsNvPtr, StdHeader) {
+    //Disabled
+    if (NvValue == 0) {
+      status = IDS_UNSUPPORTED;
+    }
+  }
+
+  IDS_EXTENDED_CODE (
+    IdsGetBvmUcodeBase (pUcodeptr, StdHeader);
+  )
+
+  return status;
+}
+
+/**
+ *  IDS Backend Function for Post P-State
+ *
+ *  This function is used to set Post P-State which are CPU specifically.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubPostPState (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_CPU_EARLY_PARAMS *PCpuEarlyParams;
+  IDS_STATUS idsvalue;
+  UINT8 curpstatesnum;
+
+  PCpuEarlyParams = (AMD_CPU_EARLY_PARAMS *)DataPtr;
+  curpstatesnum = IdsGetNumPstatesFamCommon (StdHeader);
+  idsvalue = AmdIdsNvReader (AGESA_IDS_NV_POSTPSTATE, IdsNvPtr, StdHeader);
+
+  if (idsvalue < (IDS_STATUS) (curpstatesnum + 3)) {
+    switch (idsvalue) {
+    case (IDS_STATUS) 0x0:
+      // Auto
+      break;
+    case (IDS_STATUS) 0x1:
+      // Maximum Performance
+      PCpuEarlyParams->MemInitPState = 0;
+      break;
+    case (IDS_STATUS) 0x2:
+      // Minimum Performance
+      PCpuEarlyParams->MemInitPState = curpstatesnum - 1;
+      break;
+    default:
+      PCpuEarlyParams->MemInitPState = (UINT8) (idsvalue - 3);
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+
+
+/**
+ *  IDS Backend Function for Memory Mode Unganged
+ *
+ *  This function is used to override Memory Mode Unganged.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubGangingMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS GangingMode;
+  IDS_NV_READ_SKIP (GangingMode, AGESA_IDS_NV_DCT_GANGING_MODE, IdsNvPtr, StdHeader) {
+    *((UINT8 *)DataPtr) = (UINT8) GangingMode;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Power Down Mode
+ *
+ *  This function is used to override Power Down Mode.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubPowerDownMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS PowerDownMode;
+  PowerDownMode = AmdIdsNvReader (AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, IdsNvPtr, StdHeader);
+  if (PowerDownMode < (IDS_STATUS)0x2) {
+    *((UINT8 *) DataPtr) = (UINT8)PowerDownMode;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Burst Length32
+ *
+ *  This function is used to override Burst Length32.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubBurstLength32 (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS BurstLength32;
+  BurstLength32 = AmdIdsNvReader (AGESA_IDS_NV_DRAM_BURST_LENGTH32, IdsNvPtr, StdHeader);
+  if (BurstLength32 < (IDS_STATUS)0x2) {
+    *((UINT8 *) DataPtr) = (UINT8)BurstLength32;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for All Memory Clks Enable
+ *
+ *  This function is used to override All Memory Clks Enable
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubAllMemClkEn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS AllMemClkEn;
+
+  AllMemClkEn = AmdIdsNvReader (AGESA_IDS_NV_ALL_MEMCLKS , IdsNvPtr, StdHeader);
+  if (AllMemClkEn < (IDS_STATUS)0x2) {
+    *((UINT8 *) DataPtr) = (UINT8)AllMemClkEn;
+  }
+
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Dll Shut Down
+ *
+ *  This function is used to override Dll Shut Down Option
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubDllShutDownSR (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS DllShutDownSR;
+  IDS_NV_READ_SKIP (DllShutDownSR, AGESA_IDS_NV_DLL_SHUT_DOWN , IdsNvPtr, StdHeader) {
+    *((UINT8 *) DataPtr) = (UINT8)DllShutDownSR;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for HT Link Configuration
+ *
+ *  Provide the nv settings to the HT code in the form of a port override list.
+ *  Create the list on the heap, so the HT code doesn't have to keep asking for it.
+ *
+ *  @param[out] Data         A reference to the HT Port Override List
+ *  @param[in]  StdHeader    Header for library and services.
+ *  @param[in] IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ */
+IDS_STATUS
+IdsSubHtLinkControl (
+     OUT   VOID  *Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  HTIDS_PORT_OVERRIDE_LIST   *ListReference;
+  HTIDS_PORT_OVERRIDE_LIST   PortOverrideList;
+  UINT32 HTlinkSocket;
+  UINT32 HTlinkPort;
+  UINT32 HTlinkFre;
+  UINT32 HTlinkWidthIn;
+  UINT32 HTlinkWidthOut;
+
+  ASSERT (IdsNvPtr != NULL);
+  ASSERT (Data != NULL);
+
+  ListReference = Data;
+  *ListReference = NULL;
+  // Allocated the number of portlist override option sets supported (currently 2) plus 1 more for terminal.
+  AllocHeapParams.RequestedBufferSize = (sizeof (HTIDS_PORT_OVERRIDE) * 3);
+  AllocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST) AllocHeapParams.BufferPtr;
+    LibAmdMemFill (PortOverrideList, HT_LIST_TERMINAL, AllocHeapParams.RequestedBufferSize, StdHeader);
+    *ListReference = PortOverrideList;
+
+    HTlinkSocket = AmdIdsNvReader (AGESA_IDS_NV_HTLINKSOCKET, IdsNvPtr, StdHeader);
+    if (HTlinkSocket != IDS_UNSUPPORTED) {
+      switch (HTlinkSocket) {
+      case (UINT32) 0xE:
+        HTlinkSocket = 0xFE;
+        break;
+      case (UINT32) 0xF:
+        HTlinkSocket = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->Socket = (UINT8) HTlinkSocket;
+    }
+    HTlinkPort = AmdIdsNvReader (AGESA_IDS_NV_HTLINKPORT, IdsNvPtr, StdHeader);
+    if (HTlinkPort != IDS_UNSUPPORTED) {
+      switch (HTlinkPort) {
+      case (UINT32) 0xC:
+        HTlinkPort = 0xFC;
+        break;
+      case (UINT32) 0xD:
+        HTlinkPort = 0xFD;
+        break;
+      case (UINT32) 0xE:
+        HTlinkPort = 0xFE;
+        break;
+      case (UINT32) 0xF:
+        HTlinkPort = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->Link = (UINT8) HTlinkPort;
+    }
+    HTlinkFre = AmdIdsNvReader (AGESA_IDS_NV_HTLINKFREQ, IdsNvPtr, StdHeader);
+    if (HTlinkFre != IDS_UNSUPPORTED) {
+      switch (HTlinkFre) {
+      case (UINT32) 0x1F:
+        HTlinkFre = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->Frequency = (UINT8) HTlinkFre;
+    }
+    HTlinkWidthIn = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHIN , IdsNvPtr, StdHeader);
+    if (HTlinkWidthIn != IDS_UNSUPPORTED) {
+      switch (HTlinkWidthIn) {
+      case (UINT32) 0x0:
+        HTlinkWidthIn = 8;
+        break;
+      case (UINT32) 0x01:
+        HTlinkWidthIn = 16;
+        break;
+      case (UINT32) 0x04:
+        HTlinkWidthIn = 2;
+        break;
+      case (UINT32) 0x5:
+        HTlinkWidthIn = 4;
+        break;
+      case (UINT32) 0x7:
+        HTlinkWidthIn = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn;
+    }
+    HTlinkWidthOut = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHOUT, IdsNvPtr, StdHeader);
+    if (HTlinkWidthOut != IDS_UNSUPPORTED) {
+      switch (HTlinkWidthOut) {
+      case (UINT32) 0x0:
+        HTlinkWidthOut = 8;
+        break;
+      case (UINT32) 0x01:
+        HTlinkWidthOut = 16;
+        break;
+      case (UINT32) 0x04:
+        HTlinkWidthOut = 2;
+        break;
+      case (UINT32) 0x5:
+        HTlinkWidthOut = 4;
+        break;
+      case (UINT32) 0x7:
+        HTlinkWidthOut = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut;
+    }
+    if (PortOverrideList->Link == 0xFC) {
+      // force both internal and external links
+      // switch first PortOverride to force External
+      HTlinkPort = 0xFE;  //Match external
+      PortOverrideList->Link = (UINT8) HTlinkPort;
+
+      // read all settings from first override list except Link
+      HTlinkSocket = PortOverrideList->Socket;
+      HTlinkPort = 0xFD;  //Match internal
+      HTlinkFre = PortOverrideList->Frequency;
+      HTlinkWidthIn = PortOverrideList->WidthIn;
+      HTlinkWidthOut = PortOverrideList->WidthOut;
+
+      // copy settings into second override list
+      PortOverrideList++;
+
+      PortOverrideList->Socket = (UINT8) HTlinkSocket;
+      PortOverrideList->Link = (UINT8) HTlinkPort;
+      PortOverrideList->Frequency = (UINT8) HTlinkFre;
+      PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn;
+      PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut;
+    }
+  }
+  return IDS_SUCCESS;
+}
+/**
+ *  IDS Backend Function for Select Platform Power Policy
+ *
+ *  Parameters:
+ *  @param[in,out]   DataPtr  The Pointer of PLATFORM_CONFIGURATION.
+ *  @param[in,out]   StdHeader        AMD standard header config param
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+IDS_STATUS
+IdsSubPowerPolicyOverride (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  PLATFORM_CONFIGURATION *PlatformConfig;
+  IDS_STATUS NvValue;
+
+  PlatformConfig = (PLATFORM_CONFIGURATION *)DataPtr;
+
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_POWER_POLICY, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    case IDS_POWER_POLICY_PERFORMANCE:
+      PlatformConfig->PlatformProfile.PlatformPowerPolicy = Performance;
+      break;
+    case IDS_POWER_POLICY_POWER:
+      PlatformConfig->PlatformProfile.PlatformPowerPolicy = BatteryLife;
+      break;
+    case IDS_POWER_POLICY_AUTO:
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+
+  return IDS_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm
new file mode 100644
index 0000000000..9615e853cd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm
@@ -0,0 +1,362 @@
+;/**
+; * @file
+; *
+; * Ids Assembly library 32bit
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  IDS
+; * @e \$Revision: 14305 $   @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+public IdsDelay
+IdsDelay  PROC  NEAR C USES EAX EDX
+Local targetedx:dword, targeteax:dword
+  rdtsc
+;set target time
+  add eax,1500000000
+  adc edx,0
+  mov targetedx,edx
+  mov targeteax,eax
+
+  rdtsc
+;set "Si!=0" skip below loop
+  .while(1)
+    .if(si != 0)
+      jmp delay_exit
+    .endif
+    .if(edx > targetedx)
+      jmp delay_exit
+    .elseif (edx == targetedx)
+      .if(eax > targeteax)
+        jmp delay_exit
+      .endif
+    .endif
+    rdtsc
+  .endw
+delay_exit:
+  ret
+IdsDelay    ENDP
+;/*++
+;
+;Routine Description:
+;
+;  IdsErrorStop -- Function for Assert
+;
+;Arguments:
+;  Filecode
+;
+;Returns:
+;
+;  None
+;
+;--*/
+public IdsErrorStop
+IdsErrorStop PROC NEAR  C filecode:dword
+local tmpebx:dword,tmpedx:dword
+  pushad
+
+  mov     si,0                      ; Si is used as control flag, "Si!=0" skip postcode loop
+; send debug port 1st, then fire SimNow breakpoint
+  mov     ax,  0deadh
+  out     0e0h, ax
+  mov     eax, filecode
+  out     84h, eax
+  mov     eax, 0BACCD00Bh         ; Backdoor in SimNow
+  mov     ebx, 2                  ; Select breakpoint feature
+  cpuid
+
+  mov   ebx,0dead0000h
+  mov   edx,filecode
+  ror   edx,16
+  mov   bx,dx
+  mov   dx,0
+;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
+  mov   tmpebx,ebx
+  mov   tmpedx,edx
+
+  xor   eax,eax
+  mov   cl,6
+
+  .while((cl != 0) && (si == 0))
+    .if(cl <= 2)
+      shld  eax,edx,8
+      shl   edx,8
+    .else
+      shld  eax,ebx,8
+      shl   ebx,8
+    .endif
+
+    out   80h,eax
+    call IdsDelay
+    dec cl
+    .if(cl == 0)
+      mov   cl,6
+      mov   ebx,tmpebx
+      mov   edx,tmpedx
+    .endif
+  .endw
+
+  popad
+  xor eax,eax
+  ret
+IdsErrorStop  endp
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Stop CPU
+; *
+; *
+; *
+; */
+IDS_STOP_HERE MACRO
+@@:
+  jmp short @b
+ENDM
+
+;======================================================================
+; IdsExceptionHandler:  Simply performs a jmp $ and IRET.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC _IdsExceptionHandler
+PUBLIC _SizeIdtDescriptor
+PUBLIC _SizeTotalIdtDescriptors
+
+; Size of each exception MUST be the same
+Exception00:
+  push eax
+  mov  al, 00h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception01:
+  push eax
+  mov  al, 01h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception02:
+  push eax
+  mov  al, 02h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception03:
+  push eax
+  mov  al, 03h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception04:
+  push eax
+  mov  al, 04h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception05:
+  push eax
+  mov  al, 05h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception06:
+  push eax
+  mov  al, 06h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception07:
+  push eax
+  mov  al, 07h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception08:
+  push eax
+  mov  al, 08h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception09:
+  push eax
+  mov  al, 09h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception10:
+  push eax
+  mov  al, 10h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception11:
+  push eax
+  mov  al, 11h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception12:
+  push eax
+  mov  al, 12h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception13:
+  push eax
+  mov  al, 13h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception14:
+  push eax
+  mov  al, 14h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception15:
+  push eax
+  mov  al, 15h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception16:
+  push eax
+  mov  al, 16h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception17:
+  push eax
+  mov  al, 17h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception18:
+  push eax
+  mov  al, 18h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception19:
+  push eax
+  mov  al, 19h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception20:
+  push eax
+  mov  al, 20h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception21:
+  push eax
+  mov  al, 21h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception22:
+  push eax
+  mov  al, 22h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception23:
+  push eax
+  mov  al, 23h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception24:
+  push eax
+  mov  al, 24h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception25:
+  push eax
+  mov  al, 25h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception26:
+  push eax
+  mov  al, 26
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception27:
+  push eax
+  mov  al, 27h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception28:
+  push eax
+  mov  al, 28h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception29:
+  push eax
+  mov  al, 29h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception30:
+  push eax
+  mov  al, 30h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception31:
+  push eax
+  mov  al, 31h
+  jmp  near ptr CommonHandler
+CommonHandler:
+  out 80h, al
+  pop eax
+  IDS_STOP_HERE
+  iretd
+
+_IdsExceptionHandler dq offset Exception00
+_SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
+_SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
+
+END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
new file mode 100644
index 0000000000..2651494e4f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
@@ -0,0 +1,369 @@
+;/**
+; * @file
+; *
+; * Ids Assembly library 64bit
+; *
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  IDS
+; * @e \$Revision: 14126 $   @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*****************************************************************************
+
+.code
+IdsDelay  PROC
+  push    rax
+  push    rdx
+  push    rbx
+  xor     rax,rax
+  xor     rdx,rdx
+  rdtsc
+;set target time
+  add     eax,1500000000
+  adc     edx,0
+  shl     rdx,32
+  add     rdx,rax
+  mov     rbx,rdx
+;rbx store the target
+;set "Si!=0" skip below loop
+__loop:
+  cmp     si,0
+  jnz     __loopexit
+  rdtsc
+  shl     rdx,32
+  add     rdx,rax
+  cmp     rdx,rbx
+  jae     __loopexit
+  jmp     __loop
+__loopexit:
+  pop     rbx
+  pop     rdx
+  pop     rax
+  ret
+IdsDelay    ENDP
+;/*++
+;
+;Routine Description:
+;
+;  IdsErrorStop -- Function for Assert
+;
+;Arguments:
+;  Filecode
+;
+;Returns:
+;
+;  None
+;
+;--*/
+public IdsErrorStop
+IdsErrorStop PROC
+;As x64 calling convention RCX is used as input parameters
+  push    rcx
+  push    rbx
+  push    si
+  push    dx
+  push    rbx
+
+  mov     si,0                      ; Si is used as control flag, "Si!=0" skip postcode loop
+; send debug port 1st, then fire SimNow breakpoint
+  mov     ax,  0deadh
+  out     0e0h, ax
+  mov     eax, ecx
+  out     84h, eax
+  mov     eax, 0BACCD00Bh         ; Backdoor in SimNow
+  mov     ebx, 2                  ; Select breakpoint feature
+  cpuid
+
+  mov     rax,0dead00000000h
+  or      rcx,rax
+;rcx= 0dead__FILECODE
+  shl     rcx,16
+;rcx= 0dead__FILECODE__0000
+  mov     rbx,rcx
+
+  xor     rax,rax
+  mov     dl,6
+
+IdsErrorStopLoop:
+  cmp     dl,0
+  jz      IdsErrorStopExit
+  cmp     si,0
+  jnz     IdsErrorStopExit
+
+  shld    rax,rcx,8
+  shl     rcx,8
+  out     80h,eax
+  call    IdsDelay
+
+  dec     dl
+  cmp     dl,0
+  jnz     _nextloop
+  mov     dl,6
+  mov     rcx,rbx
+_nextloop:
+  jmp     IdsErrorStopLoop
+IdsErrorStopExit:
+  pop     rbx
+  pop     dx
+  pop     si
+  pop     rbx
+  pop     rcx
+  xor     rax,rax
+  ret
+IdsErrorStop  endp
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Stop CPU
+; *
+; *
+; *
+; */
+IDS_STOP_HERE MACRO
+@@:
+  jmp short @b
+ENDM
+
+;======================================================================
+; IdsExceptionHandler:  Simply performs a jmp $ and IRET.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC IdsExceptionHandler
+PUBLIC SizeIdtDescriptor
+PUBLIC SizeTotalIdtDescriptors
+
+; Size of each exception MUST be the same
+Exception00:
+  push rax
+  mov  al, 00h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception01:
+  push rax
+  mov  al, 01h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception02:
+  push rax
+  mov  al, 02h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception03:
+  push rax
+  mov  al, 03h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception04:
+  push rax
+  mov  al, 04h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception05:
+  push rax
+  mov  al, 05h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception06:
+  push rax
+  mov  al, 06h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception07:
+  push rax
+  mov  al, 07h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception08:
+  push rax
+  mov  al, 08h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception09:
+  push rax
+  mov  al, 09h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception10:
+  push rax
+  mov  al, 10h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception11:
+  push rax
+  mov  al, 11h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception12:
+  push rax
+  mov  al, 12h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception13:
+  push rax
+  mov  al, 13h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception14:
+  push rax
+  mov  al, 14h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception15:
+  push rax
+  mov  al, 15h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception16:
+  push rax
+  mov  al, 16h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception17:
+  push rax
+  mov  al, 17h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception18:
+  push rax
+  mov  al, 18h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception19:
+  push rax
+  mov  al, 19h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception20:
+  push rax
+  mov  al, 20h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception21:
+  push rax
+  mov  al, 21h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception22:
+  push rax
+  mov  al, 22h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception23:
+  push rax
+  mov  al, 23h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception24:
+  push rax
+  mov  al, 24h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception25:
+  push rax
+  mov  al, 25h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception26:
+  push rax
+  mov  al, 26
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception27:
+  push rax
+  mov  al, 27h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception28:
+  push rax
+  mov  al, 28h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception29:
+  push rax
+  mov  al, 29h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception30:
+  push rax
+  mov  al, 30h
+  jmp  near ptr CommonHandler
+; Size of each exception MUST be the same
+Exception31:
+  push rax
+  mov  al, 31h
+  jmp  near ptr CommonHandler
+CommonHandler:
+  out 80h, al
+  pop rax
+  IDS_STOP_HERE
+  iretq
+
+IdsExceptionHandler dq offset Exception00
+SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
+SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
+
+END
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c
new file mode 100644
index 0000000000..b9a69b7863
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c
@@ -0,0 +1,442 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "IdsNvToCmos.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern IDS_NV_TO_CMOS gIdsNVToCmos[];
+
+/**
+ *
+ *  Read CMOS
+ *
+ *  @param[in] IndexPort   Index port of access CMOS
+ *  @param[in] DataPort   Data port of access CMOS
+ *  @param[in] Index   Index of CMOS
+ *  @param[in,out] Value   Point to Value
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ **/
+VOID
+IdsReadCmos (
+  IN       UINT16       IndexPort,
+  IN       UINT16       DataPort,
+  IN       UINT16       Index,
+  IN OUT   UINT8        *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth8, IndexPort, &Index, StdHeader);
+  LibAmdIoRead (AccessWidth8, DataPort, Value, StdHeader);
+}
+/**
+ *
+ *  Write CMOS
+ *
+ *  @param[in] IndexPort   Index port of access CMOS
+ *  @param[in] DataPort   Data port of access CMOS
+ *  @param[in] Index   Index of CMOS
+ *  @param[in,out] Value   Point to Value
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ **/
+VOID
+IdsWriteCmos (
+  IN       UINT16       IndexPort,
+  IN       UINT16       DataPort,
+  IN       UINT16       Index,
+  IN OUT   UINT8        *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth8, IndexPort, &Index, StdHeader);
+  LibAmdIoWrite (AccessWidth8, DataPort, Value, StdHeader);
+}
+/**
+ *
+ *  Get IDS CMOS save region in the AGESA Heap.
+ *
+ *  @param[in,out] IdsCmosRegion   The Pointer of IDS CMOS save address in heap.
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of NV Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of NV Table.
+ **/
+AGESA_STATUS
+AmdGetIdsCmosSaveRegion (
+  IN OUT   VOID  **IdsCmosRegion,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  LocateHeapStructPtr.BufferHandle = IDS_NV_TO_CMOS_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status == AGESA_SUCCESS) {
+    *IdsCmosRegion = LocateHeapStructPtr.BufferPtr;
+  } else {
+    //Allocated the heap when can't located
+    AllocHeapParams.RequestedBufferSize = IDS_CMOS_REGION_END - IDS_CMOS_REGION_START + 1;
+    AllocHeapParams.BufferHandle = IDS_NV_TO_CMOS_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    status = HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader);
+    if (status == AGESA_SUCCESS) {
+      *IdsCmosRegion = AllocHeapParams.BufferPtr;
+    }
+  }
+  return status;
+}
+
+
+/**
+ *  IDS Backend Function for save BSP's NV heap to CMOS
+ *
+ *
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsCheckCmosValid (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 CmosIndex;
+  UINT8 TmpValue;
+  UINT8 Len;
+  UINT8 Sum;
+  CmosIndex = IDS_CMOS_REGION_SIGNATURE_OFFSET;
+  //Validate the Signature
+  IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+  if (TmpValue != 'N') {
+    return IDS_UNSUPPORTED;
+  }
+
+  CmosIndex++;
+  IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+  if (TmpValue != 'V') {
+    return IDS_UNSUPPORTED;
+  }
+
+  CmosIndex = IDS_CMOS_REGION_LENGTH_OFFSET;
+  IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &Len, StdHeader);
+  if (Len > (IDS_CMOS_REGION_END - IDS_CMOS_REGION_START - IDS_NV_TO_CMOS_HEADER_SIZE + 1)) {
+    return IDS_UNSUPPORTED;
+  }
+  Sum = 0;
+  CmosIndex = IDS_CMOS_REGION_CHECKSUM_OFFSET;
+  for (; CmosIndex < IDS_CMOS_REGION_DATA_OFFSET + Len; CmosIndex++) {
+    IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+    Sum = (UINT8) (Sum + TmpValue);
+  }
+  if (Sum != 0) {
+    return IDS_UNSUPPORTED;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *
+ *  AP get NV from CMOS
+ *
+ *  If Ap Can't get Nv Data from Callout, Try to Create NV heap via the
+ *  CMOS data area save by BSP previous
+
+ *
+ *  @param[in,out] StdHeader    The Pointer of IDS Initial Parameter
+ *
+ *  @retval AGESA_SUCCESS       Success to get the NV from CMOS
+ *  @retval AGESA_ERROR         Fail to get
+ *
+ **/
+AGESA_STATUS
+AmdIdsApGetNvFromCmos (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+  UINT8 CmosIndex;
+  UINT8 TmpValue;
+  UINT8 TmpU16Value;
+  UINT8 k;
+  UINT16 i;
+  IDS_NV_ITEM *NvPtr;
+  UINT8 Len;
+  status = AGESA_ERROR;
+  if (IdsCheckCmosValid (StdHeader) == IDS_SUCCESS) {
+    AllocHeapParams.RequestedBufferSize = sizeof (IDS_CONTROL_STRUCT);
+    AllocHeapParams.RequestedBufferSize += (IDS_CMOS_REGION_END - IDS_CMOS_REGION_START - IDS_NV_TO_CMOS_HEADER_SIZE + 2) * sizeof (IDS_NV_ITEM) ;
+    AllocHeapParams.BufferHandle = IDS_CONTROL_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+
+    //
+    // Allocate data buffer in heap
+    //
+    status = HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader);
+    if (status == AGESA_SUCCESS) {
+      IdsCtrlPtr = (IDS_CONTROL_STRUCT *) AllocHeapParams.BufferPtr;
+      IdsCtrlPtr->IgnoreIdsDefault = TRUE;
+      IdsCtrlPtr->IdsHeapMemSize = AllocHeapParams.RequestedBufferSize;
+      IdsCtrlPtr->IdsNvTableOffset = sizeof (IDS_CONTROL_STRUCT);
+      NvPtr = (IDS_NV_ITEM *) (AllocHeapParams.BufferPtr + IdsCtrlPtr->IdsNvTableOffset);
+      i = 0;
+      CmosIndex = IDS_CMOS_REGION_LENGTH_OFFSET;
+      IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &Len, StdHeader);
+      CmosIndex = IDS_CMOS_REGION_DATA_OFFSET;
+      while ((gIdsNVToCmos[i].Length != IDS_NV_TO_CMOS_LEN_END) &&
+           (gIdsNVToCmos[i].IDS_NV_ID != IDS_NV_TO_CMOS_ID_END) &&
+           (CmosIndex <= IDS_CMOS_REGION_END) &&
+           (Len-- > 0)) {
+        if (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_BYTE || gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_WORD) {
+          TmpU16Value = 0;
+          for (k = 0; k < gIdsNVToCmos[i].Length; k++, CmosIndex++) {
+            IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+            TmpU16Value |= (UINT16)TmpValue << (k * 8);
+          }
+          if ((TmpU16Value != IDS_NV_TO_CMOS_BYTE_IGNORED && (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_BYTE)) ||
+              (TmpU16Value != IDS_NV_TO_CMOS_WORD_IGNORED && (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_WORD))) {
+            NvPtr->IdsNvId = gIdsNVToCmos[i].IDS_NV_ID;
+            NvPtr->IdsNvValue = TmpU16Value;
+            NvPtr ++;
+          }
+        }
+        i++;
+      }
+      NvPtr->IdsNvId = AGESA_IDS_NV_END;
+    }
+  }
+  return status;
+}
+
+/**
+ *  IDS Backend Function for Restore  CMOS
+ *
+ *
+ *  @param[in,out]   DataPtr      NULL
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubRestoreCmos (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  UINT8 *PCmosSave;
+  UINT8 CmosIndex;
+
+  //Save CMOS to BSP heap
+  if (AmdGetIdsCmosSaveRegion ((VOID **) &PCmosSave, StdHeader) == AGESA_SUCCESS) {
+    for (CmosIndex = IDS_CMOS_REGION_START; CmosIndex <= IDS_CMOS_REGION_END; CmosIndex++, PCmosSave++) {
+      IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, PCmosSave, StdHeader);
+    }
+  }
+  return IDS_SUCCESS;
+}
+/**
+ *  IDS Backend Function for save BSP's NV heap to CMOS
+ *
+ *
+ *  @param[in,out]   DataPtr      NULL
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubSaveBspNvHeapToCmos (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  UINT8 i;
+  UINT8 k;
+  UINT8 CmosIndex;
+  UINT8 TmpValue;
+  UINT8 Sum;
+  UINT8 Len;
+  UINT8 *PCmosSave;
+  IDS_STATUS IdsNvValue;
+
+  //Save CMOS to BSP heap
+  if (AmdGetIdsCmosSaveRegion ((VOID **) &PCmosSave, StdHeader) == AGESA_SUCCESS) {
+    for (CmosIndex = IDS_CMOS_REGION_START; CmosIndex <= IDS_CMOS_REGION_END; CmosIndex++) {
+      IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+      *(PCmosSave++) = TmpValue;
+    }
+    //The CMOS Region is saved to heap,Now we can save BSP NV to CMOS
+    i = 0;
+    CmosIndex = IDS_CMOS_REGION_SIGNATURE_OFFSET;
+    //CMOS Map
+    // **********************************************************************************
+    // Field          |   Offset   | Description
+    // **********************************************************************************
+    // Signature      |     0      | 'NV' specify the IDS Cmos save region
+    // **********************************************************************************
+    // Length         |     2      | Actual Length of all save NV, may less than platform
+    //               |            | define
+    // **********************************************************************************
+    // CheckSum       |     3      | CheckSum of all NV fields exclue Signature & Length
+    // **********************************************************************************
+    // NVSaveRegion   |     4      | Nv Save Region
+    // **********************************************************************************
+    // Set Signature 'NV';
+    TmpValue = 'N';
+    IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+    CmosIndex++;
+    TmpValue = 'V';
+    IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+
+    CmosIndex = IDS_CMOS_REGION_DATA_OFFSET;
+    Sum = 0;
+    Len = 0;
+    while ((gIdsNVToCmos[i].Length != IDS_NV_TO_CMOS_LEN_END) &&
+               (gIdsNVToCmos[i].IDS_NV_ID != IDS_NV_TO_CMOS_ID_END) &&
+               (CmosIndex <= IDS_CMOS_REGION_END)) {
+      //Get NV Value length
+      if (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_BYTE || gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_WORD) {
+        IdsNvValue = AmdIdsNvReader (gIdsNVToCmos[i].IDS_NV_ID, IdsNvPtr, StdHeader);
+        for (k = 0; k < gIdsNVToCmos[i].Length; k++) {
+          TmpValue = (UINT8) ((IdsNvValue >> (8 * k)) & 0xFF);
+          Sum = (UINT8) (Sum + TmpValue);
+          Len++;
+          IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+          CmosIndex++;
+        }
+      } else {
+        ASSERT (FALSE);
+      }
+      i++;
+    }
+    CmosIndex = IDS_CMOS_REGION_LENGTH_OFFSET;
+    IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &Len, StdHeader);
+    CmosIndex = IDS_CMOS_REGION_CHECKSUM_OFFSET;
+    TmpValue = (UINT8) (0x100 - Sum);
+    IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader);
+  }
+  return IDS_SUCCESS;
+}
+
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock =
+{
+  IDS_FEAT_NV_TO_CMOS,
+  IDS_BSP_ONLY,
+  IDS_CPU_Early_Override,
+  IDS_FAMILY_ALL,
+  IdsSubSaveBspNvHeapToCmos
+};
+
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock =
+{
+  IDS_FEAT_NV_TO_CMOS,
+  IDS_BSP_ONLY,
+  IDS_BEFORE_AP_EARLY_HALT,
+  IDS_FAMILY_ALL,
+  IdsSubRestoreCmos
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h
new file mode 100644
index 0000000000..4e2a41f0d1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+#ifndef _IDSNVTOCMOS_H_
+#define _IDSNVTOCMOS_H_
+AGESA_STATUS
+AmdGetIdsCmosSaveRegion (
+  IN OUT   VOID  **IdsCmosRegion,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsCheckCmosValid (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+AmdIdsApGetNvFromCmos (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsSubRestoreCmos (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubSaveBspNvHeapToCmos (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+#define IDS_NV_TO_CMOS_HEADER_SIZE   4
+
+#define IDS_CMOS_REGION_SIGNATURE_OFFSET  IDS_CMOS_REGION_START
+#define IDS_CMOS_REGION_LENGTH_OFFSET (IDS_CMOS_REGION_START + 2)
+#define IDS_CMOS_REGION_CHECKSUM_OFFSET (IDS_CMOS_REGION_START + 3)
+#define IDS_CMOS_REGION_DATA_OFFSET (IDS_CMOS_REGION_START + 4)
+
+#define IDS_NV_TO_CMOS_BYTE_IGNORED   0xFF
+#define IDS_NV_TO_CMOS_WORD_IGNORED   0xFFFF
+#endif  //_IDSNVTOCMOS_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
new file mode 100644
index 0000000000..24d64b3fc0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
@@ -0,0 +1,229 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63552 $   @e \$Date: 2011-12-26 19:46:05 -0600 (Mon, 26 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "AMD.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "IdsDebugPrint.h"
+#include "IdsDpHdtout.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_DEBUG_IDSDEBUG_FILECODE
+
+/*--------------------------------------------------------------------------------------*/
+/**
+ *  IDS back-end code for AGESA_TESTPOINT
+ *
+ *  @param[in] TestPoint  Progress indicator value, see @ref AGESA_TP
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+/*--------------------------------------------------------------------------------------*/
+VOID
+IdsAgesaTestPoint (
+  IN       AGESA_TP      TestPoint,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PORT, &TestPoint, StdHeader);
+}
+
+/**
+ *
+ *  HDT out Function for Assert.
+ *
+ *  fire a HDTOUT Command of assert to let hdtout script do corresponding things.
+ *
+ *  @param[in,out] FileCode    FileCode of the line
+ *
+ **/
+#if 0
+VOID
+AmdIdsDebugPrintAssert (
+  IN      UINT32 FileCode
+  )
+{
+  //TODO:if (AmdIdsHdtOutSupport ()) {
+  //  IdsOutPort (HDTOUT_ASSERT, FileCode, 0);
+  //}
+}
+#endif
+
+/**
+ *  IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval         TRUE     No error
+ **/
+BOOLEAN
+IdsAssert (
+  IN      UINT32 FileCode
+  )
+{
+  UINT32 file;
+  UINT32 line;
+
+  file = (FileCode >> 16);
+  line = (FileCode & 0xFFFF);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line);
+  IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL);
+  IDS_HDT_CONSOLE_ASSERT (FileCode);
+  //IdsErrorStop (FileCode);
+  return TRUE;
+}
+
+/**
+ *  IDS Backend Function for Memory timeout control
+ *
+ *  This function is used to override Memory timeout control.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of UINT8.
+ *
+ **/
+VOID
+IdsMemTimeOut (
+  IN OUT   VOID *DataPtr
+  )
+{
+//TODO:  UINTN i;
+//
+//  IDS_DEBUG_PRINT **DebugPrintList;
+//
+//  GetDebugPrintList (&DebugPrintList);
+//
+//  for (i = 0; DebugPrintList[i] != NULL; i++) {
+//    if (DebugPrintList[i]->support ()) {
+//      // Turn timeout off if any Debug service is on
+//      *((UINT8 *)DataPtr) = (UINT8)0;
+//    }
+//  }
+}
+
+/**
+ *
+ *  IDS Debug Function to check the sentinels are intact
+ *
+ * This function complete heap walk and check to be performed at any time.
+ *
+ * @param[in]      StdHeader         Config handle for library and services.
+ *
+ * @retval         TRUE     No error
+ *
+ **/
+BOOLEAN
+AmdHeapIntactCheck (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/**
+ * Check for CAR Corruption, the performance monitor number three programed to log the CAR Corruption.
+ * Check to see if control register is enabled and then check the preformance counter and stop the system by executing
+ * IDS_ERROR_TRAP if counter has any value other than zero.
+ *
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *
+ **/
+VOID
+IdsCarCorruptionCheck (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+
+  UINT64 Perf_Msr;
+
+  LibAmdMsrRead (MSR_PERF_CONTROL3, (UINT64*)&Perf_Msr, StdHeader);
+  if ((Perf_Msr & PERF_RESERVE_BIT_MASK) == PERF_CAR_CORRUPTION_EVENT) {
+    LibAmdMsrRead (MSR_PERF_COUNTER3, (UINT64*)&Perf_Msr, StdHeader);
+    if ((Perf_Msr != 0)) {
+      IDS_ERROR_TRAP;
+    }
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c
new file mode 100644
index 0000000000..67ec5974c2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c
@@ -0,0 +1,678 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Print Routines
+ *
+ * Contains all functions related to IDS Debug Print
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "IdsDebugPrint.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE
+
+//
+// Also support coding convention rules for var arg macros
+//
+#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
+typedef CHAR8 *VA_LIST;
+#define VA_START(ap, v) (ap = (VA_LIST) & (v) + _INT_SIZE_OF (v))
+#define VA_ARG(ap, t)   (*(t *) ((ap += _INT_SIZE_OF (t)) - _INT_SIZE_OF (t)))
+#define VA_END(ap)      (ap = (VA_LIST) 0)
+
+#define LEFT_JUSTIFY    0x01
+#define PREFIX_SIGN     0x02
+#define PREFIX_BLANK    0x04
+#define COMMA_TYPE      0x08
+#define LONG_TYPE       0x10
+#define PREFIX_ZERO     0x20
+
+#define MAX_LOCAL_BUFFER_SIZE   512
+#define BUFFER_OVERFLOW 0xFFFF
+
+/**
+ *  Check If any print service is enabled.
+ *
+ *  @param[in] DebugPrintList    The Pointer to print service list
+ *
+ *  @retval       TRUE    At least on print service is enabled
+ *  @retval       FALSE   All print service is disabled
+ *
+ **/
+STATIC BOOLEAN
+AmdIdsDebugPrintCheckSupportAll (
+  IN      IDS_DEBUG_PRINT **DebugPrintList
+  )
+{
+  BOOLEAN IsSupported;
+  UINTN i;
+  IsSupported = FALSE;
+  for (i = 0; DebugPrintList[i] != NULL; i++) {
+    if (DebugPrintList[i]->support ()) {
+      IsSupported = TRUE;
+    }
+  }
+  return IsSupported;
+}
+
+/**
+ *  Parses flag and width information from theFormat string and returns the next index
+ *  into the Format string that needs to be parsed. See file headed for details of Flag and Width.
+ *
+ *  @param[in]  Format  Current location in the AvSPrint format string.
+ *  @param[out] Flags  Returns flags
+ *  @param[out] Width  Returns width of element
+ *  @param[out] Marker Vararg list that may be partially consumed and returned.
+ *
+ *  @retval Pointer indexed into the Format string for all the information parsed by this routine.
+ *
+ **/
+STATIC CHAR8 *
+GetFlagsAndWidth (
+  IN       CHAR8 *Format,
+     OUT   UINTN *Flags,
+     OUT   UINTN *Width,
+  IN OUT   VA_LIST *Marker
+  )
+{
+  UINTN   Count;
+  BOOLEAN Done;
+
+  *Flags = 0;
+  *Width = 0;
+  for (Done = FALSE; !Done; ) {
+    Format++;
+
+    switch (*Format) {
+
+    case '-':			/* ' - ' */
+      *Flags |= LEFT_JUSTIFY;
+      break;
+    case '+':			/* ' + ' */
+      *Flags |= PREFIX_SIGN;
+      break;
+    case ' ':
+      *Flags |= PREFIX_BLANK;
+      break;
+    case ',':			/* ', ' */
+      *Flags |= COMMA_TYPE;
+      break;
+    case 'L':
+    case 'l':
+      *Flags |= LONG_TYPE;
+      break;
+
+    case '*':
+      *Width = VA_ARG (*Marker, UINTN);
+      break;
+
+    case '0':
+      *Flags |= PREFIX_ZERO;
+      break;
+
+    case '1':
+    case '2':
+    case '3':
+    case '4':
+    case '5':
+    case '6':
+    case '7':
+    case '8':
+    case '9':
+      Count = 0;
+      do {
+        Count = (Count * 10) + *Format - '0';
+        Format++;
+      } while ((*Format >= '0')  &&  (*Format <= '9'));
+      Format--;
+      *Width = Count;
+      break;
+
+    default:
+      Done = TRUE;
+    }
+  }
+  return Format;
+}
+
+CHAR8 STATIC HexStr[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+extern CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[];
+
+/**
+ *
+ *  @param[in,out] Value  - Hex value to convert to a string in Buffer.
+ *
+ *
+ */
+VOID
+GetDebugPrintList (
+  IN OUT   CONST IDS_DEBUG_PRINT   ***pIdsDebugPrintListPtr
+  )
+{
+  *pIdsDebugPrintListPtr = &IdsDebugPrint[0];
+}
+
+/**
+ *
+ *  @param[in,out] Buffer Location to place ascii hex string of Value.
+ *  @param[in] Value  - Hex value to convert to a string in Buffer.
+ *  @param[in] Flags  - Flags to use in printing Hex string, see file header for details.
+ *  @param[in] Width  - Width of hex value.
+ *  @param[in,out] BufferSize  - Size of input buffer
+ *
+ *  @retval Number of characters printed.
+ **/
+
+STATIC UINTN
+ValueToHexStr (
+  IN OUT   CHAR8   *Buffer,
+  IN       UINT64      Value,
+  IN       UINTN       Flags,
+  IN       UINTN       Width,
+  IN OUT   UINTN       *BufferSize
+  )
+{
+  CHAR8   TempBuffer[30];
+  CHAR8   *TempStr;
+  CHAR8   Prefix;
+  CHAR8   *BufferPtr;
+  UINTN   Count;
+  UINTN   Index;
+
+  TempStr = TempBuffer;
+  BufferPtr = Buffer;
+  //
+  // Count starts at one since we will null terminate. Each iteration of the
+  // loop picks off one nibble. Oh yea TempStr ends up backwards
+  //
+  Count = 0;
+  do {
+    *(TempStr++) = HexStr[Value & 0x0f];
+    Value >>= 4;
+    Count++;
+  } while (Value != 0);
+
+  if (Flags & PREFIX_ZERO) {
+    Prefix = '0';
+  } else if (!(Flags & LEFT_JUSTIFY)) {
+    Prefix = ' ';
+  } else {
+    Prefix = 0x00;
+  }
+  for (Index = Count; Index < Width; Index++) {
+    *(TempStr++) = Prefix;
+  }
+
+  //
+  // Reverse temp string into Buffer.
+  //
+  while (TempStr != TempBuffer) {
+    (*BufferSize)--;
+    if (*BufferSize == 0) {
+      return BUFFER_OVERFLOW;
+    }
+    *(BufferPtr++) = *(--TempStr);
+  }
+
+  *BufferPtr = 0;
+  return Index;
+}
+
+/**
+ *  Prints a Value as a decimal number in Buffer
+ *
+ *  @param[in] Buffer  Location to place ascii decimal number string of Value.
+ *  @param[in] Value  Decimal value to convert to a string in Buffer.
+ *  @param[in] Flags  Flags to use in printing decimal string, see file header for details.
+ *  @param[in,out] BufferSize  Size of input buffer
+ *
+ *  @retval Number of characters printed.
+ *
+**/
+
+STATIC UINTN
+ValueToString (
+  IN OUT   CHAR8   *Buffer,
+  IN       INT32       Value,
+  IN       UINTN       Flags,
+  IN OUT   UINTN       *BufferSize
+  )
+{
+  CHAR8   TempBuffer[30];
+  CHAR8   *TempStr;
+  CHAR8   *BufferPtr;
+  UINTN   Count;
+  UINTN   Remainder;
+
+  ASSERT (*BufferSize);
+  TempStr = TempBuffer;
+  BufferPtr = Buffer;
+  Count = 0;
+
+  if (Value < 0) {
+    (*BufferSize)--;
+    if (*BufferSize == 0) {
+      return BUFFER_OVERFLOW;
+    }
+    *(BufferPtr++) = '-';	/* ' - ' */
+    Value = - Value;
+    Count++;
+  }
+
+  do {
+    Remainder = Value % 10;
+    Value /= 10;
+    *(TempStr++) = (CHAR8)(Remainder + '0');
+    Count++;
+    if ((Flags & COMMA_TYPE) == COMMA_TYPE) {
+      if (Count % 3 == 0) {
+        *(TempStr++) = ',';
+      }
+    }
+  } while (Value != 0);
+
+  //
+  // Reverse temp string into Buffer.
+  //
+  while (TempStr != TempBuffer) {
+    (*BufferSize)--;
+    if (*BufferSize == 0) {
+      return BUFFER_OVERFLOW;
+    }
+    *(BufferPtr++) = *(--TempStr);
+  }
+
+  *BufferPtr = 0;
+  return Count;
+}
+
+/**
+ *  Worker function for print string to buffer
+ *
+ *  @param[in] Flag    - filter flag
+ *  @param[in] *Format - format string
+ *  @param[in] Marker  - Variable parameter
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[out] OutputStringLen  - output string length, include '\0' at the end
+ *
+ *  @retval    IDS_DEBUG_PRINT_SUCCESS      succeed
+ *  @retval    IDS_DEBUG_PRINT_BUFFER_OVERFLOW      input buffer overflow
+**/
+STATIC IDS_DEBUG_PRINT_STATUS
+AmdIdsDebugPrintWorker (
+  IN       CONST CHAR8 *Format,
+  IN       VA_LIST Marker,
+  IN       CHAR8 *Buffer,
+  IN       UINTN BufferSize,
+     OUT   UINTN *OutputStringLen
+  )
+{
+  UINTN Index;
+  UINTN Length;
+  UINTN Flags;
+  UINTN Width;
+  UINT64 Value;
+  CHAR8 *AsciiStr;
+
+  //Init the default Value
+  Index = 0;
+  //
+  // Process format string
+  //
+  for (; (*Format != '\0') && (BufferSize > 0); Format++) {
+    if (*Format != '%') {
+      Buffer[Index++] = *Format;
+      BufferSize--;
+    } else {
+      Format = GetFlagsAndWidth ((CHAR8 *)Format, &Flags, &Width, &Marker);
+      switch (*Format) {
+      case 'X':
+        Flags |= PREFIX_ZERO;
+        Width = sizeof (UINT64) * 2;
+        //
+        // break skipped on purpose
+        //
+      case 'x':
+        if ((Flags & LONG_TYPE) == LONG_TYPE) {
+          Value = VA_ARG (Marker, UINT64);
+        } else {
+          Value = VA_ARG (Marker, UINTN);
+        }
+        Length = ValueToHexStr (&Buffer[Index], Value, Flags, Width, &BufferSize);
+        if (Length != BUFFER_OVERFLOW) {
+          Index += Length;
+        } else {
+          return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+        }
+        break;
+
+      case 'd':
+        Value = (UINTN)VA_ARG (Marker, UINT32);
+        Length = ValueToString (&Buffer[Index], (UINT32)Value, Flags, &BufferSize);
+        if (Length != BUFFER_OVERFLOW) {
+          Index += Length;
+        } else {
+          return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+        }
+
+        break;
+
+      case 's':
+      case 'S':
+        AsciiStr = (CHAR8 *)VA_ARG (Marker, CHAR8 *);
+        while (*AsciiStr != '\0') {
+          BufferSize--;
+          if (BufferSize == 0) {
+            return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+          }
+          Buffer[Index++] = *AsciiStr++;
+        }
+        break;
+
+      case 'c':
+        BufferSize--;
+        if (BufferSize == 0) {
+          return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+        }
+        Buffer[Index++] = (CHAR8)VA_ARG (Marker, UINTN);
+        break;
+
+      case 'v':
+        ASSERT (FALSE);   // %v is no longer supported
+        break;
+
+      case '%':
+        BufferSize--;
+        if (BufferSize == 0) {
+          return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+        }
+        Buffer[Index++] = *Format;
+        break;
+
+      default:
+        //
+        // if the type is unknown print it to the screen
+        //
+        BufferSize--;
+        if (BufferSize == 0) {
+          return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+        }
+        Buffer[Index++] = '%';
+
+        BufferSize--;
+        if (BufferSize == 0) {
+          return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+        }
+        Buffer[Index++] = *Format;
+        break;
+      }
+    }
+  }
+  if (BufferSize == 0) {
+    return IDS_DEBUG_PRINT_BUFFER_OVERFLOW;
+  }
+  //Mark the end of word
+  Buffer[Index] = 0;
+  *OutputStringLen = Index;
+  return IDS_DEBUG_PRINT_SUCCESS;
+}
+
+
+/**
+ *  Insert Overflow warning to the tail of output
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *
+**/
+STATIC VOID
+InsertOverflowWarningMessage (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize
+  )
+{
+  CHAR8 *Destination;
+  CHAR8 WarningString[] = "\n#BUFFER  OVERFLOW#\n";
+  AMD_CONFIG_PARAMS StdHeader;
+
+  Destination = Buffer + BufferSize - sizeof (WarningString);
+  LibAmdMemCopy (Destination, WarningString, sizeof (WarningString), &StdHeader);
+}
+
+/**
+ *  Process debug string
+ *
+ *  @param[in] Flag    - filter flag
+ *  @param[in] *Format - format string
+ *  @param[in] Marker  - Variable parameter
+ *
+**/
+STATIC VOID
+AmdIdsDebugPrintProcess (
+  IN      UINT64 Flag,
+  IN      CONST CHAR8 *Format,
+  IN      VA_LIST Marker
+  )
+{
+  UINT64 Filter;
+  CHAR8 LocalBuffer[MAX_LOCAL_BUFFER_SIZE];
+  UINTN OutPutStringLen;
+  IDS_DEBUG_PRINT **DebugPrintList;
+  IDS_DEBUG_PRINT_PRIVATE_DATA debugPrintPrivate;
+  UINT8 i;
+
+
+  GetDebugPrintList ((CONST IDS_DEBUG_PRINT ***)&DebugPrintList);
+  if (AmdIdsDebugPrintCheckSupportAll (DebugPrintList)) {
+    if (AmdIdsDebugPrintWorker (Format, Marker, &LocalBuffer[0], sizeof (LocalBuffer), &OutPutStringLen) == IDS_DEBUG_PRINT_BUFFER_OVERFLOW) {
+      InsertOverflowWarningMessage (&LocalBuffer[0], sizeof (LocalBuffer));
+      OutPutStringLen = sizeof (LocalBuffer);
+    }
+
+    //init input
+    debugPrintPrivate.saveContext = FALSE;
+
+    for (i = 0; DebugPrintList[i] != NULL; i++) {
+      if (DebugPrintList[i]->support ()) {
+        Filter = IDS_DEBUG_PRINT_MASK;
+        //Get Customize filter (Option)
+        DebugPrintList[i]->customfilter (&Filter);
+        if (Flag & Filter) {
+          //Init Private Date (Option)
+          DebugPrintList[i]->InitPrivateData (Flag, &debugPrintPrivate);
+          //Print Physical Layer
+          DebugPrintList[i]->print (&LocalBuffer[0], OutPutStringLen, &debugPrintPrivate);
+        }
+      }
+    }
+  }
+}
+
+/**
+ *  Prints string to debug host like printf in C
+ *
+ *  @param[in] Flag    - filter flag
+ *  @param[in] *Format - format string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsDebugPrint (
+  IN      UINT64 Flag,
+  IN      CONST CHAR8 *Format,
+  IN      ...
+  )
+{
+  VA_LIST Marker;
+  VA_START (Marker, Format); //init marker to 1st dynamic parameters.
+  AmdIdsDebugPrintProcess (Flag, Format, Marker);
+  VA_END (Marker);
+}
+
+/**
+ *  Prints memory debug strings
+ *
+ *  @param[in] *Format - format string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsDebugPrintMem (
+  IN      CHAR8 *Format,
+  IN      ...
+  )
+{
+  VA_LIST Marker;
+  VA_START (Marker, Format); //init marker to 1st dynamic parameters.
+  AmdIdsDebugPrintProcess (MEM_FLOW, Format, Marker);
+  VA_END (Marker);
+}
+
+/**
+ *  Prints CPU debug strings
+ *
+ *  @param[in] *Format - format string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsDebugPrintCpu (
+  IN      CHAR8 *Format,
+  IN      ...
+  )
+{
+  VA_LIST Marker;
+  VA_START (Marker, Format); //init marker to 1st dynamic parameters.
+  AmdIdsDebugPrintProcess (CPU_TRACE, Format, Marker);
+  VA_END (Marker);
+}
+
+
+/**
+ *  Prints HT debug strings
+ *
+ *  @param[in] *Format - format string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsDebugPrintHt (
+  IN      CHAR8 *Format,
+  IN      ...
+  )
+{
+  VA_LIST Marker;
+  VA_START (Marker, Format); //init marker to 1st dynamic parameters.
+  AmdIdsDebugPrintProcess (HT_TRACE, Format, Marker);
+  VA_END (Marker);
+}
+
+
+/**
+ *  Prints GNB debug strings
+ *
+ *  @param[in] *Format - format string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsDebugPrintGnb (
+  IN      CHAR8 *Format,
+  IN      ...
+  )
+{
+  VA_LIST Marker;
+  VA_START (Marker, Format); //init marker to 1st dynamic parameters.
+  AmdIdsDebugPrintProcess (GNB_TRACE, Format, Marker);
+  VA_END (Marker);
+}
+
+/**
+ *  Prints debug strings in any condition
+ *
+ *  @param[in] *Format - format string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsDebugPrintAll (
+  IN      CHAR8 *Format,
+  IN      ...
+  )
+{
+  VA_LIST Marker;
+  VA_START (Marker, Format); //init marker to 1st dynamic parameters.
+  AmdIdsDebugPrintProcess (TRACE_MASK_ALL, Format, Marker);
+  VA_END (Marker);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h
new file mode 100644
index 0000000000..5061426cd0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Print Routines
+ *
+ * Contains all functions related to IDS Debug Print
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_DEBUGPRINT_H_
+#define _IDS_DEBUGPRINT_H_
+
+/// return status for debug print
+typedef enum {
+  IDS_DEBUG_PRINT_SUCCESS = 0,      ///< success
+  IDS_DEBUG_PRINT_BUFFER_OVERFLOW,      ///< Bufer overflow
+} IDS_DEBUG_PRINT_STATUS;
+
+/// Private datas for debug print
+typedef struct _IDS_DEBUG_PRINT_PRIVATE_DATA {
+  BOOLEAN saveContext;      /// save context
+} IDS_DEBUG_PRINT_PRIVATE_DATA;
+
+typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_SUPPORT) (VOID);
+typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_FILTER) (UINT64 *Filter);
+typedef VOID (*PF_IDS_DEBUG_PRINT_PRINT) (CHAR8 *Buffer, UINTN BufferSize, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate);
+typedef VOID (*PF_IDS_DEBUG_INIT_PRIVATE_DATA) (UINT64 flag, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate);
+
+/// Debug print Hw layer service class
+typedef struct _IDS_DEBUG_PRINT {
+  PF_IDS_DEBUG_PRINT_SUPPORT  support;    ///Check if support
+  PF_IDS_DEBUG_PRINT_FILTER  customfilter;  ///Get if any customize filters
+  PF_IDS_DEBUG_INIT_PRIVATE_DATA  InitPrivateData; ///Init private data
+  PF_IDS_DEBUG_PRINT_PRINT  print;  ///Print data to Hw layer
+} IDS_DEBUG_PRINT;
+
+
+VOID
+GetDebugPrintList (
+  IN OUT   CONST IDS_DEBUG_PRINT   ***pIdsDebugPrintListPtr
+  );
+
+
+#endif //_IDS_DEBUGPRINT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c
new file mode 100644
index 0000000000..bb180cefb9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c
@@ -0,0 +1,778 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains all functions related to HDTOUT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63688 $   @e \$Date: 2012-01-03 21:18:53 -0600 (Tue, 03 Jan 2012) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "AMD.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "IdsDebugPrint.h"
+#include "IdsDpHdtout.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE
+
+/**
+ *  Check if String contain the substring
+ *
+ *  @param[in] String  Pointer of string.
+ *  @param[in] Substr  Pointer of sub string.
+ *
+ *  @retval TRUE S2 is substring of S1
+ *  @retval FALSE S2 isn't substring of S1
+ *
+**/
+BOOLEAN
+AmdIdsSubStr (
+  IN      CHAR8 *String,
+  IN      CHAR8 *Substr
+  )
+{
+  UINT16 i;
+  UINT16 j;
+
+  for (i = 0; String[i] != 0 ; i++) {
+    for (j = 0; (Substr[j] != 0) && (Substr[j] == String[i + j]); j++) {
+    }
+    if (Substr[j] == 0) {
+      return TRUE;
+    }
+  }
+
+  return FALSE;
+}
+
+/**
+ *  Determine whether IDS console is enabled.
+ *
+ *  @param[in,out] pHdtoutHeader    Address of hdtout header pointer
+ *  @param[in,out] StdHeader        The Pointer of AGESA Header
+ *
+ *  @retval       TRUE       pHdtoutHeader Non zero
+ *  @retval       FALSE   pHdtoutHeader is NULL
+ *
+ **/
+BOOLEAN
+AmdIdsHdtoutGetHeader (
+  IN OUT   HDTOUT_HEADER **pHdtoutHeaderPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Dr3Reg;
+  HDTOUT_HEADER *HdtoutHeaderPtr;
+  LibAmdReadCpuReg (DR3_REG, &Dr3Reg);
+  HdtoutHeaderPtr = (HDTOUT_HEADER *) (UINTN) Dr3Reg;
+  if ((HdtoutHeaderPtr != NULL) && (HdtoutHeaderPtr->Signature == HDTOUT_HEADER_SIGNATURE)) {
+    *pHdtoutHeaderPtr = HdtoutHeaderPtr;
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+/**
+ *  Determine whether IDS console is enabled.
+ *
+ *  @param[in,out] IdsConsole    The Pointer of Ids console data
+ *
+ *  @retval       TRUE    Ids console is enabled.
+ *  @retval       FALSE   Ids console is disabled.
+ *
+ **/
+BOOLEAN
+AmdIdsHdtOutSupport (
+  VOID
+  )
+{
+  BOOLEAN Result;
+  UINT32  DR2reg;
+
+  Result = FALSE;
+
+  LibAmdReadCpuReg (DR2_REG, &DR2reg);
+  if (DR2reg == 0x99CC) {
+    Result = TRUE;
+  }
+
+  return Result;
+}
+
+/**
+ *  Get HDTOUT customize Filter
+ *
+ *  @param[in,out] Filter    Filter do be filled
+ *
+ *  @retval       TRUE    Alway return true, for HDTOUT has its own filter mechanism
+ *
+ **/
+BOOLEAN
+AmdIdsHdtOutGetFilter (
+  IN OUT   UINT64 *Filter
+  )
+{
+  HDTOUT_HEADER *HdtoutHeaderPtr;
+
+  if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, NULL) == TRUE) {
+    *Filter = HdtoutHeaderPtr->ConsoleFilter;
+  }
+  return TRUE;
+}
+
+/**
+ *
+ *  Initial register setting used for HDT out Function.
+ *
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutRegisterRestore (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 CR4reg;
+  UINT64 SMsr;
+
+  SMsr &= ~BIT0;
+
+  LibAmdWriteCpuReg (DR2_REG, 0);
+  LibAmdWriteCpuReg (DR3_REG, 0);
+  LibAmdWriteCpuReg (DR7_REG, 0);
+
+  LibAmdReadCpuReg (CR4_REG, &CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, CR4reg & (~BIT3));
+
+}
+
+/**
+ *
+ *  Restore register setting used for HDT out Function.
+ *
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutRegisterInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 CR4reg;
+  UINT64 SMsr;
+
+  SMsr |= 1;
+
+  LibAmdWriteCpuReg (DR2_REG, 0x99CC);
+
+  LibAmdWriteCpuReg (DR7_REG, 0x02000420);
+
+  LibAmdReadCpuReg (CR4_REG, &CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
+}
+
+/**
+ *
+ *  Initial function for HDT out Function.
+ *
+ *  Init required Debug register & heap, and will also fire a HDTOUT
+ *  Command to let hdtout script do corresponding things.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  HDTOUT_HEADER HdtoutHeader;
+  UINT8  Persist;
+  AGESA_STATUS IgnoreSts;
+  HDTOUT_HEADER *pHdtoutHeader;
+
+  IDS_FUNCLIST_EXTERN ();
+  if (AmdIdsHdtOutSupport ()) {
+    AmdIdsHdtOutRegisterInit (StdHeader);
+    // Initialize HDTOUT Header
+    HdtoutHeader.Signature = HDTOUT_HEADER_SIGNATURE;
+    HdtoutHeader.Version = HDTOUT_VERSION;
+    HdtoutHeader.BufferSize = HDTOUT_DEFAULT_BUFFER_SIZE;
+    HdtoutHeader.DataIndex = 0;
+    HdtoutHeader.PrintCtrl = HDTOUT_PRINTCTRL_ON;
+    HdtoutHeader.NumBreakpointUnit = 0;
+    HdtoutHeader.FuncListAddr = (UINT32) (UINT64) IDS_FUNCLIST_ADDR;
+    HdtoutHeader.StatusStr[0] = 0;
+    HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON;
+    HdtoutHeader.EnableMask = 0;
+    HdtoutHeader.ConsoleFilter = IDS_DEBUG_PRINT_MASK;
+
+    // Trigger HDTOUT breakpoint to get inputs from script
+    IdsOutPort (HDTOUT_INIT, (UINT32) (UINT64) &HdtoutHeader, 0);
+    // Disable AP HDTOUT if set BspOnlyFlag
+    if (HdtoutHeader.BspOnlyFlag == HDTOUT_BSP_ONLY) {
+      if (!IsBsp (StdHeader, &IgnoreSts)) {
+        AmdIdsHdtOutRegisterRestore (StdHeader);
+        return;
+      }
+    }
+    // Convert legacy EnableMask to new ConsoleFilter
+    HdtoutHeader.ConsoleFilter |= HdtoutHeader.EnableMask;
+
+    // Disable the buffer if the size is not large enough
+    if (HdtoutHeader.BufferSize < 128) {
+      HdtoutHeader.BufferSize = 0;
+      HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_OFF;
+    } else {
+      HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON;
+    }
+
+    // Check if Hdtout header have been initialed, if so it must 2nd time come here
+    if (AmdIdsHdtoutGetHeader (&pHdtoutHeader, StdHeader)) {
+      Persist = HEAP_SYSTEM_MEM;
+    } else {
+      Persist = HEAP_LOCAL_CACHE;
+    }
+
+    // Allocate heap
+    do {
+      AllocHeapParams.RequestedBufferSize = HdtoutHeader.BufferSize + sizeof (HdtoutHeader) - 2;
+      AllocHeapParams.BufferHandle = IDS_HDT_OUT_BUFFER_HANDLE;
+      AllocHeapParams.Persist = Persist;
+      if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+        break;
+      } else {
+        IdsOutPort (HDTOUT_ERROR, HDTOUT_ERROR_HEAP_ALLOCATION, AllocHeapParams.RequestedBufferSize);
+        HdtoutHeader.BufferSize -= 256;
+      }
+    } while ((HdtoutHeader.BufferSize & 0x8000) == 0);
+    // If the buffer have been successfully allocated?
+    if ((HdtoutHeader.BufferSize & 0x8000) == 0) {
+      LibAmdWriteCpuReg (DR3_REG, (UINT32) (UINT64) AllocHeapParams.BufferPtr);
+      LibAmdMemCopy (AllocHeapParams.BufferPtr, &HdtoutHeader, sizeof (HdtoutHeader) - 2, StdHeader);
+    } else {
+      /// Clear DR3_REG
+      IdsOutPort (HDTOUT_ERROR, HDTOUT_ERROR_HEAP_AllOCATE_FAIL, IDS_DEBUG_PRINT_MASK);
+      LibAmdWriteCpuReg (DR3_REG, 0);
+    }
+  }
+}
+
+/**
+ *
+ *  Flush all HDTOUT buffer data before HOB transfer
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutBufferFlush (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  HDTOUT_HEADER *HdtoutHeaderPtr ;
+
+  if (AmdIdsHdtOutSupport ()) {
+    if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) {
+      if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) &&
+          (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) {
+        IdsOutPort (HDTOUT_PRINT, (UINT32) (UINT64) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex);
+        HdtoutHeaderPtr->DataIndex = 0;
+      }
+    }
+  }
+}
+
+/**
+ *  Exit function for HDT out Function for each cores
+ *
+ *  @param[in] Ignored  no used
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+AmdIdsHdtOutExitCoreTask (
+  IN       VOID  *Ignored,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  HDTOUT_HEADER *HdtoutHeaderPtr;
+
+  if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) {
+    if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) &&
+        (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) {
+      IdsOutPort (HDTOUT_PRINT, (UINT32) (UINT64) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex);
+    }
+  }
+  IdsOutPort (HDTOUT_EXIT, (UINT32) (UINT64) HdtoutHeaderPtr, 0);
+
+  AmdIdsHdtOutRegisterRestore (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/**
+ *
+ *  Exit function for HDT out Function.
+ *
+ *  Restore debug register and Deallocate heap, and will also fire a HDTOUT
+ *  Command to let hdtout script do corresponding things.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDSAPLATETASK IdsApLateTask;
+  if (AmdIdsHdtOutSupport ()) {
+    IdsApLateTask.ApTask = (PF_IDS_AP_TASK) AmdIdsHdtOutExitCoreTask;
+    IdsApLateTask.ApTaskPara = NULL;
+    IdsAgesaRunFcnOnAllCoresLate (&IdsApLateTask, StdHeader);
+    HeapDeallocateBuffer (IDS_HDT_OUT_BUFFER_HANDLE, StdHeader);
+  }
+}
+
+/**
+ *
+ *  Exit function for HDT out Function of S3 Resume
+ *
+ *  Restore debug register and Deallocate heap, and will also fire a HDTOUT
+ *  Command to let hdtout script do corresponding things.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutS3Exit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS AgesaStatus;
+
+  if (AmdIdsHdtOutSupport ()) {
+    //Ap debug print exit have been done at the end of AmdInitResume, so we only BSP at here
+    AmdIdsHdtOutExitCoreTask (NULL, StdHeader);
+    if (IsBsp (StdHeader, &AgesaStatus)) {
+      HeapDeallocateBuffer (IDS_HDT_OUT_BUFFER_HANDLE, StdHeader);
+    }
+  }
+}
+/**
+ *
+ *  Exit function for HDT out Function of S3 Resume
+ *
+ *  Restore debug register and Deallocate heap, and will also fire a HDTOUT
+ *  Command to let hdtout script do corresponding things.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsHdtOutS3ApExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_TASK TaskPtr;
+  UINT32  Ignored;
+  UINT32  BscSocket;
+  UINT32  BscCoreNum;
+  UINT32  Core;
+  UINT32  Socket;
+  UINT32  NumberOfSockets;
+  UINT32  NumberOfCores;
+  AGESA_STATUS IgnoredSts;
+
+  if (AmdIdsHdtOutSupport ()) {
+    // run code on all APs except BSP
+    TaskPtr.FuncAddress.PfApTaskI = (PF_AP_TASK_I)AmdIdsHdtOutExitCoreTask;
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.DataTransfer.DataPtr = NULL;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+    NumberOfSockets = GetPlatformNumberOfSockets ();
+    IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+          for (Core = 0; Core < NumberOfCores; Core++) {
+            if ((Socket != BscSocket) || (Core != BscCoreNum)) {
+              ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/**
+ *  Print formated string with accerate buffer
+ *  Flow out only when buffer will full
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[in] HdtoutHeaderPtr  - Point to Hdtout Header
+ *
+**/
+VOID
+AmdIdsHdtOutPrintWithBuffer (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize,
+  IN      HDTOUT_HEADER *HdtoutHeaderPtr
+  )
+{
+  if ((HdtoutHeaderPtr == NULL) || (Buffer == NULL)) {
+    ASSERT (FALSE);
+    return;
+  }
+
+  while (BufferSize--) {
+    if (HdtoutHeaderPtr->DataIndex >= HdtoutHeaderPtr->BufferSize) {
+      //Flow out current buffer, and clear the index
+      IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) &HdtoutHeaderPtr->Data[0], HdtoutHeaderPtr->BufferSize);
+      HdtoutHeaderPtr->DataIndex = 0;
+    }
+    HdtoutHeaderPtr->Data[HdtoutHeaderPtr->DataIndex++] = *(Buffer++);
+  }
+}
+/**
+ *  Save HDTOUT context, use for break point function
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[in] HdtoutHeaderPtr  - Point to Hdtout Header
+ *
+**/
+VOID
+AmdIdsHdtOutSaveContext (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize,
+  IN      HDTOUT_HEADER *HdtoutHeaderPtr
+  )
+{
+  UINTN i;
+  UINTN j;
+  UINTN ArrayIndex;
+  UINTN unusedPrefix;
+  UINTN ArrayLength;
+  BOOLEAN SaveStatus;
+
+  ArrayLength = 0;
+
+  // Look for the start of the first ASCII
+  for (i = 0; i < BufferSize - 1; i++) {
+    if ((Buffer[i] > 32) && (Buffer[i] < 127)) {
+      break;
+    }
+  }
+
+  unusedPrefix = i;
+  //ASSERT if no "\n" in status string
+  ASSERT (AmdIdsSubStr (&Buffer[i], "\n"));
+
+  if (i < (BufferSize - 1)) {
+    // Match the first word in StatusStr
+    SaveStatus = FALSE;
+    for (j = 0; !SaveStatus && (HdtoutHeaderPtr->StatusStr[j] != 0); j++) {
+      for (; (Buffer[i] == HdtoutHeaderPtr->StatusStr[j]) && (i < BufferSize); i++, j++) {
+        ArrayLength++;
+        if (Buffer[i] == ' ') {
+          ArrayIndex = j;
+          for (; HdtoutHeaderPtr->StatusStr[j] != '\n'; j++) {
+            ArrayLength++;
+          }
+          // Remove old entry if it's size does not fit
+          if (ArrayLength != ((UINT32) BufferSize - unusedPrefix)) {
+            for (++j; HdtoutHeaderPtr->StatusStr[j] != 0; j++) {
+              HdtoutHeaderPtr->StatusStr[j - ArrayLength] = HdtoutHeaderPtr->StatusStr[j];
+            }
+            j = j - ArrayLength - 1;
+            i = unusedPrefix;
+            // Mark the end of string
+            HdtoutHeaderPtr->StatusStr[j + BufferSize - unusedPrefix + 1] = 0;
+          } else {
+            j = ArrayIndex - 1;
+          }
+
+          // Word match, exit for saving
+          SaveStatus = TRUE;
+          break;
+        }
+      }
+    }
+
+    // Copy string to StatusStr
+    if ((HdtoutHeaderPtr->StatusStr[j] == 0) || SaveStatus) {
+      for (; i < BufferSize; j++, i++) {
+        HdtoutHeaderPtr->StatusStr[j] = Buffer[i];
+      }
+    }
+
+    if (!SaveStatus) {
+      // Mark the end of string if not done so
+      HdtoutHeaderPtr->StatusStr[j] = 0;
+    }
+  }
+}
+
+BOOLEAN
+AmdIdsHdtOutBreakPointUnit (
+  IN OUT   BREAKPOINT_UNIT **pBpunitptr,
+  IN OUT   UINT32 *numBp,
+  IN       HDTOUT_HEADER *HdtoutHeaderPtr,
+  IN       CHAR8   *Buffer
+  )
+{
+  BOOLEAN isMatched;
+  CHAR8 *PCmpStr;
+  CHAR8 *Pbpstr;
+  BREAKPOINT_UNIT *pBpunit;
+
+  pBpunit = *pBpunitptr;
+  if ((pBpunit == NULL) ||
+      (numBp == NULL) ||
+      (HdtoutHeaderPtr == NULL) ||
+      (*numBp == 0)) {
+    ASSERT (FALSE);
+    return FALSE;
+  }
+  //Get to be compared string
+  if (pBpunit->BpFlag == IDS_HDTOUT_BPFLAG_FORMAT_STR) {
+    PCmpStr = Buffer;
+  } else {
+    PCmpStr = HdtoutHeaderPtr->StatusStr;
+  }
+  //Get BreakPoint string
+  Pbpstr = HdtoutHeaderPtr->BreakpointList + pBpunit->BpStrOffset;
+  isMatched = AmdIdsSubStr (PCmpStr, Pbpstr);
+  //Point to next one, and decrease the numbp
+  *pBpunitptr = ++pBpunit;
+  (*numBp)--;
+  return isMatched;
+}
+/**
+ *  Process HDTOUT breakpoint
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[in] HdtoutHeaderPtr  - Point to Hdtout Header
+ *
+**/
+VOID
+AmdIdsHdtOutBreakPoint (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize,
+  IN      HDTOUT_HEADER *HdtoutHeaderPtr
+  )
+{
+  UINT32 numBp;
+  BREAKPOINT_UNIT *Pbpunit;
+  BOOLEAN isMatched;
+  UINT32 i;
+  Pbpunit = (BREAKPOINT_UNIT *) &HdtoutHeaderPtr->BreakpointList[0];
+  numBp = HdtoutHeaderPtr->NumBreakpointUnit;
+
+  for (;;) {
+    if (Pbpunit->AndFlag == IDS_HDTOUT_BP_AND_ON) {
+      isMatched = TRUE;
+      do {
+        isMatched &= AmdIdsHdtOutBreakPointUnit (&Pbpunit, &numBp, HdtoutHeaderPtr, Buffer);
+      } while ((Pbpunit->AndFlag == IDS_HDTOUT_BP_AND_ON) &&
+               (isMatched == TRUE) &&
+               (numBp > 0));
+      //Next one is IDS_HDTOUT_BP_AND_OFF
+      if (numBp > 0) {
+        if (isMatched == TRUE) {
+          isMatched &= AmdIdsHdtOutBreakPointUnit (&Pbpunit, &numBp, HdtoutHeaderPtr, Buffer);
+        } else {
+          Pbpunit++;
+          numBp--;
+        }
+      }
+    } else {
+      isMatched = AmdIdsHdtOutBreakPointUnit (&Pbpunit, &numBp, HdtoutHeaderPtr, Buffer);
+    }
+    if ((isMatched == TRUE) || (numBp == 0)) {
+      break;
+    }
+  }
+  //Do action
+  if (isMatched) {
+//    AmdIdsSerialPrint (Buffer, BufferSize, NULL);
+    Pbpunit--;
+    switch (Pbpunit->Action) {
+    case HDTOUT_BP_ACTION_HALT:
+      i = (UINT32) (Pbpunit - ((BREAKPOINT_UNIT *) &HdtoutHeaderPtr->BreakpointList[0]));
+      IdsOutPort (HDTOUT_BREAKPOINT, (UINT32) (UINTN) Buffer, ( i << 16) | (UINT32) BufferSize);
+      break;
+    case HDTOUT_BP_ACTION_PRINTON:
+      if (HdtoutHeaderPtr->PrintCtrl != 1) {
+        HdtoutHeaderPtr->PrintCtrl = 1;
+        if (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON) {
+          AmdIdsHdtOutPrintWithBuffer (Buffer, BufferSize, HdtoutHeaderPtr);
+        } else {
+          IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32) BufferSize);
+        }
+      }
+      break;
+    case HDTOUT_BP_ACTION_PRINTOFF:
+      if (HdtoutHeaderPtr->PrintCtrl != 0) {
+        HdtoutHeaderPtr->PrintCtrl = 0;
+        IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32)BufferSize);
+      }
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+  }
+}
+
+
+/**
+ *  Print formated string to HDTOUT
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[in] debugPrintPrivate  - Option
+ *
+**/
+VOID
+AmdIdsHdtOutPrint (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize,
+  IN      IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate
+  )
+{
+  HDTOUT_HEADER *HdtoutHeaderPtr;
+  if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, NULL)) {
+    //Print Function
+    if (HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) {
+      if (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON) {
+        AmdIdsHdtOutPrintWithBuffer (Buffer, BufferSize, HdtoutHeaderPtr);
+      } else {
+        IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32) BufferSize);
+      }
+    }
+    //Check BreakPoint
+    if (HdtoutHeaderPtr->NumBreakpointUnit) {
+      AmdIdsHdtOutBreakPoint (Buffer, BufferSize, HdtoutHeaderPtr);
+      if (debugPrintPrivate->saveContext) {
+        AmdIdsHdtOutSaveContext (Buffer, BufferSize, HdtoutHeaderPtr);
+        debugPrintPrivate->saveContext = FALSE;
+      }
+    }
+  } else {
+    //No HDTOUT header found print directly without buffer
+    IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32) BufferSize);
+  }
+}
+
+/**
+ *  Init local private data for HDTOUT
+ *
+ *  @param[in] Flag    - filter flag
+ *  @param[in] debugPrintPrivate  - Point to debugPrintPrivate
+ *
+**/
+VOID
+AmdIdsHdtOutInitPrivateData (
+  IN      UINT64 Flag,
+  IN      IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate
+  )
+{
+  if (Flag == MEM_STATUS) {
+    debugPrintPrivate->saveContext = TRUE;
+  }
+}
+
+CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintHdtoutInstance =
+{
+  AmdIdsHdtOutSupport,
+  AmdIdsHdtOutGetFilter,
+  AmdIdsHdtOutInitPrivateData,
+  AmdIdsHdtOutPrint
+};
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h
new file mode 100644
index 0000000000..bb4cc1df87
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h
@@ -0,0 +1,146 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains all functions related to HDTOUT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_HDTOUT_H_
+#define _IDS_HDTOUT_H_
+
+#define HDTOUT_VERSION          0x0200
+
+/// HDTOUT command
+#define HDTOUT_COMMAND        0x99cc
+#define HDTOUT_INIT           (0x10BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_ASSERT         (0xA0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_EXIT           (0xE0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_PRINT          (0xC0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_TIME_ANALYSE   (0xD0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_BREAKPOINT     (0xB0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_ERROR          (0x1EBF0000ul | HDTOUT_COMMAND)
+
+
+#define HDTOUT_ERROR_HEAP_ALLOCATION       0x1
+#define HDTOUT_ERROR_HEAP_AllOCATE_FAIL       0x2
+
+#define HDTOUT_PRINTCTRL_OFF      0
+#define HDTOUT_PRINTCTRL_ON       1
+#define HDTOUT_ALL_CORES          0
+#define HDTOUT_BSP_ONLY           1
+#define HDTOUT_BUFFER_MODE_OFF    0
+#define HDTOUT_BUFFER_MODE_ON     1
+
+#define HDTOUT_HEADER_SIGNATURE     0xDB1099CCul
+#define HDTOUT_DEFAULT_BUFFER_SIZE  0x1000
+/// HDTOUT Header.
+typedef struct _HDTOUT_HEADER {
+  UINT32 Signature;               ///< 0xDB1099CC
+  UINT16 Version;                 ///< HDTOUT version.
+  UINT16 BufferSize;              ///< Size in bytes.
+  UINT16 DataIndex;               ///< Data Index.
+  UINT8  PrintCtrl;               ///< 0 off no print  1 on print
+  UINT8  NumBreakpointUnit;       ///< default 0 no bp unit others number of bp unit
+  UINT32 FuncListAddr;            ///< 32 bit address to the list of functions that script can execute
+  UINT8  ConsoleType;             ///< Console type - deprecated
+  UINT8  Event;                   ///< Event type. - deprecated
+  UINT8  OutBufferMode;           ///< Off:stack mode, On: heap mode - deprecated
+  UINT32 EnableMask;              ///< Bitmap to select which part should be streamed out
+  UINT64 ConsoleFilter;           ///< Filter use to select which part should be streamed out
+  UINT8  BspOnlyFlag;             ///< 1 Only Enable Bsp output, 0 enable On All cores
+  UINT8  Reserved[56 - 32];       ///< Reserved for header expansion
+
+  CHAR8  BreakpointList[300];     ///< Breakpoint list
+  CHAR8  StatusStr[156];          ///< Shows current node, DCT, CS,...
+  CHAR8  Data[2];                 ///< HDTOUT content. Its size will be determined by BufferSize.
+} HDTOUT_HEADER;
+
+#define IDS_HDTOUT_BP_AND_OFF             0
+#define IDS_HDTOUT_BP_AND_ON              1
+
+#define IDS_HDTOUT_BPFLAG_FORMAT_STR   0
+#define IDS_HDTOUT_BPFLAG_STATUS_STR   1
+
+#define HDTOUT_BP_ACTION_HALT          1
+#define HDTOUT_BP_ACTION_PRINTON       2
+#define HDTOUT_BP_ACTION_PRINTONE      3
+#define HDTOUT_BP_ACTION_PRINTOFF      4
+
+///breakpoint unit of HDTOUT
+typedef struct _BREAKPOINT_UNIT {
+  UINT8 AndFlag : 1;        ///< Next string is ANDed to current string
+  UINT8 BpFlag : 1;         ///< Format string or Status string
+  UINT8 Action : 4;         ///< Halt, start HDTOUT, or stop HDT,...
+  UINT8 BpStrOffset;        ///< Offset from BreakpointList to the breakpoint string
+} BREAKPOINT_UNIT;
+
+
+BOOLEAN
+AmdIdsHdtOutSupport (
+  VOID
+  );
+
+#endif //_IDS_HDTOUT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c
new file mode 100644
index 0000000000..fbcf1b749d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c
@@ -0,0 +1,172 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains all functions related to Redirect IO
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "AMD.h"
+#include "IdsDebugPrint.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE
+
+/**
+ *  Determine whether IDS console is enabled.
+ *
+ *
+ *  @retval       TRUE    Alway return true
+ *
+ **/
+BOOLEAN
+AmdIdsRedirectIoSupport (
+  VOID
+  )
+{
+
+  return TRUE;
+}
+
+/**
+ *  Get customize Filter
+ *
+ *  @param[in,out] Filter    Filter do be filled
+ *
+ *  @retval       FALSE    Alway return FALSE
+ *
+ **/
+BOOLEAN
+AmdIdsRedirectIoGetFilter (
+  IN OUT   UINT64 *Filter
+  )
+{
+  return FALSE;
+}
+
+#define REDIRECT_IO_DATA_BEGIN 0x5f535452ul
+#define REDIRECT_IO_DATA_END   0x5f454e44ul
+
+/**
+ *  Print formated string with redirect IO
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[in] debugPrintPrivate  - Option
+ *
+**/
+VOID
+AmdIdsRedirectIoPrint (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize,
+  IN      IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate
+  )
+{
+  UINT32 Value;
+
+  Value = REDIRECT_IO_DATA_BEGIN;
+  LibAmdIoWrite (AccessWidth32, IDS_DEBUG_PRINT_IO_PORT, &Value, NULL);
+
+  while (BufferSize--) {
+    LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PRINT_IO_PORT, Buffer++, NULL);
+  }
+
+  Value = REDIRECT_IO_DATA_END;
+  LibAmdIoWrite (AccessWidth32, IDS_DEBUG_PRINT_IO_PORT, &Value, NULL);
+}
+
+/**
+ *  Init local private data
+ *
+ *  @param[in] Flag    - filter flag
+ *  @param[in] debugPrintPrivate  - Point to debugPrintPrivate
+ *
+**/
+VOID
+AmdIdsRedirectIoInitPrivateData (
+  IN      UINT64 Flag,
+  IN      IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate
+  )
+{
+
+}
+
+CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintRedirectIoInstance =
+{
+  AmdIdsRedirectIoSupport,
+  AmdIdsRedirectIoGetFilter,
+  AmdIdsRedirectIoInitPrivateData,
+  AmdIdsRedirectIoPrint
+};
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c
new file mode 100644
index 0000000000..749c02a652
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c
@@ -0,0 +1,211 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains all functions related to HDTOUT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "AMD.h"
+#include "IdsDebugPrint.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE
+
+/**
+ *  Determine whether IDS console is enabled.
+ *
+ *
+ *  @retval       TRUE    Alway return true
+ *
+ **/
+STATIC BOOLEAN
+AmdIdsSerialSupport (
+  VOID
+  )
+{
+
+  return TRUE;
+}
+
+/**
+ *  Get Serial customize Filter
+ *
+ *  @param[in,out] Filter    Filter do be filled
+ *
+ *  @retval       FALSE    Alway return FALSE
+ *
+ **/
+STATIC BOOLEAN
+AmdIdsSerialGetFilter (
+  IN OUT   UINT64 *Filter
+  )
+{
+  return FALSE;
+}
+
+
+#define IDS_SERIAL_PORT_LSR (IDS_SERIAL_PORT + 5)
+#define IDS_LSR_TRANSMIT_HOLDING_REGISTER_EMPTY_MASK BIT5
+/**
+ *  Send byte to  Serial Port
+ *
+ *  Before use this routine, please make sure Serial Communications Chip have been initialed
+ *
+ *  @param[in] ByteSended   Byte to be sended
+ *
+ *  @retval       TRUE    Byte sended successfully
+ *  @retval       FALSE   Byte sended failed
+ *
+ **/
+STATIC BOOLEAN
+AmdIdsSerialSendByte (
+  IN      CHAR8   ByteSended
+  )
+{
+  UINT32 RetryCount;
+  UINT8 Value;
+
+  //Wait until LSR.Bit5 (Transmitter holding register Empty)
+  RetryCount = 200;
+  do {
+    LibAmdIoRead (AccessWidth8, IDS_SERIAL_PORT_LSR, &Value, NULL);
+    RetryCount--;
+  } while (((Value & IDS_LSR_TRANSMIT_HOLDING_REGISTER_EMPTY_MASK) == 0) &&
+           (RetryCount > 0));
+
+  if (RetryCount == 0) {
+    //Time expired
+    return FALSE;
+  } else {
+    LibAmdIoWrite (AccessWidth8, IDS_SERIAL_PORT, &ByteSended, NULL);
+    return TRUE;
+  }
+}
+
+
+/**
+ *  Print formated string
+ *
+ *  @param[in] Buffer  - Point to input buffer
+ *  @param[in] BufferSize  - Buffer size
+ *  @param[in] debugPrintPrivate  - Option
+ *
+**/
+STATIC VOID
+AmdIdsSerialPrint (
+  IN      CHAR8   *Buffer,
+  IN      UINTN BufferSize,
+  IN      IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate
+  )
+{
+  BOOLEAN SendStatus;
+  UINT32 RetryCount;
+  RetryCount = 200;
+  while (BufferSize--) {
+    do {
+      if (*Buffer == '\n') {
+        SendStatus = AmdIdsSerialSendByte ('\r');
+      }
+      SendStatus = AmdIdsSerialSendByte (*Buffer);
+      RetryCount--;
+    } while ((SendStatus == FALSE) && (RetryCount > 0));
+    Buffer ++;
+  }
+}
+
+/**
+ *  Init local private data
+ *
+ *  @param[in] Flag    - filter flag
+ *  @param[in] debugPrintPrivate  - Point to debugPrintPrivate
+ *
+**/
+STATIC VOID
+AmdIdsSerialInitPrivateData (
+  IN      UINT64 Flag,
+  IN      IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate
+  )
+{
+
+}
+
+CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintSerialInstance =
+{
+  AmdIdsSerialSupport,
+  AmdIdsSerialGetFilter,
+  AmdIdsSerialInitPrivateData,
+  AmdIdsSerialPrint
+};
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c
new file mode 100644
index 0000000000..f7e6a560eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c
@@ -0,0 +1,329 @@
+/**
+ * @file
+ *
+ * Adding IDT table for debugging exception
+ *
+ * Contains IDT related function
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "AMD.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ IDS_STATUS
+STATIC
+IdsReplaceIdtr (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+STATIC
+IdsRestoreIdtr (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+STATIC
+IdsUpdateExceptionVector (
+  IN       VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern UINT64 IdsExceptionHandler;
+extern UINT32 SizeIdtDescriptor;
+extern UINT32 SizeTotalIdtDescriptors;
+
+/**
+ * IDS IDT table.
+ *
+ * This is the top level interface for IDS IDT table function.
+ * Adding a 'jmp $' into every exception handler.
+ * So debugger could use HDT to skip 'jmp $' and execute the iret,
+ * then they could find which instruction cause the exception.
+ *
+ * @param[in]     IdsIdtFuncId IDT indicator value, see @ref IDS_IDT_FUNC_ID
+ * @param[in]     DataPtr      Points to data that may used by IdsIdtTable routine
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+IdsExceptionTrap (
+  IN       IDS_IDT_FUNC_ID IdsIdtFuncId,
+  IN       VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_STATUS   ReturnFlag;
+  AGESA_STATUS Ignored;
+
+  ReturnFlag = IDS_SUCCESS;
+  switch (IdsIdtFuncId) {
+  case IDS_IDT_REPLACE_IDTR_FOR_BSC:
+    if (IsBsp (StdHeader, &Ignored)) {
+      ReturnFlag = IdsReplaceIdtr (StdHeader);
+    }
+    break;
+  case IDS_IDT_RESTORE_IDTR_FOR_BSC:
+    if (IsBsp (StdHeader, &Ignored)) {
+      ReturnFlag = IdsRestoreIdtr (StdHeader);
+    }
+    break;
+  case IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP:
+    ReturnFlag = IdsUpdateExceptionVector (DataPtr, StdHeader);
+    break;
+  default:
+    return IDS_UNSUPPORTED;
+    break;
+  }
+  return ReturnFlag;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/**
+ * Replace IDTR of BSC.
+ *
+ * Save IDTR of BSC to heap and replace IDTR.
+ *
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+STATIC
+IdsReplaceIdtr (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocParams;
+  LOCATE_HEAP_PTR LocateHeap;
+  IDT_BASE_LIMIT IdtInfo;
+
+  // Save IDTR to Heap
+  AllocParams.BufferHandle = IDS_SAVE_IDTR_HANDLE;
+  AllocParams.RequestedBufferSize = sizeof (IDT_BASE_LIMIT);
+  AllocParams.Persist = HEAP_TEMP_MEM;
+  if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
+    return IDS_UNSUPPORTED;
+  }
+  GetIdtr ((IDT_BASE_LIMIT *) AllocParams.BufferPtr, StdHeader);
+
+  // Check if host env has their own IDT
+  if (((IDT_BASE_LIMIT *) AllocParams.BufferPtr)->Base == 0) {
+    // Load AGESA's IDT
+    LocateHeap.BufferHandle = IDS_BSC_IDT_HANDLE;
+    // Check if we already allocated heap for creating IDT
+    if (HeapLocateBuffer (&LocateHeap, StdHeader) != AGESA_SUCCESS) {
+      // Create IDT for BSC in heap
+      AllocParams.BufferHandle = IDS_BSC_IDT_HANDLE;
+      AllocParams.RequestedBufferSize = sizeof (IDT_DESCRIPTOR) * 32;
+      AllocParams.Persist = HEAP_SYSTEM_MEM;
+      if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
+        return IDS_UNSUPPORTED;
+      }
+      IdtInfo.Base = (UINT64) AllocParams.BufferPtr;
+    } else {
+      IdtInfo.Base = (UINT64) LocateHeap.BufferPtr;
+    }
+    IdsUpdateExceptionVector ((VOID *) &IdtInfo,  StdHeader);
+    SetIdtr (&IdtInfo, StdHeader);
+  } else {
+    return IDS_UNSUPPORTED;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ * Restore IDTR of BSC.
+ *
+ * Restore IDTR of BSC from heap.
+ *
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+STATIC
+IdsRestoreIdtr (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateHeap;
+  IDT_BASE_LIMIT IdtInfo;
+
+  IdtInfo.Base = 0;
+  IdtInfo.Limit = 0;
+  GetIdtr (&IdtInfo, StdHeader);
+
+  LocateHeap.BufferHandle = IDS_BSC_IDT_HANDLE;
+  if (HeapLocateBuffer (&LocateHeap, StdHeader) != AGESA_SUCCESS) {
+    // If AGESA loaded its own IDT, there must be a buffer with handle IDS_BSC_IDT_HANDLE in heap
+    return IDS_UNSUPPORTED;
+  }
+  // If current IDTR.Base != address of AGESA's own IDT, it is possibile that Host env load their own IDT
+  if (IdtInfo.Base != ((UINT64) (LocateHeap.BufferPtr))) {
+    return IDS_UNSUPPORTED;
+  } else {
+    LocateHeap.BufferHandle = IDS_SAVE_IDTR_HANDLE;
+    if (HeapLocateBuffer (&LocateHeap, StdHeader) != AGESA_SUCCESS) {
+      return IDS_UNSUPPORTED;
+    }
+    SetIdtr ((IDT_BASE_LIMIT *) LocateHeap.BufferPtr, StdHeader);
+    HeapDeallocateBuffer (IDS_SAVE_IDTR_HANDLE, StdHeader);
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ * Update exception vector.
+ *
+ *  Adding a 'jmp $' into every exception handler.
+ *  So debugger could use HDT to skip 'jmp $' and execute the iret,
+ *  then they could find which instruction cause the exception.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+STATIC
+IdsUpdateExceptionVector (
+  IN       VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDT_DESCRIPTOR *IdtDesc;
+  UINT8   DescSize;
+  UINT16  Selector;
+  UINT16  i;
+  UINT64  HandlerOffset;
+  UINT64  EferRegister;
+  AGESA_STATUS Ignored;
+
+  LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader);
+  if ((EferRegister & 0x100) != 0) {
+    DescSize = 16;
+  } else {
+    DescSize = 8;
+  }
+
+  // Update limit
+  ((IDT_BASE_LIMIT *) DataPtr)->Limit = (UINT16) ((DescSize * 32) - 1);
+  // Update IDT
+  IdtDesc = (IDT_DESCRIPTOR *) (((IDT_BASE_LIMIT *) DataPtr)->Base);
+  HandlerOffset = (UINT64) IdsExceptionHandler;
+  GetCsSelector (&Selector, StdHeader);
+
+  ASSERT (SizeTotalIdtDescriptors == (SizeIdtDescriptor * 32));
+  for (i = 0; i < 32; i++) {
+    // Vector - 2 NMI handler for APs is used by AGESA. So we should not replace that handler.
+    if ((i == 2) && (!IsBsp (StdHeader, &Ignored)))  {
+      IdtDesc = (IDT_DESCRIPTOR *) (((UINT8 *) IdtDesc) + DescSize);
+      HandlerOffset += SizeIdtDescriptor;
+      continue;
+    }
+    IdtDesc->OffsetLo = (UINT16) HandlerOffset & 0xFFFF;
+    IdtDesc->OffsetHi = (UINT16) (HandlerOffset >> 16);
+    IdtDesc->Flags = IDT_DESC_PRESENT | IDT_DESC_TYPE_INT32;
+    IdtDesc->Selector = Selector;
+    IdtDesc->Rsvd = 0;
+    if ((EferRegister & 0x100) != 0) {
+      IdtDesc->Offset64 = (UINT32) (HandlerOffset >> 32);
+      IdtDesc->Rsvd64 = 0;
+    }
+    IdtDesc = (IDT_DESCRIPTOR *) (((UINT8 *) IdtDesc) + DescSize);
+    HandlerOffset += SizeIdtDescriptor;
+  }
+  return IDS_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c
new file mode 100644
index 0000000000..ba19c87441
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c
@@ -0,0 +1,79 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for common F15
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "IdsLib.h"
+
+
+#define FILECODE PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h
new file mode 100644
index 0000000000..dcea949c5b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h
@@ -0,0 +1,76 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+#ifndef _IDS_F15_ALLSERVICE_H_
+#define _IDS_F15_ALLSERVICE_H_
+#ifdef __IDS_EXTENDED__
+  #include IDS_EXT_INCLUDE_F15 (IdsIntF15AllService)
+#endif
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
new file mode 100644
index 0000000000..633d821c45
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
@@ -0,0 +1,420 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for common F15
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF15PowerMgmt.h"
+#include "cpuF15TnPowerMgmt.h"
+#include "IdsF15AllService.h"
+#include "IdsF15TnAllService.h"
+#include "IdsF15TnNvDef.h"
+#include "Gnb.h"
+#include "GnbGfx.h"
+#include "GnbRegistersTN.h"
+#include "GnbRegisterAccTN.h"
+#include "IdsRegAcc.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE
+
+/**
+ *  IDS F15 Backend Function for HTC Controls
+ *
+ *  This function is used to override HTC control Parameter.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of HTC register.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+STATIC IDS_STATUS
+IdsSubHTCControlF15Tn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  HTC_REGISTER *PHtcReg;
+  IDS_STATUS NvValue;
+
+  PHtcReg = (HTC_REGISTER *) DataPtr;
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_EN, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    case  IdsNvThermalHTCEnDisabled:
+      PHtcReg->HtcEn = 0;
+      break;
+    case  IdsNvThermalHTCEnEnabled:
+      PHtcReg->HtcEn = 1;
+      break;
+    case  IdsNvThermalHTCEnAuto:
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_OVERRIDE, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    case  IdsNvThermalHTCOverrideDisabled:
+      break;
+    case  IdsNvThermalHTCOverrideEnabled:
+      IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_PSTATE_LIMIT, IdsNvPtr, StdHeader) {
+        ASSERT ((NvValue >= IdsNvThermalHtcPstateLimitMin) && (NvValue <= IdsNvThermalHtcPstateLimitMax));
+        PHtcReg->HtcPstateLimit = NvValue;
+      }
+
+      IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_TEMP_HYS, IdsNvPtr, StdHeader) {
+        ASSERT ((NvValue >= IdsNvThermalHTCTempHysMin) && (NvValue <= IdsNvThermalHTCTempHysMax));
+        PHtcReg->HtcHystLmt = NvValue;
+      }
+
+      IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_ACT_TEMP, IdsNvPtr, StdHeader) {
+        ASSERT ((NvValue >= IdsNvThermalHTCActTempMin) && (NvValue <= IdsNvThermalHTCActTempMax));
+        PHtcReg->HtcTmpLmt = NvValue;
+      }
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Memory Mapping
+ *
+ *  This function is used to override the following setting.
+ *    EnableBankIntlv, ChannelIntlvMode, EnableNodeIntlv, MemHole,
+ *    EnablePowerDown, PowerDownMode, EnableBurstLen32, BankSwizzle,
+ *    UserTimingMode, MemClockValue, EnableParity, DqsTrainCtl, AllMemClks,
+ *    and EnableClkHZAltVidC3.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+STATIC IDS_STATUS
+IdsSubMemoryMappingF15Tn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_POST_PARAMS *PostParamsPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  IDS_STATUS NvValue;
+  MEM_DATA_STRUCT * memdataptr;
+
+  PostParamsPtr = (AMD_POST_PARAMS *)DataPtr;
+  memdataptr = PostParamsPtr->MemConfig.MemData;
+  RefPtr = memdataptr->ParameterListPtr;
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_BANK_INTERLEAVE, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    case  IdsNvMemMappingBankInterleaveDisabled:
+      RefPtr->EnableBankIntlv = FALSE;
+      break;
+    case  IdsNvMemMappingBankInterleaveAuto:
+      RefPtr->EnableBankIntlv = TRUE;
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_CHANNEL_INTERLEAVE, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    case  IdsNvMemMappingChlInterleaveAddress_bit_6:
+    case  IdsNvMemMappingChlInterleaveAddress_bit_12:
+    case  IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_:
+    case  IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_:
+    case  IdsNvMemMappingChlInterleaveAddress_bit_8:
+    case  IdsNvMemMappingChlInterleaveAddress_bit_9:
+      RefPtr->EnableChannelIntlv = TRUE;
+      break;
+    case  IdsNvMemMappingChlInterleaveDisabled:
+      RefPtr->EnableChannelIntlv = FALSE;
+      break;
+    case  IdsNvMemMappingChlInterleaveAuto:
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Channel Interleave F10
+ *
+ *  This function is used to override Channel Interleave.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of Data to Override.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+STATIC IDS_STATUS
+IdsIntSubChannelInterleaveF15Tn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS NvValue;
+  UINT8 *PDctSelIntLvAddr;
+
+  PDctSelIntLvAddr = (UINT8 *)DataPtr;
+  //DctSelIntLvAddr DCT Select Function
+  //000b            Address bit 6.
+  //001b            Address bit 12.
+  //010b            Hash: exclusive OR of address bits[20:16, 6].
+  //011b            Hash: exclusive OR of address bits[20:16, 9].
+  //100b            Address bit 8.
+  //101b            Address bit 9.
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_CHANNEL_INTERLEAVE, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    case  IdsNvMemMappingChlInterleaveAddress_bit_6:
+      *PDctSelIntLvAddr = 0;
+      break;
+    case  IdsNvMemMappingChlInterleaveAddress_bit_12:
+      *PDctSelIntLvAddr = 1;
+      break;
+    case  IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_:
+      *PDctSelIntLvAddr = 2;
+      break;
+    case  IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_:
+      *PDctSelIntLvAddr = 3;
+      break;
+    case  IdsNvMemMappingChlInterleaveAddress_bit_8:
+      *PDctSelIntLvAddr = 4;
+      break;
+    case  IdsNvMemMappingChlInterleaveAddress_bit_9:
+      *PDctSelIntLvAddr = 5;
+      break;
+    case  IdsNvMemMappingChlInterleaveDisabled:
+    case  IdsNvMemMappingChlInterleaveAuto:
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for override GNB platform config
+ *
+ *  @param[in,out]   DataPtr      The Pointer of BOOLEAN.
+ *  @param[in,out]   StdHeader The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+STATIC IDS_STATUS
+IdsSubGnbPlatformCfgF15Tn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  GFX_PLATFORM_CONFIG   *PGfx;
+  IDS_STATUS NvValue;
+
+  PGfx = (GFX_PLATFORM_CONFIG*) DataPtr;
+  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_GNBHDAUDIOEN, IdsNvPtr, StdHeader) {
+    switch (NvValue) {
+    //Auto
+    case  IdsNvGnbGfxNbAzaliaAuto:
+      break;
+    //Disabled
+    case  IdsNvGnbGfxNbAzaliaDisabled:
+      PGfx->GnbHdAudio = 0;
+      break;
+    //Enabled
+    case  IdsNvGnbGfxNbAzaliaEnabled:
+      PGfx->GnbHdAudio = 1;
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+/**
+ *  IDS Family specific Function for programming GMMX register
+ *
+ *  @param[in,out]   DataPtr      The Pointer of BOOLEAN.
+ *  @param[in,out]   StdHeader The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *
+ **/
+STATIC IDS_STATUS
+IdsRegSetGmmxF15Tn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_REG_GMMX *PIdsRegGmmx;
+  UINT32 Value;
+
+  PIdsRegGmmx = (IDS_REG_GMMX *) DataPtr;
+  GnbRegisterReadTN (
+    TYPE_GMM,
+    PIdsRegGmmx->Offset,
+    &Value,
+    0,
+    StdHeader);
+
+  IdsLibDataMaskSet32 (&Value, PIdsRegGmmx->AndMask, PIdsRegGmmx->OrMask);
+
+  GnbRegisterWriteTN (
+    TYPE_GMM,
+    PIdsRegGmmx->Offset,
+    &Value,
+    0,
+    StdHeader);
+
+  return IDS_SUCCESS;
+}
+
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn =
+{
+  IDS_FEAT_HTC_CTRL,
+  IDS_ALL_CORES,
+  IDS_HTC_CTRL,
+  AMD_FAMILY_15_TN,
+  IdsSubHTCControlF15Tn
+};
+
+
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn =
+{
+  IDS_FEAT_MEMORY_MAPPING,
+  IDS_ALL_CORES,
+  IDS_INIT_POST_BEFORE,
+  AMD_FAMILY_15_TN,
+  IdsSubMemoryMappingF15Tn
+};
+
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn =
+{
+  IDS_FEAT_MEMORY_MAPPING,
+  IDS_ALL_CORES,
+  IDS_CHANNEL_INTERLEAVE,
+  AMD_FAMILY_15_TN,
+  IdsIntSubChannelInterleaveF15Tn
+};
+
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn =
+{
+  IDS_FEAT_GNB_PLATFORMCFG,
+  IDS_ALL_CORES,
+  IDS_GNB_PLATFORMCFG_OVERRIDE,
+  AMD_FAMILY_15_TN,
+  IdsSubGnbPlatformCfgF15Tn
+};
+
+// For register access
+CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn =
+  MAKE_IDS_FAMILY_FEAT_ALL_CORES (
+    IDS_FAM_REG_GMMX,
+    AMD_FAMILY_15_TN,
+    IdsRegSetGmmxF15Tn
+  );
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
new file mode 100644
index 0000000000..ed9df50b3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
@@ -0,0 +1,76 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+#ifndef _IDS_F15_TN_ALLSERVICE_H_
+#define _IDS_F15_TN_ALLSERVICE_H_
+#ifdef __IDS_EXTENDED__
+  #include IDS_EXT_INCLUDE_F15_TN (IdsIntF15TnAllService)
+#endif
+
+#endif  //_IDS_F15_TN_ALLSERVICE_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
new file mode 100644
index 0000000000..53007a4159
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
@@ -0,0 +1,311 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS NV definition for F15Tn
+ *
+ * Auto generated from CBS XML file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS F15Tn
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+
+
+#ifndef _IDSF15TNNVDEF_H_
+#define _IDSF15TNNVDEF_H_
+///HTC Enable
+///Enable or disable Hardware Thermal Control. D18F3x64[0]
+typedef enum {
+  IdsNvThermalHTCEnDisabled = 0,///<Disabled
+  IdsNvThermalHTCEnEnabled = 1,///<Enabled
+  IdsNvThermalHTCEnAuto = 3,///<Auto
+} IdsNvThermalHTCEn;
+
+///HTC Override
+///Enable or disable Thermal Control Override
+typedef enum {
+  IdsNvThermalHTCOverrideDisabled = 0,///<Disabled
+  IdsNvThermalHTCOverrideEnabled = 1,///<Enabled
+} IdsNvThermalHTCOverride;
+
+///HTC P-state limit select
+///Specifies the P-state limit of all cores when in the P-state based HTC-active state
+#define IdsNvThermalHtcPstateLimitMin 0
+#define IdsNvThermalHtcPstateLimitMax 7
+
+///HTC Temperature Hysteresis
+///Sets the temperature hysteresis for HTC. D18F3x64[27:24]
+#define IdsNvThermalHTCTempHysMin 0
+#define IdsNvThermalHTCTempHysMax 0xF
+
+///HTC Activation Temp
+///Sets the HTC temperature limit. D18F3x64[22:16]
+#define IdsNvThermalHTCActTempMin 0
+#define IdsNvThermalHTCActTempMax 0x7F
+
+///Bank Interleave
+///Interleave memory blocks across the DRAM chip selects for node 0.
+typedef enum {
+  IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled
+  IdsNvMemMappingBankInterleaveAuto = 1,///<Auto
+} IdsNvMemMappingBankInterleave;
+
+///DRAM Channel Interleave
+///Interleave between two DCTs when they are in unganged mode.
+typedef enum {
+  IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6
+  IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12
+  IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6]
+  IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9]
+  IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8
+  IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9
+  IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled
+  IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto
+} IdsNvMemMappingChlInterleave;
+
+///ECC Symbol Size
+///ECC symbol size and code selection. D18F3x180[25]
+typedef enum {
+  IdsNvEccSymbolSizex4 = 0,///<x4
+  IdsNvEccSymbolSizex8 = 1,///<x8
+  IdsNvEccSymbolSizeAuto = 3,///<Auto
+} IdsNvEccSymbolSize;
+
+///DRAM prefetches triggered from CPU requests
+///Enable or disable DRAM prefetches Prefetch triggered by CPU requests.
+typedef enum {
+  IdsNvPrefetchPrefCpuDis0 = 0,///<0
+  IdsNvPrefetchPrefCpuDis1 = 1,///<1
+  IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto
+} IdsNvPrefetchPrefCpuDis;
+
+///HW prefetch training on SW Prefetches
+///Enable or disable Hardware Prefetch training on Software Prefetches
+typedef enum {
+  IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0
+  IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1
+  IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto
+} IdsNvPrefetchDisHWPFforSWPF;
+
+///Hardware Prefetches
+///Enable or disable Hardware Prefetches.
+typedef enum {
+  IdsNvPrefetchDisHWPF0 = 0,///<0
+  IdsNvPrefetchDisHWPF1 = 1,///<1
+  IdsNvPrefetchDisHWPFAuto = 3,///<Auto
+} IdsNvPrefetchDisHWPF;
+
+///UMI Gen2
+///Enable or disable UMI link Gen2
+typedef enum {
+  IdsNvFchGppUmiGen2Disabled = 0,///<Disabled
+  IdsNvFchGppUmiGen2Enabled = 1,///<Enabled
+} IdsNvFchGppUmiGen2;
+
+///SATA Controller
+///Disable or enable OnChip SATA controller
+typedef enum {
+  IdsNvFchSataEnableDisabled = 0,///<Disabled
+  IdsNvFchSataEnableEnabled = 1,///<Enabled
+} IdsNvFchSataEnable;
+
+///SATA Mode
+///Select OnChip SATA Type
+typedef enum {
+  IdsNvFchSataClassNative_IDE = 0,///<Native IDE
+  IdsNvFchSataClassRAID = 1,///<RAID
+  IdsNvFchSataClassAHCI = 3,///<AHCI
+  IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE
+  IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI
+  IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804
+  IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804
+} IdsNvFchSataClass;
+
+///OnChip IDE
+///Select OnChip IDE controller mode
+typedef enum {
+  IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE
+  IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE
+} IdsNvFchSataIdeMode;
+
+///IDE Controller
+///Disable or enable OnChip IDE controller
+typedef enum {
+  IdsNvFchSataIdeEnableDisabled = 0,///<Disabled
+  IdsNvFchSataIdeEnableEnabled = 1,///<Enabled
+} IdsNvFchSataIdeEnable;
+
+///XHC Switch (Bus 0 Dev 16 Fn 0/1)
+///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1)
+typedef enum {
+  IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled
+  IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled
+} IdsNvFchUsbXhciSwitch;
+
+///USB1(Bus 0 Dev 18 Fn 0/2)
+///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2)
+typedef enum {
+  IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled
+  IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci1Enable;
+
+///USB2 (Bus 0 Dev 19 Fn 0/2)
+///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2)
+typedef enum {
+  IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled
+  IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci2Enable;
+
+///USB3 (Bus 0 Dev 22 Fn 0/2)
+///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2)
+typedef enum {
+  IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled
+  IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci3Enable;
+
+///USB4 (Bus 0 Dev 20 Fn 5)
+///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5)
+typedef enum {
+  IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled
+  IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci4Enable;
+
+///Hardware Monitor Enable
+///Master switch to enable or disable hardware monitor function
+typedef enum {
+  IdsNvFchHwmEnableDisabled = 0,///<Disabled
+  IdsNvFchHwmEnableEnabled = 1,///<Enabled
+} IdsNvFchHwmEnable;
+
+///In-Chip IR
+///Enable or disable the In-Chip IR
+typedef enum {
+  IdsNvFchIrConfigDisabled = 0,///<Disabled
+  IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only
+  IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only
+  IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1
+} IdsNvFchIrConfig;
+
+///SD Configuration Mode
+///Select SD Mode
+typedef enum {
+  IdsNvFchSdConfigDisabled = 0,///<Disabled
+  IdsNvFchSdConfigADMA = 1,///<ADMA
+  IdsNvFchSdConfigDMA = 2,///<DMA
+  IdsNvFchSdConfigPIO = 3,///<PIO
+} IdsNvFchSdConfig;
+
+typedef enum {
+  IdsNvFchAzaliaControlAuto = 0,///<Auto
+  IdsNvFchAzaliaControlDisabled = 1,///<Disabled
+  IdsNvFchAzaliaControlEnabled = 2,///<Enabled
+  IdsNvFchAzaliaControlReserved = 3,///<Reserved
+} IdsNvFchAzaliaControl;
+
+///Integrated Graphics Controller
+///Enable Integrate Graphics controller
+typedef enum {
+  IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto
+  IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled
+  IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces
+} IdsNvGnbGfxiGPU_CONTROL;
+
+///UMA Frame buffer Size
+///Set UMA FB size
+typedef enum {
+  IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto
+  IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M
+  IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M
+  IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M
+  IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M
+  IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M
+  IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M
+  IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G
+  IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G
+  IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G
+} IdsNvGnbGfxUmaFrameBufferSize;
+
+///Enable Integrate HD Audio controller
+typedef enum {
+  IdsNvGnbGfxNbAzaliaAuto = 0,///<Auto
+  IdsNvGnbGfxNbAzaliaDisabled = 1,///<Disabled
+  IdsNvGnbGfxNbAzaliaEnabled = 2,///<Enabled
+} IdsNvGnbGfxNbAzalia;
+
+///PSPP Policy
+///PCIe speed power policy
+typedef enum {
+  IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled
+  IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance
+  IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High
+  IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low
+  IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving
+  IdsNvGnbPciePsppPolicyAuto = 5,///<Auto
+} IdsNvGnbPciePsppPolicy;
+
+///IOMMU
+///
+typedef enum {
+  IdsNvGnbNbIOMMUDisabled = 0,///<Disabled
+  IdsNvGnbNbIOMMUEnabled = 1,///<Enabled
+} IdsNvGnbNbIOMMU;
+
+#endif // _IDSF15TNNVDEF_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h
new file mode 100644
index 0000000000..a5db129f12
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h
@@ -0,0 +1,444 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_LIB_H_
+#define _IDS_LIB_H_
+#include "OptionsIds.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "Table.h"
+///Specific time stamp performance analysis which need ids control support
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define PERF_SPEC_TS_ANALYSE(StdHeader)  IdsPerfSpecTsAnalyse(StdHeader)
+#else
+  #define PERF_SPEC_TS_ANALYSE(StdHeader)
+#endif
+
+
+#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader)\
+  if (((NvValue) = AmdIdsNvReader ((Nvid), (IdsNvPtr), (StdHeader))) != IDS_UNSUPPORTED)
+#define IDS_GET_MASK32(HighBit, LowBit) ((((UINT32) 1 << (HighBit - LowBit + 1)) - 1) << LowBit)
+
+#define IDS_MAX_MEM_ITEMS   80     ///< Maximum IDS Mem Table Size in Heap.
+///Macro for Ids family feat
+#define MAKE_IDS_FAMILY_FEAT_ALL_CORES(FEAT_ID, FAMILY, FUNCTION) \
+        {IDS_FEAT_COMMON, IDS_ALL_CORES, FEAT_ID, FAMILY, FUNCTION}
+
+
+// TYPEDEFS, STRUCTURES, ENUMS
+//
+
+typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader);
+
+///Structure define for IdsAgesaRunFcnOnApLate
+typedef struct _IDSAPLATETASK {
+  PF_IDS_AP_TASK  ApTask; ///< Point function which AP need to do
+  VOID *ApTaskPara; ///< Point to Ap function parameter1
+} IDSAPLATETASK;
+
+/// Data Structure defining IDS Data in HEAP
+/// This data structure contains information that is stored in HEAP and will be
+/// used in IDS backend function. It includes the size of memory to be allocated
+/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA
+/// table and the register table to override mem setting. It also includes a base
+/// address of IDS override image which will be used to control the behavior of
+/// AGESA testpoint if this feature is enabled.
+typedef struct {
+  BOOLEAN IgnoreIdsDefault;             ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset
+  UINT64 IdsImageBase;                 ///< IDS Override Image Base Address
+  UINT32 IdsHeapMemSize;              ///< IDS Total Memory Size in Heap
+  UINT32 IdsNvTableOffset;            ///< Offset of IDS NV Table
+  UINT32 IdsMemTableOffset;           ///< Offset of IDS Mem Table
+  UINT32 IdsExtendOffset;                ///< Offset of Ids extend heap
+} IDS_CONTROL_STRUCT;
+
+#define MAX_PERFORMANCE_UNIT_NUM 100
+/// Data Structure of Parameters for TestPoint_TSC.
+typedef struct {
+  UINT32 LineInFile;                    ///< Line of current time counter
+  UINT64 StartTsc;                  ///< The StartTimer of TestPoint_TSC
+} TestPoint_TSC;
+
+/// Data Structure of Parameters for TP_Perf_STRUCT.
+typedef struct {
+  UINT32 Signature;                ///< "TIME"
+  UINT32 Index;                    ///< The Index of TP_Perf_STRUCT
+  UINT32 TscInMhz;            ///< Tsc counter in 1 mhz
+  TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM];       ///< The TP of TP_Perf_STRUCT
+} TP_Perf_STRUCT;
+
+///Bus speed Optimization
+typedef enum {
+  IDS_POWER_POLICY_PERFORMANCE = 0,              ///< Performance
+  IDS_POWER_POLICY_POWER = 1,              ///< Power
+  IDS_POWER_POLICY_AUTO = 3,              ///< Auto
+} IDS_NV_AMDBUSSPEEDOPTIMIZATION;
+
+///IDS early AP task
+typedef struct _IDS_EARLY_AP_TASK0 {
+  UINT8 Core;             ///< Core to run Aptask
+  AP_TASK ApTask;        ///< Speicify task property
+} IDS_EARLY_AP_TASK0;
+
+#define IDS_EARLY_AP_TASK_PARA_NUM 100
+///IDS early AP task
+typedef struct _IDS_EARLY_AP_TASK {
+  IDS_EARLY_AP_TASK0 Ap_Task0;    ///< Ap Task exclude parameter buffer
+  UINT8 Parameters[IDS_EARLY_AP_TASK_PARA_NUM];          ///< Parameter buffer
+} IDS_EARLY_AP_TASK;
+
+
+#define IDS_ALL_SOCKET 0xFF
+#define IDS_ALL_MODULE 0xFF
+#define IDS_ALL_CORE   0xFF
+#define IDS_ALL_DCT   0xFF
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+IDS_STATUS
+IdsSubUCode (
+  IN OUT  VOID *DataPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader,
+  IN      IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubGangingMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubPowerDownMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubBurstLength32 (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+
+IDS_STATUS
+IdsSubAllMemClkEn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubDllShutDownSR (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubHtLinkControl (
+     OUT   VOID  *Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubPostPState (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubPowerPolicyOverride (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+AGESA_STATUS
+AmdIdsCtrlInitialize (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+AmdIdsNvReader (
+  IN      UINT16 IdsNvId,
+  IN      IDS_NV_ITEM *NvTablePtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+AmdGetIdsNvTable (
+  IN OUT   VOID  **IdsNvTable,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsOutPort (
+  IN       UINT32 Addr,
+  IN       UINT32 Value,
+  IN       UINT32 Flag
+  );
+
+IDS_STATUS
+IdsCommonReturn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+AGESA_STATUS
+IdsAgesaRunFcnOnApLate  (
+  IN       UINTN               ApicIdOfCore,
+  IN         IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsAgesaRunFcnOnAllCoresLate  (
+  IN         IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsParseFeatTbl (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN       CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[],
+  IN OUT   VOID *DataPtr,
+  IN       IDS_NV_ITEM *IdsNvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsSubPowerDownCtrl (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubHdtOut (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+UINT8
+IdsGetNumPstatesFamCommon (
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+IdsApRunCodeOnAllLocalCores (
+  IN       AP_TASK *TaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+IDS_STATUS
+IdsSubTargetPstate (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+VOID
+IdsMakePciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN        UINT32 Mask
+  );
+
+VOID
+IdsMakeHtLinkPciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtHostFeat,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN        UINT32 Mask
+  );
+
+VOID
+IdsMakeHtFeatPciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtHostFeat,
+  IN       UINT32 PackageType,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN        UINT32 Mask
+  );
+
+VOID
+IdsMakeHtHostPciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtHostFeat,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN        UINT32 Mask
+  );
+
+VOID
+IdsMakeHtPhyRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtPhyLinkFeat,
+  IN       UINT32 Address,
+  IN       UINT32 Data,
+  IN        UINT32 Mask
+  );
+
+VOID
+IdsLibPciWriteBitsToAllNode (
+  IN       PCI_ADDR PciAddress,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       UINT32 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+VOID
+IdsRunCodeOnCoreEarly (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AP_TASK* ApTask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsGetMask64bits (
+  IN       UINT64 RegVal,
+  IN       UINT8  Highbit,
+  IN       UINT8  Lowbit,
+  IN OUT   UINT64 *AndMask,
+  IN OUT   UINT64 *OrMask
+  );
+
+VOID
+IdsGetMask32bits (
+  IN       UINT32 RegVal,
+  IN       UINT8  Highbit,
+  IN       UINT8  Lowbit,
+  IN OUT   UINT32 *AndMask,
+  IN OUT   UINT32 *OrMask
+  );
+
+VOID
+IdsGetMask16bits (
+  IN       UINT16 RegVal,
+  IN       UINT8  Highbit,
+  IN       UINT8  Lowbit,
+  IN OUT   UINT32 *AndMask,
+  IN OUT   UINT32 *OrMask
+  );
+
+VOID
+IdsGetStartEndModule (
+  IN       UINT8  ModuleId,
+  IN OUT   UINT8 *StartModule,
+  IN OUT   UINT8 *EndModule
+  );
+
+
+VOID
+IdsGetStartEndSocket (
+  IN       UINT8  SocketId,
+  IN OUT   UINT8 *StartSocket,
+  IN OUT   UINT8 *EndSocket
+  );
+
+BOOLEAN
+IdsCheckPciExisit (
+  IN       PCI_ADDR PciAddr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsLibDataMaskSet32 (
+  IN OUT   UINT32 *Value,
+  IN       UINT32  AndMask,
+  IN       UINT32  OrMask
+  );
+#define IDS_CPB_BOOST_DIS_IGNORE  0xFFFFFFFFul
+
+#endif //_IDS_LIB_H_
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h
new file mode 100644
index 0000000000..a3995e8a15
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for Integrated Debug Support Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/**
+ * @page idsmain Integrated Debug Support Component Documentation
+ *
+ * Additional documentation for the Integrated Debug Support component consists of
+ *
+ * - Maintenance Guides:
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
new file mode 100644
index 0000000000..ec9355a70a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
@@ -0,0 +1,959 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "IdsLib.h"
+#include "heapManager.h"
+
+#include "mm.h"
+#include "mn.h"
+#include "cpuLateInit.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ *
+ *  Get IDS NV table pointer in the AGESA Heap.
+ *
+ *  @param[in,out] IdsNvTable   The Pointer of IDS NV Table.
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of NV Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of NV Table.
+ **/
+AGESA_STATUS
+AmdGetIdsNvTable (
+  IN OUT   VOID  **IdsNvTable,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+
+  LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status == AGESA_SUCCESS) {
+    IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr;
+    *IdsNvTable = LocateHeapStructPtr.BufferPtr + IdsCtrlPtr->IdsNvTableOffset;
+  }
+  return status;
+}
+
+/**
+ *
+ *  Get IDS Override Image Base Address
+ *
+ *  @param[in,out] IdsImageBase The Base Address of IDS Override Image.
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of NV Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of NV Table.
+ *
+ **/
+#if 0
+AGESA_STATUS
+AmdGetIdsImagebase (
+  IN OUT   UINT64 *IdsImageBase,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+
+  LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status == AGESA_SUCCESS) {
+    IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr;
+    *IdsImageBase = IdsCtrlPtr->IdsImageBase;
+  }
+  return status;
+}
+#endif
+/**
+ *
+ * Read IDS NV value in NV table.
+ *
+ * It searches the table until the Nv Id is found and return the NV value
+ * in the table. Otherwise, return IDS_UNSUPPORTED.
+ *
+ * @param[in] IdsNvId       IDS NV ID
+ * @param[in] NvTablePtr    NV Table pointer.
+ * @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ * @retval IDS_UNSUPPORTED  NV ID is not found in the table
+ *         Other Value      The NV value
+ *
+ **/
+IDS_STATUS
+AmdIdsNvReader (
+  IN       UINT16 IdsNvId,
+  IN       IDS_NV_ITEM *NvTablePtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_STATUS Status;
+  IDS_NV_ITEM *NvPtr;
+  BOOLEAN IgnoreIdsDefault;
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+
+  IgnoreIdsDefault = FALSE;
+  Status = IDS_UNSUPPORTED;
+  NvPtr = NvTablePtr;
+
+  if (NvPtr != NULL) {
+    while (NvPtr->IdsNvId != AGESA_IDS_NV_END) {
+      if (NvPtr->IdsNvId == IdsNvId) {
+        break;
+      } else {
+        NvPtr ++;
+      }
+    }
+    if ((NvPtr->IdsNvId != AGESA_IDS_NV_END)) {
+      //Get IgnoreIdsDefault from heap
+      LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE;
+      LocateHeapStructPtr.BufferPtr = NULL;
+      status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+      if (status == AGESA_SUCCESS) {
+        IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr;
+        IgnoreIdsDefault = IdsCtrlPtr->IgnoreIdsDefault;
+      }
+
+      if (IgnoreIdsDefault || (NvPtr->IdsNvValue != AGESA_IDS_DFT_VAL)) {
+        Status = NvPtr->IdsNvValue;
+      }
+    }
+  }
+  return Status;
+}
+
+/**
+ * IDS function for only return IDS_SUCCESS
+ *
+ *
+ *  @param[in,out]   DataPtr      meaningless data pointer
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS          Always succeeds.
+ *
+ **/
+IDS_STATUS
+IdsCommonReturn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  return IDS_SUCCESS;
+}
+
+
+/**
+ * IDS function for ap run specific task after amdinitpost
+ *
+ *
+ *  @param[in]   ApicIdOfCore      apic id of specific AP
+ *  @param[in]   ApLateTaskPtr    The Pointer of IDSAPLATETASK.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+IdsAgesaRunFcnOnApLate  (
+  IN       UINTN               ApicIdOfCore,
+  IN       IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS  Status;
+  AP_EXE_PARAMS LaunchApParams;
+
+//init AgesaRunFcnOnAp parameters
+  LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID;
+  LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK);
+  LaunchApParams.RelatedDataBlock = ApLateTaskPtr;
+  LaunchApParams.StdHeader = *StdHeader;
+
+  AGESA_TESTPOINT (TpIfBeforeRunApFromIds, StdHeader);
+  Status = AgesaRunFcnOnAp ((UINTN) ApicIdOfCore, &LaunchApParams);
+  AGESA_TESTPOINT (TpIfAfterRunApFromIds, StdHeader);
+
+  return Status;
+}
+
+/**
+ * IDS function force all cores run specific task after amdinitpost
+ *
+ *
+ *  @param[in]   ApLateTaskPtr    The Pointer of IDSAPLATETASK.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+IdsAgesaRunFcnOnAllCoresLate  (
+  IN       IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_EXE_PARAMS LaunchApParams;
+  AGESA_STATUS Status;
+
+//init AgesaRunFcnOnAp parameters
+  Status = AGESA_SUCCESS;
+  LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID;
+  LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK);
+  LaunchApParams.RelatedDataBlock = ApLateTaskPtr;
+  LaunchApParams.StdHeader = *StdHeader;
+
+  Status = RunLateApTaskOnAllAPs (&LaunchApParams, StdHeader);
+
+//do it on Bsp
+  Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, StdHeader);
+  return Status;
+}
+
+/**
+ * IDS call-back function for ApDispatchTable
+ *
+ *  @param[in] AmdApExeParams  AP_EXE_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  )
+{
+  IDSAPLATETASK *ApLateTaskPtr;
+  AGESA_STATUS Status;
+
+  ApLateTaskPtr = (IDSAPLATETASK *)AmdApExeParams->RelatedDataBlock;
+  Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, &AmdApExeParams->StdHeader);
+  return Status;
+}
+
+/**
+ *  Get the number of P-State to support
+ *
+ *  @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval num    The number of P-State to support.
+ *
+ **/
+UINT8
+IdsGetNumPstatesFamCommon (
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 pstatesnum;
+  UINT8 i;
+  UINT8 IgnoredByte;
+  UINT32 Ignored;
+  BOOLEAN PStateEnabled;
+  UINT32 TempVar_c;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+
+  pstatesnum = 0;
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &IgnoredByte, StdHeader);
+  for (i = 0; i <= TempVar_c; i++) {
+    // Check if PState is enabled
+    FamilyServices->GetPstateRegisterInfo (        FamilyServices,
+                                                   (UINT32) i,
+                                                   &PStateEnabled,
+                                                   &Ignored,
+                                                   &Ignored,
+                                                   &Ignored,
+                                                   StdHeader);
+    if (PStateEnabled) {
+      pstatesnum++;
+    }
+  }
+  return pstatesnum;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the given task on all cores (including self) on the socket of the executing
+ * core 0.
+ *
+ * This function is used to invoke all APs on the socket of the executing core 0 to
+ * run a specified AGESA procedure.
+ *
+ * @param[in]  TaskPtr      Function descriptor
+ * @param[in]  StdHeader    Config handle for library and services
+ *
+ */
+VOID
+IdsApRunCodeOnAllLocalCores (
+  IN       AP_TASK *TaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Core;
+  UINT32 BscCoreNum;
+  UINT32 Socket;
+  UINT32 BscSocket;
+  UINT32 IgnoredModule;
+  UINT32 NumberOfCores;
+  UINT32 NumberOfSockets;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+ // BSP codes
+  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL);
+}
+
+/**
+ *  IdsMakePciRegEntry
+ *
+ *
+ *  @param[in,out]      TableEntry      The Pointer of TableEntry
+*  @param[in]      Family      Family
+*  @param[in]      Revision      Revision
+*  @param[in]      PciAddr      PCI address
+*  @param[in]      Data      Or Mask
+*  @param[in]      Mask      And Mask
+ *
+ *
+ */
+VOID
+IdsMakePciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN       UINT32 Mask
+  )
+{
+  (*TableEntry)->EntryType = PciRegister;
+  (*TableEntry)->CpuRevision.Family = Family;
+  (*TableEntry)->CpuRevision.Revision = Revision;
+  (*TableEntry)->Features.PlatformValue = AMD_PF_ALL;
+  (*TableEntry)->Entry.PciEntry.Address.AddressValue = PciAddr;
+  (*TableEntry)->Entry.PciEntry.Data = Data;
+  (*TableEntry)->Entry.PciEntry.Mask = Mask;
+  (*TableEntry)++;
+}
+
+/**
+ *  IdsMakeHtLinkPciRegEntry
+ *
+ *
+ *  @param[in,out]      TableEntry      The Pointer of TableEntry
+*  @param[in]      Family      Family
+*  @param[in]      Revision      Revision
+*  @param[in]      HtHostFeat      HtHostFeat
+*  @param[in]      PciAddr      PCI address
+*  @param[in]      Data      Or Mask
+*  @param[in]      Mask      And Mask
+ *
+ *
+ */
+VOID
+IdsMakeHtLinkPciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtHostFeat,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN       UINT32 Mask
+  )
+{
+  (*TableEntry)->EntryType = HtLinkPciRegister;
+  (*TableEntry)->CpuRevision.Family = Family;
+  (*TableEntry)->CpuRevision.Revision = Revision;
+  (*TableEntry)->Features.PlatformValue = AMD_PF_ALL;
+  (*TableEntry)->Entry.HtLinkPciEntry.LinkFeats.HtHostValue = HtHostFeat;
+  (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Address.AddressValue = PciAddr;
+  (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Data = Data;
+  (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Mask = Mask;
+  (*TableEntry)++;
+}
+/**
+ *  IdsMakeHtFeatPciRegEntry
+ *
+ *
+ *  @param[in,out]      TableEntry      The Pointer of TableEntry
+*  @param[in]      Family      Family
+*  @param[in]      Revision      Revision
+*  @param[in]      HtHostFeat      HtHostFeat
+*  @param[in]      PackageType      PackageType
+*  @param[in]      PciAddr      PCI address
+*  @param[in]      Data      Or Mask
+*  @param[in]      Mask      And Mask
+ *
+ *
+ */
+VOID
+IdsMakeHtFeatPciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtHostFeat,
+  IN       UINT32 PackageType,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN       UINT32 Mask
+  )
+{
+  (*TableEntry)->EntryType = HtFeatPciRegister;
+  (*TableEntry)->CpuRevision.Family = Family;
+  (*TableEntry)->CpuRevision.Revision = Revision;
+  (*TableEntry)->Features.PlatformValue = AMD_PF_ALL;
+  (*TableEntry)->Entry.HtFeatPciEntry.LinkFeats.HtHostValue = HtHostFeat;
+  (*TableEntry)->Entry.HtFeatPciEntry.PackageType.PackageTypeValue = PackageType;
+  (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Address.AddressValue = PciAddr;
+  (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Data = Data;
+  (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Mask = Mask;
+  (*TableEntry)++;
+}
+/**
+ *  IdsMakeHostPciRegEntry
+ *
+ *
+ *  @param[in,out]      TableEntry      The Pointer of TableEntry
+*  @param[in]      Family      Family
+*  @param[in]      Revision      Revision
+*  @param[in]      HtHostFeat      HtHostFeat
+*  @param[in]      PciAddr      PCI address
+*  @param[in]      Data      Or Mask
+*  @param[in]      Mask      And Mask
+ *
+ *
+ */
+VOID
+IdsMakeHtHostPciRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtHostFeat,
+  IN       UINT32 PciAddr,
+  IN       UINT32 Data,
+  IN       UINT32 Mask
+  )
+{
+  (*TableEntry)->EntryType = HtHostPciRegister;
+  (*TableEntry)->CpuRevision.Family = Family;
+  (*TableEntry)->CpuRevision.Revision = Revision;
+  (*TableEntry)->Features.PlatformValue = AMD_PF_ALL;
+  (*TableEntry)->Entry.HtHostEntry.TypeFeats.HtHostValue = HtHostFeat;
+  (*TableEntry)->Entry.HtHostEntry.Address.AddressValue = PciAddr;
+  (*TableEntry)->Entry.HtHostEntry.Data = Data;
+  (*TableEntry)->Entry.HtHostEntry.Mask = Mask;
+  (*TableEntry)++;
+}
+/**
+ *  IdsMakeHtPhyRegEntry
+ *
+ *
+ *  @param[in,out]      TableEntry      The Pointer of TableEntry
+*  @param[in]      Family      Family
+*  @param[in]      Revision      Revision
+*  @param[in]      HtPhyLinkFeat      HtPhyLinkFeat
+*  @param[in]      Address      PCI address
+*  @param[in]      Data      Or Mask
+*  @param[in]      Mask      And Mask
+ *
+ *
+ */
+VOID
+IdsMakeHtPhyRegEntry (
+  IN OUT   TABLE_ENTRY_FIELDS **TableEntry,
+  IN       UINT64 Family,
+  IN       UINT64 Revision,
+  IN       UINT32 HtPhyLinkFeat,
+  IN       UINT32 Address,
+  IN       UINT32 Data,
+  IN       UINT32 Mask
+  )
+{
+  (*TableEntry)->EntryType = HtPhyRegister;
+  (*TableEntry)->CpuRevision.Family = Family;
+  (*TableEntry)->CpuRevision.Revision = Revision;
+  (*TableEntry)->Features.PlatformValue = AMD_PF_ALL;
+  (*TableEntry)->Entry.HtPhyEntry.TypeFeats.HtPhyLinkValue = HtPhyLinkFeat;
+  (*TableEntry)->Entry.HtPhyEntry.Address = Address;
+  (*TableEntry)->Entry.HtPhyEntry.Data = Data;
+  (*TableEntry)->Entry.HtPhyEntry.Mask = Mask;
+  (*TableEntry)++;
+}
+
+/**
+ *  IdsOptionCallout
+ *
+ * Description
+ *    Call the host environment interface to provide a user hook opportunity.
+ *
+ *  @param[in]      CallOutId         This parameter indicates the IDS Call-Out-function desired.
+ *  @param[in,out]  DataPtr           The pointer for callout function use
+ *  @param[in,out]  StdHeader    Config handle for library and services
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ */
+AGESA_STATUS
+IdsOptionCallout (
+  IN       UINTN                CallOutId,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_CALLOUT_STRUCT IdsCalloutData;
+  IDS_NV_ITEM NullEntry;
+
+  NullEntry.IdsNvId = 0xFFFF;
+  NullEntry.IdsNvValue = 0xFFFF;
+  IdsCalloutData.StdHeader = *StdHeader;
+  IdsCalloutData.IdsNvPtr = &NullEntry;
+  IdsCalloutData.Reserved = (UINTN) DataPtr;
+
+  return AgesaGetIdsData (CallOutId, &IdsCalloutData);
+
+}
+
+/**
+ * Ids Write PCI register to All node
+ *
+ *
+ * @param[in] PciAddress    Pci address
+ * @param[in]   Highbit       High bit position of the field in DWORD
+ * @param[in]   Lowbit        Low bit position of the field in DWORD
+ * @param[in] Value         Pointer to input value
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+IdsLibPciWriteBitsToAllNode (
+  IN       PCI_ADDR PciAddress,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       UINT32 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  AGESA_STATUS IgnoreStatus;
+  PCI_ADDR PciAddr;
+
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+      if (GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoreStatus)) {
+        PciAddr.Address.Function = PciAddress.Address.Function;
+        PciAddr.Address.Register = PciAddress.Address.Register;
+        LibAmdPciWriteBits (PciAddr, Highbit, Lowbit, Value, StdHeader);
+      }
+    }
+  }
+}
+
+/**
+ *
+ *
+ *     Core 0 task to run local ap task at early
+ *
+ *     @param[in]   PEarlyApTask   - point to  IDS_EARLY_AP_TASK structure
+ *     @param[in,out]   StdHeader    - The Pointer of AGESA Header
+ *
+ */
+
+STATIC VOID
+IdsCmnTaskCore0Early (
+  IN       IDS_EARLY_AP_TASK *PEarlyApTask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  AGESA_STATUS IgnoredSts;
+
+  ASSERT (PEarlyApTask->Ap_Task0.Core != 0);
+
+  PEarlyApTask->Ap_Task0.ApTask.DataTransfer.DataPtr = &PEarlyApTask->Parameters[0];
+  IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+  ApUtilRunCodeOnSocketCore ((UINT8)Socket, PEarlyApTask->Ap_Task0.Core, &PEarlyApTask->Ap_Task0.ApTask, StdHeader);
+}
+
+/**
+ *
+ *
+ *     BSC task to run Core0 task at early, must only run on BSC
+ *
+ *     @param[in]   Socket   - Socket which run the task
+ *     @param[in]   Core   - Core which run the task
+ *     @param[in]   ApTask   - Task for AP
+ *     @param[in,out]   StdHeader    - The Pointer of AGESA Header
+ *
+ */
+VOID
+IdsRunCodeOnCoreEarly (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AP_TASK* ApTask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 BscSocket;
+  UINT32 BscCoreNum;
+  UINT32 IgnoredModule;
+  AGESA_STATUS IgnoredSts;
+  AP_TASK Core0Task;
+  IDS_EARLY_AP_TASK IdsEarlyTask;
+
+  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts);
+  ASSERT (~((Socket == BscSocket) && (Core == BscCoreNum)));
+  if ((Socket == BscSocket) || (Core == 0)) {
+    ApUtilRunCodeOnSocketCore (Socket, Core, ApTask, StdHeader);
+  } else {
+    //Init IDS_EARLY_AP_TASK for Core 0
+    IdsEarlyTask.Ap_Task0.ApTask = *ApTask;
+    IdsEarlyTask.Ap_Task0.Core = Core;
+    //Init Parameter buffer, Target core can't get the parameter from pointer, which point to Host Core memory space
+    ASSERT ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM);
+    LibAmdMemCopy (&IdsEarlyTask.Parameters[0], ApTask->DataTransfer.DataPtr, sizeof (UINT32) * ApTask->DataTransfer.DataSizeInDwords, StdHeader);
+    if ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM) {
+      //Lauch Core0 1st
+      Core0Task.FuncAddress.PfApTaskI = (PF_AP_TASK_I)IdsCmnTaskCore0Early;
+      Core0Task.ExeFlags = WAIT_FOR_CORE;
+      Core0Task.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (IDS_EARLY_AP_TASK0) + ApTask->DataTransfer.DataSizeInDwords;
+      Core0Task.DataTransfer.DataPtr = &IdsEarlyTask;
+      Core0Task.DataTransfer.DataTransferFlags = 0;
+      ApUtilRunCodeOnSocketCore (Socket, 0, &Core0Task, StdHeader);
+    }
+  }
+}
+
+/**
+ *
+ *
+ *     This function get start end Module according to input ModuleId
+ *
+ *     @param[in]   ModuleId   - 0xFF means all nodes, other value Specifies real NodeId
+ *     @param[in,out]   StartModule    - Point to start Node
+ *     @param[in,out]   EndModule   - Point to end Node
+ *
+ */
+VOID
+IdsGetStartEndModule (
+  IN       UINT8  ModuleId,
+  IN OUT   UINT8 *StartModule,
+  IN OUT   UINT8 *EndModule
+  )
+{
+  if (ModuleId == 0xFF) {
+    *StartModule = 0;
+    *EndModule = (UINT8) (GetPlatformNumberOfSockets () * GetPlatformNumberOfModules () - 1);
+    if (*EndModule > 7) {
+      *EndModule = 7;
+    }
+  } else {
+    *StartModule = ModuleId;
+    *EndModule = ModuleId;
+  }
+}
+
+/**
+ *
+ *
+ *     This function get start end socket according to input SocketId
+ *
+ *     @param[in]   SocketId   - 0xFF means all sockets, other value Specifies real SokcetId
+ *     @param[in,out]   StartSocket    - Point to start Socket
+ *     @param[in,out]   EndSocket   - Point to end Socket
+ *
+ */
+VOID
+IdsGetStartEndSocket (
+  IN       UINT8  SocketId,
+  IN OUT   UINT8 *StartSocket,
+  IN OUT   UINT8 *EndSocket
+  )
+{
+  if (SocketId == 0xFF) {
+    *StartSocket = 0;
+    *EndSocket = (UINT8) (GetPlatformNumberOfSockets () - 1);
+  } else {
+    *StartSocket = SocketId;
+    *EndSocket = SocketId;
+  }
+}
+
+/**
+ *
+ *
+ *     This function transfer input High low bit to Mask
+ *
+ *     @param[in]   RegVal   - Regval want to set
+ *     @param[in]   Highbit   - (0~63)
+ *     @param[in]   Lowbit    - (0~63)
+ *     @param[in,out]   AndMask   - point value contain output AndMask
+ *     @param[in,out]   OrMask   - point value contain output OrMask
+ *
+ */
+VOID
+IdsGetMask64bits (
+  IN       UINT64 RegVal,
+  IN       UINT8  Highbit,
+  IN       UINT8  Lowbit,
+  IN OUT   UINT64 *AndMask,
+  IN OUT   UINT64 *OrMask
+  )
+{
+  UINT64 Mask;
+
+  if ((Highbit - Lowbit) != 63) {
+    Mask = (((UINT64) 1 << (Highbit - Lowbit + 1)) - 1);
+  } else {
+    Mask = (UINT64) 0xFFFFFFFFFFFFFFFF;
+  }
+  *AndMask = ~(Mask << Lowbit);
+  *OrMask = (RegVal & Mask) << Lowbit;
+}
+/**
+ *
+ *
+ *     This function transfer input High low bit to Mask
+ *
+ *     @param[in]   RegVal   - Regval want to set
+ *     @param[in]   Highbit   - (0~31)
+ *     @param[in]   Lowbit    - (0~31)
+ *     @param[in,out]   AndMask   - point value contain output AndMask
+ *     @param[in,out]   OrMask   - point value contain output OrMask
+ *
+ */
+
+VOID
+IdsGetMask32bits (
+  IN       UINT32 RegVal,
+  IN       UINT8  Highbit,
+  IN       UINT8  Lowbit,
+  IN OUT   UINT32 *AndMask,
+  IN OUT   UINT32 *OrMask
+  )
+{
+  UINT32 Mask;
+
+  if ((Highbit - Lowbit) != 31) {
+    Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
+  } else {
+    Mask = (UINT32) 0xFFFFFFFF;
+  }
+  *AndMask = ~(Mask << Lowbit);
+  *OrMask = (RegVal & Mask) << Lowbit;
+
+}
+/**
+ *
+ *
+ *     This function transfer input High low bit to Mask
+ *
+ *     @param[in]   RegVal   - Regval want to set
+ *     @param[in]   Highbit   - (0~15)
+ *     @param[in]   Lowbit    - (0~15)
+ *     @param[in,out]   AndMask   - point value contain output AndMask
+ *     @param[in,out]   OrMask   - point value contain output OrMask
+ *
+ */
+
+VOID
+IdsGetMask16bits (
+  IN       UINT16 RegVal,
+  IN       UINT8  Highbit,
+  IN       UINT8  Lowbit,
+  IN OUT   UINT32 *AndMask,
+  IN OUT   UINT32 *OrMask
+  )
+{
+  UINT16 Mask;
+
+  if ((Highbit - Lowbit) != 15) {
+    Mask = (((UINT16) 1 << (Highbit - Lowbit + 1)) - 1);
+  } else {
+    Mask = (UINT16) 0xFFFF;
+  }
+  *AndMask = ~(Mask << Lowbit);
+  *OrMask = (RegVal & Mask) << Lowbit;
+}
+
+/**
+ *
+ *
+ *     IdsCheckPciExisit
+ *     Use to check is the PCI device exisit of given address
+ *
+ *     @param[in]   PciAddr   - Given PCI address
+ *     @param[in,out]   StdHeader    - The Pointer of AGESA Header
+ *
+ *     @retval TRUE         The PCI device exisit
+ *     @retval FALSE        The PCI device doesn't exisit
+ *
+ *
+ */
+BOOLEAN
+IdsCheckPciExisit (
+  IN       PCI_ADDR PciAddr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR _pciaddr;
+  UINT32 _pcidata;
+  BOOLEAN status;
+
+  status = FALSE;
+  _pciaddr = PciAddr;
+  _pciaddr.Address.Register = 0;
+  LibAmdPciRead (AccessWidth32, _pciaddr, &_pcidata, StdHeader);
+  if (_pcidata != 0xFFFFFFFF || _pcidata != 0) {
+    status = TRUE;
+  }
+  return status;
+}
+
+/**
+ *
+ *
+ *     This function transfer input High low bit to Mask
+ *
+ *     @param[in,out]   Value   - Regval want to And Or with Mask
+ *     @param[in]   AndMask   - AndMask
+ *     @param[in]   OrMask   - OrMask
+ *
+ */
+
+VOID
+IdsLibDataMaskSet32 (
+  IN OUT   UINT32 *Value,
+  IN       UINT32  AndMask,
+  IN       UINT32  OrMask
+  )
+{
+  *Value &= AndMask;
+  *Value |= OrMask;
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c
new file mode 100644
index 0000000000..02b2ed7be2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c
@@ -0,0 +1,316 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Filecode.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "IdsRegAcc.h"
+
+#define FILECODE PROC_IDS_LIBRARY_IDSREGACC_FILECODE
+
+extern CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[];
+
+/**
+ *
+ *  set the MSR of AP
+ *
+ *  @param[in] PRegMsr  point to REG_MSR
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *
+ **/
+VOID
+IdsRegSetMsrCmnTask (
+  IN       IDS_REG_MSR  *PRegMsr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 value;
+
+  LibAmdMsrRead (PRegMsr->MsrAddr, &value, StdHeader);
+  value &= PRegMsr->AndMask;
+  value |= PRegMsr->OrMask;
+  LibAmdMsrWrite (PRegMsr->MsrAddr, &value, StdHeader);
+}
+
+/**
+ *
+ *
+ *     IDS Common routine for RMW MSR for both ealry & later stage
+ *     This routine can only be used when AP service have been established
+ *
+ *     @param[in]   PMsrReg     Point MSR reg structure, contain TimePoint, Socket, Core,address, andmask, ormask
+ *     @param[in,out]   StdHeader    - The Pointer of AGESA Header
+ *
+ */
+VOID
+IdsRegSetMsr (
+  IN       IDS_REG_MSR *PMsrReg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_TASK ApTask;
+  IDSAPLATETASK IdsLateTask;
+  UINT32 NumberOfCores;
+  UINT8 StartSocket;
+  UINT8 EndSocket;
+  UINT8 Socket;
+  UINT8 StartCore;
+  UINT8 EndCore;
+  UINT8 Core;
+  UINT32 BscCoreNum;
+  UINT32 BscSocket;
+  UINT32 IgnoredModule;
+  UINT32 ApicIdOfCore;
+  AGESA_STATUS IgnoredSts;
+  IDS_REG_AP_SERVICE_TIMEPOINT TimePoint;
+
+  TimePoint = PMsrReg->TimePoint;
+  ASSERT ((TimePoint == IDS_REG_AP_SERVICE_EARLY) ||
+          (TimePoint == IDS_REG_AP_SERVICE_POST) ||
+          (TimePoint == IDS_REG_AP_SERVICE_LATE));
+
+  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts);
+  IdsGetStartEndSocket (PMsrReg->Socket, &StartSocket, &EndSocket);
+  //TaskPtr for both IDS_REG_AP_SERVICE_EARLY, IDS_REG_AP_SERVICE_POST
+  ApTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)IdsRegSetMsrCmnTask;
+  ApTask.ExeFlags = WAIT_FOR_CORE;
+  ApTask.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (IDS_REG_MSR);
+  ApTask.DataTransfer.DataPtr = PMsrReg;
+  ApTask.DataTransfer.DataTransferFlags = 0;
+
+  for (Socket = StartSocket; Socket <= EndSocket; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      if (PMsrReg->Core == IDS_ALL_CORE) {
+        StartCore = 0;
+        EndCore = (UINT8)NumberOfCores - 1;
+      } else {
+        StartCore = PMsrReg->Core;
+        EndCore = PMsrReg->Core;
+      }
+      for (Core = StartCore; (Core <= EndCore) && (Core <= (NumberOfCores - 1)); Core++) {
+        if ((Core == BscCoreNum) && (Socket == BscSocket)) {
+          IdsRegSetMsrCmnTask (PMsrReg, StdHeader);
+        } else {
+          if (IsProcessorPresent (Socket, StdHeader)) {
+            if (TimePoint == IDS_REG_AP_SERVICE_EARLY) {
+              // At early stage, the AP's task has to be called by core 0, not by bsc
+              IdsRunCodeOnCoreEarly (Socket, Core, &ApTask, StdHeader);
+            } else if (TimePoint == IDS_REG_AP_SERVICE_POST) {
+              ApUtilRunCodeOnSocketCore (Socket, Core, &ApTask, StdHeader);
+            } else if (TimePoint == IDS_REG_AP_SERVICE_LATE) {
+              IdsLateTask.ApTask = (PF_IDS_AP_TASK)IdsRegSetMsrCmnTask;
+              IdsLateTask.ApTaskPara = PMsrReg;
+              GetLocalApicIdForCore (Socket, Core, &ApicIdOfCore, StdHeader);
+              IdsAgesaRunFcnOnApLate (ApicIdOfCore, &IdsLateTask, StdHeader);
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/**
+ *
+ *
+ *     IDS Common routine for set Memory bit field using memory sevice
+ *
+ *     @param[in]   PMemReg     Point to MEM reg structure
+ *     @param[in,out]   NBPtr    - The Pointer of NBPtr
+ *
+ */
+
+AGESA_STATUS
+IdsRegSetMemBitField (
+  IN       IDS_REG_MEM *PMemReg,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 CurDct;
+  UINT32 BfType;
+  UINT32 BfIndex;
+  UINT8 HighBit;
+  UINT8 LowBit;
+  UINT32 RegValue;
+  UINT8 Dct;
+  HighBit = 31;
+  LowBit = 0;
+  //Check if current module need set
+  if ((PMemReg->Module == IDS_ALL_MODULE) || (PMemReg->Module == NBPtr->Node)) {
+    //Save Current DCT
+    CurDct = NBPtr->Dct;
+    //Set BfType for MAKE_TSEFO
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      if ((PMemReg->Dct == IDS_ALL_DCT) || (PMemReg->Dct == Dct)) {
+        if (PMemReg->Type == IDS_REG_MEM_NB) {
+          BfType = NB_ACCESS;
+          BfIndex = _FN (PMemReg->Addr.PciAddr.Func, PMemReg->Addr.PciAddr.Offset);
+        } else if (PMemReg->Type == IDS_REG_MEM_PHY) {
+          if ((PMemReg->Addr.Index & 0xFFF00000) == 0x0D000000) {
+            BfType = DCT_PHY_DIRECT;
+            //Dram debug PHY only support 16 bits access
+            HighBit = 15;
+            LowBit = 0;
+          } else {
+            BfType = DCT_PHY_ACCESS;
+          }
+          BfIndex = PMemReg->Addr.Index;
+        } else if (PMemReg->Type == IDS_REG_MEM_EXTRA) {
+          BfType = DCT_EXTRA;
+          BfIndex = PMemReg->Addr.Index;
+        } else {
+          return AGESA_UNSUPPORTED;
+        }
+        MAKE_TSEFO (NBPtr->NBRegTable, BfType, BfIndex, HighBit, LowBit, BFIdsCmnMemReg);
+
+        NBPtr->SwitchDCT (NBPtr, Dct);
+        RegValue = NBPtr->GetBitField (NBPtr, BFIdsCmnMemReg);
+        RegValue &= PMemReg->AndMask;
+        RegValue |= PMemReg->OrMask;
+        NBPtr->SetBitField (NBPtr, BFIdsCmnMemReg, RegValue);
+      }
+    }
+    //Restore DCT
+    NBPtr->SwitchDCT (NBPtr, CurDct);
+  }
+  return AGESA_SUCCESS;
+}
+
+/**
+ *
+ *
+ *     IDS routine for set family specific register
+ *
+ *     @param[in]   PFamReg     Point Famreg structure, contain register define, and type
+ *     @param[in,out]   StdHeader    - The Pointer of AGESA Header
+ *
+ */
+
+VOID
+IdsFamRegAccess (
+  IN       IDS_FAM_REG *PFamReg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_IDS_OPTION RegFamId;
+
+  switch (PFamReg->Type) {
+  case IDS_FAM_REG_TYPE_GMMX:
+    RegFamId = IDS_FAM_REG_GMMX;
+    break;
+  default:
+    RegFamId = IDS_OPTION_END;
+  }
+  if (RegFamId != IDS_OPTION_END) {
+    IdsParseFeatTbl (RegFamId, IdsRegAccessTbl, &PFamReg->Reg, NULL, StdHeader);
+  }
+}
+
+/**
+ * Set PCI indirect registers
+ *
+ *
+ *     @param[in]   PPciIndirectReg     Point to IDS_REG_PCI_INDIRECT structure
+ *     @param[in,out]   StdHeader    - The Pointer of AGESA Header
+ */
+
+VOID
+IdsRegSetPciIndirect (
+  IN       IDS_REG_PCI_INDIRECT *PPciIndirectReg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 IndexOffset;
+  UINT32 IndexValue;
+  UINT32 Value;
+  PCI_ADDR PciIndexPortAddr;
+  PCI_ADDR PciDataPortAddr;
+
+  IndexOffset = LibAmdAccessWidth (PPciIndirectReg->Width);
+  PciIndexPortAddr.AddressValue = PPciIndirectReg->PciAddr;
+  PciDataPortAddr.AddressValue = PPciIndirectReg->PciAddr + IndexOffset;
+  //Read
+  LibAmdPciWrite (PPciIndirectReg->Width, PciIndexPortAddr, &PPciIndirectReg->IndirectRegOff, StdHeader);
+  LibAmdPciRead (PPciIndirectReg->Width, PciDataPortAddr, &Value, StdHeader);
+  //Modify
+  IdsLibDataMaskSet32 (&Value, PPciIndirectReg->AndMask, PPciIndirectReg->OrMask);
+  //Write
+  IndexValue = PPciIndirectReg->IndirectRegOff | PPciIndirectReg->WriteEnBit;
+  LibAmdPciWrite (PPciIndirectReg->Width, PciIndexPortAddr, &IndexValue, StdHeader);
+  LibAmdPciWrite (PPciIndirectReg->Width, PciDataPortAddr, &Value, StdHeader);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h
new file mode 100644
index 0000000000..250eae5f6c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h
@@ -0,0 +1,180 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef _IDSREGACC_H_
+#define _IDSREGACC_H_
+#include "mm.h"
+#include "mn.h"
+///AP service Time Point
+typedef enum {
+  IDS_REG_AP_SERVICE_EARLY,       ///< Amdinitearly
+  IDS_REG_AP_SERVICE_POST,        ///< Amdinitpost
+  IDS_REG_AP_SERVICE_LATE,        ///< After AmdInitPost
+} IDS_REG_AP_SERVICE_TIMEPOINT;
+
+///Structure define for MSR register
+typedef struct _IDS_REG_MSR {
+  IDS_REG_AP_SERVICE_TIMEPOINT TimePoint; ///< TimePoint
+  UINT8 Socket;                           ///< Socket
+  UINT8 Core;                             ///< Core
+  UINT32 MsrAddr;                         ///< Address of MSR Register
+  UINT64 AndMask;                       ///< And Mask
+  UINT64 OrMask;                        ///< Or Mask
+} IDS_REG_MSR;
+
+///Enum for Mem Register access Type
+typedef enum {
+  IDS_REG_MEM_NB,           ///< PCI access
+  IDS_REG_MEM_PHY,          ///< Memory Phy access
+  IDS_REG_MEM_EXTRA,        ///< Memory Extra register access
+  IDS_REG_MEM_END,          ///< End
+} IDS_REG_MEM_ACCESS_TYPE;
+
+///Structure define for Mem register
+typedef struct _IDS_REG_MEM {
+  IDS_REG_MEM_ACCESS_TYPE  Type;    ///< Type
+  UINT8 Module;                     ///< Module
+  UINT8 Dct;                        ///< Dct
+  union {
+    struct {
+      UINT8 Func;                      ///< PCI function
+      UINT16 Offset;                   ///< PCI offset
+    } PciAddr;                         ///< Pci Address
+    UINT32 Index;                      ///< index of indirect access
+  } Addr;                             ///< address
+  UINT32 AndMask;                   ///< And Mask
+  UINT32 OrMask;                    ///< Or Mask
+} IDS_REG_MEM;
+
+///Family register type
+typedef enum {
+  IDS_FAM_REG_TYPE_GMMX,           ///< GMMX register access
+  IDS_FAM_REG_TYPE_END,            ///< End
+} IDS_FAM_REG_TYPE;
+
+///Structure define for GMMX register
+typedef struct _IDS_REG_GMMX {
+  UINT32 Offset;                    ///< Offset of GMMX register
+  UINT32 AndMask;                   ///< And Mask
+  UINT32 OrMask;                    ///< Or Mask
+} IDS_REG_GMMX;
+
+///Structure define for family specific register
+typedef struct _IDS_FAM_REG {
+  IDS_FAM_REG_TYPE Type;           ///< Register type
+  union {
+    IDS_REG_GMMX Gmmx;             ///< GMMX
+  } Reg;
+} IDS_FAM_REG;
+
+///Structure define for PCI indirect register
+typedef struct _IDS_REG_PCI_INDIRECT {
+  ACCESS_WIDTH  Width;        ///< access width
+  UINT32  PciAddr;            ///< PCI address
+  UINT32  IndirectRegOff;     ///< PCI indirect register offset
+  UINT32  WriteEnBit;         ///< Write Enable bit
+  UINT32  AndMask;            ///< And Mask
+  UINT32  OrMask;             ///< Or Mask
+} IDS_REG_PCI_INDIRECT;
+
+VOID
+IdsRegSetMsrCmnTask (
+  IN       IDS_REG_MSR  *PRegMsr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+);
+
+VOID
+IdsRegSetMsr (
+  IN       IDS_REG_MSR *PMsrReg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+);
+
+AGESA_STATUS
+IdsRegSetMemBitField (
+  IN       IDS_REG_MEM *PMemReg,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+);
+
+VOID
+IdsFamRegAccess (
+  IN       IDS_FAM_REG *PFamReg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+);
+
+VOID
+IdsRegSetPciIndirect (
+  IN       IDS_REG_PCI_INDIRECT *PPciIndirectReg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+);
+
+#endif  //_IDSREGACC_H_
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h
new file mode 100644
index 0000000000..39c83f6eb7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h
@@ -0,0 +1,113 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ *  This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *
+ *      Warning: When you enable the IDSOPT_CONTROL_NV_TO_CMOS feature.
+ *      please make the cmos region defined by IDS_OPT_CMOS_REGION_START &
+ *      IDS_OPT_CMOS_REGION_END can be touched between IDS HOOK point
+ *      IDS_CPU_Early_Override and IDS_BEFORE_AP_EARLY_HALT of BSP
+ *
+ *      IDSOPT_CONTROL_NV_TO_CMOS
+ *        IDS_OPT_CMOS_INDEX_PORT
+ *        IDS_OPT_CMOS_DATA_PORT
+ *        IDS_OPT_CMOS_REGION_START
+ *        IDS_OPT_CMOS_REGION_END
+ *
+ *    IDSOPT_TRACING_ENABLED
+ *      IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ *
+ *      IDSOPT_TRACING_CONSOLE_HDTOUT
+ *      IDSOPT_TRACING_CONSOLE_SERIALPORT
+ *        IDSOPT_SERIAL_PORT (default 0x3F8)
+ *      IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ *        IDSOPT_DEBUG_PRINT_IO_PORT (default 0x80)
+ *    IDSOPT_TRACE_BLD_CFG
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *    IDSOPT_DEBUG_CODE_ENABLED
+ *    IDSOPT_IDT_EXCEPTION_TRAP
+ *    IDSOPT_C_OPTIMIZATION_DISABLED
+ *
+ **/
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c
new file mode 100644
index 0000000000..a94ba44db0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c
@@ -0,0 +1,248 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Routines for performance analysis
+ *
+ * Contains AMD AGESA debug macros and functions for performance analysis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ */
+/*****************************************************************************
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "IdsDpHdtout.h"
+#include "heapManager.h"
+#include "cpuFamilyTranslation.h"
+#include "amdlib.h"
+
+#define FILECODE PROC_IDS_PERF_IDSPERF_FILECODE
+/**
+ *
+ *  IDS Performance function for Output to HDT.
+ *
+ *  Invoke communications with the HDT environment to allow the user to issue
+ *  debug commands. If the sign = 0x0, HDT Control Register will be initialized to
+ *  catch the special I/O for HDT_OUT. Otherwise, it will inform HDT script
+ *  function what is meaning for the value to output to HDT.
+ *
+ *  @param[in] Command    HDT_OUT Command.
+ *  @param[in] Data       The Data to output to HDT.
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+#define HDTOUT_COMMAND        0x99cc
+#define HDTOUT_TIME_ANALYSE   (0xD0BF0000ul | HDTOUT_COMMAND)
+
+VOID
+IdsPerfHdtOut (
+  IN       UINT16 Command,
+  IN       UINT32 Data,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IdsOutPort (HDTOUT_TIME_ANALYSE, Data, 0);
+}
+
+/**
+ *
+ *  Get Ids Performance analysis table pointer in the AGESA Heap.
+ *
+ *  @param[in] LineInFile  ((FILECODE) shift 16)+ Line number
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of Performance analysis Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of Performance analysis Table.
+ *  @retval AGESA_UNSUPPORTED   Get an exclude testpoint
+ *
+ **/
+AGESA_STATUS
+IdsPerfTimestamp (
+  IN       UINT32 LineInFile,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  UINT32 Index;
+  TP_Perf_STRUCT *PerfTableEntry;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  UINT64 CurrentTsc;
+
+  //if heap is not ready yet, don't invoke locate buffer, or else will cause event log & locate heap dead loop
+  if (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET ) {
+    LibAmdMsrRead (TSC, &CurrentTsc, StdHeader);
+
+    LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
+    LocateHeapStructPtr.BufferPtr = NULL;
+    status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+    if (status == AGESA_SUCCESS) {
+      PerfTableEntry = (TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr);
+    } else {
+      AllocHeapParams.RequestedBufferSize = sizeof (TP_Perf_STRUCT);
+      AllocHeapParams.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
+      AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+      status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+      if (status != AGESA_SUCCESS) {
+        return status;
+      }
+      PerfTableEntry = (TP_Perf_STRUCT *) (AllocHeapParams.BufferPtr);
+      LibAmdMemFill (PerfTableEntry, 0, sizeof (TP_Perf_STRUCT), StdHeader);
+      PerfTableEntry->Signature = 'EMIT';
+    }
+
+    Index = PerfTableEntry ->Index;
+
+    PerfTableEntry ->TP[Index].LineInFile = LineInFile;
+    PerfTableEntry ->TP[Index].StartTsc = CurrentTsc;
+    PerfTableEntry ->Index = ++Index;
+  }
+  return AGESA_SUCCESS;
+}
+
+typedef struct _PERFREGBACKUP {
+  UINT64 SMsr;
+  UINT32 Dr0Reg;
+  UINT32 Dr7Reg;
+  UINT32 Cr4Reg;
+} PERFREGBACKUP;
+
+VOID
+IdsPerfSaveReg (
+  IN OUT   PERFREGBACKUP * perfreg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+
+  LibAmdReadCpuReg (DR0_REG, &perfreg->Dr0Reg);
+
+  LibAmdReadCpuReg (DR7_REG, &perfreg->Dr7Reg);
+
+  LibAmdReadCpuReg (CR4_REG, &perfreg->Cr4Reg);
+}
+
+VOID
+IdsPerfRestoreReg (
+  IN       PERFREGBACKUP * perfreg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+
+  LibAmdWriteCpuReg (DR0_REG, perfreg->Dr0Reg);
+
+  LibAmdWriteCpuReg (DR7_REG, perfreg->Dr7Reg);
+
+  LibAmdWriteCpuReg (CR4_REG, perfreg->Cr4Reg);
+}
+/**
+ * Output Test Point function .
+ *
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
+ *  @retval AGESA_ERROR         Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
+ *
+ **/
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  UINT32 TscRateInMhz;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PERFREGBACKUP PerfReg;
+  UINT32 CR4reg;
+  UINT64 SMsr;
+
+  LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status != AGESA_SUCCESS) {
+    return status;
+  }
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
+  ((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
+  if (AmdIdsHdtOutSupport () == FALSE) {
+  //Init break point
+    IdsPerfSaveReg (&PerfReg, StdHeader);
+
+    SMsr |= 1;
+
+    LibAmdWriteCpuReg (DR2_REG, 0x99cc);
+    LibAmdWriteCpuReg (DR7_REG, 0x02000420);
+
+    LibAmdReadCpuReg (CR4_REG, &CR4reg);
+    LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
+
+    IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader);
+    IdsPerfRestoreReg (&PerfReg, StdHeader);
+  }
+  return status;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c
new file mode 100644
index 0000000000..464dde6322
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c
@@ -0,0 +1,172 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * ma.c
+ *
+ * Initializes ARDK Block
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_ARDK_MA_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This is the default return function of the ARDK block. The function always
+ *    returns   AGESA_UNSUPPORTED
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID        Socket number
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_UNSUPPORTED  AGESA status indicating that default is unsupported
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgDef (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  return AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function returns the rank type map of a channel.
+ *
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          UINT16 - The map of rank type.
+ *
+ */
+UINT16
+MemAGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  UINT8 i;
+  UINT16 DIMMRankType;
+
+  DIMMRankType = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if (CurrentChannel->MCTPtr->Status[SbLrdimms]) {
+      if ((CurrentChannel->LrDimmPresent & (UINT8) 1 << i) != 0) {
+        DIMMRankType |= (UINT16) 1 << (i << 2);
+      }
+    } else {
+      if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
+        if (i < 2) {
+          DIMMRankType |= (UINT16) 4 << (i << 2);
+        }
+      } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
+        DIMMRankType |= (UINT16) 2 << (i << 2);
+      } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
+        DIMMRankType |= (UINT16) 1 << (i << 2);
+      }
+    }
+  }
+  return DIMMRankType;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c
new file mode 100644
index 0000000000..29b8cc4e28
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -0,0 +1,238 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfchi.c
+ *
+ * Feature Channel interleaving support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Chintlv)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfchi.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_ (0x10000ul >> 10)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   MemFInterleaveChannels:
+ *
+ *  Applies DIMM channel interleaving if enabled, if not ganged mode, and
+ *  there are valid dimms in both channels.  Called once per Node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveChannels (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 DramBase;
+  UINT32 DctSelBase;
+  UINT32 HoleSize;
+  UINT32 HoleBase;
+  UINT32 HoleOffset;
+  UINT32 Dct0Size;
+  UINT32 Dct1Size;
+  UINT32 SmallerDct;
+  UINT8 DctSelIntLvAddr;
+  UINT8 DctSelHi;
+  UINT8 DctSelHiRngEn;
+  UINT32 HoleValid;
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+
+  DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr;
+  if (RefPtr->EnableChannelIntlv) {
+    HoleSize = 0;
+    HoleBase = 0;
+    if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
+      // HoleBase scaled from [47:16] to [47:26]
+      HoleBase = RefPtr->HoleBase >> 10;
+      HoleSize = _4GB_ - HoleBase;
+    }
+
+    MCTPtr = NBPtr->MCTPtr;
+
+    HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid);
+    if ((!MCTPtr->GangedMode) &&
+        (MCTPtr->DctData[0].Timings.DctMemSize != 0) &&
+        (MCTPtr->DctData[1].Timings.DctMemSize != 0)) {
+      // DramBase scaled [47:16] to [47:26]
+      DramBase = MCTPtr->NodeSysBase >> 10;
+      // Scale NodeSysLimit [47:16] to [47:26]
+      Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10;
+      Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset);
+      if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) {
+        Dct0Size -= HoleSize;
+      }
+      if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) {
+        Dct1Size -= HoleSize;
+      }
+      Dct1Size -= Dct0Size;
+      Dct0Size -= DramBase;
+
+       // Select the bigger size DCT to put in DctSelHi
+      DctSelHiRngEn = 1;
+      DctSelHi = 0;
+      SmallerDct = Dct1Size;
+      if (Dct1Size == Dct0Size) {
+        SmallerDct = 0;
+        DctSelHiRngEn = 0;
+      } else if (Dct1Size > Dct0Size) {
+        SmallerDct = Dct0Size;
+        DctSelHi = 1;
+      }
+
+      if (SmallerDct != 0) {
+        DctSelBase = (SmallerDct * 2) + DramBase;
+      } else {
+        DctSelBase = 0;
+      }
+      if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) {
+        DctSelBase += HoleSize;
+      }
+      IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader));
+      NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1);
+      NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn);
+      NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi);
+      NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr);
+      NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1);
+
+       // DctSelBaseOffset = DctSelBaseAddr - Interleaved region
+      NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct);
+
+       // Adjust DramHoleOffset
+      if (HoleValid != 0) {
+        HoleOffset = DramBase;
+        if ((DctSelBase < HoleBase) && (DctSelBase != 0)) {
+          HoleOffset += (DctSelBase - DramBase) >> 1;
+        }
+        HoleOffset += HoleSize;
+        NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3);
+      }
+    } else {
+      //
+      // Channel Interleaving is requested but cannot be enabled
+      //
+      PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, MCTPtr);
+    }
+
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h
new file mode 100644
index 0000000000..a9cde96d2b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfchi.h
+ *
+ * Feature channel interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCHI_H_
+#define _MFCHI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveChannels (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFCHI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c
new file mode 100644
index 0000000000..90f15b4652
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c
@@ -0,0 +1,412 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfCrat.c
+ *
+ * Feature CRAT table support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mfCrat.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE (0xF095)
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define FOURGB 0x010000ul
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+CRAT_MEMORY_AFFINITY_INFO_ENTRY
+STATIC
+*MakeMemAffinityInfoEntry (
+  IN UINT8                            Domain,
+  IN UINT32                           Base,
+  IN UINT32                           Size,
+  IN CRAT_MEMORY_AFFINITY_INFO_ENTRY  *BufferLocPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFCratSupport (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets CRAT memory affinity info and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFCratSupport (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8    Node;
+  UINT32   DramLeng;
+  UINT32   DramBase;
+  UINT32   DramLimit;
+  UINT8    DramRngRE;
+  UINT8    DramRngWE;
+  UINT8    Domain;
+  UINT8    DomainForBase640K;
+  UINT32   ValueLimit;
+  UINT32   ValueTOM;
+  UINT64   MsrValue;
+  BOOLEAN  isModified;
+  UINT8    MaxNumOfMemAffinityInfoEntries;
+  UINT8    NumOfMemAffinityInfoEntries;
+  UINT32   TopOfMemoryAbove4Gb;
+  CRAT_MEMORY_AFFINITY_INFO_HEADER *MemAffinityInfoHeaderPtr;
+  CRAT_MEMORY_AFFINITY_INFO_ENTRY *MemAffinityInfoEntryPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  MEM_NB_BLOCK    *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT      *MCTPtr;
+  MEM_SHARED_DATA *SharedPtr;
+
+  NBPtr     = MemMainPtr->NBPtr;
+  MemPtr    = MemMainPtr->MemPtr;
+  MCTPtr    = NBPtr->MCTPtr;
+  SharedPtr = NBPtr->SharedPtr;
+
+  // The maximum number of entries take the following two factors into consideration
+  // 1. The entry for conventional memory less than 640k
+  // 2. The memory hole below 4G may divide the memory range across the hole into two
+  MaxNumOfMemAffinityInfoEntries = NBPtr->NodeCount + 2;
+
+  // Allocate heap for CRAT memory affinity info entry
+  AllocHeapParams.RequestedBufferSize = MaxNumOfMemAffinityInfoEntries * sizeof (CRAT_MEMORY_AFFINITY_INFO_ENTRY) +
+                                        sizeof (CRAT_MEMORY_AFFINITY_INFO_HEADER);
+  AllocHeapParams.BufferHandle = AMD_MEM_CRAT_INFO_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    // Could not allocate heap for CRAT memory affinity info
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT (FALSE);
+    return FALSE;
+  }
+
+  MemAffinityInfoHeaderPtr = (CRAT_MEMORY_AFFINITY_INFO_HEADER *) ((UINT8 *) (AllocHeapParams.BufferPtr));
+  MemAffinityInfoHeaderPtr ++;
+  MemAffinityInfoEntryPtr  = (CRAT_MEMORY_AFFINITY_INFO_ENTRY *) MemAffinityInfoHeaderPtr;
+  MemAffinityInfoHeaderPtr --;
+
+  NumOfMemAffinityInfoEntries = 0;
+  DomainForBase640K = 0xFF;
+
+  for (Node = 0; Node < NBPtr->NodeCount; Node++) {
+    // FALSE means normal update procedure
+    isModified = FALSE;
+    // Get DRAM Base Address
+    DramBase = MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node);
+    DramRngRE = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramRngRE0 + Node);
+    DramRngWE = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramRngWE0 + Node);
+    if ((DramRngRE == 0) || (DramRngWE == 0)) {
+      // 0:1 set if memory range enabled
+      // Not set, so we don't have an enabled range
+      // Proceed to next Base register
+      continue;
+    }
+
+    // Get DRAM Limit
+    DramLimit = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + Node);
+    if (DramLimit == 0xFFFFFFFF) {
+      // Node not installed(all FF's)?
+      // Proceed to next Base register
+      continue;
+    }
+
+    // Node ID is assigned to Domain
+    Domain = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramRngDstNode0 + Node);
+    // Get DRAM Limit addr [47:24]
+    DramLimit = ((((MemNGetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node) & 0xFF) << 16) | DramLimit >> 16));
+    // Add 1 for potential length
+    DramLimit++;
+    DramLimit <<= 8;
+
+    // Get DRAM Base Address
+    // Get DRAM Base Base value [47:24]
+    DramBase = (((MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) & 0xFF) << 24) | (DramBase >> 8) & 0xFFFFFF00);
+    // Subtract base from limit to get length
+    DramLeng = DramLimit - DramBase;
+
+    // Leave hole for conventional memory (Less than 640K).  It must be on CPU 0.
+    if (DramBase == 0) {
+      if (DomainForBase640K == 0xFF) {
+        // It is the first time that the range start at 0.
+        // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K
+        MemAffinityInfoEntryPtr = MakeMemAffinityInfoEntry (
+                                    Domain,
+                                    0,              // Base = 0
+                                    0xA0000 >> 16,  // Put it into format used in DRAM regs..
+                                    MemAffinityInfoEntryPtr
+                                    );
+        NumOfMemAffinityInfoEntries ++;
+
+        // Add 1MB, so range = 1MB to Top of Region
+        DramBase += 0x10;
+        // Also subtract 1MB from the length
+        DramLeng -= 0x10;
+        // Save Domain number for memory Less than 640K
+        DomainForBase640K = Domain;
+      } else {
+        // If No, there are more than one memory range less than 640K, it should that
+        // node interleaving is enabled. All nodes have the same memory ranges
+        // and all cores in these nodes belong to the same domain.
+        Domain = DomainForBase640K;
+        break;
+      }
+    }
+    LibAmdMsrRead (TOP_MEM, &MsrValue, &MemPtr->StdHeader);
+    // Save it in 39:24 format
+    ValueTOM   = (UINT32) MsrValue >> 16;
+    // We need to know how large region is
+    ValueLimit = DramBase + DramLeng;
+
+    LibAmdMsrRead (SYS_CFG, &MsrValue, &MemPtr->StdHeader);
+    if ((MsrValue & BIT21) != 0) {
+      LibAmdMsrRead (TOP_MEM2, &MsrValue, &MemPtr->StdHeader);
+      // Save it in 47:16 format
+      TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16);
+    } else {
+      TopOfMemoryAbove4Gb = 0xFFFFFFFF;
+    }
+
+    //  SPECIAL CASES:
+    //
+    //  Several conditions require that we process the values of the memory range differently.
+    //  Here are descriptions of the corner cases.
+    //
+    //  1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole).  For this case,
+    //     the range must be truncated to end at TOM.
+    //  *******************************            *******************************
+    //  *                    *        *      ->    *                             *
+    //  *******************************            *******************************
+    //  2                    TOM      4            2                             TOM
+    //
+    //  2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB.  This is handled by changing the
+    //     start base to 4GB.
+    //          ****************                        **********
+    //          *     *        *      ->                *        *
+    //          ****************                        **********
+    //  TOM     3.8   4        6            TOM   3.8   4        6
+    //
+    //  3. Memory range starts below TOM, ends above 4GB.  For this case, the range must be truncated
+    //     to end at TOM.  Note that this scenario creates two ranges, as the second comparison below
+    //     will find that it ends above 4GB since base and limit have been restored after first truncation,
+    //     and a second range will be written based at 4GB ending at original end address.
+    //  *******************************            ****************          **********
+    //  *              *     *        *      ->    *              *          *        *
+    //  *******************************            ****************          **********
+    //  2              TOM   4        6            2              TOM        4        6
+    //
+    //  4. Memory range starts above TOM, ends below or equal to 4GB.  This invalid range should simply
+    //     be ignored.
+    //          *******
+    //          *     *      ->    < NULL >
+    //          *******
+    //  TOM     3.8   4
+    //
+    //  5. Memory range starts below TOM2, and ends beyond TOM2.  This range must be truncated to TOM2.
+    //  ************************         *******************************
+    //  *              *       *   ->    *                             *
+    //  ************************         *******************************
+    //  768          TOM2   1024         768                        TOM2
+    //
+    //  6. Memory range starts above TOM2.  This invalid range should simply be ignored.
+    //          ********************
+    //          *                  *    ->    < NULL >
+    //          ********************
+    //  TOM2    1024            1280
+
+    if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM))
+        || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) {
+      //   TRUNCATE LOW!!! Shrink entry below TOM...
+      //   Base = DramBase, Size = TOM - DramBase
+      MemAffinityInfoEntryPtr = MakeMemAffinityInfoEntry (Domain, DramBase, (ValueTOM - DramBase), MemAffinityInfoEntryPtr);
+      NumOfMemAffinityInfoEntries ++;
+      isModified = TRUE;
+    }
+
+    if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) {
+      //   TRUNCATE HIGH!!! Shrink entry above 4GB...
+      //   Size = Base + Size - 4GB, Base = 4GB
+      MemAffinityInfoEntryPtr = MakeMemAffinityInfoEntry (Domain, FOURGB, (DramLeng + DramBase - FOURGB), MemAffinityInfoEntryPtr);
+      NumOfMemAffinityInfoEntries ++;
+      isModified = TRUE;
+    }
+
+    if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) {
+      //   IGNORE!!!  Entry located entirely within memory hole
+      isModified = TRUE;
+    }
+
+    if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) {
+      //   Truncate to TOM2
+      //   Base = DramBase, Size = TOM2 - DramBase
+      MemAffinityInfoEntryPtr = MakeMemAffinityInfoEntry (Domain, DramBase, (TopOfMemoryAbove4Gb - DramBase), MemAffinityInfoEntryPtr);
+      NumOfMemAffinityInfoEntries ++;
+      isModified = TRUE;
+    }
+
+    if (DramBase >= TopOfMemoryAbove4Gb) {
+      //   IGNORE!!!  Entry located entirely above TOM2
+      isModified = TRUE;
+    }
+
+    //    If special range(isModified), we are done.
+    //    If not, finally write the memory entry.
+    if (isModified == FALSE) {
+      // Finally write the memory entry.
+      MemAffinityInfoEntryPtr = MakeMemAffinityInfoEntry (Domain, DramBase, DramLeng, MemAffinityInfoEntryPtr);
+      NumOfMemAffinityInfoEntries ++;
+    }
+  }
+
+  MemAffinityInfoHeaderPtr->NumOfMemAffinityInfoEntries = NumOfMemAffinityInfoEntries;
+  MemAffinityInfoHeaderPtr->MemoryWidth = NBPtr->MemNGetMemoryWidth (NBPtr);
+
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will add Memory entry.
+ *
+ *  Parameters:
+ *    @param[in]  Domain               Proximity Domain
+ *    @param[in]  Base                  Memory Base
+ *    @param[in]  Size                  Memory Size
+ *    @param[in]  BufferLocPtr          Point to the address of buffer
+ *
+ *    @retval       CRAT_MEMORY_AFFINITY_INFO_ENTRY * (new buffer location ptr)
+ */
+CRAT_MEMORY_AFFINITY_INFO_ENTRY
+STATIC
+*MakeMemAffinityInfoEntry (
+  IN  UINT8                             Domain,
+  IN  UINT32                            Base,
+  IN  UINT32                            Size,
+  IN  CRAT_MEMORY_AFFINITY_INFO_ENTRY   *BufferLocPtr
+  )
+{
+  BufferLocPtr->Domain = Domain;
+  BufferLocPtr->BaseAddressLow = Base << 16;
+  BufferLocPtr->BaseAddressHigh = Base >> 16;
+  BufferLocPtr->LengthLow = Size << 16;
+  BufferLocPtr->LengthHigh = Size >> 16;
+  BufferLocPtr ++;
+
+  return BufferLocPtr;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.h
new file mode 100644
index 0000000000..0fb24e3011
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.h
@@ -0,0 +1,115 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfCrat.h
+ *
+ * Feature CRAT table support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCRAT_H_
+#define _MFCRAT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// CRAT Memory Affinity Info Header
+typedef struct {
+  UINT8                 NumOfMemAffinityInfoEntries;  ///< Integer that represents the proximity domain to
+  UINT32                MemoryWidth;                  ///< Specifies the number of parallel bits of the memory interface
+} CRAT_MEMORY_AFFINITY_INFO_HEADER;
+
+/// CRAT Memory Affinity Info Entry
+typedef struct {
+  UINT8                 Domain;                 ///< Integer that represents the proximity domain to
+                                                ///< which the memory belongs
+  UINT32                BaseAddressLow;         ///< Low 32Bits of the Base Address of the memory range
+  UINT32                BaseAddressHigh;        ///< High 32Bits of the Base Address of the memory range
+  UINT32                LengthLow;              ///< Low 32Bits of the length of the memory range
+  UINT32                LengthHigh;             ///< High 32Bits of the length of the memory range
+} CRAT_MEMORY_AFFINITY_INFO_ENTRY;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif  /* _MFCRAT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c
new file mode 100644
index 0000000000..3dd2e1720d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -0,0 +1,382 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfcsi.c
+ *
+ * Feature bank interleaving support (AKA Chip Select Interleaving )
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Csintlv)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+/* This file contains functions for Chip Select interleaving */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mfcsi.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemFDctInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+CsIntSwap (
+  IN OUT   UINT32 *BaseMaskRegPtr,
+  IN       UINT8 EnChipSels,
+  IN       UINT8 LoBit,
+  IN       UINT8 HiBit
+  );
+
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function Applies DIMM bank (chip-select) interleaving if enabled
+ *      and if all criteria are met.  Interleaves chip-selects on page boundaries.
+ *      This function calls subfunctions that sets up CS interleaving on multiple Sockets
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN RetFlag;
+
+  ASSERT (NBPtr != NULL);
+
+  RetFlag = FALSE;
+  if (NBPtr->RefPtr->EnableBankIntlv) {
+    if (NBPtr->MCTPtr->NodeMemSize) {
+      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+        NBPtr->SwitchDCT (NBPtr, Dct);
+        RetFlag |= MemFDctInterleaveBanks (NBPtr);
+      }
+    }
+  }
+  return RetFlag;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function checks if bank interleaving has been enabled or not. If yes, it will
+ *     undo bank interleaving. Otherwise, it does nothing.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Bank interleaving has been enabled.
+ *     @return          FALSE - Bank interleaving has not been enabled.
+ */
+
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Cs;
+  UINT8 Dct;
+  UINT32 CSMask;
+  BOOLEAN CSIntlvEnabled;
+  BOOLEAN RetFlag;
+
+  ASSERT (NBPtr != NULL);
+
+  RetFlag = FALSE;
+
+  if (NBPtr->RefPtr->EnableBankIntlv) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize) {
+        CSIntlvEnabled = FALSE;
+        for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
+          if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
+            CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
+            if (((CSMask >> 5) & 0x1FF) != 0x1FF) {
+              CSIntlvEnabled = TRUE;
+              break;
+            }
+          }
+        }
+        if (CSIntlvEnabled) {
+          MemFDctInterleaveBanks (NBPtr);
+          RetFlag = TRUE;
+        }
+      }
+    }
+  }
+  return RetFlag;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function Applies DIMM bank (chip-select) interleaving if enabled
+ *      and if all criteria are met.  Interleaves chip-selects on page boundaries.
+ *      This function is run once per Socket
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Register bits have been swapped.
+ *     @return          FALSE - Register bits have not been swapped.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemFDctInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Cs;
+  UINT8 EnChipSels;
+  UINT8 BankEncd;
+  UINT8 BankEncd0;
+  UINT8 i;
+  UINT8 j;
+  UINT32 BankAddrReg;
+  UINT32 BaseRegS0;
+  UINT32 BaseRegS1;
+  UINT32 MaskReg;
+  UINT8 Offset;
+  UINT8 Dct;
+
+  ASSERT (NBPtr != NULL);
+
+  Dct = NBPtr->Dct;
+
+  // Check if CS interleaving can be enabled
+  EnChipSels = 0;
+  BankEncd0 = 0xFF;
+  Offset = 0;
+  for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
+    if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 3) != 0) {
+      BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg);
+      BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF);
+      if (BankEncd0 == 0xFF) {
+        BankEncd0 = BankEncd;
+      } else if (BankEncd0 != BankEncd) {
+        break;
+      }
+      if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
+        EnChipSels++;
+      }
+    }
+  }
+
+  // Swap Dram Base/Mask Addr to enable CS interleaving
+  if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) {
+    NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j);
+    // Family specific CS interleaving low address adjustment
+    NBPtr->FamilySpecificHook[AdjustCSIntLvLowAddr] (NBPtr, &i);
+
+    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+      i++;
+      j++;
+    }
+
+    for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) {
+      //
+      // LRDIMMS - Add an offset to the bit positions specified based on D18F2x[6C:60]_dct[1:0][RankDef] as follows:
+      //    RankDef=0xb: 0 RankDef=10b: 1 RankDef=11b: 2
+      //    Using RankMult information:  Lo/HiBit <<= (Mult >> 1)
+      //
+      if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+        Offset = ((NBPtr->ChannelPtr->LrDimmRankMult[Cs >> 1]) >> 1);
+      }
+      BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs);
+      BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1);
+      if (((BaseRegS0 | BaseRegS1) & 1) != 0) {
+        // Swap Mask register bits
+        MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
+        CsIntSwap (&MaskReg, EnChipSels, (i + Offset), (j + Offset));
+        NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg);
+
+        // Swap Base register bits
+        CsIntSwap (&BaseRegS0, EnChipSels, (i + Offset), (j + Offset));
+        NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0);
+        CsIntSwap (&BaseRegS1, EnChipSels, (i + Offset), (j + Offset));
+        NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1);
+      }
+    }
+    //
+    // Bank Interleaving is requested and has been enabled as well
+    //
+    NBPtr->MCTPtr->DctData[Dct].BkIntDis = FALSE;
+    return TRUE;
+  } else {
+    //
+    // Bank Interleaving is requested but cannot be enabled
+    //
+    PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    NBPtr->MCTPtr->DctData[Dct].BkIntDis = TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This supporting function swaps Chip selects
+ *
+ *     @param[in,out]  *BaseMaskRegPtr   - Pointer to the Mask Register
+ *     @param[in]      *EnChipSels    - Chip Selects to Enable
+ *     @param[in]      *LoBit         - Lowest Bit
+ *     @param[in]      *HiBit         - Highest Bit
+ *
+ *
+ */
+
+VOID
+STATIC
+CsIntSwap (
+  IN OUT   UINT32 *BaseMaskRegPtr,
+  IN       UINT8 EnChipSels,
+  IN       UINT8 LoBit,
+  IN       UINT8 HiBit
+  )
+{
+  UINT8 BitDelta;
+  UINT32 TempHi;
+  UINT32 TempLo;
+  UINT32 AddrLoMask;
+  UINT32 AddrHiMask;
+
+  ASSERT (BaseMaskRegPtr != NULL);
+  ASSERT (HiBit > LoBit);
+
+  BitDelta = HiBit - LoBit;
+  AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit;
+  AddrHiMask = AddrLoMask << BitDelta;
+
+  TempHi = TempLo = *BaseMaskRegPtr;
+  TempLo &= AddrLoMask;
+  TempLo <<= BitDelta;     // move lower bits to upper bit position
+  TempHi &= AddrHiMask;
+  TempHi >>= BitDelta;     // move upper bits to lower bit position
+
+  *BaseMaskRegPtr &= ~AddrLoMask;
+  *BaseMaskRegPtr &= ~AddrHiMask;
+  *BaseMaskRegPtr |= TempLo | TempHi;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h
new file mode 100644
index 0000000000..9adc2dbf9c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfcsi.h
+ *
+ * Memory Controller
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCSI_H_
+#define _MFCSI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFCSI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
new file mode 100644
index 0000000000..213c3ccff6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
@@ -0,0 +1,677 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfDMI.c
+ *
+ * Memory DMI table support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 64954 $ @e \$Date: 2012-02-03 03:04:45 -0600 (Fri, 03 Feb 2012) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define MAX_DCTS_PER_DIE 2
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets DDR3 DMI information from SPD buffer and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8  i;
+  UINT8  Dimm;
+  UINT8  Socket;
+  UINT8  NodeId;
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT8  temp;
+  UINT8  MaxDimms;
+  UINT8  DimmIndex;
+  UINT8  MaxChannelsPerSocket;
+  UINT8  MaxDimmsPerChannel;
+  UINT8  FormFactor;
+  UINT16 TotalWidth;
+  UINT16 Capacity;
+  UINT16 Width;
+  UINT16 Rank;
+  UINT16 BusWidth;
+  UINT64 ManufacturerIdCode;
+  UINT32 MaxSockets;
+  UINT32 Address;
+  UINT32 TotalSize;
+  UINT32 DimmSize;
+  UINT64 AddrValue;
+  UINT64 DctMemBase;
+  UINT64 NodeMemBase;
+  UINT64 SysMemSize;
+  INT32  MTB_ps;
+  INT32  FTB_ps;
+  INT32  Value32;
+  BOOLEAN DctInterleaveEnabled;
+  BOOLEAN NodeInterleaveEnabled;
+
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DMI_INFO *DmiTable;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SpdDataStructure;
+
+  NBPtr = MemMainPtr->NBPtr;
+  MemPtr = MemMainPtr->MemPtr;
+  SpdDataStructure = MemPtr->SpdDataStructure;
+  MCTPtr = NBPtr->MCTPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Initialize local variables
+  MaxDimms = 0;
+  TotalSize = 0;
+  NodeMemBase = 0;
+  SysMemSize = 0;
+
+  AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader);
+
+  ASSERT (NBPtr != NULL);
+
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
+      temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      MaxDimms = MaxDimms + temp;
+    }
+  }
+
+  // Allocate heap for memory DMI table 16, 17, 19, 20
+  AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 6 + sizeof (DMI_T17_MEMORY_TYPE);
+
+  AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3
+    return FALSE;
+  }
+
+  DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE));
+  *((UINT8 *) (AllocHeapParams.BufferPtr)) = MaxDimms;          // Number of memory devices
+  *((UINT8 *) (AllocHeapParams.BufferPtr) + 1) = 0;             // For Type Detail
+  *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 6)) = Ddr3MemType;  // Memory type
+
+  // Calculate the total memory size in the system
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    SysMemSize += (NBPtr[Socket].MCTPtr->NodeMemSize << 6);
+  }
+  //
+  // Gather memory DMI info
+  //
+  DimmIndex = 0;
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
+    NodeInterleaveEnabled = (NBPtr[Socket].GetBitField (&NBPtr[Socket], BFDramIntlvEn) == 0) ? FALSE : TRUE;
+    DctInterleaveEnabled = (NBPtr[Socket].GetBitField (&NBPtr[Socket], BFDctSelIntLvEn) == 0) ? FALSE : TRUE;
+    DctMemBase = 0;
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      //
+      // Get Node number and Dct number for this channel
+      //
+      ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
+      NodeId = ChannelPtr->MCTPtr->NodeId;
+      Dct = ChannelPtr->Dct;
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
+        DmiTable[DimmIndex].TotalWidth = 0xFFFF;
+        DmiTable[DimmIndex].DataWidth = 0xFFFF;
+        DmiTable[DimmIndex].MemorySize = 0;
+        DmiTable[DimmIndex].Speed = 0;
+        DmiTable[DimmIndex].ManufacturerIdCode = 0;
+        DmiTable[DimmIndex].Attributes = 0;
+        DmiTable[DimmIndex].StartingAddr = 0;
+        DmiTable[DimmIndex].EndingAddr = 0;
+        DmiTable[DimmIndex].DimmPresent = 0;
+        DmiTable[DimmIndex].Socket = Socket;
+        DmiTable[DimmIndex].Channel = Channel;
+        DmiTable[DimmIndex].Dimm = Dimm;
+        DmiTable[DimmIndex].ConfigSpeed = 0;
+        DmiTable[DimmIndex].ExtSize = 0;
+        DmiTable[DimmIndex].ExtStartingAddr = 0;
+        DmiTable[DimmIndex].ExtEndingAddr = 0;
+        DmiTable[DimmIndex].FormFactor = UnknowFormFactor;
+
+        for (i = 0; i < 4; i++) {
+          DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
+        }
+
+        for (i = 0; i < 18; i++) {
+          DmiTable[DimmIndex].PartNumber[i] = 0x0;
+        }
+
+        if (SpdDataStructure[DimmIndex].DimmPresent) {
+          // Total Width (offset 08h) & Data Width (offset 0Ah)
+          TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8];
+          if ((TotalWidth & 0x18) == 0) {
+            // non ECC
+            if ((TotalWidth & 0x07) == 0) {
+              DmiTable[DimmIndex].TotalWidth = 8;           // 8 bits
+            } else if ((TotalWidth & 0x07) == 1) {
+              DmiTable[DimmIndex].TotalWidth  = 16;         // 16 bits
+            } else if ((TotalWidth & 0x07) == 2) {
+              DmiTable[DimmIndex].TotalWidth  = 32;         // 32 bits
+            } else if ((TotalWidth & 0x07) == 3) {
+              DmiTable[DimmIndex].TotalWidth  = 64;         // 64 bits
+            }
+            DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ;
+          } else {
+            // ECC
+            if ((TotalWidth & 0x07) == 0) {
+              DmiTable[DimmIndex].TotalWidth  = 8 + 8;      // 8 bits
+            } else if ((TotalWidth & 0x07) == 1) {
+              DmiTable[DimmIndex].TotalWidth = 16 + 8;      // 16 bits
+            } else if ((TotalWidth & 0x07) == 2) {
+              DmiTable[DimmIndex].TotalWidth  = 32 + 8;     // 32 bits
+            } else if ((TotalWidth & 0x07) == 3) {
+              DmiTable[DimmIndex].TotalWidth  = 64 + 8;     // 64 bits
+            }
+            DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8;
+          }
+
+          // Memory Size (offset 0Ch)
+          Capacity = 0;
+          BusWidth = 0;
+          Width = 0;
+          Rank = 0;
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[4];
+          if ((temp & 0x0F) == 0) {
+            Capacity = 0x0100;                              // 256M
+          } else if ((temp & 0x0F) == 1) {
+            Capacity = 0x0200;                              // 512M
+          } else if ((temp & 0x0F) == 2) {
+            Capacity = 0x0400;                              // 1G
+          } else if ((temp & 0x0F) == 3) {
+            Capacity = 0x0800;                              // 2G
+          } else if ((temp & 0x0F) == 4) {
+            Capacity = 0x1000;                              // 4G
+          } else if ((temp & 0x0F) == 5) {
+            Capacity = 0x2000;                              // 8G
+          } else if ((temp & 0x0F) == 6) {
+            Capacity = 0x4000;                              // 16G
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[8];
+          if ((temp & 0x07) == 0) {
+            BusWidth = 8;                                   // 8 bits
+          } else if ((temp & 0x07) == 1) {
+            BusWidth = 16;                                  // 16 bits
+          } else if ((temp & 0x07) == 2) {
+            BusWidth = 32;                                  // 32 bits
+          } else if ((temp & 0x07) == 3) {
+            BusWidth = 64;                                  // 64 bits
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
+          if ((temp & 0x07) == 0) {
+            Width = 4;                                      // 4 bits
+          } else if ((temp & 0x07) == 1) {
+            Width = 8;                                      // 8 bits
+          } else if ((temp & 0x07) == 2) {
+            Width = 16;                                     // 16 bits
+          } else if ((temp & 0x07) == 3) {
+            Width = 32;                                     // 32 bits
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
+          if (((temp >> 3) & 0x07) == 0) {
+            Rank = 1;                                       // 4 bits
+            DmiTable[DimmIndex].Attributes = 1;             // Single Rank Dimm
+          } else if (((temp >> 3) & 0x07) == 1) {
+            Rank = 2;                                       // 8 bits
+            DmiTable[DimmIndex].Attributes = 2;             // Dual Rank Dimm
+          } else if (((temp >> 3) & 0x07) == 2) {
+            Rank = 3;                                       // 16 bits
+          } else if (((temp >> 3) & 0x07) == 3) {
+            Rank = 4;                                       // 32 bits
+            DmiTable[DimmIndex].Attributes = 4;             // Quad Rank Dimm
+          }
+
+          DimmSize = (UINT32) (Capacity / 8 * BusWidth / Width * Rank);
+          if (DimmSize < 0x7FFF) {
+            DmiTable[DimmIndex].MemorySize = (UINT16) DimmSize;
+          } else {
+            DmiTable[DimmIndex].MemorySize = 0x7FFF;
+            DmiTable[DimmIndex].ExtSize = DimmSize;
+          }
+
+          // Form Factor (offset 0Eh)
+          FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3];
+          if ((FormFactor & 0x0F) == 0x01 || (FormFactor & 0x0F) == 0x02) {
+            DmiTable[DimmIndex].FormFactor = 0x09;         // RDIMM or UDIMM
+          } else if ((FormFactor & 0x0F) == 0x03) {
+            DmiTable[DimmIndex].FormFactor = 0x0D;         // SO-DIMM
+          }
+
+          // Type Detail (offset 13h)
+          if ((FormFactor & 0x0F) == 0x01) {
+            *((UINT8 *) (AllocHeapParams.BufferPtr) + 1) = 1;      // Registered (Buffered)
+          } else {
+            *((UINT8 *) (AllocHeapParams.BufferPtr) + 1) = 2;      // Unbuffered (Unregistered)
+          }
+
+          // Speed (offset 15h)
+          MTB_ps = ((INT32) SpdDataStructure[DimmIndex].Data[10] * 1000) / SpdDataStructure[DimmIndex].Data[11];
+          FTB_ps = (SpdDataStructure[DimmIndex].Data[9] >> 4) / (SpdDataStructure[DimmIndex].Data[9] & 0xF);
+          Value32 = (MTB_ps * SpdDataStructure[DimmIndex].Data[12]) + (FTB_ps * (INT8) SpdDataStructure[DimmIndex].Data[34]) ;
+          if (Value32 <= 938) {
+            DmiTable[DimmIndex].Speed = 1067;              // DDR3-2133
+          } else if (Value32 <= 1071) {
+            DmiTable[DimmIndex].Speed = 933;               // DDR3-1866
+          } else if (Value32 <= 1250) {
+            DmiTable[DimmIndex].Speed = 800;               // DDR3-1600
+          } else if (Value32 <= 1500) {
+            DmiTable[DimmIndex].Speed = 667;               // DDR3-1333
+          } else if (Value32 <= 1875) {
+            DmiTable[DimmIndex].Speed = 533;               // DDR3-1066
+          } else if (Value32 <= 2500) {
+            DmiTable[DimmIndex].Speed = 400;               // DDR3-800
+          }
+
+          // Manufacturer (offset 17h)
+          ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118];
+          DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]);
+
+          // Serial Number (offset 18h)
+          for (i = 0; i < 4; i++) {
+            DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122];
+          }
+          // Part Number (offset 1Ah)
+          for (i = 0; i < 18; i++) {
+            DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128];
+          }
+
+          // Configured Memory Clock Speed (offset 20h)
+          DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed;
+
+          // Starting/Ending Address for each DIMM
+          // If Ending Address >= 0xFFFFFFFF, update Starting Address & Ending Address to 0xFFFFFFFF,
+          // and use the Extended Starting Address & Extended Ending Address instead.
+          if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
+            Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & NBPtr->CsRegMsk;
+            Address = (Address & 0xFFFF0000) >> 2;
+            if (DctInterleaveEnabled) {
+              // When channel interleave is enabled, all the DIMMs on the node share the same starting address
+              Address = (UINT32)NodeMemBase;
+            } else {
+              Address += (UINT32) (NodeMemBase + DctMemBase);
+            }
+            if (NodeInterleaveEnabled) {
+              // When node interleave is enabled, all the DIMMs in the system share the same starting address
+              Address = 0;
+            }
+            DmiTable[DimmIndex].StartingAddr = Address;
+            AddrValue = (UINT64) Address + ((UINT64) ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSMask0Reg + Dimm) & 0xFFFF0000) + 0x00080000) >> 2) - 1;
+            if (DctInterleaveEnabled) {
+              // When channle interleave is enabled, all the DIMMs on the node share the same ending address
+              AddrValue = (NodeMemBase + (NBPtr[NodeId].MCTPtr->NodeMemSize << 6)) - 1;
+            }
+            if (NodeInterleaveEnabled) {
+              // When node interleave is enabled, all the DIMMs in the system share the same ending address
+              AddrValue = SysMemSize - 1;
+            }
+            if (AddrValue >= ((UINT64) 0xFFFFFFFF)) {
+              DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFFUL;
+              DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFFUL;
+              DmiTable[DimmIndex].ExtStartingAddr = (UINT64) Address;
+              DmiTable[DimmIndex].ExtEndingAddr = AddrValue;
+            } else {
+              DmiTable[DimmIndex].EndingAddr = (UINT32) AddrValue;
+            }
+          }
+        }  // Dimm present
+        TotalSize += (UINT32) DmiTable[DimmIndex].MemorySize;
+      }    // Dimm loop
+      DctMemBase += (NBPtr[Socket].DCTPtr->Timings.DctMemSize << 6);
+    }      // Channel loop
+    NodeMemBase += (NBPtr[Socket].MCTPtr->NodeMemSize << 6);
+  }          // Socket loop
+
+  *((UINT32 *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = TotalSize;      // Max Capacity
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets DDR2 DMI information from SPD buffer and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8  i;
+  UINT8  Dimm;
+  UINT8  Socket;
+  UINT8  NodeId;
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT8  temp;
+  UINT8  MaxDimms;
+  UINT8  DimmIndex;
+  UINT8  MaxChannelsPerSocket;
+  UINT8  MaxDimmsPerChannel;
+  UINT8  FormFactor;
+  UINT8  Temp;
+  UINT8  Rank;
+  UINT16 TotalWidth;
+  UINT32 Speed;
+  UINT32 MaxSockets;
+  UINT32 Address;
+
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DMI_INFO *DmiTable;
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SpdDataStructure;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  MemPtr = MemMainPtr->MemPtr;
+  SpdDataStructure = MemPtr->SpdDataStructure;
+  MCTPtr = NBPtr->MCTPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Initialize local variables
+  MaxDimms = 0;
+
+  ASSERT (NBPtr != NULL);
+
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
+      temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      MaxDimms = MaxDimms + temp;
+    }
+  }
+
+  // Allocate heap for memory DMI table 16, 17, 19, 20
+  AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3;
+
+  AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2
+    return FALSE;
+  }
+
+  DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+  *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms;          // Number of memory devices
+  *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType;  // Memory type
+
+  //
+  // DMI TYPE 17
+  //
+  DimmIndex = 0;
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      //
+      // Get Node number and Dct number for this channel
+      //
+      ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
+      NodeId = ChannelPtr->MCTPtr->NodeId;
+      Dct = ChannelPtr->Dct;
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
+        DmiTable[DimmIndex].TotalWidth = 0xFFFF;
+        DmiTable[DimmIndex].DataWidth = 0xFFFF;
+        DmiTable[DimmIndex].MemorySize = 0xFFFF;
+        DmiTable[DimmIndex].Speed = 0;
+        DmiTable[DimmIndex].ManufacturerIdCode = 0;
+        DmiTable[DimmIndex].Attributes = 0;
+        DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].DimmPresent = 0;
+        DmiTable[DimmIndex].ConfigSpeed = 0;
+
+        for (i = 0; i < 4; i++) {
+          DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
+        }
+
+        for (i = 0; i < 18; i++) {
+          DmiTable[DimmIndex].PartNumber[i] = 0x0;
+        }
+
+        if (SpdDataStructure[DimmIndex].DimmPresent) {
+          // Total Width (offset 08h) & Data Width (offset 0Ah)
+          TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13];
+          if ((TotalWidth & 0x04) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 4;          // 4 bits
+          } else if ((TotalWidth & 0x08) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 8;          // 8 bits
+          } else if ((TotalWidth & 0x10) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 16;         // 16 bits
+          } else if ((TotalWidth & 0x20) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 32;         // 32 bits
+          }
+          DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth;
+
+          // Memory Size (offset 0Ch), Attributes (offset 1Bh)
+          Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07;
+          if (Rank == 0) {
+            DmiTable[DimmIndex].Attributes = 1;          // Single Rank Dimm
+          } else if (Rank == 1) {
+            DmiTable[DimmIndex].Attributes = 2;          // Dual Rank Dimm
+          } else if (Rank == 3) {
+            DmiTable[DimmIndex].Attributes = 4;          // Quad Rank Dimm
+          }
+
+          Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31];
+          for (i = 0; i < 8; i++) {
+            if ((Temp & 0x01) == 1) {
+              DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1);
+            }
+            Temp = Temp >> 1;
+          }
+
+          // Form Factor (offset 0Eh)
+          FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
+          if ((FormFactor & 0x04) == 4) {
+            DmiTable[DimmIndex].FormFactor = 0x0D;       // SO-DIMM
+          } else {
+            DmiTable[DimmIndex].FormFactor = 0x09;       // RDIMM or UDIMM
+          }
+
+          // DIMM Present
+          DmiTable[DimmIndex].DimmPresent = 1;
+
+          // DIMM Index
+          DmiTable[DimmIndex].Socket = Socket;
+          DmiTable[DimmIndex].Channel = Channel;
+          DmiTable[DimmIndex].Dimm = Dimm;
+
+          // Speed (offset 15h)
+          Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg);
+          Speed = Speed & 0x00000007;
+          if (Speed == 0) {
+            DmiTable[DimmIndex].Speed = 400;              // 400MHz
+          } else if (Speed == 1) {
+            DmiTable[DimmIndex].Speed = 533;              // 533MHz
+          } else if (Speed == 2) {
+            DmiTable[DimmIndex].Speed = 667;              // 667MHz
+          } else if (Speed == 3) {
+            DmiTable[DimmIndex].Speed = 800;              // 800MHz
+          }
+
+          // Manufacturer (offset 17h)
+          DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64];
+
+          // Serial Number (offset 18h)
+          for (i = 0; i < 4; i++) {
+            DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95];
+          }
+
+          // Part Number (offset 1Ah)
+          for (i = 0; i < 18; i++) {
+            DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73];
+          }
+
+          // Configured Memory Clock Speed (offset 20h)
+          DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed;
+
+          // AGESA does NOT support this feature when bank interleaving is enabled.
+          if (!RefPtr->EnableBankIntlv) {
+            if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
+              Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & NBPtr->CsRegMsk;
+              Address = Address >> 2;
+              DmiTable[DimmIndex].StartingAddr = Address;
+              DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
+            }
+          }
+
+        }        // DIMM Present
+      }          // DIMM loop
+    }
+  }
+
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c
new file mode 100644
index 0000000000..8161bdd294
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c
@@ -0,0 +1,316 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfecc.c
+ *
+ * Feature ECC initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/ECC)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfecc.h"
+#include "Filecode.h"
+#include "mfmemclr.h"
+#include "GeneralServices.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+InitECCOverriedeStruct (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   ECC_OVERRIDE_STRUCT *pecc_override_struct
+  );
+
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function checks to see if ECC can be enabled on all nodes
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  MEM_SHARED_DATA *SharedPtr;
+  BOOLEAN ErrorRecovery;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  SharedPtr = NBPtr->SharedPtr;
+
+  ErrorRecovery = TRUE;
+  IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, &NBPtr->MemPtr->StdHeader);
+
+  if (MCTPtr->NodeMemSize != 0) {
+    if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (ErrorRecovery || (MCTPtr->ErrCode < AGESA_ERROR))) {
+      // Clear all MCA reports before using scrubber
+      // to initialize ECC check bits
+      //
+      NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg);
+      NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0);
+      NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0);
+      // In unganged mode, set DctDctIntlv
+      if (!NBPtr->Ganged) {
+        NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1);
+      }
+      //
+      // Set Ecc Symbol Size
+      //
+      NBPtr->SetEccSymbolSize (NBPtr);
+      // If ECC can be enabled on this node,
+      // set the master ECCen bit (according to setup)
+      //
+      NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
+      // Do mem clear on current node
+      MemFMctMemClr_Init (NBPtr);
+      return TRUE;
+    } else {
+      if (SharedPtr->AllECC) {
+        SharedPtr->AllECC = FALSE;
+      }
+      // ECC requested but cannot be enabled
+      MCTPtr->Status[SbEccDimms] = FALSE;
+      MCTPtr->ErrStatus[EsbDramECCDis] = TRUE;
+      PutEventLog (AGESA_WARNING, MEM_WARNING_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, MCTPtr);
+    }
+  }
+  return FALSE;
+}
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the ECC on all nodes
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInitECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Node;
+  UINT32 ScrubAddrRJ16;
+  DIE_STRUCT *MCTPtr;
+  MEM_SHARED_DATA *SharedPtr;
+  ECC_OVERRIDE_STRUCT  ecc_override_struct;
+  BOOLEAN Flag;
+
+  InitECCOverriedeStruct (NBPtr, &ecc_override_struct);
+  IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader));
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  Node = MCTPtr->NodeId;
+  SharedPtr = NBPtr->SharedPtr;
+  Flag = TRUE;
+
+  NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag);
+
+  if ((MCTPtr->Status[SbEccDimms]) && (SharedPtr->AllECC)) {
+    // Check if the input dram scrub rate is supported or not
+    ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16);
+    if (ecc_override_struct.CfgScrubDramRate != 0) {
+    // Program scrub address,
+    // let the scrub Addr be the Base of this Node
+    // Only enable Dram scrubber when there is memory on current node
+    //
+      NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0);
+      ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
+      ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24;
+      NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
+      NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
+      NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate);
+    }
+  }
+  // Scrub CTL for Dcache, L2, L3
+  // Check if the input L2 scrub rate is supported or not
+  ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16);
+  NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate);
+  // Check if the input Dcache scrub rate is supported or not
+  ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16);
+  NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate);
+  // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[DisableL3] is 1
+  if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFDisableL3) == 0)) {
+    // Check if input L3 scrub rate is supported or not
+    ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16);
+    NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate);
+  }
+
+  // Check if Dcache scrubber or L2 scrubber is enabled
+  if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) {
+    // If ClkDivisor is deeper than divide-by-16
+    if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) {
+      // Set it to divide-by-16
+      NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4);
+    }
+  }
+
+  NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection);
+  NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood);
+  // Restore MCA reports after scrubber is done
+  // with initializing ECC check bits
+  NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg);
+
+  Flag = FALSE;
+  NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag);
+
+  return TRUE;
+}
+
+VOID
+STATIC
+InitECCOverriedeStruct (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   ECC_OVERRIDE_STRUCT *pecc_override_struct
+  )
+{
+  //
+  // If (D18F3x44[DramEccEn]==1) THEN 1 ELSE 0 ENDIF
+  //
+  if (NBPtr->GetBitField (NBPtr, BFDramEccEn) == 1) {
+    pecc_override_struct->CfgEccRedirection = 1;
+  } else {
+    pecc_override_struct->CfgEccRedirection = 0;
+  }
+
+  pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood;
+  pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate;
+
+  if (UserOptions.CfgScrubDramRate != 0xFF) {
+    pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate;
+  } else {
+    if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) {
+      pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) {
+      pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) {
+      pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) {
+      pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) {
+      pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB
+    } else {
+      pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above
+    }
+  }
+
+  pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate;
+  pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h
new file mode 100644
index 0000000000..d9b1e20282
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfecc.h
+ *
+ * Feature ECC initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFECC_H_
+#define _MFECC_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInitECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFECC_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c
new file mode 100644
index 0000000000..f530aff045
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c
@@ -0,0 +1,204 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfemp.c
+ *
+ * Feature EMP initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/ECC)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN       UINT32 TestNumber
+  );
+
+BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes EMP (Enhanced Memory Protection)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  if (RefPtr->EnableEccFeature) {
+    if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE;
+    } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPConflict] = TRUE;
+    } else if ((!MCTPtr->GangedMode) &&
+               (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) &&
+                !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPDis] = TRUE;
+    } else {
+      // Reduce memory size to 7/8 of the original memory size
+      ASSERT ((MCTPtr->NodeMemSize % 8) == 0);
+      NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0);
+      MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7;
+      NBPtr->HtMemMapInit (NBPtr);
+      NBPtr->CpuMemTyping (NBPtr);
+
+      // Enable EMP
+      NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
+
+      // Scrub CTL settings for Dcache, L2
+      NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate);
+      NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate);
+
+      NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood);
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function checks to see if the input is power of two.
+ *
+ *     @param[in]    TestNumber  - Value to check for power of two
+ *
+ *     @return          TRUE     - is power of two
+ *                      FALSE    - is not power of two
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN       UINT32 TestNumber
+  )
+{
+  return (BOOLEAN) ((TestNumber & (TestNumber - 1)) == 0);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
new file mode 100644
index 0000000000..991237d64b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -0,0 +1,233 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfdimmexclud.c
+ *
+ * Feature DIMM exclude.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/EXCLUDIMM)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and disable Chip selects that fail training for each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ReserveDCT;
+  UINT8 q;
+  BOOLEAN Flag;
+  BOOLEAN IsCSIntlvEnabled;
+  UINT16 CsTestFail;
+  DIE_STRUCT *MCTPtr;
+  BOOLEAN RetVal;
+
+  ASSERT (NBPtr != NULL);
+  ReserveDCT = NBPtr->Dct;
+  CsTestFail = 0;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.CsTestFail != 0) {
+      // When there is no new failed dimm that needs to be excluded, then no need to go through the process.
+      switch (NBPtr->SharedPtr->DimmExcludeFlag) {
+      case NORMAL:
+        // See there is new dimm that needs to be excluded
+        if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) {
+          CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
+        }
+        break;
+      case TRAINING:
+        // Do not do any dimm excluding during training
+        // Dimm exclude will be done at the end of training
+        break;
+      case END_TRAINING:
+        // Exclude all dimms that have failures during training
+        if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) ||
+            ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) {
+          CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
+        }
+        break;
+      default:
+        IDS_ERROR_TRAP;
+      }
+    }
+  }
+
+  if (CsTestFail != 0) {
+    IsCSIntlvEnabled = FALSE;
+    MCTPtr = NBPtr->MCTPtr;
+    MCTPtr->NodeMemSize = 0;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0;
+    NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+    NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0);
+
+    if (MCTPtr->GangedMode) {
+      // if ganged mode, disable all pairs of CS that fail.
+      NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail;
+    }
+
+    // if chip select interleaving has been enabled, need to undo it before remapping memory
+    if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) {
+      IsCSIntlvEnabled = TRUE;
+    }
+
+    Flag = TRUE;
+    NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          NBPtr->DCTPtr->Timings.DctMemSize = 0;
+
+          NBPtr->DCTPtr->Timings.CsEnabled = 0;
+          for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+            NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
+          }
+
+          // Set F2x94[DisDramInterface] = 1 if all chip selects fail training on the DCT
+          if ((NBPtr->DCTPtr->Timings.CsPresent & ~NBPtr->DCTPtr->Timings.CsTestFail) == 0) {
+            NBPtr->DisableDCT (NBPtr);
+          }
+
+          Flag = NBPtr->StitchMemory (NBPtr);
+          ASSERT (Flag == TRUE);
+        }
+      }
+    }
+    Flag = FALSE;
+    NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
+
+    // Re-enable chip select interleaving when remapping is done.
+    if (IsCSIntlvEnabled) {
+      NBPtr->FeatPtr->InterleaveBanks (NBPtr);
+    }
+
+    RetVal = TRUE;
+  } else {
+    RetVal = FALSE;
+  }
+  NBPtr->SwitchDCT (NBPtr, ReserveDCT);
+  return RetVal;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
new file mode 100644
index 0000000000..d99cf6804f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -0,0 +1,575 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfidendimm.c
+ *
+ * Translate physical system address to dimm identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "heapManager.h"
+#include "mfidendimm.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_DIE        2   ///< Max DCTs per die
+#define MAX_CHLS_PER_DCT        1   ///< Max Channels per DCT
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+STATIC
+MemFTransSysAddrToCS (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify,
+  IN       MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+UINT32
+STATIC
+MemFGetPCI (
+  IN   MEM_NB_BLOCK *NBPtr,
+  IN   UINT8 NodeID,
+  IN   UINT8 DctNum,
+  IN   BIT_FIELD_NAME BitFieldName
+  );
+
+UINT8
+STATIC
+MemFUnaryXOR (
+  IN   UINT32 address
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function identifies the dimm on which the given memory address locates.
+*
+*   @param[in, out]   *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
+*
+*   @retval           AGESA_SUCCESS - Successfully translate physical system address
+*                                     to dimm identification.
+*                     AGESA_BOUNDS_CHK - Targeted address is out of bound.
+*
+*/
+
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+  )
+{
+  UINT8 i;
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;             // Main Data block
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT MemData;
+  LOCATE_HEAP_PTR LocHeap;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 Node;
+  UINT8 Dct;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader));
+  mmData.MemPtr = &MemData;
+  RetVal = MemSocketScan (&mmData);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  // Search for AMD_MEM_AUTO_HANDLE on the heap first.
+  // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
+  LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    mmData.NBPtr = NBPtr;
+  } else {
+    AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
+    AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) {
+      PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader);
+      ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM
+      return AGESA_FATAL;
+    }
+    NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+    mmData.NBPtr = NBPtr;
+    // Construct each die.
+    for (Die = 0; Die < DieCount; Die ++) {
+      i = 0;
+      while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) {
+        if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) {
+          break;
+        }
+        i++;
+      };
+      if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) {
+        PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader);
+        ASSERT(FALSE); // No Identify DIMM constructor found
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) {
+    // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number.
+    Node = AmdDimmIdentify->SocketId;
+    Dct = AmdDimmIdentify->MemChannelId;
+    AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId;
+    AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0);
+    AmdDimmIdentify->DimmId /= 2;
+  }
+
+  return RetVal;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function translates the given physical system address to
+*   a node, channel select, chip select, bank, row, and column address.
+*
+*   @param[in, out]   *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
+*   @param[in, out]   *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
+*
+*   @retval           AGESA_SUCCESS - The chip select address is found
+*   @retval           AGESA_BOUNDS_CHK - Targeted address is out of bound.
+*
+*/
+AGESA_STATUS
+STATIC
+MemFTransSysAddrToCS (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify,
+  IN       MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  BOOLEAN CSFound;
+  BOOLEAN DctSelHiRngEn;
+  BOOLEAN DctSelIntLvEn;
+  BOOLEAN DctGangEn;
+  BOOLEAN HiRangeSelected;
+  BOOLEAN DramHoleValid;
+  BOOLEAN CSEn;
+  BOOLEAN SwapDone;
+  BOOLEAN IntLvRgnSwapEn;
+  UINT8 DctSelHi;
+  UINT8 DramEn;
+  UINT8 range;
+  UINT8 IntlvEn;
+  UINT8 IntlvSel;
+  UINT8 ILog;
+  UINT8 DctSelIntLvAddr;
+  UINT8 DctNum;
+  UINT8 cs;
+  UINT8 BadDramCs;
+  UINT8 spare;
+  UINT8 IntLvRgnBaseAddr;
+  UINT8 IntLvRgnLmtAddr;
+  UINT8 IntLvRgnSize;
+  UINT32 temp;
+  UINT32 DramHoleOffset;
+  UINT32 DramHoleBase;
+  UINT64 DramBase;
+  UINT64 DramLimit;
+  UINT64 DramLimitSysAddr;
+  UINT64 DctSelBaseAddr;
+  UINT64 DctSelBaseOffset;
+  UINT64 ChannelAddr;
+  UINT64 CSBase;
+  UINT64 CSMask;
+  UINT64 InputAddr;
+  UINT64 ChannelOffset;
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 Die;
+
+  UINT64 SysAddr;
+  UINT8 *NodeID;
+  UINT8 *ChannelSelect;
+  UINT8 *ChipSelect;
+
+  SysAddr = AmdDimmIdentify->MemoryAddress;
+  NodeID = &(AmdDimmIdentify->SocketId);
+  ChannelSelect = &(AmdDimmIdentify->MemChannelId);
+  ChipSelect = &(AmdDimmIdentify->DimmId);
+  CSFound = FALSE;
+  ILog = 0;
+  NBPtr = mmPtr->NBPtr;
+
+  NBPtr->FamilySpecificHook[FixupSysAddr] (NBPtr, &SysAddr);
+
+  // Loop to determine the dram range
+  for (Die = 0; Die < mmPtr->DieCount; Die ++) {
+    range = NBPtr[Die].Node;
+
+    // DRAM Base
+    temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range);
+    DramEn = (UINT8) (temp & 0x3);
+    IntlvEn = (UINT8) ((temp >> 8) & 0x7);
+
+    DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) |
+                 (((UINT64) temp & 0xFFFF0000) << 8);
+
+    // DRAM Limit
+    temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range);
+    *NodeID = (UINT8) (temp & 0x7);
+    IntlvSel = (UINT8) ((temp >> 8) & 0x7);
+    DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) |
+                  (((UINT64) temp << 8) | 0xFFFFFF);
+    DramLimitSysAddr = (((UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDramLimitAddr)) << 27) | 0x7FFFFFF;
+    ASSERT (DramLimit <= DramLimitSysAddr);
+
+    if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimitSysAddr) &&
+        ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) {
+      // Determine the number of bit positions consumed by Node Interleaving
+      switch (IntlvEn) {
+
+      case 0x0:
+        ILog = 0;
+        break;
+
+      case 0x1:
+        ILog = 1;
+        break;
+
+      case 0x3:
+        ILog = 2;
+        break;
+
+      case 0x7:
+        ILog = 3;
+        break;
+
+      default:
+        IDS_ERROR_TRAP;
+      }
+
+      DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23;
+      DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid);
+      DramHoleBase = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleBase) << 24;
+      // Address belongs to this node based on DramBase/Limit,
+      // but is in the memory hole so it doesn't map to DRAM
+      if (DramHoleValid && (DramHoleBase <= SysAddr) && (SysAddr < 0x100000000)) {
+        return AGESA_BOUNDS_CHK;
+      }
+
+      // F2x10C Swapped Interleaved Region
+      IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn);
+      if (IntLvRgnSwapEn) {
+        IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr);
+        IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr);
+        IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize);
+        ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
+        if (((SysAddr >> 34) == 0) &&
+          ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr))
+           || ((SysAddr >> 27) < IntLvRgnSize))) {
+          SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
+        }
+      }
+
+      // Extract variables from F2x110 DRAM Controller Select Low Register
+      DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn);
+      DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi);
+      DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn);
+      DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn);
+      DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr);
+      DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27;
+      DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26;
+
+
+      // Determine if high DCT address range is being selected
+      if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) {
+        HiRangeSelected = TRUE;
+      } else {
+        HiRangeSelected = FALSE;
+      }
+
+      // Determine Channel
+      if (DctGangEn) {
+        *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1);
+      } else if (HiRangeSelected) {
+        *ChannelSelect = DctSelHi;
+      } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) {
+        *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1);
+      } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) {
+        temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F));
+        if ((DctSelIntLvAddr & 0x1) != 0) {
+          *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp);
+        } else {
+          *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp);
+        }
+      } else if (DctSelIntLvEn) {
+        *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1);
+      } else if (DctSelHiRngEn) {
+        *ChannelSelect = ~DctSelHi & 0x1;
+      } else {
+        *ChannelSelect = 0;
+      }
+      ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount);
+
+      // Determine base address offset
+      if (HiRangeSelected) {
+        if ((DctSelBaseAddr < DramHoleBase) && DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) {
+          ChannelOffset = (UINT64) DramHoleOffset;
+        } else {
+          ChannelOffset = DctSelBaseOffset;
+        }
+      } else {
+        if (DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) {
+          ChannelOffset = (UINT64) DramHoleOffset;
+        } else {
+          ChannelOffset = DramBase;
+        }
+      }
+
+      // Remove hoisting offset and normalize to DRAM bus addresses
+      ChannelAddr = SysAddr - ChannelOffset;
+
+      // Remove node interleaving
+      if (IntlvEn != 0) {
+        ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF);
+      }
+
+      // Remove channel interleave
+      if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) {
+        if ((DctSelIntLvAddr & 1) != 1) {
+          // A[6] Select or Hash 6
+          ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F);
+        } else if (DctSelIntLvAddr == 1) {
+          // A[12]
+          ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF);
+        } else {
+          // Hash 9
+          ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF);
+        }
+      }
+
+      // Determine the Chip Select
+      for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) {
+        DctNum = DctGangEn ? 0 : *ChannelSelect;
+
+        // Obtain the CS Base
+        temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs);
+        CSEn = (BOOLEAN) (temp & 0x1);
+        CSBase = ((UINT64) temp & NBPtr->CsRegMsk) << 8;
+
+        // Obtain the CS Mask
+        CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & NBPtr->CsRegMsk) << 8;
+
+        // Adjust the Channel Addr for easy comparison
+        InputAddr = ((ChannelAddr >> 8) & NBPtr->CsRegMsk) << 8;
+
+        if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) {
+          CSFound = TRUE;
+
+          *ChipSelect = cs;
+
+          temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl);
+          SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1);
+          BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7);
+          if (SwapDone && (cs == BadDramCs)) {
+            // Find the spare rank for the channel
+            for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) {
+              if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) {
+                *ChipSelect = spare;
+                break;
+              }
+            }
+          }
+          ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL);
+
+          break;
+        }
+      }
+    }
+    if (CSFound) {
+      break;
+    }
+  }
+
+  // last ditch sanity check
+  ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL)));
+  if (CSFound) {
+    return AGESA_SUCCESS;
+  } else {
+    return AGESA_BOUNDS_CHK;
+  }
+
+}
+
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function is the interface to call the PCI register access function
+*   defined in NB block.
+*
+*   @param[in]   *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK
+*   @param[in]   NodeID - Node ID number of the target Northbridge
+*   @param[in]   DctNum - DCT number if applicable, otherwise, put 0
+*   @param[in]   BitFieldName - targeted bitfield
+*
+*   @retval      UINT32 - 32 bits PCI register value
+*
+*/
+UINT32
+STATIC
+MemFGetPCI (
+  IN   MEM_NB_BLOCK *NBPtr,
+  IN   UINT8 NodeID,
+  IN   UINT8 DctNum,
+  IN   BIT_FIELD_NAME BitFieldName
+  )
+{
+  MEM_NB_BLOCK *LocalNBPtr;
+  UINT8 Die;
+
+  // Find NBBlock that associates with node NodeID
+  for (Die = 0; (Die < MAX_NODES_SUPPORTED) && (NBPtr[Die].Node != NodeID); Die ++);
+  ASSERT (Die < MAX_NODES_SUPPORTED);
+
+  // Get the northbridge pointer for the targeted node.
+  LocalNBPtr = &NBPtr[Die];
+  LocalNBPtr->FamilySpecificHook[DCTSelectSwitch] (LocalNBPtr, &DctNum);
+  LocalNBPtr->Dct = DctNum;
+  // The caller of this function will take care of the ganged/unganged situation.
+  // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum.
+  return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function returns an even parity bit (making the total # of 1's even)
+*   {0, 1} = number of set bits in argument is {even, odd}.
+*
+*   @param[in]   address - the address on which the parity bit will be calculated
+*
+*   @retval      UINT8 - parity bit
+*
+*/
+
+UINT8
+STATIC
+MemFUnaryXOR (
+  IN   UINT32 address
+  )
+{
+  UINT8 parity;
+  UINT8 index;
+  parity = 0;
+  for (index = 0; index < 32; ++ index) {
+    parity = (UINT8) (parity ^ (address & 0x1));
+    address = address >> 1;
+  }
+  return parity;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
new file mode 100644
index 0000000000..032c236f67
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfidendimm.h
+ *
+ * Header file for address to dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFIDENDIMM_H_
+#define _MFIDENDIMM_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorLN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+#endif //_MFIDENDIMM_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
new file mode 100644
index 0000000000..0592bc344b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -0,0 +1,190 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfrintlv.c
+ *
+ * Feature Region interleaving support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Intlvrgn)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfintlvrn.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_RJ27 ((UINT32)4 << (30 - 27))
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   MemFInterleaveRegion:
+ *
+ *  Applies region interleaving if both DCTs have different size of memory, and
+ *  the channel interleaving region doesn't have UMA covered.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemFInterleaveRegion (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 TOM;
+  UINT32 TOM2;
+  UINT32 TOMused;
+  UINT32 UmaBase;
+  UINT32 DctSelBase;
+  S_UINT64 SMsr;
+  LOCATE_HEAP_PTR LocHeap;
+  UMA_INFO *UmaInfoPtr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  MemPtr = NBPtr->MemPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16);
+
+  //TOM scaled from [47:0] to [47:27]
+  LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo += (16 << 20);  // Add 16MB to gain back C6 region if C6 is enabled
+  TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
+
+  //TOM2 scaled from [47:0] to [47:27]
+  LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
+
+  TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM;
+
+  if (UmaBase != 0) {
+    //Check if channel interleaving is enabled ? if so, go to next step.
+    if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) {
+      DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr);
+      //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1.
+      if (DctSelBase != 0) {
+        //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA.
+        if (DctSelBase < TOMused) {
+          NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused);
+
+          // Set UMA attribute to interleaved after interleaved region has been swapped
+          LocHeap.BufferHandle = AMD_UMA_INFO_HANDLE;
+          if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
+            UmaInfoPtr = (UMA_INFO *) LocHeap.BufferPtr;
+            UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
+          } else {
+            ASSERT (FALSE);
+          }
+        }
+      }
+    }
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
new file mode 100644
index 0000000000..c2de6b7616
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfintlvrn.h
+ *
+ * Feature region interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFINTLVRN_H_
+#define _MFINTLVRN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemFInterleaveRegion (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFINTLVRN_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c
new file mode 100644
index 0000000000..7a821a7cad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -0,0 +1,199 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * lvddr3.c
+ *
+ * Voltage change for DDR3 DIMMs.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/LVDDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE
+/* features */
+#include "mflvddr3.h"
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculate the common lowest voltage supported by all DDR3
+ *   DIMMs in the system. This function only needs to be called on BSP.
+ *
+ *   @param[in, out]    *NBPtr - Pointer to NB block
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFLvDdr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_TECH_BLOCK  *TechPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 Dimm;
+  UINT8 *SpdBufferPtr;
+  UINT8 VDDByte;
+  UINT8 VoltageMap;
+
+  mmSharedPtr = NBPtr->SharedPtr;
+  TechPtr = NBPtr->TechPtr;
+  VoltageMap = 0xFF;
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) {
+          // SPD byte 6: Module Nominal Voltage, VDD
+          // 1.5v - bit 0
+          // 1.35v - bit 1
+          // 1.2v - bit 2
+          VDDByte = SpdBufferPtr[MNVVDD];
+          IDS_HDT_CONSOLE (MEM_FLOW, "Node%d DCT%d Channel%d Dimm%d VDD Byte: 0x%02x\n", NBPtr->Node, Dct, Channel, Dimm, VDDByte);
+
+          // Reverse the 1.5V operable bit. So its encoding can be consistent
+          // with that of 1.35V and 1.25V operable bit.
+          VDDByte ^= 1;
+          ASSERT (VDDByte != 0);
+
+          if (mmSharedPtr->VoltageMap != 0) {
+            // Get the common supported voltage map
+            VoltageMap &= VDDByte;
+          } else {
+            // This is the second execution of all the loop as no common voltage is found
+            if (VDDByte == (1 << VOLT1_5_ENCODED_VAL)) {
+              // Always exclude 1.5V dimm if no common voltage is found
+              ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm;
+            }
+          }
+        }
+      }
+      if (mmSharedPtr->VoltageMap == 0) {
+        NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude;
+      }
+    }
+  }
+
+  if (mmSharedPtr->VoltageMap != 0) {
+    mmSharedPtr->VoltageMap &= VoltageMap;
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.h
new file mode 100644
index 0000000000..e7cff05eae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mflvddr3.h
+ *
+ * Header file for DDR3 DIMMs voltage configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFLVDDR3_H_
+#define _MFLVDDR3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MNVVDD 6
+#define LOWEST_VOLT_BIT 2
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFLvDdr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+);
+
+#endif //_MFLVDDR3_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
new file mode 100644
index 0000000000..b054be4fd2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -0,0 +1,178 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfmemclr.c
+ *
+ * Feature function for memory clear operation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Memclr)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfmemclr.h"
+#include "Ids.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Initiates memory clear operation on one node with Dram on it.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemFMctMemClr_Init (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader);
+  if (NBPtr->RefPtr->EnableMemClr == TRUE) {
+    if (NBPtr->MCTPtr->NodeMemSize != 0) {
+      if (!NBPtr->MemCleared) {
+        NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE);
+        if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) {
+          NBPtr->FamilySpecificHook[BeforeMemClr] (NBPtr, NBPtr);
+          NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+          NBPtr->SetBitField (NBPtr, BFMemClrInit, 1);
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Ensures memory clear operation has completed on one node with Dram on it.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemFMctMemClr_Sync (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 MicroSecondToWait;
+
+  MicroSecondToWait = 0;
+  if (NBPtr->RefPtr->EnableMemClr == TRUE) {
+    if (NBPtr->MCTPtr->NodeMemSize != 0) {
+      // Calculate Timeout value:
+      // Timeout (in microsecond) = Memory Size * 1.5 ns / 8 Byte * 4 (Margin) * 1000 (change millisecond to us)
+      // NodeMemSize is system address right shifted by 16, so shift it 4 bits to right to convert it to MB.
+      // 1.5 / 8 * 4 * 1000 = 750
+      MicroSecondToWait = (NBPtr->MCTPtr->NodeMemSize >> 4) * 750;
+
+      if (!NBPtr->MemCleared) {
+        NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, MicroSecondToWait, FALSE);
+        NBPtr->PollBitField (NBPtr, BFMemCleared, 1, MicroSecondToWait, FALSE);
+        NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16));
+        NBPtr->MemCleared = TRUE;
+      }
+    }
+  }
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
new file mode 100644
index 0000000000..84449b1e2e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -0,0 +1,199 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfodthermal.c
+ *
+ * On Dimm thermal management.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "mfodthermal.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function does On-Dimm thermal management.
+ *
+ *   @param[in, out]   *NBPtr - Pointer to the MEM_NB_BLOCK.
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFOnDimmThermal (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  UINT8 Dct;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  UINT8 *SpdBufferPtr;
+  UINT8 ThermalOp;
+  BOOLEAN ODTSEn;
+  BOOLEAN ExtendTmp;
+
+  ODTSEn = FALSE;
+  ExtendTmp = FALSE;
+
+  ASSERT (NBPtr != NULL);
+  MemPtr = NBPtr->MemPtr;
+  AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader);
+  if (NBPtr->MCTPtr->NodeMemSize != 0) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      // Only go through the DCT if it is not disabled.
+      if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        // If Ganged mode is enabled, need to go through all dram devices on both DCTs.
+        if (!NBPtr->Ganged || (NBPtr->Dct != 1)) {
+          if (!(NBPtr->IsSupported[CheckSetSameDctODTsEn]) || (NBPtr->IsSupported[CheckSetSameDctODTsEn] && (NBPtr->Dct != 1))) {
+            ODTSEn = TRUE;
+            ExtendTmp = TRUE;
+          }
+        }
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+          if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) {
+            // Check byte 31: thermal and refresh option.
+            ThermalOp = SpdBufferPtr[THERMAL_OPT];
+            // Bit 3: ODTS readout
+            if (!((ThermalOp >> 3) & 1)) {
+              ODTSEn = FALSE;
+            }
+            // Bit 0: Extended Temperature Range.
+            if (!(ThermalOp & 1)) {
+              ExtendTmp = FALSE;
+            }
+          }
+        }
+
+        if (!NBPtr->Ganged || (NBPtr->Dct == 1)) {
+          // If in ganged mode, need to switch back to DCT0 to set the registers.
+          if (NBPtr->Ganged || NBPtr->IsSupported[CheckSetSameDctODTsEn]) {
+            NBPtr->SwitchDCT (NBPtr, 0);
+            ChannelPtr = NBPtr->ChannelPtr;
+          }
+          // If all dram devices on support ODTS
+          NBPtr->SetBitField (NBPtr, BFODTSEn, (ODTSEn == TRUE) ? 1 : 0);
+          ChannelPtr->ExtendTmp = ExtendTmp;
+        }
+      }
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tDct %d\n", Dct);
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\tODTSEn = %d\n", ODTSEn);
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtendTmp = %d\n", ExtendTmp);
+    }
+  }
+  return TRUE;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
new file mode 100644
index 0000000000..1015e66ac9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfodthermal.h
+ *
+ * Header file for On-Dimm thermal management.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFODTHERMAL_H_
+#define _MFODTHERMAL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFOnDimmThermal (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif //_MFODTHERMAL_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
new file mode 100644
index 0000000000..178beb4fdd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -0,0 +1,315 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfParallelTraining.c
+ *
+ * This is the parallel training feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/PARTRN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
+
+/*-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *    This is the main function to perform parallel training on all nodes.
+ *    This is the routine which will run on the remote AP.
+ *
+ *     @param[in,out]   *EnvPtr   - Pointer to the Training Environment Data
+ *     @param[in,out]   *StdHeader   - Pointer to the Standard Header of the AP
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFParallelTraining (
+  IN OUT   REMOTE_TRAINING_ENV *EnvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  MEM_PARAMETER_STRUCT ParameterList;
+  MEM_NB_BLOCK NB;
+  MEM_TECH_BLOCK TB;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  UINT8 p;
+  UINT8 i;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 *BufferPtr;
+  UINT8 DctCount;
+  UINT8 ChannelCount;
+  UINT8 RowCount;
+  UINT8 ColumnCount;
+  UINT16 SizeOfNewBuffer;
+  AP_DATA_TRANSFER ReturnData;
+
+  //
+  // Initialize Parameters
+  //
+  ReturnData.DataPtr = NULL;
+  ReturnData.DataSizeInDwords = 0;
+  ReturnData.DataTransferFlags = 0;
+
+  ASSERT (EnvPtr != NULL);
+  //
+  // Replace Standard header of a AP
+  //
+  LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
+
+
+  //
+  //  Allocate buffer for training data
+  //
+  BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
+  DctCount = EnvPtr->DieStruct.DctCount;
+  BufferPtr += sizeof (DIE_STRUCT);
+  ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
+  BufferPtr += DctCount * sizeof (DCT_STRUCT);
+  RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
+  ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
+
+  SizeOfNewBuffer = sizeof (DIE_STRUCT) +
+                    DctCount * (
+                      sizeof (DCT_STRUCT) + (
+                        ChannelCount * (
+                          sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
+                            RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
+                            (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
+                            (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
+                          )
+                        )
+                      )
+                    );
+  AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    BufferPtr = AllocHeapParams.BufferPtr;
+    LibAmdMemCopy ( BufferPtr,
+                    &(EnvPtr->DieStruct),
+                    sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
+                    StdHeader
+                  );
+
+    //
+    //  Fix up pointers
+    //
+    MCTPtr = (DIE_STRUCT *) BufferPtr;
+    BufferPtr += sizeof (DIE_STRUCT);
+    MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
+    BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
+    for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+      MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
+      BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
+      for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
+        MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
+        MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
+      }
+    }
+    NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
+    BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
+
+    ReturnData.DataPtr = AllocHeapParams.BufferPtr;
+    ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
+    ReturnData.DataTransferFlags = 0;
+
+    //
+    // Allocate Memory for the MEM_DATA_STRUCT we will use
+    //
+    AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+    AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+      MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
+
+      LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
+
+      //
+      // Copy Parameters from environment
+      //
+      ParameterList.HoleBase = EnvPtr->HoleBase;
+      ParameterList.BottomIo = EnvPtr->BottomIo;
+      ParameterList.UmaSize = EnvPtr->UmaSize;
+      ParameterList.SysLimit = EnvPtr->SysLimit;
+      ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
+      ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
+      MemPtr->ParameterListPtr = &ParameterList;
+
+      for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+        MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
+      }
+
+      MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
+      //
+      // Create Local NBBlock and Tech Block
+      //
+      EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
+      NB.RefPtr = &ParameterList;
+      NB.MemPtr = MemPtr;
+      i = 0;
+      while (memTechInstalled[i] != NULL) {
+        if (memTechInstalled[i] (&TB, &NB)) {
+          break;
+        }
+        i++;
+      }
+      NB.TechPtr = &TB;
+      NB.TechBlockSwitch (&NB);
+
+      //
+      // Setup CPU Mem Type MSRs on the AP
+      //
+      NB.CpuMemTyping (&NB);
+
+      IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node);
+      //
+      // Call Technology Specific Training routine
+      //
+      NB.TrainingFlow (&NB);
+      //
+      // Copy training data to ReturnData buffer
+      //
+      LibAmdMemCopy ( BufferPtr,
+                      MCTPtr->DctData[0].ChData[0].RcvEnDlys,
+                      ((DctCount * ChannelCount) * (
+                         (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
+                         (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
+                         (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
+                        )
+                      ),
+                      StdHeader);
+
+      HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+      //
+      // Restore pointers
+      //
+      for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+        for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
+          MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
+          MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
+
+          MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
+        }
+        MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
+      }
+      MCTPtr->DctData = EnvPtr->DieStruct.DctData;
+    }
+
+    //
+    // Signal to BSP that training is complete and Send Results
+    //
+    ASSERT (ReturnData.DataPtr != NULL);
+    ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
+
+    //
+    // Clean up and exit.
+    //
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
+  } else {
+    MCTPtr = &EnvPtr->DieStruct;
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
new file mode 100644
index 0000000000..d61c1f309b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -0,0 +1,112 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfStandardTraining.c
+ *
+ * This is the standard training routine which performs all training from the BSP
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/PARTRN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "mfStandardTraining.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the main function to perform memory training on all nodes from
+ *       the BSP only.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFStandardTraining (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  ASSERT (NBPtr != NULL);
+
+  NBPtr->TrainingFlow (NBPtr);
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c
new file mode 100644
index 0000000000..45fed9f1f6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c
@@ -0,0 +1,745 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfs3.c
+ *
+ * Main S3 resume memory Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/FEAT/S3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "heapManager.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the main memory entry point for the S3 resume sequence
+ *      Requirements:
+ *
+ *      Run-Time Requirements:
+ *      1. Complete Hypertransport Bus Configuration
+ *      4. BSP in Big Real Mode
+ *      5. Stack available
+ *
+ *      @param[in]  *StdHeader - Config handle for library and services
+ *
+ *      @return     AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+AmdMemS3Resume (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  //---------------------------------------------
+  //1. Errata Before resume sequence
+  //2. S3 Resume sequence
+  //3. Errata After resume sequence
+  //---------------------------------------------
+  for (Die = 0; Die < DieCount; Die ++) {
+    if (!S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die)) {
+      return AGESA_FATAL;
+    }
+    S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die);
+  }
+
+  HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function deallocates heap space allocated in memory S3 resume.
+ *
+ *      @param[in]  *StdHeader - Config handle for library and services
+ *
+ *      @return     AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3Deallocate (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  AGESA_STATUS tempRetVal;
+  UINT8 Tab;
+
+  RetVal = AGESA_SUCCESS;
+  for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) {
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), StdHeader);
+  }
+
+  tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the entrance to get device list for memory registers.
+ *
+ *      @param[in, out]  **DeviceBlockHdrPtr - Pointer to the memory containing the
+ *                                             device descriptor list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetDeviceList (
+  IN OUT   DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  UINT16 BufferSize;
+  UINT64 BufferOffset;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  MEM_MAIN_DATA_BLOCK mmData;
+  UINT8 Die;
+  UINT8 DieCount;
+  AGESA_STATUS RetVal;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
+  BufferSize = 0;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  // Get the mask bit and the register list for node that presents
+  for (Die = 0; Die < DieCount; Die ++) {
+    S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+    S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+    BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+  }
+
+  // Base on the size of the device list, apply for a buffer for it.
+  AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER);
+  AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_S3_RESUME;
+  AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader);
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader);
+
+  *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr;
+  (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
+
+  // Copy device list on the stack to the heap.
+  BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINTN) AllocHeapParams.BufferPtr;
+  for (Die = 0; Die < DieCount; Die ++) {
+    for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+      // Copy PCI device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
+      }
+      // Copy conditional PCI device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+      }
+      // Copy MSR device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
+      }
+      // Copy conditional MSR device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+      }
+    }
+  }
+
+  return RetVal;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initialize the northbridge block and apply for heap space
+ *      before any function call is made to memory component during S3 resume.
+ *
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3ResumeInitNB (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  UINT8 Die;
+  UINT8 DieCount;
+  UINT8 SpecialCaseHeapSize;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED];
+
+  SpecialCaseHeapSize = 0;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  //--------------------------------------------------
+  //  Apply for heap space for special case registers
+  //--------------------------------------------------
+  for (Die = 0; Die < DieCount; Die ++) {
+    // Construct the header for the special case heap.
+    SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node;
+    SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER)));
+    SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize;
+  }
+  AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize;
+  AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER"
+    return AGESA_FATAL;
+  }
+  LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the PCI device register list according to the register
+ *      list ID.
+ *
+ *      @param[in]       *Device - pointer to the PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader);
+
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the conditional PCI device register list according
+ *      to the register list ID.
+ *
+ *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader);
+
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the MSR device register list according to the register
+ *      list ID.
+ *
+ *      @param[in]       *Device - pointer to the MSR_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader);
+
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the conditional MSR device register list according
+ *      to the register list ID.
+ *
+ *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                     *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+
+  AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader);
+
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initialize needed data structures for S3 resume.
+ *
+ *      @param[in, out]  **S3NBPtr - Pointer to the pointer of northbridge block.
+ *      @param[in, out]  *MemPtr - Pointer to MEM_DATA_STRUCT.
+ *      @param[in, out]  *mmData - Pointer to MEM_MAIN_DATA_BLOCK.
+ *      @param[in]       *StdHeader - Config handle for library and services.
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3InitNB (
+  IN OUT   S3_MEM_NB_BLOCK **S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT **MemPtr,
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  AGESA_STATUS RetVal;
+  LOCATE_HEAP_PTR LocHeap;
+  MEM_NB_BLOCK *NBPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 Die;
+  UINT8 DieCount;
+  BOOLEAN SkipScan;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  SkipScan = FALSE;
+  LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr;
+    SkipScan = TRUE;
+  } else {
+    AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+    AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT
+      return AGESA_FATAL;
+    }
+    *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
+    LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(*MemPtr)->StdHeader);
+    FamilySpecificServices->GetTscRate (FamilySpecificServices, &(*MemPtr)->TscRate, &(*MemPtr)->StdHeader);
+
+  }
+  mmData->MemPtr = *MemPtr;
+
+  if (!SkipScan) {
+    RetVal = MemSocketScan (mmData);
+    if (RetVal == AGESA_FATAL) {
+      return RetVal;
+    }
+  } else {
+    // We already have initialize data block, no need to do it again.
+    mmData->DieCount = mmData->MemPtr->DieCount;
+  }
+  DieCount = mmData->DieCount;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  // Search for AMD_MEM_AUTO_HANDLE on the heap first.
+  // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK)));
+    AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK"
+      return AGESA_FATAL;
+    }
+    *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+
+    LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+    if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+      // NB block has already been constructed by main block.
+      // No need to construct it here.
+      NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    } else {
+      AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
+      AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+      AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+      if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+        ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK"
+        return AGESA_FATAL;
+      }
+      NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+    }
+    // Construct each die.
+    for (Die = 0; Die < DieCount; Die ++) {
+      i = 0;
+      ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die];
+      while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) {
+        if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) {
+          break;
+        }
+        i++;
+      };
+      if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
+        ASSERT(FALSE); // S3 resume NB constructor not found
+        return AGESA_FATAL;
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of 10ns cycles
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Count - Number of 10ns cycles to wait
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemFS3Wait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT64 TargetTsc;
+  UINT64 CurrentTsc;
+
+  ASSERT (Count <= 1000000);
+
+  LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
+  TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100);
+  do {
+    LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
+  } while (CurrentTsc < TargetTsc);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c
new file mode 100644
index 0000000000..fc5b3a7e1c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c
@@ -0,0 +1,362 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mftds.c
+ *
+ * Northbridge table drive support file for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/TABLE)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mftds.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MAX_BYTELANES_PER_CHANNEL   (8 + 1)  ///< Max Bytelanes per channel
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+SetTableValues (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS MTPtr
+  );
+
+VOID
+SetTableValuesLoop (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS *MTPtr,
+  IN       UINT8     time
+  );
+
+/*-----------------------------------------------------------------------------
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_TABLE_ALIAS structure
+ *     @param[in]       time     - Indicate the timing for the register which is written.
+ *
+ *     @return          None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemFInitTableDrive (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8     time
+  )
+{
+  MEM_TABLE_ALIAS *MTPtr;
+  MEM_TABLE_ALIAS *IdsMTPtr;
+
+  ASSERT (NBPtr != NULL);
+  IdsMTPtr = NULL;
+  IDS_HDT_CONSOLE (MEM_FLOW, "MemFInitTableDrive [%X] Start\n", time);
+  MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations;
+
+  IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) {
+    IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader));
+  }
+
+  SetTableValuesLoop (NBPtr, MTPtr, time);
+  SetTableValuesLoop (NBPtr, IdsMTPtr, time);
+
+  IDS_OPTION_HOOK (IDS_MT_BASE + time, NBPtr, &(NBPtr->MemPtr->StdHeader));
+  IDS_HDT_CONSOLE (MEM_FLOW, "MemFInitTableDrive End\n");
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MTPtr   - Pointer to the MEM_TABLE_ALIAS structure
+ *     @param[in]       time     - Indicate the timing for the register which is written.
+ *
+ *     @return          None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+SetTableValuesLoop (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS *MTPtr,
+  IN       UINT8     time
+  )
+{
+  UINT8 i;
+  UINT8 CurDct;
+
+  if (MTPtr != NULL) {
+    CurDct = NBPtr->Dct;
+    for (i = 0; MTPtr[i].time != MTEnd; i++) {
+      if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) {
+        SetTableValues (NBPtr, MTPtr[i]);
+      }
+    }
+    NBPtr->SwitchDCT (NBPtr, CurDct);
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *   Engine for setting Table Value.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       MTPtr    - Pointer to the MEM_TABLE_ALIAS structure
+ *
+ *     @return      None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+SetTableValues (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS MTPtr
+  )
+{
+  UINT8 AccessType;
+  UINT16 ByteLane;
+  UINT8 Dct;
+  UINT8 i;
+  UINT8 j;
+  UINT32 TempVal[36];
+  UINT8 *DqsSavePtr;
+  UINT8  DqsOffset;
+  BOOLEAN SaveDqs;
+
+  AccessType = 0;
+  DqsSavePtr = NULL;
+  SaveDqs = TRUE;
+
+  ASSERT (MTPtr.time <= MTValidTimePointLimit);
+  ASSERT (MTPtr.attr <= MTOr);
+  ASSERT (MTPtr.node <= MTNodes);
+  ASSERT (MTPtr.dct <= MTDcts);
+  ASSERT (MTPtr.dimm <= MTDIMMs);
+  ASSERT (MTPtr.data.s.bytelane <= MTBLs);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      switch (MTPtr.bfindex) {
+      case BFRcvEnDly:
+        AccessType = AccessRcvEnDly;
+        DqsSavePtr = NULL;
+        break;
+      case BFWrDatDly:
+        AccessType = AccessWrDatDly;
+        DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys;
+        break;
+      case BFRdDqsDly:
+        AccessType = AccessRdDqsDly;
+        DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys;
+        break;
+      case BFWrDqsDly:
+        AccessType = AccessWrDqsDly;
+        DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys;
+        break;
+      case BFPhRecDly:
+        AccessType = AccessPhRecDly;
+        SaveDqs = FALSE;
+        break;
+      default:
+        AccessType = 0xFF;
+        break;
+      }
+      if (AccessType == 0xFF) {
+        if (MTPtr.attr == MTOverride) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTSubtract) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTAdd) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTAnd) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, (NBPtr->GetBitField (NBPtr, MTPtr.bfindex) & MTPtr.data.s.value));
+        }
+        if (MTPtr.attr == MTOr) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, (NBPtr->GetBitField (NBPtr, MTPtr.bfindex) | MTPtr.data.s.value));
+        }
+      } else {
+        // Store the DQS data first
+        for (i = 0; i < NBPtr->CsPerChannel; i = i + NBPtr->CsPerDelay) {
+            for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+              TempVal[i / NBPtr->CsPerDelay * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i / NBPtr->CsPerDelay, j));
+            }
+        }
+        //
+        // Single Value with Bytleane mask option
+        //   Indicated by the vtype flag
+        //
+        if (MTPtr.vtype == VT_MSK_VALUE) {
+          // set the value which defined in Memory table.
+          for (i = 0; i < NBPtr->CsPerChannel; i = i + NBPtr->CsPerDelay) {
+            ByteLane = MTPtr.data.s.bytelane;
+            if ((MTPtr.dimm == MTDIMMs) || ((MTPtr.dimm * NBPtr->CsPerDelay) == i)) {
+                for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                  DqsOffset = (i / NBPtr->CsPerDelay * MAX_BYTELANES_PER_CHANNEL + j);
+                  if ((ByteLane & (UINT16)1) != 0) {
+                    if (MTPtr.attr == MTOverride) {
+                      TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value;
+                    }
+                    if (MTPtr.attr == MTSubtract) {
+                      TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value;
+                    }
+                    if (MTPtr.attr == MTAdd) {
+                      TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value;
+                    }
+                    NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i / NBPtr->CsPerDelay, j), (UINT16)TempVal[DqsOffset]);
+                    if (SaveDqs) {
+                      if (DqsSavePtr == NULL) {
+                        NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
+                      } else {
+                        DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
+                      }
+                    }
+                  }
+                  ByteLane = ByteLane >> (UINT16)1;
+                }
+            }
+          }
+        } else {
+          // Multiple values specified in a byte array
+          for (i = 0; i < NBPtr->CsPerChannel; i = i + NBPtr->CsPerDelay) {
+            if ((MTPtr.dimm == MTDIMMs) || ((MTPtr.dimm * NBPtr->CsPerDelay) == i)) {
+                for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                  DqsOffset = (i / NBPtr->CsPerDelay * MAX_BYTELANES_PER_CHANNEL + j);
+                  if (MTPtr.attr == MTOverride) {
+                    TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j];
+                  }
+                  if (MTPtr.attr == MTSubtract) {
+                    TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j];
+                  }
+                  if (MTPtr.attr == MTAdd) {
+                    TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j];
+                  }
+                  NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i / NBPtr->CsPerDelay, j), (UINT16)TempVal[DqsOffset]);
+                  if (SaveDqs) {
+                    if (DqsSavePtr == NULL) {
+                      NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
+                    } else {
+                      DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
+                    }
+                  }
+                }
+            }
+          }
+        }
+        // set the DQS value to left DIMMs.
+        i = MTPtr.dimm;
+        if (i != MTDIMMs) {
+          i = i * NBPtr->CsPerDelay + NBPtr->CsPerDelay;
+          while (i < NBPtr->CsPerChannel) {
+              for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i / NBPtr->CsPerDelay, j), (UINT16)TempVal[i / NBPtr->CsPerDelay * MAX_BYTELANES_PER_CHANNEL + j]);
+              }
+            i = i + NBPtr->CsPerDelay;
+          }
+        }
+      }
+    }
+  }
+}
+
+
+
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c
new file mode 100644
index 0000000000..d363e0682c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c
@@ -0,0 +1,389 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmflowtn.c
+ *
+ * Main Memory initialization sequence for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main/TN)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mntn.h"
+#include "mt.h"
+#include "mmlvddr3.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE
+/* features */
+#include "mftds.h"
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+extern OPTION_MEM_FEATURE_MAIN MemMS3Save;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+MemMFlowTN (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function defines the memory initialization flow for
+ *      systems that only support TN processors.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_FATAL
+ *                          - AGESA_CRITICAL
+ *                          - AGESA_SUCCESS
+ */
+AGESA_STATUS
+MemMFlowTN (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ID_INFO CallOutIdInfo;
+
+  NBPtr = MemMainPtr->NBPtr;
+  TechPtr = MemMainPtr->TechPtr;
+  MemPtr = MemMainPtr->MemPtr;
+
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
+    MemPtr->IsFlowControlSupported = FALSE;
+    return AGESA_FATAL;
+  } else {
+    MemPtr->IsFlowControlSupported = TRUE;
+  }
+
+  MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeInitializeMCT);
+
+  //----------------------------------------------------------------
+  // Initialize MCT
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].InitializeMCT (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Low voltage DDR3
+  //----------------------------------------------------------------
+  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
+  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Initialize DRAM and DCTs
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
+  // Initialize Memory Controller and Dram
+  if (!NBPtr[BSP_DIE].InitMCT (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL; //fatalexit
+  }
+
+  MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeDInit);
+
+  //------------------------------------------------
+  // Finalize target frequency
+  //------------------------------------------------
+  if (!MemMLvDdr3PerformanceEnhFinalize (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //------------------------------------------------
+  // Callout before Dram Init
+  //------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(MemMainPtr->MemPtr->StdHeader));
+  CallOutIdInfo.IdField.SocketId = NBPtr[BSP_DIE].MCTPtr->SocketId;
+  CallOutIdInfo.IdField.ModuleId = NBPtr[BSP_DIE].MCTPtr->DieId;
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d, Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId);
+  AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, MemMainPtr->MemPtr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr[BSP_DIE].RefPtr->DDR3Voltage == VOLT1_5) ? 5 :
+                                        (NBPtr[BSP_DIE].RefPtr->DDR3Voltage == VOLT1_35) ? 35 :
+                                        (NBPtr[BSP_DIE].RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);
+  AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+
+  //-------------------------------------------------
+  // Do dram init and create memory map
+  //-------------------------------------------------
+  IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, &NBPtr[BSP_DIE], &(MemMainPtr->MemPtr->StdHeader));
+  NBPtr[BSP_DIE].StartupDCT (&NBPtr[BSP_DIE]);
+
+  // Create memory map
+  AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].HtMemMapInit (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------
+  // If there is no dimm on the system, do fatal exit
+  //----------------------------------------------------
+  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // CpuMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Before Training Table values
+  //----------------------------------------------------------------
+  MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeTrn);
+
+  //----------------------------------------------------------------
+  // Memory Context Restore
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemRestore (MemMainPtr)) {
+    // Do DQS training only if memory context restore fails
+
+    //----------------------------------------------------------------
+    // Training
+    //----------------------------------------------------------------
+    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
+    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
+    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
+      if (!MemFeatMain.Training (MemMainPtr)) {
+        return AGESA_FATAL;
+      }
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
+  }
+
+  //----------------------------------------------------------------
+  // Disable chipselects that fail training
+  //----------------------------------------------------------------
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
+  MemFeatMain.ExcludeDIMM (MemMainPtr);
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
+
+  //----------------------------------------------------------------
+  // OtherTiming
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].OtherTiming (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // After Training Table values
+  //----------------------------------------------------------------
+  MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterTrn);
+
+  //----------------------------------------------------------------
+  // Interleave channels
+  //----------------------------------------------------------------
+  if (NBPtr[BSP_DIE].FeatPtr->InterleaveChannels (&NBPtr[BSP_DIE])) {
+    if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Interleave banks
+  //----------------------------------------------------------------
+  if (NBPtr[BSP_DIE].FeatPtr->InterleaveBanks (&NBPtr[BSP_DIE])) {
+    if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // After Programming Interleave registers
+  //----------------------------------------------------------------
+  MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterInterleave);
+
+  //----------------------------------------------------------------
+  // Memory Clear
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.MemClr (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // C6 Storage Allocation
+  //----------------------------------------------------------------
+  NBPtr[BSP_DIE].AllocateC6Storage (&NBPtr[BSP_DIE]);
+
+  //----------------------------------------------------------------
+  // UMA Allocation & UMAMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave region
+  //----------------------------------------------------------------
+  NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
+
+  //----------------------------------------------------------------
+  // OnDimm Thermal
+  //----------------------------------------------------------------
+  if (NBPtr[BSP_DIE].FeatPtr->OnDimmThermal (&NBPtr[BSP_DIE])) {
+    if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Finalize MCT
+  //----------------------------------------------------------------
+  if (!NBPtr[BSP_DIE].FinalizeMCT (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // After Finalize MCT
+  //----------------------------------------------------------------
+  MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterFinalizeMCT);
+
+  //----------------------------------------------------------------
+  // Memory Context Save
+  //----------------------------------------------------------------
+  MemFeatMain.MemSave (MemMainPtr);
+
+  //----------------------------------------------------------------
+  // Memory DMI support
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemDmi (MemMainPtr)) {
+    return AGESA_CRITICAL;
+  }
+
+
+  //----------------------------------------------------------------
+  // Save memory S3 data
+  //----------------------------------------------------------------
+  if (!MemMS3Save (MemMainPtr)) {
+    return AGESA_CRITICAL;
+  }
+
+  //----------------------------------------------------------------
+  // Switch back to DCT 0 before sending control back
+  //----------------------------------------------------------------
+  NBPtr[BSP_DIE].SwitchDCT (&NBPtr[BSP_DIE], 0);
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c
new file mode 100644
index 0000000000..243b048d65
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c
@@ -0,0 +1,173 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mdef.c
+ *
+ * Memory Controller header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Filecode.h"
+#include "mm.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+MemMFlowDef (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is the default return function
+ */
+
+VOID
+memDefRet ( VOID )
+{
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is the default return function that returns TRUE
+ *
+ */
+BOOLEAN
+memDefTrue ( VOID )
+{
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is used in place of an un-supported function that returns FALSE.
+ *
+ */
+BOOLEAN
+memDefFalse ( VOID )
+{
+  return FALSE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is the default return function for flow control
+ */
+AGESA_STATUS
+MemMFlowDef (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  MemMainPtr->MemPtr->IsFlowControlSupported = FALSE;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is used in place of an un-supported function that returns AGESA_SUCCESS.
+ *
+ */
+AGESA_STATUS
+memDefRetSuccess ( VOID )
+{
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
new file mode 100644
index 0000000000..8b46a49640
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
@@ -0,0 +1,214 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * merrhdl.c
+ *
+ * Memory error handling
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "heapManager.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function handle errors occur in memory code.
+ *
+ *
+ *     @param[in,out]   *MCTPtr - pointer to DIE_STRUCT.
+ *     @param[in,out]   DCT - DCT that needs to be handled.
+ *     @param[in,out]   ChipSelMask - Chip select mask that needs to be handled
+ *     @param[in,out]   *StdHeader - pointer to AMD_CONFIG_PARAMS
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemErrHandle (
+  IN       DIE_STRUCT *MCTPtr,
+  IN       UINT8  DCT,
+  IN       UINT16  ChipSelMask,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN ErrorRecovery;
+  BOOLEAN IgnoreErr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 CurrentDCT;
+  LOCATE_HEAP_PTR LocHeap;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_MAIN_DATA_BLOCK mmData;
+
+  DCTPtr = MCTPtr->DctData;
+  ErrorRecovery = TRUE;
+  IgnoreErr = FALSE;
+  IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader);
+
+  if (ErrorRecovery) {
+    if (DCT == EXCLUDE_ALL_DCT) {
+      // Exclude all DCTs on a node
+      for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) {
+        DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent;
+      }
+    } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) {
+      // Exclude the specified DCT
+      DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent;
+    } else {
+      // Exclude the chip select that has been marked out
+      DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent;
+      IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader);
+    }
+
+    // Exclude the failed dimm to recovery from error
+    if (MCTPtr->NodeMemSize != 0) {
+      LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+      if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+        // NB block has already been constructed by main block.
+        // No need to construct it here.
+        NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+        if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) {
+          // Memory map has not been calculated, no need to remap memory across node here.
+          // Only need to remap memory within the node.
+          NBPtr = &NBPtr[MCTPtr->NodeId];
+          NBPtr->FeatPtr->ExcludeDIMM (NBPtr);
+        } else {
+          // Need to remap memory across the whole system.
+          mmData.MemPtr = NBPtr->MemPtr;
+          mmData.mmSharedPtr = NBPtr->SharedPtr;
+          mmData.NBPtr = NBPtr;
+          mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]);
+          mmData.DieCount = NBPtr->MemPtr->DieCount;
+          if (!MemFeatMain.ExcludeDIMM (&mmData)) {
+            return FALSE;
+          }
+        }
+      }
+      // If allocation fails, that means the code is not running at BSP.
+      // Parallel training is in process.
+      // Remap for parallel training will be done when control returns to BSP.
+    }
+    return TRUE;
+  } else {
+    IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader);
+    if (IgnoreErr) {
+      return TRUE;
+    }
+    SetMemError (AGESA_FATAL, MCTPtr);
+    // ErrorRecovery is FALSE
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c
new file mode 100644
index 0000000000..41b83cfb88
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c
@@ -0,0 +1,164 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * minit.c
+ *
+ * Initializer support function
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "AdvancedApi.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "Ids.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function initializes the default parameter, function pointers, build options
+ *   and SPD data for memory configuration
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   *PlatFormConfig -  Platform profile/build option config structure
+ *
+ */
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   PLATFORM_CONFIGURATION   *PlatFormConfig
+  )
+{
+  UINT8 p;
+  UINT8 i;
+  // We need a way of specifying default values for each particular northbridge
+  // family.  We also need to make sure that the IBV knows which parameter struct
+  // is for which northbridge.
+  //----------------------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader);
+
+  MemPtr->PlatFormConfig = PlatFormConfig;
+
+  memNBInstalled[0].MemNInitDefaults (MemPtr);
+
+  //----------------------------------------------------------------------------
+  // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT
+  //----------------------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader);
+  i = 0;
+  for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+    if (memPlatformTypeInstalled[i] != NULL) {
+      MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i];
+      i++;
+    } else {
+      MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef;
+    }
+  }
+  AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader);
+  MemPtr->ErrorHandling = MemErrHandle;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c
new file mode 100644
index 0000000000..0a2b8e1ff4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c
@@ -0,0 +1,279 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mm.c
+ *
+ * Main Memory Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MM_FILECODE
+/* features */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function deallocates heap buffers that were allocated in AmdMemAuto
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemAmdFinalize (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Die;
+
+  for (Die = 0; Die < MemPtr->DieCount; Die++ ) {
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader);
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader);
+  }
+
+  HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader);
+  HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader);
+  HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader);
+  HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ * MemSocketScan - Scan all nodes, recording the physical Socket number,
+ * Die Number (relative to the socket), and PCI Device address of each
+ * populated socket.
+ *
+ * This information is used by the northbridge block to map a dram
+ * channel on a particular DCT, on a particular CPU Die, in a particular
+ * socket to a the DRAM SPD Data for the DIMMS physically connected to
+ * that channel.
+ *
+ * Also, the customer socket map is populated with pointers to the
+ * appropriate channel structures, so that the customer can locate the
+ * appropriate channel configuration data.
+ *
+ * This socket scan will always result in Die 0 as the BSP.
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+AGESA_STATUS
+MemSocketScan (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  UINT8 DieIndex;
+  UINT8 DieCount;
+  UINT32 SocketId;
+  UINT32 DieId;
+  UINT8 Die;
+  PCI_ADDR Address;
+  AGESA_STATUS AgesaStatus;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (mmPtr != NULL);
+  ASSERT (mmPtr->MemPtr != NULL);
+  MemPtr = mmPtr->MemPtr;
+
+  //
+  //  Count the number of dies in the system
+  //
+  DieCount = 0;
+  for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {
+    if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {
+      DieCount++;
+    }
+  }
+  MemPtr->DieCount = DieCount;
+  mmPtr->DieCount = DieCount;
+
+  if (DieCount > 0) {
+    //
+    //  Allocate buffer for DIE_STRUCTs
+    //
+    AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT));
+    AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+      MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;
+      //
+      //  Find SocketId, DieId, and PCI address of each node
+      //
+      DieIndex = 0;
+      for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {
+        if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {
+          if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) {
+            MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId;
+            MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId;
+            MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue;
+
+            DieIndex++;
+          }
+        }
+      }
+      AgesaStatus = AGESA_SUCCESS;
+    } else {
+      ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs
+      AgesaStatus = AGESA_FATAL;
+    }
+  } else {
+    ASSERT(FALSE); // No die in the system
+    AgesaStatus = AGESA_FATAL;
+  }
+  return AgesaStatus;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function sets memory errors into MemDataStruct
+ *
+ *
+ *     @param[in,out]   *MCTPtr  - Pointer to the DIE_STRUCT
+ *     @param[in]       Errorval - Error value to update
+ */
+
+VOID
+SetMemError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  )
+{
+  if (MCTPtr->ErrCode < Errorval) {
+    MCTPtr->ErrCode = Errorval;
+  }
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is default function for the fultion list
+ *
+ *     @param[in,out]   *pMemData   - Pointer to the MEM_DATA_STRUCT
+ */
+VOID
+AmdMemFunctionListDef (
+  IN OUT   VOID *pMemData
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c
new file mode 100644
index 0000000000..f543d397c0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c
@@ -0,0 +1,722 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmConditionalPso.c
+ *
+ * Functions to support conditional entries in the Platform Specific Override Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define PSO_TYPE    0
+#define PSO_LENGTH  1
+#define PSO_DATA    2
+
+typedef enum _PSO_STATE {
+  PSO_FIND_CONDITION = 100,  // Searching for initial Condition statement
+  PSO_FIND_ACTION,           // Searching for initial Action Statement
+  PSO_MATCH_ACTION,          // Trying to find an action that matches the caller's request
+  PSO_CHECK_CONDITION,       // Checking the condition that preceded the found action
+  PSO_DO_ACTION,             // Performing Action
+  PSO_COMPLETE               // Completed processing of this request
+} PSO_STATE;
+
+typedef struct _D3_CMP_CAL {
+  UINT32 D3Cmp0NCal   :3;
+  UINT32 Reserved34   :2;
+  UINT32 D3Cmp0PCal   :3;
+  UINT32 Reserved89   :2;
+  UINT32 D3Cmp1NCal   :3;
+  UINT32 Reserved1314 :2;
+  UINT32 D3Cmp1PCal   :3;
+  UINT32 Reserved1819 :2;
+  UINT32 D3Cmp2NCal   :3;
+  UINT32 Reserved2324 :2;
+  UINT32 D3Cmp2PCal   :3;
+  UINT32 Reserved2831 :2;
+} D3_CMP_CAL;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+ STATIC
+ MemPSODoActionODT (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+ BOOLEAN
+ STATIC
+ MemPSODoActionAddrTmg (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+ BOOLEAN
+ STATIC
+ MemPSODoActionODCControl (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+ BOOLEAN
+ STATIC
+ MemPSODoActionSlewRate (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+BOOLEAN
+STATIC
+MemPSODoActionGetFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+BOOLEAN
+STATIC
+MemCheckRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel,
+  IN       UINT16 RankType
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Process Conditional Platform Specific Overrides
+ *
+ *      @param[in] PlatformMemoryConfiguration - Pointer to Platform config table
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] PsoAction - Action type
+ *      @param[in] Dimm - Dimm Number
+ *
+ *      @return          BOOLEAN -            TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemProcessConditionalOverrides (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 PsoAction,
+  IN       UINT8 Dimm
+  )
+{
+  BOOLEAN Result;
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 *Buffer;
+  UINT8 *ConditionStartPtr;
+  UINT8 *ActionStartPtr;
+  UINT8 *SpdBufferPtr;
+  UINT8 i;
+  UINT8 DimmMask;
+  UINT8 CurDimmMask;
+  BOOLEAN Condition;
+  BOOLEAN TmpCond;
+  PSO_STATE State;
+  ASSERT (PlatformMemoryConfiguration != NULL);
+  ASSERT (NBPtr != NULL);
+  ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX));
+  //
+  // Set up local data
+  //
+  TechPtr = NBPtr->TechPtr;
+  Buffer = PlatformMemoryConfiguration;
+  State = PSO_FIND_CONDITION;
+  ConditionStartPtr = NULL;
+  ActionStartPtr = NULL;
+  Condition = FALSE;
+  DimmMask = 0xFF;
+  CurDimmMask = 0xFF;
+  Result = FALSE;
+
+  if (Dimm != 0xFF) {
+    DimmMask = ( 1 << Dimm);
+  }
+  DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF);
+  if (DimmMask == 0) {
+    return Result;
+  }
+
+  //
+  // Search for Condition Entry
+  //
+  while (State != PSO_COMPLETE) {
+    switch (State) {
+    //
+    // Searching for initial Condition statement
+    //
+    case PSO_FIND_CONDITION:
+      ASSERT (Buffer != NULL);
+      while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) {
+        //
+        // If end of table is reached, Change state to complete and break.
+        //
+        if (Buffer[PSO_TYPE] == PSO_END) {
+          State = PSO_COMPLETE;
+          break;
+        }
+        //
+        // Otherwise, increment Buffer Pointer to the next PSO entry.
+        //
+        Buffer += (Buffer[PSO_LENGTH] + 2);
+      }
+      //
+      // If Condition statement has been found, save the Condition Start Pointer,
+      //  and change to next state
+      //
+      if (State != PSO_COMPLETE) {
+        ASSERT (Buffer != NULL);
+        State = PSO_FIND_ACTION;
+        ConditionStartPtr = Buffer;
+        Buffer += (Buffer[PSO_LENGTH] + 2);
+      }
+      break;
+    //
+    // Searching for an action that matches the caller's request
+    //
+    case PSO_FIND_ACTION:
+      ASSERT (Buffer != NULL);
+      while (Buffer[PSO_TYPE] != PsoAction) {
+        //
+        // If non-conditional entry, change state to complete and break.
+        //
+        if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) {
+          State = PSO_COMPLETE;
+          break;
+        }
+        //
+        // Check for the Start of a new condition block
+        //
+        if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) {
+          ConditionStartPtr = Buffer;
+        }
+        //
+        // Otherwise, increment buffer pointer to the next PSO entry.
+        //
+        Buffer += (Buffer[PSO_LENGTH] + 2);
+      }
+      //
+      // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start
+      //  and Change to next state.
+      //
+      if (State != PSO_COMPLETE) {
+        State = PSO_CHECK_CONDITION;
+        ASSERT (Buffer != NULL);
+        ActionStartPtr = Buffer;
+        Buffer = ConditionStartPtr;
+        Condition = TRUE;
+      }
+      break;
+    //
+    // Checking the condition that preceded the found action
+    //
+    case PSO_CHECK_CONDITION:
+      ASSERT (Buffer != NULL);
+      //
+      // Point to the next Condition
+      //
+      Buffer += (Buffer[PSO_LENGTH] + 2);
+      ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX));
+      //
+      // This section has already been checked for invalid statements so just exit on ACTION_xx
+      //
+      if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) {
+        if (Condition) {
+          ASSERT (Buffer != NULL);
+          State = PSO_DO_ACTION;              // Perform the Action
+        } else {
+          State = PSO_FIND_CONDITION;         // Go back and look for another condition/action
+        }
+        Buffer = ActionStartPtr;              // Restore Action Pointer
+        break;
+      }
+      switch (Buffer[PSO_TYPE]) {
+
+      case PSO_CONDITION_AND:
+        //
+        // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE
+        //  just restore action pointer and perform the action.
+        //
+        if (Condition) {
+          State = PSO_DO_ACTION;
+          Buffer = ActionStartPtr;
+        } else {
+          //
+          // If its false, Start over and evaluate next cond.
+          // reset the Current Dimm Mask
+          //
+          Condition = TRUE;
+          CurDimmMask = 0xFF;
+        }
+        break;
+
+      case PSO_CONDITION_LOC:
+        //
+        // Condition location
+        //
+        CurDimmMask = Buffer[4];
+        Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) &&
+                       ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) &&
+                       ((CurDimmMask & DimmMask) != 0) );
+        break;
+
+      case PSO_CONDITION_SPD:
+        //
+        // Condition SPD
+        //
+        TmpCond = FALSE;
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+          if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) {
+            if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) {
+              TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]);
+            }
+          }
+        }
+        Condition &= TmpCond;
+        break;
+
+      case PSO_CONDITION_REG:
+        //
+        // Condition Register - unsupported at this time
+        //
+        break;
+
+      default:
+        ASSERT (FALSE);
+      } // End Condition Switch
+    break;
+
+    case PSO_DO_ACTION:
+      ASSERT (Buffer != NULL);
+      //
+      // Performing Action
+      //
+      if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) {
+        State = PSO_COMPLETE;
+      }
+      if (Buffer[PSO_TYPE] == PsoAction) {
+        switch (Buffer[PSO_TYPE]) {
+        case PSO_ACTION_ODT:
+          Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_ADDRTMG:
+          Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_ODCCONTROL:
+          Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_SLEWRATE:
+          Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_SPEEDLIMIT:
+          Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_REG:
+          break;
+        default:
+          ASSERT (FALSE);
+        } // End Action Switch
+        //
+        // If Action was performed, mark complete.
+        //
+        if (Result) {
+          State = PSO_COMPLETE;
+        }
+    }// End Action
+
+      //
+      // Point to the next PSO Entry
+      //
+      Buffer += (Buffer[PSO_LENGTH] + 2);
+      break;
+
+    case PSO_COMPLETE:
+      //
+      // Completed processing of this request
+      //
+      break;
+
+    default:
+      ASSERT (FALSE);
+    } // End State Switch
+
+  } // End While
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *      Perform ODT Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return         BOOLEAN -             TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionODT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  UINT32 Speed;
+  UINT8 Dimms;
+  UINT8 i;
+  UINT8 QR_Dimms;
+  Result = FALSE;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  Dimms = NBPtr->ChannelPtr->Dimms;
+  QR_Dimms = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) {
+      QR_Dimms ++;
+    }
+  }
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) {
+      if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) ||
+          ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) ||
+           (Buffer[5] == ANY_NUM)) {
+        NBPtr->PsPtr->DramTerm = Buffer[6];
+        NBPtr->PsPtr->QR_DramTerm = Buffer[7];
+        NBPtr->PsPtr->DynamicDramTerm = Buffer[8];
+        Result = TRUE;
+        IDS_HDT_CONSOLE (MEM_FLOW, "      Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]);
+      }
+    }
+  }
+  return Result;
+ }
+
+ /* -----------------------------------------------------------------------------*/
+/**
+ *      Perform Address Timing Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return          BOOLEAN -             TRUE : Action was performed
+ *                                             FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionAddrTmg (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT32 Speed;
+  UINT16 DimmConfig;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  DimmConfig = *(UINT16 *) &(Buffer[4]);
+
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]);
+      Result = TRUE;
+      IDS_HDT_CONSOLE (MEM_FLOW, "      Platform Override: Address Timing:%08x\n", *(UINT32*) &(Buffer[6]));
+    }
+  }
+  return Result;
+ }
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *      Perform Drive Strength Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return          BOOLEAN -             TRUE : Action was performed
+ *                                             FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionODCControl (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT32 Speed;
+  UINT16 DimmConfig;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  DimmConfig = *(UINT16 *) &(Buffer[4]);
+
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]);
+      Result = TRUE;
+      IDS_HDT_CONSOLE (MEM_FLOW, "      Platform Override: ODC Control:%08x\n", *(UINT32*)&(Buffer[6]));
+    }
+  }
+  return Result;
+ }
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *      Perform Slew Rate Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *     @return          BOOLEAN -             TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionSlewRate (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT32 Speed;
+  UINT16 DimmConfig;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  DimmConfig = *(UINT16 *) &(Buffer[4]);
+
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal );
+      Result = TRUE;
+      IDS_HDT_CONSOLE (MEM_FLOW, "      Platform Override: Slew Rate:%08x\n", *(UINT32 *) &(Buffer[6]));
+    }
+  }
+  return Result;
+ }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides the  POR supported speed for a specific config
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return          BOOLEAN -            TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ */
+BOOLEAN
+STATIC
+MemPSODoActionGetFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT16 DimmConfig;
+  UINT16 SpeedLimit;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  DimmConfig = *(UINT16*) &(Buffer[0]);
+  SpeedLimit = 0;
+  //
+  // Match number of dimms, then Rank Type
+  //
+  if (ChannelPtr->Dimms == Buffer[2]) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      //
+      // Select speed based on current voltage
+      //
+      if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+        SpeedLimit = *(UINT16*) &(Buffer[3]);
+      } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) {
+        SpeedLimit = *(UINT16*) &(Buffer[7]);
+      } else {
+        SpeedLimit = *(UINT16*) &(Buffer[5]);
+      }
+      //
+      // Set the Speed limit
+      //
+      if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+        DCTPtr->Timings.TargetSpeed = SpeedLimit;
+      }
+      Result = TRUE;
+      IDS_HDT_CONSOLE (MEM_FLOW, "      Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit);
+    }
+  }
+  return Result;
+}
+
+ /* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function matches a particular Rank Type Mask to the installed
+ *    DIMM configuration on the provided channel.
+ *
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *     @param[in]       RankType              Mask of rank type to match
+ *
+ *     @return          BOOLEAN -             TRUE : Rank types match
+ *                                            FALSE: Rank types do not match
+ *
+ */
+BOOLEAN
+STATIC
+MemCheckRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel,
+  IN       UINT16 RankType
+  )
+{
+  BOOLEAN Result;
+  UINT8 i;
+  UINT16 DIMMRankType;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+  Result = TRUE;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) {
+      Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0);
+    }
+    if (!Result) {
+      break;
+    }
+  }
+  return Result;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c
new file mode 100644
index 0000000000..b8aef6609e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c
@@ -0,0 +1,162 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmEcc.c
+ *
+ * Main Memory Feature implementation file for ECC Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mfmemclr.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemMEcc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMEcc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  UINT8 Die;
+  MEM_SHARED_DATA *SharedPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  BOOLEAN RetVal;
+
+  RetVal = TRUE;
+  RefPtr = mmPtr->MemPtr->ParameterListPtr;
+  SharedPtr = mmPtr->mmSharedPtr;
+
+  //
+  // Run Northbridge-specific ECC initialization feature for each die.
+  //
+  SharedPtr->AllECC = FALSE;
+  if (RefPtr->EnableEccFeature) {
+    SharedPtr->AllECC = TRUE;
+    AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader));
+
+    for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
+      mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die]));
+      RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL);
+    }
+    if (SharedPtr->AllECC == TRUE) {
+      RefPtr->GStatus[GsbAllECCDimms] = TRUE;
+      // Sync mem clear before setting scrub rate.
+      for (Die = 0; Die < mmPtr->DieCount; Die++) {
+        MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die]));
+      }
+    }
+  }
+  // Scrubber control
+  for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
+    mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die]));
+  }
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c
new file mode 100644
index 0000000000..18dbe48763
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c
@@ -0,0 +1,271 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmExcludeDimm.c
+ *
+ * Main Memory Feature implementation file for RAS DIMM Exclude Feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mport.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMRASExcludeDIMM (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and disable Chip selects that fail training on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMRASExcludeDIMM (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  BOOLEAN IsEnabled;
+  BOOLEAN RetVal;
+  BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED];
+  UINT8   FirstEnabledNode;
+  UINT32  BottomIO;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  S_UINT64 SMsr;
+
+  FirstEnabledNode = 0;
+  IsEnabled = FALSE;
+  RetVal = TRUE;
+  NBPtr = MemMainPtr->NBPtr;
+  RefPtr = NBPtr[BSP_DIE].RefPtr;
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) {
+      if (!IsEnabled) {
+        // Record the first node that has exclude dimm enabled
+        FirstEnabledNode = Node;
+        IsEnabled = TRUE;
+      }
+    }
+  }
+
+  // Force memory address remap when we want to undo 1TB hoisting
+  if (NBPtr->SharedPtr->UndoHoistingAbove1TB) {
+    IsEnabled = TRUE;
+  }
+
+  if (IsEnabled) {
+    // Check if all nodes have all dimms excluded. If yes, fatal exit
+    NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
+    BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
+    // If the first node that has excluded dimms does not have a system base smaller
+    // than bottomIO, then we don't need to reset the GStatus, as we don't need to
+    // remap memory hole.
+    if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
+      RefPtr->GStatus[GsbHWHole] = FALSE;
+      RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
+      RefPtr->GStatus[GsbSoftHole] = FALSE;
+      RefPtr->HoleBase = 0;
+      RefPtr->SysLimit = 0;
+    }
+    // If Node Interleaving has been executed before the remapping then we need to
+    // start from the first node.
+    // There may be a few senarios:
+    // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after
+    //    remap
+    // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after
+    //    remap
+    // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap
+    if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
+      FirstEnabledNode = 0;
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      IsChannelIntlvEnabled [Node] = FALSE;
+      // Check if node interleaving has been enabled on this node
+      // if yes, disable it.
+      if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) {
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0);
+      }
+      if (Node >= FirstEnabledNode) {
+        // Remap memory on nodes with node number larger than the first node that has excluded dimms.
+        // If channel interleaving has already been enabled, need to disable it before remapping memory.
+        if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) {
+          NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0);
+          IsChannelIntlvEnabled [Node] = TRUE;
+        }
+        NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
+        NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
+      } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
+        // No change is needed in the memory map of this node.
+        // Need to adjust the current system base for other nodes processed later.
+        NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
+        RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit;
+        // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
+        // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
+        // and DramMemHoistValid.
+        // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
+        // DramHoleValid.
+        if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
+          NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        }
+      }
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
+    }
+
+    LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+    // Only when TOM is set can CpuMemTyping be re-run
+    if ((SMsr.hi != 0) || (SMsr.lo != 0)) {
+      if (RefPtr->SysLimit != 0) {
+        NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
+
+        // When 1TB hoisting is not supported, TOP_MEM2 cannot exceed HT reserved region base.
+        if ((RefPtr->SysLimit >= HT_REGION_BASE_RJ16) && (NBPtr->SharedPtr->UndoHoistingAbove1TB)) {
+          SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16);
+          SMsr.lo = HT_REGION_BASE_RJ16 << 16;
+          LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+          IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", HT_REGION_BASE_RJ16);
+          RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16;
+          RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1;
+        }
+      }
+    }
+
+    // Re-run node interleaving if it has been exeucuted before the remap
+    if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
+      MemFeatMain.InterleaveNodes (MemMainPtr);
+    }
+
+    // Re-enable channel interleaving if it was enabled before remapping memory
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      if (IsChannelIntlvEnabled [Node]) {
+        NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]);
+      }
+    }
+
+    // Reset UndoHoistingAbove1TB if it was previously set
+    NBPtr->SharedPtr->UndoHoistingAbove1TB = FALSE;
+  }
+
+  // if all dimms on all nodes are excluded, do fatal exit
+  if (RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
+    ASSERT (FALSE);
+  }
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+  }
+
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
new file mode 100644
index 0000000000..b0445e7f79
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
@@ -0,0 +1,331 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmLvDdr3.c
+ *
+ * Main Memory Feature implementation file for low voltage DDR3 support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mmlvddr3.h"
+#include "GeneralServices.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMLvDdr3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Find the common supported voltage on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMLvDdr3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  BOOLEAN RetVal;
+  BOOLEAN SecondLoop;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *ParameterPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  mmSharedPtr = MemMainPtr->mmSharedPtr;
+  ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
+  mmSharedPtr->VoltageMap = 0xFF;
+  SecondLoop = FALSE;
+  RetVal = TRUE;
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]);
+    // Check if there is no common supported voltage
+    if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) {
+      // restart node loop by setting node to 0xFF
+      Node = 0xFF;
+      SecondLoop = TRUE;
+    }
+  }
+
+  if (mmSharedPtr->VoltageMap == 0) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo commonly supported VDDIO is found.\n");
+    PutEventLog (AGESA_WARNING, MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader));
+    SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr);
+    // When there is no commonly supported VDDIO, use 1.35V as the temporal VDDIO
+    ParameterPtr->DDR3Voltage = VOLT1_35;
+  } else {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nCommonly supported VDDIO is: %s%s%s.\n", ((mmSharedPtr->VoltageMap & 1) != 0) ? "1.5V, " : "", ((mmSharedPtr->VoltageMap & 2) != 0) ? "1.35V, " : "", ((mmSharedPtr->VoltageMap & 4) != 0) ? "1.25V" : "");
+    ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (LibAmdBitScanReverse (mmSharedPtr->VoltageMap));
+  }
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+    // Check if the voltage needs force to 1.5V
+    NBPtr[Node].FamilySpecificHook[ForceLvDimmVoltage] (&NBPtr[Node], MemMainPtr);
+
+    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+  }
+
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Find the common supported voltage on all nodes, taken into account of the
+ *  user option for performance and power saving.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMLvDdr3PerformanceEnhPre (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8 Node;
+  BOOLEAN RetVal;
+  DIMM_VOLTAGE VDDIO;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_PARAMETER_STRUCT *ParameterPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+  PLATFORM_POWER_POLICY PowerPolicy;
+  UINT8 *PowerPolicyPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  mmSharedPtr = MemMainPtr->mmSharedPtr;
+  ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
+  PowerPolicyPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMORY_POWER_POLICY, 0, 0, 0, NULL, NULL);
+  if (PowerPolicyPtr != NULL) {
+    PowerPolicy = (PLATFORM_POWER_POLICY) *PowerPolicyPtr;
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nPlatform overrides memory power policy");
+  } else {
+    PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;
+  }
+
+  IDS_OPTION_HOOK (IDS_MEMORY_POWER_POLICY, &PowerPolicy, &NBPtr->MemPtr->StdHeader);
+  IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "\nMaximize Performance\n" : "\nMaximize Battery Life\n");
+
+  if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) {
+    mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
+    PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader));
+    SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr);
+    IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed.\n");
+    RetVal = TRUE;
+  } else {
+    RetVal = MemMLvDdr3 (MemMainPtr);
+
+    VDDIO = ParameterPtr->DDR3Voltage;
+    if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) {
+      // When there is no commonly supported voltage, do not optimize performance
+      // For cases where we can maximize performance, do the following
+      // When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO
+      // So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance.
+      ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
+    }
+
+    IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);
+
+    if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {
+      // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance
+      mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
+      IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done.\n");
+    } else {
+      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+        NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
+        NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
+        NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
+      }
+      // Reprogram the leveling result as temporal candidate
+      ParameterPtr->DDR3Voltage = VDDIO;
+    }
+  }
+
+  ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED);
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Finalize the VDDIO for the board for performance enhancement.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMLvDdr3PerformanceEnhFinalize (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Node;
+  UINT8 NodeCnt[VOLT1_25 + 1];
+  UINT8 MaxCnt;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_PARAMETER_STRUCT *ParameterPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+  UINT8 CurrentVoltage;
+  DIMM_VOLTAGE Voltage;
+  MEMORY_BUS_SPEED HighestFreq;
+
+  ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
+  mmSharedPtr = MemMainPtr->mmSharedPtr;
+  NBPtr = MemMainPtr->NBPtr;
+
+  LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader);
+  if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
+    Voltage = ParameterPtr->DDR3Voltage;
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n");
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      HighestFreq = 0;
+      // Find out what the highest frequency that can be reached is on this node across different voltage.
+      for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
+        if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) {
+          HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage];
+        }
+      }
+      IDS_HDT_CONSOLE (MEM_FLOW, "Node%d: 1.5V -> %dMHz, 1.35V -> %dMHz, 1.25V -> %dMHz\n", Node, NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL]);
+      // Figure out what voltage we can have when attaining the highest frequency.
+      for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
+        if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) {
+          NodeCnt[CurrentVoltage] ++;
+        }
+      }
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "Number of nodes that can run at maximize performance: 1.5V -> %d Nodes 1.35V -> %d Nodes 1.25V -> %d Nodes.\n", NodeCnt[VOLT1_5_ENCODED_VAL], NodeCnt[VOLT1_35_ENCODED_VAL], NodeCnt[VOLT1_25_ENCODED_VAL]);
+    MaxCnt = 0;
+    // Use the VDDIO at which most nodes can run at higher frequency
+    for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
+      if (MaxCnt <= NodeCnt[CurrentVoltage]) {
+        MaxCnt = NodeCnt[CurrentVoltage];
+        ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (CurrentVoltage);
+      }
+    }
+
+    ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED);
+
+    mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
+    if (Voltage != ParameterPtr->DDR3Voltage) {
+      // Finalize frequency with updated finalized VDDIO
+      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+        // Need to re-sync target speed and different VDDIO may cause different settings
+        NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr);
+        for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) {
+          NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct);
+          if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) {
+            if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) {
+              return FALSE;
+            }
+          }
+        }
+      }
+    }
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c
new file mode 100644
index 0000000000..78fa3d427f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmMemclr.c
+ *
+ * Main Memory Feature implementation file for Memory Clear.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "mfmemclr.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMMctMemClr (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Initiates/synchronizes memory clear on all nodes with Dram on it.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMMctMemClr (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  BOOLEAN RetVal;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  NodeCnt = MemMainPtr->DieCount;
+  RetVal = TRUE;
+
+  IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader);
+
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFMctMemClr_Init (&NBPtr[Node]);
+  }
+
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFMctMemClr_Sync (&NBPtr[Node]);
+    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+  }
+
+  return RetVal;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c
new file mode 100644
index 0000000000..4ca5e8cb99
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c
@@ -0,0 +1,698 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmMemRestore.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE
+
+#define ST_PRE_ESR  0
+#define ST_POST_ESR 1
+#define ST_DONE     2
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemMRestoreDqsTimings (
+  IN       VOID                *Storage,
+  IN       MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+STATIC
+MemMSetCSRNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       PCI_SPECIAL_CASE *SpecialCases,
+  IN       PCI_ADDR PciAddr,
+  IN       UINT32 Value
+  );
+
+VOID
+STATIC
+MemMCreateS3NbBlock (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr,
+     OUT   S3_MEM_NB_BLOCK **S3NBPtr
+  );
+
+VOID
+MemMContextSave (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+MemMContextRestore (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+BOOLEAN
+MemMS3Save (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and save memory context if possible.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+VOID
+MemMContextSave (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8 Node;
+  UINT8 i;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  LOCATE_HEAP_PTR LocHeap;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  DEVICE_BLOCK_HEADER *DeviceList;
+  AMD_CONFIG_PARAMS *StdHeader;
+  UINT32 BufferSize;
+  VOID *BufferOffset;
+  MEM_NB_BLOCK  *NBArray;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
+
+  NBArray = MemMainPtr->NBPtr;
+  RefPtr = NBArray[BSP_DIE].RefPtr;
+
+  if (RefPtr->SaveMemContextCtl) {
+    RefPtr->MemContext.NvStorage = NULL;
+    RefPtr->MemContext.NvStorageSize = 0;
+
+    // Make sure DQS training has occurred before saving memory context
+    if (!RefPtr->MemRestoreCtl) {
+      StdHeader = &MemMainPtr->MemPtr->StdHeader;
+
+      MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr);
+      if (S3NBPtr != NULL) {
+        // Get the mask bit and the register list for node that presents
+        BufferSize = 0;
+        for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+          S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Node].NBPtr, (VOID *)&DeviceDescript[Node]);
+          S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Node].NBPtr, (VOID *)&DeviceDescript[Node]);
+          BufferSize += S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Node].NBPtr, (VOID *)&DeviceDescript[Node]);
+        }
+
+        // Base on the size of the device list, apply for a buffer for it.
+        AllocHeapParams.RequestedBufferSize = (UINT32) (BufferSize + sizeof (DEVICE_BLOCK_HEADER));
+        AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+        AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+        if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+          DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr;
+          DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
+
+          // Copy device list on the stack to the heap.
+          BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + AllocHeapParams.BufferPtr;
+          for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+            for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+              // Copy PCI device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset = sizeof (PCI_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset;
+              }
+              // Copy conditional PCI device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset = sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset;
+              }
+              // Copy MSR device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset = sizeof (MSR_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset;
+              }
+              // Copy conditional MSR device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset = sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset;
+              }
+            }
+          }
+
+          // Determine size needed
+          BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader);
+          AllocHeapParams.RequestedBufferSize = BufferSize;
+          AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE;
+          AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+          if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+            // Save memory context
+            SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader);
+            RefPtr->MemContext.NvStorageSize = BufferSize;
+          }
+
+          HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
+        }
+      }
+      HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
+
+      // Locate MemContext since it might have been shifted after deallocating
+      LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE;
+      if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+        RefPtr->MemContext.NvStorage = LocHeap.BufferPtr;
+      }
+    }
+  }
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and restore memory context if possible.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  DQS timing restore succeeds.
+ *     @return          FALSE - DQS timing restore fails.
+ */
+BOOLEAN
+MemMContextRestore (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8 Node;
+  MEM_NB_BLOCK  *NBArray;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+
+  NBArray = MemMainPtr->NBPtr;
+  RefPtr = NBArray[BSP_DIE].RefPtr;
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Mem Restore\n");
+  if (RefPtr->MemRestoreCtl) {
+    if (RefPtr->MemContext.NvStorage != NULL) {
+      MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr);
+      if (S3NBPtr != NULL) {
+        // Check DIMM config and restore DQS timings if possible
+        if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) {
+          RefPtr->MemRestoreCtl = FALSE;
+        }
+      } else {
+        RefPtr->MemRestoreCtl = FALSE;
+      }
+      HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader));
+    } else {
+      IEM_SKIP_CODE (IEM_MEM_RESTORE) {
+        RefPtr->MemRestoreCtl = FALSE;
+      }
+    }
+  }
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]);
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n");
+  return RefPtr->MemRestoreCtl;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Save all memory related data for S3.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMS3Save (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  BOOLEAN SaveMemContextCtl;
+  BOOLEAN MemRestoreCtl;
+
+  RefPtr = MemMainPtr->NBPtr[BSP_DIE].RefPtr;
+
+  // If memory context has not been saved
+  if (RefPtr->MemContext.NvStorage == NULL) {
+    // Change memory context save and restore control to allow memory context to happen
+    SaveMemContextCtl = RefPtr->SaveMemContextCtl;
+    MemRestoreCtl = RefPtr->MemRestoreCtl;
+    RefPtr->SaveMemContextCtl = TRUE;
+    RefPtr->MemRestoreCtl = FALSE;
+
+    MemMContextSave (MemMainPtr);
+
+    // Restore the original control
+    RefPtr->SaveMemContextCtl = SaveMemContextCtl;
+    RefPtr->MemRestoreCtl = MemRestoreCtl;
+
+    if (RefPtr->MemContext.NvStorage == NULL) {
+      // Memory context cannot be saved succesfully
+      ASSERT (FALSE);
+      return FALSE;
+    }
+  }
+
+  // Allocate heap for memory S3 data to pass to main AMDS3Save
+  // Apply for 4 bytes more than the size of the data buffer to store the size of data buffer
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nSave memory S3 data in heap\n");
+  AllocHeapParams.RequestedBufferSize = RefPtr->MemContext.NvStorageSize + 4;
+  AllocHeapParams.BufferHandle = AMD_MEM_S3_SAVE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+
+  if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
+    LibAmdMemCopy (AllocHeapParams.BufferPtr + 4, RefPtr->MemContext.NvStorage, RefPtr->MemContext.NvStorageSize, &(MemMainPtr->MemPtr->StdHeader));
+    *(UINT32 *) AllocHeapParams.BufferPtr = RefPtr->MemContext.NvStorageSize;
+    return TRUE;
+  } else {
+    ASSERT (FALSE);
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores all devices that contains DQS timings
+ *
+ *     @param[in]     Storage        Beginning of the device list.
+ *     @param[in,out]   MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ *
+ */
+BOOLEAN
+STATIC
+MemMRestoreDqsTimings (
+  IN       VOID                *Storage,
+  IN       MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  UINT8 *OrMask;
+  DEVICE_DESCRIPTORS Device;
+  INT16 i;
+  INT16 j;
+  DEVICE_BLOCK_HEADER *DeviceList;
+  PCI_REGISTER_BLOCK_HEADER *Reg;
+  CPCI_REGISTER_BLOCK_HEADER *CReg;
+  MSR_REGISTER_BLOCK_HEADER *MsrReg;
+  CMSR_REGISTER_BLOCK_HEADER *CMsrReg;
+  PCI_ADDR PciAddress;
+  MEM_NB_BLOCK  *NBArray;
+  UINT8 State;
+  UINT8 Node;
+  UINT8 Dct;
+  UINT8 MaxNode;
+
+  NBArray = MemMainPtr->NBPtr;
+  StdHeader = &(MemMainPtr->MemPtr->StdHeader);
+  DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
+
+  if (DeviceList->NumDevices == 0) {
+    return FALSE;
+  }
+
+  MaxNode = 0;
+  State = ST_PRE_ESR;
+  for (i = 0; State != ST_DONE; i++) {
+    if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) ||
+        ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) {
+      MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader);
+      Node = Device.PciDevice->Node;
+      IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
+      PciAddress = NBArray[Node].PciAddr;
+      for (j = 0; j < Reg->NumRegisters; j++) {
+        PciAddress.Address.Function = Reg->RegisterList[j].Function;
+        PciAddress.Address.Register = Reg->RegisterList[j].Offset;
+        PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ?
+                                     0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0;
+        if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) {
+          return FALSE;   // Restore fails
+        }
+        OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize;
+      }
+
+      if (MaxNode < Node) {
+        MaxNode = Node;
+      }
+
+    } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) ||
+               ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) {
+      MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader);
+      Node = Device.CPciDevice->Node;
+      IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
+      PciAddress = NBArray[Node].PciAddr;
+      for (j = 0; j < CReg->NumRegisters; j++) {
+        if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) &&
+            ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) {
+          PciAddress.Address.Function = CReg->RegisterList[j].Function;
+          PciAddress.Address.Register = CReg->RegisterList[j].Offset;
+          PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ?
+                                       0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0;
+          if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) {
+            return FALSE;   // Restore fails
+          }
+          OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize;
+        }
+      }
+    } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) ||
+               ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) {
+      MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader);
+      for (j = 0; j < MsrReg->NumRegisters; j++) {
+        OrMask += 8;
+      }
+    } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) ||
+               ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) {
+      MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader);
+      for (j = 0; j < CMsrReg->NumRegisters; j++) {
+        if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) &&
+            ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) {
+          OrMask += 8;
+        }
+      }
+    }
+
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_PCI:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CPCI:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_MSR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CMSR:
+      Device.CMsrDevice++;
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+
+    if (i == (DeviceList->NumDevices - 1)) {
+      // Go to next state
+      State++;
+      i = -1;
+      Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+
+      // Check to see if processor or DIMM population has changed
+      if ((MaxNode + 1) != MemMainPtr->DieCount) {
+        IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: Population changed\n");
+        return FALSE;
+      }
+
+      // Perform MemClk frequency change
+      for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+        if (NBArray[Node].MCTPtr->NodeMemSize != 0) {
+          NBArray[Node].BeforeDqsTraining (&NBArray[Node]);
+          if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) {
+            for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) {
+              NBArray[Node].SwitchDCT (&NBArray[Node], Dct);
+              NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed;
+            }
+            IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader));
+            NBArray[Node].ChangeFrequency (&NBArray[Node]);
+          }
+        }
+      }
+    }
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function filters out other settings and only restores DQS timings.
+ *
+ *     @param[in,out]   NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   SpecialCases - Pointer to special cases array handlers
+ *     @param[in]   PciAddr - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   Value - Value to be programmed
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemMSetCSRNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       PCI_SPECIAL_CASE *SpecialCases,
+  IN       PCI_ADDR PciAddr,
+  IN       UINT32 Value
+  )
+{
+  UINT32 Offset;
+  UINT8  Dct;
+  UINT32 Temp;
+  BOOLEAN RetVal;
+  UINT32 BOffset;
+
+  RetVal = TRUE;
+  if (PciAddr.Address.Segment != 0) {
+    if (PciAddr.Address.Segment == 0xF) {
+      PciAddr.Address.Segment = 0;
+      Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1);
+      Offset = PciAddr.Address.Register & 0x3FF;
+      BOffset = PciAddr.Address.Register & 0xFF;
+      if ((PciAddr.Address.Register & 0x800) == 0) {
+        if (((BOffset >= 1) && (BOffset <= 3)) ||
+            ((BOffset >= 5) && (BOffset <= 7)) ||
+            ((Offset >= 0x10) && (Offset <= 0x2B)) ||
+            ((Offset >= 0x30) && (Offset <= 0x4A))) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value);
+          //MemNS3SetCSR
+          SpecialCases[0].Restore (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+        }
+      }
+    }
+  } else {
+    Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1);
+    Offset = PciAddr.Address.Register & 0xFF;
+
+    if (PciAddr.Address.Function == 2) {
+      if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) {
+        // If TestFail bit is set, set CsTestFail
+        NBPtr->SwitchDCT (NBPtr, Dct);
+        NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2);
+        IDS_HDT_CONSOLE (MEM_FLOW, "\tBad CS:%d\n", ((Offset - 0x40) >> 2));
+      } else if (Offset == 0x80) {
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        if (Temp != Value) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+      } else if (Offset == 0x90) {
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        if ((Temp & 0x0001F000) != (Value & 0x0001F000)) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+      } else if (Offset == 0x94) {
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        if ((Temp & 0x00061000) != (Value & 0x00061000)) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+        if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n");
+          RetVal = FALSE;
+        }
+        // Restore ZqcsInterval
+        Temp &= 0xFFFFF3FF;
+        Temp |= (Value & 0x00000C00);
+        LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+      } else if (Offset == 0x78) {
+        // Program MaxRdLat
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        Temp &= 0x0009BF0F;
+        Temp |= (Value & 0xFFC00000);
+        LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+      } else if (PciAddr.Address.Register == 0x110) {
+        if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+      }
+    }
+  }
+
+  if (RetVal == FALSE) {
+    NBPtr->SwitchDCT (NBPtr, 0);
+    NBPtr->DCTPtr->Timings.CsTrainFail = 0;
+    NBPtr->SwitchDCT (NBPtr, 1);
+    NBPtr->DCTPtr->Timings.CsTrainFail = 0;
+  }
+
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Create S3 NB Block.
+ *
+ *     @param[in,out]   MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *     @param[out]      S3NBPtr   - Pointer to the S3 NB Block pointer
+ *
+ */
+VOID
+STATIC
+MemMCreateS3NbBlock (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr,
+     OUT   S3_MEM_NB_BLOCK **S3NBPtr
+  )
+{
+  UINT8 Node;
+  UINT8 i;
+  MEM_NB_BLOCK  *NBArray;
+  MEM_NB_BLOCK  *DummyNBs;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  NBArray = MemMainPtr->NBPtr;
+
+  *S3NBPtr = NULL;
+
+  // Allocate heap for S3 NB Blocks
+  AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK)));
+  AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
+    *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr;
+    DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK));
+
+    // Initialize S3 NB Blocks
+    for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+      (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node];
+
+      for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) {
+        if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) {
+          break;
+        }
+      };
+      if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
+        *S3NBPtr = NULL;
+        break;
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c
new file mode 100644
index 0000000000..5e39949ead
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c
@@ -0,0 +1,173 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmNodeInterleave.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMInterleaveNodes (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and enable node interleaving on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMInterleaveNodes (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  BOOLEAN RetVal;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  NodeCnt = 0;
+  RetVal = TRUE;
+
+  if (NBPtr->RefPtr->EnableNodeIntlv) {
+    if (!MemFeatMain.MemClr (MemMainPtr)) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+      return FALSE;
+    }
+
+    MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE;
+    MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0;
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) {
+        break;
+      }
+      if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
+        NodeCnt ++;
+      }
+    }
+
+    if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) {
+      MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt;
+      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+        if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
+          NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]);
+        }
+      }
+      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+        NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
+        RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+      }
+    } else {
+      //
+      // If all nodes cannot be interleaved
+      //
+      PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    }
+  }
+
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c
new file mode 100644
index 0000000000..9c5a26e7e6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c
@@ -0,0 +1,192 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmOnlineSpare.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMOnlineSpare (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and enable online spare on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMOnlineSpare (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  BOOLEAN IsEnabled;
+  UINT8   FirstEnabledNode;
+  UINT32  BottomIO;
+  BOOLEAN RetVal;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader));
+  FirstEnabledNode = 0;
+  IsEnabled = FALSE;
+  RetVal = TRUE;
+  NBPtr = MemMainPtr->NBPtr;
+  RefPtr = NBPtr[BSP_DIE].RefPtr;
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) {
+      if (!IsEnabled) {
+        // Record the first node that has spared dimm enabled
+        FirstEnabledNode = Node;
+        IsEnabled = TRUE;
+      }
+    }
+  }
+
+  if (IsEnabled) {
+    NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
+    BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
+    // If the first node that has spared dimms does not have a system base smaller
+    // than bottomIO, then we don't need to reset the GStatus, as we don't need to
+    // remap memory hole.
+    if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
+      RefPtr->GStatus[GsbHWHole] = FALSE;
+      RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
+      RefPtr->GStatus[GsbSoftHole] = FALSE;
+      RefPtr->HoleBase = 0;
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      if (Node >= FirstEnabledNode) {
+        // Remap memory on nodes with node number larger than the first node that has spared dimms.
+        NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
+        NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
+      } else {
+        // No change is needed in the memory map of this node.
+        // Need to adjust the current system base for other nodes processed later.
+        NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
+        // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
+        // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
+        // and DramMemHoistValid.
+        // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
+        // DramHoleValid.
+        if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
+          NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        }
+      }
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
+      RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+    }
+    NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
+  }
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c
new file mode 100644
index 0000000000..7b2916dcfc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c
@@ -0,0 +1,315 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmNodeInterleave.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "GeneralServices.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mu.h"
+#include "mfParallelTraining.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemMParallelTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMParallelTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK *NBPtr;
+  DIE_INFO TrainInfo[MAX_NODES_SUPPORTED];
+  AP_DATA_TRANSFER ReturnData;
+  AGESA_STATUS Status;
+  UINT8 ApSts;
+  UINT8 Die;
+  UINT8 Socket;
+  UINT32 Module;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 Time;
+  UINT32 TimeOut;
+  UINT32 TargetApicId;
+  BOOLEAN StillTraining;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 *BufferPtr;
+  BOOLEAN TimeoutEn;
+
+  NBPtr = mmPtr->NBPtr;
+  MemPtr = mmPtr->MemPtr;
+  StdHeader = &(mmPtr->MemPtr->StdHeader);
+  Time = 0;
+  TimeOut = PARALLEL_TRAINING_TIMEOUT;
+  TimeoutEn = TRUE;
+  IDS_TIMEOUT_CTL (&TimeoutEn);
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n");
+  AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader);
+  //
+  // Initialize Training Info Array
+  //
+  for (Die = 0; Die < mmPtr->DieCount; Die ++) {
+    Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId;
+    Module = NBPtr[Die].MCTPtr->DieId;
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket);
+    TrainInfo[Die].Training = FALSE;
+  }
+  //
+  // Start Training on Each remote die.
+  //
+  for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
+    if (Die != BSP_DIE) {
+      NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die]));
+      if (NBPtr[Die].MCTPtr->NodeMemSize != 0) {
+        if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) {
+          // Fail to launch code on AP
+          PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr);
+          if (!MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader)) {
+            ASSERT (FALSE);
+          }
+        } else {
+          TrainInfo[Die].Training = TRUE;
+        }
+      }
+    }
+  }
+  //
+  // Call training on BSP
+  //
+  IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node);
+  NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE]));
+  NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE]));
+  NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE]));
+
+  //
+  // Get Results from remote processors training
+  //
+  do {
+    StillTraining = FALSE;
+    for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
+      //
+      // For each Die that is training, read the status
+      //
+      if (TrainInfo[Die].Training == TRUE) {
+        GetLocalApicIdForCore (TrainInfo[Die].Socket, TrainInfo[Die].Core, &TargetApicId, StdHeader);
+        ApSts = ApUtilReadRemoteControlByte (TargetApicId, StdHeader);
+        if ((ApSts & 0x80) == 0) {
+          //
+          // Allocate buffer for received data
+          //
+          AllocHeapParams.RequestedBufferSize = (
+            sizeof (DIE_STRUCT) +
+            NBPtr[Die].DctCount * (
+              sizeof (DCT_STRUCT) + (
+                NBPtr[Die].ChannelCount * (
+                  sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
+                   (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount *
+                    NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount *
+                    NUMBER_OF_DELAY_TABLES) +
+                    (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
+                    (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
+                  )
+                )
+              )
+            )
+          ) + 3;
+          AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0);
+          AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+          if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+            //
+            // Receive Training Results
+            //
+
+            ReturnData.DataPtr = AllocHeapParams.BufferPtr;
+            ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4;
+            ReturnData.DataTransferFlags = 0;
+            Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader);
+            if (Status != AGESA_SUCCESS) {
+              SetMemError (Status, NBPtr[Die].MCTPtr);
+            }
+
+            BufferPtr = AllocHeapParams.BufferPtr;
+            LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader);
+            BufferPtr += sizeof (DIE_STRUCT);
+            LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData,
+                            BufferPtr,
+                            NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)),
+                            StdHeader);
+            BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT));
+            LibAmdMemCopy ( NBPtr[Die].PSBlock,
+                            BufferPtr,
+                            NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK),
+                            StdHeader);
+            BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK);
+            LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys,
+                            BufferPtr,
+                            (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) *
+                            ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount *
+                              NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount *
+                              NUMBER_OF_DELAY_TABLES) +
+                              (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
+                              (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
+                            ),
+                            StdHeader);
+
+            HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
+
+            NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die]));
+            TrainInfo[Die].Training = FALSE;
+          } else {
+            PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader);
+            SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr);
+            ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer
+          }
+        } else if (ApSts == CORE_IDLE) {
+          // AP does not have buffer to transmit to BSP
+          // AP fails to locate a buffer for data transfer
+          TrainInfo[Die].Training = FALSE;
+        } else {
+          // Signal to loop through again
+          StillTraining = TRUE;
+        }
+      }
+    }
+    // Wait for 1 us
+    MemUWait10ns (100, NBPtr->MemPtr);
+    Time ++;
+  } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished
+                                                // if cannot finish in 1 s, do fatal exit
+
+  if (StillTraining && TimeoutEn) {
+    // Parallel training time out, do fatal exit, as there is at least one AP hangs.
+    PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
+    ASSERT(FALSE); // Timeout occurred while still training
+  }
+
+  for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
+    if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
+      return FALSE;
+    }
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
new file mode 100644
index 0000000000..8facb1af1c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
@@ -0,0 +1,159 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmStandardTraining.c
+ *
+ * Main Memory Feature implementation file for Standard Training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemMStandardTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+extern BUILD_OPT_CFG UserOptions;
+extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * MemMStandardTraining
+ *
+ * This function implements standard memory training whereby training functions
+ * for all nodes are run by the BSP.
+ *
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMStandardTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  UINT8 Die;
+  //
+  // If training is disabled, return success.
+  //
+  if (!UserOptions.CfgDqsTrainingControl) {
+    return TRUE;
+  }
+  //
+  // Run Northbridge-specific Standard Training feature for each die.
+  //
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n");
+  for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die);
+    AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
+    mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);
+    mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = TRUE;
+    mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);
+    mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL);
+    mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);
+    if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
+      break;
+    }
+  }
+  return (BOOLEAN) (Die == mmPtr->DieCount);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
new file mode 100644
index 0000000000..02292c50f0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
@@ -0,0 +1,272 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmUmaAlloc.c
+ *
+ * Main Memory Feature implementation file for UMA allocation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "mport.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMUmaAlloc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *    UMA allocation mechanism.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemMUmaAlloc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT32 TOM;
+  UINT32 TOM2;
+  UINT32 UmaSize;
+  UINT32 TopOfChIntlv;
+  UINT32 DctSelHi;
+  UINT32 UmaAlignment;
+  UINT32 UmaAbove4GBase;
+  UINT32 UmaBelow4GBase;
+  BOOLEAN DctSelIntLvEn;
+  BOOLEAN UmaAbove4GEn;
+  S_UINT64 SMsr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UMA_INFO *UmaInfoPtr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  MemPtr = MemMainPtr->MemPtr;
+  NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]);
+  RefPtr = NBPtr->RefPtr;
+
+  TOM2 = 0;
+  SMsr.lo = SMsr.hi = 0;
+  UmaAbove4GBase = 0;
+  RefPtr->UmaBase = 0;
+  UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment;
+  UmaAbove4GEn = UserOptions.CfgUmaAbove4G;
+  DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) != 0) ? TRUE : FALSE;
+  TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16);
+  DctSelHi = NBPtr->GetBitField (NBPtr, BFDctSelHi);
+
+  // Allocate heap for UMA_INFO
+  AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO);
+  AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    ASSERT(FALSE); // Could not allocate heap for Uma information.
+    return FALSE;
+  }
+  UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr;
+  // Default all the fields of UMA_INFO
+  UmaInfoPtr->UmaMode = (UINT8) UMA_NONE;
+  UmaInfoPtr->UmaSize = 0;
+  UmaInfoPtr->UmaBase = 0;
+  UmaInfoPtr->UmaAttributes = 0;
+  UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed;
+
+  switch (RefPtr->UmaMode) {
+  case UMA_NONE:
+    UmaSize = 0;
+    break;
+  case UMA_SPECIFIED:
+    UmaSize = RefPtr->UmaSize;
+    break;
+  case UMA_AUTO:
+    UmaSize = NBPtr->GetUmaSize (NBPtr);
+    break;
+  default:
+    UmaSize = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  if (UmaSize != 0) {
+    //TOM scaled from [47:0] to [47:16]
+    LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16));
+
+    UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment;
+    // Initialize Ref->UmaBase to UmaBelow4GBase
+    RefPtr->UmaBase = UmaBelow4GBase;
+
+    // Uma Above 4G support
+    if (UmaAbove4GEn) {
+      //TOM2 scaled from [47:0] to [47:16]
+      LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+      TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16));
+      if (TOM2 != 0) {
+        UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment;
+        //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB
+        if (UmaAbove4GBase < _4GB_RJ16) {
+          UmaAbove4GBase = 0;
+        }
+        if (UmaAbove4GBase != 0) {
+          RefPtr->UmaBase = UmaAbove4GBase;
+          // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved.
+          // 2. TopOfChIntlv >= TOM tells us :
+          //   -All or portion of Uma region that above 4G is NOT interleaved.
+          //   -Whole Uma region that below 4G is interleaved.
+          if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) {
+            RefPtr->UmaBase = UmaBelow4GBase;
+          }
+        }
+      }
+    }
+
+    UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode);
+    UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16);
+
+    if (RefPtr->UmaBase >= _4GB_RJ16) {
+      // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it.
+      RefPtr->UmaSize = TOM2 - UmaAbove4GBase;
+      // Uma Typing
+      MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2);
+      if (DctSelIntLvEn && (TopOfChIntlv == 0)) {
+        UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
+      } else {
+        // Entire UMA region is in the high DCT
+        UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1;
+      }
+    } else {
+      // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it.
+      RefPtr->UmaSize = TOM - UmaBelow4GBase;
+      // Uma Typing
+      NBPtr->UMAMemTyping (NBPtr);
+      if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) {
+        UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
+      } else {
+        if (UmaBelow4GBase >= TopOfChIntlv) {
+          // Entire UMA region is in the high DCT
+          UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1;
+        } else if (TopOfChIntlv >= TOM) {
+          // Entire UMA region is in the low DCT
+          UmaInfoPtr->UmaAttributes = (DctSelHi == 1) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1;
+        } else {
+          // UMA region is in both DCT0 and DCT1
+          UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
+        }
+      }
+    }
+    UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16;
+    IDS_HDT_CONSOLE (MEM_FLOW, "UMA is allocated:\n\tBase: %x0000\n\tSize: %x0000\n", RefPtr->UmaBase, RefPtr->UmaSize);
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c
new file mode 100644
index 0000000000..bd60a0a31a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c
@@ -0,0 +1,421 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmflow.c
+ *
+ * Main Memory Flow Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE
+/* features */
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+extern MEM_FLOW_CFG* memFlowControlInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemSPDDataProcess (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the main memory configuration function for DR DDR3
+ *
+ *      Requirements:
+ *
+ *      Run-Time Requirements:
+ *      1. Complete Hypertransport Bus Configuration
+ *      2. AmdMemInitDataStructDef must be run to set default values
+ *      3. MSR bit to allow access to high PCI regs set on all nodes
+ *      4. BSP in Big Real Mode
+ *      5. Stack available
+ *      6. MCG_CTL=-1, MC4_EN=0 for all CPUs
+ *      7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
+ *      8. All var MTRRs reset to zero
+ *      9. State of NB_CFG.DisDatMsk set properly on all CPUs
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  MEM_SHARED_DATA  mmSharedData;
+  MEM_MAIN_DATA_BLOCK mmData;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AGESA_STATUS Retval;
+  UINT8 i;
+  UINT8 Die;
+  UINT8 DieCount;
+  UINT8 Tab;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  ASSERT (MemPtr != NULL);
+
+  AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n");
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tLimitBelow1TB : %d\n", MemPtr->ParameterListPtr->LimitMemoryToBelow1Tb);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n", MemPtr->ParameterListPtr->SaveMemContextCtl);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tExternalVrefCtl : %d\n", MemPtr->ParameterListPtr->ExternalVrefCtl );
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tForceTrainMode : %d\n\n", MemPtr->ParameterListPtr->ForceTrainMode );
+
+  //----------------------------------------------------------------------------
+  // Get TSC rate, which will be used later in Wait10ns routine
+  //----------------------------------------------------------------------------
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
+  FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader);
+
+  //----------------------------------------------------------------------------
+  // Read In SPD Data
+  //----------------------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader);
+  MemSPDDataProcess (MemPtr);
+
+  //----------------------------------------------------------------
+  // Initialize Main Data Block
+  //----------------------------------------------------------------
+  mmData.MemPtr = MemPtr;
+  mmData.mmSharedPtr = &mmSharedData;
+  LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader);
+  mmSharedData.DimmExcludeFlag = NORMAL;
+  mmSharedData.NodeIntlv.IsValid = FALSE;
+  //----------------------------------------------------------------
+  // Discover populated CPUs
+  //
+  //----------------------------------------------------------------
+  Retval = MemSocketScan (&mmData);
+  if (Retval == AGESA_FATAL) {
+    return Retval;
+  }
+  DieCount = mmData.DieCount;
+  //----------------------------------------------------------------
+  //
+  // Allocate Memory for NB and Tech Blocks
+  //
+  //  NBPtr[Die]----+
+  //                |
+  //                V
+  //  +---+---+---+---+---+---+---+---+
+  //  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |   NB Blocks
+  //  +---+---+---+---+---+---+---+---+
+  //    |   |   |   |   |   |   |   |
+  //    |   |   |   |   |   |   |   |
+  //    v   v   v   v   v   v   v   v
+  //  +---+---+---+---+---+---+---+---+
+  //  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |   Tech Blocks
+  //  +---+---+---+---+---+---+---+---+
+  //
+  //
+  //----------------------------------------------------------------
+  AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK)));
+  AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    ASSERT(FALSE); // NB and Tech Block Heap allocate error
+    return AGESA_FATAL;
+  }
+  NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+  TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]);
+  mmData.NBPtr = NBPtr;
+  mmData.TechPtr = TechPtr;
+
+  //----------------------------------------------------------------
+  // Create NB Blocks
+  //
+  //----------------------------------------------------------------
+  for (Die = 0 ; Die < DieCount ; Die++ ) {
+    i = 0;
+    while (memNBInstalled[i].MemConstructNBBlock != 0) {
+      if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) {
+        break;
+      }
+      i++;
+    }
+    // Couldn't find a NB which supported this family
+    if (memNBInstalled[i].MemConstructNBBlock == 0) {
+      return AGESA_FATAL;
+    }
+  }
+  //----------------------------------------------------------------
+  // Create Technology Blocks
+  //
+  //----------------------------------------------------------------
+  for (Die = 0 ; Die < DieCount ; Die++ ) {
+    i = 0;
+    while (memTechInstalled[i] != NULL) {
+      if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) {
+        NBPtr[Die].TechPtr = &TechPtr[Die];
+        break;
+      }
+      i++;
+    }
+    // Couldn't find a Tech block which supported this family
+    if (memTechInstalled[i] == NULL) {
+      return AGESA_FATAL;
+    }
+  }
+  //----------------------------------------------------------------
+  //
+  //                 MEMORY INITIALIZATION TASKS
+  //
+  //----------------------------------------------------------------
+  i = 0;
+  while (memFlowControlInstalled[i] != NULL) {
+    Retval = memFlowControlInstalled[i] (&mmData);
+    if (MemPtr->IsFlowControlSupported == TRUE) {
+      break;
+    }
+    i++;
+  }
+
+  //----------------------------------------------------------------
+  // Deallocate NB register tables
+  //----------------------------------------------------------------
+  for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) {
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), &MemPtr->StdHeader);
+  }
+
+  //----------------------------------------------------------------
+  // Check for errors and return
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader);
+  for (Die = 0; Die < DieCount; Die++) {
+    if (NBPtr[Die].MCTPtr->ErrCode > Retval) {
+      Retval = NBPtr[Die].MCTPtr->ErrCode;
+    }
+  }
+  return Retval;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
+ *
+ *    The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms.  At this
+ *  point, the Memory controller type is not known, and the platform BIOS does not know the anything
+ *  about which DIMM is on which DCT.  So the DCT relationship is abstracted from the arrangement
+ *  of SPD information here.  We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(),
+ *  and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs
+ *  are connected to.  The functions rely on either the maximum values in the
+ *  PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H.
+ *
+ *  This mapping is translated in the Northbridge object Constructor and the Technology block constructor.
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+
+VOID
+STATIC
+MemSPDDataProcess (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  UINT8 Dimm;
+  UINT8 DimmIndex;
+  UINT32 AgesaStatus;
+  UINT8 MaxSockets;
+  UINT8 MaxChannelsPerSocket;
+  UINT8 MaxDimmsPerChannel;
+  SPD_DEF_STRUCT *DimmSPDPtr;
+  PSO_TABLE *PsoTable;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AGESA_READ_SPD_PARAMS SpdParam;
+
+  ASSERT (MemPtr != NULL);
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration;
+  //
+  // Allocate heap for the table
+  //
+  AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT));
+  AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+    MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    //
+    // Initialize SpdParam Structure
+    //
+    LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader);
+    //
+    // Populate SPDDataBuffer
+    //
+    SpdParam.MemData = MemPtr;
+    DimmIndex = 0;
+    for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) {
+      MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader);
+      SpdParam.SocketId = Socket;
+      for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+        SpdParam.MemChannelId = Channel;
+        MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel);
+        for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) {
+          SpdParam.DimmId = Dimm;
+          DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]);
+          SpdParam.Buffer = DimmSPDPtr->Data;
+          AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader);
+          AgesaStatus = AgesaReadSpd (0, &SpdParam);
+          AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader);
+          if (AgesaStatus == AGESA_SUCCESS) {
+            DimmSPDPtr->DimmPresent = TRUE;
+            IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer);
+          } else {
+            DimmSPDPtr->DimmPresent = FALSE;
+          }
+        }
+      }
+    }
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader);
+    //
+    // Assert here if unable to allocate heap for SPDs
+    //
+    IDS_ERROR_TRAP;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmlvddr3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmlvddr3.h
new file mode 100644
index 0000000000..d9d995c310
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmlvddr3.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmLvDdr3.h
+ *
+ * Main low voltage DDR3 support common header
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MMLVDDR3_H_
+#define _MMLVDDR3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemMLvDdr3PerformanceEnhPre (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+MemMLvDdr3PerformanceEnhFinalize (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+#endif  /* _MMLVDDR3_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
new file mode 100644
index 0000000000..bec90ce0e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
@@ -0,0 +1,523 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+;  $Workfile:: mu.asm   $ $Revision:: 634#$  $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+; Description: Main memory controller system configuration for AGESA
+;
+;
+;*****************************************************************************
+;
+; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*****************************************************************************
+;============================================================================
+
+
+    .XLIST
+    .LIST
+
+    .686p
+    .MODEL FLAT
+    .CODE
+    ASSUME FS: NOTHING
+
+; Define the calling convention used for the C library modules
+;@attention - This should be in a central include file
+CALLCONV    EQU     NEAR C
+
+
+;===============================================================================
+;memUOutPort:
+;
+; Do a 32 Bit IO Out operation using edx.
+; NOTE: This function will be obsolete in the future.
+;
+;             In: Port  - port number
+;                 Value - value to be written
+;
+;            Out:
+;
+; All registers preserved.
+;===============================================================================
+MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
+    pushad
+    mov edx,Port
+    mov eax,Value
+    out dx,al
+    popad
+    ret
+MemUOutPort ENDP
+
+
+;----------------------------------------------------------------------------
+; _SFENCE();
+;
+_SFENCE macro
+    db  0Fh,0AEh,0F8h
+    endm
+
+;----------------------------------------------------------------------------
+; _MFENCE();
+;
+_MFENCE macro
+    db  0Fh,0AEh,0F0h
+    endm
+
+;----------------------------------------------------------------------------
+; _EXECFENCE();
+;
+_EXECFENCE macro
+    out 0EDh,al             ;prevent speculative execution of following instructions
+    endm
+
+;===============================================================================
+;MemUWriteCachelines:
+;   Write a test pattern to DRAM
+;
+;             In: Pattern   - pointer to the write pattern
+;                 Address   - Physical address to be read
+;                 ClCount   - number of cachelines to be read
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
+        pushad
+        push ds
+
+        mov eax,Address
+        push ss
+        pop ds
+        xor edx,edx
+        mov edx, DWORD PTR Pattern
+        mov esi,edx
+        mov edx,16
+        _EXECFENCE
+        xor ecx, ecx
+        mov cx,ClCount
+        shl ecx,2
+        @@:
+        db 66h, 0Fh,6Fh,06           ;MOVDQA xmm0,[esi]
+        db 64h, 66h, 0Fh,0E7h,00      ;MOVNTDQ fs:[eax],xmm0  (xmm0 is 128 bits)
+        add eax,edx
+        add esi,edx
+        loop @B
+
+        pop ds
+        popad
+        ret
+MemUWriteCachelines ENDP
+
+;===============================================================================
+;MemUReadCachelines:
+;
+; Read a pattern of 72 bit times (per DQ), to test dram functionality.  The
+;pattern is a stress pattern which exercises both ISI and crosstalk.  The number
+;of cache lines to fill is dependent on DCT width mode and burstlength.
+;
+;             In: Buffer    - pointer to a buffer where read data will be stored
+;                 Address   - Physical address to be read
+;                 ClCount   - number of cachelines to be read
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
+LOCAL Count:BYTE
+        pushad
+        ; First, issue continuous dummy reads to fill up the cache
+        mov eax,Address
+        .if (ClCount > 18)
+            mov cx,ClCount
+            shr cx,4
+            mov Count,cl
+            .while (Count != 0)
+                push eax
+                mov edi,eax
+                add edi,128                     ;bias value (to account for signed displacement)
+                                                ;clflush opcode=0F AE /7
+                mov esi,edi
+                mov ebx,esi
+                mov ecx,esi
+                mov edx,esi
+                add edi,4*64                    ;TestAddr+4 cache lines
+                add ebx,8*64                    ;TestAddr+8 cache lines
+                add ecx,12*64                   ;TestAddr+12 cache lines
+                add edx,16*64                   ;TestAddr+16 cache lines
+                sub edx,128
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+                mov eax,fs:[edi]                ;TestAddr+6 cache lines
+                _MFENCE
+                mov eax,fs:[edi+64]             ;TestAddr+7 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-128]            ;TestAddr+8 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-64]             ;TestAddr+9 cache lines
+                _MFENCE
+                mov eax,fs:[ebx]                ;TestAddr+10 cache lines
+                _MFENCE
+                mov eax,fs:[ebx+64]             ;TestAddr+11 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-128]            ;TestAddr+12 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-64]             ;TestAddr+13 cache lines
+                _MFENCE
+                mov eax,fs:[ecx]                ;TestAddr+14 cache lines
+                _MFENCE
+                mov eax,fs:[ecx+64]             ;TestAddr+15 cache lines
+                _MFENCE
+                pop eax
+                add eax,(16*64)                 ;Next 16CL
+                dec Count
+            .endw
+        .else
+            mov edi,eax
+            add edi,128                     ;bias value (to account for signed displacement)
+                                            ;clflush opcode=0F AE /7
+            mov esi,edi
+            mov ebx,esi
+            mov ecx,esi
+            mov edx,esi
+            add edi,4*64                    ;TestAddr+4 cache lines
+            add ebx,8*64                    ;TestAddr+8 cache lines
+            add ecx,12*64                   ;TestAddr+12 cache lines
+            add edx,16*64                   ;TestAddr+16 cache lines
+            sub edx,128
+            .if(ClCount == 1)
+                _MFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+            .elseif(ClCount == 3)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+            .elseif(ClCount == 6)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+            .elseif(ClCount == 9)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+                mov eax,fs:[edi]                ;TestAddr+6 cache lines
+                _MFENCE
+                mov eax,fs:[edi+64]             ;TestAddr+7 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-128]            ;TestAddr+8 cache lines
+                _MFENCE
+            .elseif(ClCount == 18)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+                mov eax,fs:[edi]                ;TestAddr+6 cache lines
+                _MFENCE
+                mov eax,fs:[edi+64]             ;TestAddr+7 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-128]            ;TestAddr+8 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-64]             ;TestAddr+9 cache lines
+                _MFENCE
+                mov eax,fs:[ebx]                ;TestAddr+10 cache lines
+                _MFENCE
+                mov eax,fs:[ebx+64]             ;TestAddr+11 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-128]            ;TestAddr+12 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-64]             ;TestAddr+13 cache lines
+                _MFENCE
+                mov eax,fs:[ecx]                ;TestAddr+14 cache lines
+                _MFENCE
+                mov eax,fs:[ecx+64]             ;TestAddr+15 cache lines
+                _MFENCE
+                mov eax,fs:[edx]                ;TestAddr+16 cache lines
+                _MFENCE
+                mov eax,fs:[edx+64]             ;TestAddr+17 cache lines
+                _MFENCE
+            .endif
+        .endif
+        _MFENCE
+
+        ; Then, copy data to buffer
+        mov esi,Address
+        xor edx,edx
+        mov edx,DWORD PTR Buffer
+        mov edi,edx
+        xor ecx, ecx
+        mov cx,ClCount
+        shl ecx,6
+        @@:
+        mov al,fs:[esi]
+        mov ss:[edi],al
+        inc esi
+        inc edi
+        loop @B
+
+        popad
+        ret
+MemUReadCachelines ENDP
+
+;===============================================================================
+;MemUDummyCLRead:
+;
+;   Perform a single cache line read from a given physical address.
+;
+;             In: Address   - Physical address to be read
+;                 ClCount   - number of cachelines to be read
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
+    _SFENCE
+    pushad
+    mov eax,Address
+    mov dl,fs:[eax]
+    popad
+    ret
+MemUDummyCLRead ENDP
+
+;===============================================================================
+;MemUFlushPattern:
+;
+; Flush a pattern of 72 bit times (per DQ) from cache.  This procedure is used
+;to ensure cache miss on the next read training.
+;
+;             In: Address   - Physical address to be flushed
+;                 ClCount   - number of cachelines to be flushed
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
+        pushad
+        mov edi,Address
+        movzx ecx,ClCount
+        @@:
+        _MFENCE                     ; Force strong ordering of clflush
+        db  64h,0Fh,0AEh,3Fh        ; MemUClFlush fs:[edi]
+        _MFENCE
+        add edi,64
+        loop @B
+        popad
+        ret
+MemUFlushPattern ENDP
+
+
+;===============================================================================
+;MemUGetWrLvNblErr:
+;   Read ClCount number of cachelines then return the bitmap that indicates
+;   the write leveling result of each byte lane.
+;
+;   IN:     ErrBitmap - pointer to a DWORD that will be assigned with WL result
+;           Address   - Physical address to be sampled
+;           ClCount   - number of cachelines to be read
+;
+;   OUT:    ErrBitmap - WL result
+;
+;All registers preserved
+;===============================================================================
+MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
+LOCAL ZeroCount[32]:WORD
+
+        pushad
+        mov esi,Address
+        _EXECFENCE
+    ;Cache fill
+        movzx ecx,ClCount
+        @@:
+        mov eax,fs:[esi]
+        add esi,64
+        loop @B
+        _MFENCE
+
+    ; Then, count the number of 0's
+        ;push es
+        ;push ss
+        ;pop es
+        lea edi,ZeroCount
+        mov cx,SIZEOF ZeroCount
+        mov al,0
+        rep stosb
+        ;pop es
+
+        mov esi,Address
+        lea edi,ZeroCount
+        mov cx,ClCount
+        shl cx,6
+        .while(cx > 0)
+            mov al,fs:[esi]
+            test al,00Fh        ;check lower nibble
+            .if(ZERO?)
+                inc WORD PTR [edi]
+            .endif
+            add edi,2
+            test al,0F0h        ;check upper nibble
+            .if(ZERO?)
+                inc WORD PTR [edi]
+            .endif
+            add edi,2
+            inc esi
+            dec cx
+            test cx,07h
+            .if(ZERO?)
+                sub edi,(16*2)
+                sub cx,8
+                add esi,8
+            .endif
+        .endw
+
+    ; Then, average and compress data to error bits
+        lea esi,ZeroCount
+        mov dx,ClCount
+        shl dx,1
+        xor eax,eax
+        xor ecx,ecx
+        mov cl,0
+        .while(cl<16)
+            .if(WORD PTR [esi] < dx)
+                bts eax,ecx
+            .endif
+            add esi,2
+            inc cl
+        .endw
+        xor edx,edx
+        mov dx,WORD PTR ErrBitmap
+        mov [edx], ax
+
+        popad
+        ret
+MemUGetWrLvNblErr ENDP
+
+;===============================================================================
+;AlignPointerTo16Byte:
+;   Modifies BufferPtr to be 16 byte aligned
+;
+;             In: BufferPtrPtr - Pointer to buffer pointer
+;            Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
+;
+;All registers preserved.
+;===============================================================================
+AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
+        push edx
+        push eax
+        mov edx, BufferPtrPtr
+        mov eax, [edx]
+        add eax, 16
+        and ax, 0FFF0h
+        mov [edx], eax
+        pop eax
+        pop edx
+        ret
+AlignPointerTo16Byte ENDP
+
+;===============================================================================
+;MemUMFenceInstr:
+;   Serialize instruction
+;
+;             In:
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUMFenceInstr PROC CALLCONV PUBLIC
+        _MFENCE
+        ret
+MemUMFenceInstr ENDP
+
+    END
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.c
new file mode 100644
index 0000000000..a4e5716fad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.c
@@ -0,0 +1,250 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 35978 $   @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Filecode.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+MemUWriteCachelines (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemUReadCachelines (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemUDummyCLRead (
+  IN       UINT32 Address
+  );
+
+VOID
+MemUMFenceInstr (
+  VOID
+  );
+
+VOID
+MemUFlushPattern (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+AlignPointerTo16Byte (
+  IN OUT   UINT8 **BufferPtrPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+//----------------------------------------------------------------------------
+
+VOID
+MemUWriteCachelines (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  UINTN Index;
+  CHAR8 *Position;
+  __m128i *Src = (void *) Pattern;
+  __m128i *Dest = (void *) (size_t)Address;
+
+  Position = (void *) Pattern;
+
+  // ssd - important: without this, the src data may get evicted from cache
+  _mm_mfence ();
+
+  for (Index = 0; Index < ClCount * 4; Index++){
+    _mm_stream_si128_fs (Dest, Src);
+    Src++;
+    Dest++;
+  }
+
+  // ssd - might not be required, but no measurable boot time impact
+  _mm_mfence ();
+}
+
+//----------------------------------------------------------------------------
+// MemUReadCachelines:
+//
+// Read a pattern of 72 bit times (per DQ), to test dram functionality.  The
+// pattern is a stress pattern which exercises both ISI and crosstalk.  The number
+// of cache lines to fill is dependent on DCT width mode and burstlength.
+//
+//             In: Buffer    - pointer to a buffer where read data will be stored
+//                 Address   - Physical address to be read
+//                 ClCount   - number of cachelines to be read
+
+VOID
+MemUReadCachelines (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  UINTN Index;
+  UINT32 *Dest;
+
+  for (Index = 0; Index < ClCount * 16; Index++) {
+    Dest = (void *) &Buffer [Index * 4];
+    *Dest = __readfsdword (Address + Index * 4);
+    _mm_mfence ();
+  }
+}
+
+//----------------------------------------------------------------------------
+// MemUDummyCLRead:
+//
+//    Perform a single cache line read from a given physical address.
+//
+//              In: Address   - Physical address to be read
+//                  ClCount   - number of cachelines to be read
+
+//FUNC_ATTRIBUTE (noinline)
+VOID
+MemUDummyCLRead (
+  IN       UINT32 Address
+  )
+{
+  _mm_sfence ();
+  __readfsbyte (Address);
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+MemUMFenceInstr (
+  VOID
+  )
+{
+  _mm_mfence ();
+}
+
+//----------------------------------------------------------------------------
+// MemUFlushPattern:
+//
+//  Flush a pattern of 72 bit times (per DQ) from cache.  This procedure is used
+//  to ensure cache miss on the next read training.
+//
+//              In: Address   - Physical address to be flushed
+//                  ClCount   - number of cachelines to be flushed
+//FUNC_ATTRIBUTE(noinline)
+VOID
+MemUFlushPattern (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  UINTN Index;
+
+  // ssd - theory: a tlb flush is needed to avoid problems with clflush
+  __writemsr (0x20F, __readmsr (0x20F));
+
+  for (Index = 0; Index < ClCount; Index++) {
+    // mfence prevents speculative execution of the clflush
+    _mm_mfence ();
+    _mm_clflush_fs ((void *) (size_t) (Address + Index * 64));
+  }
+}
+
+//----------------------------------------------------------------------------
+
+//FUNC_ATTRIBUTE(noinline)
+VOID
+AlignPointerTo16Byte (
+  IN OUT   UINT8 **BufferPtrPtr
+  )
+{
+  size_t Address = (size_t) *BufferPtrPtr;
+  Address += 15;
+  Address -= Address % 16;
+  *BufferPtrPtr = (void *) Address;
+}
+
+//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
new file mode 100644
index 0000000000..751947962d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
@@ -0,0 +1,787 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * muc.c
+ *
+ * Utility functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "cpuServices.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mu.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCacheInit.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_MAIN_MUC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+CONST UINT32 Pattern2[16] = {
+  0x12345678, 0x87654321, 0x23456789, 0x98765432,
+  0x59385824, 0x30496724, 0x24490795, 0x99938733,
+  0x40385642, 0x38465245, 0x29432163, 0x05067894,
+  0x12349045, 0x98723467, 0x12387634, 0x34587623
+};
+
+CONST UINT32 MaxLatPat[48] = {
+  0x6E0E3FAC, 0x0C3CFF52,
+  0x4A688181, 0x49C5B613,
+  0x7C780BA6, 0x5C1650E3,
+  0x0C4F9D76, 0x0C6753E6,
+  0x205535A5, 0xBABFB6CA,
+  0x610E6E5F, 0x0C5F1C87,
+  0x488493CE, 0x14C9C383,
+  0xF5B9A5CD, 0x9CE8F615,
+
+  0xAAD714B5, 0xC38F1B4C,
+  0x72ED647C, 0x669F7562,
+  0x5233F802, 0x4A898B30,
+  0x10A40617, 0x3326B465,
+  0x55386E04, 0xC807E3D3,
+  0xAB49E193, 0x14B4E63A,
+  0x67DF2495, 0xEA517C45,
+  0x7624CE51, 0xF8140C51,
+
+  0x4824BD23, 0xB61DD0C9,
+  0x072BCFBE, 0xE8F3807D,
+  0x919EA373, 0x25E30C47,
+  0xFEB12958, 0x4DA80A5A,
+  0xE9A0DDF8, 0x792B0076,
+  0xE81C73DC, 0xF025B496,
+  0x1DB7E627, 0x808594FE,
+  0x82668268, 0x655C7783
+};
+
+CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54};
+
+CONST UINT8 PatternJD_256[256] = {
+  0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
+  0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF,
+  0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF,
+  0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF,
+  0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7,
+  0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF,
+  0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04,
+  0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB,
+  0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB,
+  0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04,
+  0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F,
+  0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F,
+  0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF,
+  0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF,
+  0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF,
+  0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40,
+  0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD,
+  0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF,
+  0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF,
+  0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF,
+  0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE,
+  0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01,
+  0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE,
+  0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF,
+  0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF,
+  0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF,
+  0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF,
+  0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF,
+  0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10,
+  0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10,
+  0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F,
+  0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF
+};
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the (index)th UINT8
+ *   from an indicated test pattern.
+ *
+ *     @param[in] Pattern - encoding of test pattern type
+ *     @param[in] Buffer[] - buffer to be filled
+ *     @param[in] Size - Size of the buffer
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUFillTrainPattern (
+  IN       TRAIN_PATTERN Pattern,
+  IN       UINT8 Buffer[],
+  IN       UINT16 Size
+  )
+{
+  UINT8 Result;
+  UINT8 i;
+  UINT8 Mask;
+  UINT16 Index;
+  UINT16 k;
+
+  for (Index = 0; Index < Size; Index++) {
+    k = Index;
+    // get one byte from Pattern
+    switch (Pattern) {
+    case TestPattern0:
+      Result = 0xAA;
+      break;
+    case TestPattern1:
+      Result = 0x55;
+      break;
+    case TestPattern2:
+      ASSERT (Index < sizeof (Pattern2));
+      Result = ((UINT8 *)Pattern2)[Index];
+      break;
+    case TestPatternML:
+      if (Size != 6 * 64) {
+        Result = ((UINT8 *)MaxLatPat)[Index];
+      } else {
+        Result = ((UINT8 *)MaxLatPat)[Index & 0xF7];
+      }
+      break;
+    case TestPatternJD256B:
+      k >>= 1;
+      // break is not being used here because TestPatternJD256B also need
+      // to run TestPatternJD256A sequence.
+    case TestPatternJD256A:
+      k >>= 3;
+      ASSERT (k < sizeof (PatternJD_256));
+      Result = PatternJD_256[k];
+      break;
+    case TestPatternJD1B:
+      k >>= 1;
+      // break is not being used here because TestPatternJD1B also need
+      // to run TestPatternJD1A sequence.
+    case TestPatternJD1A:
+      k >>= 3;
+      i = (UINT8) (k >> 3);
+      Mask = (UINT8) (0x80 >> (k & 7));
+
+      if (i == 0) {
+        Result = 0;
+      } else {
+        Result = (UINT16)1 << (i - 1);
+      }
+
+      ASSERT (i < sizeof (PatternJD));
+      if (PatternJD[i] & Mask) {
+        Result = ~Result;
+      }
+      break;
+    case TestPattern3:
+      Result = 0x36;
+      break;
+    case TestPattern4:
+      Result = 0xC9;
+      break;
+    default:
+      Result = 0;
+      IDS_ERROR_TRAP;
+    }
+
+    // fill in the Pattern buffer
+    Buffer[Index] = Result;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function flushes cache lines
+ *
+ *     @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *     @param[in] ClCount - Number of cache lines
+ *     @param[in] Address - System Address [47:16]
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUProcIOClFlush (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  MemUSetTargetWTIO (Address, MemPtr);
+  MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount);
+  MemUResetTargetWTIO (MemPtr);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Address - System Address [47:16]
+ *
+ *     @return  Address - Lowest 32-bit of physical address
+ * ----------------------------------------------------------------------------
+ */
+
+UINT32
+MemUSetUpperFSbase (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  SMsr.lo = 0;
+  SMsr.hi = Address >> 16;
+  LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  return Address << 16;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function resets the target address space to Write Through IO by disabling IORRs
+ *
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUResetTargetWTIO (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+  SMsr.hi = 0;
+  SMsr.lo = 0;
+  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function sets the target range to WT IO (using an IORR overlapping
+ *       the already existing
+ *
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Address - System Address [47:16]
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUSetTargetWTIO (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  SMsr.lo = Address << 16;
+  SMsr.hi = Address >> 16;
+  LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader);           // IORR0 Base
+  SMsr.hi = 0xFFFF;
+  SMsr.lo = 0xFC000800;
+  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);          // 64MB Mask
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of 10ns cycles
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Count - Number of 10ns cycles to wait; Note that Count must not exceed 1000000
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUWait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT64 TargetTsc;
+  UINT64 CurrentTsc;
+
+  ASSERT (Count <= 1000000);
+
+  MemUMFenceInstr ();
+
+  LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
+  TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100);
+  IEM_SKIP_CODE (IEM_WAIT) {
+    do {
+      LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
+    } while (CurrentTsc < TargetTsc);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Find the entry of platform specific overriding table.
+ *
+ *      @param[in] PlatformMemoryConfiguration - Platform config table
+ *      @param[in] EntryType - Entry type
+ *      @param[in] SocketID - Physical socket ID
+ *      @param[in] ChannelID - Physical channel ID
+ *      @param[in] DimmID - Physical Dimm ID
+ *      @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *      @param[in,out]  *StdHeader - Pointer of AMD_CONFIG_PARAMS
+ *                 - If both *LogicalIdPtr and *StdHeader are "NULL" input,
+ *                   that means, the "EntryType" are not CPU family dependent,
+ *                   ex. PSO_MAX_DIMMS for NUMBER_OF_DIMMS_SUPPORTED macro.
+ *
+ *
+ *      @return  NULL - entry could not be found.
+ *      @return  Pointer - points to the entry's data.
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID *
+FindPSOverrideEntry (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       PSO_ENTRY EntryType,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID,
+  IN       UINT8 DimmID,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *Buffer;
+  CPU_LOGICAL_ID LogicalCpuId;
+  UINT32 RawCpuId;
+
+  LogicalCpuId.Family = AMD_FAMILY_UNKNOWN;
+  LogicalCpuId.Revision = 0;
+  RawCpuId = 0;
+
+  Buffer = PlatformMemoryConfiguration;
+  //
+  // Do not need to look for CPU family specific PSO if LogicalIdPtr and StdHeader are NULL.
+  //
+  if ((LogicalIdPtr != NULL) && (StdHeader != NULL)) {
+    //
+    // Looking for the CPU family signature followed by CPUID value.
+    // And check to see if the CPUID value is matched with current CPU's :
+    //    - If matched, Buffer points to following PSO macros' start address.
+    //    - If not matched, Buffer points to PlatformMemoryConfiguration for global PSO parsing.
+    //
+    while (Buffer[0] != PSO_END) {
+      if (Buffer[0] == PSO_CPU_FAMILY_TO_OVERRIDE) {
+        RawCpuId = *(UINT32 *)&Buffer[2];
+        GetLogicalIdFromCpuid (RawCpuId, &LogicalCpuId, StdHeader);
+        if ((LogicalCpuId.Family & LogicalIdPtr->Family) != 0) {
+          if ((LogicalCpuId.Revision & LogicalIdPtr->Revision) != 0) {
+            Buffer += Buffer[1] + 2;
+            break;
+          }
+        }
+      }
+      Buffer += Buffer[1] + 2;
+    }
+    //
+    // If no CPU family specific PSO macros exist, Buffer points to PlatformMemoryConfiguration again
+    //
+    if (Buffer[0] == PSO_END) {
+      Buffer = PlatformMemoryConfiguration;
+    }
+  }
+
+  while ((Buffer[0] != PSO_END) && (Buffer[0] != PSO_CPU_FAMILY_TO_OVERRIDE)) {
+    if (Buffer[0] == EntryType) {
+      if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) {
+        if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) {
+          if ((Buffer[4] & ((UINT8) 1 << DimmID)) != 0 ) {
+            return &Buffer[5];
+          }
+        }
+      }
+    }
+    Buffer += Buffer[1] + 2;
+  }
+
+  return NULL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max dimms for a given memory channel on a given
+ *  processor.  It first searches the platform override table for the max dimms
+ *  value.  If it is not provided, the AGESA default value is returned. The target
+ *  socket must be a valid present socket.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID  - ID of the processor that owns the channel
+ *     @param[in] ChannelID - Channel to get max dimms for
+ *
+ *
+ *     @return UINT8 - Max Number of Dimms for that channel
+ */
+UINT8
+GetMaxDimmsPerChannel (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  )
+{
+  UINT8  *DimmsPerChPtr;
+  UINT8  MaxDimmPerCH;
+
+  DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID, 0, NULL, NULL);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL;
+  }
+  // Maximum number of dimms per channel cannot be larger than its default value.
+  ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL);
+
+  return MaxDimmPerCH;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max soldered-down dimms for a given memory channel on a given
+ *  processor.  It first searches the platform override table for the soldered-down dimms
+ *  value.  If it is not provided, the AGESA default value is returned. The target
+ *  socket must be a valid present socket.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID  - ID of the processor that owns the channel
+ *     @param[in] ChannelID - Channel to get max dimms for
+ *
+ *
+ *     @return UINT8 - Max Number of soldered-down dimms for that channel
+ */
+UINT8
+GetMaxSolderedDownDimmsPerChannel (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  )
+{
+  UINT8  *DimmsPerChPtr;
+  UINT8  MaxSolderedDownDimmPerCH;
+
+  DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_SOLDERED_DOWN_DIMMS, SocketID, ChannelID, 0, NULL, NULL);
+  if (DimmsPerChPtr != NULL) {
+    MaxSolderedDownDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxSolderedDownDimmPerCH = 0;
+  }
+  // Maximum number of dimms per channel cannot be larger than its default value.
+  ASSERT (MaxSolderedDownDimmPerCH <= MAX_DIMMS_PER_CHANNEL);
+
+  return MaxSolderedDownDimmPerCH;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max memory channels on a given processor.
+ *  It first searches the platform override table for the max channels value.
+ *  If it is not provided, the AGESA default value is returned.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] StdHeader - Header for library and services
+ *
+ *
+ *     @return UINT8 - Max Number of Channels on that Processor
+ */
+UINT8
+GetMaxChannelsPerSocket (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  *ChannelsPerSocketPtr;
+  UINT8  MaxChannelsPerSocket;
+
+  if (IsProcessorPresent (SocketID, StdHeader)) {
+    ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0, 0, NULL, NULL);
+    if (ChannelsPerSocketPtr != NULL) {
+      MaxChannelsPerSocket = *ChannelsPerSocketPtr;
+    } else {
+      MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET;
+    }
+    // Maximum number of channels per socket cannot be larger than its default value.
+    ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET);
+  } else {
+    MaxChannelsPerSocket = 0;
+  }
+
+  return MaxChannelsPerSocket;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max number of chip select on a given channel of
+ *  a given processor. It first searches the platform override table for the max
+ *  chip select value. If it is not provided, the AGESA default value is returned.
+ *  The target socket must be a valid present socket.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] ChannelID - ID of a channel
+ *
+ *
+ *     @return UINT8 - Max Number of chip selects on the channel of the Processor
+ */
+UINT8
+GetMaxCSPerChannel (
+  IN      PSO_TABLE *PlatformMemoryConfiguration,
+  IN      UINT8 SocketID,
+  IN      UINT8 ChannelID
+  )
+{
+  UINT8  *CSPerSocketPtr;
+  UINT8  MaxCSPerChannel;
+
+  CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID, 0, NULL, NULL);
+  if (CSPerSocketPtr != NULL) {
+    MaxCSPerChannel = *CSPerSocketPtr;
+  } else {
+    MaxCSPerChannel = MAX_CS_PER_CHANNEL;
+  }
+  // Max chip select per channel cannot be larger than its default value
+  ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL);
+
+  return MaxCSPerChannel;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the index of the first Dimm SPD structure for a
+ *  given processor socket. It checks the Max Dimms per channel for every memory
+ *  channel on every processor up to the current one, and adds them together.
+ *
+ *      This function may also be used to calculate the maximum dimms per system
+ *  by passing the total number of dimm sockets
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] StdHeader - Header for library and services
+ *
+ *     @return UINT8 - SPD Index
+ */
+UINT8
+GetSpdSocketIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 SpdSocketIndex;
+  UINT8 Socket;
+  UINT8 Channel;
+  UINT8  MaxChannelsPerSocket;
+
+  SpdSocketIndex = 0;
+  for (Socket = 0; Socket < SocketID; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel);
+    }
+  }
+  return SpdSocketIndex;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the index of the first Dimm SPD structure for a
+ *  given channel relative to the processor socket. It checks the Max Dimms per
+ *  channel for every memory channel on that processor up to the current one,
+ *  and adds them together.
+ *
+ *      This function may also be used to calculate the maximum dimms per system
+ *  by passing the total number of DIMM sockets
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] ChannelID - ID of the Channel
+ *     @param[in] StdHeader - Header for library and services
+ *
+ *     @return UINT8 - SPD Index
+ */
+UINT8
+GetSpdChannelIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 SpdChannelIndex;
+  UINT8 Channel;
+
+  SpdChannelIndex = 0;
+  ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader))
+  for (Channel = 0; Channel < ChannelID; Channel++) {
+    SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel);
+  }
+  return SpdChannelIndex;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the upper 32 bits mask for variable MTRR based on
+ *     the CPU_LOGICAL_ID.
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *     @param[in]       StdHeader - Header for library and services
+ *
+ *     @return          UINT32 - MTRR mask for upper 32 bits
+ *
+ */
+UINT32
+GetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempNotCare;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  CONST CACHE_INFO *CacheInfoPtr;
+
+  GetCpuServicesFromLogicalId (LogicalIdPtr, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &TempNotCare, StdHeader);
+  return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
+}
+
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns number of memclk converted from ns
+ *     @param[in]       Speed - memclk frequency
+ *     @param[in]       NumberOfns - number of ns to be converted
+ *
+ *     @return          UINT32 - number of memclk
+ *
+ */
+UINT32
+MemUnsToMemClk (
+  IN       MEMORY_BUS_SPEED Speed,
+  IN       UINT32 NumberOfns
+  )
+{
+  return (UINT32) ((NumberOfns * Speed + 999) / 1000);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h
new file mode 100644
index 0000000000..7014b8a00c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h
@@ -0,0 +1,111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnS3tn.h
+ *
+ * S3 resume memory related function for TN.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MNS3TN_H_
+#define _MNS3TN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of TN
+typedef enum {
+  PCI_LST_ESR_TN,  ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_TN,      ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_TN, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_TN,     ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_TN,  ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_TN,      ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_TN, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_TN      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDTN;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define SET_S3_NB_PSTATE_OFFSET(Offset, NBPstate) ((NBPstate << 10) | Offset)
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3TN_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c
new file mode 100644
index 0000000000..6bbcb70b93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c
@@ -0,0 +1,906 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mndcttn.c
+ *
+ * Northbridge DCT support for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63661 $ @e \$Date: 2012-01-03 01:02:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "mntn.h"
+#include "mftds.h"
+#include "merrhdl.h"
+#include "cpuFamRegisters.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCommonF15Utilities.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_MEM_NB_TN_MNDCTTN_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+#define MAX_RD_DQS_DLY 0x1F
+
+CONST BIT_FIELD_NAME MemPstateBF[4] = {BFMemPstate0, BFMemPstate1, BFMemPstate2, BFMemPstate3};
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT32
+STATIC
+MemNTotalSyncComponentsTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
+ */
+
+BOOLEAN
+MemNAutoConfigTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT32 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  //
+  //======================================================================
+  // Build Dram Config Lo Register Value
+  //======================================================================
+  MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
+  MemNSetBitFieldNb (NBPtr, BFPendRefPaybackS3En, 1);
+  MemNSetBitFieldNb (NBPtr, BFStagRefEn, 1);
+  //
+  //======================================================================
+  // Build Dram Config Hi Register Value
+  //======================================================================
+  //
+  //
+  // MemClkFreq
+  //
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DCTPtr->Timings.Speed));
+
+  PowerDownMode = 1;
+  IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+  MemNSetBitFieldNb (NBPtr, BFPowerDownMode, PowerDownMode);
+
+  if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) {
+    MemNBrdcstSetNb (NBPtr, BFM1MemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DDR667_FREQUENCY));
+    MemNBrdcstSetNb (NBPtr, BFRate, MemNGetMemClkFreqIdUnb (NBPtr, DDR667_FREQUENCY) | 0x8);
+    MemNBrdcstSetNb (NBPtr, BFMxMrsEn, 7);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFDphyMemPsSelEn, 1);
+  //
+  //======================================================================
+  // Build Dram MRS Register Value
+  //======================================================================
+  //
+  MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1);
+  MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 1);
+
+  //======================================================================
+  // DRAM Controller Miscellaneous 2
+  //======================================================================
+  MemNSetBitFieldNb (NBPtr, BFPerRankTimingEn, 1);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\nEnable Per Rank Training....\n\n");
+  MemNSetBitFieldNb (NBPtr, BFPrtlChPDEnhEn, 0);
+  MemNSetBitFieldNb (NBPtr, BFAggrPDEn, 1);
+
+  //======================================================================
+  // GMC to DCT control
+  //======================================================================
+  MemNSetBitFieldNb (NBPtr, BFGmcTokenLimit, 4);
+  MemNSetBitFieldNb (NBPtr, BFMctTokenLimit, 4);
+  MemNSetBitFieldNb (NBPtr, BFGmcToDctControl1, 0x4444);
+  if ((MCTPtr->LogicalCpuid.Revision & 0x0000000000000100ull ) != 0) {
+    MemNSetBitFieldNb (NBPtr, BFCpuElevPrioDis, 1);
+  }
+
+  //======================================================================
+  // Other Registers
+  //======================================================================
+  //
+  //
+  // Non-SPD Timings
+  //
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, 0x17);
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, 0x16);
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, 0xB );
+
+  MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, 0xB);
+  MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, 0xB);
+  MemNSetBitFieldNb (NBPtr, BFTrdrdDd, 0xB);
+
+  MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, 0xB);
+  MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, 0xB);
+  MemNSetBitFieldNb (NBPtr, BFTwrwrDd, 0xB);
+
+  MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_TN);
+  MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_TN);
+  MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, DEFAULT_RD_ODT_TRNONDLY_TN);
+
+  for (i = 0; i < 4; i++) {
+    MemNSetBitFieldNb (NBPtr, BFTstag0 + i, 0x14);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFTmrd, 4);
+  MemNSetBitFieldNb (NBPtr, BFFlushWrOnS3StpGnt, 1);
+  MemNSetBitFieldNb (NBPtr, BFFastSelfRefEntryDis, 0);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function caps speed based on battery life check.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+VOID
+MemNCapSpeedBatteryLifeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT16 SupportedFreq[] = {
+    DDR2133_FREQUENCY,
+    DDR1866_FREQUENCY,
+    DDR1600_FREQUENCY,
+    DDR1333_FREQUENCY,
+    DDR1066_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR667_FREQUENCY
+  };
+
+  UINT32 FreqNumeratorInMHz;
+  UINT32 FreqDivisor;
+  UINT32 VoltageInuV;
+  UINT32 NBFreq;
+  UINT16 DdrFreq;
+  UINT16 j;
+  INT8   NbPs;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN SkipAdjustNbPs;
+
+  FamilySpecificServices = NULL;
+  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
+
+
+  // Find the lowest supported NB Pstate
+  NBFreq = 0;
+  for (NbPs = 3; NbPs >= 0; NbPs--) {
+    if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
+                                                  NBPtr->MemPtr->PlatFormConfig,
+                                                  &NBPtr->PciAddr,
+                                                  (UINT32) NbPs,
+                                                  &FreqNumeratorInMHz,
+                                                  &FreqDivisor,
+                                                  &VoltageInuV,
+                                                  &(NBPtr->MemPtr->StdHeader))) {
+      if (MemNGetBitFieldNb (NBPtr, MemPstateBF[NbPs]) == 0) {
+        NBFreq = FreqNumeratorInMHz / FreqDivisor;
+        break;
+      }
+    }
+  }
+
+  ASSERT (NBFreq > 0);
+
+  // Pick Max MEMCLK that is less than or equal to NCLK
+  DdrFreq = DDR800_FREQUENCY;
+  for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
+    if (NBFreq >= ((UINT32) SupportedFreq[j])) {
+      DdrFreq = SupportedFreq[j];
+      break;
+    }
+  }
+
+  // Cap MemClk frequency to lowest NCLK frequency
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
+  }
+
+  // Adjust the NB P-state northbridge voltage
+  SkipAdjustNbPs = FALSE;
+  IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipAdjustNbPs, &(NBPtr->MemPtr->StdHeader));
+  if (SkipAdjustNbPs == FALSE) {
+    MemNAdjustNBPstateVolTN (NBPtr);
+  }
+
+  // Initialize NbPsCtlReg
+  NBPtr->NbPsCtlReg = 0;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retrieves the Max latency parameters
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @param[in]  *MinDlyPtr - Pointer to variable to store the Minimum Delay value
+ *     @param[in]  *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
+ *     @param[in]  *DlyBiasPtr - Pointer to variable to store Delay Bias value
+ *     @param[in]  MaxRcvEnDly - Maximum receiver enable delay value
+ */
+
+VOID
+MemNGetMaxLatParamsTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  )
+{
+  UINT32 N;
+  UINT32 T;
+  UINT32 P;
+  UINT32 MemClkPeriod;
+
+  // 1. P = N = T = 0.
+  P = N = T = 0;
+
+  // Get all sync components BKDG steps 3,4,6
+  P = MemNTotalSyncComponentsTN (NBPtr);
+
+  // 7. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] +
+  //    D18F2x9C_x0000_0[3:0]0[7:5]_dct[1:0][RdDqsTime] PCLKs)) + 1
+  P = P + (MaxRcvEnDly + 31) / 32 + 1;
+
+  // 10. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs.
+  MemClkPeriod = 1000000 / ((NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : DDR667_FREQUENCY);
+  N = ((((P * MemClkPeriod + 1) / 2) + T) * NBPtr->NBClkFreq + 999999) / 1000000;
+
+  // Calculate a starting MaxRdLatency delay value with steps 5, 9, and 12 excluded
+  *MinDlyPtr = (UINT16) N;
+
+  *MaxDlyPtr = 0x3FF;
+
+  // Left edge of MaxRdLat will be added with 1 NCLK and 3 PCLK (1.5 MEMCLK)
+  N = 1;
+  P = 3;
+  N += (((P * MemClkPeriod + 1) / 2) * NBPtr->NBClkFreq + 999999) / 1000000;
+  *DlyBiasPtr = (UINT16) N;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function  sets the maximum round-trip latency in the system from the processor to the DRAM
+ *   devices and back.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     MaxRcvEnDly - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemNSetMaxLatencyTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  )
+{
+  UINT32 N;
+  UINT32 T;
+  UINT32 P;
+  UINT32 Px2;
+  UINT32 MemClkPeriod;
+
+  AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
+
+  //
+  // Initial value for MaxRdLat used in training
+  //
+  N = 0x55;
+
+  if (MaxRcvEnDly != 0xFFFF) {
+    // 1. P = N = T = 0.
+    P = N = T = 0;
+
+    // Get all sync components BKDG steps 3,4,6
+    P = MemNTotalSyncComponentsTN (NBPtr);
+
+    // 5. P = P + 5
+    P += 5;
+
+    // 7. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] +
+    //    D18F2x9C_x0000_0[3:0]0[6:5]_dct[1:0][RdDqsTime] PCLKs)) + 1
+    P = P + ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32 + 1;
+
+    // 8. If (NclkFreq/MemClkFreq < 2) then P = P + 4.5 Else P = P + 2.5
+    if ((NBPtr->NBClkFreq / NBPtr->DCTPtr->Timings.Speed) < 2) {
+      Px2 = P * 2 + 9;
+    } else {
+      Px2 = P * 2 + 5;
+    }
+
+    // 9. T = T + 1050 ps
+    T += 1050;
+
+    // 10. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs.
+    MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+    N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000;
+
+    // 11. D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] = CEIL(N) - 1
+    N = N - 1;
+  }
+
+  NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N;
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N);
+  MemNSetBitFieldNb (NBPtr, BFMaxLatency, N);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function set MaxRdLat after HW receiver enable training is completed
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNExitPhyAssistedTrainingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+  MEM_TECH_BLOCK  *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Calculate Max Latency for both channels to prepare for position training
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN ; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+
+    // Reset DisAutoRefresh and ZqcsInterval for position training.
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+      MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+      MemNSetBitFieldNb (NBPtr, BFRx4thStgEn, 0);
+      MemNSetBitFieldNb (NBPtr, BFRxBypass3rd4thStg, 4);
+    }
+
+    if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
+      NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat);
+    }
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the total of sync components for Max Read Latency calculation
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Total in PCLKs
+ */
+UINT32
+STATIC
+MemNTotalSyncComponentsTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 P;
+
+  P = 0;
+
+  // 3. If (D18F2x9C_x0000_0004_dct[1:0][AddrCmdSetup] = 0 & D18F2x9C_x0000_0004_dct[1:0][CsOdt-
+  // Setup] = 0 & D18F2x9C_x0000_0004_dct[1:0][CkeSetup] = 0)
+  // then P = P + 1
+  // else P = P + 2
+  if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
+    P += 1;
+  } else {
+    P += 2;
+  }
+
+  // 4. P = P + (8 - D18F2x210_dct[1:0]_nbp[3:0][RdPtrInit])
+  P = P + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit));
+
+  // 6. P = P + (2 * (D18F2x200_dct[1:0][Tcl] - 1 clocks))
+  P = P + (2 * (MemNGetBitFieldNb (NBPtr, BFTcl) - 1));
+
+  return P;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function calculates and programs NB P-state dependent registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramNbPstateDependentRegistersTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 RdPtrInit;
+  UINT8 Dct;
+  MEMORY_BUS_SPEED MemClkSpeed;
+
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      break;
+    }
+  }
+
+  if (MemNGetBitFieldNb (NBPtr, MemPstateBF[MemNGetBitFieldNb (NBPtr, BFNbPsSel)]) == 0) {
+    MemClkSpeed = NBPtr->DCTPtr->Timings.Speed;
+  } else {
+    MemClkSpeed = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq));
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMemclk Freq: %d\n", MemClkSpeed);
+
+  // NCLK:MCLK ratio    DDR rate (MT/s)       RdPtrInit
+  // < 2:1              < 2133                0011b (2.5T)
+  // < 2:1              2133 <= rate <= 2400  0011b (2.5T) or 0010b (3T)
+  // For each NB P-state, IF any D18F2x9C_x0000_0[3:0]0[2:1]_dct[1:0]_mp[MemPstate][WrDat-
+  // GrossDly] ==0 THEN RdPtrInit=0010b ELSE RdPtrInit=0011b
+  // >=2:1              < 1866                0110b
+  // >=2:1              1866 <= rate < 2400   0101b
+  // >=2:1              2400                  0100b
+  if (NBPtr->NBClkFreq < (UINT32) (MemClkSpeed * 2)) {
+    RdPtrInit = ((MemClkSpeed >= DDR2133_FREQUENCY) && (NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessWrDatDly, FALSE) == 0)) ? 2 : 3;
+  } else {
+    RdPtrInit = (MemClkSpeed < DDR1866_FREQUENCY) ? 6 : ((MemClkSpeed < DDR2400_FREQUENCY) ? 5 : 4);
+  }
+  MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
+
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      // Set ProcOdtAdv
+      if ((NBPtr->ChannelPtr->SODimmPresent != 0) && (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY)) {
+        MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
+      } else {
+        MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000);
+      }
+    }
+  }
+
+  MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0);
+
+  IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
+  MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM init
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDramInitTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      //
+      // 2.10.6.7 DCT Training Specific Configuration
+      //
+      MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 0);
+      MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+      MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0);
+      MemNSetBitFieldNb (NBPtr, BFDynPageCloseEn, 0);
+      MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 0);
+      MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0);
+      MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 0);
+      MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+      MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0);
+      MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0);
+      MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0);
+      MemNSetBitFieldNb (NBPtr, BFBankSwap, 0);
+      MemNSetBitFieldNb (NBPtr, BFODTSEn, 0);
+      MemNSetBitFieldNb (NBPtr, BFDctSelIntLvEn, 0);
+      MemNSetBitFieldNb (NBPtr, BFCmdThrottleMode, 0);
+      MemNSetBitFieldNb (NBPtr, BFBwCapEn, 0);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function modifies CS interleaving low address according to several conditions for TN.
+ *
+ *     @param[in,out]  *NBPtr    - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  *LowBit   - Pointer to low bit
+ *
+ */
+
+BOOLEAN
+MemNCSIntLvLowAddrAdjTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *LowBit
+  )
+{
+  UINT8 DctSelIntLvAddr;
+
+  DctSelIntLvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr);
+  //
+  //D18F2x[5C:40]_dct[1:0][15:5] = BaseAddr[21:11] &&
+  //D18F2x[6C:60]_dct[1:0][15:5] = AddrMask[21:11], so *LowBit needs to be added with 2.
+  //
+  *(UINT8 *) LowBit += 2;
+
+  if (MemNGetBitFieldNb (NBPtr, BFBankSwap) == 1) {
+    if (DctSelIntLvAddr == 4) {
+      *(UINT8 *) LowBit = 5;
+    } else {
+      *(UINT8 *) LowBit = 6;
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function releases the NB P-state force.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   OptParam - Optional parameter
+ *
+ *     @return    TRUE
+ */
+BOOLEAN
+MemNReleaseNbPstateTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+
+  // 6. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0] values.
+  MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF9FFF) | (NBPtr->NbPsCtlReg & 0x6000));
+  // 7. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values.
+  MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFFF13F) | (NBPtr->NbPsCtlReg & 0x0EC0));
+  // 8. Restore the initial D18F5x170[NbPstateLo] values.
+  MemNSetBitFieldNb (NBPtr, BFNbPstateLo, (NBPtr->NbPsCtlReg >> 3) & 3);
+
+  // Clear NbPsSel to 0
+  MemNSetBitFieldNb (NBPtr, BFNbPsSel, 0);
+  // Update TSC rate
+  FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
+
+  if (MemNGetBitFieldNb (NBPtr, BFMemPsSel) != 0) {
+    MemNChangeMemPStateContextNb (NBPtr, 0);
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function handles multiple stage of training when multiple Mem Pstate is enabled
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNMemPstateStageChangeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  BOOLEAN RetVal;
+  TRN_DLY_TYPE AccessType;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT8 ByteLane;
+  UINT16 CsEnabled;
+  UINT16 TrnDly;
+
+  RetVal = FALSE;
+
+  if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) {
+    MemNChangeMemPStateContextNb (NBPtr, 1);
+    // Load memory registers in M1 context from data saved in the heap
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nLoad Training registers for M1 with DDR667 training result\n");
+    for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        // Save MemPstate 1 data in output data structures
+        LibAmdMemCopy  (NBPtr->ChannelPtr->RcvEnDlysMemPs1, NBPtr->ChannelPtr->RcvEnDlys, (MAX_DIMMS * MAX_DELAYS) * 2, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->RdDqsDlysMemPs1, NBPtr->ChannelPtr->RdDqsDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->WrDqsDlysMemPs1, NBPtr->ChannelPtr->WrDqsDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->WrDatDlysMemPs1, NBPtr->ChannelPtr->WrDatDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->RdDqs2dDlysMemPs1, NBPtr->ChannelPtr->RdDqs2dDlys, MAX_DIMMS * MAX_NUMBER_LANES, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->RdDqsMinDlysMemPs1, NBPtr->ChannelPtr->RdDqsMinDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->RdDqsMaxDlysMemPs1, NBPtr->ChannelPtr->RdDqsMaxDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->WrDatMinDlysMemPs1, NBPtr->ChannelPtr->WrDatMinDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->WrDatMaxDlysMemPs1, NBPtr->ChannelPtr->WrDatMaxDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+        LibAmdMemCopy  (NBPtr->ChannelPtr->FailingBitMaskMemPs1, NBPtr->ChannelPtr->FailingBitMask, MAX_CS_PER_CHANNEL * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader));
+
+        CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+        // Set Memory Pstate 1 training value into registers
+        for (AccessType = AccessRcvEnDly; AccessType <= AccessWrDqsDly; AccessType ++) {
+          for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL_TN; ChipSel = ChipSel + NBPtr->CsPerDelay) {
+            if ((CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSel)) != 0) {
+              for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+                TrnDly = (UINT16) GetTrainDlyFromHeapNb (NBPtr, AccessType, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane));
+                NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane), TrnDly);
+              }
+            }
+          }
+        }
+
+        if (NBPtr->RefPtr->EnablePowerDown) {
+          MemNSetTxpNb (NBPtr);
+          MemNSetBitFieldNb (NBPtr, BFPchgPDEnDelay, (MAX (MAX ((NBPtr->DCTPtr->Timings.CasL + 5),
+                                                                (UINT8) (MemNGetBitFieldNb (NBPtr, BFTcwl) + NBPtr->DCTPtr->Timings.Twr + 5)),
+                                                           (UINT8) MemNGetBitFieldNb (NBPtr, BFTmod))));
+          MemNSetBitFieldNb (NBPtr, BFAggrPDDelay, 0x20);
+        }
+        MemNSetOtherTimingTN (NBPtr);
+        // Save timing data structure for memory Pstate 1
+        LibAmdMemCopy  (NBPtr->DCTPtr->TimingsMemPs1, &(NBPtr->DCTPtr->Timings), sizeof (CH_TIMING_STRUCT), &(NBPtr->MemPtr->StdHeader));
+
+        MemFInitTableDrive (NBPtr, MTAfterMemPstate1PartialTrn);
+      }
+    }
+
+    // Switch back to M0 context
+    MemNChangeMemPStateContextNb (NBPtr, 0);
+
+    // Load memory registers in M1 context from data saved in the heap
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nGoing into training stage 2. Complete training at DDR667 is done.\n");
+    NBPtr->MemPstateStage = MEMORY_PSTATE_2ND_STAGE;
+  } else if ((NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE) && (NBPtr->DCTPtr->Timings.TargetSpeed == NBPtr->DCTPtr->Timings.Speed)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nGoing into training stage 3. Partial training at all frequencies is done.\n");
+    NBPtr->MemPstateStage = MEMORY_PSTATE_3RD_STAGE;
+    RetVal = TRUE;
+  } else {
+    // MemPstate is disabled. Do not go through the MemPstate handling flow.
+    RetVal = TRUE;
+  }
+
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Sets Power Down options and enables Power Down
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     The following registers are set:
+ *      BFPowerDownMode         BFPrtlChPDEnhEn
+ *      BFTxp                   BFAggrPDDelay
+ *      BFTxpDll                BFAggrPDEn
+ *      BFPchgPDEnDelay         BFPowerDownEn
+ *
+ * NOTE:  Delay values must be set before turning on the associated Enable bit
+ */
+VOID
+MemNPowerDownCtlTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 PowerDownMode;
+  UINT8 Tmod;
+  UINT8 Twr;
+  UINT8 Tcwl;
+  UINT8 Tcl;
+
+  if (NBPtr->RefPtr->EnablePowerDown) {
+    //
+    // PowerDownMode
+    //
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode == 1) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+    //
+    // Txp
+    //
+    MemNSetTxpNb (NBPtr);
+    //
+    // PchgPDModeSel is set elswhere.
+    //
+    // PchgPDEnDelay = MAX(Tcl + 5, Tcwl + Twr + 5, Tmod)
+    //
+    Tmod = (UINT8) MemNGetBitFieldNb (NBPtr, BFTmod);
+    Twr = NBPtr->DCTPtr->Timings.Twr;
+    Tcwl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcwl);
+    Tcl = NBPtr->DCTPtr->Timings.CasL;
+    MemNSetBitFieldNb (NBPtr, BFPchgPDEnDelay, (MAX (MAX ((Tcl + 5), (Tcwl + Twr + 5)), Tmod)));
+    //
+    // Partial Channel Power Down
+    //
+    MemNSetBitFieldNb (NBPtr, BFPrtlChPDDynDly, 0);
+    MemNSetBitFieldNb (NBPtr, BFPrtlChPDEnhEn, 0);
+    //
+    // Aggressive PowerDown
+    //
+    MemNSetBitFieldNb (NBPtr, BFAggrPDDelay, 0x20);
+    MemNSetBitFieldNb (NBPtr, BFAggrPDEn, 1);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Always set upper 2 bits of CKETri bitfield
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNBeforePlatformSpecTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFCKETri, 0xC | MemNGetBitFieldNb (NBPtr, BFCKETri));
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
new file mode 100644
index 0000000000..a00fd2fb94
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
@@ -0,0 +1,156 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnflowtn.c
+ *
+ * TN initializer for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mntn.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_MEM_NB_TN_MNFLOWTN_FILECODE
+/* features */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function selects appropriate Tech functions for the NB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNTechBlockSwitchTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Specify Dimm-Byte training for Nb
+  MemTDimmByteTrainInit (TechPtr);
+
+  // Remove the following functions because they are not needed for TN
+  TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
+  TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
+  TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
+  TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb;
+  TechPtr->ResetDCTWrPtr = MemTResetRcvFifoUnb;
+}
+
+/*----------------------------------------------------------------------------
+ *                            LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c
new file mode 100644
index 0000000000..ea93ecfc2a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c
@@ -0,0 +1,172 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnidendimmtn.c
+ *
+ * TN northbridge constructor for dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "OptionMemory.h"
+#include "mntn.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->NodeCount = 1;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_TN;
+  NBPtr->CsRegMsk = 0x7FF8FFE0;
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Ganged = FALSE;
+  MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable);
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c
new file mode 100644
index 0000000000..def21eee36
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c
@@ -0,0 +1,562 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnmcttn.c
+ *
+ * Northbridge TN MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "GnbRegistersTN.h"
+#include "GnbRegisterAccTN.h"
+#include "mm.h"
+#include "mn.h"
+#include "OptionMemory.h"
+#include "mntn.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#include "mftds.h"
+#include "mu.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_MEM_NB_TN_MNMCTTN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _16MB_RJ16  0x0100
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function force memory Pstate to M0
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNInitializeMctTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0);
+  MemNSetBitFieldNb (NBPtr, BFEnSplitMctDatBuffers, 1);
+
+  MemUMFenceInstr ();
+  MemNSetBitFieldNb (NBPtr, BFMctEccDisLatOptEn, 1);
+  MemUMFenceInstr ();
+
+  MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0);
+
+  MemNForcePhyToM0Unb (NBPtr);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets final values for specific registers.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNFinalizeMctTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DRAM_PREFETCH_MODE DramPrefetchMode;
+  UINT16 Speed;
+  UINT32 Value32;
+  UINT8 DcqBwThrotWm1;
+  UINT8 DcqBwThrotWm2;
+  UINT8 Dct;
+
+  MemPtr = NBPtr->MemPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+  DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+
+  //
+  // F2x11C
+  //
+  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x0CE00F31);
+  if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) {
+    MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1);
+  }
+
+  if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) {
+    MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1);
+  }
+
+
+  if (Speed == DDR667_FREQUENCY) {
+    DcqBwThrotWm1 = 3;
+    DcqBwThrotWm2 = 4;
+  } else if (Speed == DDR800_FREQUENCY) {
+    DcqBwThrotWm1 = 3;
+    DcqBwThrotWm2 = 5;
+  } else if (Speed == DDR1066_FREQUENCY) {
+    DcqBwThrotWm1 = 4;
+    DcqBwThrotWm2 = 6;
+  } else if (Speed == DDR1333_FREQUENCY) {
+    DcqBwThrotWm1 = 5;
+    DcqBwThrotWm2 = 8;
+  } else if  (Speed == DDR1600_FREQUENCY) {
+    DcqBwThrotWm1 = 6;
+    DcqBwThrotWm2 = 9;
+  } else if  (Speed == DDR1866_FREQUENCY) {
+    DcqBwThrotWm1 = 7;
+    DcqBwThrotWm2 = 10;
+  } else {
+    DcqBwThrotWm1 = 8;
+    DcqBwThrotWm2 = 12;
+  }
+  //
+  // F2x1B0
+  //
+  Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
+  Value32 &= 0x003FE8C0;
+  Value32 |= 0x0FC01001;
+  MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, Value32);
+
+  //
+  // F2x1B4
+  //
+  Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgHiReg);
+  Value32 &= 0xFFFFFC00;
+  Value32 |= (((UINT32) DcqBwThrotWm2 << 5) | (UINT32) DcqBwThrotWm1);
+  MemNSetBitFieldNb (NBPtr, BFExtMctCfgHiReg, Value32);
+
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      //
+      // Phy Power Saving
+      //
+      MemNPhyPowerSavingMPstateUnb (NBPtr);
+      if (NBPtr->MemPstateStage == MEMORY_PSTATE_3RD_STAGE) {
+        MemNChangeMemPStateContextNb (NBPtr, 1);
+        MemNPhyPowerSavingMPstateUnb (NBPtr);
+        MemFInitTableDrive (NBPtr, MTAfterSettingMemoryPstate1);
+        MemNChangeMemPStateContextNb (NBPtr, 0);
+      }
+      //
+      // Power Down Enable
+      //
+      if (NBPtr->RefPtr->EnablePowerDown) {
+        MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+      }
+    }
+  }
+
+  // Set LockDramCfg
+  if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
+    IDS_SKIP_HOOK (IDS_LOCK_DRAM_CFG, NBPtr, &NBPtr->MemPtr->StdHeader) {
+      MemNSetBitFieldNb (NBPtr, BFLockDramCfg, 1);
+    }
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function create the HT memory map for TN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNHtMemMapInitTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 WeReMask;
+  UINT32 BottomIo;
+  UINT32 HoleOffset;
+  UINT32 DctSelBaseAddr;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  //
+  // Physical addresses in this function are right adjusted by 16 bits ([47:16])
+  // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit.
+  //
+
+  // Enforce bottom of IO be be 128MB aligned
+  BottomIo = (RefPtr->BottomIo & 0xF8) << 8;
+
+  if (MCTPtr->NodeMemSize != 0) {
+    NodeSysBase = 0;
+    NodeSysLimit = MCTPtr->NodeMemSize - 1;
+    DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize;
+
+    if (NodeSysLimit >= BottomIo) {
+      // HW Dram Remap
+      MCTPtr->Status[SbHWHole] = TRUE;
+      RefPtr->GStatus[GsbHWHole] = TRUE;
+      MCTPtr->NodeHoleBase = BottomIo;
+      RefPtr->HoleBase = BottomIo;
+
+      HoleOffset = _4GB_RJ16 - BottomIo;
+
+      NodeSysLimit += HoleOffset;
+
+      if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) {
+        HoleOffset += DctSelBaseAddr;
+      } else {
+        if (DctSelBaseAddr >= BottomIo) {
+          DctSelBaseAddr += HoleOffset;
+        }
+        HoleOffset += NodeSysBase;
+      }
+
+      MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8);
+      MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7);
+      MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1);
+      MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1);
+    } else {
+      // No Remapping.  Normal Contiguous mapping
+    }
+    MCTPtr->NodeSysBase = NodeSysBase;
+    MCTPtr->NodeSysLimit = NodeSysLimit;
+    RefPtr->SysLimit = MCTPtr->NodeSysLimit;
+
+    WeReMask = 3;
+    // Set the Dram base and set the WE and RE flags in the base.
+    MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask);
+    MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0, NodeSysBase >> 24);
+    // Set the Dram limit and set DstNode.
+    MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000));
+    MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0, NodeSysLimit >> 24);
+
+    MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16));
+    MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16));
+
+    if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
+      MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11);
+      MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1);
+      MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1);
+      MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10);
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Report the Uma size that is going to be allocated.
+ *     Total system memory   UMASize
+ *     >= 2G                 512M
+ *     >=1G                  256M
+ *     <1G                    64M
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          Uma size [31:0] = Addr [47:16]
+ */
+UINT32
+MemNGetUmaSizeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 SysMemSize;
+  UINT32 SizeOfUma;
+
+  SysMemSize = NBPtr->RefPtr->SysLimit + 1;
+  SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000;   // Ignore 16MB allocated for C6 when finding UMA size
+  if (SysMemSize >= 0x8000) {
+    SizeOfUma = 512 << (20 - 16);
+  } else if (SysMemSize >= 0x4000) {
+    SizeOfUma = 256 << (20 - 16);
+  } else {
+    SizeOfUma = 64 << (20 - 16);
+  }
+
+  return SizeOfUma;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function allocates 16MB of memory for C6 storage when it is requested to be enabled
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNAllocateC6StorageTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 SysLimit;
+  UINT32 DramLimitReg;
+
+  if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
+
+    SysLimit = NBPtr->RefPtr->SysLimit;
+
+    // Calculate new SysLimit
+    if (!NBPtr->SharedPtr->C6Enabled) {
+      // System memory available is reduced by 16MB
+      SysLimit -= _16MB_RJ16;
+
+      NBPtr->MCTPtr->NodeSysLimit = SysLimit;
+      NBPtr->RefPtr->SysLimit = SysLimit;
+      NBPtr->SharedPtr->C6Enabled = TRUE;
+
+      // Set TOPMEM and MTRRs (only need to be done once for BSC)
+      MemNC6AdjustMSRs (NBPtr);
+    }
+
+    // Set Dram Limit
+    DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0) & 0x0000FFFF;
+    MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg);
+    MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0, SysLimit >> 24);
+
+    MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, 0);
+
+    // Set BFCC6SaveEn
+    MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1);
+    // LockDramCfg will be set in FinalizeMCT
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function adjusts NB pstate norbridge voltage for TN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNAdjustNBPstateVolTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+
+  D0F0xBC_xE0104168_STRUCT D0F0xBC_xE0104168;
+  D0F0xBC_xE010416C_STRUCT D0F0xBC_xE010416C;
+  D0F0xBC_xE0104170_STRUCT D0F0xBC_xE0104170;
+  UINT8 MemClkVidHi;
+  UINT8 MemClkVidLo;
+  UINT8 MemPstate;
+  UINT8 NbVid;
+  UINT8 NbPs;
+  UINT8 NbPstateMaxVal;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nStart NB Pstate voltage adjustment.\n");
+
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0104168_ADDRESS, &D0F0xBC_xE0104168.Value, 0, &(NBPtr->MemPtr->StdHeader));
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010416C_ADDRESS, &D0F0xBC_xE010416C.Value, 0, &(NBPtr->MemPtr->StdHeader));
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0104170_ADDRESS, &D0F0xBC_xE0104170.Value, 0, &(NBPtr->MemPtr->StdHeader));
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE0104168: %08x\n", D0F0xBC_xE0104168.Value);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE010416C: %08x\n", D0F0xBC_xE010416C.Value);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE0104170: %08x\n", D0F0xBC_xE0104170.Value);
+
+  // MemClkVidHi = read D0F0xBC_xE0104168 through D0F0xBC_xE0104170 to find the VID code corresponding
+  // to the M0 MEMCLK. If the M0 MEMCLK is not found, use the next higher defined MEMCLK as the target.
+  switch (NBPtr->DCTPtr->Timings.TargetSpeed) {
+  case DDR667_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid0_7_0;
+    break;
+  case DDR800_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid1_7_0;
+    break;
+  case DDR1066_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid2_7_0;
+    break;
+  case DDR1333_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid3_1_0 | ((UINT8) D0F0xBC_xE010416C.Field.MemClkVid3_7_2 << 2);
+    break;
+  case DDR1600_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid4_7_0;
+    break;
+  case DDR1866_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid5_7_0;
+    break;
+  case DDR2100_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid6_7_0;
+    break;
+  case DDR2133_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid7_1_0 | ((UINT8) D0F0xBC_xE0104170.Field.MemClkVid7_7_2 << 2);
+    break;
+  case DDR2400_FREQUENCY:
+    MemClkVidHi = (UINT8) D0F0xBC_xE0104170.Field.MemClkVid8_7_0;
+    break;
+  default:
+    // If the M0 MEMCLK is greater than MemClkVid8, use the MemClkVid8 VID as the target
+    MemClkVidHi = (UINT8) D0F0xBC_xE0104170.Field.MemClkVid8_7_0;
+  }
+
+  // MemClkVidLo = read D0F0xBC_xE0104168 through D0F0xBC_xE0104170 to find the VID code corresponding
+  // to the M1 MEMCLK. If the M1 MEMCLK is not found, use the next higher defined MEMCLK as the target.
+  MemClkVidLo = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid0_7_0;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tOriginal MemClkVidLo: %02x\n", MemClkVidLo);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tOriginal MemClkVidHi: %02x\n", MemClkVidHi);
+
+  // If D18F5x188[NbOffsetTrim] == 01b, MemClkVid = Fuse[MemClkVid] - 4 (-25mV offset so add 25mV to VID)
+  // Else if D18F5x188[NbOffsetTrim] == 11b, MemClkVid = Fuse[MemClkVid] + 4 (+25mV offset so decrease 25mV from VID)
+  // Else MemClkVid = Fuse[MemClkVid]
+  if (MemNGetBitFieldNb (NBPtr, BFNbOffsetTrim) == 1) {
+    MemClkVidLo -= 4;
+    MemClkVidHi -= 4;
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdd 25mV\n");
+  } else if (MemNGetBitFieldNb (NBPtr, BFNbOffsetTrim) == 3) {
+    MemClkVidLo += 4;
+    MemClkVidHi += 4;
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDecrease 25mV\n");
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdjusted MemClkVidLo: %02x\n", MemClkVidLo);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdjusted MemClkVidHi: %02x\n", MemClkVidHi);
+
+  // For each NB P-state from NBP0 through D18F5x170[NbPstateMaxVal]:
+  // If ((D18F5x1[6C:60][MemPstate] == 0) && (MemClkVidHi voltage > D18F5x1[6C:60][NbVid] voltage)):
+  // Program D18F5x1[6C:60][NbVid] == MemClkVidHi.
+  // If ((D18F5x1[6C:60][MemPstate] == 1) && (MemClkVidLo voltage > D18F5x1[6C:60][NbVid] voltage)):
+  // Program D18F5x1[6C:60][NbVid] == MemClkVidLo.
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tNBPs\tNbVid\tMemPstate\tOverride\n");
+  NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal);
+  for (NbPs = 0; NbPs <= NbPstateMaxVal; NbPs ++) {
+    NbVid = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1));
+    MemPstate = (UINT8) MemNGetBitFieldNb (NBPtr, BFMemPstate0 + NbPs);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t  %01d \t  %02x  \t    %01d     \t", NbPs, NbVid, MemPstate);
+    // higher voltage correspond to smaller VID
+    if ((MemPstate == 0) && (MemClkVidHi < NbVid)) {
+      MemNSetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1), MemClkVidHi);
+      IDS_HDT_CONSOLE (MEM_FLOW, "MemClkVidHi\n");
+    } else if ((MemPstate == 1) && (MemClkVidLo < NbVid)) {
+      MemNSetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1), MemClkVidLo);
+      IDS_HDT_CONSOLE (MEM_FLOW, "MemClkVidLo\n");
+    } else {
+      IDS_HDT_CONSOLE (MEM_FLOW, "No change\n");
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c
new file mode 100644
index 0000000000..821bb1d63d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c
@@ -0,0 +1,348 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnottn.c
+ *
+ * Northbridge Non-SPD timings for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "OptionMemory.h"
+#include "mntn.h"
+#include "mu.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_MEM_NB_TN_MNOTTN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+#if 0
+UINT32
+STATIC
+MemNGetODTDelaysTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+#endif
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNOtherTimingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Programming of Non-SPD Timings.\n");
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
+      MemNSetOtherTimingTN (NBPtr);
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings  in PCI registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSetOtherTimingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 ROD;
+  INT8 WOD;
+  INT8 LD;
+  INT8 WrEarlyx2;
+  INT8 CDDTrdrdSdDc;
+  INT8 CDDTrdrdDd;
+  INT8 CDDTwrwrDd;
+  INT8 CDDTwrwrSdDc;
+  INT8 CDDTrwtTO;
+  INT8 CDDTwrrd;
+  UINT8 TrdrdSdDc;
+  UINT8 TrdrdDd;
+  UINT8 TwrwrSdDc;
+  UINT8 TwrwrDd;
+  UINT8 TrdrdSdSc;
+  UINT8 TwrwrSdSc;
+  UINT8 Twrrd;
+  UINT8 TrwtTO;
+  BOOLEAN PerRankTimingEn;
+
+  CH_DEF_STRUCT *ChannelPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  PerRankTimingEn = (BOOLEAN) (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn));
+  //
+  // Latency Difference (LD) = Tcl - Tcwl
+  //
+  LD = (INT8) (MemNGetBitFieldNb (NBPtr, BFTcl)) - (INT8) (MemNGetBitFieldNb (NBPtr, BFTcwl));
+
+  //
+  // Read ODT Delay (ROD) = MAX ( 0, (RdOdtOnDuration - 6)) + MAX ( 0, (RdOdtTrnOnDly - LD))
+  //
+  ROD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtOnDuration) - 6)) +
+          MAX ( 0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtTrnOnDly) - LD));
+  //
+  // Write ODT Delay (WOD) = MAX (0, (WrOdtOnDuration - 6))
+  //
+  WOD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFWrOdtOnDuration) - 6));
+  //
+  // WrEarly = ABS (WrDqDqsEarly) / 2
+  //
+  WrEarlyx2 = (INT8) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLD: %d     ROD: %d     WOD: %d     WrEarlyx2: %d\n\n", LD, ROD, WOD, WrEarlyx2);
+  //
+  // Read to Read Timing (TrdrdSdSc, TrdrdScDc, TrdrdDd)
+  //
+  // TrdrdSdSc = 1.
+  // TrdrdSdDc (in MEMCLKs) = MAX(TrdrdSdSc, 3 + (IF (D18F2xA8_dct[1:0][PerRankTimingEn])
+  //             THEN CEIL(CDDTrdrdSdDc / 2 ) ELSE 0 ENDIF)).
+  // TrdrdDd   = MAX(TrdrdSdDc, CEIL(MAX(ROD + 3, CDDTrdrdDd/2 + 3.5)))
+  //
+  TrdrdSdSc = 1;
+
+  CDDTrdrdSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, TRUE, FALSE);
+  TrdrdSdDc = MAX (0, PerRankTimingEn ? (3 + (CDDTrdrdSdDc + 1) / 2) : 3);
+  TrdrdSdDc = MAX (TrdrdSdSc, TrdrdSdDc);
+
+  CDDTrdrdDd = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE);
+  TrdrdDd = MAX (ROD + 3, (CDDTrdrdDd + 7 + 1) / 2);
+  TrdrdDd = MAX (TrdrdSdDc, TrdrdDd);
+
+  MemNSetBitFieldNb (NBPtr, BFTrdrdDd, (UINT32) TrdrdDd);
+  MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, (UINT32) TrdrdSdDc);
+  MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, (UINT32) TrdrdSdSc);
+  //
+  // Write to Write Timing (TwrwrSdSc, TwrwrScDc, TwrwrDd)
+  //
+  // TwrwrSdSc = 1.
+  // TwrwrSdDc = CEIL(MAX(WOD + 3, CDDTwrwrSdDc / 2 +
+  //            (IF (D18F2xA8_dct[1:0][PerRankTimingEn]) THEN 3.5 ELSE 3 ENDIF))).
+  //
+  // TwrwrDd = CEIL (MAX (WOD + 3, CDDTwrwrDd / 2 + 3.5))
+  // TwrwrSdSc <= TwrwrSdDc <= TwrwrDd
+  //
+  TwrwrSdSc = 1;
+
+  CDDTwrwrSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, TRUE, FALSE);
+  TwrwrSdDc = (UINT8) MAX (WOD + 3, (CDDTwrwrSdDc + (PerRankTimingEn ? 7 : 6) + 1 ) / 2);
+
+  CDDTwrwrDd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE);
+  TwrwrDd = (UINT8) MAX ((UINT8) (WOD + 3), (CDDTwrwrDd + 7 + 1) / 2);
+
+  TwrwrSdDc = (TwrwrSdSc <= TwrwrSdDc) ? TwrwrSdDc : TwrwrSdSc;
+  TwrwrDd = (TwrwrSdDc <= TwrwrDd) ? TwrwrDd : TwrwrSdDc;
+
+  MemNSetBitFieldNb (NBPtr, BFTwrwrDd, (UINT32) TwrwrDd);
+  MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, (UINT32) TwrwrSdDc);
+  MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, (UINT32) TwrwrSdSc);
+  //
+  // Write to Read DIMM Termination Turn-around
+  //
+  // Twrrd = MAX ( 1, CEIL (MAX (WOD, (CDDTwrrd / 2) + 0.5 - WrEarly) - LD + 3))
+  //
+  CDDTwrrd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, TRUE);
+  Twrrd =  MAX (1, MAX (WOD, (CDDTwrrd + 1 - WrEarlyx2 + 1) / 2) - LD + 3);
+
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT32) Twrrd);
+  //
+  // Read to Write Turnaround for Data, DQS Contention
+  //
+  // TrwtTO = CEIL (MAX (ROD, (CDDTrwtTO / 2) - 0.5 + WrEarly) + LD + 3)
+  //
+  CDDTrwtTO = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE);
+
+  TrwtTO = MAX ((ChannelPtr->Dimms == 1 ? 0 : ROD) , (CDDTrwtTO - 1 + WrEarlyx2 + 1) / 2) + LD + 3;
+
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT32) TrwtTO);
+  //
+  // Read to Write Turnaround for opportunistic Write Bursting
+  //
+  // TrwtWB = TrwtTO + 1
+  //
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, (UINT32) TrwtTO + 1);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t                            TrdrdSdSc : %02x\n", TrdrdSdSc);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdSdDc : %02x           TrdrdSdDc : %02x\n", CDDTrdrdSdDc, TrdrdSdDc);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdDd   : %02x           TrdrdDd   : %02x\n\n", CDDTrdrdDd, TrdrdDd);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t                            TwrwrSdSc  : %02x\n", TwrwrSdSc);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrSdDc : %02x           TwrwrSdDc : %02x\n", CDDTwrwrSdDc, TwrwrSdDc );
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrDd   : %02x           TwrwrDd   : %02x\n\n", CDDTwrwrDd, TwrwrDd);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t                            TrwtWB    : %02x\n", TrwtTO + 1);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd     : %02x           Twrrd     : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd );
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO    : %02x           TrwtTO    : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO );
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the ODT delays
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+#if 0
+UINT32
+STATIC
+MemNGetODTDelaysTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Ld;
+  UINT32 ODTDelays;
+  //
+  // The BIOS must additionally configure the ODT pattern
+  // and the ODT switching delays.
+  //
+  // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
+  //     -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
+  //     -Value of 2, BL = 4 else assume BL=8.
+  //     -Initialize ODTDelays based on BL value
+  //     -WrOdtOnDuration [14:12] = BL / 2 + 1
+  //     -WrOdtTrnOnDly [10:8] = 0
+  //     -RdOdtOnDuration [6:4] = BL / 2 + 1
+  //
+  ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
+
+  // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
+  // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
+  Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
+  if (Ld < 0) {
+    Ld = 0;
+  }
+  if (Ld > 7) {
+    Ld = 7;
+  }
+  ODTDelays += Ld;
+  return ODTDelays;
+}
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c
new file mode 100644
index 0000000000..8a0199420f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c
@@ -0,0 +1,742 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnphytn.c
+ *
+ * Northbridge Phy support for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "ma.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
+#include "mntn.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_MEM_NB_TN_MNPHYTN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+
+/// The structure of TxPrePN tables
+typedef struct {
+  UINT32 Speed;                          ///< Applied memory speed
+  UINT16 TxPrePNVal[4];                  ///< Table values
+} TXPREPN_STRUCT;
+
+/// The entry of individual TxPrePN tables
+typedef struct {
+  UINT8 TxPrePNTblSize;                  ///< Total Table size
+  CONST TXPREPN_STRUCT *TxPrePNTblPtr;   ///< Pointer to the table
+} TXPREPN_ENTRY;
+
+/// Type of an entry for processing phy init compensation for TN
+typedef struct {
+  BIT_FIELD_NAME IndexBitField;          ///< Bit field on which the value is decided
+  BIT_FIELD_NAME StartTargetBitField;    ///< First bit field to be modified
+  BIT_FIELD_NAME EndTargetBitField;      ///< Last bit field to be modified
+  UINT16 ExtraValue;                     ///< Extra value needed to be written to bit field
+  CONST TXPREPN_ENTRY *TxPrePN;          ///< Pointer to slew rate table
+} PHY_COMP_INIT_NB;
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemNRdPosTrnTN (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
+/* -----------------------------------------------------------------------------*/
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  //
+  // Phy Predriver Calibration Codes for Data/DQS
+  //
+  CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV15TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V
+    {DDR667 + DDR800, {0x924, 0x924, 0x924, 0x924}},
+    {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV135TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V
+    {DDR667 + DDR800, {0xFF6, 0xB6D, 0xB6D, 0x924}},
+    {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV125TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V
+    {DDR667 + DDR800, {0xFF6, 0xDAD, 0xDAD, 0x924}},
+    {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC TXPREPN_ENTRY TxPrePNDataDqsTN[] = {
+    {GET_SIZE_OF (TxPrePNDataDqsV15TN), (TXPREPN_STRUCT *)&TxPrePNDataDqsV15TN},
+    {GET_SIZE_OF (TxPrePNDataDqsV135TN), (TXPREPN_STRUCT *)&TxPrePNDataDqsV135TN},
+    {GET_SIZE_OF (TxPrePNDataDqsV125TN), (TXPREPN_STRUCT *)&TxPrePNDataDqsV125TN}
+  };
+
+  //
+  // Phy Predriver Calibration Codes for Cmd/Addr
+  //
+  CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV15TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V
+    {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}},
+    {DDR1066 + DDR1333, {0x6DB, 0x6DB, 0x6DB, 0x6DB}},
+    {DDR1600 + DDR1866 + DDR2133, {0xB6D, 0xB6D, 0xB6D, 0xB6D}}
+  };
+  CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV135TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V
+    {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}},
+    {DDR1066 + DDR1333, {0x924, 0x6DB, 0x6DB, 0x6DB}},
+    {DDR1600 + DDR1866 + DDR2133, {0xB6D, 0xB6D, 0x924, 0x924}}
+  };
+  CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV125TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V
+    {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}},
+    {DDR1066 + DDR1333, {0xDAD, 0x924, 0x6DB, 0x492}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xDAD, 0xB64, 0xB64}}
+  };
+  CONST STATIC TXPREPN_ENTRY TxPrePNCmdAddrTN[] = {
+    {GET_SIZE_OF (TxPrePNCmdAddrV15TN), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV15TN},
+    {GET_SIZE_OF (TxPrePNCmdAddrV135TN), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV135TN},
+    {GET_SIZE_OF (TxPrePNCmdAddrV125TN), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV125TN}
+  };
+
+  //
+  // Phy Predriver Calibration Codes for Clock
+  //
+  CONST STATIC TXPREPN_STRUCT TxPrePNClockV15TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V
+    {DDR667 + DDR800, {0x924, 0x924, 0x924, 0x924}},
+    {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xB6D}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC TXPREPN_STRUCT TxPrePNClockV135TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V
+    {DDR667 + DDR800, {0xDAD, 0xDAD, 0x924, 0x924}},
+    {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xDAD}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xDAD}}
+  };
+  CONST STATIC TXPREPN_STRUCT TxPrePNClockV125TN[] = {
+    //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V
+    {DDR667 + DDR800, {0xDAD, 0xDAD, 0x924, 0x924}},
+    {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC TXPREPN_ENTRY TxPrePNClockTN[] = {
+    {GET_SIZE_OF (TxPrePNClockV15TN), (TXPREPN_STRUCT *)&TxPrePNClockV15TN},
+    {GET_SIZE_OF (TxPrePNClockV135TN), (TXPREPN_STRUCT *)&TxPrePNClockV135TN},
+    {GET_SIZE_OF (TxPrePNClockV125TN), (TXPREPN_STRUCT *)&TxPrePNClockV125TN}
+  };
+
+  //
+  // Tables to describe the relationship between drive strength bit fields, PreDriver Calibration bit fields and also
+  // the extra value that needs to be written to specific PreDriver bit fields
+  //
+  CONST PHY_COMP_INIT_NB PhyCompInitBitFieldTN[] = {
+    // 3. Program TxPreP/TxPreN for Data and DQS according toTable 25 if VDDIO is 1.5V or Table 26 if 1.35V.
+    //    A. Program D18F2x9C_x0D0F_0[F,7:0]0[A,6]_dct[1:0]={0000b, TxPreP, TxPreN}.
+    //    B. Program D18F2x9C_x0D0F_0[F,7:0]02_dct[1:0]={0000b, TxPreP, TxPreN}.
+    {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqsTN},
+    {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqsTN},
+    {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqsTN},
+    // 4. Program TxPreP/TxPreN for Cmd/Addr according to Table 28 if VDDIO is 1.5V or Table 29 if 1.35V.
+    //    A. Program D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[1:0]={0000b, TxPreP, TxPreN}.
+    //    B. Program D18F2x9C_x0D0F_[C,8][1:0]02_dct[1:0]={1000b, TxPreP, TxPreN}.
+    {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddrTN},
+    {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddrTN},
+    {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddrTN},
+    {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddrTN},
+    {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddrTN},
+    // 5. Program TxPreP/TxPreN for Clock according to Table 31 if VDDIO is 1.5V or Table 32 if 1.35V.
+    //    A. Program D18F2x9C_x0D0F_2[2:0]02_dct[1:0]={1000b, TxPreP, TxPreN}.
+    {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock2TxPreDriverCalPad0, 8, TxPrePNClockTN}
+  };
+
+  BIT_FIELD_NAME CurrentBitField;
+  UINT32 SpeedMask;
+  UINT8 SizeOfTable;
+  UINT8 Voltage;
+  UINT8 i;
+  UINT8 j;
+  UINT8 k;
+  UINT8 Dct;
+  CONST TXPREPN_STRUCT *TblPtr;
+
+  Dct = NBPtr->Dct;
+  NBPtr->SwitchDCT (NBPtr, 0);
+  // 1. Program D18F2x[1,0]9C_x0000_0008[DisAutoComp, DisablePreDriverCal] = {1b, 1b}.
+  MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 3);
+  NBPtr->SwitchDCT (NBPtr, Dct);
+
+  SpeedMask = (UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66);
+  Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage);
+
+  for (j = 0; j < GET_SIZE_OF (PhyCompInitBitFieldTN); j ++) {
+    i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitFieldTN[j].IndexBitField);
+    TblPtr = (PhyCompInitBitFieldTN[j].TxPrePN[Voltage]).TxPrePNTblPtr;
+    SizeOfTable = (PhyCompInitBitFieldTN[j].TxPrePN[Voltage]).TxPrePNTblSize;
+    for (k = 0; k < SizeOfTable; k++, TblPtr++) {
+      if ((TblPtr->Speed & SpeedMask) != 0) {
+        for (CurrentBitField = PhyCompInitBitFieldTN[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitFieldTN[j].EndTargetBitField; CurrentBitField ++) {
+          MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitFieldTN[j].ExtraValue << 12) | TblPtr->TxPrePNVal[i]));
+        }
+        break;
+      }
+    }
+    // Asserting if no table is found corresponding to current memory speed.
+    ASSERT (k < SizeOfTable);
+  }
+  NBPtr->SwitchDCT (NBPtr, 0);
+  // 6. Program D18F2x9C_x0000_0008_dct[1:0]_mp[1:0][DisAutoComp] = 0.
+  MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 1);
+  NBPtr->SwitchDCT (NBPtr, Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDQSTrainingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      MemNSetBitFieldNb (NBPtr, BFTrNibbleSel, 0);
+      //
+      // 2.10.6.9.2 - BIOS should program D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] to 55h.
+      //
+      MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x55);
+      NBPtr->CsPerDelay = MemNCSPerDelayNb (NBPtr);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a function that executes after DRAM training for TN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNAfterDQSTrainingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN DllShutDownEn;
+  UINT8 Dimm;
+  UINT8 Byte;
+  UINT16 Dly;
+
+  DllShutDownEn = TRUE;
+  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
+
+  MemNBrdcstSetNb (NBPtr, BFMemPhyPllPdMode, 2);
+  MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x190);
+
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      //
+      // 2.10.6.7 DCT Training Specific Configuration
+      //
+      MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1);
+      MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
+      if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
+        MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
+      }
+      MemNSetBitFieldNb (NBPtr , BFForceAutoPchg, 0);
+      MemNSetBitFieldNb (NBPtr , BFDynPageCloseEn, 0);
+      if (NBPtr->RefPtr->EnableBankSwizzle) {
+        MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
+      }
+      MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0x01F);
+      MemNPowerDownCtlTN (NBPtr);
+      MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
+      MemNSetBitFieldNb (NBPtr, BFBankSwap, 1);
+      //
+      // Post Training values for BFRxMaxDurDllNoLock, BFTxMaxDurDllNoLock,
+      //  and BFEnRxPadStandby are handled by Power savings code
+      //
+      // BFBwCapEn and BFODTSEn are handled by OnDimmThermal Code
+      //
+      // BFDctSelIntLvEn is programmed by Interleaving feature
+      //
+    }
+  }
+  //
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      if (!(NBPtr->DctCachePtr->excel846 )) {
+        for (Dimm = 0; Dimm < 4; Dimm++) {
+          for (Byte = 0; Byte < 9; Byte++) {
+            Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte));
+            MemNSetTrainDlyNb (NBPtr, excel845 , DIMM_NBBL_ACCESS (Dimm, Byte * 2), Dly);
+            MemNSetTrainDlyNb (NBPtr, excel845 , DIMM_NBBL_ACCESS (Dimm, (Byte * 2) + 1), Dly);
+          }
+        }
+      }
+    }
+  }
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function overrides the seed for hardware based RcvEn training of TN.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *SeedPtr - Pointer to the seed value.
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNOverrideRcvEnSeedTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *SeedPtr
+  )
+{
+  *(UINT16 *)SeedPtr = 0x32 - (0x20 * (UINT16) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly));
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function choose the correct PllLockTime for TN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *PllLockTime -  Bit offset of the field to be programmed
+ *
+ *     @return    TRUE
+ */
+BOOLEAN
+MemNAdjustPllLockTimeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *PllLockTime
+  )
+{
+  if (MemNGetBitFieldNb (NBPtr, BFMemPhyPllPdMode) == 2) {
+    *(UINT16*) PllLockTime = 0x190;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function overrides the seed for hardware based WL for TN.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *SeedPtr - Pointer to the seed value.
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNOverrideWLSeedTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *SeedPtr
+  )
+{
+  if (NBPtr->ChannelPtr->SODimmPresent != 0) {
+    *(UINT8*) SeedPtr = 0xE;
+  } else {
+    // Unbuffered dimm
+    *(UINT8*) SeedPtr = 0x15;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function adjusts Avg PRE value of Phy fence training for TN.
+ *
+ *     @param[in,out]   *NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Value16 - Pointer to the value that we want to adjust
+ *
+ */
+VOID
+MemNPFenceAdjustTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   INT16 *Value16
+  )
+{
+  if (*Value16 < 0) {
+    *Value16 = 0;
+  }
+
+  // This makes sure the phy fence value will be written to M1 context as well.
+  MULTI_MPSTATE_COPY_TSEFO (NBPtr->NBRegTable, BFPhyFence);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function programs Fence2RxDll for TN.
+ *
+ *     @param[in,out]   *NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Fence2Data - Pointer to the value of fence2 data
+ *
+ */
+BOOLEAN
+MemNProgramFence2RxDllTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Fence2Data
+  )
+{
+  UINT8 Dct;
+  UINT16 Fence2RxDllTxPad;
+  UINT16 Fence2Value;
+  UINT16 Fence1;
+  BIT_FIELD_NAME BitField;
+
+  Fence2Value = (UINT16) MemNGetBitFieldNb (NBPtr, BFFence2);
+  Fence2RxDllTxPad = (*(UINT16*) Fence2Data & 0x1F) | (((*(UINT16*) Fence2Data >> 5) & 0x1F) << 10);
+
+  Fence2Value &= ~(UINT16) ((0x1F << 10) | 0x1F);
+  Fence2Value |= Fence2RxDllTxPad;
+  MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Value);
+
+  if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) {
+    MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 16, BFPhyFence);
+    BitField = (NBPtr->Dct == 0) ? BFChAM1FenceSave : BFChBM1FenceSave;
+
+    Fence1 = (UINT16) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+    Dct = NBPtr->Dct;
+    MemNSwitchDCTNb (NBPtr, 1);
+    MemNSetBitFieldNb (NBPtr, BitField, Fence1);
+    MemNSwitchDCTNb (NBPtr, Dct);
+  }
+
+  return TRUE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function checks if RdDqsDly needs to be restarted for Trinity
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Center - Center of the data eye
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNRdDqsDlyRestartChkTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Center
+  )
+{
+  INT8 EyeCenter;
+  UINT8 ByteLane;
+  BOOLEAN RetVal;
+  MEM_TECH_BLOCK *TechPtr;
+  CH_DEF_STRUCT *ChanPtr;
+
+  TechPtr = NBPtr->TechPtr;
+  ChanPtr = NBPtr->ChannelPtr;
+  ByteLane = NBPtr->TechPtr->Bytelane;
+  RetVal = TRUE;
+
+  // If the average value of passing read DQS delay for the lane is negative, then adjust the input receiver
+  // DQ delay in D18F2x9C_x0D0F_0[F,7:0][5F,1F]_dct[1:0] for the lane as follows:
+
+  EyeCenter = ((INT8) ChanPtr->RdDqsMinDlys[ByteLane] + (INT8) ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2;
+
+  if ((EyeCenter < 0) && (NBPtr->RdDqsDlyRetrnStat != RDDQSDLY_RTN_SUSPEND)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "        Negative data eye center.\n");
+
+    if (MemNGetBitFieldNb (NBPtr, BFRxBypass3rd4thStg) == 4) {
+      // IF (RxBypass3rd4thStg == 1) program RxBypass3rd4thStg=0 and repeat step 3 above for all
+      // ranks and lanes
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tRxByPass3rd4thStg is 1, clear it and restart RdDqsDly training on current Dct.\n");
+
+      MemNSetBitFieldNb (NBPtr, BFRxBypass3rd4thStg, 0);
+      NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_ONGOING;
+
+      // When Retrain condition is first detected, record the current chipsel at which the retrain starts
+      // so we don't need to retrain RcvEnDly and WrDatDly on the chipsels that are already done with these steps.
+      TechPtr->RestartChipSel = (INT8) TechPtr->ChipSel;
+
+      RetVal = FALSE;
+    } else if (MemNGetBitFieldNb (NBPtr, BFRx4thStgEn) == 0) {
+      // ELSEIF (Rx4thStgEn == 0) program Rx4thStgEn=1 and repeat step 3 above for all ranks and lanes
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tRx4thStg is 0, set it and restart RdDqsDly training on current Dct.\n");
+
+      MemNSetBitFieldNb (NBPtr, BFRx4thStgEn, 0x100);
+      NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_ONGOING;
+
+      // If the second retrain starts beyond the chip selects that are previously trained, update the record so
+      // we don't need to retrain RcvEnDly and WrDatDly
+      if (TechPtr->RestartChipSel < ((INT8) TechPtr->ChipSel)) {
+        TechPtr->RestartChipSel = (INT8) TechPtr->ChipSel;
+      }
+
+      RetVal = FALSE;
+    } else {
+      // ELSE program the read DQS delay for the lane with a value of zero
+      IDS_HDT_CONSOLE (MEM_FLOW, "                                                   ");
+      IDS_HDT_CONSOLE (MEM_FLOW, "Center of data eye is still negative after 2 retires. Do not restart training, just use 0\n");
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t  ");
+      *(UINT8 *) Center = 0;
+    }
+  }
+
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function executes RdDQS training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+*/
+BOOLEAN
+MemNRdPosTrnTN (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  BOOLEAN RetVal;
+
+  if (((INT8) TechPtr->ChipSel) > TechPtr->RestartChipSel) {
+    RetVal = MemTRdPosWithRxEnDlySeeds3 (TechPtr);
+  } else {
+    // Skip RcvEnDly cycle training when current chip select has already gone through that step.
+    // Because a retrain condition can only be detected on a chip select after RcvEnDly cycle training
+    // So when current chip select is equal to RestartChipSel, we don't need to redo RcvEnDly cycle training.
+    // Only redo DQS position training.
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tSkip RcvEnDly Cycle Training on Current Chip Select.\n\n");
+    RetVal = MemTTrainDQSEdgeDetect (TechPtr);
+  }
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function skips WrDatDly training when a retrain condition is just detected
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *ChipSel - Pointer to ChipSel
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNHookBfWrDatTrnTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *ChipSel
+  )
+{
+  BOOLEAN RetVal;
+
+  RetVal = TRUE;
+  if (NBPtr->RdDqsDlyRetrnStat == RDDQSDLY_RTN_ONGOING) {
+    NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED;
+    // Clear chipsel value to force a restart of Rd Dqs Training
+    if (NBPtr->CsPerDelay == 1) {
+      *(UINT8 *) ChipSel = 0xFF;
+    } else {
+      *(UINT8 *) ChipSel = 0xFE;
+    }
+
+    RetVal = FALSE;
+  } else if (((INT8) NBPtr->TechPtr->ChipSel) < NBPtr->TechPtr->RestartChipSel) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSkip WrDatDly Training on Current Chip Select.\n\n");
+    // Skip WrDatDly training when current chip select has gone through WrDatDly procedure
+    // A retrain is detected during RdDqsDly training, so if RestartChipSel is equal to current
+    // chip select, then WrDatDly has not been started for current chip select in the previous cycle.
+    // However, RcvEnDly cycle training has been done for current chip select.
+    // So we don't need to do RcvEnDly cycle training when current chip select is equal to RestartChipSel
+    // but we need to do WrDatDly training for current chip select.
+    RetVal = FALSE;
+  }
+
+  // when return is FALSE, WrDatDly training will be skipped
+
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function sets up output driver and write leveling mode in MR1 during WL
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Value   - MR1 value
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNWLMR1TN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Value
+  )
+{
+  BOOLEAN Target;
+
+  // For the target rank of the target DIMM, enable write leveling mode and enable the output driver.
+  // For all other ranks of the target DIMM, enable write leveling mode and disable the output driver.
+  Target = (BOOLEAN) (*(UINT16 *) Value >> 7) & 1;
+
+  if (NBPtr->CsPerDelay == 1) {
+    // Clear Qoff and reset it based on TN requirement
+    *(UINT16 *) Value &= ~((UINT16) 1 << 12);
+
+    if (!Target) {
+      *(UINT16 *) Value |= (((UINT16) 1 << 7) | ((UINT16) 1 << 12));
+    }
+  }
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c
new file mode 100644
index 0000000000..385416575c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c
@@ -0,0 +1,856 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnregtn.c
+ *
+ * Common Northbridge register related functions for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Gnb.h"
+#include "GnbCommonLib.h"
+#include "GnbRegistersTN.h"
+#include "GnbRegisterAccTN.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mntn.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_MEM_NB_TN_MNREGTN_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define PHY_DIRECT_ADDRESS_MASK   0x0D000000ul
+
+STATIC CONST UINT8 InstancesPerTypeTN[8] = {8, 3, 1, 2, 2, 0, 1, 1};
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemNIsIdSupportedTn
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a TN.
+ *     @return          FALSE - This node is not a TN.
+ *
+ */
+BOOLEAN
+MemNIsIdSupportedTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+  if (((LogicalIdPtr->Family & AMD_FAMILY_15_TN) != 0)
+      && ((LogicalIdPtr->Revision & (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  ) != 0)) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field to be programmed
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNCmnGetSetFieldTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  TSEFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT8 IsLinked;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+  UINT8  IsPhyDirectAccess;
+  UINT8  IsWholeRegAccess;
+  UINT8  NumOfInstances;
+  UINT8  Instance;
+  UINT8  IsMultipleMPstate;
+
+  Value = 0;
+  if (FieldName == BFDctAccessDone) {
+    // No need to poll DctAccessDone for TN due to enhancement in phy
+    Value = 1;
+  } else if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = (UINT8) TSEFO_TYPE (Address);
+      IsLinked = (UINT8) TSEFO_LINKED (Address);
+      IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address);
+      IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address);
+      if (NBPtr->MemPstate == MEMORY_PSTATE0) {
+        IsMultipleMPstate = TSEFO_MULTI_MPSTATE_COPY (Address);
+      } else {
+        // Do not write in both instances when context is already in MP1
+        IsMultipleMPstate = 0;
+      }
+
+      Address = TSEFO_OFFSET (Address);
+
+      // By default, a bit field has only one instance
+      NumOfInstances = 1;
+
+      if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
+        Address |= PHY_DIRECT_ADDRESS_MASK;
+        if (IsWholeRegAccess) {
+          // In the case of whole regiter access (bit 0 to 15),
+          // HW broadcast and nibble mask will be used.
+          Address |= Lowbit << 16;
+          Lowbit = 0;
+          Highbit = 15;
+        } else {
+          // In the case only some bits on a register is accessed,
+          // BIOS will do read-mod-write to all chiplets manually.
+          // And nibble mask will be 1111b always.
+          if ((Address & 0xFFFF) == 0xE008) {
+          // Special case for PStateToAccess, which use nibble mask
+            Address |= 0x00040000;
+          } else {
+            Address |= 0x000F0000;
+          }
+          Field >>= Lowbit;
+          if ((Address & 0x0F00) == 0x0F00) {
+            // Broadcast mode
+            // Find out how many instances to write to
+            NumOfInstances = InstancesPerTypeTN[(Address >> 13) & 0x7];
+            if (!IsSet) {
+              // For read, only read from instance 0 in broadcast mode
+              NumOfInstances = 1;
+            }
+          }
+        }
+      }
+
+      ASSERT (NumOfInstances > 0);
+
+      for (Instance = 0; Instance < NumOfInstances; Instance++) {
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+          PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+          PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+          Address = PciAddr.AddressValue;
+          LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+          if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) {
+            IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n",
+                             NBPtr->PciAddr.Address.Device, NBPtr->Dct,
+                             (Address >> 12) & 0xF, Address & 0xFFF, Value);
+          }
+        } else if (Type == DCT_PHY_ACCESS) {
+          if (IsPhyDirectAccess && (NumOfInstances > 1)) {
+            Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8);
+          }
+          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+          IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn2_9C_%x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, Address & 0x0FFFFFFF, Value);
+        } else {
+          // DCT_EXTRA_ACCESS is not supported on TN
+          ASSERT (FALSE);
+        }
+
+        if (IsSet) {
+          // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+          if ((Highbit - Lowbit) != 31) {
+            Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+          } else {
+            Mask = (UINT32)0xFFFFFFFF;
+          }
+          Value &= ~(Mask << Lowbit);
+          Value |= (Field & Mask) << Lowbit;
+
+          do {
+            if (Type == NB_ACCESS) {
+              PciAddr.AddressValue = Address;
+              LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+              if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) {
+                IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n",
+                                 NBPtr->PciAddr.Address.Device, NBPtr->Dct,
+                                 (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
+              }
+            } else if (Type == DCT_PHY_ACCESS) {
+              MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+              Address |= DCT_ACCESS_WRITE;
+              MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+              IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn2_9C_%x [%d:%d] = %x\n",
+                               NBPtr->PciAddr.Address.Device, NBPtr->Dct,
+                               Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
+            } else {
+              // DCT_EXTRA_ACCESS is not supported on TN
+              ASSERT (FALSE);
+            }
+            if (IsLinked) {
+              MemNCmnGetSetFieldTN (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+            }
+            if (IsMultipleMPstate && (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE)) {
+              // if there are multiple Pstate register copies, program register in M1 context when the frequency is DDR667
+              if (NBPtr->MemPstate == MEMORY_PSTATE0) {
+                MemNChangeMemPStateContextNb (NBPtr, 1);
+              } else {
+                // Switch back to M0 context
+                MemNChangeMemPStateContextNb (NBPtr, 0);
+              }
+            }
+          } while ((NBPtr->MemPstate == MEMORY_PSTATE1) && IsMultipleMPstate && (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE));
+        } else {
+          Value = Value >> Lowbit;  // Shift
+          // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+          if ((Highbit - Lowbit) != 31) {
+            Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+          }
+          if (IsLinked) {
+            Value |= MemNCmnGetSetFieldTN (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+          }
+          // For direct phy access, shift the bit back for compatibility reason.
+          if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
+            Value <<= Lowbit;
+          }
+        }
+      }
+    } else {
+      IDS_HDT_CONSOLE (MEM_UNDEF_BF, "\t\tUndefined BF enum: %x\n", FieldName);
+    }
+  } else {
+    ASSERT (FALSE);   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   NBRegTable[]  - Pointer to the bit field data structure
+ *
+ */
+
+VOID
+MemNInitNBRegTableTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   TSEFO NBRegTable[]
+  )
+{
+  UINT16 i;
+
+  // Allocate heap for NB register table
+  if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabTN)) {
+    return;     // escape if fails
+  }
+  NBRegTable = NBPtr->NBRegTable;
+
+  for (i = 0; i < BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  // ---------------------------------------------------------------------------
+  //
+  // FUNCTION 1
+  //
+  // ---------------------------------------------------------------------------
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 0, 0, BFDramRngRE0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 1, 1, BFDramRngWE0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 2, 0, BFDramRngDstNode0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C),  5,  4, BFNbPsSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C),  3,  3, BFMemPsSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C),  0,  0, BFDctCfgSel);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
+  // ---------------------------------------------------------------------------
+  //
+  // FUNCTION 2
+  //
+  // ---------------------------------------------------------------------------
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 23, 21, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 20, 18, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 17,  0, BFMrsAddress);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 16,  0, BFDramBankAddrReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 29, 24, BFMemClkDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFPendRefPaybackS3En);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 24, 24, BFStagRefEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 20, 20, BFDynPageCloseEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 31, BFDphyMemPsSelEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 28, 24, BFDcqBypassMax);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  7,  7, BFMemClkFreqVal);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  4,  0, BFMemClkFreq);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  23, 20, BFBwCapCmdThrottleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  14, 12, BFCmdThrottleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  11, 11, BFBwCapEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),   8,  8, BFODTSEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 31, BFPerRankTimingEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 29, 29, BFRefChCmdMgtDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 28, 28, BFFastSelfRefEntryDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 22, BFPrtlChPDEnhEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 21, 21, BFAggrPDEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 20, 20, BFBankSwap);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 17, 16, BFMemPhyPllPdMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  0,  0, BFIntLvRgnSwapEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  9,  3, BFIntLvRgnBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  17, 11, BFIntLvRgnLmtAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  26, 20, BFIntLvRgnSize);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114),  9,  9, BFDctSelIntLvAddrHi);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 27, 27, BFMctEccDisLatOptEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFLockDramCfg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 18, 18, BFCC6SaveEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31,  0, BFExtMctCfgLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 31,  0, BFExtMctCfgHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 27, 27, BFFlushWrOnS3StpGnt);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 26, 26, BFEnSplitMctDatBuffers);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 29, 24, BFTras);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 20, 16, BFTrp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 12,  8, BFTrcd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200),  4,  0, BFTcl);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 27, 24, BFTrtp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 21, 16, BFFourActWindow);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 11,  8, BFTrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204),  5,  0, BFTrc);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 26, 24, BFTrfc3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 18, 16, BFTrfc2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 10,  8, BFTrfc1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208),  2,  0, BFTrfc0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 17, 16, BFWrDqDqsEarly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 11,  8, BFTwtr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C),  4,  0, BFTcwl);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 31, 22, BFMaxLatency);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 18, 16, BFDataTxFifoWrDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210),  3,  0, BFRdPtrInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 19, 16, BFTwrwrSdSc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 11,  8, BFTwrwrSdDc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214),  3,  0, BFTwrwrDd);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 27, 24, BFTrdrdSdSc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 19, 16, BFTrdrdSdDc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 11,  8, BFTwrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218),  3,  0, BFTrdrdDd);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x21C), 20, 16, BFTrwtWB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x21C), 12,  8, BFTrwtTO);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x220), 12,  8, BFTmod);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x220),  3,  0, BFTmrd);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x224), 10,  8, BFTzqcs);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x224),  3,  0, BFTzqoper);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 31, 24, BFTstag3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 23, 16, BFTstag2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 15,  8, BFTstag1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228),  7,  0, BFTstag0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x22C), 4,  0, BFTwrDDR3);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x230), 31, 0, BFPhyRODTCSLow);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x234), 31, 0, BFPhyRODTCSHigh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x238), 31, 0, BFPhyWODTCSLow);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x23C), 31, 0, BFPhyWODTCSHigh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 14, 12, BFWrOdtOnDuration);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 10,  8, BFWrOdtTrnOnDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240),  6,  4, BFRdOdtOnDuration);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240),  3,  0, BFRdOdtTrnOnDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x244),  3,  0, BFPrtlChPDDynDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248),  31, 31, BFRxChMntClkEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248),  29, 24, BFAggrPDDelay);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248),  21, 16, BFPchgPDEnDelay);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248),  12,  8, BFTxpdll);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248),   3,  0, BFTxp);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C),   29,  24, BFTcksrx);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C),   21,  16, BFTcksre);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C),   13,   8, BFTckesr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C),    3,   0, BFTpd);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 12,  12, BFCmdSendInProg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 11,  11, BFSendCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 10,  10, BFTestStatus);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250),  9,   8, BFCmdTgt);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250),  7,   5, BFCmdType);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250),  4,   4, BFStopOnErr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250),  3,   3, BFResetAllErr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250),  2,   2, BFCmdTestEnable);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250),  13,   13, BFLfsrRollOver );
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254),  26,   24, BFTgtChipSelectA);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254),  23,   21, BFTgtBankA);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254),   9,    0, BFTgtAddressA);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258),  26,   24, BFTgtChipSelectB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258),  23,   21, BFTgtBankB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258),   9,    0, BFTgtAddressB);
+
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x260), 20,  0, BFCmdCount);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x264), 31,  25, BFErrDqNum);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x264), 24,  0, BFErrCnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x268), 17,  0, BFNibbleErrSts);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x26C), 17,  0, BFNibbleErr180Sts);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x270), 18,   0, BFDataPrbsSeed);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x274), 31,   0, BFDramDqMaskLow );
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x278), 31,   0, BFDramDqMaskHigh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 31, 31, BFSendActCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 30, 30, BFSendPchgCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 29, 22, BFCmdChipSelect);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 21, 19, BFCmdBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 17,  0, BFCmdAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 31,  0, BFDramCommand2 );
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x290), 26,  24, BFErrBeatNum);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x290), 20,   0, BFErrCmdNum);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x294), 31,  0, BFDQErrLow);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x298), 31,  0, BFDQErrHigh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E0), 30,  30, BFFastMstateDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E0), 28, 24, BFM1MemClkFreq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E0), 22, 20, BFMxMrsEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E8), 31, 16, BFMxMr1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E8), 15, 0, BFMxMr0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2EC), 15, 0, BFMxMr2);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2F0),  0,   0, BFEffArbDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x400), 11,  8, BFGmcTokenLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x400),  3,  0, BFMctTokenLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x404), 16,  0, BFGmcToDctControl1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x408),  0,  0, BFCpuElevPrioDis);
+
+  // ---------------------------------------------------------------------------
+  //
+  // DCT PHY REGISTERS
+  //
+  // ---------------------------------------------------------------------------
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10,  8, BFAddrCmdDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  6,  4, BFCsOdtDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  2,  0, BFCkeDrvStren);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 29, BFDisablePredriverCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  7,  6, BFFenceTrSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  2,  2, BFTrNibbleSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31,  0, BFDramPhyStatusReg);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 15, 12, BFCKETri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D,  9,  8, BFTxDLLWakeupTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D,  6,  4, BFTxCPUpdPeriod);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D,  3,  0, BFTxMaxDurDllNoLock);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x50, 31,  0, BFRstRcvFifo);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13,  8,  8, BFRxSsbMntClkEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 14, 14, BFProcOdtAdv);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13,  7,  0, BFPhy0x0D0F0F13);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F30,  4,  4, BFEccDLLPwrDnConf);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15,  0, BFPllRegWaitTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15,  0, BFPllLockTime);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15,  0, BFDataByteTxPreDriverCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15,  0, BFDataByteTxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15,  0, BFDataByteTxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15,  0, BFCmdAddr0TxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15,  0, BFCmdAddr0TxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15,  0, BFCmdAddr1TxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15,  0, BFCmdAddr1TxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15,  0, BFAddrTxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15,  0, BFAddrTxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15,  0, BFAddrTxPreDriverCal2Pad3);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15,  0, BFAddrTxPreDriverCal2Pad4);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15,  0, BFCmdAddr0TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15,  0, BFCmdAddr1TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15,  0, BFAddrTxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15,  0, BFClock0TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15,  0, BFClock1TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2202, 15,  0, BFClock2TxPreDriverCalPad0);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15,  0, BFAddrCmdTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10,  3,  0, BFDllNoLock);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D04E008,  8,  8, BFPStateToAccess);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE00A,  4,  4, BFSkewMemClk);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4003, 15,  0, BFChAM1FenceSave);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4004, 15,  0, BFChBM1FenceSave);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030,  4,  4, BFPhyClkConfig0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130,  4,  4, BFPhyClkConfig1);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000,  8,  8, BFLowPowerDrvStrengthEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE040,  3,  0, BFRate);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F,  8,  8, BFRx4thStgEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F,  4,  3, BFDataRxVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F,  2,  2, BFRxBypass3rd4thStg);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F,  4,  3, BFClkRxVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009,  3,  2, BFCsrComparator);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F,  4,  3, BFCmdRxVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F,  4,  3, BFAddrRxVioLvl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31,  9,  0, BFDataFence2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE019, 14,  0, BFFence2);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F30,  8,  8, BFBlockRxDqsLock);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F001C, 15,  0, BFDataByteDllPowerMgnByte0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F011C, 15,  0, BFDataByteDllPowerMgnByte1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F021C, 15,  0, BFDataByteDllPowerMgnByte2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F031C, 15,  0, BFDataByteDllPowerMgnByte3);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F041C, 15,  0, BFDataByteDllPowerMgnByte4);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F051C, 15,  0, BFDataByteDllPowerMgnByte5);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F061C, 15,  0, BFDataByteDllPowerMgnByte6);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F071C, 15,  0, BFDataByteDllPowerMgnByte7);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1C, 15,  0, BFDataByteDllPowerMgnByteAll);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE018,  8,  8, BFPhyPSMasterChannel);
+
+
+  // ---------------------------------------------------------------------------
+  //
+  // FUNCTION 4
+  //
+  // ---------------------------------------------------------------------------
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x128), 17, 12, BFCoreStateSaveDestNode);
+
+  // ---------------------------------------------------------------------------
+  //
+  // FUNCTION 5
+  //
+  // ---------------------------------------------------------------------------
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x84),  20, 16, BFDdrMaxRate);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x160),  18, 18, BFMemPstate0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x164),  18, 18, BFMemPstate1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x168),  18, 18, BFMemPstate2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x16C),  18, 18, BFMemPstate3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x160),  16, 10, BFNbVid0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x164),  16, 10, BFNbVid1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x168),  16, 10, BFNbVid2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x16C),  16, 10, BFNbVid3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x160),  21, 21, BFNbVid0Hi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x164),  21, 21, BFNbVid1Hi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x168),  21, 21, BFNbVid2Hi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x16C),  21, 21, BFNbVid3Hi);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 31,  0, BFNbPstateCtlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 31, 31, BFMemPstateDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 14, 14, BFSwNbPstateLoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170),  7,  6, BFNbPstateHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170),  4,  3, BFNbPstateLo);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170),  1,  0, BFNbPstateMaxVal);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 24, 24, BFCurMemPstate);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 20, 19, BFCurNbPstate);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174),  0,  0, BFNbPstateDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x188),  1,  0, BFNbOffsetTrim);
+
+  // ---------------------------------------------------------------------------
+  //
+  // LINK BITFIELD
+  //
+  // ---------------------------------------------------------------------------
+  LINK_TSEFO (NBRegTable, BFDctSelIntLvAddr, BFDctSelIntLvAddrHi);
+  LINK_TSEFO (NBRegTable, BFNbVid0, BFNbVid0Hi);
+  LINK_TSEFO (NBRegTable, BFNbVid1, BFNbVid1Hi);
+  LINK_TSEFO (NBRegTable, BFNbVid2, BFNbVid2Hi);
+  LINK_TSEFO (NBRegTable, BFNbVid3, BFNbVid3Hi);
+
+  // ---------------------------------------------------------------------------
+  //
+  // REGISTERS WITH MULTIPLE MEMORY PSTATE COPIES
+  //
+  // ---------------------------------------------------------------------------
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFODCControl);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDqsDrvStren);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDataDrvStren);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFClkDrvStren);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFAddrCmdDrvStren);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFCsOdtDrvStren);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFCkeDrvStren);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFAddrTmgControl);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDisablePredriverCal);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFProcOdtAdv);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDataRxVioLvl);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRx4thStgEn);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRxBypass3rd4thStg);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTras);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrp);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrcd);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTcl);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrtp);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFFourActWindow);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrrd);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrc);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFWrDqDqsEarly);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTwtr);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTcwl);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTwrDDR3);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFWrOdtOnDuration);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFWrOdtTrnOnDly);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRdOdtOnDuration);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRdOdtTrnOnDly);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFMxMr0);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFMxMr1);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFMxMr2);
+  // These Phy fence registers don't have mutiple memory Pstate copies
+  // But they need to be written again in M1 context
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDataFence2);
+  MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFFence2);
+
+  IDS_OPTION_HOOK (IDS_INIT_MEM_REG_TABLE, NBPtr, &NBPtr->MemPtr->StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
new file mode 100644
index 0000000000..2a48eb55cf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
@@ -0,0 +1,1498 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mns3tn.c
+ *
+ * TN memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mntn.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mnS3tn.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_MEM_NB_TN_MNS3TN_FILECODE
+#define DCT0_MEMPSTATE_MASK 0x10
+#define DCT1_MEMPSTATE_MASK 0x20
+#define DO_NOT_CARE 0
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstTN (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3SetDfltPhyRegTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3SetDynModeChangeTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3SetPhyStatusRegTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3DisableChannelTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3GetConPCIMaskTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+VOID
+STATIC
+MemNS3ChangeMemPStateContextAndFlowNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3GetCSRTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3SetCSRTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3SetPhyFenceTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+BOOLEAN
+MemS3ResumeConstructNBBlockTN (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = {
+  {MemNS3GetCSRTN, MemNS3SetCSRTN},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb},
+  {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPhyRegTN},
+  {MemNS3ChangeMemPStateContextAndFlowNb, MemNS3ChangeMemPStateContextAndFlowNb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeTN},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3DisableChannelTN},
+  {MemNS3SaveNBRegiserUnb, MemNS3RestoreNBRegiserUnb},
+  {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegTN},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb},
+  {MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb},
+  {MemNS3GetBitFieldNb, MemNS3SetPhyFenceTN},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ForceNBP0Unb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = {
+  {{14,3, 1}, DO_NOT_CARE, 0, 0},
+  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFF8E7},
+  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF0703},
+  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF0707},
+  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF87},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
+  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFE00},
+  {{0, 0, 0}, FUNC_2, 0x118, 0xFF73FFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0xAFFFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F},
+  {{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF},
+  {{0, 0, 0}, FUNC_2, 0xA4,  0x00F07900},
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorTN) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorTN,
+  PciSpecialCaseFuncTN
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = {
+   // DCT 0
+  {{7, 0, 1}, DCT0,   0x40,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x44,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x48,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x4C,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x50,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x54,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x58,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x5C,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x60,  0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x64,  0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x68,  0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x6C,  0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x78,  0x00020000, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x84,  0x00800003, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x88,  0x3F000000, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x8C,  0x00070000, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x90,  0x0BF70000, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0xA8,  0xBC730024, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x200, 0x3F1F1F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x204, 0x0F3F0F3F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x208, 0x07070707, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x20C, 0x00030F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT0,   SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT0,   SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT0,   SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT0,   SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x214, 0x000F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x218, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x21C, 0x001F1F00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x220, 0x00001F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x224, 0x0000070F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x228, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT0,   0x22C, 0x0000001F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x230, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x234, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x238, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x23C, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x240, 0x000077FF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT0,   0x244, 0x0000000F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x248, 0xBF3F1F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x24C, 0x3F3F3F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x2E0, 0x5F700000, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x2E8, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x2EC, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT0,   0x2F0, 0x00000001, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x400, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x404, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT0,   0x408, 0x00000003, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x420, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+
+  // DCT 1
+  {{7, 0, 1}, DCT1,   0x40,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x44,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x48,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x4C,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x50,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x54,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x58,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x5C,  0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x60,  0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x64,  0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x68,  0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x6C,  0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x78,  0x00020000, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x80,  0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x84,  0x00800003, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x88,  0x3F000000, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x8C,  0x00070000, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x90,  0x0BF70000, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0xA8,  0xBC730024, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x200, 0x3F1F1F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x204, 0x0F3F0F3F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x208, 0x07070707, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x20C, 0x00030F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT1,   SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT1,   SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT1,   SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK},
+  {{2, 0, 1}, DCT1,   SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x214, 0x000F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x218, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x21C, 0x001F1F00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x220, 0x00001F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x224, 0x0000070F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x228, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT1,   0x22C, 0x0000001F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x230, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x234, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x238, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x23C, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x240, 0x000077FF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT1,   0x244, 0x0000000F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x248, 0xBF3F1F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x24C, 0x3F3F3F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x2E0, 0x5F700000, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x2E8, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x2EC, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT1,   0x2F0, 0x00000001, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x400, 0x00000F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x404, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT1,   0x408, 0x00000003, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x420, 0x00000F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+
+  // Phy Initialization
+  // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h.
+  {{1, 2, 1}, DCT0,   BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  // 2. Force the phy to M0 with the following sequence:
+  // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h.
+  {{3, 3, 1}, DCT0,   BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{3, 3, 1}, DCT1,   BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h.
+  {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B),  0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B),  0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  // C. Program D18F2x9C_x0D0F_E018_dct[0][PhyPSMasterChannel] = 0.
+  {{3, 3, 1}, DCT0,  BFPhyPSMasterChannel, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  // D. Program D18F2x9C_x0000_000B_dct[0] = 40000000h.
+  // E. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h
+  {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B),  0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B),  0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+
+  // 3. Phy voltage related
+  {{1, 1, 1}, DCT0,   BFDataRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFClkRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFCmpVioLvl, 0x0000C000, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFCmdRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFCsrComparator, 0x0000000C, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFAddrRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFDataRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFClkRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFCmpVioLvl, 0x0000C000, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFCmdRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFAddrRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK},
+
+  // 4. Frequency Change
+  // Check if a channel needs to be disabled
+  {{1, 1, 1}, DCT0,   BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{6, 3, 1}, DCT0,   0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{6, 3, 1}, DCT1,   0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhyClkConfig0, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhyClkConfig1, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFPhyClkConfig0, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFPhyClkConfig1, 0, DCT1_MASK, ANY_DIMM_MASK},
+
+  {{7, 0, 1}, DCT0,   0x94,  0x9FF9CC1F, DCT0_MASK, ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x94,  0x9FF9CC1F, DCT1_MASK, ANY_DIMM_MASK},
+
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFProcOdtAdv, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFProcOdtAdv, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFSkewMemClk, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFSkewMemClk, 0, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Enable MemClk
+  {{10, 0, 1}, DCT0,   0x94, 0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{10, 0, 1}, DCT1,   0x94, 0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK},
+
+  // DCT 0
+  // 5. Phy Fence
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataFence2, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFFence2, 0x00007C1F, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x70777777, DCT0_MASK, ANY_DIMM_MASK},
+  // 6. Phy Compensation Init
+  {{3, 3, 1}, DCT0,   BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFDataByteTxPreDriverCal, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad3, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad4, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFCmdAddr0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFCmdAddr1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFAddrTxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFClock0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFClock1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT0,   BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+
+  // DCT 1
+  // 5. Phy Fence
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataFence2, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFFence2, 0x00007C1F, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),  0x70777777, DCT1_MASK, ANY_DIMM_MASK},
+  // 6. Phy Compensation Init
+  {{1, 2, 1}, DCT1,   BFDataByteTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFDataByteTxPreDriverCal, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFAddrTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFAddrTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFAddrTxPreDriverCal2Pad3, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFAddrTxPreDriverCal2Pad4, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFCmdAddr0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFCmdAddr1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFAddrTxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFClock0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFClock1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{8, 2, 1}, DCT1,   BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK},
+
+  {{1, 1, 1}, DCT0,   BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+
+  // Program MemPstate 1 registers
+  // Switch to MemPstate context 1
+  {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFRate, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFRate, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFProcOdtAdv, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFProcOdtAdv, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFDataRxVioLvl, 0x00000018, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFDataRxVioLvl, 0x00000018, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x200, 0x3F1F1F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x204, 0x0F3F0F3F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x208, 0x07070707, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x20C, 0x00030F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x214, 0x000F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x218, 0x0F0F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x21C, 0x001F1F00, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT0,   0x22C, 0x0000001F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x240, 0x000077FF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x248, 0xBF3F1F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT0,   0x2E8, 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT0,   0x2EC, 0x0000FFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x200, 0x3F1F1F1F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x204, 0x0F3F0F3F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x208, 0x07070707, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x20C, 0x00030F1F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x214, 0x000F0F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x218, 0x0F0F0F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x21C, 0x001F1F00, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 1, 1}, DCT1,   0x22C, 0x0000001F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x240, 0x000077FF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x248, 0xBF3F1F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 0, 1}, DCT1,   0x2E8, 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  {{7, 2, 1}, DCT1,   0x2EC, 0x0000FFFF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK},
+  // Compute Phy fence for MemPstate 1
+  // DCT 0
+  {{12, 2, 1}, DCT1,  BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  // DCT 1
+  {{12, 2, 1}, DCT1,  BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+  {{1, 1, 1}, DCT0,   BFDisablePredriverCal, 0, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  // Switch back to MemPstate context 0
+  {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+  // Set Fence back to Fence of M0 to prepare for fine delay restore for M0
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataFence2, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFFence2, 0x00007C1F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataFence2, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFFence2, 0x00007C1F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = {
+  0,
+  (sizeof (S3CPciPreSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPreSelfDescriptorTN,
+  PciSpecialCaseFuncTN
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = {
+  // DCT0
+  {{12, 2, 1}, DCT1,  BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFRx4thStgEn, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFRxBypass3rd4thStg, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x03FF03FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x03FF03FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x03FF03FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x03FF03FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x03FF03FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x03FF03FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x03FF03FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x03FF03FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x03FF03FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x03FF03FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x03FF03FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x03FF03FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x03FF03FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x03FF03FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x03FF03FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x03FF03FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0xFFFFFFFF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0xFFFFFFFF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3E3E3E3E, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3E3E3E3E, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x037F037F, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhy0x0D0F0F13, 0x00000083, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFRxSsbMntClkEn, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFLowPowerDrvStrengthEn, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFEnRxPadStandby, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK},
+
+    // DCT1
+  {{12, 2, 1}, DCT1,  BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFRx4thStgEn, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFRxBypass3rd4thStg, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x03FF03FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x03FF03FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x03FF03FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x03FF03FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x03FF03FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x03FF03FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x03FF03FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x03FF03FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x03FF03FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x03FF03FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x03FF03FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x03FF03FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x03FF03FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x03FF03FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x03FF03FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x03FF03FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0xFFFFFFFF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0xFFFFFFFF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3E3E3E3E, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3E3E3E3E, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x037F037F, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFPhy0x0D0F0F13, 0x00000083, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFRxSsbMntClkEn, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFLowPowerDrvStrengthEn, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFEnRxPadStandby, 0, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte0, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte1, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte2, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte3, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte4, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte5, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte6, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte7, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK},
+
+  {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+  // DCT0
+  {{12, 2, 1}, DCT1,  BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFRx4thStgEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFRxBypass3rd4thStg, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x037F037F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhy0x0D0F0F13, 0x00000083, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFRxSsbMntClkEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFLowPowerDrvStrengthEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFEnRxPadStandby, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+    // DCT1
+  {{12, 2, 1}, DCT1,  BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFRx4thStgEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFRxBypass3rd4thStg, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x037F037F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFPhy0x0D0F0F13, 0x00000083, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFRxSsbMntClkEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFLowPowerDrvStrengthEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFEnRxPadStandby, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte0, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte1, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte2, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte3, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte4, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte5, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte6, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT1,   BFDataByteDllPowerMgnByte7, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+  {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK},
+
+  {{1, 1, 1}, DCT0,   BFAddrCmdTri, 0x0000000A1, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFDisDllShutdownSR, 0, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFAddrCmdTri, 0x0000000A1, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT1,   BFDisDllShutdownSR, 0, DCT1_MASK, ANY_DIMM_MASK},
+
+  {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK},
+
+  {{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorTN,
+  PciSpecialCaseFuncTN
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F0000},
+  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001F, 0x0044601080000600}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorTN) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorTN,
+  NULL
+};
+
+VOID *MemS3RegListTN[] = {
+  (VOID *)&S3PciPreSelfRefTN,
+  NULL,
+  (VOID *)&S3CPciPreSelfRefTN,
+  (VOID *)&S3CPciPostSelfRefTN,
+  (VOID *)&S3MSRPreSelfRefTN,
+  NULL,
+  NULL,
+  NULL
+};
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *      @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemS3ResumeConstructNBBlockTN (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_TN;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_TN;
+  NBPtr->MemPstate = MEMORY_PSTATE0;
+  NBPtr->MemPstateStage = 0;
+  NBPtr->NbPsCtlReg = 0;
+
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  for (i = 0; i < NumberOfHooks; i++) {
+    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedTN;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskTN;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeUNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrTN;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstTN;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0;
+  NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNS3DctCfgSelectUnb;
+
+  MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0);
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0);
+
+  if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) != 1) {
+    NBPtr->MemPstateStage = MEMORY_PSTATE_S3_STAGE;
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0);
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for TN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListTN[PCI_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_TN + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListTN[CPCI_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_TN + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListTN[MSR_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_TN + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListTN[CMSR_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_TN + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      AGESA_STATUS
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstTN (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListTN) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListTN[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListTN[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device register list error
+  return AGESA_FATAL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function that set PllLockTime or PhyPSMasterChannel or disable auto compensation.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetDfltPhyRegTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT16 RegValue;
+  BIT_FIELD_NAME BitField;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    BitField = (BIT_FIELD_NAME) Address.Address.Register;
+    RegValue = 0;
+
+    if (BitField == BFPllLockTime) {
+      RegValue = 0x190;
+    } else if (BitField == BFPhyPSMasterChannel) {
+    } else if (BitField == BFDisablePredriverCal) {
+      RegValue = 3;
+    } else {
+      ASSERT (FALSE);
+    }
+    MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets bit 31 [DynModeChange] of F2x9C_xB
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetDynModeChangeTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 RegValue;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    if ((Address.Address.Register & 0x400) == 0) {
+      RegValue = 0x40000000;
+      MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+    }
+    RegValue = 0x80000000;
+    MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets F2x9C_xB to 0x80800000
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetPhyStatusRegTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 RegValue;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    RegValue = 0x80800000;
+    MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function does the channel disable sequence
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3DisableChannelTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  UINT32 RegValue;
+  UINT8 Die;
+
+  // See which Node should be accessed
+  Die = (UINT8) (Address.Address.Device - 24);
+
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+    NBPtr = S3NBPtr[Die].NBPtr;
+
+    // Function field contains the DCT number
+    NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
+    RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri);
+    // if CKETri is 0b1111, this channel is disabled
+    if (RegValue == 0xF) {
+      //Wait for 24 MEMCLKs, which is 60ns under 400MHz
+      MemFS3Wait10ns (6, NBPtr->MemPtr);
+      MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+      MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+      if (NBPtr->Dct == 0) {
+        MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0x100);
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function changes memory Pstate context
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNS3ChangeMemPStateContextAndFlowNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  UINT8 Die;
+
+  // See which Node should be accessed
+  Die = (UINT8) (Address.Address.Device - 24);
+
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+    NBPtr = S3NBPtr[Die].NBPtr;
+    if (NBPtr->MemPstate == MEMORY_PSTATE0) {
+      // If MemoryPstate is not disabled, switch to MemPState 1 context, and reprocess the register list
+      MemNChangeMemPStateContextNb (NBPtr, 1);
+      *(UINT32 *) Value = RESTART_FROM_BEGINNING_LIST;
+    } else {
+      // Switch back to MemPstate0 Context
+      MemNChangeMemPStateContextNb (NBPtr, 0);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the conditional PCI device mask
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *      @return         none
+ */
+VOID
+STATIC
+MemNS3GetConPCIMaskTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  BIT_FIELD_NAME bitfield;
+  UINT32 RegVal;
+  UINT8 DCT;
+  UINT8 DimmMask;
+  UINT8 BadDimmMask;
+  UINT8 NbPsCapMsk;
+  UINT8 MemPstateMsk;
+  UINT8 CsPerDelay;
+
+  NbPsCapMsk = 0;
+  MemPstateMsk = 0;
+  DimmMask = 0;
+  BadDimmMask = 0;
+  CsPerDelay = 1;
+
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
+      if (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn) == 0) {
+        CsPerDelay = 2;
+      }
+      for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
+        RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
+        if (RegVal & 0x1) {
+          DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT));
+        } else if (RegVal & 0x4) {
+          BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT));
+        }
+      }
+    }
+  }
+  // Check if the system is capable of doing NB Pstate change
+  if (MemNGetBitFieldNb (NBPtr, BFNbPstateDis) == 0) {
+    NbPsCapMsk = DCT0_NBPSTATE_SUPPORT_MASK;
+  }
+  if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) == 0) {
+    MemPstateMsk = DCT0_MEMPSTATE_MASK;
+  }
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  // Set channel mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    if (DimmMask & (0x55 << DCT)) {
+      // Set mask before exit self refresh
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT;
+      // Set mask after exit self refresh
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT;
+    } else if (BadDimmMask & (0x55 << DCT)) {
+      // Need to save function 2 registers for bad dimm
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
+    }
+  }
+
+  // Set dimm mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function read the value of CSR register.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3GetCSRTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8 TempValue;
+  UINT8 Dct;
+  UINT32 ExtendOffset;
+  UINT32 TempFunc;
+
+  ExtendOffset = Address.Address.Register;
+  TempFunc = Address.Address.Function;
+
+  // Switch Dct
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  Dct = 0;
+  if (ExtendOffset & 0x400) {
+    Dct = 1;
+  }
+  LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  TempValue = (TempValue & 0xFE) | Dct;
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  Address.Address.Function = TempFunc;
+
+  Address.Address.Register = 0x98;
+  ExtendOffset &= 0x3FF;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
+  IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr);
+  Address.Address.Register = 0x9C;
+  LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function write to a CSR register
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetCSRTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8 TempValue;
+  UINT8 Dct;
+  UINT32 ExtendOffset;
+  UINT32 ValueWrite;
+  UINT32 TempFunc;
+
+  ExtendOffset = Address.Address.Register;
+
+  TempFunc = Address.Address.Function;
+  // Switch Dct
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  Dct = 0;
+  if (ExtendOffset & 0x400) {
+    Dct = 1;
+  }
+  LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  TempValue = (TempValue & 0xFE) | Dct;
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+
+  Address.Address.Function = TempFunc;
+  Address.Address.Register = 0x9C;
+
+  ExtendOffset &= 0x3FF;
+  ExtendOffset |= 0x40000000;
+  switch (AccessWidth) {
+  case AccessS3SaveWidth8:
+    ValueWrite = *(UINT8 *) Value;
+    break;
+  case AccessS3SaveWidth16:
+    ValueWrite = *(UINT16 *) Value;
+    break;
+  case AccessS3SaveWidth32:
+    ValueWrite = *(UINT32 *) Value;
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr);
+  Address.Address.Register = 0x98;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
+  IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function that set PllLockTime or PhyPSMasterChannel or disable auto compensation.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetPhyFenceTN (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT16 FenceValue;
+  UINT16 Fence2Data;
+  UINT16 Fence2Reg;
+  BIT_FIELD_NAME BitField;
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+
+  BitField = (BIT_FIELD_NAME) Address.Address.Register;
+  FenceValue = *(UINT16 *) Value;
+  // See which Node should be accessed
+
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+    NBPtr = S3NBPtr[0].NBPtr;
+
+    // Do nothing if currently in memory pstate 0 context
+    if (NBPtr->MemPstate == MEMORY_PSTATE0) {
+      return;
+    }
+
+    if (BitField == BFChAM1FenceSave) {
+      MemNSwitchDCTNb (NBPtr, 0);
+    } else {
+      MemNSwitchDCTNb (NBPtr, 1);
+    }
+    MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 16, BFPhyFence);
+    MemNSetBitFieldNb (NBPtr, BFPhyFence, FenceValue);
+
+    // Program Fence 2 for MState 1
+    Fence2Data = 0;
+    if ((FenceValue & 0x1F) < 16) {
+      Fence2Data |= (FenceValue & 0x1F) | 0x10;
+    }
+    if (((FenceValue >> 5) & 0x1F) < 16) {
+      Fence2Data |= (((FenceValue >> 5) & 0x1F) | 0x10) << 10;
+    }
+    if (((FenceValue >> 10) & 0x1F) < 16) {
+      Fence2Data |= (((FenceValue >> 10) & 0x1F) | 0x10) << 5;
+    }
+    MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data);
+
+    // Program another Fence 2 register for Mstate 1
+    Fence2Reg = (UINT16) MemNGetBitFieldNb (NBPtr, BFFence2);
+    Fence2Reg = (Fence2Reg &~(UINT16) ((0x1F << 10) | 0x1F)) | (Fence2Data & 0x1F) | (((Fence2Data >> 5) & 0x1F) << 10);
+    MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
new file mode 100644
index 0000000000..63f255bc0a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -0,0 +1,618 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mntn.c
+ *
+ * Common Northbridge  functions for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mntn.h"
+#include "mu.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_MEM_NB_TN_MNTN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNRegAccessFenceTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+/**
+ * Array for frequency change related parameters.
+ */
+CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamTN = {0x0190, 0, 0, 0, 0, 0, 0, 0};
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @return     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 SpdSocketIndex;
+  UINT8 SpdChannelIndex;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem->SocketId, &(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem->LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = MemPtr->DiesPerSystem;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_TN * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_TN * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + sizeof (CH_TIMING_STRUCT))
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_TN;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_TN * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_TN;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_TN * sizeof (CH_DEF_STRUCT);
+    MCTPtr->DctData[Dct].TimingsMemPs1 = (CH_TIMING_STRUCT *) AllocHeapParams.BufferPtr;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_TN * sizeof (CH_TIMING_STRUCT);
+  }
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
+    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
+  }
+
+  MemNInitNBDataTN (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  FeatPtr->InitHwRxEn (NBPtr);
+  FeatPtr->excel221 (NBPtr);
+
+  NBPtr->FeatPtr = FeatPtr;
+
+  //
+  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
+  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
+  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
+  // dimm types(QR or not) are known. This is done in the Technology block constructor.
+  //
+  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
+  // This will facilitate modifications due to some processors that might
+  // map the DCT-CHANNEL differently.
+  //
+  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
+  //
+  // Traverse the Dct/Channel structures
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_TN; Channel++) {
+      //
+      // Calculate the number of Dimms on this channel using the
+      //   die/dct/channel to Socket/channel conversion.
+      //
+      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            NBPtr->MCTPtr->SocketId,
+                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
+                                            &MemPtr->StdHeader);
+      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
+    }
+  }
+
+  //
+  // Initialize Dct and DctCfgSel bit
+  //
+  MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0);
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) == 1) {
+    // MemPstate is disabled
+    NBPtr->MemPstateStage = 0;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_TN;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_TN;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_TN;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_256B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR667_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0x1FF;
+  NBPtr->DefDctSelIntLvAddr = 4;
+  NBPtr->NbFreqChgState = 0;
+  NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamTN;
+  NBPtr->MaxRxEnSeedTotal = 0x1FF;
+  NBPtr->MinRxEnSeedGross = 0;
+  NBPtr->CsRegMsk = 0x7FF8FFE0;
+  NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED;
+  NBPtr->MemPstate = MEMORY_PSTATE0;
+  NBPtr->MemPstateStage = MEMORY_PSTATE_1ST_STAGE;
+  NBPtr->CsPerChannel = MAX_CS_PER_CHANNEL_TN;
+  NBPtr->CsPerDelay = 1;
+  NBPtr->TotalMaxVrefRange = 0x20;
+  NBPtr->TotalRdDQSDlyRange = 0x40;
+  NBPtr->PhaseLaneMask = 0x3FFFF;
+  NBPtr->MaxDiamondStep = 3;
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+  MemNInitNBDataNb (NBPtr);
+
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyTN;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsTN;
+  NBPtr->InitializeMCT = MemNInitializeMctTN;
+  NBPtr->FinalizeMCT = MemNFinalizeMctTN;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdUnb;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternTN;
+  NBPtr->ReadPattern = MemNReadPatternTN;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->StitchMemory = MemNStitchMemoryNb;
+  NBPtr->AutoConfig = MemNAutoConfigTN;
+  NBPtr->PlatformSpec = MemNPlatformSpecUnb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->DisableDCT = MemNDisableDCTUnb;
+  NBPtr->StartupDCT = MemNStartupDCTUnb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyUnb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyUnb;
+  NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyUnb;
+  NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapUnb;
+  NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersTN;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb;
+  NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitTN;
+  NBPtr->SyncAddrMapToAllNodes = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingTN;
+  NBPtr->AfterDqsTraining = MemNAfterDQSTrainingTN;
+  NBPtr->OtherTiming = MemNOtherTimingTN;
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchTN;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN;
+  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->TrainingFlow = MemNTrainingFlowUnb;
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
+  NBPtr->BrdcstSet = MemNBrdcstSetNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitTN;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyUnb;
+  NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompTN;
+  NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitTblDrvNb;
+  NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustTN;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsUnb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeTN;
+  NBPtr->GetUmaSize = MemNGetUmaSizeTN;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdUnb;
+  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
+  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
+  NBPtr->MemNGetDramTerm = MemNGetDramTermTblDrvNb;
+  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermTblDrvNb;
+  NBPtr->MemNGetMR0CL = MemNGetMR0CLTblDrvNb;
+  NBPtr->MemNGetMR0WR = MemNGetMR0WRTblDrvNb;
+  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
+  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLUnb;
+  NBPtr->AllocateC6Storage = MemNAllocateC6StorageTN;
+  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecTN;
+  NBPtr->MemNGetMemoryWidth = MemNGetMemoryWidthUnb;
+
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
+  NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
+  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
+  NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE;
+  NBPtr->IsSupported[UnifiedNbFence] = TRUE;
+  NBPtr->IsSupported[CheckODTControls] = TRUE;
+  NBPtr->IsSupported[CheckDramTerm] = TRUE;
+  NBPtr->IsSupported[CheckDramTermDyn] = TRUE;
+  NBPtr->IsSupported[CheckQoff] = TRUE;
+  NBPtr->IsSupported[CheckDrvImpCtrl] = TRUE;
+  NBPtr->IsSupported[CheckSetSameDctODTsEn] = TRUE;
+  NBPtr->IsSupported[WLSeedAdjust] = TRUE;
+  NBPtr->IsSupported[WLNegativeDelay] = TRUE;
+  NBPtr->IsSupported[TwoStageDramInit] = TRUE;
+  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
+  NBPtr->IsSupported[ProgramCsrComparator] = TRUE;
+  NBPtr->IsSupported[AdjustTrp] = TRUE; // erratum 638
+  NBPtr->IsSupported[ForcePhyToM0] = TRUE;
+
+  NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] = MemNExitPhyAssistedTrainingTN;
+  NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNDctCfgSelectUnb;
+  NBPtr->FamilySpecificHook[AfterSaveRestore] = MemNAfterSaveRestoreUnb;
+  NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedTN;
+  NBPtr->FamilySpecificHook[OverrideWLSeed] = MemNOverrideWLSeedTN;
+  NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] = MemNCalcWrDqDqsEarlyUnb;
+  NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] = MemNAdjustRdDqsDlyOffsetUnb;
+  NBPtr->FamilySpecificHook[GetDdrMaxRate] = MemNGetMaxDdrRateUnb;
+  NBPtr->FamilySpecificHook[SetSkewMemClk] = MemNSetSkewMemClkUnb;
+  NBPtr->FamilySpecificHook[AfterMemClkFreqVal] = MemNAdjustPllLockTimeTN;
+  NBPtr->FamilySpecificHook[AdjustCSIntLvLowAddr] = MemNCSIntLvLowAddrAdjTN;
+  NBPtr->FamilySpecificHook[ReleaseNbPstate] = MemNReleaseNbPstateTN;
+  NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] = MemNInitializeRxEnSeedlessTrainingUnb;
+  NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] = MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb;
+  NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] = MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb;
+  NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] = MemNInitialzeRxEnSeedlessByteLaneErrorUnb;
+  NBPtr->FamilySpecificHook[MemPstateStageChange] = MemNMemPstateStageChangeTN;
+  NBPtr->FamilySpecificHook[ProgramFence2RxDll] = MemNProgramFence2RxDllTN;
+  NBPtr->FamilySpecificHook[RdDqsDlyRestartChk] = MemNRdDqsDlyRestartChkTN;
+  NBPtr->FamilySpecificHook[BeforeWrDatTrn] = MemNHookBfWrDatTrnTN;
+  NBPtr->FamilySpecificHook[RegAccessFence] = MemNRegAccessFenceTN;
+  NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] = MemNAdjustWrDqsBeforeSeedScalingUnb;
+  NBPtr->FamilySpecificHook[WLMR1] = MemNWLMR1TN;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+VOID
+MemNInitDefaultsTN (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
+      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
+    }
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
+  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
+  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
+
+  // Vref
+  RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature;
+
+  //Training Mode
+  RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates DQS training for TN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+memNEnableTrainSequenceTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN Retval;
+  Retval = TRUE;
+  if (!MemNIsIdSupportedTN (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
+    Retval = FALSE;
+  }
+  return Retval;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function makes sure that previous phy register writes are done.
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+STATIC
+MemNRegAccessFenceTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  // If subsequent writes to this array are scheduled, such as when writing several byte lanes during dram
+  // training, then it is recommended to issue a dummy register read to ensure the last write.
+  NBPtr->GetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (0, 0));
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h
new file mode 100644
index 0000000000..4d4316bfdb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h
@@ -0,0 +1,341 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mntn.h
+ *
+ * Northbridge TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNTN_H_
+#define _MNTN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_NODE_TN          2
+#define MAX_CHANNELS_PER_DCT_TN       1
+#define MAX_NODES_SUPPORTED_TN        1
+#define MAX_CS_PER_CHANNEL_TN         4
+
+#define DEFAULT_WR_ODT_TN 6
+#define DEFAULT_RD_ODT_TN 6
+#define DEFAULT_RD_ODT_TRNONDLY_TN 0
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemConstructNBBlockTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitNBDataTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDefaultsTN (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNInitializeMctTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAutoConfigTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNOtherTimingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitPhyCompTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWritePatternTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNInitNBRegTableTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   TSEFO NBRegTable[]
+  );
+
+BOOLEAN
+MemNIsIdSupportedTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+UINT32
+MemNCmnGetSetFieldTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+BOOLEAN
+memNEnableTrainSequenceTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNTechBlockSwitchTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNAfterDQSTrainingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNCapSpeedBatteryLifeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNGetMaxLatParamsTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  );
+
+VOID
+MemNSetMaxLatencyTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  );
+
+BOOLEAN
+MemNExitPhyAssistedTrainingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNOverrideRcvEnSeedTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *SeedPtr
+  );
+
+VOID
+MemNBeforeDQSTrainingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramNbPstateDependentRegistersTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAdjustPllLockTimeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *PllLockTime
+  );
+
+BOOLEAN
+MemNOverrideWLSeedTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *SeedPtr
+  );
+
+BOOLEAN
+MemNFinalizeMctTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNHtMemMapInitTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNGetUmaSizeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNBeforeDramInitTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNCSIntLvLowAddrAdjTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *LowBit
+  );
+
+VOID
+MemNAllocateC6StorageTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPFenceAdjustTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   INT16 *Value16
+  );
+
+BOOLEAN
+MemNReleaseNbPstateTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNMemPstateStageChangeTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNProgramFence2RxDllTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Fence2Data
+  );
+
+VOID
+MemNAdjustNBPstateVolTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNRdDqsDlyRestartChkTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Center
+  );
+
+BOOLEAN
+MemNHookBfWrDatTrnTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *ChipSel
+  );
+
+VOID
+MemNSetOtherTimingTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPowerDownCtlTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNBeforePlatformSpecTN (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNWLMR1TN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Value
+  );
+#endif  /* _MNTN_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
new file mode 100644
index 0000000000..e203fd0388
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
@@ -0,0 +1,530 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mn.c
+ *
+ * Common Northbridge functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MN_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT32 i;
+  UINT8 *BytePtr;
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  BytePtr = (UINT8 *) (NBPtr->DctCache);
+  for (i = 0; i < sizeof (NBPtr->DctCache); i++) {
+    *BytePtr++ = 0;
+  }
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  for (i = 0; i < NumberOfHooks; i++) {
+    NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb;
+  }
+
+  for (i = 0; i < NBPtr->DctCount; i++) {
+    NBPtr->PSBlock[i].MemPGetPass1Seeds = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
+  }
+
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Get System address of Chipselect RJ 16 bits (Addr[47:16])
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Receiver - Chipselect to be targeted [0-7]
+ *     @param[out]      AddrPtr -  Pointer to System Address [47:16]
+ *
+ *     @return      TRUE  - Address is valid
+ *     @return      FALSE  - Address is not valid
+ */
+
+BOOLEAN
+MemNGetMCTSysAddrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver,
+     OUT   UINT32 *AddrPtr
+  )
+{
+  S_UINT64 SMsr;
+  UINT32 CSBase;
+  UINT32 HoleBase;
+  UINT32 DctSelBaseAddr;
+  UINT32 BottomUma;
+  DIE_STRUCT *MCTPtr;
+  MEM_DATA_STRUCT *MemPtr;
+
+  MCTPtr = NBPtr->MCTPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  ASSERT (Receiver < 8);
+
+  CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
+  if (CSBase & 1) {
+    ASSERT ((CSBase & 0xE0) == 0);   // Should not enable CS interleaving before DQS training.
+
+    // Scale base address from [39:8] to [47:16]
+    CSBase >>= 8;
+
+    HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF;
+
+    if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) {
+      DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16);
+      if (DctSelBaseAddr > HoleBase) {
+        DctSelBaseAddr -= _4GB_RJ16 - HoleBase;
+      }
+      CSBase += DctSelBaseAddr;
+    } else {
+      CSBase += MCTPtr->NodeSysBase;
+    }
+
+    if (CSBase >= HoleBase) {
+      CSBase += _4GB_RJ16 - HoleBase;
+    }
+
+    CSBase += (UINT32)1 << (21 - 16);  // Add 2MB offset to avoid compat area.
+    if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) {
+      CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0;
+    }
+
+    if (MCTPtr->Status[SbHWHole]) {
+      if (MCTPtr->Status[SbSWNodeHole]) {
+        LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+        if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) {
+          return FALSE;
+        }
+      }
+    }
+
+    BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16;
+    if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) {
+      return FALSE;
+    }
+    *AddrPtr = CSBase;
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function determines if a Rank is enabled.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]    Receiver - Receiver to check
+ *     @return - FALSE
+ *
+ */
+
+BOOLEAN
+MemNRankEnabledNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT32 CSBase;
+  CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
+  if (CSBase & 1) {
+    return  TRUE;
+  } else {
+    return  FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function sets the EccSymbolSize bit depending upon configurations
+ *     and system override.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSetEccSymbolSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16 X4DimmsOnly;
+  BOOLEAN Size;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  // Determine if this node has only x4 DRAM parts
+  X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present);
+  //
+  // Check if EccSymbolSize BKDG value is overridden
+  //
+  if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) {
+    Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE;
+  } else {
+    if (X4DimmsOnly && MCTPtr->GangedMode) {
+      Size = FALSE;
+    } else {
+      Size = TRUE;
+    }
+  }
+  IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader));
+  MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the training control flow
+ *      The DDR3 mode bit must be set prior to calling this function
+ *
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+BOOLEAN
+MemNTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
+    memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
+  } else {
+    memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr);
+  }
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function flushes the  training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNFlushPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  // Due to speculative execution during MemUReadCachelines, we must
+  //  flush one more cache line than we read.
+  MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function compares test pattern with data in buffer and
+ *     return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]   *NBPtr    - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  - Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @return  PASS - Bitmap of results of comparison
+ */
+
+UINT16
+MemNCompareTestPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  UINT16 i;
+  UINT16 Pass;
+  UINT8 ColumnCount;
+  UINT8 FailingBitMask[8];
+
+  ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
+
+  ColumnCount = NBPtr->ChannelPtr->ColumnCount;
+  Pass = 0xFFFF;
+  //
+  // Clear Failing Bit Mask
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    FailingBitMask[i] = 0;
+  }
+
+  if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
+    i = 8;   // DCT 1 in ganged mode
+  } else {
+    i = 0;
+  }
+
+  for (; i < ByteCount; i++) {
+    if (Buffer[i] != Pattern[i]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (i % 8));    // clear bit n
+      FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]);
+    }
+
+    if (NBPtr->Ganged && ((i & 7) == 7)) {
+      i += 8;     // if ganged, skip over other Channel's Data
+    }
+  }
+  //
+  // Accumulate Failing bit data
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
+      FailingBitMask[i];
+  }
+
+  return Pass;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function compares test pattern with data in buffer and
+ *     return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  - Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @retval  PASS - Bitmap of results of comparison
+ * ----------------------------------------------------------------------------
+ */
+UINT16
+MemNInsDlyCompareTestPatternNb (
+  IN       MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  UINT16 i;
+  UINT16 Pass;
+  UINT16 BeatOffset;
+  UINT16 BeatCnt;
+  UINT8 ColumnCount;
+  UINT8 FailingBitMask[8];
+
+  ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
+
+  ColumnCount = NBPtr->ChannelPtr->ColumnCount;
+  Pass = 0xFFFF;
+  //
+  // Clear Failing Bit Mask
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    FailingBitMask[i] = 0;
+  }
+
+  if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
+    i = 8;   // DCT 1 in ganged mode
+  } else {
+    i = 0;
+  }
+
+  if (NBPtr->Ganged) {
+    BeatOffset = 16;
+  } else {
+    BeatOffset = 8;
+  }
+
+  BeatCnt = 0;
+  for (; i < ByteCount; i++) {
+
+    if (Buffer[i] != Pattern[i + BeatOffset]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (i % 8));    // clear bit n
+      FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]);
+    }
+
+    if ((i & 7) == 7) {
+      if (NBPtr->Ganged) {
+        i += 8;     // if ganged, skip over other Channel's Data
+      }
+      BeatCnt++;
+    }
+
+    if ((BeatCnt & 3) == 3) {
+      // Skip last data beat of a 4-beat burst.
+      BeatCnt++;
+      i = i + BeatOffset;
+    }
+  }
+  //
+  // Accumulate Failing bit data
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
+      FailingBitMask[i];
+  }
+
+  return Pass;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the training control flow for UNB
+ *      The DDR3 mode bit must be set prior to calling this function
+ *
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+BOOLEAN
+MemNTrainingFlowUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
+  return TRUE;
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c
new file mode 100644
index 0000000000..97ac25fa0b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c
@@ -0,0 +1,1493 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnS3.c
+ *
+ * Common Northbridge S3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_MEM_NB_MNS3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNS3GetSetBitField (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       BOOLEAN IsSet,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+BOOLEAN
+STATIC
+MemNS3GetDummyReadAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+     OUT   UINT64 *TestAddr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes the S3 resume for a node
+ *
+ *     @param[in,out]   *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
+ *     @param[in]       NodeID - The Node id of the target die
+ *
+ *     @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemNS3ResumeNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 DCT;
+  BOOLEAN GangedEn;
+  UINT64 TestAddr;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+
+  NBPtr = S3NBPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE;
+
+  // Errata before S3 resume sequence
+
+  // Resume Sequence
+  // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+
+  // Program F2x[1, 0]94[MemClkFreqVal] = 1.
+  // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
+      MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
+      while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {}
+    }
+  }
+
+  // Program F2x9C_x08[DisAutoComp]=0
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+  //    BIOS must wait 750 us for the phy compensation engine
+  //    to reinitialize.
+  MemFS3Wait10ns (75000, NBPtr->MemPtr);
+
+  // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C
+  // 4. Restore F2x[1,0]9C_x04
+  // Get the register value from the heap.
+  S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader);
+
+  // Add a hook here
+  AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+  if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
+  }
+  AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+
+  // 5. Set F2x[1,0]90[ExitSelfRef]
+  // 6. Wait for F2x[1,0]90[ExitSelfRef]=0
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
+      MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
+      while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
+    }
+    if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
+      if (DCT == 0) {
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
+      }
+      // NOTE: wait 512 clocks for DLL-relock
+      MemFS3Wait10ns (50000, NBPtr->MemPtr);  // wait 500us
+    }
+  }
+
+  // Errata After S3 resume sequence
+  // Errata 350
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
+      if (!((DCT == 1) && GangedEn)) {
+        if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) {
+          // Do dummy read
+          Read64Mem8 (TestAddr);
+          // Flush the cache line
+          LibAmdCLFlush (TestAddr, 1);
+        }
+      }
+      MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
+      MemFS3Wait10ns (60, NBPtr->MemPtr);   // Wait 300ns
+      MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
+      MemFS3Wait10ns (400, NBPtr->MemPtr);  // Wait 2us
+    }
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes the S3 resume for a node on a client NB
+ *
+ *     @param[in,out]   *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
+ *     @param[in]       NodeID - The Node id of the target die
+ *
+ *     @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemNS3ResumeClientNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 DCT;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+
+  NBPtr = S3NBPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  // Errata before S3 resume sequence
+
+  // Add a hook here
+  AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+  if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
+  }
+  AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+
+  NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
+  //Override the NB Pstate if needed
+  IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader);
+  // Set F2x[1,0]90[ExitSelfRef]
+  // Wait for F2x[1,0]90[ExitSelfRef]=0
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
+      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
+      MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
+      while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
+      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
+    }
+  }
+
+  // Errata After S3 resume sequence
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes the S3 resume for a node on a UNB
+ *
+ *     @param[in,out]   *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
+ *     @param[in]       NodeID - The Node id of the target die
+ *
+ *     @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemNS3ResumeUNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 DCT;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+
+  NBPtr = S3NBPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  // Errata before S3 resume sequence
+
+  // Add a hook here
+  AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+  if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
+  }
+  AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+
+  //Override the NB Pstate if needed
+  IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader);
+  // Set F2x[1,0]90[ExitSelfRef]
+  // Wait for F2x[1,0]90[ExitSelfRef]=0
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
+      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
+      MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
+      while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
+      if (NBPtr->IsSupported[SetDllShutDown]) {
+        MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
+      }
+    }
+  }
+
+  // Errata After S3 resume sequence
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the conditional PCI device mask
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *      @return         none
+ */
+VOID
+MemNS3GetConPCIMaskNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  BIT_FIELD_NAME bitfield;
+  UINT32 RegVal;
+  UINT8 DCT;
+  UINT8 DimmMask;
+  UINT8 BadDimmMask;
+  UINT8 DctGangEn;
+  BOOLEAN IsDDR3;
+
+  IsDDR3 = FALSE;
+  DimmMask = 0;
+  BadDimmMask = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    NBPtr->SwitchDCT (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
+      if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
+        IsDDR3 = TRUE;
+      }
+      for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
+        RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
+        if (RegVal & 0x3) {
+          DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
+        } else if (RegVal & 0x4) {
+          BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
+        }
+      }
+    }
+  }
+
+  NBPtr->SwitchDCT (NBPtr, 0);
+  DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn);
+  // Set channel mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    if (DimmMask & (0x55 << DCT)) {
+      // Set mask before exit self refresh
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
+      // Set mask after exit self refresh
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT;
+      // Set DDR3 mask if Dimms present are DDR3
+      if (IsDDR3) {
+        DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
+      }
+    } else if (BadDimmMask & (0x55 << DCT)) {
+      // Need to save function 2 registers for bad dimm
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
+    }
+  }
+
+  // Set dimm mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
+  if (DctGangEn) {
+    // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers
+    // need to be restored on both channels in ganged mode
+    DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2;
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2;
+    if (IsDDR3) {
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4);
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4);
+    }
+    // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored
+    // in that time frame don't care about individual dimm population. We want to
+    // skip registers that are not needed to be restored for DCT1 in ganged mode.
+    //
+    // After exit self refresh, training registers will be restored and will only be
+    // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1.
+    //
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1;
+  }
+
+  // Adjust the mask if there is no dimm on the node
+  if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) &&
+    (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) {
+    DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the conditional PCI device mask
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *      @return         none
+ */
+VOID
+MemNS3GetConPCIMaskUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  BIT_FIELD_NAME bitfield;
+  UINT32 RegVal;
+  UINT8 DCT;
+  UINT8 DimmMask;
+  UINT8 BadDimmMask;
+  UINT8 NbPsCap;
+
+  DimmMask = 0;
+  BadDimmMask = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
+      for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
+        RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
+        if (RegVal & 0x1) {
+          DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
+        } else if (RegVal & 0x4) {
+          BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
+        }
+      }
+    }
+  }
+  // Check if the system is capable of doing NB Pstate change
+  NbPsCap = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateDis);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  // Set channel mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    if (DimmMask & (0x55 << DCT)) {
+      // Set mask before exit self refresh
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= ((NbPsCap == 0) ? 5 : 1) << DCT;
+      // Set mask after exit self refresh
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT;
+      // Set DDR3 mask if Dimms present are DDR3
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
+    } else if (BadDimmMask & (0x55 << DCT)) {
+      // Need to save function 2 registers for bad dimm
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
+    }
+  }
+
+  // Set dimm mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
+
+  // Adjust the mask if there is no dimm on the node
+  if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) &&
+    (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) {
+    DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function read the value of CSR register.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3GetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 ExtendOffset;
+  UINT32 ValueRead;
+  UINT8 DataPort;
+
+  ValueRead = 0;
+  ExtendOffset = Address.Address.Register;
+  if (ExtendOffset & 0x800) {
+    Address.Address.Register = 0xF0;
+    DataPort = 0xF4;
+  } else {
+    Address.Address.Register = 0x98;
+    DataPort = 0x9C;
+  }
+  if (ExtendOffset & 0x400) {
+    Address.Address.Register |= 0x100;
+  }
+  ExtendOffset &= 0x3FF;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
+  while (((ValueRead >> 31) & 1) == 0) {
+    LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
+  }
+  Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort;
+  LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function write to a CSR register
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 ExtendOffset;
+  UINT32 ValueRead;
+  UINT32 ValueWrite;
+  UINT8 DataOffset;
+
+  ValueRead = 0;
+  ExtendOffset = Address.Address.Register;
+  // Check the flag and see the type of the access
+  if (ExtendOffset & 0x800) {
+    Address.Address.Register = 0xF4;
+    DataOffset = 0xF0;
+  } else {
+    Address.Address.Register = 0x9C;
+    DataOffset = 0x98;
+  }
+  if (ExtendOffset & 0x400) {
+    Address.Address.Register |= 0x100;
+  }
+  ExtendOffset &= 0x3FF;
+  ExtendOffset |= 0x40000000;
+  switch (AccessWidth) {
+  case AccessS3SaveWidth8:
+    ValueWrite = *(UINT8 *) Value;
+    break;
+  case AccessS3SaveWidth16:
+    ValueWrite = *(UINT16 *) Value;
+    break;
+  case AccessS3SaveWidth32:
+    ValueWrite = *(UINT32 *) Value;
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr);
+  Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
+  while (((ValueRead >> 31) & 1) == 0) {
+    LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function reads register bitfield
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3GetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function writes register bitfield
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function restores scrubber base register
+ *
+ *     @param[in,out]   *NBPtr - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Node - The Node id of the target die
+ *
+ */
+VOID
+MemNS3RestoreScrubNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Node
+  )
+{
+  UINT32 ScrubAddrRJ16;
+
+  ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
+  ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24;
+  MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
+  MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disable NB Pstate Debug.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3DisNbPsDbgNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 RegValue;
+
+  LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  // Clear NbPsDbgEn and NbPsCsrAccSel
+  if ((RegValue & 0xC0000000) != 0) {
+    RegValue &= 0x3FFFFFFF;
+    LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function that enable NB Pstate debug register to allow access to NB Pstate
+ *   1 registers without actually changing NB Pstate.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3EnNbPsDbg1Nb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 RegValue;
+
+  LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  // Set NbPsDbgEn to 1 and NbPsCsrAccSel to 1
+  if ((RegValue & 0xC0000000) != 0xC0000000) {
+    RegValue = (*(UINT32 *)Value & 0x3FFFFFFF) | 0xC0000000;
+    LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets bit 31 [DynModeChange] of F2x9C_xB
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetDynModeChangeNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 RegValue;
+
+  RegValue = 0x80000000;
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function does the channel disable sequence
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3DisableChannelNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  UINT32 RegValue;
+  UINT8 Die;
+
+  // See which Node should be accessed
+  Die = (UINT8) (Address.Address.Device - 24);
+
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+    NBPtr = S3NBPtr[Die].NBPtr;
+
+    // Function field contains the DCT number
+    NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
+    RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri);
+    // if CKETri is 0b11, this channel is disabled
+    if (RegValue == 3) {
+      //Wait for 24 MEMCLKs, which is 60ns under 400MHz
+      MemFS3Wait10ns (6, NBPtr->MemPtr);
+      MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+      MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+      MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disables auto compensation.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetDisAutoCompUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT16 RegValue;
+
+  MemNS3GetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+  RegValue = 0x6000 | RegValue;
+  MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retores Pre Driver Calibration with pre driver calibration code
+ *   code valid bit set.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetPreDriverCalUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT16 RegValue;
+
+  RegValue = 0x8000 | *(UINT16 *) Value;
+  MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is used by families that use a separate DctCfgSel bit to
+ *     select the current DCT which will be accessed by function 2.
+ *     NOTE:  This function must be called BEFORE the NBPtr->Dct variable is
+ *     updated.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Dct     - Pointer to ID of the target DCT
+ *
+ */
+
+BOOLEAN
+MemNS3DctCfgSelectUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *Dct
+  )
+{
+  // Set the DctCfgSel to new DCT
+  //
+  MemNSetBitFieldNb (NBPtr, BFDctCfgSel, *(UINT8*)Dct);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function write to a register that has one copy for each NB Pstate
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3GetNBPStateDepRegUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8 NBPstate;
+  UINT8 TempValue;
+  UINT8 Dct;
+  UINT32 Temp;
+
+  Temp = Address.Address.Register;
+  NBPstate = (UINT8) (Temp >> 10);
+  Dct = (UINT8) Address.Address.Function;
+  Temp &= 0x3FF;
+
+  // Switch Dct
+  // Function field contains DCT value
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  TempValue = (TempValue & 0xC8) | ((NBPstate << 4) | Dct);
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+
+  Address.Address.Function = FUNC_2;
+  Address.Address.Register = Temp;
+  LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
+
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  TempValue = 0;
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function write to a register that has one copy for each NB Pstate
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetNBPStateDepRegUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8 NBPstate;
+  UINT8 TempValue;
+  UINT8 Dct;
+  UINT32 Temp;
+
+  Temp = Address.Address.Register;
+  NBPstate = (UINT8) (Temp >> 10);
+  Dct = (UINT8) Address.Address.Function;
+  Temp &= 0x3FF;
+
+  // Switch Dct
+  // Function field contains DCT value
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct);
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+
+  Address.Address.Function = FUNC_2;
+  Address.Address.Register = Temp;
+  LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr);
+
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  TempValue = 0;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function read the value of Function 2 PCI register.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the NB register in PCI_ADDR format.
+ *     @param[in]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SaveNBRegiserUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8 TempValue;
+  UINT8 Dct;
+  UINT32 Temp;
+
+  Temp = Address.Address.Register;
+  Dct = (UINT8) Address.Address.Function;
+
+  // Switch Dct
+  // Function field contains DCT value
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  TempValue = (TempValue & 0xFE) | Dct;
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+
+  Address.Address.Register = Temp;
+  Address.Address.Function = FUNC_2;
+  LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function set the value of Function 2 PCI register.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the NB register in PCI_ADDR format.
+ *     @param[in]  *Value - Pointer to the value be write.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3RestoreNBRegiserUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8 TempValue;
+  UINT8 Dct;
+  UINT32 Temp;
+
+  Temp = Address.Address.Register;
+  Dct = (UINT8) Address.Address.Function;
+
+  // Switch Dct
+  // Function field contains DCT value
+  Address.Address.Function = FUNC_1;
+  Address.Address.Register = 0x10C;
+  LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+  TempValue = (TempValue & 0xFE) | Dct;
+  LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
+
+  Address.Address.Register = Temp;
+  Address.Address.Function = FUNC_2;
+  LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets MemClkFreqVal bit.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetMemClkFreqValUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 TempValue;
+
+  // 1. Program MemClkFreqVal = 1
+  MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  TempValue |= 0x80;
+  MemNS3RestoreNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+
+  // 2. Wait for FreqChgInPrg = 0
+  MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  while ((TempValue & 0x200000) != 0) {
+    MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function changes memory Pstate context
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format. Target MemPState is in
+ *                            Address.Address.Register.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNS3ChangeMemPStateContextNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  UINT8 Die;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    // See which Node should be accessed
+    Die = (UINT8) (Address.Address.Device - 24);
+
+    LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+    if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+      S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+      NBPtr = S3NBPtr[Die].NBPtr;
+      MemNChangeMemPStateContextNb (NBPtr, Address.Address.Register);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retores Phy Clk DLL fine delay
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetPhyClkDllFineClientNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT16 RegValue;
+
+  RegValue = 0x4000 | *(UINT16 *) Value;
+  MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+  RegValue = 0xBFFF & *(UINT16 *) Value;
+  MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function forces NBPstate to NBP0
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read or  written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3ForceNBP0Unb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT8   NbPstateMaxVal;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+    if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+      S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+      NBPtr = S3NBPtr[0].NBPtr;
+
+      if (MemNGetBitFieldNb (NBPtr, BFCurNbPstate) != 0) {
+
+        NBPtr->NbPsCtlReg = MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg);
+
+        // If current NBPstate is already in NBPstateLo, do not do transition to NBPstateLo.
+        if (MemNGetBitFieldNb (NBPtr, BFNbPstateLo) != MemNGetBitFieldNb (NBPtr, BFCurNbPstate)) {
+          // 2.Program D18F5x170 to transition the NB P-state:
+          //   NbPstateLo = NbPstateMaxVal. (HW requires an intermediate transition to low)
+          //   SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0.
+          NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal);
+          MemNSetBitFieldNb (NBPtr, BFNbPstateLo, NbPstateMaxVal);
+          MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF91FF);
+          // 3.Wait for D18F5x174[CurNbPstate] to equal NbPstateLo.
+          while (MemNGetBitFieldNb (NBPtr, BFCurNbPstate) != NbPstateMaxVal) {}
+        }
+        // 4.Program D18F5x170 to force the NB P-state:
+        //   NbPstateHi = target NB P-state.
+        //   SwNbPstateLoDis = 1 (triggers the transition)
+        MemNSetBitFieldNb (NBPtr, BFNbPstateHi, 0);
+        MemNSetBitFieldNb (NBPtr, BFSwNbPstateLoDis, 1);
+        // 5.Wait for D18F5x174[CurNbPstate] to equal the target NB P-state.
+        while (MemNGetBitFieldNb (NBPtr, BFCurNbPstate) != 0) {}
+
+        // Update TSC rate
+        GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+        FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
+      }
+    } else {
+      ASSERT (FALSE);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function releases NBPState force
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read or  written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3ReleaseNBPSUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
+    LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+    if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+      S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+      NBPtr = S3NBPtr[0].NBPtr;
+
+      if (NBPtr->NbPsCtlReg != 0) {
+        // 6. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0] values.
+        MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF9FFF) | (NBPtr->NbPsCtlReg & 0x6000));
+        // 7. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values.
+        MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFFF13F) | (NBPtr->NbPsCtlReg & 0x0EC0));
+        // 8. Restore the initial D18F5x170[NbPstateLo] values.
+        MemNSetBitFieldNb (NBPtr, BFNbPstateLo, (NBPtr->NbPsCtlReg >> 3) & 3);
+      }
+    } else {
+      ASSERT (FALSE);
+    }
+  }
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function reads and writes register bitfield
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   IsSet - if this is a register read or write
+ *     @param[in, out]  *Value - Pointer to the value be read or  written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3GetSetBitField (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       BOOLEAN IsSet,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  BIT_FIELD_NAME BitField;
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  UINT32 RegValue;
+  UINT8 Die;
+
+  RegValue = 0;
+  // See which Node should be accessed
+  Die = (UINT8) (Address.Address.Device - 24);
+
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+    NBPtr = S3NBPtr[Die].NBPtr;
+
+    // Function field contains the DCT number
+    NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
+
+    // Get the bitfield name to be accessed
+    // Register field contains the bitfield name
+    BitField = (BIT_FIELD_NAME) Address.Address.Register;
+
+    if (IsSet) {
+      switch (AccessWidth) {
+      case AccessS3SaveWidth8:
+        RegValue = *(UINT8 *) Value;
+        break;
+      case AccessS3SaveWidth16:
+        RegValue = *(UINT16 *) Value;
+        break;
+      case AccessS3SaveWidth32:
+        RegValue = *(UINT32 *) Value;
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+      MemNSetBitFieldNb (NBPtr, BitField, RegValue);
+    } else {
+      RegValue = MemNGetBitFieldNb (NBPtr, BitField);
+
+      switch (AccessWidth) {
+      case AccessS3SaveWidth8:
+        *(UINT8 *) Value = (UINT8) RegValue;
+        break;
+      case AccessS3SaveWidth16:
+        *(UINT16 *) Value = (UINT16) RegValue;
+        break;
+      case AccessS3SaveWidth32:
+        *(UINT32 *) Value = RegValue;
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+    }
+  } else {
+    ASSERT (FALSE);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the dummy read address for a channel of a node.
+ *
+ *     @param[in, out]  *NBPtr - Pointer to northbridge block
+ *     @param[out]      *TestAddr - Pointer to the test address
+ *
+ *     @retval           TRUE - Dummy read address can be found
+ *     @retval           FALSE - Dummy read address cannot be found
+ *
+ */
+BOOLEAN
+STATIC
+MemNS3GetDummyReadAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+     OUT   UINT64 *TestAddr
+  )
+{
+  BOOLEAN DctSelIntlvEn;
+  UINT8 DramIntlvEn;
+  UINT8 DctSelIntlvAddr;
+  UINT8 IntLvRgnBaseAddr;
+  UINT8 IntLvRgnLmtAddr;
+  UINT8 IntLvRgnSize;
+  UINT32 DctSelBaseAddr;
+  UINT64 TOM;
+  BOOLEAN AddrFound;
+
+  AddrFound = TRUE;
+  // Check if Node interleaving is enabled
+  DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn);
+  if (DramIntlvEn != 0) {
+    // Set the address bits that identify the node
+    *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12;
+  } else {
+    *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27;
+  }
+
+  // Check if channel interleaving is enabled
+  DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn);
+  DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr);
+  if (!DctSelIntlvEn) {
+    if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
+      *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
+    }
+  } else {
+    DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr);
+    // Set the address bits that identify the channel
+    if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) {
+      *TestAddr |= (UINT64) NBPtr->Dct << 6;
+    } else if (DctSelIntlvAddr == 1) {
+      *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1));
+    } else if (DctSelIntlvAddr == 3) {
+      *TestAddr |= (UINT64) NBPtr->Dct << 9;
+    }
+  }
+  // Adding 2M to avoid conflict
+  *TestAddr += 0x200000;
+
+  // If memory hoisting is disabled, the address can fall into MMIO area
+  // Need to find an address out of MMIO area but belongs to the channel
+  // If the whole channel is in MMIO, then do not do dummy read.
+  //
+  LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader);
+  if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) {
+    if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
+      // This is the DCT that goes to high address range
+      if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) {
+        // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr
+        if (DctSelIntlvEn) {
+          *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
+        }
+      } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) {
+        // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as
+        // dummy read address
+        *TestAddr =  ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
+      } else {
+        AddrFound = FALSE;
+      }
+    } else {
+      // This is the DCT that only goes to low address range
+      if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) {
+        // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address
+        // Keep the lower bits for node and channel selection
+        *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
+      } else {
+        AddrFound = FALSE;
+      }
+    }
+  }
+
+  // Interleaved Swap Region handling
+  if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) {
+    IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr);
+    IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr);
+    IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize);
+    ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
+    if (((*TestAddr >> 34) == 0) &&
+      ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr))
+       || ((*TestAddr >> 27) < IntLvRgnSize))) {
+      *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
+    }
+  }
+
+  return AddrFound;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
new file mode 100644
index 0000000000..48020c4aaa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
@@ -0,0 +1,3613 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mndct.c
+ *
+ * Common Northbridge DCT support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mftds.h"
+#include "merrhdl.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MNDCT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemNAfterStitchMemNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGet1KTFawTkNb (
+  IN       UINT8 k
+  );
+
+UINT8
+MemNGet2KTFawTkNb (
+  IN       UINT8 k
+  );
+
+VOID
+STATIC
+MemNQuarterMemClk2NClkNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *SubTotalPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function combines all the memory into a contiguous map.
+ *      Requires that Mask values for each bank be programmed first and that
+ *      the chip-select population indicator is correctly set.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNStitchMemoryNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN DSpareEn;
+  UINT32 NxtCSBase;
+  UINT32 CurCSBase;
+  UINT32 CsSize;
+  UINT32 BiggestBank;
+  UINT8 p;
+  UINT8 q;
+  UINT8 BiggestDimm;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  DSpareEn = FALSE;
+  if (NBPtr->IsSupported[SetSpareEn]) {
+    DSpareEn = FALSE;
+    if (RefPtr->GStatus[GsbEnDIMMSpareNW]) {
+      DSpareEn = TRUE;
+    }
+  }
+
+  DCTPtr->Timings.CsEnabled = 0;
+  NxtCSBase = 0;
+  for (p = 0; p < MAX_CS_PER_CHANNEL; p++) {
+    BiggestBank = 0;
+    BiggestDimm = 0;
+    for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+      if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) {
+        if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) {
+          // (CSEnable|Spare==1)bank is not enabled yet
+          CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1));
+          if (CsSize != 0) {
+            CsSize += ((UINT32)1 << 19);
+            CsSize &= 0xFFF80000;
+          }
+          if (CsSize > BiggestBank) {
+            BiggestBank = CsSize;
+            BiggestDimm = q;
+          }
+        }
+      }
+    }
+
+    if (BiggestBank != 0) {
+      CurCSBase = NxtCSBase;
+      if (NBPtr->IsSupported[CheckSpareEn]) {
+        if (DSpareEn) {
+          CurCSBase = ((UINT32)1 << BFSpare);
+          DSpareEn = FALSE;
+        } else {
+          CurCSBase |= ((UINT32)1 << BFCSEnable);
+          NxtCSBase += BiggestBank;
+        }
+      } else {
+        CurCSBase |= ((UINT32)1 << BFCSEnable);
+        NxtCSBase += BiggestBank;
+      }
+      if ((BiggestDimm & 1) != 0) {
+        if (!(MCTPtr->Status[SbLrdimms])) {
+          // For LRDIMMS, On Dimm Mirroring is enabled after SDI
+          if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) {
+            CurCSBase |= ((UINT32)1 << BFOnDimmMirror);
+          }
+        }
+      }
+      MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase);
+      DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm);
+    }
+    if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "Node %d Dct %d exclude CS %d\n", NBPtr->Node, NBPtr->Dct, p);
+      MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail);
+    }
+  }
+
+  if (NxtCSBase != 0) {
+    DCTPtr->Timings.DctMemSize = NxtCSBase >> 8;    // Scale base address from [39:8] to [47:16]
+    MemNAfterStitchMemNb (NBPtr);
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets platform specific config/timing values from the interface layer and
+ *   programs them into DCT.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST BIT_FIELD_NAME ChipletPDRegs[] = {
+  BFPhyClkConfig0,
+  BFPhyClkConfig3,
+  BFPhyClkConfig1,
+  BFPhyClkConfig2
+  };
+  CONST UINT8 ChipletPDClkDisMap[][2] = {
+  //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]]
+  {0, 1},
+  //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]]
+  {6, 7},
+  //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]]
+  {4, 5},
+  //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]]
+  {2, 3},
+  //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]]
+  {2, 5},
+  //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]]
+  {3, 4}
+  };
+
+  UINT8 MemClkDis;
+  UINT8 i;
+  UINT8 MemoryAllClocks;
+  UINT8 *MemClkDisMap;
+  UINT16 CsPresent;
+  UINT8 RegIndex;
+  UINT8 Cs1;
+  UINT8 Cs2;
+
+  if (!MemNGetPlatformCfgNb (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+  MemNProgramPlatformSpecNb (NBPtr);
+
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS);
+
+  if (NBPtr->MCTPtr->GangedMode) {
+    MemNSwitchDCTNb (NBPtr, 1);
+    if (!MemNGetPlatformCfgNb (NBPtr)) {
+      IDS_ERROR_TRAP;
+    }
+    MemNProgramPlatformSpecNb (NBPtr);
+    MemNSwitchDCTNb (NBPtr, 0);
+  }
+
+  //======================================================================
+  // Disable unused MemClk to save power
+  //======================================================================
+  //
+  MemClkDis = 0;
+  MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn;
+  IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader));
+  if (!MemoryAllClocks) {
+    // Special Jedec SPD diagnostic bit - "enable all clocks"
+    if (!NBPtr->MCTPtr->Status[SbDiagClks]) {
+      MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0), 0,
+                                          &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+      if (MemClkDisMap == NULL) {
+        MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap;
+      }
+
+      // Turn off the unused CS clocks
+      CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+      if (NBPtr->IsSupported[CheckMemClkCSPresent]) {
+        if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
+          // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register
+          // regardless of how many Ranks are on the DIMM (Single, Dual or Quad)
+          CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555;
+        }
+      }
+      for (i = 0; i < 8; i++) {
+        if ((CsPresent & MemClkDisMap[i]) == 0) {
+          MemClkDis |= (UINT8) (1 << i);
+        }
+      }
+      //Chiplet power down
+      for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) {
+        if ((NBPtr->Dct == 1) && (RegIndex >= 2)) {
+          Cs1 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]];
+          Cs2 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]];
+        } else {
+          Cs1 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]];
+          Cs2 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]];
+        }
+        if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) {
+          MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10));
+        }
+      }
+    }
+  }
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis);
+
+  AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->MemNInitPhyComp (NBPtr);
+
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
+
+  // Program DramTerm for DDR2
+  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) {
+    MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm);
+  } else {
+    // Dynamic Dynamic DramTerm for DDR3
+    // Dram Term for DDR3 may vary based on chip selects
+    MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm);
+  }
+
+  MemFInitTableDrive (NBPtr, MTAfterPlatformSpec);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets platform specific config/timing values from the interface layer and
+ *   programs them into DCT.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNPlatformSpecUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 MemClkDis;
+  UINT8 i;
+  UINT8 MemoryAllClocks;
+  UINT8 *MemClkDisMap;
+  UINT16 CsPresent;
+
+  if (!MemNGetPlatformCfgNb (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tDisable DCT%d due to unsupported DIMM configuration\n", NBPtr->Dct);
+    if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+      ASSERT (FALSE);
+    }
+    NBPtr->DisableDCT (NBPtr);
+  } else {
+
+    MemNProgramPlatformSpecNb (NBPtr);
+    MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS);
+
+    //======================================================================
+    // Disable unused MemClk to save power
+    //======================================================================
+    //
+    MemClkDis = 0;
+    MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn;
+    IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader));
+    if (!MemoryAllClocks) {
+      // Special Jedec SPD diagnostic bit - "enable all clocks"
+      if (!NBPtr->MCTPtr->Status[SbDiagClks]) {
+        MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct, 0,
+                                            &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+        if (MemClkDisMap == NULL) {
+          MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap;
+        }
+
+        // Turn off unused clocks
+        CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+        for (i = 0; i < 8; i++) {
+          if ((CsPresent & MemClkDisMap[i]) == 0) {
+            MemClkDis |= (UINT8) (1 << i);
+          }
+        }
+
+        // Turn off unused chiplets
+        for (i = 0; i < 3; i++) {
+          if (((MemClkDis >> (i * 2)) & 0x3) == 0x3) {
+            MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0 + i, 0x0010);
+          }
+        }
+      }
+    }
+    MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis);
+    MemFInitTableDrive (NBPtr, MTAfterPlatformSpec);
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disables the DCT and mem clock
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNDisableDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03);
+  MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F);
+  MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF);
+
+  // To maximize power savings when DisDramInterface=1b,
+  // all of the MemClkDis bits should also be set.
+  //
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+  MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disables the DCT and mem clock for client NB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNDisableDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03);
+  MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F);
+  MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF);
+
+  //Wait for 24 MEMCLKs
+  MemNWaitXMemClksNb (NBPtr, 24);
+
+  // To maximize power savings when DisDramInterface=1b,
+  // all of the MemClkDis bits should also be set.
+  //
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+
+  MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
+
+  MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disables the DCT and mem clock for UNB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNDisableDCTUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFExtendedParityEn, 0);
+  MemNSetBitFieldNb (NBPtr, BFParEn, 0);
+  MemNSetBitFieldNb (NBPtr, BFCKETri, 0x0F);
+
+  //Wait for 24 MEMCLKs
+  MemNWaitXMemClksNb (NBPtr, 24);
+
+  // To maximize power savings when DisDramInterface=1b,
+  // all of the MemClkDis bits should also be set.
+  //
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+
+  MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+
+  if (NBPtr->Dct == 0) {
+    MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0x100);
+  }
+
+  // If channel is disabled after dram init, set DisDllShutdownSR
+  if (MemNGetBitFieldNb (NBPtr, BFDramEnabled) == 1) {
+    MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function initializes the DRAM devices on all DCTs at the same time
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1.
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // DisAutoComp is still being set since InitPhyComp
+
+  if (NBPtr->MCTPtr->NodeMemSize != 0) {
+    // Init MemClk frequency
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+
+
+    AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+    NBPtr->MemNBeforeDramInitNb (NBPtr);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed);
+    AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
+    NBPtr->FeatPtr->DramInit (NBPtr->TechPtr);
+  }
+
+  // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0.
+  // 8. BIOS must wait 750 us for the phy compensation engine
+  //    to reinitialize.
+  // DisAutoComp will be cleared after DramEnabled turns to 1
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function initializes the DRAM devices on all DCTs at the same time
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNStartupDCTUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT16 FinalPllLockTime;
+
+  if (NBPtr->MCTPtr->NodeMemSize != 0) {
+    // Update NB frequency for startup DDR speed
+    NBPtr->ChangeNbFrequency (NBPtr);
+
+    if (!NBPtr->IsSupported[ForcePhyToM0]) {
+      MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000);
+
+      MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118);
+    }
+
+    // Phy Voltage Level Programming
+    MemNPhyVoltageLevelNb (NBPtr);
+
+    // Run frequency change sequence
+    MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+    NBPtr->FamilySpecificHook[SetSkewMemClk] (NBPtr, NULL);
+    NBPtr->ProgramNbPsDependentRegs (NBPtr);
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
+        MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
+        MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+      }
+    }
+    FinalPllLockTime = 0xF;
+    NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime);
+    if (!NBPtr->IsSupported[CsrPhyPllPdEn]) {
+      // IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program
+      // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh
+      MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime);
+    }
+
+    NBPtr->FamilySpecificHook[BeforePhyFenceTraining] (NBPtr, NBPtr);
+
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+
+        // Phy fence programming
+        AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->PhyFenceTraining (NBPtr);
+
+        // Phy compensation initialization
+        AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->MemNInitPhyComp (NBPtr);
+        MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
+      }
+    }
+
+    AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+    NBPtr->MemNBeforeDramInitNb (NBPtr);
+
+    AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed);
+    NBPtr->FeatPtr->DramInit (NBPtr->TechPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * MemNChangeFrequencyHy:
+ *
+ *  This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNChangeFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+
+  TechPtr = NBPtr->TechPtr;
+  if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) {
+    // #107421
+    MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
+  }
+
+  //Program F2x[1,0]90[EnterSelfRefresh]=1.
+  //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
+  MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  //Program F2x9C_x08[DisAutoComp]=1
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+
+  //Program F2x[1, 0]94[MemClkFreqVal] = 0.
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
+
+  //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency.
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+
+  IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
+  //Program F2x[1, 0]94[MemClkFreqVal] = 1.
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+
+  //Wait until F2x[1, 0]94[FreqChgInProg]=0.
+  MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->IsSupported[CheckPhyFenceTraining]) {
+    //Perform Phy Fence retraining after frequency changed
+    AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+        AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+        MemNPhyFenceTrainingNb (NBPtr);
+      }
+    }
+  }
+
+  //Program F2x9C_x08[DisAutoComp]=0
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+
+  //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
+  //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
+  MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->MCTPtr->Status[SbRegistered]) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        TechPtr->FreqChgCtrlWrd (TechPtr);
+      }
+    }
+  }
+
+  //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns
+  MemNWaitXMemClksNb (NBPtr, 500);
+
+  if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) {
+    // #107421
+    MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
+  }
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+
+      //9.Configure the DCT to send initialization MR commands:
+      //  BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
+      //  Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values.
+      TechPtr->AutoCycTiming (TechPtr);
+      if (!MemNPlatformSpecNb (NBPtr)) {
+        IDS_ERROR_TRAP;
+      }
+
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+        if (NBPtr->IsSupported[CheckGetMCTSysAddr]) {
+          if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+            // if chip select present
+            TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+            // NOTE: wait 512 clocks for DLL-relock
+            MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+          }
+        }
+        if (NBPtr->IsSupported[CheckSendAllMRCmds]) {
+          if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+
+            // if chip select present
+            TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+          }
+        }
+      }
+      if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
+        if (Dct == 0) {
+          MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
+        }
+        // NOTE: wait 512 clocks for DLL-relock
+        MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+      }
+    }
+  }
+  // Re-enable phy compensation since it had been disabled during InitPhyComp
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+
+  MemFInitTableDrive (NBPtr, MTAfterFreqChg);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function ramp up frequency the next level if it have not reached
+ *      its TargetSpeed yet.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNRampUpFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT16 FreqList[] = {
+    DDR400_FREQUENCY,
+    DDR533_FREQUENCY,
+    DDR667_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR1066_FREQUENCY,
+    DDR1333_FREQUENCY,
+    DDR1600_FREQUENCY,
+    DDR1866_FREQUENCY,
+    DDR2133_FREQUENCY
+  };
+  UINT8 Dct;
+  UINT8 i;
+  UINT16 NewSpeed;
+  DIE_STRUCT *MCTPtr;
+
+  MCTPtr = NBPtr->MCTPtr;
+
+  // Do not change frequency when it is already at TargetSpeed
+  if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
+    return TRUE;
+  }
+
+  // Find the next supported frequency level
+  NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed;
+  for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) {
+    if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) {
+      NewSpeed = FreqList[i + 1];
+      break;
+    }
+  }
+  ASSERT (i < (GET_SIZE_OF (FreqList) - 1));
+  ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed);
+
+  // BIOS must program both DCTs to the same frequency.
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed);
+  for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.Speed = NewSpeed;
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NewSpeed);
+
+  NBPtr->ChangeFrequency (NBPtr);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function ramp up frequency to target frequency
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNRampUpFrequencyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  DIE_STRUCT *MCTPtr;
+
+  MCTPtr = NBPtr->MCTPtr;
+
+  // Do not change frequency when it is already at TargetSpeed
+  if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
+    return TRUE;
+  }
+
+  // BIOS must program both DCTs to the same frequency.
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed);
+  for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.Speed = NBPtr->DCTPtr->Timings.TargetSpeed;
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NBPtr->DCTPtr->Timings.TargetSpeed);
+
+  NBPtr->ChangeFrequency (NBPtr);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function uses calculated values from DCT.Timings structure to
+ *      program its registers.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramCycTimingsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST CTENTRY TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 4, 12, 4, 2},
+    {BFTrcd, 5, 12, 5, 2},
+    {BFTrp, 5, 12, 5, 2},
+    {BFTrtp, 4, 7, 4, 2},
+    {BFTras, 15, 30, 15, 2},
+    {BFTrc, 11, 42, 11, 2},
+    {BFTwrDDR3, 5, 12, 4, 2},
+    {BFTrrd, 4, 7, 4, 2},
+    {BFTwtr, 4, 7, 4, 2},
+    {BFFourActWindow, 16, 32, 14, 1}
+  };
+
+  DCT_STRUCT *DCTPtr;
+  UINT8  *MiniMaxTmg;
+  UINT8  *MiniMaxTrfc;
+  UINT8  Value8;
+  UINT8  j;
+  BIT_FIELD_NAME BitField;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //======================================================================
+  // Program turnaround timings to their max during DRAM init and training
+  //======================================================================
+  //
+  MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF);
+
+  MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  MiniMaxTmg = &DCTPtr->Timings.CasL;
+  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
+    BitField = TmgAdjTab[j].BitField;
+
+    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Min;
+    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Max;
+    }
+
+    Value8 = (UINT8) MiniMaxTmg[j];
+
+    if (BitField == BFTwrDDR3) {
+      Value8 = (Value8 == 10) ? 9 : (Value8 >= 11) ? 10 : Value8;
+    } else if (BitField == BFTrtp) {
+      Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6;
+    }
+
+    Value8 = Value8 - TmgAdjTab[j].Bias;
+    Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
+
+    ASSERT ((BitField == BFTcl ) ? (Value8 <= 8) :
+            (BitField == BFTrcd) ? (Value8 <= 7) :
+            (BitField == BFTrp ) ? (Value8 <= 7) :
+            (BitField == BFTrtp) ? (Value8 <= 3) :
+            (BitField == BFTras) ? (Value8 <= 15) :
+            (BitField == BFTrc ) ? (Value8 <= 31) :
+            (BitField == BFTrrd) ? (Value8 <= 3) :
+            (BitField == BFTwtr) ? (Value8 <= 3) :
+            (BitField == BFTwrDDR3) ? ((Value8 >= 1) && (Value8 <= 6)) :
+            (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 9)) : FALSE);
+    MemNSetBitFieldNb (NBPtr, BitField, Value8);
+  }
+
+  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
+  for (j = 0; j < 4; j++) {
+    ASSERT (MiniMaxTrfc[j] <= 4);
+    MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ?
+                                     (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0));
+
+  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // 7.8 us
+
+  //======================================================================
+  // DRAM MRS Register, set ODT
+  //======================================================================
+  //
+  // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
+  MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
+
+  // burst length control
+  if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+    MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2);
+  }
+
+  // ASR=1, auto self refresh; SRT=0
+  MemNSetBitFieldNb (NBPtr, BFASR, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function uses calculated values from DCT.Timings structure to
+ *      program its registers.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramCycTimingsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST CTENTRY TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 5, 14, 4, 2},
+    {BFTrcd, 5, 14, 5, 2},
+    {BFTrp, 5, 14, 5, 2},
+    {BFTrtp, 4, 8, 4, 2},
+    {BFTras, 15, 36, 15, 2},
+    {BFTrc, 20, 49, 11, 2},
+    {BFTwrDDR3, 5, 16, 4, 2},
+    {BFTrrd, 4, 8, 4, 2},
+    {BFTwtr, 4, 8, 4, 2},
+    {BFFourActWindow, 16, 40, 14, 1}
+  };
+
+  DCT_STRUCT *DCTPtr;
+  UINT8  *MiniMaxTmg;
+  UINT8  *MiniMaxTrfc;
+  UINT8  Value8;
+  UINT8  j;
+  UINT8  Tcwl;
+  UINT8  Trcd;
+  INT32  TCK_ps;
+  BIT_FIELD_NAME BitField;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  MiniMaxTmg = &DCTPtr->Timings.CasL;
+  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
+    BitField = TmgAdjTab[j].BitField;
+
+    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Min;
+    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Max;
+    }
+
+    Value8 = (UINT8) MiniMaxTmg[j];
+
+    if (BitField == BFTwrDDR3) {
+      if (NBPtr->IsSupported[AdjustTwr]) {
+        Value8 ++;
+      }
+      Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8;
+    }
+
+    if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) {
+      Value8 -= 5;
+    }
+
+    Value8 = Value8 - TmgAdjTab[j].Bias;
+    Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
+
+    ASSERT ((BitField == BFTcl ) ? ((Value8 >= 1) && (Value8 <= 10)) :
+            (BitField == BFTrcd) ? (Value8 <= 9) :
+            (BitField == BFTrp ) ? (Value8 <= 9) :
+            (BitField == BFTrtp) ? (Value8 <= 4) :
+            (BitField == BFTras) ? (Value8 <= 21) :
+            (BitField == BFTrc ) ? (NBPtr->IsSupported[AdjustTrc] ? ((Value8 >= 4) && (Value8 <= 38)) : ((Value8 >= 9) && (Value8 <= 38))) :
+            (BitField == BFTrrd) ? (Value8 <= 4) :
+            (BitField == BFTwtr) ? (Value8 <= 4) :
+            (BitField == BFTwrDDR3) ? (Value8 <= 7) :
+            (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 13)) : FALSE);
+    MemNSetBitFieldNb (NBPtr, BitField, Value8);
+  }
+
+  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
+  for (j = 0; j < 4; j++) {
+    ASSERT (MiniMaxTrfc[j] <= 5);
+    MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
+  }
+
+  Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2;
+  MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0));
+
+  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // Tref = 7.8 us
+
+  // Skid buffer can only be programmed once before Dram init
+  if (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) {
+    TCK_ps = 1000500 / DCTPtr->Timings.TargetSpeed;
+    Trcd = (UINT8) ((((1000 / 40) * (UINT32)DCTPtr->Timings.DIMMTrcd) + TCK_ps - 1) / TCK_ps);
+    MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (Trcd > 10) ? 0 : 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0);
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function uses calculated values from DCT.Timings structure to
+ *      program its registers for UNB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramCycTimingsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST CTENTRY TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 5, 14, 0, 2},
+    {BFTrcd, 2, 19, 0, 2},
+    {BFTrp, 2, 19, 0, 2},
+    {BFTrtp, 4, 10, 0, 2},
+    {BFTras, 8, 40, 0, 2},
+    {BFTrc, 10, 56, 0, 2},
+    {BFTwrDDR3, 5, 16, 0, 2},
+    {BFTrrd, 4, 9, 0, 2},
+    {BFTwtr, 4, 9, 0, 2},
+    {BFFourActWindow, 6, 42, 0, 2}
+  };
+
+  DCT_STRUCT *DCTPtr;
+  UINT8  *MiniMaxTmg;
+  UINT8  *MiniMaxTrfc;
+  UINT8  Value8;
+  UINT8  j;
+  UINT8  Tcwl;
+  UINT8 RdOdtTrnOnDly;
+  BIT_FIELD_NAME BitField;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  MiniMaxTmg = &DCTPtr->Timings.CasL;
+  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
+    BitField = TmgAdjTab[j].BitField;
+
+    if (BitField == BFTrp) {
+      if (NBPtr->IsSupported[AdjustTrp]) {
+        MiniMaxTmg[j] ++;
+        if (MiniMaxTmg[j] < 5) {
+          MiniMaxTmg[j] = 5;
+        }
+      }
+    }
+
+    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Min;
+    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Max;
+    }
+
+    Value8 = (UINT8) MiniMaxTmg[j];
+
+    if (BitField == BFTwrDDR3) {
+      if ((Value8 > 8) && ((Value8 & 1) != 0)) {
+        ASSERT (FALSE);
+      }
+    }
+
+    MemNSetBitFieldNb (NBPtr, BitField, Value8);
+  }
+
+  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
+  for (j = 0; j < 4; j++) {
+    if ((NBPtr->DCTPtr->Timings.DctDimmValid & (1 << j)) != 0) {
+      ASSERT (MiniMaxTrfc[j] <= 4);
+      MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
+    }
+  }
+
+  Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2;
+  Tcwl = (Tcwl > 5) ? Tcwl : 5;
+  MemNSetBitFieldNb (NBPtr, BFTcwl, Tcwl);
+
+  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // 7.8 us
+
+  RdOdtTrnOnDly = (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0;
+  MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, RdOdtTrnOnDly);
+  NBPtr->FamilySpecificHook[ProgOdtControl] (NBPtr, NULL);
+
+  //
+  // Program Tmod
+  //
+  MemNSetBitFieldNb (NBPtr, BFTmod, (DCTPtr->Timings.Speed < DDR1866_FREQUENCY) ? 0x0C :
+                                    (DCTPtr->Timings.Speed > DDR1866_FREQUENCY) ? 0x10 : 0x0E);
+  //
+  // Program Tzqcs and Tzqoper
+  //
+  // Tzqcs max(64nCK, 80ns)
+  MemNSetBitFieldNb (NBPtr, BFTzqcs, MIN (6, (MAX (64, MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 80)) + 15) / 16));
+  // Tzqoper max(256nCK, 320ns)
+  MemNSetBitFieldNb (NBPtr, BFTzqoper, MIN (0xC, (MAX (256, MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 320)) + 31) / 32));
+
+  // Program power management timing
+  MemNDramPowerMngTimingNb (NBPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets platform specific settings for the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - All platform types defined have initialized successfully
+ *     @return          FALSE - At least one of the platform types gave not been initialized successfully
+ */
+
+BOOLEAN
+MemNGetPlatformCfgNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 p;
+
+  for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+    ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL);
+    if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) {
+      break;
+    }
+  }
+  return (p < MAX_PLATFORM_TYPES);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retrieves the Max latency parameters
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @param[in]  *MinDlyPtr - Pointer to variable to store the Minimum Delay value
+ *     @param[in]  *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
+ *     @param[in]  *DlyBiasPtr - Pointer to variable to store Delay Bias value
+ *     @param[in]  MaxRcvEnDly - Maximum receiver enable delay value
+ */
+
+VOID
+MemNGetMaxLatParamsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  )
+{
+  *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2;
+  MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr);
+
+  *MaxDlyPtr = 0x3FF;
+
+  *DlyBiasPtr = 4;
+  MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr);   // 1 MEMCLK Margin
+
+  *DlyBiasPtr += 1;  // add 1 NCLK
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function  sets the maximum round-trip latency in the system from the processor to the DRAM
+ *   devices and back.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     MaxRcvEnDly - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  )
+{
+  UINT16 SubTotal;
+
+  AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
+
+  SubTotal = 0xC8;    // init value for MaxRdLat used in training
+
+
+  if (MaxRcvEnDly != 0xFFFF) {
+    // Get all sync components BKDG steps 1-5
+    SubTotal = MemNTotalSyncComponentsNb (NBPtr);
+
+    // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay
+    // that exists across all DIMMs and byte lanes.
+    //
+    SubTotal += MaxRcvEnDly >> 5;
+
+
+    // Add 14.5 to the sub-total. 14.5 represents part of the processor
+    // specific constant delay value in the DRAM clock domain.
+    //
+    SubTotal <<= 1;             // scale 1/2 MemClk to 1/4 MemClk
+    SubTotal += 29;             // add 14.5 1/2 MemClk
+
+    // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs)
+    // as follows (assuming DDR400 and assuming that no P-state or link speed
+    // changes have occurred).
+    //
+    MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal);
+
+    // Add 2 NCLKs to the sub-total. 2 represents part of the processor
+    // specific constant value in the northbridge clock domain.
+    //
+    SubTotal += 2;
+  }
+
+  NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal;
+  // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", SubTotal);
+  MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends the ZQCL command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 1.Program MrsAddress[10]=1
+  MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10);
+
+  // 2.Set SendZQCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1);
+
+  // 3.Wait for SendZQCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+
+  // 4.Wait 512 MEMCLKs
+  MemNWaitXMemClksNb (NBPtr, 512);
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function is used to create the DRAM map
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+
+VOID
+STATIC
+MemNAfterStitchMemNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->MCTPtr->GangedMode) {
+    NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize;
+    NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
+    NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+    NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+    NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize;
+  } else {
+    // In unganged mode, add DCT0 and DCT1 to NodeMemSize
+    NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
+    NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This function Return the binary value of tfaw associated with
+ *       the index k
+ *
+ *     @param[in]     k value
+ *
+ *     @return       F[k], in Binary MHz.
+ */
+
+UINT8
+MemNGet1KTFawTkNb (
+  IN       UINT8 k
+  )
+{
+  CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19};
+  ASSERT (k <= 5);
+  return Tab1KTfawTK[k];
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This function Return the binary value of the 2KTFaw associated with
+ *       the index k
+ *
+ *     @param[in]     k value
+ *
+ *     @return       2KTFaw converted based on k.
+ */
+
+UINT8
+MemNGet2KTFawTkNb (
+  IN       UINT8 k
+  )
+{
+  CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24};
+  ASSERT (k <= 5);
+  return Tab2KTfawTK[k];
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs)
+ *      (assuming DDR400 and assuming that no P-state or link speed
+ *      changes have occurred).
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *SubTotalPtr - pointer to Sub-Total
+ */
+
+VOID
+STATIC
+MemNQuarterMemClk2NClkNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *SubTotalPtr
+  )
+{
+  UINT32 NBFreq;
+  UINT32 MemFreq;
+
+  // Multiply SubTotal by NB COF
+  NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;
+  // Divide SubTotal by 4 times current MemClk frequency
+  MemFreq = NBPtr->DCTPtr->Timings.Speed * 4;
+  *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq);  // round up
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the total of sync components for Max Read Latency calculation
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Total in 1/2 MEMCLKs
+ */
+
+UINT16
+MemNTotalSyncComponentsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16 SubTotal;
+
+  // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs.
+  SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1;
+  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) {
+    SubTotal += 3;
+  }
+  SubTotal *= 2;
+
+  // If registered DIMMs are being used then add 1 MEMCLK to the sub-total.
+  if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) {
+    SubTotal += 2;
+  }
+
+  // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1
+  // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2
+  if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
+    SubTotal += 1;
+  } else {
+    SubTotal += 2;
+  }
+
+  // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
+  // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total.
+  //
+  SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit));
+
+  return SubTotal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function swaps bits for OnDimmMirror support
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSwapBitsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT32 MRSReg;
+
+  ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel);
+  if ((ChipSel & 1) != 0) {
+    MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg);
+    if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
+      MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1);
+      MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function swaps bits for OnDimmMirror support for Unb
+ *
+ *     Dimm Mirroring Requires that, during MRS command cycles, the following
+ *     bits are swapped by software
+ *
+ *             A3 -> A4         A7 -> A8
+ *             A4 -> A3         BA0 -> BA1
+ *             A5 -> A6         BA1 -> BA0
+ *             A6 -> A5
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSwapBitsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT32 MRSBank;
+  UINT32 MRSAddr;
+
+  ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel);
+  if ((ChipSel & 1) != 0) {
+    if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
+      MRSBank = MemNGetBitFieldNb (NBPtr, BFMrsBank);
+      MRSAddr = MemNGetBitFieldNb (NBPtr, BFMrsAddress);
+
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x swapped to ->",
+                                                                    (ChipSel & 0x7),
+                                                                    (MRSBank & 0x7),
+                                                                    (MRSAddr & 0x3FFFF));
+      //
+      // Swap Mrs Bank bits 0 with 1
+      MRSBank = (MRSBank & 0x0100) | ((MRSBank & 0x01) << 1) | ((MRSBank & 0x02) >> 1);
+      //
+      // Swap Mrs Address bits 3 with 4, 5 with 6, and 7 with 8
+      MRSAddr = (MRSAddr & 0x03FE07) | ((MRSAddr&0x000A8) << 1) | ((MRSAddr&0x00150) >> 1);
+      MemNSetBitFieldNb (NBPtr, BFMrsBank, MRSBank);
+      MemNSetBitFieldNb (NBPtr, BFMrsAddress, MRSAddr);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   Programs Address/command timings, driver strengths, and tri-state fields.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNProgramPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8           PinType[3]  = {PSO_CKE_TRI, PSO_ODT_TRI,   PSO_CS_TRI};
+  CONST UINT8           TabSize[3]  = {          2,           4,            8};
+  CONST BIT_FIELD_NAME  BitField[3] = {   BFCKETri,    BFODTTri, BFChipSelTri};
+  UINT8  *TabPtr;
+  UINT8  i;
+  UINT8  k;
+  UINT8  Value;
+  //===================================================================
+  // Tristate unused CKE, ODT and chip select to save power
+  //===================================================================
+  //
+  TabPtr = NULL;
+  for (k = 0; k < sizeof (PinType); k++) {
+    if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) {
+      TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0), 0,
+                                    &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+    }
+    if (NBPtr->IsSupported[CheckFindPSDct]) {
+      TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct, 0,
+                                    &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+    }
+    if (TabPtr == NULL) {
+      switch (k) {
+      case 0:
+        TabPtr = NBPtr->ChannelPtr->CKETriMap;
+        break;
+      case 1:
+        TabPtr = NBPtr->ChannelPtr->ODTTriMap;
+        break;
+      case 2:
+        TabPtr = NBPtr->ChannelPtr->ChipSelTriMap;
+        break;
+      default:
+        IDS_ERROR_TRAP;
+      }
+    }
+    ASSERT (TabPtr != NULL);
+
+    Value = 0;
+    for (i = 0; i < TabSize[k]; i++) {
+      if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) {
+        Value |= (UINT8) (1 << i);
+      }
+    }
+
+    if (k == PSO_CS_TRI) {
+      NBPtr->FamilySpecificHook[BeforeSetCsTri] (NBPtr, &Value);
+    }
+
+    ASSERT (k < GET_SIZE_OF (BitField));
+    MemNSetBitFieldNb (NBPtr, BitField[k], Value);
+  }
+  NBPtr->MemNBeforePlatformSpecNb (NBPtr);
+
+  //===================================================================
+  // Program Address/Command timings and driver strength
+  //===================================================================
+  //
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS);
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS);
+
+  MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0);
+  MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
+  MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
+  NBPtr->FamilySpecificHook[SetDqsODT] (NBPtr, NBPtr);
+
+  if (NBPtr->IsSupported[CheckODTControls]) {
+    MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow);
+    MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh);
+    MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow);
+    MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
+  }
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Trdrd value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Trdrd value
+ */
+
+UINT8
+MemNGetTrdrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+  INT8 Cgdd;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the
+  // converted field value. BIOS rounds fractional values down.
+  // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1,
+  // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1,
+  // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM.
+
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly);
+  DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3;
+
+  // Transfer clk to reg definition, 2T is 00b, etc.
+  DCTPtr->Timings.Trdrd -= 2;
+  if (DCTPtr->Timings.Trdrd > 8) {
+    DCTPtr->Timings.Trdrd = 8;
+  }
+
+  return DCTPtr->Timings.Trdrd;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Twrwr value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Twrwr value
+ */
+
+UINT8
+MemNGetTwrwrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+  INT8 Cgdd;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the
+  // converted field value. BIOS rounds fractional values down.
+  // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6,
+  // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1,
+  // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross
+  // Delay Difference (CGDD) for Twrwr.
+
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly);
+  DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3;
+  NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr);
+
+  return DCTPtr->Timings.Twrwr;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs
+ * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional
+ * values down.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return  Value to be programmed to Twrrd field
+ *              pDCT->Timings.Twrrd updated
+ */
+
+UINT8
+MemNGetTwrrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Cgdd;
+  INT8 Ld;
+  INT8 Twrrd;
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //
+  // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
+  // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
+  // value.
+  // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
+  //
+  Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr);
+
+  // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM
+  // minus the DqsRcvEnGrossDelay delay of any other DIMM is
+  // equal to the Critical Gross Delay Difference (CGDD) for Twrrd.
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly);
+  Twrrd = (Cgdd / 2) - Ld + 3;
+  DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0);
+  NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr);
+
+  return DCTPtr->Timings.Twrrd;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the TrwtTO value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return  pDCT->Timings.TrwtTO updated
+ */
+
+UINT8
+MemNGetTrwtTONb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Cgdd;
+  INT8 Ld;
+  INT8 TrwtTO;
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+  //
+  // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
+  // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
+  // value.
+  // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
+  //
+  Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr);
+
+  // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus
+  // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross
+  // Delay Difference (CGDD) for TrwtTO.
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly);
+  TrwtTO = (Cgdd / 2) + Ld + 3;
+  TrwtTO -= 2;
+  DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1);
+
+  return DCTPtr->Timings.TrwtTO;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the TrwtWB value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      TrwtWB value
+ */
+UINT8
+MemNGetTrwtWBNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  // TrwtWB ensures read-to-write data-bus turnaround.
+  // This value should be one more than the programmed TrwtTO.
+  return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts MemClk frequency in MHz to MemClkFreq value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Speed   - MemClk frequency in MHz
+ *
+ *     @return      MemClkFreq value
+ */
+UINT8
+MemNGetMemClkFreqIdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  )
+{
+  return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables swapping interleaved region feature.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Base   - Swap interleaved region base [47:27]
+ *     @param[in]   Limit   - Swap interleaved region limit [47:27]
+ *
+ */
+VOID
+MemNEnableSwapIntlvRgnNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Base,
+  IN       UINT32 Limit
+  )
+{
+  UINT32 Size;
+  UINT32 SizeOfAlign;
+
+  // Swapped interleaving region must be below 16G
+  if (Limit < (1 << (34 - 27))) {
+    // Adjust Base and Size to meet :
+    // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase].
+    // 2. Entire UMA region is swapped with interleaving region.
+    Size = Limit - Base;
+    SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base);
+    while (SizeOfAlign <= Size) {
+      // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB.
+      Base -= 1;
+      Size += 1;
+      SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base);
+    }
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base);
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1));
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size);
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts MemClk frequency in MHz to MemClkFreq value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Speed   - MemClk frequency in MHz
+ *
+ *     @return      MemClkFreq value
+ */
+UINT8
+MemNGetMemClkFreqIdClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  )
+{
+  return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts MemClk frequency in MHz to MemClkFreq value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Speed   - MemClk frequency in MHz
+ *
+ *     @return      MemClkFreq value
+ */
+UINT8
+MemNGetMemClkFreqIdUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  )
+{
+  return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts MemClkFreq Id value to MemClk frequency in MHz
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       FreqId   - FreqId from Register
+ *
+ *     @return          MemClk frequency in MHz
+ */
+UINT16
+MemNGetMemClkFreqUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 FreqId
+  )
+{
+  UINT16 MemClkFreq;
+  if (FreqId > 2) {
+    MemClkFreq = (FreqId == 14) ? 667 : (300 + ((FreqId - 3) * 33) + (FreqId - 3) / 3);
+  } else if (FreqId == 2) {
+    MemClkFreq = 200;
+  } else {
+    MemClkFreq = 50 + (50 * FreqId);
+  }
+  return MemClkFreq;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
+ *  for client NB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNChangeFrequencyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT16 FinalPllLockTime;
+  BOOLEAN FrequencyChangeSuccess;
+  UINT64  OrgMMIOCfgBase;
+  UINT64  NewMMIOCfgBase;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Disable MMIO to prevent speculative DRAM reads during self refresh
+  LibAmdMsrRead (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader));
+  NewMMIOCfgBase = OrgMMIOCfgBase & (~(BIT0));
+  LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &NewMMIOCfgBase, &(NBPtr->MemPtr->StdHeader));
+
+  MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
+
+  //Program F2x[1,0]90[EnterSelfRefresh]=1.
+  //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
+  MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->ChangeNbFrequency (NBPtr)) {
+    // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        TechPtr->AutoCycTiming (TechPtr);
+        if (!MemNPlatformSpecUnb (NBPtr)) {
+          IDS_ERROR_TRAP;
+        }
+      }
+    }
+
+    // 1. Program PllLockTime to Family-specific value
+    MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
+
+    // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
+
+    // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+
+    // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
+    // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
+    // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule
+    // Delay Programming].
+    // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
+    //                                                                         THEN 2 ELSE 3 ENDIF (Ontario)
+    NBPtr->ProgramNbPsDependentRegs (NBPtr);
+
+    NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr);
+    IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+    MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE);
+    FinalPllLockTime = 0xF;
+    NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime);
+
+    // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program
+    // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh.
+    if (!NBPtr->IsSupported[CsrPhyPllPdEn]) {
+      MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime);
+    }
+
+    FrequencyChangeSuccess = TRUE;
+  } else {
+    // If NB frequency cannot be updated, use the current speed as the target speed
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed;
+      NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed;
+    }
+    FrequencyChangeSuccess = FALSE;
+  }
+
+  //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
+  //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
+  MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
+
+  if (FrequencyChangeSuccess) {
+    NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL);
+
+    // Perform Phy Fence training and Phy comp init after frequency change
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+
+        // Phy fence programming
+        AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->PhyFenceTraining (NBPtr);
+
+        // Phy compensation initialization
+        AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->MemNInitPhyComp (NBPtr);
+        MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
+      }
+    }
+
+    //======================================================================
+    // Calculate and program DRAM Timings at new frequency
+    //======================================================================
+    //
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+          if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+            // if chip select present
+            if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) {
+              TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+            }
+          }
+        }
+        // Wait 512 clocks for DLL-relock
+        MemNWaitXMemClksNb (NBPtr, 512);
+      }
+    }
+  }
+
+  // Restore MMIO setting
+  LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader));
+
+  MemFInitTableDrive (NBPtr, MTAfterFreqChg);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
+ *  for UNB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNChangeFrequencyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT16 FinalPllLockTime;
+  BOOLEAN FrequencyChangeSuccess;
+  UINT64  OrgMMIOCfgBase;
+  UINT64  NewMMIOCfgBase;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Disable MMIO to prevent speculative DRAM reads during self refresh
+  LibAmdMsrRead (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader));
+  NewMMIOCfgBase = OrgMMIOCfgBase & (~(BIT0));
+  LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &NewMMIOCfgBase, &(NBPtr->MemPtr->StdHeader));
+
+  MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
+
+  //Program F2x[1,0]90[EnterSelfRefresh]=1.
+  //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
+  MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->ChangeNbFrequency (NBPtr)) {
+    // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        TechPtr->AutoCycTiming (TechPtr);
+        if (!MemNPlatformSpecUnb (NBPtr)) {
+          IDS_ERROR_TRAP;
+        }
+      }
+    }
+
+    // 1. Program PllLockTime to Family-specific value
+    MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
+
+    // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
+
+    // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+
+    // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
+    // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
+    // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule
+    // Delay Programming].
+    // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
+    //                                                                         THEN 2 ELSE 3 ENDIF (Ontario)
+    NBPtr->ProgramNbPsDependentRegs (NBPtr);
+
+    IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
+        MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
+        MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+      }
+    }
+    FinalPllLockTime = 0xF;
+    NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime);
+
+    // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program
+    // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh.
+    if (!NBPtr->IsSupported[CsrPhyPllPdEn]) {
+      MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime);
+    }
+
+    FrequencyChangeSuccess = TRUE;
+  } else {
+    // If NB frequency cannot be updated, use the current speed as the target speed
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed;
+      NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed;
+    }
+    FrequencyChangeSuccess = FALSE;
+  }
+
+  if (FrequencyChangeSuccess) {
+    // Perform Phy Fence training and Phy comp init after frequency change
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+
+        // Phy fence programming
+        AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->PhyFenceTraining (NBPtr);
+
+        // Phy compensation initialization
+        AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->MemNInitPhyComp (NBPtr);
+        MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
+      }
+    }
+  }
+
+  //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
+  //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
+  MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  if (NBPtr->IsSupported[SetDllShutDown]) {
+    MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
+  }
+
+  if (FrequencyChangeSuccess) {
+    NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL);
+
+    //======================================================================
+    // Calculate and program DRAM Timings at new frequency
+    //======================================================================
+    //
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+          if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+            // if chip select present
+            if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) {
+              TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+            }
+          }
+        }
+        // Wait 512 clocks for DLL-relock
+        MemNWaitXMemClksNb (NBPtr, 512);
+      }
+    }
+  }
+
+  // Restore MMIO setting
+  LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader));
+
+  MemFInitTableDrive (NBPtr, MTAfterFreqChg);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function calculates and programs NB P-state dependent registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramNbPstateDependentRegistersUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 RdPtrInit;
+
+  RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 4;
+  MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
+
+  MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
+  );
+
+  switch (RdPtrInit) {
+  case 4:
+    if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) {
+      MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2);
+    } else {
+      MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
+    }
+    break;
+  case 5:
+    MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
+    break;
+  case 6:
+    MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+
+  NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr);
+  IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
+CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};
+
+/**
+ *
+ *  This function calculates and programs NB P-state dependent registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramNbPstateDependentRegistersClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  UINT8 Dct;
+  UINT8 NclkFid;
+  UINT16 MemClkDid;
+  UINT8 PllMult;
+  UINT8 NclkDiv;
+  UINT8 RdPtrInitMin;
+  UINT8 RdPtrInit;
+  UINT32 NclkPeriod;
+  UINT32 MemClkPeriod;
+  INT32 PartialSum2x;
+  INT32 PartialSumSlotI2x;
+  INT32 RdPtrInitRmdr2x;
+  INT32 TDataProp;
+  UINT8 NbPstate;
+  UINT8 SlowMode;
+  UINT32 CalcNclkDiv;
+  UINT32 DbeGskFifoNumeratorVal;
+  UINT32 DbeGskFifoDenominatorVal;
+
+  CalcNclkDiv = 0;
+  NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10);  // NclkFid is in 100MHz
+
+  MemClkDid = PllDivTab[NBPtr->DCTPtr->Timings.Speed / 133];
+  NBPtr->FamilySpecificHook[OverridePllDiv] (NBPtr, &MemClkDid);
+  PllMult = PllMultTab[NBPtr->DCTPtr->Timings.Speed / 133];
+  NBPtr->FamilySpecificHook[OverridePllMult] (NBPtr, &PllMult);
+
+  if (NBPtr->NbFreqChgState == 2) {
+    MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 1);
+    MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 1);
+    NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv);
+    // Divisors less than 8 are undefined.  Maybe the CPU does not support NB P-states.
+    if (NclkDiv < 8) {
+      // Set a dummy divisor to prevent divide by zero exception below.
+      NclkDiv = 8;
+    }
+    NbPstate = 1;
+  } else {
+    NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv);
+    NbPstate = 0;
+  }
+
+  if (NclkDiv >= 0x60) {
+    CalcNclkDiv = (NclkDiv - 0x40) * 10000;
+  } else if (NclkDiv >= 0x40) {
+    CalcNclkDiv = ((NclkDiv - 0x40) * 5000) + 160000;
+  } else {
+    CalcNclkDiv = 2500 * NclkDiv;
+  }
+
+  NclkPeriod = CalcNclkDiv / NclkFid;  // (1,000,000 * 0.25 * NclkDiv) / (NclkFid * 100MHz) = ps
+  MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+  NBPtr->NBClkFreq = ((UINT32) NclkFid * 1000000) / CalcNclkDiv;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d  Freq: %dMHz\n", NbPstate, NBPtr->NBClkFreq);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed);
+  // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
+  //                                                                      THEN 2 ELSE 3 ENDIF (Ontario)
+  RdPtrInit = RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667;
+  NBPtr->FamilySpecificHook[AdjustRdPtrInit] (NBPtr, &RdPtrInit);
+  MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
+
+  // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
+  DbeGskFifoNumeratorVal = NclkFid * MemClkDid * 16;
+  DbeGskFifoDenominatorVal = NclkDiv * PllMult;
+  if (NclkDiv >= 0x40) {
+    DbeGskFifoNumeratorVal = NclkFid * MemClkDid * 4;
+    DbeGskFifoDenominatorVal = CalcNclkDiv * PllMult / 10000;
+  }
+  MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, DbeGskFifoNumeratorVal);
+  MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, DbeGskFifoDenominatorVal);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", DbeGskFifoNumeratorVal);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", DbeGskFifoDenominatorVal);
+
+  // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
+  // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0].
+  //   PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
+  //   CmdSetup - PtrSeparation - 1. (Llano)
+  //   PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
+  //   CmdSetup - PtrSeparation - 1. (Ontario)
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod;
+      PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod;
+      PartialSum2x += 520 * 2;
+
+      // PtrSeparation = ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)/2 + RdPtrInitRmdr
+      // If (D18F2x[1,0]94[MemClkFreq] >= 800 MHz)
+      // then RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 990ps) MOD MemClkPeriod)/MemClkPeriod
+      // else RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 1466ps) MOD MemClkPeriod)/MemClkPeriod
+      TDataProp = (NBPtr->DCTPtr->Timings.Speed >= DDR1600_FREQUENCY) ?
+                  NBPtr->FreqChangeParam->TDataProp800orHigher : NBPtr->FreqChangeParam->TDataPropLower800;
+      RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (TDataProp + 520);
+      RdPtrInitRmdr2x %= MemClkPeriod;
+      PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16) * MemClkPeriod + RdPtrInitRmdr2x;
+
+      // Convert PartialSum2x to PCLK
+      PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod;  // round-up here
+      PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
+      if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
+        PartialSum2x -= 1;
+      } else {
+        PartialSum2x -= 2;
+      }
+      PartialSum2x -= 2;
+
+      // If PartialSumSlotN is positive:
+      //   DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN).
+      //   DataTxFifoSchedDlyNegSlotN=0.
+      // Else if PartialSumSlotN is negative:
+      //   DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)).
+      //   DataTxFifoSchedDlyNegSlotN=1.
+      for (i = 0; i < 2; i++) {
+        PartialSumSlotI2x = PartialSum2x;
+        SlowMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFSlowAccessMode);
+        if ((i == 0) && (SlowMode == 0)) {
+          PartialSumSlotI2x += 2;
+        }
+        if (NBPtr->IsSupported[SchedDlySlot1Extra] && (i == 1) && (SlowMode != 0)) {
+          PartialSumSlotI2x -= 2;
+        }
+        if (PartialSumSlotI2x > 0) {
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0);
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2);
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2);
+        } else {
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1);
+          PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod);
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x);
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x);
+        }
+      }
+
+      // Set ProcOdtAdv
+      if ((NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) &&
+          ((!(NBPtr->IsSupported[EnProcOdtAdvForUDIMM])) || (NBPtr->ChannelPtr->SODimmPresent != 0))) {
+        MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
+      } else {
+        MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000);
+      }
+    }
+  }
+
+  MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
+  if (NBPtr->NbFreqChgState == 2) {
+    MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 0);
+    MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 0);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the total of sync components for Max Read Latency calculation
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Total in ps
+ */
+
+UINT32
+MemNTotalSyncComponentsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 P;
+  UINT32 T;
+  UINT8  RdPtrInitMin;
+  UINT8  RdPtrInit;
+  UINT32 AddrTmgCtl;
+  UINT8  DbeGskMemClkAlignMode;
+  UINT32 MemClkPeriod;
+
+  // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)
+  RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667;
+  RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
+  P = (16 + RdPtrInitMin - RdPtrInit) % 16;
+
+  // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1
+  AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl);
+  if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) {
+    P += 1;
+  }
+
+  // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup)))
+  // THEN P = P + 1
+  DbeGskMemClkAlignMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode);
+  if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) &&
+      !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) {
+    P += 1;
+  }
+
+  // IF (SlowAccessMode==1) THEN P = P + 2
+  if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) {
+    P += 2;
+  }
+
+  // P = P + 2
+  P += 2;
+  T = 0;
+
+  // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0)
+  // then P = P + 1
+  // else P = P + 2
+  if ((AddrTmgCtl & 0x0202020) == 0) {
+    P += 1;
+  } else {
+    P += 2;
+  }
+
+  // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1))
+  P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1);
+
+  // If (DisCutThroughMode==0)
+  // then P = P + 3
+  // else P = P + 7
+  if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) {
+    P += 3;
+  } else {
+    P += 7;
+  }
+
+  MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+  return (((P * MemClkPeriod + 1) / 2) + T);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets up phy power saving for client NB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNPhyPowerSavingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b.
+  // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b.
+  // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b.
+  MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3);
+  // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins.
+  MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1);
+  // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1.
+  if (!NBPtr->FamilySpecificHook[DisLowPwrDrvStr] (NBPtr, NULL)) {
+    MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100);
+  }
+  // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <=
+  //    800 MHz) THEN 1 ELSE 0 ENDIF.
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+  // 10. Program D18F2x[1,0]9C_x0000_000D as follows:
+  //    TxMaxDurDllNoLock/RxMaxDurDllNoLock = 7h.
+  MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7);
+  MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7);
+  //    TxCPUpdPeriod/RxCPUpdPeriod = 011b.
+  MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3);
+  MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3);
+  //    TxDLLWakeupTime/RxDLLWakeupTime = 11b.
+  MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3);
+  MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3);
+
+  IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets up phy power saving for UNB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNPhyPowerSavingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16 MixedX4AndX8Dimms;
+
+  // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b.
+  // 5. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyL] = 1b.
+  MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 3);
+  // 6. D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][RxDqsUDllPowerDown] = (D18F2x90_dct[1:0][X4Dimm]!=0).
+  MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFX4Dimm) == 0 ? (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80) : (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) & 0xFF7F));
+  // 7. D18F2x9C_x0D0F_812F_dct[1:0][PARTri] = ~D18F2x90_dct[1:0][ParEn].
+  MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFParEn) == 0 ? (MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 1) : (MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) & 0xFFFE));
+  // 8. D18F2x9C_x0D0F_812F_dct[1:0][Add17Tri, Add16Tri] = {1b, 1b}
+  MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA0);
+  // 9. IF (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz && ~(mixed channel of x4 and x8 DIMMs)) THEN
+  //    Program D18F2x9C_x0D0F_0[F,8:0]10_dct[1:0][EnRxPadStandby] = 1.
+  //    ELSE
+  //    Program D18F2x9C_x0D0F_0[F,8:0]10_dct[1:0][EnRxPadStandby] = 0.
+  //    ENDIF.
+  MixedX4AndX8Dimms = NBPtr->DCTPtr->Timings.Dimmx4Present != 0 && NBPtr->DCTPtr->Timings.Dimmx8Present != 0;
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) && !MixedX4AndX8Dimms ? 0x1000 : 0);
+  // 10. IF (~(mixed channel of x4 and x8 DIMMs)) THEN
+  if (MixedX4AndX8Dimms == FALSE) {
+  //    Program D18F2x9C_x0000_000D_dct[1:0] as follows:
+  //    TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
+    MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7);
+    MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7);
+  //    TxCPUpdPeriod = RxCPUpdPeriod = 011b.
+    MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3);
+    MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3);
+  //    TxDLLWakeupTime = RxDLLWakeupTime = 11b.
+    MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3);
+    MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3);
+  } else {
+  //    ELSE
+  //    Program D18F2x9C_x0000_000D_dct[1:0][TxMaxDurDllNoLock, RxMaxDurDllNoLock, TxCPUpdPeriod,
+  //    RxCPUpdPeriod, TxDLLWakeupTime, RxDLLWakeupTime] = {0, 0, 0, 0, 0, 0}.
+    MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0);
+    MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0);
+    MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 0);
+    MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 0);
+    MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 0);
+    MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 0);
+  }
+  //  11. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][PwrDn] to disable unused ECC byte lane.
+  if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
+    if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
+      MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
+    }
+  }
+
+  //  12. Program D18F2x9C_x0D0F_0[F,8:0]04_dct[1:0][TriDM] = IF (LRDIMM & (D18F2x90_dct[1:0][X4Dimm] == 0)) THEN 1 ELSE 0.
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    MemNSetBitFieldNb (NBPtr, BFDataByteDMConf, (MemNGetBitFieldNb (NBPtr, BFX4Dimm) == 0) ? 0x2000 : 0);
+  }
+
+  IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function overrides the ASR and SRT value in MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNSetASRSRTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 MrsAddress;
+  UINT8 Dimm;
+  UINT8 *SpdBufferPtr;
+  BOOLEAN ASREn;
+  BOOLEAN SRTEn;
+
+  // Look for MR2
+  if (NBPtr->GetBitField (NBPtr, BFMrsBank) == 2) {
+    MrsAddress = NBPtr->GetBitField (NBPtr, BFMrsAddress);
+    // Clear A6(ASR) and A7(SRT)
+    MrsAddress &= (UINT32) ~0xC0;
+    if ((NBPtr->ChannelPtr->RegDimmPresent) || (NBPtr->ChannelPtr->LrDimmPresent)) {
+      // For registered dimm and LR dimm, MRS command is sent to all chipselects.
+      // So different ASR/SRT setting can be sent to each chip select.
+      Dimm = (UINT8) (NBPtr->GetBitField (NBPtr, BFMrsChipSel) >> 1);
+      // Make sure we access SPD of the second logical dimm of QR dimm correctly
+      if ((Dimm >= 2) && ((NBPtr->ChannelPtr->DimmQrPresent & (UINT8) (1 << Dimm)) != 0)) {
+        Dimm -= 2;
+      }
+      if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, Dimm)) {
+        // Bit 2 is ASR
+        if (SpdBufferPtr[THERMAL_OPT] & 0x4) {
+          // when ASR is 1, set SRT to 0
+          MrsAddress |= 0x40;
+        } else {
+          // Set SRT based on bit on of thermal byte
+          MrsAddress |= ((SpdBufferPtr[THERMAL_OPT] & 1) << 7);
+        }
+      }
+    } else {
+      // Udimm and unbuffered dimm, MSR command will be broadcasted during Dram Init.
+      // ASR/SRT value needs to be leveled across the DCT. Only if all dimms on the DCT
+      // support ASR or SRT can ASR or SRT be enabled.
+      ASREn = TRUE;
+      SRTEn = TRUE;
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm ++) {
+        if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, Dimm)) {
+          // Bit 2 is ASR
+          if ((SpdBufferPtr[THERMAL_OPT] & 0x4) == 0) {
+            // when any dimm in the DCT does not support ASR, disable ASR for the DCT
+            ASREn = FALSE;
+            // When any dimm does not have SRT with a value of 1, set SRT to 0 for the DCT
+            if ((SpdBufferPtr[THERMAL_OPT] & 1) == 0) {
+              SRTEn = FALSE;
+            }
+          }
+        }
+      }
+      if (ASREn) {
+        MrsAddress |= 0x40;
+      } else {
+        MrsAddress |= (UINT8) SRTEn << 7;
+      }
+    }
+
+    NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function changes NB frequency as below:
+ *     NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP0-DDRTarget
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemNChangeNbFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN Status;
+
+  Status = FALSE;
+
+  // State machine to change NB frequency and NB Pstate
+  switch (NBPtr->NbFreqChgState) {
+  case 0:
+    // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency
+    Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
+    ASSERT (Status);
+
+    if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
+      // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1
+      NBPtr->NbFreqChgState = 1;
+      IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    }
+    break;
+
+  case 1:
+    // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P0
+    MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0);
+
+    // Next state would be to change NBPstate back to P0
+    NBPtr->NbFreqChgState = 2;
+
+    // Update NB freq dependent registers
+    NBPtr->ProgramNbPsDependentRegs (NBPtr);
+
+    // Change NB P-State to NBP1 for MaxRdLat training
+    if (NBPtr->ChangeNbFrequencyWrap (NBPtr, 1)) {
+      // Enable cut through mode for NB P1
+      MemNBrdcstSetNb (NBPtr, BFDisCutThroughMode, 0);
+
+      // Return TRUE to repeat MaxRdLat training
+      Status = TRUE;
+
+    } else {
+      // If transition to NB-P1 fails, transition to exit state machine
+      NBPtr->NbFreqChgState = 3;
+    }
+    break;
+
+  case 2:
+    // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P1
+    MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0);
+
+    // Change NB P-State back to NBP0
+    Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
+    ASSERT (Status);
+
+    // Return FALSE to get out of MaxRdLat training loop
+    Status = FALSE;
+
+    // Exit state machine
+    NBPtr->NbFreqChgState = 3;
+    break;
+
+  default:
+    break;
+  }
+
+  return Status;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function programs registers before phy fence training for CNB
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNBeforePhyFenceTrainingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n");
+  MemNBrdcstSetNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n");
+  MemNBrdcstSetNb (NBPtr, BFEnDramInit, 1);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function changes NB frequency foras below:
+ *     NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP2-DDRTarget -> NBP3-DDRTarget -> NBP0-DDRTarget
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemNChangeNbFrequencyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN Status;
+
+  Status = FALSE;
+
+  // State machine to change NB frequency and NB Pstate
+  switch (NBPtr->NbFreqChgState) {
+  case 0:
+    // Do not change NB Pstate, just to save initial NB Pstate value
+    Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
+    if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
+      // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1
+      NBPtr->NbFreqChgState = 1;
+      IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    }
+    break;
+
+  case 1:
+  case 2:
+  case 3:
+    // Change NB P-State to NBP1 for MaxRdLat training
+    if (NBPtr->ChangeNbFrequencyWrap (NBPtr, NBPtr->NbFreqChgState)) {
+      // Next state is to try all NBPstates
+      NBPtr->NbFreqChgState++;
+
+      // Return TRUE to repeat MaxRdLat training
+      Status = TRUE;
+    } else {
+      // If transition to any NBPs fails, transition to exit state machine
+      NBPtr->NbFreqChgState = 4;
+    }
+    break;
+
+  case 4:
+    // Change NB P-State back to NBP0
+    Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
+    ASSERT (Status);
+
+    // Return FALSE to get out of MaxRdLat training loop
+    Status = FALSE;
+
+    // Exit state machine
+    NBPtr->NbFreqChgState = 5;
+    break;
+
+  default:
+    break;
+  }
+
+  return Status;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets "Dram Term" value from data structure
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       ChipSel  - Targeted chipsel
+ *
+ *     @return       Dram Term value
+ */
+UINT8
+MemNGetDramTermNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  UINT8 DramTerm;
+
+  if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) {
+    DramTerm = NBPtr->PsPtr->QR_DramTerm;
+  } else {
+    DramTerm = NBPtr->PsPtr->DramTerm;
+  }
+
+  return DramTerm;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets "Dram Term" value from data structure for Unb
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       ChipSel  - Targeted chipsel
+ *
+ *     @return       Dram Term value
+ */
+UINT8
+MemNGetDramTermTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  UINT8 RttNom;
+  RttNom = NBPtr->PsPtr->RttNom[ChipSel];
+  IDS_OPTION_HOOK (IDS_MEM_DRAM_TERM, &RttNom, &NBPtr->MemPtr->StdHeader);
+  return RttNom;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets "Dynamic Dram Term" value from data structure
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       ChipSel  - Targeted chipsel
+ *
+ *     @return       Dynamic Dram Term value
+ */
+UINT8
+MemNGetDynDramTermNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  return (NBPtr->PsPtr->DynamicDramTerm);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets "Dynamic Dram Term" value from data structure
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       ChipSel  - Targeted chipsel
+ *
+ *     @return       Dynamic Dram Term value
+ */
+UINT8
+MemNGetDynDramTermTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  UINT8 RttWr;
+  RttWr = NBPtr->PsPtr->RttWr[ChipSel];
+  IDS_OPTION_HOOK (IDS_MEM_DYN_DRAM_TERM, &RttWr, &NBPtr->MemPtr->StdHeader);
+  return RttWr;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns MR0[CL] value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       MR0[CL] value
+ */
+UINT32
+MemNGetMR0CLNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Tcl;
+  UINT32 Value32;
+
+  Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl);
+  Value32 = (UINT32) ((Tcl < 8) ? (Tcl << 4) : (((Tcl - 8) << 4) | 4));
+
+  return Value32;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns MR0[WR] value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       MR0[WR] value
+ */
+UINT32
+MemNGetMR0WRNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Value32;
+
+  Value32 = MemNGetBitFieldNb (NBPtr, BFTwrDDR3) << 9;
+
+  return Value32;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns MR0[WR] value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       MR0[WR] value
+ */
+UINT32
+MemNGetMR0WRTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return (UINT32) (NBPtr->PsPtr->MR0WR << 9);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns MR2[CWL] value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       MR0[CWL] value
+ */
+UINT32
+MemNGetMR2CWLNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Value32;
+
+  Value32 = MemNGetBitFieldNb (NBPtr, BFTcwl) << 3;
+
+  return Value32;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function returns MR2[CWL] value for UNB
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       MR0[CWL] value
+ */
+UINT32
+MemNGetMR2CWLUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Value32;
+
+  Value32 = (MemNGetBitFieldNb (NBPtr, BFTcwl) - 5) << 3;
+
+  return Value32;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets Txp and Txpdll
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       none
+ */
+VOID
+MemNSetTxpNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8 Txp[] = {0xFF, 0xFF, 3, 3, 4, 4, 5, 6, 7};
+  CONST UINT8 Txpdll[] = {0xFF, 0xFF, 0xA, 0xA, 0xD, 0x10, 0x14, 0x17, 0x1A};
+  UINT8 i;
+  UINT8 TxpVal;
+  UINT8 TxpdllVal;
+  UINT16 Speed;
+
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  i = (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
+  ASSERT (i < sizeof (Txp));
+  ASSERT (i < sizeof (Txpdll));
+
+  TxpdllVal = Txpdll[i];
+
+  if ((NBPtr->MCTPtr->Status[SbLrdimms] || NBPtr->MCTPtr->Status[SbRegistered]) &&
+      ((NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY)) &&
+      (NBPtr->RefPtr->DDR3Voltage == VOLT1_25)) {
+    TxpVal = 4;
+  } else {
+    TxpVal = Txp[i];
+  }
+
+  if (TxpVal != 0xFF) {
+    MemNSetBitFieldNb (NBPtr, BFTxp, TxpVal);
+  }
+  if (TxpdllVal != 0xFF) {
+    NBPtr->FamilySpecificHook[AdjustTxpdll] (NBPtr, &TxpdllVal);
+    MemNSetBitFieldNb (NBPtr, BFTxpdll, TxpdllVal);
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function adjust value of Txpdll to encoded value.
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNAdjustTxpdllClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  *(UINT8 *) OptParam -= 10;
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function is a wrapper to handle or switch NB Pstate for UNB
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]  *NBPstate - NB Pstate
+ *
+ *     @return          TRUE - Succeed
+ *     @return          FALSE - Fail
+ */
+
+BOOLEAN
+MemNChangeNbFrequencyWrapUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 NBPstate
+  )
+{
+  UINT8   TargetNbPs;
+  UINT32  FreqNumeratorInMHz;
+  UINT32  FreqDivisor;
+  UINT32  VoltageInuV;
+  UINT8   NbPstateMaxVal;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  if (NBPtr->NbFreqChgState == 0) {
+    // While in state 0, keep NB Pstate at the highest supported
+    TargetNbPs = 0;
+    if (NBPtr->NbPsCtlReg == 0) {
+      // Save NbPsCtl register on the first run
+      NBPtr->NbPsCtlReg = MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg);
+    } else {
+      // Do not need to switch NB Pstate again if it is already at highest
+      return TRUE;
+    }
+  } else if (NBPtr->NbFreqChgState < 4) {
+    // While in other states, go to the next lower NB Pstate
+    TargetNbPs = (UINT8) MemNGetBitFieldNb (NBPtr, BFCurNbPstate) + 1;
+    if (TargetNbPs == 1) {
+      // Set up intermediate NBPstate
+      NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal);
+      MemNSetBitFieldNb (NBPtr, BFNbPsSel, NbPstateMaxVal);
+      GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+      if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
+                                                  NBPtr->MemPtr->PlatFormConfig,
+                                                  &NBPtr->PciAddr,
+                                                  (UINT32) NbPstateMaxVal,
+                                                  &FreqNumeratorInMHz,
+                                                  &FreqDivisor,
+                                                  &VoltageInuV,
+                                                  &(NBPtr->MemPtr->StdHeader))) {
+        // Get NCLK speed for intermediate NBPstate
+        NBPtr->NBClkFreq = FreqNumeratorInMHz / FreqDivisor;
+        NBPtr->ProgramNbPsDependentRegs (NBPtr);
+      } else {
+        ASSERT (FALSE);
+      }
+    }
+  } else {
+    // When done with training, release NB Pstate force by restoring NbPsCtl register
+    NBPtr->FamilySpecificHook[ReleaseNbPstate] (NBPtr, NBPtr);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tRelease NB Pstate force\n");
+    return TRUE;
+  }
+
+  // Make sure target NB Pstate is enabled, else find next enabled NB Pstate
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  for (; TargetNbPs < 4; TargetNbPs++) {
+    if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
+                                                  NBPtr->MemPtr->PlatFormConfig,
+                                                  &NBPtr->PciAddr,
+                                                  (UINT32) TargetNbPs,
+                                                  &FreqNumeratorInMHz,
+                                                  &FreqDivisor,
+                                                  &VoltageInuV,
+                                                  &(NBPtr->MemPtr->StdHeader))) {
+      // Record NCLK speed
+      NBPtr->NBClkFreq = FreqNumeratorInMHz / FreqDivisor;
+      break;
+    }
+  }
+
+  if (TargetNbPs < 4) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tNB P%d: %dMHz\n", TargetNbPs, NBPtr->NBClkFreq);
+
+    // 1.Program the configuration registers which contain multiple internal copies for each NB P-state. See
+    //   D18F1x10C[NbPsSel].
+    MemNSetBitFieldNb (NBPtr, BFNbPsSel, TargetNbPs);
+
+    // Check to see if NB P-states have been disabled.  @todo This should only be needed for
+    // bring up, but must be included in any releases that occur before NB P-state operation
+    // has been debugged/fixed.
+    if ((NBPtr->NbPsCtlReg & 0x00000003) != 0) {
+      NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal);
+      // Set up RdPtrInit before transit to target NBPstate
+      if ((TargetNbPs > 0) && (TargetNbPs != NbPstateMaxVal))  {
+        NBPtr->ProgramNbPsDependentRegs (NBPtr);
+      }
+
+      // If current NBPstate is already in NBPstateLo, do not do transition to NBPstateLo.
+      if ((TargetNbPs != 0) || (MemNGetBitFieldNb (NBPtr, BFNbPstateLo) != MemNGetBitFieldNb (NBPtr, BFCurNbPstate))) {
+        // 2.Program D18F5x170 to transition the NB P-state:
+        //   NbPstateLo = NbPstateMaxVal. (HW requires an intermediate transition to low)
+        //   SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0.
+        MemNSetBitFieldNb (NBPtr, BFNbPstateLo, NbPstateMaxVal);
+        MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF91FF);
+
+        // 3.Wait for D18F5x174[CurNbPstate] to equal NbPstateLo.
+        MemNPollBitFieldNb (NBPtr, BFCurNbPstate, NbPstateMaxVal, PCI_ACCESS_TIMEOUT, FALSE);
+      }
+      // 4.Program D18F5x170 to force the NB P-state:
+      //   NbPstateHi = target NB P-state.
+      //   SwNbPstateLoDis = 1 (triggers the transition)
+      MemNSetBitFieldNb (NBPtr, BFNbPstateHi, TargetNbPs);
+      MemNSetBitFieldNb (NBPtr, BFSwNbPstateLoDis, 1);
+
+      // 5.Wait for D18F5x174[CurNbPstate] to equal the target NB P-state.
+      MemNPollBitFieldNb (NBPtr, BFCurNbPstate, TargetNbPs, PCI_ACCESS_TIMEOUT, FALSE);
+    }
+
+    // When NB frequency change succeeds, TSC rate may have changed.
+    // We need to update TSC rate
+    FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
+    // Switch MemPstate context if the current MemPstate does not sync with MemPstate context
+    if (MemNGetBitFieldNb (NBPtr, BFCurMemPstate) != MemNGetBitFieldNb (NBPtr, BFMemPsSel)) {
+      MemNChangeMemPStateContextNb (NBPtr, MemNGetBitFieldNb (NBPtr, BFCurMemPstate));
+    }
+  } else {
+    // Cannot find a supported NB Pstate to switch to
+    // Release NB Pstate force by restoring NbPsCtl register
+    NBPtr->FamilySpecificHook[ReleaseNbPstate] (NBPtr, NBPtr);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tRelease NB Pstate force\n");
+    return FALSE;
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends an MRS command for Unb
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendMrsCmdUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 MrsBank;
+  UINT16 MrsBuffer;
+  UINT8 MrsChipSel;
+
+  MemNSetASRSRTNb (NBPtr);
+  MemNSwapBitsUnb (NBPtr);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x\n",
+              (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 0x7),
+              (MemNGetBitFieldNb (NBPtr, BFMrsBank) & 0x7),
+              (MemNGetBitFieldNb (NBPtr, BFMrsAddress) & 0x3FFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+
+  // Send MRS buffer if memory pstate is supported and enabled
+  if (NBPtr->MemPstateStage != 0) {
+    MrsChipSel = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 0x7);
+    // Only user even rank MRS to set MRS buffer
+    if ((MrsChipSel & 1) == 0) {
+      MrsBank = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMrsBank) & 0x7);
+      MrsBuffer = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMrsAddress) & 0xFFFF);
+      if (MrsBank == 0) {
+        MrsBuffer &= 0xFEFF;
+        MemNSetBitFieldNb (NBPtr, BFMxMr0, MrsBuffer);
+      } else if (MrsBank == 1) {
+        MemNSetBitFieldNb (NBPtr, BFMxMr1, MrsBuffer);
+      } else if (MrsBank == 2) {
+        MemNSetBitFieldNb (NBPtr, BFMxMr2, MrsBuffer);
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns MR0[CL] value with table driven support
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return       MR0[CL] value
+ */
+UINT32
+MemNGetMR0CLTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function performs MaxRdLat training for slot 1
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  TestAddrRJ16 - Test address
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNSlot1MaxRdLatTrainClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *TestAddrRJ16
+  )
+{
+  UINT8  DummyBuffer[8];
+  UINT16 MaxLatDly;
+  UINT8  i;
+
+  // Perform slot1 specific training:
+  // A.Program D18F2x[1,0]78[SlotSel]=1. Force read CAS to fifo slot1 for training.
+  // B.Program D18F2x[1,0]78[MaxRdLatency] = TrainedMaxRdLatency. Set to last slot0 value that passed.
+  // C.Read the DIMM test addresses.
+  // D.Compare the values read against the pattern written.
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1: \n");
+  MemNSetBitFieldNb (NBPtr, BFSlotSel, 1);
+
+  MaxLatDly = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMaxLatency) + 1);  // Add 1 to get back to the last passing value
+  MemNSetBitFieldNb (NBPtr, BFMaxLatency, MaxLatDly);
+
+  for (i = 0; i < 100; i++) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly);
+
+    NBPtr->ReadPattern (NBPtr, DummyBuffer, *(UINT32*)TestAddrRJ16, 6);
+
+    if (NBPtr->CompareTestPattern (NBPtr, DummyBuffer, DummyBuffer, 6 * 64) == 0xFFFF) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "  P");
+      break;
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+  }
+
+  if (i < 100) {
+    MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 0);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFMaxSkipErrTrain, 0);
+
+  return TRUE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function programs dram power management timing related registers
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return    none
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNDramPowerMngTimingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  STATIC CONST UINT8 Tckesr[] = {4, 4, 4, 5, 5, 6, 7, 2, 2};
+  UINT8 Tck;
+
+  // These timings are based on DDR3 spec
+  // Tcksrx = max(5 nCK, 10 ns)
+  Tck = (UINT8) MAX (5, (MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 10)));
+  MemNSetBitFieldNb (NBPtr, BFTcksrx, MIN (0xE, MAX (Tck, 2)));
+
+  // Tcksre = max(5 nCK, 10 ns)
+  MemNSetBitFieldNb (NBPtr, BFTcksre, MIN (0x27, MAX (Tck, 5)));
+
+  // Tckesr = tCKE(min) + 1 nCK
+  //                               tCKE(min)
+  // DDR-667   7.5ns = 3nCk     max(3nCK, 7.5ns)   + 1 = 3nCK + 1nCK = 4nCK
+  // DDR-800   7.5ns = 3nCk     max(3nCK, 7.5ns)   + 1 = 3nCK + 1nCK = 4nCK
+  // DDR-1066  5.625ns = 3nCK   max(3nCK, 5.625ns) + 1 = 3nCL + 1nCK = 4nCK
+  // DDR-1333  5.625ns = 4nCK   max(3nCK, 4nCK)    + 1 = 4nCK + 1nCK = 5nCK
+  // DDR-1600  5ns = 4nCK       max(3nCK, 4nCK)    + 1 = 4nCK + 1nCK = 5nCK
+  // DDR-1866  5ns = 5nCK       max(3nCK, 5nCK)    + 1 = 5nCK + 1nCK = 6nCK
+  // DDR-2133  5ns = 6nCK       max(3nCK, 6nCK)    + 1 = 6nCK + 1nCK = 7nCK
+  ASSERT (((NBPtr->DCTPtr->Timings.Speed / 133) >= 2) && ((NBPtr->DCTPtr->Timings.Speed / 133) <= 10));
+  MemNSetBitFieldNb (NBPtr, BFTckesr, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 2]);
+
+  // Tpd = tCKE(min)
+  MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 2] - 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       The function resets Rcv Fifo
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Dummy - Dummy parameter
+ *
+ */
+
+VOID
+MemTResetRcvFifoUnb (
+  IN OUT   struct _MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dummy
+  )
+{
+  // Program D18F2x9C_x0000_0050_dct[1:0]=00000000h
+  MemNSetBitFieldNb (TechPtr->NBPtr, BFRstRcvFifo, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the memory width
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Memory width
+ */
+
+UINT32
+MemNGetMemoryWidthUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT      *MCTPtr;
+  MEM_SHARED_DATA *SharedPtr;
+
+  MCTPtr    = NBPtr->MCTPtr;
+  SharedPtr = NBPtr->SharedPtr;
+
+  return 64 + ((SharedPtr->AllECC && MCTPtr->Status[SbEccDimms]) ? 8 : 0);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c
new file mode 100644
index 0000000000..2d9d23fac8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c
@@ -0,0 +1,1418 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnfeat.c
+ *
+ * Common Northbridge features
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "PlatformMemoryConfiguration.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CL_CONT_READ  32
+#define MAX_CL_CONT_WRITE 32
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemNContWritePatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNContReadPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNGenHwRcvEnReadsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  );
+
+UINT16
+STATIC
+MemNCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+UINT16
+STATIC
+MemNInsDlyCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+VOID
+STATIC
+MemNContWritePatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNContReadPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNGenHwRcvEnReadsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  );
+
+BOOLEAN
+STATIC
+MemNBeforeMemClrClientNb (
+  IN OUT   MEM_NB_BLOCK  *NBPtr,
+  IN       VOID *UnUsed
+  );
+
+VOID
+STATIC
+MemNGenHwRcvEnReadsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  );
+
+VOID
+STATIC
+MemNEnableInfiniteWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNDisableInfiniteWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitCPGNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitCPGClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitCPGUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function assigns read/write function pointers to CPG read/write modules.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNInitCPGNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->WritePattern = MemNContWritePatternNb;
+  NBPtr->ReadPattern = MemNContReadPatternNb;
+  NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions of HW Rx En Training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function disables member functions of Hw Rx En Training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNDisableDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->MemNPrepareRcvrEnDlySeed = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes 9 or 18 cache lines continuously using GH CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Pattern - Array of bytes that will be written to DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+VOID
+STATIC
+MemNContWritePatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  UINT16 ClDiff;
+  if (ClCount > MAX_CL_CONT_WRITE) {
+    ClDiff = ClCount - MAX_CL_CONT_WRITE;
+    ClCount = MAX_CL_CONT_WRITE;
+  } else {
+    ClDiff = 0;
+  }
+
+  // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst.
+  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount);
+
+  // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set
+  // again), all the writes are written to DRAM.
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+
+  // Flush out prior writes by setting F2x11C[FlushWr].
+  MemNSetBitFieldNb (NBPtr, BFFlushWr, 1);
+  // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed.
+  while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {}
+
+  // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting.
+  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F);
+
+  if (ClDiff > 0) {
+    MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function reads 9 or 18 cache lines continuously using GH CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+STATIC
+MemNContReadPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  BOOLEAN DisAutoRefresh;
+  UINT16 ClDiff;
+  if (ClCount > MAX_CL_CONT_READ) {
+    ClDiff = ClCount - MAX_CL_CONT_READ;
+    ClCount = MAX_CL_CONT_READ;
+  } else {
+    ClDiff = 0;
+  }
+
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+
+  // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads.
+  // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64
+  // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices
+  // to change to an 8-beat burst length and then to restore the desired burst length after training
+  // is complete.
+
+  if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) {
+    DisAutoRefresh = FALSE;
+    // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1.
+    // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description.
+    MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+    // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0);  // ForceAutoPchg is 0 by default.
+    MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+  } else {
+    DisAutoRefresh = TRUE;
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+
+  // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the
+  // training sequence.
+  MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1);
+
+  // 6. BIOS sets F2x11C[PrefDramTrainMode] bit.
+  // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor
+  // table (removing any existing prefetch stride patterns).
+  MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1);
+
+  // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes.
+  // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS
+  // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must
+  // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary.
+  // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to
+  // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears
+  // F2x11C[PrefDramTrainMode].
+  MemUDummyCLRead (Address);
+  MemUDummyCLRead (Address + 0x40);
+  if (NBPtr->IsSupported[CheckDummyCLRead]) {
+    MemUDummyCLRead (Address + 0x80);
+  }
+  // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after
+  // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines
+  // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches
+  // and read the data from the prefetch buffer.
+  while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {}
+  MemUReadCachelines (Buffer, Address, ClCount);
+
+  // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and
+  // F2x[1, 0]90[BurstLength32].
+  if (!DisAutoRefresh) {
+    MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
+    MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
+  }
+
+  if (ClDiff > 0) {
+    MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function generates a continuous burst of reads during HW RcvEn training.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Address - System Address [47:16]
+ *
+ */
+VOID
+STATIC
+MemNGenHwRcvEnReadsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  )
+{
+  UINT8  TempBuffer[12 * 64];
+  UINT8  BurstCount;
+
+  for (BurstCount = 0; BurstCount < 10; BurstCount++) {
+    NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12);
+    NBPtr->FlushPattern (NBPtr, Address, 12);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes cache lines continuously using TCB CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Pattern - Array of bytes that will be written to DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+VOID
+STATIC
+MemNContWritePatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  UINT32 PatternHash;
+  UINT32 *DwordPtr;
+  UINT16 i;
+  UINT16 j;
+  UINT16 Multiplier;
+
+  Multiplier = 1;
+
+  // 1. Program D18F2x1C0[WrDramTrainMode]=1.
+  MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1);
+
+  PatternHash = ClCount << 24;
+  for (i = 0; i < 3; i ++) {
+    PatternHash |= (Pattern[i * ClCount * 24 + 9] << (8 * i));
+  }
+  if (NBPtr->CPGInit != PatternHash) {
+
+    if (ClCount == 3) {
+      // Double pattern length for MaxRdLat training
+      Multiplier = 2;
+    }
+
+    // If write training buffer has not been initialized, initialize it
+    // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
+    MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier);
+
+    // 3. Program D18F2x1D0[WrTrainBufAddr]=000h.
+    MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
+
+    // 4. Successively write each dword of the training pattern to D18F2x1D4.
+    DwordPtr = (UINT32 *) Pattern;
+    for (j = 0; j < Multiplier; j++) {
+      for (i = 0; i < (ClCount * 16); i++) {
+        MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]);
+      }
+    }
+
+    NBPtr->CPGInit = PatternHash;
+  }
+
+  // 5. Program D18F2x1D0[WrTrainBufAddr]=000h
+  MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
+
+  // 6. Program the DRAM training address
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6));
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3);
+
+  // 7. Program D18F2x1C0[WrTrainGo]=1.
+  MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1);
+
+  // 8. Wait for D18F2x1C0[WrTrainGo]=0.
+  while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {}
+
+  // 9. Program D18F2x1C0[WrDramTrainMode]=0.
+  MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function reads cache lines continuously using TCB CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+STATIC
+MemNContReadPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  UINT16 Multiplier;
+
+  Multiplier = 1;
+  if (ClCount == 3) {
+    // Double pattern length for MaxRdLat training
+    Multiplier = 2;
+  }
+
+  // 1. Program D18F2x1C0[RdDramTrainMode]=1.
+  MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1);
+
+  // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
+  MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier);
+
+  // 3. Program the DRAM training address as follows:
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6));
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3);
+
+  // 4. Program D18F2x1D0[WrTrainBufAddr]=000h
+  MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
+
+  // 5. Program D18F2x1C0[RdTrainGo]=1.
+  MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1);
+
+  // 6. Wait for D18F2x1C0[RdTrainGo]=0.
+  while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {}
+
+  // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2].
+  // This step will be accomplished in Compare routine.
+
+  // 8. Program D18F2x1C0[RdDramTrainMode]=0.
+  MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function generates a continuous burst of reads during HW RcvEn training.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Address - System Address [47:16]
+ *
+ */
+VOID
+STATIC
+MemNGenHwRcvEnReadsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  )
+{
+  UINT8  TempBuffer[64];
+  UINT8  Count;
+
+  for (Count = 0; Count < 3; Count++) {
+    NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function assigns read/write function pointers to CPG read/write modules.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNInitCPGClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->WritePattern = MemNContWritePatternClientNb;
+  NBPtr->ReadPattern = MemNContReadPatternClientNb;
+  NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb;
+  NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb;
+  NBPtr->FamilySpecificHook[BeforeMemClr] = MemNBeforeMemClrClientNb;
+  NBPtr->CPGInit = 0;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and
+ *       return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @return  PASS - Bitmap of results of comparison
+ */
+
+UINT16
+STATIC
+MemNCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and
+ *       return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @retval  Bitmap of results of comparison
+ */
+UINT16
+STATIC
+MemNInsDlyCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function calculates RcvEn seed value for each rank
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNPrepareRcvrEnDlySeedNb (
+  IN OUT   MEM_NB_BLOCK  *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  DIE_STRUCT *MCTPtr;
+  UINT16 SeedTotal;
+  UINT16 SeedFine;
+  UINT16 SeedGross;
+  UINT16 SeedPreGross;
+  UINT16 SeedTotalPreScaling;
+  UINT8  ByteLane;
+  UINT16 Speed;
+  UINT16 PlatEst;
+  UINT8 ChipSel;
+  UINT8 Pass;
+  UINT16 *PlatEstSeed;
+  UINT16 SeedValue[9];
+  UINT16 SeedTtl[9];
+  UINT16 SeedPre[9];
+
+  TechPtr = NBPtr->TechPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  SeedTotalPreScaling = 0;
+  ChipSel = TechPtr->ChipSel;
+  Pass = TechPtr->Pass;
+
+  for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+    TechPtr->Bytelane = ByteLane;
+    if (Pass == 1) {
+      // Get platform override seed
+      PlatEstSeed = (UINT16 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_RXEN_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID, ChipSel >> 1,
+                                                    &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+      // For Pass1, BIOS starts with the delay value obtained from the first pass of write
+      // levelization training that was done in DDR3 Training and add a delay value of 3Bh.
+      PlatEst = 0x3B;
+      NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst);
+      PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst);
+      SeedTotal = ChannelPtr->WrDqsDlys[(ChipSel / NBPtr->CsPerDelay) * TechPtr->DlyTableWidth () + ByteLane] + PlatEst;
+      SeedValue[ByteLane] = PlatEst;
+    } else {
+      // For Pass2
+      // SeedTotalPreScaling = (the total delay values in D18F2x[1,0]9C_x0000_00[24:10] from pass 1 of
+      //  DQS receiver enable training) - 20h. Subtract 1UI to get back to preamble left edge.
+      if ((((ChipSel & 1) == 0) || (NBPtr->CsPerDelay == 1)) && NBPtr->FamilySpecificHook[TrainingNibbleZero] (NBPtr, &ChipSel)) {
+        // Save Seed for odd CS SeedTotalPreScaling RxEn Value
+        TechPtr->PrevPassRcvEnDly[ByteLane] = ChannelPtr->RcvEnDlys[(ChipSel / NBPtr->CsPerDelay) * TechPtr->DlyTableWidth () + ByteLane];
+      }
+      NBPtr->FamilySpecificHook[OverridePrevPassRcvEnDly] (NBPtr, &TechPtr->PrevPassRcvEnDly[ByteLane]);
+      SeedTotalPreScaling = TechPtr->PrevPassRcvEnDly[ByteLane] - 0x20;
+      // SeedTotal = SeedTotalPreScaling*target frequency/lowest supported frequency.
+      SeedTotal = (UINT16) (((UINT32) SeedTotalPreScaling * Speed) / TechPtr->PrevSpeed);
+      NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] (NBPtr, &SeedTotal);
+    }
+    SeedTtl[ByteLane] = SeedTotal;
+
+    // SeedGross = SeedTotal DIV 32.
+    SeedGross = SeedTotal >> 5;
+    // SeedFine = SeedTotal MOD 32.
+    SeedFine = SeedTotal & 0x1F;
+    // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32.
+    // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32.
+    // Use SeedGrossPass1 to determine SeedPreGrossPass1:
+
+    if ((SeedGross & 0x1) != 0) {
+      //if SeedGross is odd
+      SeedPreGross = 1;
+    } else {
+      //if SeedGross is even
+      SeedPreGross = 2;
+    }
+    // (SeedGross - SeedPreGross)
+    TechPtr->DiffSeedGrossSeedPreGross[ByteLane] = (SeedGross - SeedPreGross) << 5;
+
+    //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 with SeedPreGrossPass1
+    //and SeedFinePass1 from the preceding steps.
+
+    NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane), (SeedPreGross << 5) | SeedFine);
+    SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine;
+
+    NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane), SeedGross << 5);
+  }
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    if (Pass == 1) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: ");
+      for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+        IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]);
+      }
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: ");
+    for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t  SeedPRE: ");
+    for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+  );
+
+  NBPtr->FamilySpecificHook[RegAccessFence] (NBPtr, NULL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of MEMCLKs
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *      @param[in] MemClkCount - Number of MEMCLKs
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNWaitXMemClksNb (
+  IN OUT   MEM_NB_BLOCK  *NBPtr,
+  IN       UINT32 MemClkCount
+  )
+{
+  MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Issues dummy TCB write read to zero out CL that is used for MemClr
+ *      @param[in,out] *NBPtr  - Pointer to the MEM_NB_BLOCK
+ *      @param[in,out] *UnUsed - unused
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNBeforeMemClrClientNb (
+  IN OUT   MEM_NB_BLOCK  *NBPtr,
+  IN       VOID *UnUsed
+  )
+{
+  UINT8 Pattern[64];
+  UINT8 i;
+
+  for (i = 0; i < 64; i++) {
+    Pattern[i] = 0;
+  }
+
+  MemNContWritePatternClientNb (NBPtr, 0x20, Pattern, 1);
+  MemNContReadPatternClientNb (NBPtr, Pattern, 0x20, 1);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function uses the PRBS generator in the DCT to send a DDR Activate command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]        ChipSelect - Chip select 0-7
+ *     @param[in]        Bank - Bank Address 0-7
+ *     @param[in]        RowAddress - Row Address [17:0]
+ *
+ */
+
+VOID
+MemNRrwActivateCmd (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 Bank,
+  IN       UINT32 RowAddress
+  )
+{
+  // Set Chip select
+  MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << ChipSelect));
+  // Set Bank Address
+  MemNSetBitFieldNb (NBPtr, BFCmdBank, Bank);
+  // Set Row Address
+  MemNSetBitFieldNb (NBPtr, BFCmdAddress, RowAddress);
+  // Send the command
+  MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1);
+  // Wait for command complete
+  MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  // Wait 75 MEMCLKs
+  NBPtr->WaitXMemClks (NBPtr, 75);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function uses the PRBS generator in the DCT to send a DDR Precharge
+ *     or Precharge All command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]        ChipSelect - Chip select 0-7
+ *     @param[in]        Bank - Bank Address 0-7, PRECHARGE_ALL_BANKS = Precharge All
+ *
+ *
+ */
+
+VOID
+MemNRrwPrechargeCmd (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 Bank
+  )
+{
+  // Wait 25 MEMCLKs
+  NBPtr->WaitXMemClks (NBPtr, 25);
+  // Set Chip select
+  NBPtr->SetBitField (NBPtr, BFCmdChipSelect, (1 << ChipSelect));
+  if (Bank == PRECHARGE_ALL_BANKS) {
+    // Set Row Address, bit 10
+    NBPtr->SetBitField (NBPtr, BFCmdAddress,  NBPtr->GetBitField (NBPtr, BFCmdAddress) | (1 << 10) );
+  } else {
+    // Clear Row Address, bit 10
+    NBPtr->SetBitField (NBPtr, BFCmdAddress,  NBPtr->GetBitField (NBPtr, BFCmdAddress) & (~(1 << 10)) );
+    // Set Bank Address
+    NBPtr->SetBitField (NBPtr, BFCmdBank, Bank);
+  }
+  // Send the command
+  NBPtr->SetBitField (NBPtr, BFSendPchgCmd, 1);
+  // Wait for command complete
+  NBPtr->PollBitField (NBPtr, BFSendPchgCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  // Wait 25 MEMCLKs
+  NBPtr->WaitXMemClks (NBPtr, 25);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function generates a continuous burst of reads for HW RcvEn
+ *        training using the Unified Northbridge Reliable Read/Write Engine.
+ *
+ *     @param[in,out] NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Address - Unused by this function
+ *
+ */
+VOID
+STATIC
+MemNGenHwRcvEnReadsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  )
+{
+  VOID  *DummyPtr;
+  DummyPtr = NULL;
+  //
+  // Issue Stream of Reads from the Target Rank
+  //
+  NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function generates a continuous stream of reads from DRAM using the
+ *       Unified Northbridge Reliable Read/Write Engine.
+ *
+ *     @param[in,out] NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out] Buffer  - Unused by this function
+ *     @param[in]     Address - Unused by this function
+ *     @param[in]     ClCount - Number of cache lines to read
+ *
+ *     Assumptions:
+ *
+ *
+ *
+ */
+
+VOID
+MemNContReadPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  RRW_SETTINGS *Rrw;
+  UINT8 CmdTgt;
+  UINT8 ChipSel;
+
+  TechPtr = NBPtr->TechPtr;
+  Rrw = &NBPtr->RrwSettings;
+
+  ChipSel = TechPtr->ChipSel;
+  CmdTgt = Rrw->CmdTgt;
+  //
+  // Wait for RRW Engine to be ready and turn it on
+  //
+  NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1);
+  //
+  // Depending upon the Cmd Target, send Row Activate and set Chipselect
+  //   for the Row or Rows that will be used
+  //
+  MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA);
+  NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel);
+  if (CmdTgt == CMD_TGT_AB) {
+    MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB);
+    NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel);
+  }
+  // Set Comparison Masks
+  NBPtr->SetBitField (NBPtr, BFDramDqMaskLow, Rrw->CompareMaskLow);
+  NBPtr->SetBitField (NBPtr, BFDramDqMaskHigh, Rrw->CompareMaskHigh);
+  //
+  // If All Dimms are ECC Capable Test ECC. Otherwise, mask it off
+  //
+  NBPtr->SetBitField (NBPtr, BFDramEccMask, (NBPtr->MCTPtr->Status[SbEccDimms] == TRUE) ? Rrw->CompareMaskEcc : 0xFF);
+  //
+  // Program the PRBS Seed
+  //
+  NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed);
+  //
+  // Set the Command Count
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount);
+  //
+  // Program the Starting Address
+  //
+  NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA);
+  NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA);
+  if (CmdTgt == CMD_TGT_AB) {
+    NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB);
+    NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB);
+  }
+  //
+  // Reset All Errors and Disable StopOnErr
+  //
+  NBPtr->SetBitField (NBPtr, BFResetAllErr, 1);
+  NBPtr->SetBitField (NBPtr, BFStopOnErr, 0);
+  //
+  // Program the CmdTarget
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt);
+  //
+  // Set CmdType to read
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_READ);
+  //
+  // Start the Commands
+  //
+  AGESA_TESTPOINT (TpProcMemContinPatternGenRead, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
+  //
+  // Commands have started, wait for the reads to complete then clear the command
+  //
+  NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
+  //
+  // Send the Precharge All Command
+  //
+  MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS);
+  //
+  // Turn Off the RRW Engine
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function generates a continuous stream of writes to DRAM using the
+ *       Unified Northbridge Reliable Read/Write Engine.
+ *
+ *     @param[in,out] NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out] Address - Unused by this function
+ *     @param[in]     Pattern - Unused by this function
+ *     @param[in]     ClCount - Number of cache lines to write
+ *
+ */
+
+VOID
+MemNContWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  RRW_SETTINGS *Rrw;
+  UINT8 CmdTgt;
+  UINT8 ChipSel;
+
+  TechPtr = NBPtr->TechPtr;
+  Rrw = &NBPtr->RrwSettings;
+
+  ChipSel = TechPtr->ChipSel;
+  CmdTgt = Rrw->CmdTgt;
+  //
+  // Wait for RRW Engine to be ready and turn it on
+  //
+  NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1);
+  //
+  // Depending upon the Cmd Target, send Row Activate and set Chipselect
+  //   for the Row or Rows that will be used
+  //
+  MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA);
+  NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel);
+  if (CmdTgt == CMD_TGT_AB) {
+    MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB);
+    NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel);
+  }
+  //
+  // Program the PRBS Seed
+  //
+  NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed);
+  //
+  // Set the Command Count
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount);
+  //
+  // Program the Starting Address
+  //
+  NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA);
+  NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA);
+  if (CmdTgt == CMD_TGT_AB) {
+    NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB);
+    NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB);
+  }
+  //
+  // Program the CmdTarget
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt);
+  //
+  // Set CmdType to Write
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE);
+  //
+  // Start the Commands
+  //
+  AGESA_TESTPOINT (TpProcMemContinPatternGenWrite, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
+  //
+  // Commands have started, wait for the writes to complete then clear the command
+  //
+  // Wait for TestStatus = 1 and CmdSendInProg = 0.
+  NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
+  //
+  // Send the Precharge All Command
+  //
+  MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS);
+  //
+  // Turn Off the RRW Engine
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function checks the Error status bits for comparison results
+ *
+ *     @param[in,out]   *NBPtr    - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  -  Not used in this implementation
+ *     @param[in]       Pattern[] - Not used in this implementation
+ *     @param[in]       ByteCount - Not used in this implementation
+ *
+ *     @return  PASS - Bitmap of results of comparison
+ */
+
+UINT16
+MemNCompareTestPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+
+
+  UINT16 i;
+  UINT16 Pass;
+  UINT8 ChipSel;
+  UINT8 ColumnCount;
+  UINT8* FailingBitMaskPtr;
+  UINT8 FailingBitMask[9];
+  UINT32 NibbleErrSts;
+
+  ChipSel = NBPtr->TechPtr->ChipSel;
+  ColumnCount = NBPtr->ChannelPtr->ColumnCount;
+  // Calculate Failing Bitmask pointer
+  FailingBitMaskPtr = &(NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel)]);
+
+  //
+  // Get Failing bit data
+  //
+  *((UINT32*)FailingBitMask) = NBPtr->GetBitField (NBPtr, BFDQErrLow);
+  *((UINT32*)&FailingBitMask[4]) = NBPtr->GetBitField (NBPtr, BFDQErrHigh);
+  FailingBitMask[8] = (UINT8)NBPtr->GetBitField (NBPtr, BFEccErr);
+
+  Pass = 0x0000;
+  //
+  // Get Comparison Results - Convert Nibble Masks to Byte Masks
+  //
+  NibbleErrSts = NBPtr->GetBitField (NBPtr, BFNibbleErrSts);
+
+  for (i = 0; i < ColumnCount ; i++) {
+    Pass |= ((NibbleErrSts & 0x03) > 0 ) ? (1 << i) : 0;
+    NibbleErrSts >>= 2;
+    FailingBitMaskPtr[i] = FailingBitMask[i];
+  }
+  Pass = ~Pass;
+  return Pass;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function checks the Error status bits for offset comparison results
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @retval  Bitmap of results of comparison
+ */
+UINT16
+STATIC
+MemNInsDlyCompareTestPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  UINT16 i;
+  UINT16 Pass;
+  UINT8 ColumnCount;
+  UINT32 NibbleErr180Sts;
+
+  ColumnCount = NBPtr->ChannelPtr->ColumnCount;
+  Pass = 0x0000;
+  //
+  // Get Comparison Results - Convert Nibble Masks to Byte Masks
+  //
+  NibbleErr180Sts = NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts);
+
+  for (i = 0; i < ColumnCount ; i++) {
+    Pass |= ((NibbleErr180Sts & 0x03) > 0 ) ? (1 << i) : 0;
+    NibbleErr180Sts >>= 2;
+  }
+  Pass = ~Pass;
+
+  return Pass;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function assigns read/write function pointers to CPG read/write modules.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNInitCPGUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->WritePattern = MemNContWritePatternUnb;
+  NBPtr->ReadPattern = MemNContReadPatternUnb;
+  NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsUnb;
+  NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet;
+  NBPtr->TrainingPatternInit = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess;
+  NBPtr->TrainingPatternFinalize = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternUnb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternUnb;
+  NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb;
+  NBPtr->EnableInfiniteWritePattern = MemNEnableInfiniteWritePatternUnb;
+  NBPtr->DisableInfiniteWritePattern = MemNDisableInfiniteWritePatternUnb;
+  NBPtr->CPGInit = 0;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function generates a continuous stream of writes infinite writes to DRAM using the
+ *       Unified Northbridge Reliable Read/Write Engine.
+ *
+ *     @param[in,out] NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNEnableInfiniteWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  RRW_SETTINGS *Rrw;
+  UINT8 CmdTgt;
+  UINT8 ChipSel;
+  TechPtr = NBPtr->TechPtr;
+  Rrw = &NBPtr->RrwSettings;
+  ChipSel = TechPtr->ChipSel;
+  CmdTgt = Rrw->CmdTgt;
+
+  // Ensure that DisAutoRefresh and ZqCals are disabled during the use of RRWM
+  if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) {
+    NBPtr->OrigDisAutoRefreshState = FALSE;
+    MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+    MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+  } else {
+    NBPtr->OrigDisAutoRefreshState = TRUE;
+  }
+
+
+
+  //
+  // Enable PRBS
+  //
+
+  //
+  // Wait for RRW Engine to be ready and turn it on
+  //
+  NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1);
+  //
+  // Depending upon the Cmd Target, send Row Activate and set Chipselect
+  //   for the Row or Rows that will be used
+  //
+  MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA);
+  NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel);
+  //
+  // Program the PRBS Seed
+  //
+  NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed);
+  //
+  // Set the Command Count
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdCount, 0);
+  //
+  // Program the Starting Address
+  //
+  NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA);
+  NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA);
+  //
+  // Program the CmdTarget
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdTgt, CMD_TGT_A);
+  //
+  // Set CmdType to write
+  //
+  NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE);
+  //
+  // Start the Commands
+  //
+  NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function disables the infinite stream of writes to DRAM using the
+ *       Unified Northbridge Reliable Read/Write Engine.
+ *
+ *     @param[in,out] NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNDisableInfiniteWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  //
+  // Disable PRBS
+  NBPtr->SetBitField (NBPtr, BFCmdCount, 1);
+  //Wait for TestStatus = 1 and CmdSendInProg = 0
+  NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
+  //
+  //
+  // Turn Off the RRW Engine
+  //
+  MemNRrwPrechargeCmd (NBPtr, NBPtr->TechPtr->ChipSel, PRECHARGE_ALL_BANKS);
+  NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
+  //
+  // Restore DisAutoRefresh and ZQCals to original state
+  //
+  if (!NBPtr->OrigDisAutoRefreshState) {
+    MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
+    MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
+  }
+
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function is an empty function used to intialize FamilySpecificHook array
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return  TRUE - always
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNDefaultFamilyHookNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c
new file mode 100644
index 0000000000..4ae0fac85c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c
@@ -0,0 +1,359 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnflow.c
+ *
+ * Common Northbridge initializer flow for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE
+/* features */
+#include "mftds.h"
+
+extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemNInitDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNCleanupDctRegsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNGetPORFreqLimitTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the MCT with initial values
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS)
+ *     @return          FALSE - AGESA_FATAL error occurred
+ */
+
+BOOLEAN
+MemNInitMCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  BOOLEAN Flag;
+  ID_INFO CallOutIdInfo;
+
+  TechPtr = NBPtr->TechPtr;
+  // Switch Tech functions for Nb
+  NBPtr->TechBlockSwitch (NBPtr);
+  // Start Memory controller initialization sequence
+  Flag = FALSE;
+  if (TechPtr->DimmPresence (TechPtr)) {
+    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));
+    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {
+      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));
+      if (TechPtr->SpdCalcWidth (TechPtr)) {
+        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));
+        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {
+          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+            NBPtr->SwitchDCT (NBPtr, Dct);
+
+            Flag |= MemNInitDCTNb (NBPtr);
+          }
+
+          if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {
+            MemFInitTableDrive (NBPtr, MTBeforeDInit);
+            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+            CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId;
+            CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId;
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId);
+            AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr);
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 :
+                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 :
+                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);
+            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));
+            NBPtr->StartupDCT (NBPtr);
+          }
+        }
+      }
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the platform specific block for families that support
+ *      table driven form factor
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_SUCCESS
+ */
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->PsPtr->MemPDoPs = MemPPSCFlow;
+    NBPtr->PsPtr->MemPGetPORFreqLimit = MemNGetPORFreqLimitTblDrvNb;
+    NBPtr->PsPtr->MemPGetPass1Seeds = MemPGetPSCPass1Seed;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function selects appropriate Tech functions for the NB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNTechBlockSwitchNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Specify Dimm-Byte training for Nb
+  MemTDimmByteTrainInit (TechPtr);
+
+  // Filter included for RcvrEn training.
+  // note: If you'd like to drop the filter, you have to comment out these two lines together.
+  TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3;
+  TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the DCT with initial values
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Error did not occur
+ *     @return          FALSE - Error occurred
+ */
+
+BOOLEAN
+STATIC
+MemNInitDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  TechPtr = NBPtr->TechPtr;
+  TechPtr->SetDramMode (TechPtr);
+
+  if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) {
+    if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) {
+      NBPtr->DisableDCT (NBPtr);
+    } else {
+      MemNCleanupDctRegsNb (NBPtr);
+      if (TechPtr->AutoCycTiming (TechPtr)) {
+        if (TechPtr->SpdSetBanks (TechPtr)) {
+          if (NBPtr->StitchMemory (NBPtr)) {
+            // if all dimms on a DCT are disabled, the DCT needs to be disabled.
+            if (NBPtr->DCTPtr->Timings.CsEnabled != 0) {
+              if (NBPtr->AutoConfig (NBPtr)) {
+                if (NBPtr->PlatformSpec (NBPtr)) {
+                  return TRUE;
+                }
+              }
+            } else {
+              NBPtr->DisableDCT (NBPtr);
+            }
+          }
+        }
+      }
+    }
+  }
+  return FALSE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function clears DCT registers
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNCleanupDctRegsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BIT_FIELD_NAME BitField;
+
+  for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) {
+    MemNSetBitFieldNb (NBPtr, BitField, 0);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This is function gets the POR speed limit for families supports table driven form factor
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNGetPORFreqLimitTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+
+  i = 0;
+  while (memPlatSpecFlowArray[i] != NULL) {
+    if ((memPlatSpecFlowArray[i])->MaxFrequency (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+      break;
+    }
+    i++;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c
new file mode 100644
index 0000000000..ad2c01e294
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c
@@ -0,0 +1,1313 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnmct.c
+ *
+ * Northbridge Common MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MNMCT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _16MB_RJ16  0x0100
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNSetMTRRrangeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Base,
+  IN OUT   UINT32 *LimitPtr,
+  IN       UINT32 MtrrAddr,
+  IN       UINT8 MtrrType
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     Get max frequency from OEM platform definition, from
+ *     any user override (limiting) of max frequency, and
+ *     from any Si Revision Specific information.  Return
+ *     the least of these three in DIE_STRUCT.Timings.TargetSpeed.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSyncTargetSpeedNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT16 DdrMaxRateTab[] = {
+    UNSUPPORTED_DDR_FREQUENCY,
+    DDR1600_FREQUENCY,
+    DDR1333_FREQUENCY,
+    DDR1066_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR667_FREQUENCY,
+    DDR533_FREQUENCY,
+    DDR400_FREQUENCY
+  };
+
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT16 MinSpeed;
+  UINT16 DdrMaxRate;
+  DCT_STRUCT *DCTPtr;
+  USER_MEMORY_TIMING_MODE *ChnlTmgMod;
+  USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET];
+  MEMORY_BUS_SPEED MemClkFreq;
+  MEMORY_BUS_SPEED ProposedFreq;
+
+  ASSERT (NBPtr->DctCount <= sizeof (Mode));
+  MinSpeed = 16000;
+  DdrMaxRate = 16000;
+  if (NBPtr->IsSupported[CheckMaxDramRate]) {
+    // Check maximum DRAM data rate that the processor is designed to support.
+    DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)];
+    NBPtr->FamilySpecificHook[GetDdrMaxRate] (NBPtr, &DdrMaxRate);
+    IDS_OPTION_HOOK (IDS_SKIP_FUSED_MAX_RATE, &DdrMaxRate, &NBPtr->MemPtr->StdHeader);
+  }
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    // Check if input user time mode is valid or not
+    ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) ||
+        (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) ||
+        (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO));
+    Mode[Dct] = NBPtr->RefPtr->UserTimingMode;
+    // Check if input clock value is valid or not
+    ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
+      (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) :
+      (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY));
+    MemClkFreq = NBPtr->RefPtr->MemClockValue;
+    if (DCTPtr->Timings.DctDimmValid != 0) {
+      Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0);
+      ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel, 0,
+                                                                    &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+      if (ChnlTmgMod != NULL) {
+        // Check if input user timing mode is valid or not
+        ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) ||
+          (ChnlTmgMod[0] != TIMING_MODE_AUTO));
+        if (ChnlTmgMod[0] != TIMING_MODE_AUTO) {
+          Mode[Dct] = ChnlTmgMod[0];
+          // Check if input clock value is valid or not
+          ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
+            ((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) :
+            ((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY));
+          MemClkFreq = (MEMORY_BUS_SPEED)ChnlTmgMod[1];
+        }
+      }
+
+      ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit;
+      if (Mode[Dct] == TIMING_MODE_LIMITED) {
+        if (MemClkFreq < ProposedFreq) {
+          ProposedFreq = MemClkFreq;
+        }
+      } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
+        ProposedFreq = MemClkFreq;
+      }
+
+      if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
+        DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq;
+      } else {
+        // "limit" mode
+        if (DCTPtr->Timings.TargetSpeed > ProposedFreq) {
+          DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq;
+        }
+      }
+
+      NBPtr->MemNCapSpeedBatteryLife (NBPtr);
+
+      if (DCTPtr->Timings.TargetSpeed > DdrMaxRate) {
+        if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
+          PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ALERT, NBPtr->MCTPtr);
+        }
+        DCTPtr->Timings.TargetSpeed = DdrMaxRate;
+      }
+
+      IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) {
+        //
+        //Call Platform POR Frequency Override
+        //
+        if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) {
+          //
+          // Get the POR frequency limit
+          //
+          NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr);
+        }
+      }
+      IDS_OPTION_HOOK (IDS_STRETCH_FREQUENCY_LIMIT, NBPtr, &NBPtr->MemPtr->StdHeader);
+
+      if (MinSpeed > DCTPtr->Timings.TargetSpeed) {
+        MinSpeed = DCTPtr->Timings.TargetSpeed;
+      }
+    }
+  }
+
+  if (MinSpeed == DDR667_FREQUENCY) {
+    NBPtr->StartupSpeed = DDR667_FREQUENCY;
+  }
+
+  // Sync all DCTs to the same speed
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function waits for all DCTs to be ready
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNSyncDctsReadyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->MCTPtr->DimmValid) {
+    MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE);
+    // Re-enable phy compensation engine after Dram init has completed
+    MemNSwitchDCTNb (NBPtr, 0);
+    MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+  }
+  // Wait 750 us for the phy compensation engine to reinitialize.
+  MemUWait10ns (75000, NBPtr->MemPtr);
+
+  MemNSyncAddrMapToAllNodesNb (NBPtr);
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function create the HT memory map
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNHtMemMapInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 BottomIo;
+  UINT32 HoleOffset;
+  UINT32 DctSelBaseAddr;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  //
+  // Physical addresses in this function are right adjusted by 16 bits ([47:16])
+  // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit.
+  //
+
+  // Enforce bottom of IO be be 128MB aligned
+  ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0));
+  BottomIo = (RefPtr->BottomIo & 0xF8) << 8;
+
+  if (!MCTPtr->GangedMode) {
+    DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize;
+  } else {
+    DctSelBaseAddr = 0;
+  }
+
+  if (MCTPtr->NodeMemSize) {
+    NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase;
+    NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1;
+    DctSelBaseAddr += NodeSysBase;
+
+    if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) {
+      if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) {
+        // HW Dram Remap
+        MCTPtr->Status[SbHWHole] = TRUE;
+        RefPtr->GStatus[GsbHWHole] = TRUE;
+        MCTPtr->NodeHoleBase = BottomIo;
+        RefPtr->HoleBase = BottomIo;
+
+        HoleOffset = _4GB_RJ16 - BottomIo;
+
+        NodeSysLimit += HoleOffset;
+
+        if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) {
+          HoleOffset += DctSelBaseAddr;
+        } else {
+          if (DctSelBaseAddr >= BottomIo) {
+            DctSelBaseAddr += HoleOffset;
+          }
+          HoleOffset += NodeSysBase;
+        }
+
+        MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8);
+        MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7);
+        MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1);
+
+      } else if (NodeSysBase == BottomIo) {
+        // SW Node Hoist
+        MCTPtr->Status[SbSWNodeHole] = TRUE;
+        RefPtr->GStatus[GsbSpIntRemapHole] = TRUE;
+        RefPtr->GStatus[GsbSoftHole] = TRUE;
+
+        RefPtr->HoleBase = NodeSysBase;
+        DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase);
+        NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase);
+        NodeSysBase = _4GB_RJ16;
+
+      } else if ((NodeSysBase < HT_REGION_BASE_RJ16) && (NodeSysLimit >= HT_REGION_BASE_RJ16)) {
+        if (!NBPtr->SharedPtr->UndoHoistingAbove1TB) {
+          // SW Hoisting above 1TB to avoid HT Reserved region
+          DctSelBaseAddr = _1TB_RJ16 + (DctSelBaseAddr - NodeSysBase);
+          NodeSysLimit = _1TB_RJ16 + (NodeSysLimit - NodeSysBase);
+          NodeSysBase = _1TB_RJ16;
+
+          if (RefPtr->LimitMemoryToBelow1Tb) {
+            // Flag to undo 1TB hoisting after training
+            NBPtr->SharedPtr->UndoHoistingAbove1TB = TRUE;
+          }
+        }
+
+      } else {
+        // No Remapping.  Normal Contiguous mapping
+      }
+    } else {
+      // No Remapping.  Normal Contiguous mapping
+    }
+
+    if (NBPtr->IsSupported[Check1GAlign]) {
+      if (UserOptions.CfgNodeMem1GBAlign) {
+        NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit);
+      }
+    }
+
+    MCTPtr->NodeSysBase = NodeSysBase;
+    MCTPtr->NodeSysLimit = NodeSysLimit;
+    RefPtr->SysLimit = NodeSysLimit;
+    RefPtr->Sub1THoleBase = (NodeSysLimit < HT_REGION_BASE_RJ16) ? (NodeSysLimit + 1) : RefPtr->Sub1THoleBase;
+    IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader);
+
+    NBPtr->SharedPtr->TopNode = NBPtr->Node;
+
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00;
+
+    MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16));
+    MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16));
+
+    if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
+      MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11);
+      MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1);
+      MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1);
+      MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10);
+    }
+
+    NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0;
+  }
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Program system DRAM map to this node
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSyncAddrMapToAllNodesNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Node;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  UINT8  WeReMask;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  for (Node = 0; Node < NBPtr->NodeCount; Node++) {
+    NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase;
+    NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit;
+    if (NBPtr->SharedPtr->NodeMap[Node].IsValid) {
+      WeReMask = 3;
+    } else {
+      WeReMask = 0;
+    }
+    // Set the Dram base and set the WE and RE flags in the base.
+    MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask);
+    MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24);
+    // Set the Dram limit and set DstNode.
+    MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node);
+    MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24);
+
+    if (RefPtr->GStatus[GsbHWHole]) {
+      MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1);
+      MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8));
+    }
+  }
+
+  NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPowerDownCtlNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+
+  // we can't enable powerdown mode when doing WL
+  if (RefPtr->EnablePowerDown) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+    PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode);
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Optimal Critical Gross Delay Difference between
+ *   the delay parameters across all Dimms on each bytelane.  Then takes the
+ *   largest of all the bytelanes.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       TrnDly1 - Type of first Gross Delay parameter
+ *     @param[in]       TrnDly2 - Type of second Gross Delay parameter
+ *
+ *     @return  The largest difference between the largest and smallest
+ *               of the two Gross delay types within a single bytelane
+ */
+INT8
+MemNGetOptimalCGDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly1,
+  IN       TRN_DLY_TYPE TrnDly2
+  )
+{
+  INT8  CGDD;
+  INT8  GDD;
+  UINT8  Dimm1;
+  UINT8  Dimm2;
+  UINT8  ByteLane;
+  UINT16 CsEnabled;
+  BOOLEAN CGDDInit;
+  BOOLEAN SameDelayType;
+
+  CGDD = 0;
+  CGDDInit = FALSE;
+  SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2);
+  CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+
+  // If the two delay types compared are the same type, then no need to compare the same
+  // pair twice. Adjustments are made in the upper bound and lower bound of the loop to
+  // handle this.
+  for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) {
+    if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) {
+      for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) {
+        if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) {
+          for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) {
+            // check each byte lane delay pair
+            GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) -
+                  (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5);
+            // If the 2 delay types to be compared are the same, then keep the absolute difference
+            if (SameDelayType && (GDD < 0)) {
+              GDD = (-GDD);
+            }
+
+            // If CGDD is yet to be initialized, initialize it
+            // Otherwise, keep the largest difference so far
+            CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD);
+            if (!CGDDInit) {
+              CGDDInit = TRUE;
+            }
+          }
+        }
+      }
+    }
+  }
+  return CGDD;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the critical delay difference (CDD)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       TrnDlyType1 - Type of first Gross Delay parameter
+ *     @param[in]       TrnDlyType2 - Type of second Gross Delay parameter
+ *     @param[in]       SameDimm - CDD of same DIMMs
+ *     @param[in]       DiffDimm - CDD of different DIMMs
+ *
+ *     @return          CDD term - in 1/2 MEMCLK
+ */
+INT16
+MemNCalcCDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDlyType1,
+  IN       TRN_DLY_TYPE TrnDlyType2,
+  IN       BOOLEAN SameDimm,
+  IN       BOOLEAN DiffDimm
+  )
+{
+  INT16 CDD;
+  INT16 CDDtemp;
+  UINT16 TrnDly1;
+  UINT16 TrnDly2;
+  UINT8 i;
+  UINT8 j;
+  UINT8 ByteLane;
+  UINT16 CsEnabled;
+  BOOLEAN SameDlyType;
+
+  SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2);
+  CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+  CDD = -127;
+  // If the two delay types compared are the same type, then no need to compare the same
+  // pair twice. Adjustments are made in the upper bound and lower bound of the loop to
+  // handle this.
+  for (i = 0; i < (SameDlyType ? (NBPtr->CsPerChannel - NBPtr->CsPerDelay) : NBPtr->CsPerChannel); i = i + NBPtr->CsPerDelay) {
+    if ((CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2) ? 3 : 1) << i)) != 0) {
+      for (j = SameDlyType ? (i + NBPtr->CsPerDelay) : 0; j < NBPtr->CsPerChannel; j = j + NBPtr->CsPerDelay) {
+        if (((CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << j)) != 0) &&
+            ((SameDimm && ((i / 2) == (j / 2))) || (DiffDimm && ((i / 2) != (j / 2))))) {
+          for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
+            /// @todo: Gross delay mask should not be constant.
+            TrnDly1 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i / NBPtr->CsPerDelay, ByteLane)) >> 5;  // Gross delay only
+            TrnDly2 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j / NBPtr->CsPerDelay, ByteLane)) >> 5;  // Gross delay only
+
+            CDDtemp = TrnDly1 - TrnDly2;
+            // If the 2 delay types to be compared are the same, then keep the absolute difference
+            if ((SameDlyType) && (CDDtemp < 0)) {
+              CDDtemp = (-CDDtemp);
+            }
+
+            CDD = (CDD < CDDtemp) ? CDDtemp : CDD;
+          }
+        }
+      }
+    }
+  }
+
+  return CDD;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets DQS timing from data saved in heap.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDlyType - type of delay to be set
+ *     @param[in]   Drbn - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *
+ *     @return      value of the target timing.
+ */
+UINT16
+GetTrainDlyFromHeapNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDlyType,
+  IN       DRBN Drbn
+  )
+{
+  UINT8 Dimm;
+  UINT8 Byte;
+  UINT16 TrainDly;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_TECH_BLOCK *TechPtr;
+
+  Dimm = DRBN_DIMM (Drbn);
+  Byte = DRBN_BYTE (Drbn);
+  ChannelPtr = NBPtr->ChannelPtr;
+  TechPtr = NBPtr->TechPtr;
+
+  ASSERT (Dimm < (NBPtr->CsPerChannel / NBPtr->CsPerDelay));
+  ASSERT (Byte <= ECC_DLY);
+
+  if (NBPtr->MemPstate == MEMORY_PSTATE1) {
+    switch (TrnDlyType) {
+    case AccessRcvEnDly:
+      TrainDly = ChannelPtr->RcvEnDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    case AccessWrDqsDly:
+      TrainDly = ChannelPtr->WrDqsDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    case AccessWrDatDly:
+      TrainDly = ChannelPtr->WrDatDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    case AccessRdDqsDly:
+      TrainDly = ChannelPtr->RdDqsDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    default:
+      TrainDly = 0;
+      IDS_ERROR_TRAP;
+    }
+  } else {
+    switch (TrnDlyType) {
+    case AccessRcvEnDly:
+      TrainDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    case AccessWrDqsDly:
+      TrainDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    case AccessWrDatDly:
+      TrainDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    case AccessRdDqsDly:
+      TrainDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
+      break;
+    default:
+      TrainDly = 0;
+      IDS_ERROR_TRAP;
+    }
+  }
+
+  return TrainDly;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the fixed MTRRs for common legacy ranges.
+ *   It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNCPUMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Bottom32bIO;
+  UINT32 Bottom40bIO;
+  UINT32 Cache32bTOP;
+  S_UINT64 SMsr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  RefPtr = NBPtr->RefPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  //
+  //======================================================================
+  // Set temporary top of memory from Node structure data.
+  // Adjust temp top of memory down to accommodate 32-bit IO space.
+  //======================================================================
+  //Bottom40bIO=top of memory, right justified 16 bits  (defines dram versus IO space type)
+  //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type)
+  //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits
+  //
+  if (RefPtr->HoleBase != 0) {
+    Bottom32bIO = RefPtr->HoleBase;
+  } else if (RefPtr->BottomIo != 0) {
+    Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16);
+  } else {
+    Bottom32bIO = (UINT32)1 << (24 - 16);
+  }
+
+  Cache32bTOP = RefPtr->SysLimit + 1;
+  if (Cache32bTOP < _4GB_RJ16) {
+    Bottom40bIO = 0;
+    if (Bottom32bIO >= Cache32bTOP) {
+      Bottom32bIO = Cache32bTOP;
+    }
+  } else {
+    Bottom40bIO = Cache32bTOP;
+  }
+
+  Cache32bTOP = Bottom32bIO;
+
+
+  //
+  //======================================================================
+  // Set default values for CPU registers
+  //======================================================================
+  //
+  LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo |= 0x1C0000;                // turn on modification enable bit and
+                                      // mtrr enable bits
+  LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  SMsr.lo = SMsr.hi = 0x1E1E1E1E;
+  LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // 0 - 512K = WB Mem
+  LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // 512K - 640K = WB Mem
+
+  //
+  //======================================================================
+  // Set variable MTRR values
+  //======================================================================
+  //
+  MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6);
+
+  RefPtr->Sub4GCacheTop = Cache32bTOP << 16;
+
+  //
+  //======================================================================
+  // Set TOP_MEM and TOM2 CPU registers
+  //======================================================================
+  //
+  SMsr.hi = Bottom32bIO >> (32 - 16);
+  SMsr.lo = Bottom32bIO << 16;
+  LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM:  %08x0000\n", Bottom32bIO);
+
+  if (Bottom40bIO) {
+    SMsr.hi = Bottom40bIO >> (32 - 16);
+    SMsr.lo = Bottom40bIO << 16;
+  } else {
+    SMsr.hi = 0;
+    SMsr.lo = 0;
+  }
+  LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (Bottom40bIO) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", Bottom40bIO);
+    IDS_HDT_CONSOLE (MEM_FLOW, "Sub1THoleBase: %08x0000\n", RefPtr->Sub1THoleBase);
+    // Enable TOM2
+    SMsr.lo |= 0x00600000;
+  } else {
+    // Disable TOM2
+    SMsr.lo &= ~0x00600000;
+  }
+  SMsr.lo &= 0xFFF7FFFF; // turn off modification enable bit
+  LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
+ *   It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNUMAMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Bottom32bIO;
+  UINT32 Bottom32bUMA;
+  UINT32 Cache32bTOP;
+  UINT32 Value32;
+  UINT8 BitCount;
+  UINT8 i;
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  RefPtr = NBPtr->RefPtr;
+  BitCount = 0;
+  //
+  //======================================================================
+  // Adjust temp top of memory down to accommodate UMA memory start
+  //======================================================================
+  // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type)
+  // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits
+  //
+  Bottom32bIO = RefPtr->Sub4GCacheTop >> 16;
+  Bottom32bUMA = RefPtr->UmaBase;
+
+  if (Bottom32bUMA < Bottom32bIO) {
+    Cache32bTOP = Bottom32bUMA;
+    RefPtr->Sub4GCacheTop = Bottom32bUMA << 16;
+    //
+    //======================================================================
+    //Set variable MTRR values
+    //======================================================================
+    //
+    Value32 = Cache32bTOP;
+    //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing.
+    while (Value32 != 0) {
+      i = LibAmdBitScanForward (Value32);
+      Value32 &= ~ (1 << i);
+      BitCount++;
+    }
+
+    if (BitCount > 5) {
+      NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE;
+      MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO);
+    } else {
+      MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  Program MTRRs to describe given range as given cache type.  Use MTRR pairs
+ *  starting with the given MTRRphys Base address, and use as many as is
+ *  required up to (excluding) MSR 020C, which is reserved for OS.
+ *
+ *  "Limit" in the context of this procedure is not the numerically correct
+ *  limit, but rather the Last address+1, for purposes of coding efficiency
+ *  and readability.  Size of a region is then Limit-Base.
+ *
+ *  1. Size of each range must be a power of two
+ *  2. Each range must be naturally aligned (Base is same as size)
+ *
+ *  There are two code paths: the ascending path and descending path (analogous
+ *  to bsf and bsr), where the next limit is a function of the next set bit in
+ *  a forward or backward sequence of bits (as a function of the Limit).  We
+ *  start with the ascending path, to ensure that regions are naturally aligned,
+ *  then we switch to the descending path to maximize MTRR usage efficiency.
+ *  Base=0 is a special case where we start with the descending path.
+ *  Correct Mask for region is 2comp(Size-1)-1,
+ *  which is 2comp(Limit-Base-1)-1 *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Base - Base address[47:16] of specified range.
+ *     @param[in]     *LimitPtr - Limit address[47:16] of specified range.
+ *     @param[in]     MtrrAddr - address of var MTRR pair to start using.
+ *     @param[in]     MtrrType - Cache type for the range.
+ *
+ *     @return      TRUE - No failure occurred
+ *     @return      FALSE - Failure occurred because run out of variable-size MTRRs before completion.
+ */
+
+BOOLEAN
+STATIC
+MemNSetMTRRrangeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Base,
+  IN OUT   UINT32 *LimitPtr,
+  IN       UINT32 MtrrAddr,
+  IN       UINT8 MtrrType
+  )
+{
+  S_UINT64 SMsr;
+  UINT32 CurBase;
+  UINT32 CurLimit;
+  UINT32 CurSize;
+  UINT32 CurAddr;
+  UINT32 Value32;
+
+  CurBase = Base;
+  CurLimit = *LimitPtr;
+  CurAddr = MtrrAddr;
+
+  while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) {
+    CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase);
+    CurLimit += CurBase;
+    if ((CurBase == 0) || (*LimitPtr < CurLimit)) {
+      CurLimit = *LimitPtr - CurBase;
+      CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit);
+      CurLimit += CurBase;
+    }
+
+    // prog. MTRR with current region Base
+    SMsr.lo = (CurBase << 16) | (UINT32)MtrrType;
+    SMsr.hi = CurBase >> (32 - 16);
+    LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+    // prog. MTRR with current region Mask
+    CurAddr++;                              // other half of MSR pair
+    Value32 = CurSize - (UINT32)1;
+    Value32 = ~Value32;
+    SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk;
+    SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID);
+    LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+    CurBase = CurLimit;
+    CurAddr++;                              // next MSR pair
+  }
+
+  if (CurLimit < *LimitPtr) {
+    // Announce failure
+    *LimitPtr = CurLimit;
+    IDS_ERROR_TRAP;
+  }
+
+  while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) {
+    SMsr.lo = SMsr.hi = 0;
+    LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+    CurAddr++;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Program one MTRR to describe Uma region as UC cache type if we detect running out of
+ *     Mtrr circumstance.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     *BasePtr - Base address[47:24] of specified range.
+ *     @param[in]     *LimitPtr - Limit address[47:24] of specified range.
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemNSetMTRRUmaRegionUCNb  (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 *BasePtr,
+  IN OUT   UINT32 *LimitPtr
+  )
+{
+  S_UINT64 SMsr;
+  UINT32 Mtrr;
+  UINT32 Size;
+  UINT32 Value32;
+
+  Size = *LimitPtr - *BasePtr;
+  // Check if Size is a power of 2
+  if ((Size & (Size - 1)) != 0) {
+    for (Mtrr = 0x200; Mtrr < 0x20A; Mtrr += 2) {
+      LibAmdMsrRead (Mtrr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+      if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) {
+        MemNSetMTRRrangeNb (NBPtr, *BasePtr, LimitPtr, Mtrr, 0);
+        break;
+      }
+    }
+    if (Mtrr == 0x20A) {
+      // Run out of MTRRs
+      IDS_ERROR_TRAP;
+    }
+  } else {
+    Mtrr = 0x20A; //Reserved pair of MTRR for UMA region.
+
+    // prog. MTRR with current region Base
+    SMsr.lo = *BasePtr  << 16;
+    SMsr.hi = *BasePtr >> (32 - 16);
+    LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+    // prog. MTRR with current region Mask
+    Mtrr++;                              // other half of MSR pair
+    Value32 = Size - (UINT32)1;
+    Value32 = ~Value32;
+    SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk;
+    SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID);
+    LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Report the Uma size that is going to be allocated.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          Uma size [31:0] = Addr [47:16]
+ */
+UINT32
+MemNGetUmaSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return 0;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function allocates 16MB of memory for C6 storage when it is requested to be enabled
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNAllocateC6StorageClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 SysLimit;
+
+  if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
+    SysLimit = NBPtr->RefPtr->SysLimit;
+    SysLimit -= _16MB_RJ16;
+
+    // Set Dram Limit
+    NBPtr->MCTPtr->NodeSysLimit = SysLimit;
+    NBPtr->RefPtr->SysLimit = SysLimit;
+    MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000));
+
+    // Set TOPMEM and MTRRs
+    MemNC6AdjustMSRs (NBPtr);
+
+    // Set C6Base
+    MemNSetBitFieldNb (NBPtr, BFC6Base, (SysLimit + 1) >> (24 - 16));
+
+    // C6DramLock will be set in FinalizeMCT
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function allocates 16MB of memory for C6 storage when it is requested to be enabled
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNAllocateC6StorageUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8  Node;
+  UINT32 SysLimit;
+  UINT32 DramLimitReg;
+
+  if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
+
+    SysLimit = NBPtr->RefPtr->SysLimit;
+
+    // Calculate new SysLimit
+    if (!NBPtr->SharedPtr->C6Enabled) {
+      if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) {
+        // Node Interleave is enabled, system memory available is reduced by 16MB * number of nodes
+        SysLimit -= _16MB_RJ16 * NBPtr->SharedPtr->NodeIntlv.NodeCnt;
+      } else {
+        // Otherwise, system memory available is reduced by 16MB
+        SysLimit -= _16MB_RJ16;
+      }
+      NBPtr->RefPtr->SysLimit = SysLimit;
+      NBPtr->SharedPtr->C6Enabled = TRUE;
+
+      // Set TOPMEM and MTRRs (only need to be done once for BSC)
+      MemNC6AdjustMSRs (NBPtr);
+    }
+
+    // Set Dram Limit
+    if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) {
+      for (Node = 0; Node < NBPtr->NodeCount; Node++) {
+        DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + Node);
+        if ((DramLimitReg & 0xFFFF0000) != 0) {
+          MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, ((SysLimit << 8) & 0xFFFF0000) | (DramLimitReg & 0xFFFF));
+          MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, SysLimit >> 24);
+        }
+      }
+      // Node Interleave is enabled, CoreStateSaveDestNode points to its own node
+      MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->Node);
+      NBPtr->MCTPtr->NodeSysLimit = SysLimit;
+    } else {
+      DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode) & 0x0000FFFF;
+      MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg);
+      MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + NBPtr->SharedPtr->TopNode, SysLimit >> 24);
+
+      // Node Interleave is not enabled, CoreStateSaveDestNode points to the node that contains top memory
+      MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->SharedPtr->TopNode);
+
+      if (NBPtr->Node == NBPtr->SharedPtr->TopNode) {
+        NBPtr->MCTPtr->NodeSysLimit = SysLimit;
+      }
+    }
+
+    // Set BFCC6SaveEn
+    MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1);
+
+    // LockDramCfg will be set in FinalizeMCT
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function readjusts TOPMEM and MTRRs after allocating storage for C6
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNC6AdjustMSRs (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 SysLimit;
+  UINT32 CurAddr;
+  S_UINT64 SMsr;
+
+  SysLimit = NBPtr->RefPtr->SysLimit + 1;
+  SMsr.hi = SysLimit >> (32 - 16);
+  SMsr.lo = SysLimit << 16;
+  if (SysLimit < _4GB_RJ16) {
+    LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM:  %08x0000\n", SysLimit);
+    // If there is no UMA buffer, then set top of cache and MTRR.
+    // Otherwise, top of cache and MTRR will be set when UMA buffer is set up.
+    if (NBPtr->RefPtr->UmaMode == UMA_NONE) {
+      NBPtr->RefPtr->Sub4GCacheTop = (SysLimit << 16);
+      // Find unused MTRR to set C6 region to UC
+      for (CurAddr = 0x200; CurAddr < 0x20C; CurAddr += 2) {
+        LibAmdMsrRead (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+        if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) {
+          // Set region base as TOM
+          SMsr.hi = SysLimit >> (32 - 16);
+          SMsr.lo = SysLimit << 16;
+          LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+          // set region mask to 16MB
+          SMsr.hi = NBPtr->VarMtrrHiMsk;
+          SMsr.lo = 0xFF000800;
+          LibAmdMsrWrite (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+          break;
+        }
+      }
+    }
+  } else {
+    LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", SysLimit);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     Family-specific hook to override the DdrMaxRate value for families with a
+ *     non-GH-compatible encoding for BFDdrMaxRate
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *DdrMaxRate - Void pointer to DdrMaxRate.  Used as INT16.
+ *
+ *     @return          TRUE
+ *
+ */
+BOOLEAN
+MemNGetMaxDdrRateUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *DdrMaxRate
+  )
+{
+  UINT8 DdrMaxRateEncoded;
+
+  DdrMaxRateEncoded = (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate);
+
+  if (DdrMaxRateEncoded == 0) {
+    * (UINT16 *) DdrMaxRate = UNSUPPORTED_DDR_FREQUENCY;
+  } else {
+    * (UINT16 *) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, DdrMaxRateEncoded);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function performs the action after save/restore execution
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNAfterSaveRestoreUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  // Sync. up DctCfgSel value with NBPtr->Dct
+  MemNSetBitFieldNb (NBPtr, BFDctCfgSel, NBPtr->Dct);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function performs the action before and after excluding dimms on CNB
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  *IsBefore   - If the function is called before excluding dimms
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *IsBefore
+  )
+{
+  if (*(BOOLEAN *) IsBefore == TRUE) {
+    NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1);
+    NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  } else {
+    NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1);
+    NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c
new file mode 100644
index 0000000000..e2bc796126
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c
@@ -0,0 +1,2059 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnphy.c
+ *
+ * Common Northbridge Phy support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "PlatformMemoryConfiguration.h"
+#include "heapManager.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_MEM_NB_MNPHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Type of an entry for processing phy init compensation for client NB
+typedef struct {
+  BIT_FIELD_NAME IndexBitField;          ///< Bit field on which the value is decided
+  BIT_FIELD_NAME StartTargetBitField;    ///< First bit field to be modified
+  BIT_FIELD_NAME EndTargetBitField;      ///< Last bit field to be modified
+  UINT16 ExtraValue;                     ///< Extra value needed to be written to bit field
+  CONST UINT16 (*TxPrePN)[3][5];         ///< Pointer to slew rate table
+} PHY_COMP_INIT_CLIENTNB;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets a delay value a PCI register during training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *
+ *     @return      Value read
+ */
+
+UINT32
+MemNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  )
+{
+  return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets a delay value a PCI register during training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *
+ */
+
+VOID
+MemNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes prototypical Phy fence training function.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPhyFenceTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->MemPPhyFenceTrainingNb (NBPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes prototypical Phy fence training function.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPhyFenceTrainingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 FenceThresholdTxDll;
+  UINT8 FenceThresholdRxDll;
+  UINT8 FenceThresholdTxPad;
+  UINT16 Fence2Data;
+
+  MemNSetBitFieldNb (NBPtr, BFDataFence2, 0);
+  MemNSetBitFieldNb (NBPtr, BFFence2, 0);
+  // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b.
+  // 2. Perform phy fence training.
+  // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll].
+  MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2);
+  MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFenceThresholdTxDll\n");
+  MemNTrainPhyFenceNb (NBPtr);
+  FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+  NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxDll);
+
+  // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b.
+  MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000);
+
+  // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b.
+  // 6. Perform phy fence training.
+  // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll].
+  MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1);
+  MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdRxDll\n");
+  MemNTrainPhyFenceNb (NBPtr);
+  FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+  NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdRxDll);
+
+  // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b.
+  MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000);
+
+  // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b.
+  // 10. Perform phy fence training.
+  // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad].
+  MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3);
+  MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdTxPad\n");
+  MemNTrainPhyFenceNb (NBPtr);
+  FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+  NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxPad);
+
+  // Program Fence2 threshold for Clk, Cmd, and Addr
+  if (FenceThresholdTxPad < 16) {
+    MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10);
+    MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10);
+    MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFClkFence2, 0);
+    MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0);
+    MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0);
+  }
+
+  // Program Fence2 threshold for data
+  Fence2Data = 0;
+  if (FenceThresholdTxPad < 16) {
+    Fence2Data |= FenceThresholdTxPad | 0x10;
+  }
+  if (FenceThresholdRxDll < 16) {
+    Fence2Data |= (FenceThresholdRxDll | 0x10) << 10;
+  }
+  if (FenceThresholdTxDll < 16) {
+    Fence2Data |= (FenceThresholdTxDll | 0x10) << 5;
+  }
+  MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data);
+  NBPtr->FamilySpecificHook[ProgramFence2RxDll] (NBPtr, &Fence2Data);
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    // 18. If motherboard routing requires CS[7:6] to adopt address timings, e.g. 3 LRDIMMs/ch with CS[7:6]
+    // routed across all DIMM sockets, BIOS performs the following:
+    if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_NO_LRDIMM_CS67_ROUTING, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
+      //   A. Program D18F2xA8_dct[1:0][CSTimingMux67] = 1.
+      MemNSetBitFieldNb (NBPtr, BFCSTimingMux67, 1);
+      //   B. Program D18F2x9C_x0D0F_8021_dct[1:0]:
+      //       - DiffTimingEn = 1.
+      //       - IF (D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay] >=
+      //         D18F2x9C_x0D0F_E008_dct[1:0][FenceValue]) THEN Fence = 1 ELSE Fence = 0.
+      //       - Delay = D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay].
+      //
+      MemNSetBitFieldNb (NBPtr, BFDiffTimingEn, 1);
+      MemNSetBitFieldNb (NBPtr, BFFence, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay) >= MemNGetBitFieldNb (NBPtr, BFFenceValue)) ? 1 : 0);
+      MemNSetBitFieldNb (NBPtr, BFDelay, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay)));
+    }
+  }
+
+  // 19. Reprogram F2x9C_04.
+  MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes Phy fence training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNTrainPhyFenceNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Byte;
+  INT16 Avg;
+  UINT8 PREvalue;
+
+  if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) {
+    return;
+  }
+
+  // 1. BIOS first programs a seed value to the phase recovery
+  //    engine registers.
+  //
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSeeds: ");
+  for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) {
+    // This includes ECC as byte 8
+    MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19);
+    IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", 19);
+  }
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tPhyFenceTrEn = 1");
+  // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1.
+  MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1);
+
+  if (!NBPtr->IsSupported[UnifiedNbFence]) {
+    // 3. Wait 200 MEMCLKs.
+    MemNWaitXMemClksNb (NBPtr, 200);
+  } else {
+    // 3. Wait 2000 MEMCLKs.
+    MemNWaitXMemClksNb (NBPtr, 2000);
+  }
+
+  // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0.
+  MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0);
+
+  // 5. BIOS reads the phase recovery engine registers
+  //    F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52.
+  // 6. Calculate the average value of the fine delay and subtract 8.
+  //
+  Avg = 0;
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t  PRE: ");
+  for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) {
+    //
+    // This includes ECC as byte 8.   ECC Byte lane (8) is ignored by MemNGetTrainDlyNb function where
+    // ECC is not supported.
+    //
+    PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte)));
+    Avg = Avg + ((INT16) PREvalue);
+    IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", PREvalue);
+  }
+  Avg = ((Avg + 8) / 9);    // round up
+
+  Avg -= 8;
+  NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFence: %02x\n", Avg);
+
+  // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence].
+  MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg);
+
+  // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control
+  //    Register delays for both channels. This forces the phy to recompute
+  //    the fence.
+  //
+  MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
+  CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
+  CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
+  CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
+  UINT8 i;
+  UINT8 j;
+  UINT8 CurrDct;
+  UINT8 CurrChannel;
+  BOOLEAN MarginImprv;
+  MarginImprv = FALSE;
+  CurrDct = NBPtr->Dct;
+  CurrChannel = NBPtr->Channel;
+  if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) {
+    if (NBPtr->MCTPtr->GangedMode == FALSE) {
+      for (i = 0; i < NBPtr->DctCount; i++) {
+        MemNSwitchDCTNb (NBPtr, i);
+        for (j = 0; j < NBPtr->ChannelCount; j++) {
+          NBPtr->SwitchChannel (NBPtr, j);
+          if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) {
+            MarginImprv = TRUE;
+          }
+        }
+      }
+      MemNSwitchDCTNb (NBPtr, CurrDct);
+      NBPtr->SwitchChannel (NBPtr, CurrChannel);
+    }
+  }
+
+  // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // DisAutoComp will be cleared after Dram init has completed
+  //
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+  MemUWait10ns (500, NBPtr->MemPtr);
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+
+  // 3. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
+  // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
+  //
+  // 4. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
+  // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
+  // D3Cmp2PCal].
+  //
+  j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
+  i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
+
+  if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) {
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]);
+  }
+  if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) {
+    ASSERT (i <= 3);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
+  }
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDQSTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 TestAddrRJ16;
+  UINT32 RealAddr;
+
+  MemTBeginTraining (NBPtr->TechPtr);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+        if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
+
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
+
+          MemUDummyCLRead (RealAddr);
+
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
+          MemUWait10ns (60, NBPtr->MemPtr);   // Wait 300ns
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
+          MemUWait10ns (400, NBPtr->MemPtr);  // Wait 2us
+          MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
+          break;
+        }
+      }
+    }
+    if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
+      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
+      }
+      if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
+      }
+    }
+  }
+
+  MemTEndTraining (NBPtr->TechPtr);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     Returns the parameters for a requested delay value to be used in training
+ *     The correct Min, Max and Mask are determined based on the type of Delay,
+ *     and the frequency
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] TrnDly - Type of delay
+ *     @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
+ *
+ */
+
+VOID
+MemNGetTrainDlyParmsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  )
+{
+  Parms->Min = 0;
+
+  if (TrnDly == AccessWrDatDly) {
+    Parms->Max = 0x1F;
+    Parms->Mask = 0x01F;
+  } else if (TrnDly == AccessRdDqsDly) {
+    if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) {
+      Parms->Max = 0x3E;
+      Parms->Mask = 0x03E;
+    } else {
+      Parms->Max = 0x1F;
+      Parms->Mask = 0x01F;
+    }
+  }
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     Returns the parameters for a requested delay value to be used in training
+ *     The correct Min, Max and Mask are determined based on the type of Delay,
+ *     and the frequency
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] TrnDly - Type of delay
+ *     @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
+ *
+ */
+
+VOID
+MemNGetTrainDlyParmsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  )
+{
+  Parms->Min = 0;
+
+  if (TrnDly == AccessWrDatDly) {
+    Parms->Max = 0x1F;
+    Parms->Mask = 0x01F;
+  } else if (TrnDly == AccessRdDqsDly) {
+    Parms->Max = 0x3E;
+    Parms->Mask = 0x03E;
+  }
+}
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     Returns the parameters for a requested delay value to be used in training
+ *     The correct Min, Max and Mask are determined based on the type of Delay,
+ *     and the frequency
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] TrnDly - Type of delay
+ *     @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
+ *
+ */
+
+VOID
+MemNGetTrainDlyParmsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  )
+{
+  Parms->Min = 0;
+
+  if ((TrnDly == AccessWrDatDly) || (TrnDly == AccessRdDqsDly)) {
+    Parms->Max = 0x1F;
+    Parms->Mask = 0x01F;
+  }
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNcmnGetSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Rank;
+  UINT8 Byte;
+  UINT8 Nibble;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Rank = DRBN_RANK (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+  Nibble = DRBN_NBBL (DrbnVar);
+
+  ASSERT (Dimm < 4);
+  ASSERT (Byte <= ECC_DLY);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    if (Byte > 7) {
+      Index += 2;
+    }
+    Offset = 16 * (Byte % 2);
+    Index |= (Rank << 8);
+    Index |= (Nibble << 9);
+    break;
+
+  case AccessRdDqsDly:
+  case AccessWrDatDly:
+
+    if (NBPtr->IsSupported[DimmBasedOnSpeed]) {
+      if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) {
+        // if DDR speed is below 800, use DIMM 0 delays for all DIMMs.
+        Dimm = 0;
+      }
+    }
+
+    Index += (Dimm * 0x100);
+    if (Nibble) {
+      if (Rank) {
+        Index += 0xA0;
+      } else {
+        Index += 0x70;
+      }
+    } else if (Rank) {
+      Index += 0x60;
+    }
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+  Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (TrnDly == AccessRdDqsDly) {
+    NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset);
+  }
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset)));
+    MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+    MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF);
+  }
+
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+UINT32
+MemNcmnGetSetTrainDlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Byte;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+
+  ASSERT (Dimm < 2);
+  ASSERT (Byte <= ECC_DLY);
+
+  if ((Byte > 7)) {
+    // Llano does not support ECC delay, so:
+    if (IsSet) {
+      // On write, ignore
+      return 0;
+    } else {
+      // On read, redirect to byte 0 to correct fence averaging
+      Byte = 0;
+    }
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    Offset = 16 * (Byte % 2);
+    break;
+
+  case AccessRdDqsDly:
+  case AccessWrDatDly:
+    Index += (Dimm * 0x100);
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset)));
+    MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+    // Gross WrDatDly and WrDqsDly cannot be larger than 4
+    ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (NBPtr->IsSupported[WLNegativeDelay] || (Field < 0xA0)) : TRUE);
+  } else {
+    Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF);
+  }
+
+  return Value;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNcmnGetSetTrainDlyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Rank;
+  UINT8 Byte;
+  UINT8 Nibble;
+  UINT8 DimmNibble;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Rank = DRBN_RANK (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+  Nibble = DRBN_NBBL (DrbnVar);
+  DimmNibble = DRBN_DIMM_NBBL (DrbnVar);
+
+  ASSERT (Dimm < (NBPtr->CsPerChannel / NBPtr->CsPerDelay));
+  ASSERT (Byte <= ECC_DLY);
+  if ((Byte == ECC_DLY) && (!NBPtr->MCTPtr->Status[SbEccDimms] || !NBPtr->IsSupported[EccByteTraining])) {
+    // When ECC is not enabled
+    if (IsSet) {
+      // On write, ignore
+      return 0;
+    } else {
+      // On read, redirect to byte 0 to correct fence averaging
+      Byte = 0;
+    }
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case excel845 :
+    Index = 0x00;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    if (Byte > 7) {
+      Index += 2;
+    }
+    Offset = 16 * (Byte % 2);
+    Index |= (Rank << 8);
+    Index |= (Nibble << 9);
+    Address = Index;
+    break;
+
+  case AccessRdDqsDly:
+  case AccessWrDatDly:
+
+    if (NBPtr->IsSupported[DimmBasedOnSpeed]) {
+      if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) {
+        // if DDR speed is below 800, use DIMM 0 delays for all DIMMs.
+        Dimm = 0;
+      }
+    }
+
+    Index += (Dimm * 0x100);
+    if (Nibble) {
+      if (Rank) {
+        Index += 0xA0;
+      } else {
+        Index += 0x70;
+      }
+    } else if (Rank) {
+      Index += 0x60;
+    }
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    Address = Index;
+    break;
+  case excel845 :
+    Address = 0x0D0F0000;
+    Index += (DimmNibble >> 1) * 0x100;
+    Index += 0x20;
+    Index = Index + Dimm;
+    Offset = 4 * ((DimmNibble & 0x01) * 2);
+    Address += Index;
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+    Address = Index;
+  }
+  MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+  Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+  if (TrnDly == AccessRdDqsDly) {
+    NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset);
+  }
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+    if (TrnDly != excel845 ) {
+      Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x3FF : 0xFF) << Offset)));
+    } else {
+      Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) 0x1F << Offset)));
+    }
+    MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+    MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    if (TrnDly != excel845 ) {
+      Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x3FF : 0xFF);
+    } else {
+      Value = (Value >> Offset) & (UINT32) (0x1F);
+    }
+  }
+  return Value;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function initializes the training pattern.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      AGESA_STATUS - Result
+ *                  AGESA_SUCCESS - Training pattern is ready to use
+ *                  AGESA_ERROR   - Unable to initialize the pattern.
+ */
+
+AGESA_STATUS
+MemNTrainingPatternInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  TRAIN_PATTERN TrainPattern;
+  AGESA_STATUS Status;
+
+  TechPtr = NBPtr->TechPtr;
+  TrainPattern = 0;
+  //
+  // Check the training type
+  //
+  if (TechPtr->TrainingType == TRN_DQS_POSITION) {
+    //
+    // DQS Position Training
+    //
+    if (NBPtr->PosTrnPattern == POS_PATTERN_256B) {
+      //
+      // 256 Bit pattern
+      //
+      if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+        TrainPattern = TestPatternJD256B;
+        TechPtr->PatternLength = 64;
+      } else {
+        TrainPattern = TestPatternJD256A;
+        TechPtr->PatternLength = 32;
+      }
+    } else {
+      //
+      // 72 bit pattern will be used if PosTrnPattern is not specified
+      //
+      if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+        TrainPattern = TestPatternJD1B;
+        TechPtr->PatternLength = 18;
+      } else {
+        TrainPattern = TestPatternJD1A;
+        TechPtr->PatternLength = 9;
+      }
+    }
+  } else if (TechPtr->TrainingType == TRN_MAX_READ_LATENCY) {
+    //
+    // Max Read Latency Training
+    //
+    TrainPattern = TestPatternML;
+    TechPtr->PatternLength = (NBPtr->MCTPtr->Status[Sb128bitmode]) ? 6 : 3;
+  } else {
+    //
+    // Error - TechPtr->Training Type must be set to one of the types handled in this function
+    //
+    ASSERT (FALSE);
+  }
+  //
+  // Allocate training buffer
+  //
+  AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16;
+  AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr;
+  AlignPointerTo16Byte (&TechPtr->PatternBufPtr);
+  TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64);
+
+  // Prepare training pattern
+  MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
+
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function determined the settings for the Reliable Read/Write engine
+ *       for each specific type of training
+ *
+ *     @param[in,out]   *NBPtr      - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *OptParam   - Pointer to an Enum of TRAINING_TYPE
+ *
+ *     @return      TRUE
+ */
+
+BOOLEAN
+MemNSetupHwTrainingEngineUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *OptParam
+  )
+{
+  TRAINING_TYPE TrnType;
+  RRW_SETTINGS *Rrw;
+
+  TrnType = *(TRAINING_TYPE*) OptParam;
+  Rrw = &NBPtr->RrwSettings;
+  //
+  // Common Settings
+  //
+  Rrw->TgtBankAddressA = CPG_BANK_ADDRESS_A;
+  Rrw->TgtRowAddressA = CPG_ROW_ADDRESS_A;
+  Rrw->TgtColAddressA = CPG_COL_ADDRESS_A;
+  Rrw->TgtBankAddressB = CPG_BANK_ADDRESS_B;
+  Rrw->TgtRowAddressB = CPG_ROW_ADDRESS_B;
+  Rrw->TgtColAddressB = CPG_COL_ADDRESS_B;
+  Rrw->CompareMaskHigh = CPG_COMPARE_MASK_HI;
+  Rrw->CompareMaskLow = CPG_COMPARE_MASK_LOW;
+  Rrw->CompareMaskEcc = CPG_COMPARE_MASK_ECC;
+
+  switch (TrnType) {
+  case TRN_RCVR_ENABLE:
+    //
+    // Receiver Enable Training
+    //
+    NBPtr->TechPtr->PatternLength = 192;
+    break;
+  case TRN_MAX_READ_LATENCY:
+    //
+    // Max Read Latency Training
+    //
+    Rrw->CmdTgt = CMD_TGT_A;
+    NBPtr->TechPtr->PatternLength = 32;
+    Rrw->DataPrbsSeed = PRBS_SEED_32;
+    break;
+  case TRN_DQS_POSITION:
+    //
+    // Read/Write DQS Position training
+    //
+    Rrw->CmdTgt = CMD_TGT_AB;
+    NBPtr->TechPtr->PatternLength = 256;
+    Rrw->DataPrbsSeed = PRBS_SEED_256;
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function finalizes the training pattern.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Index    - Index of Write Data Delay Value
+ *     @param[in,out]   *Value   - Write Data Delay Value
+ *     @return      BOOLEAN - TRUE - Use the value returned.
+ *                            FALSE - No more values in table.
+ */
+
+BOOLEAN
+MemNGetApproximateWriteDatDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Index,
+  IN OUT   UINT8 *Value
+  )
+{
+  CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F};
+  if (Index < GET_SIZE_OF (WriteDatDelayValue)) {
+    *Value = WriteDatDelayValue[Index];
+    return TRUE;
+  }
+  return FALSE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function finalizes the training pattern.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      AGESA_STATUS - Result
+ *                  AGESA_SUCCESS - Training pattern has been finalized.
+ *                  AGESA_ERROR   - Unable to initialize the pattern.
+ */
+
+AGESA_STATUS
+MemNTrainingPatternFinalizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AGESA_STATUS Status;
+  //
+  // Deallocate training buffer
+  //
+  Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the number of Chipselects controlled by each set
+ *     of Delay registers under current conditions.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return
+ */
+
+UINT8
+MemNCSPerDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn) == 1) {
+    return 1;
+  } else {
+    return 2;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the minimum data eye width in 32nds of a UI for
+ *     the type of data eye(Rd/Wr) that is being trained.  This value will
+ *     be the minimum number of consecutive delays that yield valid data.
+ *     Uses TechPtr->Direction to determine read or write.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return
+ */
+
+UINT8
+MemNMinDataEyeWidthNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 MinRdDataeye;
+  UINT8 MinWrDataeye;
+  UINT8 *MinRdWrDataeyePtr;
+
+  MinRdWrDataeyePtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MIN_RD_WR_DATAEYE_WIDTH, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0,
+                                           &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+
+  if (NBPtr->TechPtr->Direction == DQS_READ_DIR) {
+    if (MinRdWrDataeyePtr != NULL) {
+      MinRdDataeye = MinRdWrDataeyePtr[0];
+      return MinRdDataeye;
+    } else {
+      return MIN_RD_DATAEYE_WIDTH_NB;
+    }
+  } else {
+    if (MinRdWrDataeyePtr != NULL) {
+      MinWrDataeye = MinRdWrDataeyePtr[1];
+      return MinWrDataeye;
+    } else {
+      return MIN_WR_DATAEYE_WIDTH_NB;
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function programs the phy registers according to the desired phy VDDIO voltage level
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPhyVoltageLevelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BIT_FIELD_NAME BitField;
+  BIT_FIELD_NAME BFEnd;
+  UINT16 BFValue;
+  UINT16 RegValue;
+
+  BFValue = (UINT16) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage) << 3;
+  BFEnd = NBPtr->IsSupported[ProgramCsrComparator] ? BFCsrComparator : BFCmpVioLvl;
+
+  for (BitField = BFDataRxVioLvl; BitField <= BFEnd; BitField++) {
+    RegValue = BFValue;
+    if (BitField == BFCsrComparator) {
+      RegValue >>= (3 - 2);
+      // Setting this bit in DCT0 adjusts the comparator for DCT0 and DCT1. Setting this bit in DCT1 has no effect.
+      NBPtr->SwitchDCT (NBPtr, 0);
+      MemNSetBitFieldNb (NBPtr, BitField, RegValue);
+      break;
+    } else if (BitField == BFCmpVioLvl) {
+      RegValue <<= (14 - 3);
+      // Must set this bit on DCT0 even when DCT0 has no memory
+      NBPtr->SwitchDCT (NBPtr, 0);
+      MemNSetBitFieldNb (NBPtr, BitField, RegValue);
+    }
+    MemNBrdcstSetNb (NBPtr, BitField, RegValue);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function adjusts Avg PRE value of Phy fence training according to specific CPU family.
+ *
+ *     @param[in,out]   *NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Value16 - Pointer to the value that we want to adjust
+ *
+ */
+VOID
+MemNPFenceAdjustUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   INT16 *Value16
+  )
+{
+  *Value16 += 2; //The Avg PRE value is subtracted by 6 only.
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // Slew rate table array [x][y][z]
+  // array[0]: slew rate for VDDIO 1.5V
+  // array[1]: slew rate for VDDIO 1.35V
+  // array[2]: slew rate for VDDIO 1.25V
+  // array[x][y]: slew rate for a certain frequency
+  // array[x][y][0]: frequency mask for current entry
+  CONST STATIC UINT16 TxPrePNDataDqs[3][3][5] = {
+    {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {{ (UINT16) DDR800, 0xFF6, 0xDAD, 0xDAD, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC UINT16 TxPrePNCmdAddr[3][3][5] = {
+    {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
+     { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB},
+     { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}},
+    {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
+     { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB},
+     { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}},
+    {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
+     { (UINT16) (DDR1066 + DDR1333), 0xDAD, 0x924, 0x6DB, 0x492},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xDAD, 0xB64, 0xB64}}
+  };
+  CONST STATIC UINT16 TxPrePNClock[3][3][5] = {
+    {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}},
+    {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+
+  CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = {
+    // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V.
+    //    A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}.
+    //    B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}.
+    {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs},
+    {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs},
+    {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs},
+    // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V.
+    //    A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}.
+    //    B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}.
+    {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr},
+    {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr},
+    {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr},
+    {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr},
+    {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr},
+    // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V.
+    //    A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}.
+    {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock}
+  };
+
+  BIT_FIELD_NAME CurrentBitField;
+  UINT16 SpeedMask;
+  CONST UINT16 (*TxPrePNArray)[5];
+  UINT8 Voltage;
+  UINT8 i;
+  UINT8 j;
+  UINT8 k;
+  UINT8 Dct;
+
+  Dct = NBPtr->Dct;
+  NBPtr->SwitchDCT (NBPtr, 0);
+  // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisablePreDriverCal] = {1b, 1b}.
+  MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000);
+  NBPtr->SwitchDCT (NBPtr, Dct);
+
+  SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66);
+  Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage);
+
+  for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) {
+    i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField);
+    TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage];
+    for (k = 0; k < 3; k ++) {
+      if ((TxPrePNArray[k][0] & SpeedMask) != 0) {
+        for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) {
+          MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1]));
+        }
+        break;
+      }
+    }
+    ASSERT (k < 3);
+  }
+
+  NBPtr->FamilySpecificHook[ForceAutoComp] (NBPtr, NBPtr);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function re-enable phy compensation.
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNReEnablePhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 Dct;
+
+  Dct = NBPtr->Dct;
+
+  NBPtr->SwitchDCT (NBPtr, 0);
+  // Clear DisableCal and set DisablePredriverCal
+  MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x2000);
+  NBPtr->SwitchDCT (NBPtr, Dct);
+
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function calculates the value of WrDqDqsEarly and programs it into
+ *       the DCT and adds it to the WrDqsGrossDelay of each byte lane on each
+ *       DIMM of the channel.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNCalcWrDqDqsEarlyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT8 Dimm;
+  UINT8 ByteLane;
+  UINT8 *WrDqsDlysPtr;
+  UINT8 WrDqDqsEarly;
+  UINT8 ChipSel;
+
+  ASSERT ((NBPtr->IsSupported[WLSeedAdjust]) && (NBPtr->IsSupported[WLNegativeDelay]));
+
+  TechPtr = NBPtr->TechPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  ASSERT (NBPtr != NULL);
+  ASSERT (ChannelPtr != NULL);
+  ASSERT (DCTPtr != NULL);
+  //
+  // For each DIMM:
+  // - The Critical Gross Delay (CGD) is the minimum GrossDly of all byte lanes and all DIMMs.
+  // - If (CGD < 0) Then
+  // -   D18F2xA8_dct[1:0][WrDqDqsEarly] = ABS(CGD)
+  // -   WrDqsGrossDly = GrossDly + WrDqDqsEarly
+  // - Else
+  // -   D18F2xA8_dct[1:0][WrDqDqsEarly] = 0.
+  // -   WrDqsGrossDly = GrossDly
+  //
+  WrDqDqsEarly = 0;
+  if (TechPtr->WLCriticalDelay < 0) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCalculating WrDqDqsEarly, adjusting WrDqs.\n");
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMin. Critical Delay: %x\n", TechPtr->WLCriticalDelay);
+    // We've saved the entire negative delay value, so take the ABS and convert to GrossDly.
+    WrDqDqsEarly =  (UINT8) (0x00FF &((((ABS (TechPtr->WLCriticalDelay)) + 0x1F) / 0x20)));
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWrDqDqsEarly : %02x\n\n", WrDqDqsEarly);
+    //
+    // Loop through All WrDqsDlys on all DIMMs
+    //
+    for (ChipSel = 0; ChipSel < NBPtr->CsPerChannel; ChipSel = ChipSel + NBPtr->CsPerDelay) {
+      if ((NBPtr->MCTPtr->Status[SbLrdimms]) ? ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0) :
+          ((DCTPtr->Timings.CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSel)) != 0)) {
+        //
+        // If LRDIMMs, only include the physical dimms, not logical Dimms
+        //
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS %x:", ChipSel);
+        Dimm = ChipSel / NBPtr->CsPerDelay;
+
+        WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]);
+        for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+          WrDqsDlysPtr[ByteLane] += (WrDqDqsEarly << 5);
+          NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]);
+          IDS_HDT_CONSOLE (MEM_FLOW, " %02x", WrDqsDlysPtr[ByteLane]);
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+      }
+    }
+  }
+  MemNSetBitFieldNb (NBPtr, BFWrDqDqsEarly, WrDqDqsEarly);
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function forces phy to M0 state
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return  none
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNForcePhyToM0Unb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  IDS_SKIP_HOOK (IDS_FORCE_PHY_TO_M0, NBPtr, &(NBPtr->MemPtr->StdHeader)) {
+    // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h.
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFPllRegWaitTime, 0x118);
+    // 2. For each byte lane and each memory P-state: Program D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0][RxSsbMntClkEn] = 0.
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFRxSsbMntClkEn, 0);
+    // 3. D18F2xA8_dct[1:0][MemPhyPllPdMode] = 00b.
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFMemPhyPllPdMode, 0);
+    // 4. Force the phy to M0 with the following sequence:
+    // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h. Restore the default PLL lock time.
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
+    // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h.
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
+    NBPtr->SwitchDCT (NBPtr, 0);
+    // C. Program D18F2x9C_x0D0F_E018_dct[0][PhyPSMasterChannel] = 0.
+    MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0);
+    // D. Program D18F2x9C_x0000_000B_dct[0] = 40000000h. CH0 only;
+    MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x40000000);
+    // E. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h.
+    MemNBrdcstSetUnConditionalNb (NBPtr, BFDramPhyStatusReg, 0x80000000);
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function sets SkewMemClk before enabling MemClk
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  *OptParam   - Optional parameter
+ *
+ *     @return  TRUE - always
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNSetSkewMemClkUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 Dct;
+
+  // SkewMemClk is set to 1 if all DCTs are enabled, else 0.
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize == 0) {
+    break;
+    }
+  }
+  MemNSwitchDCTNb (NBPtr, 0);
+  if (Dct == NBPtr->DctCount) {
+    MemNSetBitFieldNb (NBPtr, BFSkewMemClk, 0x10);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFSkewMemClk, 0);
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function masks the RdDqsDly Bit 0 before writing to register for UNB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Offset -  Bit offset of the field to be programmed
+ *
+ *     @return    TRUE
+ */
+BOOLEAN
+MemNAdjustRdDqsDlyOffsetUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Offset
+  )
+{
+  *(UINT16*) Offset = *(UINT16*) Offset + 1;
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function delays MEMCLK to prevent WrDqs skew due to negative PRE result.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNCalcWrDqDqsEarlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  DCT_STRUCT     *DCTPtr;
+  CH_DEF_STRUCT  *ChannelPtr;
+  UINT8  Dimm;
+  UINT8  ByteLane;
+  UINT8  *WrDqsDlysPtr;
+  UINT8  NewClkDllDelay;
+  UINT16 ClkDllFineDly;
+  UINT32 AddrCmdTmg;
+
+  TechPtr = NBPtr->TechPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  ASSERT (NBPtr != NULL);
+  ASSERT (ChannelPtr != NULL);
+  ASSERT (DCTPtr != NULL);
+
+  if (NBPtr->IsSupported[WLNegativeDelay]) {
+    if (TechPtr->WLCriticalDelay < 0) {
+      NewClkDllDelay =  (UINT8) ABS (TechPtr->WLCriticalDelay);
+
+      // Prepare new delay for MEMCLK
+      ClkDllFineDly = (UINT16) ((MemNGetBitFieldNb (NBPtr, BFPhyClkDllFine0) & 0xBF60) | NewClkDllDelay);
+
+      // Program bit 7(FenceBit) = 1 if NewClkDllDelay >= > F2x9C[FenceThresholdTxPad], else 0.
+      ClkDllFineDly |= (NewClkDllDelay >= MemNGetBitFieldNb (NBPtr, BFPhyFence)) ? 0x80 : 0;
+
+      // Apply new delay to both chiplets
+      MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine0, ClkDllFineDly | 0x4000);
+      MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine0, ClkDllFineDly);
+      MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine1, ClkDllFineDly | 0x4000);
+      MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine1, ClkDllFineDly);
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tShift MemClk, AddrCmd, CsOdt, Cke by %d to eliminate negative WL\n", NewClkDllDelay);
+
+      //
+      // Adjust AddrCmd/CsOdt/Cke timing by amount MemClk was delayed
+      //
+      AddrCmdTmg = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl);
+      AddrCmdTmg += (NewClkDllDelay << 16) | (NewClkDllDelay << 8) | NewClkDllDelay;
+      AddrCmdTmg &= 0x003F3F3F;
+      MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrCmdTmg);
+
+      //
+      // Adjust all WrDqsDlys on all DIMMs of the current channel
+      //
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS%d\n\t\t\tWrDqs:", Dimm << 1);
+          WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]);
+          for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+            WrDqsDlysPtr[ByteLane] = (UINT8) (WrDqsDlysPtr[ByteLane] + NewClkDllDelay);
+            NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]);
+            IDS_HDT_CONSOLE (MEM_FLOW, " %02x", WrDqsDlysPtr[ByteLane]);
+          }
+          IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+        }
+      }
+    }
+  }
+
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function initializes RxEn Delays for RxEn seedless training
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNInitializeRxEnSeedlessTrainingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 ByteLane;
+  // Save original PRE based RxEnDly for RxEn Seedless training
+  for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+    NBPtr->TechPtr->RxOrig[ByteLane] = NBPtr->ChannelPtr->RcvEnDlys[(NBPtr->TechPtr->ChipSel / NBPtr->CsPerDelay) * NBPtr->TechPtr->DlyTableWidth () + ByteLane];
+  }
+  return TRUE;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function checks each bytelane for no window error.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  MemTTrackRxEnSeedlessRdWrNoWindBLError (NBPtr->TechPtr, OptParam);
+  return TRUE;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *      This function checks each bytelane for small window error.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  MemTTrackRxEnSeedlessRdWrSmallWindBLError (NBPtr->TechPtr, OptParam);
+  return TRUE;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *      This function initializes a ByteLaneError error.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNInitialzeRxEnSeedlessByteLaneErrorUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 ByteLane;
+  for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+    NBPtr->TechPtr->ByteLaneError[ByteLane] = FALSE; // All Bytelanes have no errors
+  }
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function sets phy power saving related settings in different MPstate context.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return    none
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNPhyPowerSavingMPstateUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  STATIC UINT8 Sequence[] = {8, 4, 3, 5, 2, 6, 1, 7, 0};
+  UINT16 DllPower[9];
+  UINT8 NumLanes;
+  UINT8 DllWakeTime;
+  UINT8 MaxRxStggrDly;
+  UINT8 MinRcvEnGrossDly;
+  UINT8 MinWrDatGrossDly;
+  UINT8 dRxStggrDly;
+  UINT8 dTxStggrDly;
+  UINT8 TempStggrDly;
+  UINT8 MaxTxStggrDly;
+  UINT8 Tcwl;
+  UINT8 i;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate);
+  // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b.
+  // 5. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyL] = 1b.
+  // 6. D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0][RxDqsUDllPowerDown] = 1.
+  MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x83);
+  // 7. D18F2x9C_x0D0F_812F_dct[1:0][PARTri] = ~D18F2x90_dct[1:0][ParEn].
+  // 8. D18F2x9C_x0D0F_812F_dct[1:0][Add17Tri, Add16Tri] = {1b, 1b}
+  if (NBPtr->MemPstate == MEMORY_PSTATE0) {
+    MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1);
+  }
+  // 9. IF (DimmsPopulated == 1)&& ((D18F2x9C_x0000_0000_dct[1:0]_mp[1:0][CkeDrvStren]==010b) ||
+  // (D18F2x9C_x0000_0000_dct[1:0]_mp[1:0][CkeDrvStren]==011b)) THEN THEN
+  // program D18F2x9C_x0D0F_C0[40,00]_dct[1:0][LowPowerDrvStrengthEn] = 1
+  // ELSE program D18F2x9C_x0D0F_C0[40,00]_dct[1:0][LowPowerDrvStrengthEn] = 0 ENDIF.
+  if ((NBPtr->ChannelPtr->Dimms == 1) && ((MemNGetBitFieldNb (NBPtr, BFCkeDrvStren) == 2) || (MemNGetBitFieldNb (NBPtr, BFCkeDrvStren) == 3))) {
+    MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100);
+  }
+  // 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
+  // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+  // 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
+  // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
+  // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
+  if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
+    MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
+    MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7);
+    MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7);
+  }
+  // TxCPUpdPeriod = RxCPUpdPeriod = 011b.
+  MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3);
+  MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3);
+  // TxDLLWakeupTime = RxDLLWakeupTime = 11b.
+  MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3);
+  MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3);
+
+  if (NBPtr->IsSupported[DllStaggerEn]) {
+    // 12. Program D18F2x9C_x0D0F_0[F,7:0][5C,1C]_dct[1:0] as follows.
+    // Let Numlanes = 8. = 9 with ECC.
+    NumLanes = (NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8;
+    // RxDllStggrEn = TxDllStggrEn = 1.
+    for (i = 0; i < 9; i ++) {
+      DllPower[i] = 0x8080;
+    }
+    // If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
+    DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
+    // Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4.
+    MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
+    ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4);
+    MaxRxStggrDly = NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly - 4;
+    // Let (real) dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (Numlanes - 1).
+    ASSERT (MaxRxStggrDly >= DllWakeTime);
+    dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (NumLanes - 1);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tMinimum RcvEnGrossDly: 0x%02x MaxRxStggrDly: 0x%02x dRxStggrDly: 0x%02x\n", MinRcvEnGrossDly, MaxRxStggrDly, dRxStggrDly);
+    // For each byte lane in the ordered sequence {8, 4, 3, 5, 2, 6, 1, 7, 0}, program RxDllStggrDly[5:0] = an
+    // increasing value, starting with 0 for the first byte lane in the sequence and increasing at a rate of dRxStggrDly
+    // for each subsequent byte lane. Convert the real to integer by rounding down or using C (int) typecast after linearization.
+    i = 9 - NumLanes;
+    TempStggrDly = 0;
+    for (; i < 9; i ++) {
+      DllPower[Sequence[i]] |= ((TempStggrDly & 0x3F) << 8);
+      TempStggrDly = TempStggrDly + dRxStggrDly;
+    }
+
+    // Let MaxTxStggrDly = (Tcwl*2) + MIN(MIN (WrDatGrossDly for all byte lanes (see
+    // D18F2x9C_x0000_0[3:0]0[2:1]_dct[1:0]_mp[1:0])), MIN(DqsRcvEnGrossDelay for all byte lanes (see
+    // D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4.
+    Tcwl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcwl);
+    MinWrDatGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessWrDatDly, FALSE);
+    MaxTxStggrDly = Tcwl * 2 + MIN (MinRcvEnGrossDly, MinWrDatGrossDly) - 4;
+    // Let dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (Numlanes - 1).
+    ASSERT (MaxTxStggrDly >= DllWakeTime);
+    dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (NumLanes - 1);
+    // For each byte lane in the ordered sequence {8, 4, 3, 5, 2, 6, 1, 7, 0}, program TxDllStggrDly[5:0] = an
+    // increasing integer value, starting with 0 for the first byte lane in the sequence and increasing at a rate of
+    // dTxStggrDly for each subsequent byte lane.
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tMinimum WrDatGrossDly: 0x%02x MaxTxStggrDly: 0x%02x dTxStggrDly: 0x%02x\n", MinWrDatGrossDly, MaxTxStggrDly, dTxStggrDly);
+    i = 9 - NumLanes;
+    TempStggrDly = 0;
+    for (; i < 9; i ++) {
+      DllPower[Sequence[i]] |= (TempStggrDly & 0x3F);
+      TempStggrDly = TempStggrDly + dTxStggrDly;
+    }
+
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane    :  ECC   07   06   05   04   03   02   01   00\n");
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDll Power    : %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
+                     DllPower[8], DllPower[7], DllPower[6], DllPower[5], DllPower[4], DllPower[3], DllPower[2], DllPower[1], DllPower[0]);
+
+    for (i = 0; i < NumLanes; i ++) {
+      MemNSetBitFieldNb (NBPtr, BFDataByteDllPowerMgnByte0 + i, (MemNGetBitFieldNb (NBPtr, BFDataByteDllPowerMgnByte0 + i) & 0x4040) | DllPower[i]);
+    }
+  }
+  // 13. Program D18F2x248_dct[1:0]_mp[1:0] and then D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0] as follows:
+  // For M1 context program RxChMntClkEn=RxSsbMntClkEn=0.
+  // For M0 context program RxChMntClkEn=RxSsbMntClkEn=1.
+  if (NBPtr->MemPstate == MEMORY_PSTATE1) {
+    MemNSetBitFieldNb (NBPtr, BFRxChMntClkEn, 0);
+    MemNSetBitFieldNb (NBPtr, BFRxSsbMntClkEn, 0);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFRxChMntClkEn, 1);
+    MemNSetBitFieldNb (NBPtr, BFRxSsbMntClkEn, 0x100);
+  }
+
+  IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function resets RxFifo pointer during Read DQS training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *OptParam - Optional parameter
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNResetRxFifoPtrClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  if (NBPtr->TechPtr->Direction == DQS_READ_DIR) {
+    MemNSetBitFieldNb (NBPtr, BFRxPtrInitReq, 1);
+    MemNPollBitFieldNb (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  }
+  return TRUE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function adjusts WrDqsBias before seed scaling
+ *
+ *     @param[in,out]   *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *WrDqsBias - Pointer to WrDqsBias
+ *
+ *     @return    FALSE - Supported
+ *     @return    TRUE - Not supported
+ */
+
+BOOLEAN
+MemNAdjustWrDqsBeforeSeedScalingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *WrDqsBias
+  )
+{
+  // Subtract (0x20 * WrDqDqsEarly) since it is a non-scalable component
+  * (INT16 *) WrDqsBias = (INT16) (0x20 * MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly));
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c
new file mode 100644
index 0000000000..445a4659b3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c
@@ -0,0 +1,608 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnreg.c
+ *
+ * Common Northbridge register access functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "merrhdl.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MNREG_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemNSwitchDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  ASSERT (NBPtr->DctCount > Dct);
+  //
+  // Set the DctCfgSel to new DCT
+  //
+  NBPtr->FamilySpecificHook[DCTSelectSwitch] (NBPtr, &Dct);
+  NBPtr->Dct = Dct;
+  NBPtr->MCTPtr->Dct = NBPtr->Dct;
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+  NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]);
+  NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]);
+
+  MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is used by families that use a separate DctCfgSel bit to
+ *     select the current DCT which will be accessed by function 2.
+ *     NOTE:  This function must be called BEFORE the NBPtr->Dct variable is
+ *     updated.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Dct     - Pointer to ID of the target DCT
+ *
+ */
+
+BOOLEAN
+MemNDctCfgSelectUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *Dct
+  )
+{
+  //
+  // Sanity check the current DctCfgSel setting
+  //
+  ASSERT (NBPtr->Dct == NBPtr->GetBitField (NBPtr, BFDctCfgSel));
+  //
+  // Set the DctCfgSel to new DCT
+  //
+  NBPtr->SetBitField (NBPtr, BFDctCfgSel, *(UINT8*)Dct);
+
+  return TRUE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemNSwitchChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = Channel ? 1 : 0;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets a bit field from PCI register
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Field name
+ *
+ *     @return      Bit field value
+ */
+
+UINT32
+MemNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  )
+{
+  UINT32 Value;
+
+  Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0);
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets a bit field from PCI register
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Field name
+ *     @param[in]   Field - Value to be stored in PCT register
+ *
+ */
+
+VOID
+MemNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
+ *  DCTs that are disabled.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be checked
+ *
+ *     @return          TRUE -  All enabled DCTs have the expected value on the bitfield.
+ *     @return          FALSE - Not all enabled DCTs have the expected value on the bitfield.
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNBrdcstCheckNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  UINT8 Dct;
+  UINT8 CurrentDCT;
+  Dct = NBPtr->Dct;
+  for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
+    MemNSwitchDCTNb (NBPtr, CurrentDCT);
+    if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) {
+      if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) {
+        MemNSwitchDCTNb (NBPtr, Dct);
+        return FALSE;
+      }
+    }
+  }
+  MemNSwitchDCTNb (NBPtr, Dct);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Set bitfields of all enabled DCTs on a die to a value. Ignore
+ *  DCTs that are disabled.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be set
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNBrdcstSetNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  UINT8 Dct;
+  UINT8 CurrentDCT;
+  Dct = NBPtr->Dct;
+  for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
+    MemNSwitchDCTNb (NBPtr, CurrentDCT);
+    if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) {
+      MemNSetBitFieldNb (NBPtr, FieldName, Field);
+    }
+  }
+  MemNSwitchDCTNb (NBPtr, Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Set bitfields of all DCTs regardless of if they are being enabled or not on a
+ *  die to a value.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be set
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNBrdcstSetUnConditionalNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  UINT8 Dct;
+  UINT8 CurrentDCT;
+  Dct = NBPtr->Dct;
+  for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
+    MemNSwitchDCTNb (NBPtr, CurrentDCT);
+    MemNSetBitFieldNb (NBPtr, FieldName, Field);
+  }
+  MemNSwitchDCTNb (NBPtr, Dct);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *      This function calculates the memory channel index relative to the
+ *      socket, taking the Die number, the Dct, and the channel.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Dct
+ *     @param[in] Channel
+ *
+ */
+UINT8
+MemNGetSocketRelativeChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  )
+{
+  return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Poll a bitfield. If the bitfield does not get set to the target value within
+ *  specified microseconds, it times out.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be set
+ *     @param[in]   MicroSecond - Number of microsecond to wait
+ *     @param[in]   IfBroadCast - Need to broadcast to both DCT or not
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNPollBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field,
+  IN       UINT32 MicroSecond,
+  IN       BOOLEAN IfBroadCast
+  )
+{
+  BOOLEAN ErrorRecovery;
+  BOOLEAN IgnoreErr;
+  UINT8 ExcludeDCT;
+  UINT16 ExcludeChipSelMask;
+  UINT32 EventInfo;
+  UINT64 InitTSC;
+  UINT64 CurrentTSC;
+  UINT64 TimeOut;
+  AGESA_STATUS EventClass;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  BOOLEAN TimeoutEn;
+
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  ExcludeDCT = EXCLUDE_ALL_DCT;
+  ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL;
+  TimeoutEn = TRUE;
+  IDS_TIMEOUT_CTL (&TimeoutEn);
+
+  CurrentTSC = 0;
+  LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader);
+  TimeOut = InitTSC + ((UINT64) MicroSecond * MemPtr->TscRate);
+
+  while ((CurrentTSC < TimeOut) || !TimeoutEn) {
+    if (IfBroadCast) {
+      if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) {
+        break;
+      }
+    } else {
+      if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) {
+        break;
+      }
+    }
+    LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader);
+  }
+
+  if ((CurrentTSC >= TimeOut) && TimeoutEn) {
+    ErrorRecovery = TRUE;
+    IgnoreErr = FALSE;
+    IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, &MemPtr->StdHeader);
+    IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, &MemPtr->StdHeader);
+
+    // Default event class
+    // If different event class is needed in one entry, override it.
+    EventClass = AGESA_ERROR;
+    switch (FieldName) {
+    case BFDramEnabled:
+      EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tDramEnabled bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFDctAccessDone:
+      EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tDctAccessDone bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFSendCtrlWord:
+      EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tSendCtrlWord bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFPrefDramTrainMode:
+      EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tPrefDramTrainMode bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFEnterSelfRef:
+      EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tEnterSelfRef bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFFreqChgInProg:
+      EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tFreqChgInProg bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFExitSelfRef:
+      EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tExitSelfRef bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFSendMrsCmd:
+      EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tSendMrsCmd bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFSendZQCmd:
+      EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tSendZQCmd bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFDctExtraAccessDone:
+      EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tDctExtraAccessDone bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFMemClrBusy:
+      EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClrBusy bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFMemCleared:
+      EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tMemCleared bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFFlushWr:
+      EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tFlushWr bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    case BFCurNbPstate:
+      EventInfo = MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\tCurNBPstate bitfield times out.\n");
+      ASSERT (ErrorRecovery || IgnoreErr);
+      break;
+    default:
+      EventClass = 0;
+      EventInfo = 0;
+      IDS_ERROR_TRAP;
+    }
+
+    PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader);
+    SetMemError (EventClass, MCTPtr);
+    if (!MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader)) {
+      ASSERT (FALSE);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function changes memory Pstate context
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in]      MemPstate  - Target Memory Pstate
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNChangeMemPStateContextNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSTATE MemPstate
+  )
+{
+  UINT8 PSMasterChannel;
+  UINT8 Dct;
+
+  ASSERT ((MemPstate == 0) || (MemPstate == 1));
+  ASSERT (NBPtr->MemPstate == ((MemNGetBitFieldNb (NBPtr, BFMemPsSel) == 0) ? MEMORY_PSTATE0 : MEMORY_PSTATE1));
+
+  IDS_HDT_CONSOLE (MEM_SETREG, "\nGo to Memory Pstate Conext %d\n", MemPstate);
+  Dct = NBPtr->Dct;
+  MemNSwitchDCTNb (NBPtr, 0);
+  // Figure out what is the master channel
+  PSMasterChannel = (UINT8) (MemNGetBitFieldNb (NBPtr, BFPhyPSMasterChannel) >> 8);
+
+  // Switch to the master channel to change PStateToAccess
+  // PStateToAccess is only effective on the master channel
+  MemNSwitchDCTNb (NBPtr, PSMasterChannel);
+  MemNSetBitFieldNb (NBPtr, BFMemPsSel, MemPstate);
+  MemNSetBitFieldNb (NBPtr, BFPStateToAccess, MemPstate << 8);
+
+  NBPtr->MemPstate = (MemPstate == 0) ? MEMORY_PSTATE0 : MEMORY_PSTATE1;
+  MemNSwitchDCTNb (NBPtr, Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function allocates buffer for NB register table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Handle   - Handle for heap allocation for NBRegTable
+ *
+ *     @return      TRUE  - Successfully allocates buffer the first time
+ *     @return      FALSE - Buffer already allocated or fails to allocate
+ */
+
+BOOLEAN
+MemNAllocateNBRegTableNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       NB_REG_TAB_HANDLE  Handle
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  LOCATE_HEAP_PTR LocHeap;
+
+  // If NBRegTable for this family exists, use it
+  LocHeap.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Handle, 0, 0);
+  if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
+    NBPtr->NBRegTable = (TSEFO *) LocHeap.BufferPtr;
+    return FALSE;
+  }
+
+  // Allocate new buffer for NBRegTable if it has not been allocated
+  AllocHeapParams.RequestedBufferSize = sizeof (TSEFO) * BFEndOfList;
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Handle, 0, 0);
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &(NBPtr->MemPtr->StdHeader))) {
+    ASSERT(FALSE); // NB and Tech Block Heap allocate error
+    return FALSE;
+  }
+  NBPtr->NBRegTable = (TSEFO *)AllocHeapParams.BufferPtr;
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c
new file mode 100644
index 0000000000..cd284bb772
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c
@@ -0,0 +1,269 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mntrain3.c
+ *
+ * Common Northbridge function for training flow for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemNHwWlPart2Nb (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates DQS training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemNDQSTiming3Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 i;
+  BOOLEAN Retval;
+  TechPtr = NBPtr->TechPtr;
+  Retval = TRUE;
+  if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
+    //Execute Technology specific training features
+    i = 0;
+    while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) {
+      if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (NBPtr)) {
+        NBPtr->TrainingSequenceIndex = i;
+        Retval = memTrainSequenceDDR3[i].TrainingSequence (NBPtr);
+        break;
+      }
+      i++;
+    }
+  }
+  return Retval;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates DQS training for Server NB
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+memNSequenceDDR3Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 i;
+  TechPtr = NBPtr->TechPtr;
+  i = NBPtr->TrainingSequenceIndex;
+  if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) {
+    AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n");
+    if (AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {
+      // Right now we do not have anything to do if the callout is implemented
+    }
+    AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
+    //Execute Technology specific training features
+    if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) {
+      TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL);
+      if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) {
+        MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);
+        if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) {
+          MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);
+          if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {
+            MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);
+            // If target speed is higher than start-up speed, do frequency change and second pass of WL
+            do {
+              if (MemNHwWlPart2Nb (TechPtr)) {
+                if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) {
+                  IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));
+                  if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
+                    if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
+                      MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
+                      if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) {
+                        if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) {
+                          MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
+                          if (!NBPtr->FamilySpecificHook[MemPstateStageChange] (NBPtr, NULL)) {
+                            continue;
+                          }
+                          if (NBPtr->Execute1dMaxRdLatTraining) {
+                            do {
+                              if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) {
+                                MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
+                              }
+                            } while (NBPtr->ChangeNbFrequency (NBPtr));
+                          } else {
+                            memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr);
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            } while (NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE);
+          }
+        }
+      }
+    }
+    MemTMarkTrainFail (TechPtr);
+  }
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function executes HW WL at multiple speeds
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @return       TRUE - No errors occurred
+ *                   FALSE - errors occurred
+ */
+
+BOOLEAN
+STATIC
+MemNHwWlPart2Nb (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  BOOLEAN retVal;
+  UINT8 i;
+  retVal = TRUE;
+  i = TechPtr->NBPtr->TrainingSequenceIndex;
+  while ((TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) && (TechPtr->NBPtr->MemPstateStage != MEMORY_PSTATE_1ST_STAGE)) {
+    TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
+    if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) {
+      TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL);
+      if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) {
+        retVal = FALSE;
+        break;
+      }
+      MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2);
+      if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) {
+        retVal = FALSE;
+        break;
+      }
+      MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2);
+    } else {
+      retVal = FALSE;
+      break;
+    }
+  }
+  return retVal;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c
new file mode 100644
index 0000000000..09880798e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c
@@ -0,0 +1,153 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpUtnfm2.c
+ *
+ * Platform specific settings for TN DDR3 UDIMM FM2 system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps/TN/FM2)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define SOCKET_FM2_TN   2
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+//
+// MemClkDis
+//
+STATIC CONST UINT8 ROMDATA TNUDdr3CLKDisFM2[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNClkDisMapEntUFM2 = {
+   {PSCFG_CLKDIS, UDIMM_TYPE + SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FM2_TN, DDR3_TECHNOLOGY},
+   sizeof (TNUDdr3CLKDisFM2) / sizeof (UINT8),
+   (VOID *)&TNUDdr3CLKDisFM2
+};
+
+//
+// ODT tri-state
+//
+STATIC CONST UINT8 ROMDATA TNUDdr3ODTTriFM2[] = {0xFF, 0xFF, 0xFF, 0xFF};
+CONST PSC_TBL_ENTRY TNUDdr3ODTTriEntFM2 = {
+   {PSCFG_ODTTRI, UDIMM_TYPE + SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FM2_TN, DDR3_TECHNOLOGY},
+   sizeof (TNUDdr3ODTTriFM2) / sizeof (UINT8),
+   (VOID *)&TNUDdr3ODTTriFM2
+};
+
+//
+// ChipSel tri-state [UDIMM]
+//
+STATIC CONST UINT8 ROMDATA TNUDdr3CSTriFM2[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNUDdr3CSTriEntFM2 = {
+   {PSCFG_CSTRI, UDIMM_TYPE + SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FM2_TN, DDR3_TECHNOLOGY},
+   sizeof (TNUDdr3CSTriFM2) / sizeof (UINT8),
+   (VOID *)&TNUDdr3CSTriFM2
+};
+
+STATIC CONST PSCFG_S2D_ENTRY ex891_0 [] = {
+  // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable2DTraining
+  {1, DDR1333 + DDR1600 + DDR1866 + DDR2133, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 1},
+  {2, DDR1333 + DDR1600 + DDR1866 + DDR2133, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}
+  };
+CONST PSC_TBL_ENTRY ex891_1  = {
+   {PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FM2_TN, DDR3_TECHNOLOGY},
+   sizeof (ex891_0 ) / sizeof (PSCFG_S2D_ENTRY),
+   (VOID *)&ex891_0
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FP2/mpStnfp2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FP2/mpStnfp2.c
new file mode 100644
index 0000000000..51a4421d80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FP2/mpStnfp2.c
@@ -0,0 +1,196 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpStnfp2.c
+ *
+ * Platform specific settings for TN DDR3 SO-DIMM FP2 system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps/TN/FP2)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define SOCKET_FP2_TN   0
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+// Slow mode, Address timing and Output drive compensation for soldered down SODIMM configuration
+// Format :
+// DimmPerCh,   DDRrate,   VDDIO,   Dimm0,   Dimm1,   Dimm2,   SlowMode,   AddTmgCtl,   ODC
+//
+STATIC CONST PSCFG_SAO_ENTRY TNSODWNSODdr3SAO[] = {
+  {_DIMM_NONE, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222},
+  {_DIMM_NONE, DDR1066, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222},
+  {_DIMM_NONE, DDR1066, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222},
+  {_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20002222},
+  {_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20002222},
+};
+CONST PSC_TBL_ENTRY TNSAOTblEntSODWNSO3 = {
+   {PSCFG_SAO, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNSODWNSODdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
+   (VOID *)&TNSODWNSODdr3SAO
+};
+
+// Dram Term and Dynamic Dram Term for soldered down SODIMM configuration
+// Format :
+// DimmPerCh,   DDRrate,   VDDIO,   Dimm0,   Dimm1,   Dimm2,   Dimm,   Rank,   RttNom,    RttWr
+//
+// RttNom:
+// 0 On die termination disabled
+// 1 60ohms
+// 2 120ohms
+// 3 40ohms
+// 4 20ohms
+// 5 30ohms
+// RttWr:
+// 0 Dynamic termination for writes disabled.
+// 1 60ohms
+// 2 120ohms
+STATIC CONST PSCFG_RTT_ENTRY DramTermTNSODWNSODIMM[] = {
+  {_DIMM_NONE, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+};
+CONST PSC_TBL_ENTRY TNDramTermTblEntSODWNSO = {
+   {PSCFG_RTT, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (DramTermTNSODWNSODIMM) / sizeof (PSCFG_RTT_ENTRY),
+   (VOID *)&DramTermTNSODWNSODIMM
+};
+
+// Max Freq. for soldered down SODIMM configuration
+// Format :
+// DimmPerCh,   Dimms,   SR,   DR,   QR,   Speed1_5V,   Speed1_35V,   Speed1_25V
+//
+STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqTNSODWNSODIMM[] = {
+};
+CONST PSC_TBL_ENTRY TNMaxFreqTblEntSODWNSO = {
+   {PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (MaxFreqTNSODWNSODIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
+   (VOID *)&MaxFreqTNSODWNSODIMM
+};
+
+//
+// MemClkDis
+//
+STATIC CONST UINT8 ROMDATA TNSODdr3CLKDisFP2[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNClkDisMapEntSOFP2 = {
+   {PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FP2_TN, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3CLKDisFP2) / sizeof (UINT8),
+   (VOID *)&TNSODdr3CLKDisFP2
+};
+
+//
+// ODT tri-state
+//
+STATIC CONST UINT8 ROMDATA TNSODdr3ODTTriFP2[] = {0xFF, 0xFF, 0xFF, 0xFF};
+CONST PSC_TBL_ENTRY TNSODdr3ODTTriEntFP2 = {
+   {PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE,  _1DIMM + _2DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FP2_TN, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3ODTTriFP2) / sizeof (UINT8),
+   (VOID *)&TNSODdr3ODTTriFP2
+};
+
+//
+// ChipSel tri-state
+//
+STATIC CONST UINT8 ROMDATA TNSODdr3CSTriFP2[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNSODdr3CSTriEntFP2 = {
+   {PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE,  _1DIMM + _2DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FP2_TN, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3CSTriFP2) / sizeof (UINT8),
+   (VOID *)&TNSODdr3CSTriFP2
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FS1/mpStnfs1.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FS1/mpStnfs1.c
new file mode 100644
index 0000000000..cd8a60d392
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/FS1/mpStnfs1.c
@@ -0,0 +1,142 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpStnfS1.c
+ *
+ * Platform specific settings for TN DDR3 SO-DIMM FS1 system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps/TN/FS1)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define SOCKET_FS1_TN   1
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+//
+// MemClkDis
+//
+STATIC CONST UINT8 ROMDATA TNSODdr3CLKDisFS1[] = {0xFF, 0xFF, 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNClkDisMapEntSOFS1 = {
+   {PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FS1_TN, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3CLKDisFS1) / sizeof (UINT8),
+   (VOID *)&TNSODdr3CLKDisFS1
+};
+
+//
+// ODT tri-state
+//
+STATIC CONST UINT8 ROMDATA TNSODdr3ODTTriFS1[] = {0xFF, 0xFF, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNSODdr3ODTTriEntFS1 = {
+   {PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FS1_TN, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3ODTTriFS1) / sizeof (UINT8),
+   (VOID *)&TNSODdr3ODTTriFS1
+};
+
+//
+// ChipSel tri-state
+//
+STATIC CONST UINT8 ROMDATA TNSODdr3CSTriFS1[] = {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+CONST PSC_TBL_ENTRY TNSODdr3CSTriEntFS1 = {
+   {PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, SOCKET_FS1_TN, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3CSTriFS1) / sizeof (UINT8),
+   (VOID *)&TNSODdr3CSTriFS1
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c
new file mode 100644
index 0000000000..c22a527b43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c
@@ -0,0 +1,203 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpStn.c
+ *
+ * Platform specific settings for TN DDR3 SO-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_TN_MPSTN3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+// Slow mode, Address timing and Output drive compensation for normal SODIMM configuration
+// Format :
+// DimmPerCh,   DDRrate,   VDDIO,   Dimm0,   Dimm1,   Dimm2,   SlowMode,   AddTmgCtl,   ODC
+//
+STATIC CONST PSCFG_SAO_ENTRY TNSODdr3SAO[] = {
+  {_1DIMM, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222},
+  {_1DIMM, DDR1066, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222},
+  {_1DIMM, DDR1066, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222},
+  {_1DIMM, DDR1333, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20002222},
+  {_1DIMM, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20002222},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30112222},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30112222},
+  {_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30112222},
+  {_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30112222},
+  {_2DIMM, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222},
+  {_2DIMM, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000039, 0x10222323},
+  {_2DIMM, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000039, 0x20222323},
+  {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222},
+  {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222},
+  {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000037, 0x30222323},
+  {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20002222},
+  {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20002222},
+  {_2DIMM, DDR1333, VOLT_ALL, DIMM_SR, DIMM_SR, NP, 1, 0x00000035, 0x30222323},
+  {_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000035, 0x30222323},
+  {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30112222},
+  {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30112222},
+};
+CONST PSC_TBL_ENTRY TNSAOTblEntSO3 = {
+   {PSCFG_SAO, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNSODdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
+   (VOID *)&TNSODdr3SAO
+};
+
+// Dram Term and Dynamic Dram Term for normal SODIMM configuration
+// Format :
+// DimmPerCh,   DDRrate,   VDDIO,   Dimm0,   Dimm1,   Dimm2,   Dimm,   Rank,   RttNom,    RttWr
+//
+// RttNom:
+// 0 On die termination disabled
+// 1 60ohms
+// 2 120ohms
+// 3 40ohms
+// 4 20ohms
+// 5 30ohms
+// RttWr:
+// 0 Dynamic termination for writes disabled.
+// 1 60ohms
+// 2 120ohms
+STATIC CONST PSCFG_RTT_ENTRY DramTermTNSODIMM[] = {
+  {_1DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_1DIMM, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_2DIMM, DDR667, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_2DIMM, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
+  {_2DIMM, DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_2DIMM, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
+  {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
+  {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+  {_2DIMM, DDR1333, VOLT_ALL, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2},
+  {_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
+  {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0}
+};
+CONST PSC_TBL_ENTRY TNDramTermTblEntSO = {
+   {PSCFG_RTT, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (DramTermTNSODIMM) / sizeof (PSCFG_RTT_ENTRY),
+   (VOID *)&DramTermTNSODIMM
+};
+
+// Max Freq. for normal SODIMM configuration
+// Format :
+// DimmPerCh,   Dimms,   SR,   DR,   QR,   Speed1_5V,   Speed1_35V,   Speed1_25V
+//
+STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqTNSODIMM[] = {
+  {{_1DIMM, 1, 1, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_1DIMM, 1, 0, 1, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
+  {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}
+};
+CONST PSC_TBL_ENTRY TNMaxFreqTblEntSO = {
+   {PSCFG_MAXFREQ, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (MaxFreqTNSODIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
+   (VOID *)&MaxFreqTNSODIMM
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpUtn3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpUtn3.c
new file mode 100644
index 0000000000..06340ed695
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpUtn3.c
@@ -0,0 +1,205 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpUtn3.c
+ *
+ * Platform specific settings for TN DDR3 UDIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_TN_MPUTN3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+// Slow mode, Address timing and Output drive compensation
+// Format :
+// DimmPerCh,   DDRrate,   VDDIO,   Dimm0,   Dimm1,   Dimm2,   SlowMode,   AddTmgCtl,   ODC
+//
+STATIC CONST PSCFG_SAO_ENTRY TNUDdr3SAO[] = {
+  {_1DIMM, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222},
+  {_1DIMM, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222},
+  {_1DIMM, DDR1066, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222},
+  {_1DIMM, DDR1066, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00380000, 0x10112222},
+  {_1DIMM, DDR1333, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x20112222},
+  {_1DIMM, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00360000, 0x20112222},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x00000000, 0x30112222},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00000000, 0x30112222},
+  {_1DIMM, DDR1866 + DDR2133, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30112222},
+  {_1DIMM, DDR1866 + DDR2133, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30112222},
+  {_2DIMM, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222},
+  {_2DIMM, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222},
+  {_2DIMM, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222322},
+  {_2DIMM, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222322},
+  {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222},
+  {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00380000, 0x10112222},
+  {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00350037, 0x30222322},
+  {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x20112222},
+  {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00360000, 0x20112222},
+  {_2DIMM, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000035, 0x30222322},
+  {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x00000000, 0x30112222},
+  {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00000000, 0x30112222},
+  {_2DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x0000002B, 0x30222322},
+  {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000033, 0x30222322},
+  {_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30112222},
+  {_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30112222},
+  {_2DIMM, DDR1866, V1_5, DIMM_SR, DIMM_SR, NP, 1, 0x00000031, 0x30222322},
+};
+CONST PSC_TBL_ENTRY TNSAOTblEntU3 = {
+   {PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNUDdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
+   (VOID *)&TNUDdr3SAO
+};
+
+// Dram Term and Dynamic Dram Term
+// Format :
+// DimmPerCh,   DDRrate,   VDDIO,   Dimm0,   Dimm1,   Dimm2,   Dimm,   Rank,   RttNom,    RttWr
+//
+// RttNom:
+// 0 On die termination disabled
+// 1 60ohms
+// 2 120ohms
+// 3 40ohms
+// 4 20ohms
+// 5 30ohms
+// RttWr:
+// 0 Dynamic termination for writes disabled.
+// 1 60ohms
+// 2 120ohms
+STATIC CONST PSCFG_RTT_ENTRY DramTermTNUDIMM[] = {
+  {_1DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_1DIMM, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0},
+  {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0},
+  {_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_1DIMM, DDR2133, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_2DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+  {_2DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
+  {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+  {_2DIMM, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
+  {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_2DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1},
+  {_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 0},
+  {_2DIMM, DDR1866, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1},
+};
+CONST PSC_TBL_ENTRY TNDramTermTblEntU = {
+   {PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (DramTermTNUDIMM) / sizeof (PSCFG_RTT_ENTRY),
+   (VOID *)&DramTermTNUDIMM
+};
+
+// Max Freq.
+// Format :
+// DimmPerCh,   Dimms,   SR,   DR,   QR,   Speed1_5V,   Speed1_35V,   Speed1_25V
+//
+STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqTNUDIMM[] = {
+  {{_1DIMM, 1, 1, 0, 0, DDR2133_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_1DIMM, 1, 0, 1, 0, DDR2133_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 1, 1, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 1, 0, 1, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 2, 2, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
+  {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}
+};
+CONST PSC_TBL_ENTRY TNMaxFreqTblEntU = {
+   {PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (MaxFreqTNUDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
+   (VOID *)&MaxFreqTNUDIMM
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c
new file mode 100644
index 0000000000..2b3e4a8e0c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mptn3.c
+ *
+ * Platform specific settings for TN
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps/TN)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "Filecode.h"
+
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+
+#define FILECODE PROC_MEM_PS_TN_MPTN3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+//
+// Common tables of TN platform specific configuration
+//
+
+// MR0[WR]
+// Format :
+// D18F2x22C_dct[1:0][Twr], MR0[WR]
+//
+CONST PSCFG_MR0WR_ENTRY TNMR0WR[] = {
+  {0x10, 0},
+  {0x05, 1},
+  {0x06, 2},
+  {0x07, 3},
+  {0x08, 4},
+  {0x0A, 5},
+  {0x0C, 6},
+  {0x0E, 7}
+};
+CONST PSC_TBL_ENTRY TNMR0WrTblEntry = {
+   {PSCFG_MR0WR, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNMR0WR) / sizeof (PSCFG_MR0WR_ENTRY),
+   (VOID *)&TNMR0WR
+};
+
+// MR0[CL]
+// Format :
+// D18F2x200_dct[1:0][Tcl], MR0[CL][3:1], MR0[CL][0]
+//
+CONST PSCFG_MR0CL_ENTRY TNMR0CL[] = {
+  {0x05, 1, 0},
+  {0x06, 2, 0},
+  {0x07, 3, 0},
+  {0x08, 4, 0},
+  {0x09, 5, 0},
+  {0x0A, 6, 0},
+  {0x0B, 7, 0},
+  {0x0C, 0, 1},
+  {0x0D, 1, 1},
+  {0x0E, 2, 1},
+  {0x0F, 3, 1},
+  {0x10, 4, 1}
+};
+CONST PSC_TBL_ENTRY TNMR0CLTblEntry = {
+   {PSCFG_MR0CL, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNMR0CL) / sizeof (PSCFG_MR0CL_ENTRY),
+   (VOID *)&TNMR0CL
+};
+
+// ODT pattern
+// Format:
+//  Dimm0, Dimm1  RdODTCSHigh,   RdODTCSLow,   WrODTCSHigh,   WrODTCSLow
+//
+STATIC CONST PSCFG_2D_ODTPAT_ENTRY TNOdtPat[] = {
+  {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00040000},
+  {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08040000},
+  {DIMM_SR, NP, 0x00000000, 0x00000000, 0x00000000, 0x00000001},
+  {DIMM_DR, NP, 0x00000000, 0x00000000, 0x00000000, 0x00000201},
+  {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010404, 0x00000000, 0x09050605}
+};
+CONST PSC_TBL_ENTRY TNOdtPatTblEnt = {
+   {PSCFG_ODT_PAT_2D, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNOdtPat) / sizeof (PSCFG_2D_ODTPAT_ENTRY),
+   (VOID *)&TNOdtPat
+};
+
+//
+// CKE tri-state
+//
+STATIC CONST UINT8 ROMDATA TNDdr3CKETri[] = {0xFF, 0xFF};
+CONST PSC_TBL_ENTRY TNDdr3CKETriEnt = {
+   {PSCFG_CKETRI, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_TN, (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull)  }, PT_DONT_CARE, DDR3_TECHNOLOGY},
+   sizeof (TNDdr3CKETri) / sizeof (UINT8),
+   (VOID *)&TNDdr3CKETri
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
new file mode 100644
index 0000000000..b269423095
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
@@ -0,0 +1,1246 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mp.c
+ *
+ * Common platform specific configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_MP_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define PSO_TYPE    0
+#define PSO_LENGTH  1
+#define PSO_DATA    2
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPPSCGen (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+BOOLEAN
+STATIC
+MemPCheckTblDrvOverrideConfig (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+BOOLEAN
+STATIC
+MemPCheckTblDrvOverrideConfigSpeedLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+VOID
+STATIC
+MemPTblDrvOverrideSpeedLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+UINT8
+STATIC
+MemPTblDrvOverrideODT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+VOID
+STATIC
+MemPTblDrvOverrideODTPattern (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+UINT8
+STATIC
+MemPTblDrvOverrideRC2IBT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer,
+  IN       UINT8 NumOfReg
+  );
+
+BOOLEAN
+STATIC
+MemPTblDrvOverrideMR0WR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+BOOLEAN
+STATIC
+MemPTblDrvOverrideMR0CL (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+BOOLEAN
+STATIC
+MemPTblDrvOverrideMR10OpSpeed (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This is the default return function of the Platform Specific block. The function always
+ *    returns   AGESA_UNSUPPORTED
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in]       *PsPtr            Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_UNSUPPORTED  AGESA status indicating that default is unsupported
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  return AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function will set the DramTerm and DramTermDyn in the structure of a channel.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *     @param[in]       ArraySize        Size of the array of DramTerm
+ *     @param[in]       *DramTermPtr     Address the array of DramTerm
+ *
+ *     @return          TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population.
+ *
+ */
+BOOLEAN
+MemPGetDramTerm (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ArraySize,
+  IN       CONST DRAM_TERM_ENTRY *DramTermPtr
+  )
+{
+  UINT8 Dimms;
+  UINT8 QR_Dimms;
+  UINT8 i;
+  Dimms = NBPtr->ChannelPtr->Dimms;
+  QR_Dimms = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+    if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) {
+      QR_Dimms ++;
+    }
+  }
+
+  for (i = 0; i < ArraySize; i ++) {
+    if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) {
+      if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) {
+        if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) ||
+            ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) ||
+            (DramTermPtr[i].QR_Dimms == ANY_NUM)) {
+          NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm;
+          NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm;
+          NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm;
+          break;
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function gets the highest POR supported speed.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *     @param[in]       FreqLimitSize    Size of the array of Frequency Limit
+ *     @param[in]       *FreqLimitPtr     Address the array of Frequency Limit
+ *
+ *     @return          UINT8 - frequency limit
+ *
+ */
+UINT16
+MemPGetPorFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 FreqLimitSize,
+  IN       CONST POR_SPEED_LIMIT *FreqLimitPtr
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 DimmTpMatch;
+  UINT16 SpeedLimit;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+
+  SpeedLimit = 0;
+  DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr);
+  for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) {
+    if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == FreqLimitPtr->Dimms) {
+      if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+        SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V;
+        break;
+      } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) {
+        SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V;
+        break;
+      } else {
+        SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V;
+        break;
+      }
+    }
+  }
+
+  return SpeedLimit;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function is the default function for getting POR speed limit. When a
+ *    package does not need to cap the speed, it should use this function to initialize
+ *    the corresponding function pointer.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ */
+VOID
+MemPGetPORFreqLimitDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function gets the seed value of WL and HW RxEn pass 1 training.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Entries are found
+ *     @return          FALSE - Entries are not found
+ *
+ */
+BOOLEAN
+MemPGetPSCPass1Seed (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  UINT8 Dct;
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    i = 0;
+    while (memPlatSpecFlowArray[i] != NULL) {
+      if (!(memPlatSpecFlowArray[i])->TrainingSeedVal (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+        return FALSE;
+      }
+      i++;
+    }
+  }
+
+  return TRUE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
+ *    and so on.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Successfully execute platform specific configuration flow.
+ *     @return          FALSE - Fail to execute platform specific configuration flow.
+ *
+ */
+BOOLEAN
+MemPPSCFlow (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  BOOLEAN Result;
+
+  Result = TRUE;
+  i = 0;
+  while (memPlatSpecFlowArray[i] != NULL) {
+    if ((memPlatSpecFlowArray[i])->DramTerm (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+      if ((memPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+        if ((memPlatSpecFlowArray[i])->SAO (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+          if ((memPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+            if ((memPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+              if ((memPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+                if ((memPlatSpecFlowArray[i])->LRIBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+                  if ((memPlatSpecFlowArray[i])->LRNPR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+                    if ((memPlatSpecFlowArray[i])->LRNLR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+                      if (MemPPSCGen (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
+                        break;
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+    i++;
+  }
+
+  IDS_SKIP_HOOK (IDS_ENFORCE_PLAT_TABLES, NBPtr, &(NBPtr->MemPtr->StdHeader)) {
+    if (memPlatSpecFlowArray[i] == NULL) {
+      Result = FALSE;
+    }
+  }
+  return Result;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
+ *     of dimm in the table.
+ *
+ *     @param[in]       Dimm0       Rank type of Dimm0
+ *     @param[in]       Dimm1       Rank type of Dimm1
+ *     @param[in]       Dimm2       Rank type of Dimm2
+ *     @param[in, out]       *RankTypeInTable       Pointer to RankTypeInTable variable
+ *
+ *
+ */
+VOID
+MemPConstructRankTypeMap (
+  IN       UINT16 Dimm0,
+  IN       UINT16 Dimm1,
+  IN       UINT16 Dimm2,
+  IN OUT   UINT16 *RankTypeInTable
+  )
+{
+  UINT8 i;
+  UINT16 RT;
+  UINT8 BitShift;
+
+  *RankTypeInTable = 0;
+  RT = 0;
+  BitShift = 0;
+
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    switch (i) {
+    case 0:
+      RT = (Dimm0 == 0) ? NP : Dimm0;
+      BitShift = 0;
+      break;
+    case 1:
+      RT = (Dimm1 == 0) ? NP : Dimm1;
+      BitShift = 4;
+      break;
+    case 2:
+      RT = (Dimm2 == 0) ? NP : Dimm2;
+      BitShift = 8;
+      break;
+    default:
+      // dimm3 is not used, fills nibble3 with "NP"
+      RT = NP;
+      BitShift = 12;
+    }
+    *RankTypeInTable |= RT << BitShift;
+  }
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemPIsIdSupported
+ *      This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
+ *      determine if it is supported by this NB type.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       LogicalId - CPU_LOGICAL_ID
+ *     @param[in]       PackageType - Package Type
+ *
+ *     @return          TRUE -  NB type is matched !
+ *     @return          FALSE - NB type is not matched !
+ *
+ */
+BOOLEAN
+MemPIsIdSupported (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID LogicalId,
+  IN       UINT8 PackageType
+  )
+{
+  CPUID_DATA CpuId;
+  UINT8 PkgType;
+
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader));
+  PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+
+  if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0)
+      && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) {
+    if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) {
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function returns the rank type map of a channel.
+ *
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          UINT16 - The map of rank type.
+ *
+ */
+UINT16
+MemPGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  UINT8 i;
+  UINT16 DIMMRankType;
+
+  DIMMRankType = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if (CurrentChannel->MCTPtr->Status[SbLrdimms]) {
+      // For LrDimm, we construct the map according to Dimm present bits rather than rank type bits
+      if ((CurrentChannel->LrDimmPresent & (UINT8) 1 << i) != 0) {
+        DIMMRankType |= (UINT16) DIMM_LR << (i << 2);
+      } else {
+        DIMMRankType |= (UINT16) NP << (i << 2);
+      }
+    } else {
+      if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
+        if (i < 2) {
+          DIMMRankType |= (UINT16) DIMM_QR << (i << 2);
+        }
+      } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
+        DIMMRankType |= (UINT16) DIMM_DR << (i << 2);
+      } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
+        DIMMRankType |= (UINT16) DIMM_SR << (i << 2);
+      } else {
+        DIMMRankType |= (UINT16) NP << (i << 2);
+      }
+    }
+  }
+
+  return DIMMRankType;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function performs the action for the rest of platform specific configuration such as
+ *    tri-state stuff
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables       Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - No error occurred.
+ *     @return          FALSE - Error occurred.
+ *
+ */
+BOOLEAN
+STATIC
+MemPPSCGen (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  PSCFG_TYPE PSCType;
+  DIMM_TYPE DimmType;
+  UINT8 MaxDimmPerCh;
+  UINT8 NOD;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  CH_DEF_STRUCT *CurrentChannel;
+  UINT32 EventInfo;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
+
+  if (CurrentChannel->RegDimmPresent != 0) {
+    DimmType = RDIMM_TYPE;
+  } else if (CurrentChannel->SODimmPresent != 0) {
+    DimmType = SODIMM_TYPE;
+  } else if (CurrentChannel->LrDimmPresent != 0) {
+    DimmType = LRDIMM_TYPE;
+  } else {
+    DimmType = UDIMM_TYPE;
+  }
+
+  for (PSCType = PSCFG_GEN_START + 1; PSCType < PSCFG_GEN_END; PSCType++) {
+    i = 0;
+    while (EntryOfTables->TblEntryOfGen[i] != NULL) {
+      if ((EntryOfTables->TblEntryOfGen[i])->Header.PSCType == PSCType) {
+        if (((EntryOfTables->TblEntryOfGen[i])->Header.DimmType & DimmType) != 0) {
+          if (((EntryOfTables->TblEntryOfGen[i])->Header.NumOfDimm & NOD) != 0) {
+            //
+            // Determine if this is the expected NB Type
+            //
+            LogicalCpuid = (EntryOfTables->TblEntryOfGen[i])->Header.LogicalCpuid;
+            PackageType = (EntryOfTables->TblEntryOfGen[i])->Header.PackageType;
+            if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+              break;
+            }
+          }
+        }
+      }
+      i++;
+    }
+
+    // Check whether no table entry is found.
+    if (EntryOfTables->TblEntryOfGen[i] == NULL) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s Table\n", (PSCType == PSCFG_CLKDIS) ? "ClkDis" : ((PSCType == PSCFG_CKETRI) ? "CkeTri" : ((PSCType == PSCFG_ODTTRI) ? "OdtTri" : "CsTri")));
+      EventInfo = (PSCType == PSCFG_CLKDIS) ? MEM_ERROR_CLK_DIS_MAP_NOT_FOUND : ((PSCType == PSCFG_CKETRI) ? MEM_ERROR_CKE_TRI_MAP_NOT_FOUND : ((PSCType == PSCFG_ODTTRI) ? MEM_ERROR_ODT_TRI_MAP_NOT_FOUND : MEM_ERROR_CS_TRI_MAP_NOT_FOUND));
+      PutEventLog (AGESA_ERROR, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+      if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+      }
+      return FALSE;
+    }
+
+    // Perform the action for specific PSCType.
+    if (PSCType == PSCFG_CLKDIS) {
+      CurrentChannel->MemClkDisMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
+    } else if (PSCType == PSCFG_CKETRI) {
+      CurrentChannel->CKETriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
+    } else if (PSCType == PSCFG_ODTTRI) {
+      CurrentChannel->ODTTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
+    } else if (PSCType == PSCFG_CSTRI) {
+      CurrentChannel->ChipSelTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
+    }
+  }
+
+  CurrentChannel->DctEccDqsLike = 0x0403;
+  CurrentChannel->DctEccDqsScale = 0x70;
+
+  return TRUE;
+}
+
+
+ /* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function proceeds Table Driven Overriding.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] PlatformMemoryConfiguration - Pointer to Platform config table
+ *     @param[in] ProceededPSOType - Proceeded PSO type
+ *
+ *     @return          bit0 ~ bit7 - Overriding CS or DIMM map.
+ *     @return          bit15         - Invalid entry found if set.
+ *
+ */
+UINT16
+MemPProceedTblDrvOverride (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 ProceededPSOType
+  )
+{
+  UINT8 *Buffer;
+  UINT8 *PSOStartPtr;
+  UINT8 NumOfReg;
+  UINT8 RetVal;
+  UINT16 RetVal16;
+  BOOLEAN ConfigMatched;
+  BOOLEAN FirstGoThrough;
+  BOOLEAN FindNewConfig;
+  BOOLEAN InvertRetVal;
+  BOOLEAN InvalidConfigDetected;
+
+
+  ASSERT (PlatformMemoryConfiguration != NULL);
+  ASSERT ((ProceededPSOType >= PSO_TBLDRV_START) && (ProceededPSOType <= PSO_TBLDRV_END));
+
+  NumOfReg = 0;
+  RetVal = 0;
+  RetVal16 = 0;
+  FirstGoThrough = TRUE;
+  InvertRetVal = FALSE;
+  InvalidConfigDetected = FALSE;
+  //
+  //   << P E R S P E C T I V E >>
+  //
+  //   PlatformMemoryConfiguration [] = {
+  //     . . . . . . . . . . . . . . . . . . .
+  //     . . . . . . . . . . . . . . . . . . .
+  //    TBLDRV_CONFIG_TO_OVERRIDE (2, DDR1600, VOLT1_5_ + VOLT1_35_, SR_DIMM0 + DR_DIMM1),
+  //       TBLDRV_CONFIG_ENTRY_RTTNOM (CS2_ + CS3_, 2),
+  //       TBLDRV_CONFIG_ENTRY_RTTWR (CS2_, 2),
+  //       TBLDRV_CONFIG_ENTRY_RTTWR (CS3_, 1),
+  //       TBLDRV_CONFIG_ENTRY_ADDRTMG (0x003C3C3C),
+  //       TBLDRV_CONFIG_ENTRY_ODCCTRL (0x20112222),
+  //
+  //     TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE (2, 2, 0, 0)
+  //       TBLDRV_CONFIG_ENTRY_SPEEDLIMIT (DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY),
+  //
+  //     TBLDRV_CONFIG_TO_OVERRIDE (2, DDR1333, VOLT1_5_ + VOLT1_35_, SR_DIMM0 + DR_DIMM1),
+  //       TBLDRV_CONFIG_ENTRY_RTTNOM (CS2_ + CS3_, 3),
+  //       TBLDRV_CONFIG_ENTRY_RTTWR (CS2_ + CS3_, 0),
+  //
+  //     TBLDRV_OVERRIDE_MR0_WR (3, 5)
+  //     TBLDRV_OVERRIDE_MR0_WR (4, 6)
+  //
+  //     TBLDRV_OVERRIDE_MR0_CL (3, 5)
+  //     TBLDRV_OVERRIDE_MR0_CL (4, 6)
+  //     . . . . . . . . . . . . . . . . . . .
+  //     . . . . . . . . . . . . . . . . . . .
+  //
+  //     PSO_END
+  //   }
+  //
+  Buffer = PlatformMemoryConfiguration;
+  // Look for configuration descriptor and its sub-descriptor.
+  while (Buffer[PSO_TYPE] != PSO_END) {
+    FindNewConfig = FALSE;
+    ConfigMatched = FALSE;
+    if (Buffer[PSO_TYPE] == PSO_TBLDRV_CONFIG) {
+      //
+      // Config. descriptor is found, check its sub-descriptor to execute different checking routine.
+      //
+      if ((Buffer[PSO_DATA] == CONFIG_SPEEDLIMIT) && (ProceededPSOType == PSO_TBLDRV_SPEEDLIMIT)) {
+        if (MemPCheckTblDrvOverrideConfigSpeedLimit (NBPtr, &Buffer[PSO_DATA + 1])) {
+          ConfigMatched = TRUE;
+        }
+      } else if (Buffer[PSO_DATA] == CONFIG_DONT_CARE) {
+        ConfigMatched = TRUE;
+      } else {
+        if (MemPCheckTblDrvOverrideConfig (NBPtr, &Buffer[PSO_DATA + 1])) {
+          ConfigMatched = TRUE;
+          if ((Buffer[PSO_DATA] == CONFIG_RC2IBT) && (ProceededPSOType == PSO_TBLDRV_RC2_IBT)) {
+            NumOfReg = Buffer[PSO_DATA + 9];
+          }
+        }
+      }
+    }
+
+    if (ConfigMatched) {
+      //
+      // If config. is matched, parsing "Table Driven PSO" macros behinds this config. macro until PSO_END is reached.
+      //
+      PSOStartPtr = Buffer + (Buffer[PSO_LENGTH] + 2);
+      // Look for the current proceeded PSO type in PlatformMemoryConfiguration array.
+      while ((PSOStartPtr[PSO_TYPE] != PSO_END)) {
+        if (PSOStartPtr[PSO_TYPE] == PSO_TBLDRV_CONFIG) {
+          //
+          // If there is an additional config. macro existed, break this while loop,
+          // then check its content with real platform config. again.
+          // If matched, parsing "Table Driven PSO" macros behind it.
+          //
+          Buffer = PSOStartPtr;
+          FindNewConfig = TRUE;
+          break;
+        } else if (PSOStartPtr[PSO_TYPE] == PSO_TBLDRV_INVALID_TYPE) {
+          InvalidConfigDetected = TRUE;
+          break;
+        }
+
+        if (PSOStartPtr[PSO_TYPE] == ProceededPSOType) {
+          //
+          // Pre-set overriding Cs/Dimm map to "0xFF" for the types which are regardless of Cs/Dimm
+          // for the first time going through the overriding routines.
+          //
+          if (FirstGoThrough) {
+            RetVal = 0xFF;
+          }
+          switch (ProceededPSOType) {
+          case PSO_TBLDRV_SPEEDLIMIT :
+            MemPTblDrvOverrideSpeedLimit (NBPtr, &PSOStartPtr[PSO_DATA]);
+            break;
+
+          case PSO_TBLDRV_ODT_RTTNOM :
+          case PSO_TBLDRV_ODT_RTTWR :
+            // Mask off Cs overridng map to record which Cs has been overridden.
+            RetVal &= ~ MemPTblDrvOverrideODT (NBPtr, &PSOStartPtr[PSO_TYPE]);
+            // Indicate RetVal is inverted.
+            InvertRetVal = TRUE;
+            break;
+
+          case PSO_TBLDRV_ODTPATTERN :
+            MemPTblDrvOverrideODTPattern (NBPtr, &PSOStartPtr[PSO_DATA]);
+            break;
+
+          case PSO_TBLDRV_ADDRTMG :
+            NBPtr->ChannelPtr->DctAddrTmg = *(UINT32 *)&PSOStartPtr[PSO_DATA];
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: AddrTmg = 0x%x for Dct%d\n\n", *(UINT32 *)&PSOStartPtr[PSO_DATA], NBPtr->Dct);
+            break;
+
+          case PSO_TBLDRV_ODCCTRL :
+            NBPtr->ChannelPtr->DctOdcCtl = *(UINT32 *)&PSOStartPtr[PSO_DATA];
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: OdcCtl = 0x%x for Dct%d\n\n", *(UINT32 *)&PSOStartPtr[PSO_DATA], NBPtr->Dct);
+            break;
+
+          case PSO_TBLDRV_SLOWACCMODE :
+            NBPtr->ChannelPtr->SlowMode = (PSOStartPtr[PSO_DATA] == 1) ? TRUE : FALSE;
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Slow Access Mode = %d for Dct%d\n\n", PSOStartPtr[PSO_DATA], NBPtr->Dct);
+            break;
+
+          case PSO_TBLDRV_RC2_IBT :
+            // Mask off Dimm overridng map to record which Dimm has been overridden.
+            RetVal &= ~ MemPTblDrvOverrideRC2IBT (NBPtr, &PSOStartPtr[PSO_DATA], NumOfReg);
+            // Indicate RetVal is inverted.
+            InvertRetVal = TRUE;
+            break;
+
+          case PSO_TBLDRV_MR0_CL :
+            RetVal = 0;
+            if (MemPTblDrvOverrideMR0WR (NBPtr, &PSOStartPtr[PSO_DATA])) {
+              RetVal = 0xFF;
+            }
+            break;
+
+          case PSO_TBLDRV_MR0_WR :
+            RetVal = 0;
+            if (MemPTblDrvOverrideMR0CL (NBPtr, &PSOStartPtr[PSO_DATA])) {
+              RetVal = 0xFF;
+            }
+            break;
+
+          case PSO_TBLDRV_RC10_OPSPEED :
+            RetVal = 0;
+            if (MemPTblDrvOverrideMR10OpSpeed (NBPtr, &PSOStartPtr[PSO_DATA])) {
+              RetVal = 0xFF;
+            }
+            break;
+
+          case PSO_TBLDRV_LRDIMM_IBT :
+            NBPtr->PsPtr->F0RC8 = PSOStartPtr[PSO_DATA];
+            NBPtr->PsPtr->F1RC0 = PSOStartPtr[PSO_DATA + 1];
+            NBPtr->PsPtr->F1RC1 = PSOStartPtr[PSO_DATA + 2];
+            NBPtr->PsPtr->F1RC2 = PSOStartPtr[PSO_DATA + 3];
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: LRDIMM IBT for Dct%d\n", NBPtr->Dct);
+            IDS_HDT_CONSOLE (MEM_FLOW, "\nF0RC8 = %d, F1RC0 = %d, F1RC1 = %d, F1RC2 = %d", PSOStartPtr[PSO_DATA], PSOStartPtr[PSO_DATA + 1], \
+                                        PSOStartPtr[PSO_DATA + 2], PSOStartPtr[PSO_DATA + 3]);
+            break;
+
+
+          default:
+            ASSERT (FALSE);
+          }
+          FirstGoThrough = FALSE;
+        }
+         PSOStartPtr += (PSOStartPtr[PSO_LENGTH] + 2);
+      }
+
+      if (FindNewConfig) {
+        continue;
+      }
+      RetVal = (InvertRetVal) ? ~RetVal : RetVal;
+      RetVal16 = (UINT16) RetVal;
+      if (InvalidConfigDetected) {
+        RetVal16 |= INVALID_CONFIG_FLAG;
+      }
+
+      return RetVal16;
+    }
+     Buffer += (Buffer[PSO_LENGTH] + 2);
+  }
+
+  RetVal = (InvertRetVal) ? ~RetVal : RetVal;
+  RetVal16 = (UINT16) RetVal;
+  if (InvalidConfigDetected) {
+    RetVal16 |= INVALID_CONFIG_FLAG;
+  }
+  return RetVal16;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides the speed limit.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ */
+VOID
+STATIC
+MemPTblDrvOverrideSpeedLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  UINT8 CurrentVoltage;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Max. Memory Speed for Dct%d\n", NBPtr->Dct);
+
+  LibAmdMemCopy (NBPtr->PsPtr->SpeedLimit, Buffer, 6, &(NBPtr->MemPtr->StdHeader));
+
+  for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz\t", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), NBPtr->PsPtr->SpeedLimit[CurrentVoltage]);
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides the ODTs (RttNom and RttWr).
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ *     @return          Target CS overriding bit map
+ *
+ */
+UINT8
+STATIC
+MemPTblDrvOverrideODT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  UINT16 i;
+  UINT8 TgtCS;
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: ODT for Dct%d\n", NBPtr->Dct);
+    if (Buffer[0] == PSO_TBLDRV_ODT_RTTNOM) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "RttNom = %d for ", Buffer[3]);
+    } else {
+      IDS_HDT_CONSOLE (MEM_FLOW, "RttWr = %d for ", Buffer[3]);
+    }
+  );
+
+  TgtCS = Buffer[2];
+  for (i = 0; i < MAX_CS_PER_CHANNEL; i++) {
+    if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << i)) != 0) {
+      if ((TgtCS & (UINT8) 1 << i) != 0) {
+        IDS_HDT_CONSOLE (MEM_FLOW, "CS%d  ", i);
+        if (Buffer[0] == PSO_TBLDRV_ODT_RTTNOM) {
+          NBPtr->PsPtr->RttNom[i] = Buffer[3];
+        } else {
+          NBPtr->PsPtr->RttWr[i] = Buffer[3];
+        }
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+
+  return TgtCS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides the ODT patterns.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ */
+VOID
+STATIC
+MemPTblDrvOverrideODTPattern (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: ODT pattern for Dct%d\n", NBPtr->Dct);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nRODTCSHigh = 0x%x\n", *(UINT32 *)&Buffer[0]);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nRODTCSLow = 0x%x\n", *(UINT32 *)&Buffer[4]);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nWODTCSHigh = 0x%x\n", *(UINT32 *)&Buffer[8]);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nWODTCSLow = 0x%x\n", *(UINT32 *)&Buffer[12]);
+
+  CurrentChannel->PhyRODTCSHigh = *(UINT32 *)&Buffer[0];
+  CurrentChannel->PhyRODTCSLow = *(UINT32 *)&Buffer[4];
+  CurrentChannel->PhyWODTCSHigh = *(UINT32 *)&Buffer[8];
+  CurrentChannel->PhyWODTCSLow = *(UINT32 *)&Buffer[12];
+
+  //WL ODTs need to be modified as well while overriding...
+  CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F);
+  CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow  >> 16) & 0x0F);
+  CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F);
+  CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides the Ctrl Word 2 and 8.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *     @param[in]       NumOfReg  - Number of registers
+ *
+ *     @return          Target DIMM overridng bit map
+ *
+ */
+UINT8
+STATIC
+MemPTblDrvOverrideRC2IBT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer,
+  IN       UINT8 NumOfReg
+  )
+{
+  UINT16 i;
+  UINT8 TgtDimm;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: RC2[IBT] for Dct%d\n", NBPtr->Dct);
+  IDS_HDT_CONSOLE (MEM_FLOW, "RC2[IBT] = %d for ", Buffer[1]);
+
+  TgtDimm = Buffer[0];
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if ((CurrentChannel->ChDimmValid & (UINT16) (1 << i)) != 0) {
+      if (((TgtDimm & (UINT8) 1 << i) != 0) && (NBPtr->PsPtr->NumOfReg[i] == NumOfReg)) {
+        IDS_HDT_CONSOLE (MEM_FLOW, "DIMM%d  ", i);
+        CurrentChannel->CtrlWrd02[i] = (Buffer[1] & 0x1) << 2;
+        CurrentChannel->CtrlWrd08[i] = (Buffer[1] & 0xE) >> 1;
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+
+  return TgtDimm;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides MR0[WR].
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ *     @return          TRUE : Overridden
+ *     @return          FALSE : Not overriden
+ *
+ */
+BOOLEAN
+STATIC
+MemPTblDrvOverrideMR0WR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  if (Buffer[0] == (UINT8) NBPtr->GetBitField (NBPtr, BFTcl)) {
+    NBPtr->PsPtr->MR0CL31 = Buffer[1];
+    NBPtr->PsPtr->MR0CL0 = Buffer[2];
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR0[CL][3:1] = %d,\tMR0[CL][0] = %d for Dct%d\n", \
+                                     Buffer[1], Buffer[2], NBPtr->Channel);
+    IDS_HDT_CONSOLE (MEM_FLOW, "Tcl = %d\n\n", (UINT8) NBPtr->GetBitField (NBPtr, BFTcl));
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides MR0[WR].
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ *     @return          TRUE : Overridden
+ *     @return          FALSE : Not overriden
+ *
+ */
+BOOLEAN
+STATIC
+MemPTblDrvOverrideMR0CL (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  if (Buffer[0] == (UINT8) NBPtr->GetBitField (NBPtr, BFTwrDDR3)) {
+    NBPtr->PsPtr->MR0WR = Buffer[1];
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR0[WR] = %d for Dct%d\n", Buffer[1], NBPtr->Dct);
+    IDS_HDT_CONSOLE (MEM_FLOW, "Twr = %d\n\n", (UINT8) NBPtr->GetBitField (NBPtr, BFTwrDDR3));
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides MR10[OperatingSpeed].
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ *     @return          TRUE : Overridden
+ *     @return          FALSE : Not overriden
+ *
+ */
+BOOLEAN
+STATIC
+MemPTblDrvOverrideMR10OpSpeed (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  UINT32 CurDDRrate;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+
+  if ((Buffer[0] & CurDDRrate) != 0) {
+    NBPtr->PsPtr->RC10OpSpd = Buffer[1];
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR10[OperatingSpeed] = %d for Dct%d\n", Buffer[1], NBPtr->Dct);
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function checks if platform configuration is matched or not.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ *     @return          TRUE : Configuration is matched
+ *     @return          FALSE : Configuration is not matched
+ *
+ */
+BOOLEAN
+STATIC
+MemPCheckTblDrvOverrideConfig (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  UINT8 MaxDimmPerCh;
+  UINT32 CurDDRrate;
+  UINT8 DDR3Voltage;
+  UINT16 RankTypeOfPopulatedDimm;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  // Get platform configuration.
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+  DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage));
+  RankTypeOfPopulatedDimm = MemAGetPsRankType (CurrentChannel);
+
+  if ((MaxDimmPerCh == Buffer[0]) && ((DDR3Voltage & Buffer[1]) != 0) &&
+    ((CurDDRrate & *(UINT32 *)&Buffer[2]) != 0) && ((RankTypeOfPopulatedDimm & *(UINT16 *)&Buffer[6]) != 0)) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function checks if platform configuration is matched or not.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *Buffer  - Pointer to Platform config table
+ *
+ *     @return          TRUE : Configuration is matched
+ *     @return          FALSE : Configuration is not matched
+ *
+ */
+BOOLEAN
+STATIC
+MemPCheckTblDrvOverrideConfigSpeedLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  UINT8 MaxDimmPerCh;
+  UINT8 NumOfSR;
+  UINT8 NumOfDR;
+  UINT8 NumOfQR;
+  UINT8 NumOfLRDimm;
+  UINT8 i;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+  NumOfSR = 0;
+  NumOfDR = 0;
+  NumOfQR = 0;
+  NumOfLRDimm = 0;
+
+  // Get platform configuration.
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) {
+      NumOfSR += 1;
+    } else if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) {
+      NumOfDR += 1;
+    } else if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) {
+      if (i < 2) {
+        NumOfQR += 1;
+      }
+    } else if ((CurrentChannel->LrDimmPresent & (UINT16) (1 << i))) {
+      NumOfLRDimm += 1;
+    }
+  }
+
+  if ((Buffer[0] == MaxDimmPerCh) && (Buffer[1] == CurrentChannel->Dimms)) {
+    if (NBPtr->MCTPtr->Status[SbLrdimms] == TRUE) {
+      if (Buffer[5] == NumOfLRDimm) {
+        return TRUE;
+      }
+    } else {
+      if ((Buffer[2] == NumOfSR) && (Buffer[3] == NumOfDR) && (Buffer[4] == NumOfQR)) {
+        return TRUE;
+      }
+    }
+  }
+
+  return FALSE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c
new file mode 100644
index 0000000000..535b1350f3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c
@@ -0,0 +1,226 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mplribt.c
+ *
+ * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPLRIBT_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
+ *    table and stores extracted value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Succeed in extracting the table value
+ *     @return          FALSE - Fail to extract the table value
+ *
+ */
+BOOLEAN
+MemPGetLRIBT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  UINT8 MaxDimmPerCh;
+  UINT8 NOD;
+  UINT8 TableSize;
+  UINT32 CurDDRrate;
+  UINT8 DDR3Voltage;
+  UINT16 RankTypeOfPopulatedDimm;
+  UINT16 RankTypeInTable;
+  UINT8 PsoMaskLRIBT;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  PSCFG_L_IBT_ENTRY *TblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  if (CurrentChannel->LrDimmPresent == 0) {
+    return TRUE;
+  }
+
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
+  while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) {
+    if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) {
+      LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid;
+      PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType;
+      //
+      // Determine if this is the expected NB Type
+      //
+      if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+        TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr);
+        TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize;
+        break;
+      }
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n");
+    return FALSE;
+  }
+
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+  DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage));
+  RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
+
+  for (i = 0; i < TableSize; i++) {
+    MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
+    if ((TblPtr->DimmPerCh & NOD) != 0) {
+      if ((TblPtr->DDRrate & CurDDRrate) != 0) {
+        if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
+          if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
+            NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8;
+            NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0;
+            NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1;
+            NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2;
+            break;
+          }
+        }
+      }
+    }
+    TblPtr++;
+  }
+  //
+  // If there is no entry, check if overriding value existed. If not, return FALSE
+  //
+  PsoMaskLRIBT = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_LRDIMM_IBT);
+  if ((PsoMaskLRIBT == 0) && (i == TableSize)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n");
+    PutEventLog (AGESA_ERROR, MEM_ERROR_LR_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+      ASSERT (FALSE);
+    }
+    return FALSE;
+  }
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c
new file mode 100644
index 0000000000..0daac6bc57
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c
@@ -0,0 +1,137 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mplrnlr.c
+ *
+ * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPLRNLR_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
+ *    table and stores extracted value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables    - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Succeed in extracting the table value
+ *     @return          FALSE - Fail to extract the table value
+ *
+ */
+BOOLEAN
+MemPGetLRNLR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c
new file mode 100644
index 0000000000..58e0f3865a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c
@@ -0,0 +1,137 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mplrnpr.c
+ *
+ * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPLRNPR_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
+ *    table and stores extracted value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Succeed in extracting the table value
+ *     @return          FALSE - Fail to extract the table value
+ *
+ */
+BOOLEAN
+MemPGetLRNPR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c
new file mode 100644
index 0000000000..d27cf8ff19
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c
@@ -0,0 +1,342 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpmaxfreq.c
+ *
+ * A sub-engine which extracts max. frequency limit value.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct {
+  UINT16 Dimms:4;
+  UINT16 SR:4;
+  UINT16 DR:4;
+  UINT16 QR:4;
+} CDNMaxFreq;
+
+typedef struct {
+  UINT16 Dimms:4;
+  UINT16 LR:12;
+} CDNLMaxFreq;
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemPGetMaxFreqSupported (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts the value of max frequency supported from a input table and
+ *    compares it with DCTPtr->Timings.TargetSpeed
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Succeed in extracting the table value
+ *     @return          FALSE - Fail to extract the table value
+ *
+ */
+BOOLEAN
+MemPGetMaxFreqSupported (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  UINT8 MaxDimmSlotPerCh;
+  UINT8 MaxDimmPerCh;
+  UINT8 NOD;
+  UINT8 TableSize;
+  PSCFG_TYPE Type;
+  UINT16 CDN;
+  UINT16 MaxFreqSupported;
+  UINT16 *SpeedArray;
+  UINT8 DDR3Voltage;
+  UINT8 CurrentVoltage;
+  DIMM_TYPE DimmType;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  BOOLEAN DisDct;
+  UINT8 PsoMaskMaxFreq;
+  UINT16 PsoMaskMaxFreq16;
+  UINT8 NumDimmSlotInTable;
+  UINT16 DimmPopInTable;
+  PSCFG_MAXFREQ_ENTRY *TblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+  PSC_TBL_ENTRY **TblEntryOfMaxFreq;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  DisDct = FALSE;
+  Type = PSCFG_MAXFREQ;
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  NumDimmSlotInTable = 0;
+  DimmPopInTable = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+  SpeedArray = NULL;
+
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                                                       NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+
+  if (CurrentChannel->RegDimmPresent != 0) {
+    DimmType = RDIMM_TYPE;
+  } else if (CurrentChannel->SODimmPresent != 0) {
+    DimmType = SODIMM_TYPE;
+  } else if (CurrentChannel->LrDimmPresent != 0) {
+    DimmType = LRDIMM_TYPE;
+  } else {
+    DimmType = UDIMM_TYPE;
+  }
+
+  // Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration,
+  // DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist
+  if (MaxDimmSlotPerCh != MaxDimmPerCh) {
+    // SODIMM plus soldered-down DRAM
+    DimmType = SODWN_SODIMM_TYPE;
+  } else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
+    // Soldered-down DRAM only
+    DimmType = SODWN_SODIMM_TYPE;
+    MaxDimmSlotPerCh = 0;
+  }
+  NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE;
+
+  TblEntryOfMaxFreq = EntryOfTables->TblEntryOfMaxFreq;
+  IDS_OPTION_HOOK (IDS_GET_STRETCH_FREQUENCY_LIMIT, &TblEntryOfMaxFreq, &NBPtr->MemPtr->StdHeader);
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
+  while (TblEntryOfMaxFreq[i] != NULL) {
+    if (((TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) {
+      if (((TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) {
+        //
+        // Determine if this is the expected NB Type
+        //
+        LogicalCpuid = (TblEntryOfMaxFreq[i])->Header.LogicalCpuid;
+        PackageType = (TblEntryOfMaxFreq[i])->Header.PackageType;
+        if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+          TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((TblEntryOfMaxFreq[i])->TBLPtr);
+          TableSize = (TblEntryOfMaxFreq[i])->TableSize;
+          Type = (TblEntryOfMaxFreq[i])->Header.PSCType;
+          break;
+        }
+      }
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (TblEntryOfMaxFreq[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No MaxFreq table. This channel will be disabled.\n", NBPtr->Dct);
+    return FALSE;
+  }
+
+  MaxFreqSupported = UNSUPPORTED_DDR_FREQUENCY;
+  CDN = 0;
+  DDR3Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage);
+
+  // Construct the condition value
+  ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms;
+  if (Type == PSCFG_MAXFREQ) {
+    for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+      if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) {
+        ((CDNMaxFreq *)&CDN)->SR += 1;
+      }
+      if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) {
+        ((CDNMaxFreq *)&CDN)->DR += 1;
+      }
+      if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) {
+        if (i < 2) {
+          ((CDNMaxFreq *)&CDN)->QR += 1;
+        }
+      }
+    }
+  } else {
+    ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms;
+  }
+
+  for (i = 0; i < TableSize; i++) {
+    NumDimmSlotInTable = TblPtr->MAXFREQ_ENTRY.DimmSlotPerCh;
+    DimmPopInTable = (Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN : ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN;
+    if (((NumDimmSlotInTable & NOD) != 0) && (CDN == DimmPopInTable)) {
+      if (Type == PSCFG_MAXFREQ) {
+        SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed;
+      } else {
+        SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed;
+      }
+      break;
+    }
+    TblPtr++;
+  }
+
+  PsoMaskMaxFreq16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SPEEDLIMIT);
+  if ((PsoMaskMaxFreq16 & INVALID_CONFIG_FLAG) == 0) {
+    PsoMaskMaxFreq = (UINT8) PsoMaskMaxFreq16;
+    if (PsoMaskMaxFreq != 0) {
+      SpeedArray = NBPtr->PsPtr->SpeedLimit;
+    }
+  } else {
+    SpeedArray = NULL;
+  }
+
+  if (SpeedArray != NULL) {
+    if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nCheck speed supported for each VDDIO for Node%d DCT%d: ", NBPtr->Node, NBPtr->Dct);
+      for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
+        if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz ", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), SpeedArray[CurrentVoltage]);
+          if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) {
+            MaxFreqSupported = SpeedArray[CurrentVoltage];
+          } else {
+            MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed;
+          }
+          if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) {
+            NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported;
+          }
+        } else {
+          NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0;
+        }
+      }
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+    }
+    ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL);
+    MaxFreqSupported = SpeedArray[DDR3Voltage];
+  }
+
+  if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) {
+    // No entry in the table for current dimm population is found
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct);
+    DisDct = TRUE;
+  } else if (MaxFreqSupported != 0) {
+    if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) {
+      NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported;
+    }
+  } else if (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED) {
+    // Dimm population is not supported at current voltage
+    // Also if there is no performance optimization, disable the DCT
+    DisDct = TRUE;
+  }
+
+  if (DisDct) {
+    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c
new file mode 100644
index 0000000000..3be1c8a5ef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c
@@ -0,0 +1,222 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpmr0.c
+ *
+ * A sub-engine which extracts MR0[WR] and MR0[CL] value.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPMR0_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemPGetMR0WrCL (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
+ *    value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Succeed in extracting the table value
+ *     @return          FALSE - Fail to extract the table value
+ *
+ */
+BOOLEAN
+MemPGetMR0WrCL (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+
+  UINT8 i;
+  UINT8 j;
+  UINT8 p;
+  UINT32 Value32;
+  UINT8 TableSize;
+  PSCFG_TYPE Type;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  UINT8 PsoMaskMR0;
+  PSCFG_MR0CL_ENTRY *TblPtr;
+  PSC_TBL_ENTRY **ptr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+  TblPtr = NULL;
+  TableSize = 0;
+  PsoMaskMR0 = 0;
+
+  // Extract MR0[WR] value, then MR0[CL] value
+  for (i = 0; i < 2; i++) {
+    if (i == 0) {
+      ptr = EntryOfTables->TblEntryOfMR0WR;
+      Type = PSCFG_MR0WR;
+    } else {
+      ptr = EntryOfTables->TblEntryOfMR0CL;
+      Type = PSCFG_MR0CL;
+    }
+
+    p = 0;
+    // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
+    while (ptr[p] != NULL) {
+      //
+      // Determine if this is the expected NB Type
+      //
+      LogicalCpuid = (ptr[p])->Header.LogicalCpuid;
+      PackageType = (ptr[p])->Header.PackageType;
+      if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+        TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr);
+        TableSize = (ptr[p])->TableSize;
+        break;
+      }
+      p++;
+    }
+
+    // Check whether no table entry is found.
+    if (ptr[p] == NULL) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n");
+      return FALSE;
+    }
+
+    Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl);
+    for (j = 0; j < TableSize; j++, TblPtr++) {
+      if (Value32 == (UINT32) TblPtr->Timing) {
+        if (Type == PSCFG_MR0WR) {
+          NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value;
+          break;
+        } else {
+          NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value;
+          NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1;
+          break;
+        }
+      }
+    }
+
+    //
+    // If there is no entry, check if overriding value existed. If not, return FALSE.
+    //
+    PsoMaskMR0 = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, ((i == 0) ? PSO_TBLDRV_MR0_WR : PSO_TBLDRV_MR0_CL));
+    if ((PsoMaskMR0 == 0) && (j == TableSize)) {
+      IDS_HDT_CONSOLE (MEM_FLOW, (i == 0) ? "\nNo MR0[WR] entries\n" : "\nNo MR0[CL] entries\n");
+      PutEventLog (AGESA_ERROR, MEM_ERROR_MR0_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+      if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+      }
+      return FALSE;
+    }
+  }
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c
new file mode 100644
index 0000000000..3fd474df1a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c
@@ -0,0 +1,243 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpodtpat.c
+ *
+ * A sub-engine which extracts ODT pattern value.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPODTPAT_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemPGetODTPattern (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts ODT Pattern value from a input table and stores extracted
+ *    value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Table values can be extracted per dimm population and ranks type.
+ *     @return          FALSE - Table values cannot be extracted per dimm population and ranks type.
+ *
+ */
+BOOLEAN
+MemPGetODTPattern (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  UINT16 RankTypeInTable;
+  UINT16 RankTypeOfPopulatedDimm;
+  UINT8 MaxDimmPerCh;
+  UINT8 NOD;
+  UINT8 TableSize;
+  DIMM_TYPE DimmType;
+  UINT8 PsoMaskOdtPat;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  PSCFG_3D_ODTPAT_ENTRY *TblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
+
+  if (CurrentChannel->RegDimmPresent != 0) {
+    DimmType = RDIMM_TYPE;
+  } else if (CurrentChannel->SODimmPresent != 0) {
+    DimmType = SODIMM_TYPE;
+  } else if (CurrentChannel->LrDimmPresent != 0) {
+    DimmType = LRDIMM_TYPE;
+  } else {
+    DimmType = UDIMM_TYPE;
+  }
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
+  while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) {
+    if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) {
+      if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) {
+        //
+        // Determine if this is the expected NB Type
+        //
+        LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid;
+        PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType;
+        if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+          TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr);
+          TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize;
+          break;
+        }
+      }
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n");
+    return FALSE;
+  }
+
+  RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
+
+  for (i = 0; i < TableSize; i++) {
+    MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
+    if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
+      CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh;
+      CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow;
+      CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh;
+      CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow;
+
+      //WL ODT
+      if (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn) == 0) {
+        CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F);
+        CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow  >> 16) & 0x0F);
+        CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F);
+        CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F);
+      } else {
+        *(UINT32 *) &(CurrentChannel->PhyWLODT[0]) = CurrentChannel->PhyWODTCSLow & 0xF0F0F0F;
+      }
+
+      break;
+    }
+    TblPtr++;
+  }
+
+  //
+  // If there is no entry, check if overriding value existed. If not, return FALSE
+  //
+  PsoMaskOdtPat = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODTPATTERN);
+  if ((PsoMaskOdtPat == 0) && (i == TableSize)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n");
+    PutEventLog (AGESA_ERROR, MEM_ERROR_ODT_PATTERN_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+      ASSERT (FALSE);
+    }
+    return FALSE;
+  }
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c
new file mode 100644
index 0000000000..9c96dc9499
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c
@@ -0,0 +1,204 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mprc10opspd.c
+ *
+ * A sub-engine which extracts RC10 operating speed value for RDIMM configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPRC10OPSPD_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts RC10 operating speed value from a input table and stores extracted
+ *    value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Succeed in extracting the table value
+ *     @return          FALSE - Fail to extract the table value
+ *
+ */
+BOOLEAN
+MemPGetRC10OpSpd (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  UINT8 TableSize;
+  UINT32 CurDDRrate;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  UINT8 PsoMaskRC10OpSpeed;
+  PSCFG_OPSPD_ENTRY *TblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  if (CurrentChannel->RegDimmPresent == 0) {
+    return TRUE;
+  }
+
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
+  while (EntryOfTables->TblEntryOfRC10OpSpeed[i] != NULL) {
+    LogicalCpuid = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.LogicalCpuid;
+    PackageType = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.PackageType;
+    //
+    // Determine if this is the expected NB Type
+    //
+    if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+      TblPtr = (PSCFG_OPSPD_ENTRY *) ((EntryOfTables->TblEntryOfRC10OpSpeed[i])->TBLPtr);
+      TableSize = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->TableSize;
+      break;
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (EntryOfTables->TblEntryOfRC10OpSpeed[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed table\n");
+    return FALSE;
+  }
+
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+
+  for (i = 0; i < TableSize; i++) {
+    if ((TblPtr->DDRrate & CurDDRrate) != 0) {
+      NBPtr->PsPtr->RC10OpSpd = TblPtr->OPSPD;
+      break;
+    }
+    TblPtr++;
+  }
+
+  //
+  // If there is no entry, check if overriding value existed. If not, return FALSE.
+  //
+  PsoMaskRC10OpSpeed = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_RC10_OPSPEED);
+  if ((PsoMaskRC10OpSpeed == 0) && (i == TableSize)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed entries\n");
+    PutEventLog (AGESA_ERROR, MEM_ERROR_RC10_OP_SPEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+      ASSERT (FALSE);
+    }
+    return FALSE;
+  }
+
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c
new file mode 100644
index 0000000000..800d323c3c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c
@@ -0,0 +1,256 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mprc2ibt.c
+ *
+ * A sub-engine which extracts RC2[IBT] value for RDIMM configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_MEM_PS_MPRC2IBT_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts RC2[IBT] value from a input table and stores extracted
+ *    value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables       Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Table values can be extracted for all present dimms/ranks
+ *     @return          FALSE - Table values cannot be extracted for all present dimms/ranks
+ *
+ */
+BOOLEAN
+MemPGetRC2IBT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  UINT8 MaxDimmPerCh;
+  UINT8 NOD;
+  UINT8 DimmIndex;
+  UINT8 TableSize;
+  UINT32 CurDDRrate;
+  UINT8 DDR3Voltage;
+  UINT16 RankTypeOfPopulatedDimm;
+  UINT16 RankTypeInTable;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  UINT8 TgtDimmType;
+  UINT8 NumOfReg;
+  UINT8 PsoDimmMaskRc2Ibt;
+  UINT8 NoEntryDimmMask;
+  PSCFG_MR2IBT_ENTRY *TblPtr;
+  PSCFG_MR2IBT_ENTRY *OrgTblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  if (CurrentChannel->RegDimmPresent == 0) {
+    return TRUE;
+  }
+
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  NoEntryDimmMask = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
+  while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) {
+    if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) {
+      LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid;
+      PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType;
+      //
+      // Determine if this is the expected NB Type
+      //
+      if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+        TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr);
+        TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize;
+        break;
+      }
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT table\n");
+    return FALSE;
+  }
+
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+  DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage));
+  RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
+
+  OrgTblPtr = TblPtr;
+  for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) {
+    TblPtr = OrgTblPtr;
+    NumOfReg = NBPtr->PsPtr->NumOfReg[DimmIndex];
+    if ((CurrentChannel->ChDimmValid & (UINT8) (1 << DimmIndex)) != 0) {
+      if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) {
+        TgtDimmType = DIMM_QR;
+      } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) {
+        TgtDimmType = DIMM_DR;
+      } else {
+        TgtDimmType = DIMM_SR;
+      }
+
+      for (i = 0; i < TableSize; i++) {
+        MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
+        if ((TblPtr->DimmPerCh & NOD) != 0) {
+          if ((TblPtr->DDRrate & CurDDRrate) != 0) {
+            if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
+              if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
+                if ((TblPtr->Dimm & TgtDimmType) != 0) {
+                  // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM
+                  if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) {
+                    CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2);
+                    CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1);
+                    break;
+                  }
+                }
+              }
+            }
+          }
+        }
+        TblPtr++;
+      }
+
+      if (i == TableSize) {
+        NoEntryDimmMask |= (UINT8) 1 << DimmIndex;
+      }
+    }
+  }
+
+  //
+  // If there are no entries for certain Dimm(s), check if overriding value existed for them. If not, return FALSE.
+  //
+  PsoDimmMaskRc2Ibt = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_RC2_IBT);
+  if (NoEntryDimmMask != 0) {
+    if ((NoEntryDimmMask & PsoDimmMaskRc2Ibt) != NoEntryDimmMask) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT entries\n");
+      PutEventLog (AGESA_ERROR, MEM_ERROR_RC2_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+      if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+      }
+      return FALSE;
+    }
+  }
+
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c
new file mode 100644
index 0000000000..a391997842
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c
@@ -0,0 +1,307 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mprtt.c
+ *
+ * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_MPRTT_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _DONT_CARE 0xFF
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemPGetRttNomWr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
+ *    value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Table values can be extracted for all present dimms/ranks
+ *     @return          FALSE - Table values cannot be extracted for all present dimms/ranks
+ *
+ */
+BOOLEAN
+MemPGetRttNomWr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+  UINT8 i;
+  UINT8 MaxDimmPerCh;
+  UINT8 MaxDimmSlotPerCh;
+  UINT8 NOD;
+  UINT8 TableSize;
+  UINT32 CurDDRrate;
+  UINT8 DDR3Voltage;
+  UINT16 RankTypeOfPopulatedDimm;
+  UINT16 RankTypeInTable;
+  DIMM_TYPE DimmType;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  UINT8 TgtDimmType;
+  UINT8 TgtRank;
+  UINT8 Chipsel;
+  UINT8 PsoCsMaskRtt;
+  UINT16 PsoCsMaskRtt16;
+  UINT8 NoEntryCsMask;
+  PSCFG_RTT_ENTRY *TblPtr;
+  PSCFG_RTT_ENTRY *OrgTblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  PsoCsMaskRtt = 0;
+  NoEntryCsMask = 0;
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                                                       NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+
+  if (CurrentChannel->RegDimmPresent != 0) {
+    DimmType = RDIMM_TYPE;
+  } else if (CurrentChannel->SODimmPresent != 0) {
+    DimmType = SODIMM_TYPE;
+  } else if (CurrentChannel->LrDimmPresent != 0) {
+    DimmType = LRDIMM_TYPE;
+  } else {
+    DimmType = UDIMM_TYPE;
+  }
+
+  // Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration,
+  // DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist
+  if (MaxDimmSlotPerCh != MaxDimmPerCh) {
+    // SODIMM plus soldered-down DRAM
+    DimmType = SODWN_SODIMM_TYPE;
+  } else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
+    // Soldered-down DRAM only
+    DimmType = SODWN_SODIMM_TYPE;
+    MaxDimmSlotPerCh = 0;
+  }
+  NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE;
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
+  while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) {
+    if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) {
+      if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) {
+        //
+        // Determine if this is the expected NB Type
+        //
+        LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid;
+        PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType;
+        if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+          TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr);
+          TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize;
+          break;
+        }
+      }
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RTT table\n");
+    return FALSE;
+  }
+
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+  DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage));
+  RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
+
+  OrgTblPtr = TblPtr;
+  for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) {
+    TblPtr = OrgTblPtr;
+    if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) (1 << Chipsel)) != 0) {
+      if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) {
+        TgtDimmType = DIMM_QR;
+        TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1));
+      } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) {
+        TgtDimmType = DIMM_DR;
+        TgtRank = (UINT8) 1 << (Chipsel & 1);
+      } else {
+        TgtDimmType = DIMM_SR;
+        TgtRank = (UINT8) 1 << (Chipsel & 1);
+      }
+
+      if (DimmType == LRDIMM_TYPE) {
+        TgtDimmType = _DONT_CARE;
+        TgtRank = _DONT_CARE;
+      }
+
+      for (i = 0; i < TableSize; i++) {
+        MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
+        if ((TblPtr->DimmPerCh & NOD) != 0) {
+          if ((TblPtr->DDRrate & CurDDRrate) != 0) {
+            if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
+              if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
+                if (((TblPtr->Dimm & TgtDimmType) != 0) || (TgtDimmType == _DONT_CARE)) {
+                  if (((TblPtr->Rank & TgtRank) != 0) || (TgtRank == _DONT_CARE)) {
+                    NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom;
+                    NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr;
+                    break;
+                  }
+                }
+              }
+            }
+          }
+        }
+        TblPtr++;
+      }
+      // Record which Cs(s) have no entries. Later on, we will check if there are overriding values for them.
+      if ((i == TableSize) && (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED)) {
+        NoEntryCsMask |= (UINT8) 1 << Chipsel;
+      }
+    }
+  }
+
+  PsoCsMaskRtt16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODT_RTTNOM);
+  PsoCsMaskRtt16 &= MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODT_RTTWR);
+  //
+  // Check to see if invalid entry exist ?
+  //
+  if ((PsoCsMaskRtt16 & INVALID_CONFIG_FLAG) != 0) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nInvalid entry is found\n\n");
+    return FALSE;
+  }
+
+  //
+  // If there are no entries for certain Cs(s), we need to check if overriding values (both RttNom and RttWr) existed for them.
+  // Otherwise, return FALSE.
+  //
+  PsoCsMaskRtt = (UINT8) PsoCsMaskRtt16;
+  if (NoEntryCsMask != 0) {
+    if ((PsoCsMaskRtt & NoEntryCsMask) != NoEntryCsMask) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nNo Rtt entries\n");
+      PutEventLog (AGESA_ERROR, MEM_ERROR_RTT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+      if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+      }
+      return FALSE;
+    }
+  }
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c
new file mode 100644
index 0000000000..5ade0b5933
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c
@@ -0,0 +1,266 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpsao.c
+ *
+ * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_MPSAO_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemPGetSAO (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function which extracts Slow mode, Address timing and Output driver compensation value
+ *    from a input table and store those value to a specific address.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          TRUE - Table values can be extracted per dimm population and ranks type.
+ *     @return          FALSE - Table values cannot be extracted per dimm population and ranks type.
+ *
+ */
+BOOLEAN
+MemPGetSAO (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+
+  UINT8 i;
+  UINT8 MaxDimmPerCh;
+  UINT8 MaxDimmSlotPerCh;
+  UINT8 NOD;
+  UINT8 TableSize;
+  UINT32 CurDDRrate;
+  UINT8 DDR3Voltage;
+  UINT16 RankTypeOfPopulatedDimm;
+  UINT16 RankTypeInTable;
+  UINT8 PsoMaskSAO;
+  DIMM_TYPE DimmType;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  PSCFG_SAO_ENTRY *TblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                                                       NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+
+  if (CurrentChannel->RegDimmPresent != 0) {
+    DimmType = RDIMM_TYPE;
+  } else if (CurrentChannel->SODimmPresent != 0) {
+    DimmType = SODIMM_TYPE;
+  } else if (CurrentChannel->LrDimmPresent != 0) {
+    DimmType = LRDIMM_TYPE;
+  } else {
+    DimmType = UDIMM_TYPE;
+  }
+
+  // Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration,
+  // DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist
+  if (MaxDimmSlotPerCh != MaxDimmPerCh) {
+    // SODIMM plus soldered-down DRAM
+    DimmType = SODWN_SODIMM_TYPE;
+  } else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
+    // Soldered-down DRAM only
+    DimmType = SODWN_SODIMM_TYPE;
+    MaxDimmSlotPerCh = 0;
+  }
+  NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE;
+
+  i = 0;
+  // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
+  while (EntryOfTables->TblEntryOfSAO[i] != NULL) {
+    if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) {
+      if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) {
+        //
+        // Determine if this is the expected NB Type
+        //
+        LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid;
+        PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType;
+        if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+          TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr);
+          TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize;
+          break;
+        }
+      }
+    }
+    i++;
+  }
+
+  // Check whether no table entry is found.
+  if (EntryOfTables->TblEntryOfSAO[i] == NULL) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl  table\n");
+    return FALSE;
+  }
+
+  CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
+  DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage));
+  RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
+
+  for (i = 0; i < TableSize; i++) {
+    MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
+    if ((TblPtr->DimmPerCh & NOD) != 0) {
+      if ((TblPtr->DDRrate & CurDDRrate) != 0) {
+        if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
+          if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
+            CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl;
+            CurrentChannel->DctOdcCtl = TblPtr->ODC;
+            CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE;
+            break;
+          }
+        }
+      }
+    }
+    TblPtr++;
+  }
+
+  //
+  // If there is no entry, check if overriding values (SlowAccMode, AddrTmg and ODCCtrl) existed. If not, show no entry found.
+  //
+  PsoMaskSAO = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SLOWACCMODE);
+  PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODCCTRL);
+  PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ADDRTMG);
+  if ((PsoMaskSAO == 0) && (i == TableSize)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl entries\n");
+  } else {
+    return TRUE;
+  }
+
+  if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) {
+    return TRUE;
+  }
+
+  PutEventLog (AGESA_ERROR, MEM_ERROR_SAO_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+  SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+  if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+    ASSERT (FALSE);
+  }
+  return FALSE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c
new file mode 100644
index 0000000000..2ef3c3ff7f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c
@@ -0,0 +1,243 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mpseeds.c
+ *
+ * A sub-engine extracts WL and HW RxEn seeds from PSCFG tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "ma.h"
+#include "mp.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_MEM_PS_MPSEEDS_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    A sub-function extracts WL and HW RxEn seeds from PSCFG tables
+ *    from a input table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *EntryOfTables     - Pointer to MEM_PSC_TABLE_BLOCK
+ *
+ *     @return          NBPtr->PsPtr->WLSeedVal
+ *     @return          NBPtr->PsPtr->HWRxENSeedVal
+ *
+ */
+BOOLEAN
+MemPGetTrainingSeeds (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  )
+{
+
+  UINT8 i;
+  UINT8 MaxDimmPerCh;
+  UINT8 MaxDimmSlotPerCh;
+  UINT8 NOD;
+  UINT8 TableSize;
+  DIMM_TYPE DimmType;
+  CPU_LOGICAL_ID LogicalCpuid;
+  UINT8 PackageType;
+  UINT8 Seedloop;
+  UINT8 CH;
+  PSC_TBL_ENTRY **TblEntryPtr;
+  PSCFG_SEED_ENTRY *TblPtr;
+  CH_DEF_STRUCT *CurrentChannel;
+
+  CurrentChannel = NBPtr->ChannelPtr;
+  TblEntryPtr = NULL;
+  TblPtr = NULL;
+  TableSize = 0;
+  PackageType = 0;
+  LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
+
+  MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                                                       NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
+  CH = 1 << (CurrentChannel->ChannelID);
+
+  if (CurrentChannel->RegDimmPresent != 0) {
+    DimmType = RDIMM_TYPE;
+  } else if (CurrentChannel->SODimmPresent != 0) {
+    DimmType = SODIMM_TYPE;
+  } else if (CurrentChannel->LrDimmPresent != 0) {
+    DimmType = LRDIMM_TYPE;
+  } else {
+    DimmType = UDIMM_TYPE;
+  }
+
+  // Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration,
+  // DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist
+  if (MaxDimmSlotPerCh != MaxDimmPerCh) {
+    // SODIMM plus soldered-down DRAM
+    DimmType = SODWN_SODIMM_TYPE;
+  } else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
+    // Soldered-down DRAM only
+    DimmType = SODWN_SODIMM_TYPE;
+    MaxDimmSlotPerCh = 0;
+  }
+  NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE;
+
+  // Get seed value of WL, then HW RxEn
+  for (Seedloop = 0; Seedloop < 2; Seedloop++) {
+    TblEntryPtr = (Seedloop == 0) ? EntryOfTables->TblEntryOfWLSeed : EntryOfTables->TblEntryOfHWRxENSeed;
+
+    i = 0;
+    // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
+    while (TblEntryPtr[i] != NULL) {
+      if (((TblEntryPtr[i])->Header.DimmType & DimmType) != 0) {
+        //
+        // Determine if this is the expected NB Type
+        //
+        LogicalCpuid = (TblEntryPtr[i])->Header.LogicalCpuid;
+        PackageType = (TblEntryPtr[i])->Header.PackageType;
+        if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
+          TblPtr = (PSCFG_SEED_ENTRY *) ((TblEntryPtr[i])->TBLPtr);
+          TableSize = (TblEntryPtr[i])->TableSize;
+          break;
+        }
+      }
+      i++;
+    }
+
+    // Check whether no table entry is found.
+    if (TblEntryPtr[i] == NULL) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s training seeds Config table\n", (Seedloop == 0) ? "WL" : "HW RxEn");
+      return FALSE;
+    }
+
+    for (i = 0; i < TableSize; i++) {
+      if ((TblPtr->DimmPerCh & NOD) != 0) {
+        if ((TblPtr->Channel & CH) != 0) {
+          if (Seedloop == 0) {
+            NBPtr->PsPtr->WLSeedVal = (UINT8) TblPtr->SeedVal;
+          } else {
+            NBPtr->PsPtr->HWRxENSeedVal = TblPtr->SeedVal;
+          }
+          break;
+        }
+      }
+      TblPtr++;
+    }
+
+    if (i == TableSize) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s seed entries\n\n", (Seedloop == 0) ? "WL" : "HW RxEn");
+      PutEventLog (AGESA_ERROR, MEM_ERROR_TRAINING_SEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+      if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+      }
+      return FALSE;
+    }
+  }
+
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
new file mode 100644
index 0000000000..eb06c8425c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
@@ -0,0 +1,262 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mt3.c
+ *
+ * Common Technology  functions for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtspd3.h"
+#include "mtot3.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+/* features */
+#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function Constructs the technology block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemConstructTechBlock3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  TECHNOLOGY_TYPE *TechTypePtr;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT8 DimmSlots;
+
+
+  TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0, 0, NULL, NULL);
+  if (TechTypePtr != NULL) {
+    // Ensure the platform override value is valid
+    ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
+    if (*TechTypePtr != DDR3_TECHNOLOGY) {
+      return FALSE;
+    }
+  }
+
+  TechPtr->NBPtr = NBPtr;
+  TechPtr->RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  TechPtr->SendAllMRCmds = MemTSendAllMRCmds3;
+  TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3;
+  TechPtr->SetDramMode = MemTSetDramMode3;
+  TechPtr->DimmPresence = MemTDIMMPresence3;
+  TechPtr->SpdCalcWidth = MemTSPDCalcWidth3;
+  TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3;
+  TechPtr->AutoCycTiming = MemTAutoCycTiming3;
+  TechPtr->SpdSetBanks = MemTSPDSetBanks3;
+  TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
+  TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3;
+  TechPtr->AdjustTwrwr = MemTAdjustTwrwr3;
+  TechPtr->AdjustTwrrd = MemTAdjustTwrrd3;
+  TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3;
+  TechPtr->GetLD = MemTGetLD3;
+  TechPtr->MaxFilterDly = 0;
+
+  //
+  // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
+  // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
+  //
+  //    DIMM Spd Buffer                          Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
+  //    (Number of dimms varies by platform)     (Array size is determined in AGESA.H) Dimm operations loop
+  //                                              on this array only)
+  //    2 DIMMS PER CHANNEL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
+  //                                                         DimmSpdPtr[2]------->NULL
+  //                                                         DimmSpdPtr[3]------->NULL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <---------+----DimmSpdPtr[1]
+  //                                                    |    DimmSpdPtr[2]------->NULL
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //    Socket N  Channel N Dimm 0    QR DIMM <-----+--------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <-----|---+----DimmSpdPtr[1]
+  //                                                +-- | ---DimmSpdPtr[2]
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //    3 DIMMS PER CHANNEL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
+  //                        Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
+  //                                                         DimmSpdPtr[3]------->NULL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <---------+----DimmSpdPtr[1]
+  //                        Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //
+  //    FOR LRDIMMS
+  //
+  //    This code will assign SPD pointers on the basis of Physical ranks, even though
+  //    an LRDIMM may only use one or two logical ranks, that determination will have to
+  //    be made from downstream code.  An LRDIMM with greater than 2 Physical ranks will have
+  //    its DimmSpdPtr[] mapped as if it were a QR in the above diagrams.
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      ChannelPtr->TechType = DDR3_TECHNOLOGY;
+      ChannelPtr->MCTPtr = MCTPtr;
+      ChannelPtr->DCTPtr = DCTPtr;
+
+      DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                         MCTPtr->SocketId,
+                                         NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
+                                        );
+      //
+      // Initialize the SPD pointers for each Dimm
+      //
+      for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
+        ChannelPtr->DimmSpdPtr[i] = NULL;
+      }
+      for (i = 0 ; i < DimmSlots; i++) {
+        ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
+        if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
+          if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
+            if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
+              ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
+            }
+          }
+        }
+      }
+    }
+  }
+  // Initialize Common technology functions
+  MemTCommonTechInit (TechPtr);
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h
new file mode 100644
index 0000000000..9cf712b902
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h
@@ -0,0 +1,161 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mt3.h
+ *
+ * Common Technology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MT3_H_
+#define _MT3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructTechBlock3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+BOOLEAN
+MemTSetDramMode3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDIMMPresence3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDCalcWidth3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDGetTargetSpeed3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTAutoCycTiming3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDSetBanks3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTGetCSIntLvAddr3 (
+  IN       UINT8 BankEnc,
+  OUT      UINT8 *LowBit,
+  OUT      UINT8 *HiBit
+  );
+
+VOID
+MemTSendAllMRCmds3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel
+  );
+
+VOID
+FreqChgCtrlWrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+
+BOOLEAN
+MemTGetDimmSpdBuffer3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 **SpdBuffer,
+  IN       UINT8 Dimm
+  );
+#endif  /* _MT3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
new file mode 100644
index 0000000000..6ecef377f3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -0,0 +1,1474 @@
+/**
+ * @file
+ *
+ * mtlrdimm3.c
+ *
+ * Technology initialization and control workd support for DDR3 LRDIMMS
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtspd3.h"
+#include "mtrci3.h"
+#include "mtsdi3.h"
+#include "mtlrdimm3.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTSendMBCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Fn,
+  IN       UINT8 Rcw,
+  IN       UINT8 Value
+  );
+
+VOID
+STATIC
+MemTSendExtMBCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT16 Addr,
+  IN       UINT16 Data,
+  IN       UINT8 Len
+  );
+
+UINT8
+STATIC
+MemTGetSpecialMBCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Fn,
+  IN       UINT8 Rc
+  );
+
+BOOLEAN
+STATIC
+MemTLrDimmControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+STATIC
+MemTLrDimmFreqChgCtrlWrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+STATIC
+MemTWLPrepareLrdimm3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *Wl
+  );
+
+BOOLEAN
+STATIC
+MemTSendAllMRCmdsLR3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *CsPtr
+  );
+
+VOID
+STATIC
+MemTEMRS1Lr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 PhyRank
+  );
+
+VOID
+STATIC
+MemTEMRS2Lr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel
+  );
+
+
+BOOLEAN
+STATIC
+MemTLrdimmRankMultiplication (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *DimmID
+  );
+
+BOOLEAN
+STATIC
+MemTLrdimmBuf2DramTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+STATIC
+MemTLrdimmSyncTrainedDlys (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+STATIC
+MemTLrdimmPresence (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *DimmID
+  );
+
+UINT32
+STATIC
+MemTLrDimmGetBufferID (
+  IN OUT  MEM_TECH_BLOCK *TechPtr,
+  IN      UINT8 Dimm
+  );
+
+VOID
+STATIC
+MemTLrdimmInitHook (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       LRDIMM_HOOK_ENTRYPOINT Entrypoint,
+  IN       UINT8 Dimm,
+  IN OUT   VOID  *OptParam
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes LRDIMM functions.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemTLrdimmConstructor3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds]      = MemTSendAllMRCmdsLR3;
+  TechPtr->TechnologySpecificHook[LrdimmControlRegInit]     = MemTLrDimmControlRegInit3;
+  TechPtr->TechnologySpecificHook[LrdimmFreqChgCtrlWrd]     = MemTLrDimmFreqChgCtrlWrd3;
+  TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm]  = MemTWLPrepareLrdimm3;
+  TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] = MemTLrdimmRankMultiplication;
+  TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain]      = MemTLrdimmBuf2DramTrain3;
+  TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys]    = MemTLrdimmSyncTrainedDlys;
+  TechPtr->TechnologySpecificHook[LrdimmPresence]           = MemTLrdimmPresence;
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends a Control word command to an LRDIMM Memory Buffer
+ *
+ *     @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     Fn       - control word function
+ *     @param[in]     Rcw      - control word number
+ *     @param[in]     Value    - value to send
+ *
+ */
+
+VOID
+STATIC
+MemTSendMBCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Fn,
+  IN       UINT8 Rcw,
+  IN       UINT8 Value
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  ASSERT (Rcw != RCW_FN_SELECT);  // RC7 can only be used for function select
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF%dRC%d = %x\n", Fn, Rcw, Value);
+  //
+  // Select the MB Function by sending the Fn number
+  //  to the Function Select Control Word
+  //
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, Fn);
+  //
+  // Send the value to the control word
+  //
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, Rcw, Value);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends a an Extended Control word command to an LRDIMM Memory Buffer
+ *
+ *     @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     Addr     - Extended Control Word Address
+ *                                 Addr[15:12] Extended Control Workd Function Select
+ *                                 Addr[11:0] Extended Control Word CSR Address
+ *     @param[in]     Data     - value to send
+ *     @param[in]     Len      - Length of data.  1 or 2 bytes
+ *
+ */
+
+VOID
+STATIC
+MemTSendExtMBCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT16 Addr,
+  IN       UINT16 Data,
+  IN       UINT8 Len
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  ASSERT ((Len == 1) || (Len == 2));
+  if (Len == 2 ) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtRC_x%04x = %04x\n", Addr, Data);
+  } else {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtRC_x%04x = %02x\n", Addr, (UINT8) (Data & 0xFF) );
+  }
+  //
+  // Select the MB Function by sending the Fn number
+  //  to the Function Select Control Word
+  //
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, 13);
+  //
+  // Send address via control words
+  //
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, 9, (UINT8) (Addr >> 12));
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, 10, (UINT8) (Addr & 0xF));
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, 11, (UINT8) ((Addr >> 4) & 0x0F));
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, 12, (UINT8) ((Addr >> 8) & 0x0F));
+  //
+  // Send the Lower Byte of Data
+  //
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, 14, (UINT8) (Data & 0xF));
+  MemUWait10ns (800, NBPtr->MemPtr);
+  MemTSendCtlWord3 (TechPtr, 15, (UINT8) ((Data >> 4) & 0x0F));
+  //
+  // Send the Upper Byte of Data
+  //
+  if (Len == 2) {
+    MemUWait10ns (800, NBPtr->MemPtr);
+    MemTSendCtlWord3 (TechPtr, 10, (UINT8) ((Addr & 0xF) + 1));
+    MemUWait10ns (800, NBPtr->MemPtr);
+    MemTSendCtlWord3 (TechPtr, 14, (UINT8) ((Data >> 8) & 0xF));
+    MemUWait10ns (800, NBPtr->MemPtr);
+    MemTSendCtlWord3 (TechPtr, 15, (UINT8) ((Data >> 12) & 0xF));
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets the value of special RCW
+ *
+ *     @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     Dimm     - Physical LR DIMM number
+ *     @param[in]     Fn       - control word function
+ *     @param[in]     Rc       - control word number
+ *
+ *     @return      Special RCW value
+ *
+ */
+
+UINT8
+STATIC
+MemTGetSpecialMBCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Fn,
+  IN       UINT8 Rc
+  )
+{
+  CONST UINT8   F0RC13PhyRankTab[] = {3, 2, 0, 1, 0};
+  UINT8         PhyRanks;
+  UINT8         LogRanks;
+  UINT8         DramCap;
+  UINT8         Value8;
+  UINT8         *SpdBufferPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+
+  Value8 = 0;
+  switch (Fn) {
+  case 0:
+    switch (Rc) {
+    case 8:
+      // F0RC8
+      Value8 = NBPtr->PsPtr->F0RC8;
+      break;
+    case 10:
+      // F0RC10
+      // 2:0 OperatingSpeed: operating speed. BIOS: Table 88.
+      if (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) {
+        Value8 = 0;
+      } else {
+        Value8 = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) - 3;
+      }
+      break;
+    case 11:
+      // F0RC11
+      // 3:2 ParityCalculation: partiy calculation. BIOS: Table.
+      // 1:0 OperatingVoltage: operating voltage. BIOS: IF(VDDIO == 1.5) THEN 00b ELSEIF (VDDIO ==
+      //     1.35) THEN 01b ELSE 10b ENDIF.
+      DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF;
+      if (NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] > 16) {
+        Value8 = 8;
+      } else {
+        Value8 = 4;
+      }
+      Value8 |= CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage);
+      break;
+    case 13:
+      // F0RC13
+      // 3:2 NumLogicalRanks: partiy calculation. BIOS: Table 90.
+      // 1:0 NumPhysicalRanks: operating voltage. BIOS: Table 89.
+      LogRanks = NBPtr->ChannelPtr->LrDimmLogicalRanks[Dimm] >> 1;
+      PhyRanks = F0RC13PhyRankTab[(SpdBufferPtr[SPD_RANKS] >> 3) & 7];
+      Value8 = (LogRanks << 2) | PhyRanks;
+      break;
+    case 14:
+      // F0RC14
+      // 3 DramBusWidth: DRAM bus width. BIOS: IF (DeviceWidth==0) THEN 0 ELSE 1 ENDIF.
+      // 2 MRSCommandControl: MRS command control. BIOS: IF (F0RC15[RankMultiplicationControl]
+      //   > 0) THEN 1 ELSE 0 ENDIF.
+      // 1 RefreshPrechargeCommandControl: refresh and precharge command control. BIOS: IF
+      //   (F0RC15[RankMultiplicationControl] > 0) THEN D18F2xA8_dct[1:0][LrDimmEnhRefEn] ELSE 0 ENDIF.
+      // 0 AddressMirror: address mirror. BIOS: RankMap. See D18F2x[5C:40]_dct[1:0][OnDimmMirror].
+      if ((SpdBufferPtr[SPD_DEV_WIDTH] & 7) != 0) {
+        Value8 |= 8;
+      }
+      if (NBPtr->ChannelPtr->LrDimmRankMult[Dimm] > 1) {
+        Value8 |= 4;
+        if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 1) {
+          Value8 |= 2;
+        }
+      }
+      if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
+        Value8 |= 1;
+      }
+      break;
+    case 15:
+      // F0RC15
+      // 3:0 RankMultiplicationControl: rank multiplication control. BIOS: Table 91.
+      DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF;
+      ASSERT ((DramCap >= 2) && (DramCap <= 4));            // BKDG only lists 1Gb, 2Gb, and 4Gb
+      switch (NBPtr->ChannelPtr->LrDimmRankMult[Dimm]) {
+      case 1:
+        Value8 = 0;
+        break;
+      case 2:
+        Value8 = DramCap - 1;
+        break;
+      case 4:
+        Value8 = DramCap + 3;
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+    break;
+  case 1:
+    switch (Rc) {
+    case 0:
+      // F1RC0
+      Value8 = NBPtr->PsPtr->F1RC0;
+      Value8 |= (UINT8) NBPtr->GetBitField (NBPtr, BFCSTimingMux67) << 3;
+      break;
+    case 1:
+      // F1RC1
+      Value8 = NBPtr->PsPtr->F1RC1;
+      break;
+    case 2:
+      // F1RC2
+      Value8 = NBPtr->PsPtr->F1RC2;
+      break;
+    case 9:
+      // F1RC9
+      if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 0) {
+        Value8 = 1;
+      }
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+    break;
+  case 3:
+    switch (Rc) {
+    case 0:
+      // F3RC0
+      // 3   TDQSControl: TDQS control. BIOS: 0.
+      // 2:0 RttNom: RttNom. BIOS: Table 57, Table 60
+      Value8 = NBPtr->PsPtr->RttNom[Dimm << 1];
+      break;
+    case 1:
+      // F3RC1
+      // 3   Vref: Vref. BIOS: 0.
+      // 2:0 RttWr: RttWr. BIOS: Table 57, Table 60.
+      Value8 = NBPtr->PsPtr->RttWr[Dimm << 1];
+      break;
+    case 6:
+      // F3RC6
+      // IF (D18F2x90_dct[1:0][X4Dimm] == 0) THEN 1 ELSE 0
+      if (NBPtr->GetBitField (NBPtr, BFX4Dimm) == 0) {
+        Value8 = 8;
+      }
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+
+  return Value8;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends LRDIMM Control Words to all LRDIMMS
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+STATIC
+MemTLrDimmControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  CONST UINT8 RCWInitTable[] = {
+    //  RCW,  Mask, SPD
+    F0, RC0,  0x00, SPD_NONE,
+    F0, RC1,  0x00, SPD_NONE,
+    F0, RC2,  0x03, SPD_67,
+    F0, RC10, 0x00, SPECIAL_CASE,
+    F0, RC11, 0x00, SPECIAL_CASE,
+
+    F1, RC8,  0x0F, SPD_69,
+    F1, RC11, 0xF0, SPD_69,
+    F1, RC12, 0x0F, SPD_70,
+    F1, RC13, 0xF0, SPD_70,
+    F1, RC14, 0x0F, SPD_71,
+    F1, RC15, 0xF0, SPD_71,
+
+    WAIT_6US, 0, 0, 0,
+
+    F0, RC3,  0xF0, SPD_67,
+    F0, RC4,  0x0F, SPD_68,
+    F0, RC5,  0xF0, SPD_68,
+
+    F0, RC6,  0x00, SPD_NONE,
+    F0, RC8,  0x00, SPECIAL_CASE,
+    F0, RC9,  0x0C, SPD_NONE,
+    F0, RC13, 0x00, SPECIAL_CASE,
+    F0, RC14, 0x00, SPECIAL_CASE,
+    F0, RC15, 0x00, SPECIAL_CASE,
+
+    F1, RC0,  0x00, SPECIAL_CASE,
+    F1, RC1,  0x00, SPECIAL_CASE,
+    F1, RC2,  0x00, SPECIAL_CASE,
+    F1, RC3,  0x00, SPD_NONE,
+    F1, RC9,  0x00, SPECIAL_CASE,
+    F1, RC10, 0x00, SPD_NONE,
+
+    F2, RC0,  0x00, SPD_NONE,
+    F2, RC1,  0x00, SPD_NONE,
+    F2, RC2,  0x0F, SPD_NONE,
+    F2, RC3,  0x00, SPD_NONE,
+
+    F3, RC0,  0x00, SPECIAL_CASE,
+    F3, RC1,  0x00, SPECIAL_CASE,
+    F3, RC2,  0x01, SPD_NONE,
+    F3, RC6,  0x00, SPECIAL_CASE
+    //
+    // F3 RC[8,9] are programmed in MDQ RC loop
+    //
+    // F[10:3] RC[11,10] are programmed in QxODT RC loop
+    //
+    // F[15,14] RC[15:0] are programmed in personality RC loop
+  };
+
+  UINT8           Dimm;
+  UINT16          i;
+  UINT16          DimmMask;
+  UINT8           Fn;
+  UINT8           Rc;
+  UINT8           Mask;
+  UINT8           Spd;
+  UINT8           *SpdBufferPtr;
+  UINT8           FreqDiffOffset;
+  UINT8           Value8;
+  UINT32           Temp32;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK    *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+      DimmMask = (UINT16)1 << Dimm;
+      if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) {
+        //
+        // Select the Target Chipselects
+        //
+        NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1));
+        NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1));
+
+        MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSending LRDIMM Control Words: Dimm %02x\n", Dimm);
+
+        for (i = 0; i < sizeof (RCWInitTable) ; i += 4) {
+          Fn   = RCWInitTable[i];
+          Rc   = RCWInitTable[i + 1];
+          Mask = RCWInitTable[i + 2];
+          Spd  = RCWInitTable[i + 3];
+
+          if (Fn == WAIT_6US) {
+            MemUWait10ns (600, MemPtr);   // wait 6us for TSTAB
+          } else {
+            if (Spd == SPD_NONE) {
+              Value8 = Mask;
+            } else if (Spd == SPECIAL_CASE) {
+              Value8 = MemTGetSpecialMBCtlWord3 (TechPtr, Dimm, Fn, Rc);
+            } else {
+              Value8 = (Mask > 0x0F) ? ((SpdBufferPtr[Spd] & Mask) >> 4) : (SpdBufferPtr[Spd] & Mask);
+            }
+            MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8);
+          }
+        }
+
+        FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2));
+        //
+        // Send RCW to program MDQ termination and drive strength
+        //
+        for (Rc = 8; Rc <= 9; Rc++) {
+          Value8 = SpdBufferPtr[SPD_MDQ_800_1066 + FreqDiffOffset];
+          Value8 = (Rc == 9) ? (Value8 >> 4) : Value8;
+          MemTSendMBCtlWord3 (TechPtr, 3, Rc, Value8 & 0x07);
+        }
+        //
+        // Send RCW to program QxODT
+        //
+        for (Fn = 3; Fn <= 10; Fn ++) {
+          for (Rc = 10; Rc <= 11; Rc++) {
+            Value8 = SpdBufferPtr[SPD_QXODT_800_1066 + FreqDiffOffset + ((Fn - 3) >> 1)];
+            Value8 = (Rc == 11) ? (Value8 >> 4) : (Value8 & 0x0F);
+            Value8 = ((Fn & 1) == 0) ? (Value8 >> 2) : (Value8 & 0x03);
+            MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8);
+          }
+        }
+
+        MemTLrdimmInitHook (TechPtr, AFTER_TSTAB, Dimm, 0);
+        //
+        // Send Personality bytes from SPD
+        //
+        for (i = 0; i < 15; i ++) {
+          Value8 = SpdBufferPtr[SPD_PERSONALITY_BYTE + i];
+          Fn = (UINT8) (14 + (i >> 3));
+          Rc = (UINT8) ((i << 1) & 0x0F);
+          if ( i == 0) {
+            Value8 |= 0x01;
+          } else if ( i > 10) {
+            Rc += 2;
+          }
+          MemTSendMBCtlWord3 (TechPtr, Fn, Rc, (Value8 & 0x0F));
+          if (i == 3) {
+            Fn++;
+          } else {
+            Rc++;
+          }
+          MemTSendMBCtlWord3 (TechPtr, Fn, Rc, (Value8 >> 4));
+        }
+        //
+        // Send Extended Control Words to Buffer
+        //
+        // ExtRC_xAC
+        //
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00AC, 0, 1);
+        //
+        // ExtRC_xB8-BF
+        //
+        Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset];
+        for (i = 0x00B8; i < 0x00C0; i++) {
+          MemTSendExtMBCtlWord3 (TechPtr, i, Value8, 1);
+          if (i == 0xB9) {
+            //
+            // Phys ranks > 1, Rtt_nom = 0
+            //
+            Value8 &= 0xE3;
+          }
+        }
+        // ExtRC_xC8
+        Value8 = (UINT8) (NBPtr->MemNGetMR0CL (NBPtr) & 0x000000FF);
+        Value8 = ((Value8 & 0xE0) | ((Value8 & 0x04) << 1));
+        Value8 |= 1 << 2; // RBT
+        Value8 |= NBPtr->GetBitField (NBPtr, BFBurstCtrl); // BL
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00C8 , Value8, 1);
+        // ExtRC_xC9
+        // PPD
+        Value8 = (UINT8) (NBPtr->GetBitField (NBPtr, BFPchgPDModeSel) & 0x000000FF);
+        NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Value8);
+        IDS_OPTION_HOOK (IDS_MEM_MR0, &Value8, &TechPtr->NBPtr->MemPtr->StdHeader);
+        Value8 <<= 4;
+        // WR
+        Temp32 = NBPtr->MemNGetMR0WR (NBPtr);
+        Value8 |= (UINT8) ((Temp32 >> 8) & 0x000000FF);
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00C9 , Value8, 1);
+        // ExtRC_xCA
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00CA , 0, 1);
+        // ExtRC_xCB
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00CB , 0, 1);
+        // ExtRC_xCC
+        // CWL
+        Value8 = (UINT8) (NBPtr->MemNGetMR2CWL (NBPtr) & 0x000000FF);
+        // SRT|ASR
+        Value8 |= 0x40;
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00CC , Value8, 1);
+        // ExtRC_xCD
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00CD , 0, 1);
+        // ExtRC_xCE
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00CE , 0, 1);
+        // ExtRC_xCF
+        MemTSendExtMBCtlWord3 (TechPtr, 0x00CF , 0, 1);
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends LRDIMM Control Words to all LRDIMMS
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    FALSE  - The current channel does not have LRDIMM populated
+ *                TRUE   - The current channel has LRDIMM populated
+ */
+BOOLEAN
+STATIC
+MemTLrDimmFreqChgCtrlWrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 Dct;
+  MEM_NB_BLOCK    *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        MemTLrDimmControlRegInit3 (TechPtr, NULL);
+      }
+    }
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function prepares LRDIMMs for WL training.
+ *
+ *     @param[in,out]  *TechPtr     - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]  *Wl - Indicates if WL mode should be enabled
+ *
+ *     @return    TRUE - LRDIMMs present
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemTWLPrepareLrdimm3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *Wl
+  )
+{
+  UINT8 Dimm;
+  UINT8 Value8;
+  UINT16 MrsAddress;
+  MEM_NB_BLOCK  *NBPtr;
+  NBPtr = TechPtr->NBPtr;
+  MrsAddress = 0;
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+      if (*(BOOLEAN *) Wl == TRUE) {
+        // Program WrLvOdt
+        NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[Dimm]);
+      }
+      if ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0) {
+        if (Dimm == TechPtr->TargetDIMM) {
+          if (*(BOOLEAN *) Wl == TRUE) {
+            //
+            // Select the Target Chipselects
+            //
+            NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1));
+            NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1));
+            // Program F0RC12 to 1h
+            MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x01);
+            if (NBPtr->ChannelPtr->Dimms >= 2) {
+              // For two or more LRDIMMs per channel program the buffer RttNom to the
+              // corresponding specifed RttWr termination
+              Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, Dimm << 2);
+            } else {
+              // Program RttNom as normal
+              Value8 = NBPtr->MemNGetDramTerm (NBPtr, Dimm << 2);
+            }
+            if ((Value8 & ((UINT8) 1 << 2)) != 0) {
+              MrsAddress |= ((UINT16) 1 << 9);
+            }
+            if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+              MrsAddress |= ((UINT16) 1 << 6);
+            }
+            if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+              MrsAddress |= ((UINT16) 1 << 2);
+            }
+            NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+          } else {
+            // Program F0RC12 to 0h
+            MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x00);
+          }
+        }
+      }
+    }
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This send all MR commands to all physical ranks of an LRDIMM
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       *CsPtr     - Target Chip Select
+ *
+ *     @return    FALSE  - The current channel does not have LRDIMM populated
+ *                TRUE   - The current channel has LRDIMM populated
+ */
+BOOLEAN
+STATIC
+MemTSendAllMRCmdsLR3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *CsPtr
+  )
+{
+  UINT8        *SpdBufferPtr;
+  UINT8         Rank;
+  UINT8         PhyRank;
+  UINT8         ChipSel;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChipSel = *((UINT8 *) CsPtr);
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    //
+    //   For LRDIMMs, MR0, MR2, and MR3 can be broadcast to any physicall ranks behind
+    // each logical rank(CS) by setting MRSAddress[13]. MR1[Rtt_Nom] needs to be programmed
+    // differently per physical rank, so it must target a physical rank using MrsAddress[17:14].
+    // The actual bits used to index the physical rank are determined by the DRAM Capacity.
+    //
+    //   This function will be called once for each CS where CSPresent is set, so each time
+    // it only needs to handle the Physical ranks behind each CS.  If a Dimm is not using some
+    // CS due to Rank Mux, those CSPresent bits will have been already cleared.
+    //
+
+    //
+    // Select target chip select
+    //
+    NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+    //
+    // 13.Send EMRS(2)
+    //
+    MemTEMRS2Lr3 (TechPtr, ChipSel);
+    NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1);    // Set Address bit 13 to broadcast
+    NBPtr->SendMrsCmd (NBPtr);
+    //
+    // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
+    //
+    MemTEMRS33 (TechPtr);
+    NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1);    // Set Address bit 13 to broadcast
+    NBPtr->SendMrsCmd (NBPtr);
+    //
+    // 15.Send EMRS(1). Send to each physical rank.
+    //
+    MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1);
+    //
+    // Determine first physical rank relative to the LRDIMM for this CS
+    //
+    PhyRank = ((((ChipSel & NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1]) >> 1) & 2) | (ChipSel & 1));
+    for (Rank = 0; Rank < NBPtr->ChannelPtr->LrDimmRankMult[ChipSel >> 1]; Rank++) {
+      MemTEMRS1Lr3 (TechPtr, ChipSel, PhyRank);
+      //
+      // Set Address bit 14, 15, 16, or 17 to select physical rank, relative to the CS, according to the device size
+      //
+      NBPtr->SetBitField (NBPtr, BFMrsAddressHi, Rank << ((SpdBufferPtr[SPD_DENSITY] & 0xF) - 1 ) );
+      NBPtr->SendMrsCmd (NBPtr);
+      //
+      // Index to the next physical rank
+      //
+      PhyRank = PhyRank + NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1];
+    }
+    //
+    // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
+    //
+    MemTMRS3 (TechPtr);
+    NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1);    // Set Address bit 13 to broadcast
+    NBPtr->SendMrsCmd (NBPtr);
+    //
+    // If LRDIMM, return TRUE to skip sending regular MR commands.
+    //
+    return TRUE;
+  }
+  //
+  // If not LRDIMM, send regular MR commands.
+  //
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS1 value for an LRDIMM
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]        ChipSel   - Chip select number
+ *     @param[in]        PhyRank   - Physical rank number
+ */
+
+VOID
+STATIC
+MemTEMRS1Lr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 PhyRank
+  )
+{
+  UINT16       MrsAddress;
+  UINT8        Value8;
+  UINT8        *SpdBufferPtr;
+  UINT8        FreqDiffOffset;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1);
+  FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2));
+
+  // BA2=0,BA1=0,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
+
+  MrsAddress = 0;
+
+  // program MrsAddress[5,1]=output driver impedance control (DIC): 01b
+  MrsAddress |= ((UINT16) 1 << 1);
+
+  // program MrsAddress[5,1]=output driver impedance control (DIC):
+  // DIC is read from SPD byte 77, 83, or 89 depending on DDR speed
+  Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] & 3;
+  if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 5);
+  }
+  if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 1);
+  }
+
+  // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
+  // RttNom is read from SPD byte 77, 83, or 89 depending on DDR speed
+  if (PhyRank <= 1) {
+    Value8 = (SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 2) & 7;
+    if ((Value8 & ((UINT8) 1 << 2)) != 0) {
+      MrsAddress |= ((UINT16) 1 << 9);
+    }
+    if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+      MrsAddress |= ((UINT16) 1 << 6);
+    }
+    if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+      MrsAddress |= ((UINT16) 1 << 2);
+    }
+  }
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS2 value for an LRDIMM
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]        ChipSel   - Chip select number
+ */
+
+VOID
+STATIC
+MemTEMRS2Lr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  UINT8        RttWr;
+  UINT8        *SpdBufferPtr;
+  UINT8        FreqDiffOffset;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // Save default RttWr
+  RttWr = NBPtr->PsPtr->RttWr[ChipSel];
+
+  // Override RttWr with the value read from SPD byte 77, 83, or 89 depending on DDR speed
+  MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1);
+  FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2));
+  NBPtr->PsPtr->RttWr[ChipSel] = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 6;
+
+  // Call EMRS2 calculation
+  MemTEMRS23 (TechPtr);
+
+  // Restore RttWr
+  NBPtr->PsPtr->RttWr[ChipSel] = RttWr;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function to determine the Rank Multiplication to use for an LRDIMM
+ *
+ *     @param[in,out]  *TechPtr     - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]  *DimmID      - Dimm ID
+ *
+ *     @return    TRUE - LRDIMM Support is installed and LRDIMMs are present
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemTLrdimmRankMultiplication (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *DimmID
+  )
+{
+  BOOLEAN RetVal;
+  UINT8 *SpdBufferPtr;
+  UINT8 Dimm;
+  UINT8 NumDimmslots;
+  UINT8 DramCapacity;
+  UINT8 Ranks;
+  UINT8 Rows;
+  UINT8 RankMult;
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (TechPtr != NULL);
+  ASSERT (DimmID != NULL);
+
+  Dimm = *(UINT8*)DimmID;
+  ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL);
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+  RetVal = FALSE;
+  RankMult = 0;
+
+  if (!MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm)) {
+    ASSERT (FALSE);
+  }
+
+  NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                        NBPtr->MCTPtr->SocketId,
+                                        ChannelPtr->ChannelID);
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    RetVal = TRUE;
+    //
+    // Determine LRDIMM Rank Multiplication
+    //
+    Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
+    if (Ranks == 5) {
+      Ranks = 8;
+    }
+    DramCapacity = (SpdBufferPtr[SPD_DENSITY] & 0x0F);
+    Rows = 12 + ((SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7);
+
+    if (Ranks < 4) {
+      RankMult = 1;
+    } else if (Ranks == 4) {
+      RankMult = (NumDimmslots < 3) ? 1 : 2;
+    } else if (Ranks == 8) {
+      RankMult = ((NumDimmslots < 3) && (DramCapacity < 4)) ? 2 : 4;
+    }
+    //
+    // Save Rank Information
+    //
+    ChannelPtr->LrDimmRankMult[Dimm] = RankMult;
+    ChannelPtr->LrDimmLogicalRanks[Dimm] = Ranks / RankMult;
+    NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = Rows + (RankMult >> 1);
+    //
+    // Program RankDef
+    //
+    NBPtr->SetBitField (NBPtr, BFRankDef0 + Dimm, (RankMult == 4) ? 3 : RankMult);
+    //
+    // If LrdimmRowAddressBits > 16, then we must be using some CS signals for rank
+    //   multiplication.  If this is the case, then we want to clear the CSPresent bits
+    //   that correspond to those  chipselects.
+    //   If there are 3 DIMMs per channel, then it will always be CS67, if there are
+    //   2DPCH, then DIMM0 will use CS45, and DIMM1 will use CS67.
+    //
+    if ((ChannelPtr->LrDimmLogicalRanks[Dimm] < 4) && (Dimm >= NumDimmslots)) {
+      NBPtr->DCTPtr->Timings.CsPresent &= ~(0x3 << (Dimm << 1));
+      ChannelPtr->LrDimmRankMult[Dimm] = 0;
+      ChannelPtr->LrDimmLogicalRanks[Dimm] = 0;
+      NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = 0;
+    } else {
+      IDS_HDT_CONSOLE_DEBUG_CODE (
+        if (Dimm < NumDimmslots) {
+          IDS_HDT_CONSOLE (MEM_FLOW,"\tDimm %d: Log. Ranks:%d   Phys. Ranks:%d   RowAddrBits:%d   RankMult:%d\n",
+            Dimm,
+            ChannelPtr->LrDimmLogicalRanks[Dimm],
+            ChannelPtr->LrdimmPhysicalRanks[Dimm],
+            NBPtr->PsPtr->LrdimmRowAddrBits[Dimm],
+            RankMult
+            );
+        }
+      );
+    }
+  }
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------
+ *
+ *   This function performs buffer to DRAM training for LRDIMMs
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+STATIC
+MemTLrdimmBuf2DramTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK    *NBPtr;
+  UINT8  Dct;
+  UINT8  Dimm;
+  UINT8  ChipSel;
+  UINT16 DimmMask;
+  UINT8  i;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nStart Buffer to DRAM training\n");
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      //
+      // ODM needs to be set after Dram Init
+      //
+      if (NBPtr->StartupSpeed == NBPtr->DCTPtr->Timings.Speed) {
+        for (ChipSel = 1; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+          if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+            if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
+              NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel, ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel)) | ((UINT32)1 << BFOnDimmMirror )));
+            }
+          }
+        }
+      }
+      //
+      // Buffer to DRAM training
+      //
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        DimmMask = (UINT16)1 << Dimm;
+        if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) {
+          IDS_HDT_CONSOLE (MEM_STATUS, "\t\nDimm %d\n", Dimm);
+          //
+          // Select the Target Chipselects
+          //
+          NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1));
+          NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1));
+
+          NBPtr->SetBitField (NBPtr, BFLrDimmErrOutMonEn, 1);
+          MemTSendMBCtlWord3 (TechPtr, F2, RC3, 8);
+          // Send F0RC12 with data = 0010b.
+          MemTSendMBCtlWord3 (TechPtr, F0, RC12, 2);
+          //
+          // Wait until D18F2xA0_dct[1:0][RcvParErr]=0 or tCAL * the number of physical ranks expires.
+          //
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWaiting %d ms...\n", 10 * NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm]);
+          for (i = 0; i < (NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm] * 10); i++) {
+            MemUWait10ns (1000000, MemPtr);
+            //
+            // @todo: Provide option for polling RcvParErr to optimize DRAM bus timing.
+            //
+          }
+          IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tRcvParErr = %02x\n", NBPtr->GetBitField (NBPtr, BFRcvParErr));
+          NBPtr->SetBitField (NBPtr, BFLrDimmErrOutMonEn, 0);
+          MemTSendMBCtlWord3 (TechPtr, F2, RC3, 0);
+          // Configure for normal operation: Send F0RC12 with data = 0000b.
+          MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0);
+        }
+      }
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd Buffer to DRAM training\n");
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function copies trained delays of the first rank of a QR LRDIMM to the third rank
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+STATIC
+MemTLrdimmSyncTrainedDlys (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 i;
+  UINT8 Dimm;
+  UINT8 Dct;
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT16 WrDqsDly;
+  UINT16 RcvEnDly;
+  UINT16 RdDqsDly;
+  UINT16 WrDatDly;
+  UINT8  RdDqs2dDly;
+  NBPtr = TechPtr->NBPtr;
+
+  if (NBPtr->MCTPtr->Status[SbLrdimms]) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tSync LRDIMM Delays to remaining ranks.\n");
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      ChannelPtr = NBPtr->ChannelPtr;
+      for (Dimm = 0; Dimm < 2; Dimm++) {
+        if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) {
+          // If logical QR LRDIMM, copy trained delays from first rank to third rank
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDimm %d -> Dimm %d\n",Dimm, Dimm + 2);
+          for (i = 0; i < TechPtr->DlyTableWidth (); i++) {
+            WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + i];
+            NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), WrDqsDly);
+            ChannelPtr->WrDqsDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = (UINT8)WrDqsDly;
+
+            RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i];
+            NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm + 2, i), RcvEnDly);
+            ChannelPtr->RcvEnDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = RcvEnDly;
+
+            RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + i];
+            NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), RdDqsDly);
+            ChannelPtr->RdDqsDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = (UINT8)RdDqsDly;
+
+            WrDatDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + i];
+            NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm + 2, i), WrDatDly);
+            ChannelPtr->WrDatDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = (UINT8)WrDatDly;
+          }
+          if ((ChannelPtr->DimmNibbleAccess & (1 << Dimm)) != 0) {
+            //
+            // If 2D x4 (Not Currently POR for LRDIMMs)
+            //
+            for (i = 0; i < MAX_NUMBER_LANES; i++) {
+              if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) {
+                // If logical QR LRDIMM, copy trained delays from first rank to third rank
+                RdDqs2dDly = ChannelPtr->RdDqs2dDlys[Dimm * MAX_NUMBER_LANES + i];
+                NBPtr->SetTrainDly (NBPtr, excel845 , DIMM_NBBL_ACCESS (Dimm + 2, i),
+                                    ChannelPtr->RdDqs2dDlys[Dimm * MAX_NUMBER_LANES + i]);
+                ChannelPtr->RdDqs2dDlys[(Dimm + 2) * MAX_NUMBER_LANES + i] = (UINT8)RdDqs2dDly;
+              }
+            }
+          }
+        }
+      }
+    }
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function performs LRDIMM specific tasks during Dimm Presence detection
+ *
+ *     @param[in,out]  *TechPtr     - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]  *DimmID      - Dimm ID
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+STATIC
+MemTLrdimmPresence (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *DimmID
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  UINT32 BufferID;
+  UINT8 Dimm;
+  NBPtr = TechPtr->NBPtr;
+  Dimm = *(UINT8*) DimmID;
+
+  BufferID = MemTLrDimmGetBufferID (TechPtr, Dimm);
+  if ((BufferID == 0x0020B304) || (BufferID == 0x0020B380)) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\tDimm %d: Unsupported LRDIMM Buffer Revision\n", Dimm);
+    PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, Dimm, &NBPtr->MemPtr->StdHeader);
+    NBPtr->DCTPtr->Timings.CsTestFail |= (UINT16)0x3 << (Dimm << 1);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function returns LRDIMM Buffer ID Info from the SPD
+ *
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the Technology Block
+ *     @param[in]       Dimm      - Dimm number
+ *
+ *     @return          Buffer ID Information
+ *
+ */
+
+UINT32
+STATIC
+MemTLrDimmGetBufferID (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm
+  )
+{
+  UINT8   *SpdBufferPtr;
+  UINT32  BufferID;
+
+  BufferID = 0;
+  MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+  BufferID = (SpdBufferPtr[64] << 16) | (SpdBufferPtr[66] << 8) | (SpdBufferPtr[65]);
+  return BufferID;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function implements special case Initialization hooks for LRDIMMs
+ *
+ *     @param[in]     TechPtr    - Tech Block Pointer
+ *     @param[in]     Entrypoint - Entrypoint to indicate when this hook is called
+ *     @param[in]     Dimm       - Dimm being configured when hook is called
+ *     @param[in]     OptParam   - Not Used
+ */
+
+VOID
+STATIC
+MemTLrdimmInitHook (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       LRDIMM_HOOK_ENTRYPOINT Entrypoint,
+  IN       UINT8 Dimm,
+  IN OUT   VOID  *OptParam
+  )
+{
+  MEM_NB_BLOCK    *NBPtr;
+  UINT8         i;
+  CONST UINT16   AfterTstabRcwTable[] = {
+    0x0270, 0x0000,
+    0x0122, 0x0074,
+    0x0124, 0x009B,
+    0x0126, 0x00C2,
+    0x0128, 0x00E8,
+    0x01D2, 0x5942,
+    0x01D4, 0x836D,
+    0x01CE, 0x5942,
+    0x01D0, 0x836D,
+    0x01D6, 0x017F,
+    0x01D8, 0x0000,
+    0x01F0, 0x008E,
+    0x01F2, 0x00BA,
+    0x01F4, 0x00E8,
+    0x01F6, 0x0114,
+    0x0B40, 0x7054,
+    0x0B42, 0xA48A,
+    0x0B3C, 0x7054,
+    0x0B3E, 0xA48A,
+    0x0B38, 0x0100,
+    0x0B3A, 0x0000,
+
+    0x0274, 0x55AA,
+    0x3012, 0x0080,
+    0x3018, 0x6B80
+  };
+  if (MemTLrDimmGetBufferID (TechPtr, Dimm) != 0x0021B304) {
+    return;
+  }
+  NBPtr = TechPtr->NBPtr;
+  switch (Entrypoint) {
+  case AFTER_TSTAB:
+    MemTSendMBCtlWord3 (TechPtr, F14, RC0, 0xB);
+    for ( i = 0 ; i < (sizeof (AfterTstabRcwTable) / sizeof (UINT16)); i += 2 ) {
+      MemTSendExtMBCtlWord3 (TechPtr, AfterTstabRcwTable[i], AfterTstabRcwTable[i + 1], 2);
+    }
+    break;
+  default:
+    //
+    // If a hook entrypoint is called, it should have a case for it.
+    //
+    ASSERT (FALSE);
+    break;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.h
new file mode 100644
index 0000000000..be553114fe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.h
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * mtlrdimm3.h
+ *
+ * Definitions and declarations for DDR3 LRDIMM support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTLRDIMM3_H_
+#define _MTLRDIMM3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define RCW_FN_SELECT 7
+
+#define F0 0
+#define F1 1
+#define F2 2
+#define F3 3
+#define F4 4
+#define F5 5
+#define F6 6
+#define F7 7
+#define F8 8
+#define F9 9
+#define F10 10
+#define F11 11
+#define F12 12
+#define F13 13
+#define F14 14
+#define F15 15
+
+#define RC0 0
+#define RC1 1
+#define RC2 2
+#define RC3 3
+#define RC4 4
+#define RC5 5
+#define RC6 6
+#define RC7 7
+#define RC8 8
+#define RC9 9
+#define RC10 10
+#define RC11 11
+#define RC12 12
+#define RC13 13
+#define RC14 14
+#define RC15 15
+
+#define SPD_NONE             0
+#define SPD_67               67
+#define SPD_68               68
+#define SPD_69               69
+#define SPD_70               70
+#define SPD_71               71
+
+#define SPD_MDQ_800_1066     72
+#define SPD_QXODT_800_1066   73
+#define SPD_MR1_MR2_800_1066 77
+#define SPD_PERSONALITY_BYTE 102
+#define SPD_FREQ_DIFF_OFFSET 6
+
+#define SPECIAL_CASE         0xFF
+#define WAIT_6US             0xF6
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// LRDIMM SPECIALIZED HOOK ENTRY POINTS
+typedef enum {
+  AFTER_TSTAB,          ///< Time point after tStab
+  AFTER_RCW,            ///< Time point after LrDimm Rcw commands are sent
+  BEFORE_BUFFERTRN,     ///< Time point just before Buffer training
+  AFTER_BUFFERTRN,      ///< Time point just after Buffer training
+  BEFORE_HOST_WL,       ///< Time point before host WL
+  AFTER_HOST_WL         ///< Time point after host WL
+} LRDIMM_HOOK_ENTRYPOINT;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif  /* _MTLRDIMM3_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c
new file mode 100644
index 0000000000..a90c5c2aa6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c
@@ -0,0 +1,194 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtot3.c
+ *
+ * Technology Non-SPD Timings for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mtot3.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function adjusts the Twrwr value for DDR3.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTAdjustTwrwr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+
+  // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved.
+  if (DCTPtr->Timings.Twrwr < 2) {
+    DCTPtr->Timings.Twrwr = 2;
+  } else if (DCTPtr->Timings.Twrwr > 10) {
+    DCTPtr->Timings.Twrwr = 10;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function adjusts the Twrrd value for DDR3.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTAdjustTwrrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+
+  // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved.
+  if (DCTPtr->Timings.Twrrd < 2) {
+    DCTPtr->Timings.Twrrd = 2;
+  } else if (DCTPtr->Timings.Twrrd > 10) {
+    DCTPtr->Timings.Twrrd = 10;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets the LD value for DDR3.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  Value of LD
+ */
+
+INT8
+MemTGetLD3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  INT8 LD;
+  MEM_NB_BLOCK *NBPtr;
+  NBPtr = TechPtr->NBPtr;
+  //
+  // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
+  // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
+  // value.
+  //
+  LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5);
+
+  return LD;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h
new file mode 100644
index 0000000000..06073fb281
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtot3.h
+ *
+ * Technology Non-SPD timings for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTOT3_H_
+#define _MTOT3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+VOID
+MemTAdjustTwrwr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTAdjustTwrrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+INT8
+MemTGetLD3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTOT3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
new file mode 100644
index 0000000000..29a17307d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -0,0 +1,345 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtrci3.c
+ *
+ * Technology Control word initialization for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtrci3.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends control words
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTDramControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT8 i;
+  UINT8 RawCard;
+  UINT8 Data;
+  UINT16 CsPresent;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+  MemUWait10ns (800, MemPtr);   // wait 8us TACT must be changed to optimize to 8 MEM CLKs
+
+  // Set EnDramInit to start DRAM initialization
+
+  MemUWait10ns (600, MemPtr);   // wait 6us for PLL LOCK
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    //
+    // If chip select present
+    //
+    if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+
+      // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
+      NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
+
+      RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1];
+
+      for (i = 0; i <= 15; i++) {
+        // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
+        MemUWait10ns (800, MemPtr);
+        if ((i != 6) && (i != 7)) {
+          Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel);
+          MemTSendCtlWord3 (TechPtr, i, Data);
+        }
+      }
+    }
+  }
+  MemUWait10ns (600, MemPtr);   // wait 6us for TSTAB
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the ControlRC value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     CtrlWordNum  -  control Word number.
+ *     @param[in]     RawCard  -  Raw Card
+ *     @param[in]     ChipSel  - Target Chip Select
+ *     @return  Control Word value
+ */
+
+UINT8
+MemTGetCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CtrlWordNum,
+  IN       UINT8 RawCard,
+  IN       UINT8 ChipSel
+  )
+{
+  UINT8  Data;
+  UINT8  PowerDownMode;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Data = 0;  //Default value for all control words is 0
+  switch (CtrlWordNum) {
+  case 0:
+    Data = 0x02;  // DA4=1
+    break;
+  case 1:
+    if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) {
+      Data = 0x0C;  // if single rank, set DBA1 and DBA0
+    }
+    break;
+  case 2:
+    Data = ChannelPtr->CtrlWrd02[ChipSel >> 1];
+    break;
+  case 3:
+    Data = ChannelPtr->CtrlWrd03[ChipSel >> 1];
+    break;
+  case 4:
+    Data = ChannelPtr->CtrlWrd04[ChipSel >> 1];
+    break;
+  case 5:
+    Data = ChannelPtr->CtrlWrd05[ChipSel >> 1];
+    break;
+  case 8:
+    Data = ChannelPtr->CtrlWrd08[ChipSel >> 1];
+    break;
+  case 9:
+    // RC9 = 0xD except when partial powerdown mode is enabled and mix SR/DR or SR/QR configurations,
+    // RC9 should be 0x9 for SR and and 0xD for DR or QR RDIMMs.
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    PowerDownMode = (!TechPtr->NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(TechPtr->NBPtr->MemPtr->StdHeader));
+    if ((PowerDownMode == 1) &&
+        (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) &&
+        ((DCTPtr->Timings.DimmDrPresent != 0) || (DCTPtr->Timings.DimmQrPresent != 0))) {
+      Data = 0x09;
+    } else {
+      Data = 0x0D;
+    }
+    break;
+  case 11:
+    Data = CONVERT_VDDIO_TO_ENCODED (TechPtr->RefPtr->DDR3Voltage);
+    break;
+  default:;
+  }
+
+  return (Data & 0x0F);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends control word command
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     CmdNum  -  control number.
+ *     @param[in]     Value  -  value to send
+ *
+ */
+
+VOID
+MemTSendCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CmdNum,
+  IN       UINT8 Value
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // 1. Program MrsBank and MrsAddress.
+  //    n = [BA2, A2, A1, A0].
+  //    data = [BA1, BA0, A4, A3].
+  //    Set all other bits in MrsAddress to zero.
+  //
+  NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2));
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7));
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d RC%02d %04x\n", (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 7), CmdNum, Value);
+
+  // 2.Set SendCtrlWord=1
+  NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1);
+  // 3.Wait for BFSendCtrlWord=0
+  NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends specific control words commands before frequency change for certain DRAM buffers.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+FreqChgCtrlWrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT16 Speed;
+  UINT16 CsPresent;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    //
+    // If chip select present.
+    //
+    if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
+
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+      // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
+      NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
+
+      //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
+      MemUWait10ns (800, MemPtr);
+      if (Speed == DDR800_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 0);
+      } else if (Speed == DDR1066_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 1);
+      } else if (Speed == DDR1333_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 2);
+      } else if (Speed == DDR1600_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 3);
+      } else if (Speed == DDR1866_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 4);
+      } else {
+        ASSERT (FALSE);
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h
new file mode 100644
index 0000000000..189bbf7b03
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -0,0 +1,114 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtrci3.h
+ *
+ * Technology control word init for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTRCI3_H_
+#define _MTRCI3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+UINT8
+MemTGetCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CtrlWordNum,
+  IN       UINT8 RawCard,
+  IN       UINT8 ChipSel
+  );
+
+VOID
+MemTDramControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTRCI3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c
new file mode 100644
index 0000000000..1c0f27db11
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -0,0 +1,530 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtsdi3.c
+ *
+ * Technology Software DRAM Init for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtsdi3.h"
+#include "mtrci3.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates software DRAM init for  both DCTs
+ *   at the same time.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemTDramInitSw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n");
+  // 3.Program F2x[1,0]7C[EnDramInit]=1
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n");
+  NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1);
+  NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
+
+  // 4.wait 200us
+  MemUWait10ns (20000, MemPtr);
+
+  // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1.
+  NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1);
+
+  // 6.wait 500us
+  MemUWait10ns (50000, MemPtr);
+
+  // Do Phy Fence training before sending MRS commands
+  if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) {
+    AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+        NBPtr->PhyFenceTraining (NBPtr);
+      }
+    }
+  }
+
+  // 7.NOP or deselect & take CKE high
+  NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1);
+
+  // 8.wait 360ns
+  MemUWait10ns (36, MemPtr);
+
+  // The following steps are performed once for each channel with unbuffered DIMMs
+  // and once for each chip select on registered DIMMs:
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+
+      // Enable Dram Parity if appropriate.
+      NBPtr->FamilySpecificHook[EnableParityAfterMemRst] (NBPtr, NULL);
+
+      // The following steps are performed with registered DIMMs only and
+      // must be done for each chip select pair:
+      if (MCTPtr->Status[SbRegistered]) {
+        MemTDramControlRegInit3 (TechPtr);
+      }
+
+      // Initialize LRDIMM's register
+      TechPtr->TechnologySpecificHook[LrdimmControlRegInit] (TechPtr, NULL);
+
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+        if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+          IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+          // if chip select present
+          if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) {
+            MemTSendAllMRCmds3 (TechPtr, ChipSel);
+          }
+          // NOTE: wait 512 clocks for DLL-relock
+          MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+          if (!(MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])) {
+            break;
+          }
+        }
+      }
+
+      // 17.Send two ZQCL commands (to even then odd chip select)
+      NBPtr->sendZQCmd (NBPtr);
+      NBPtr->sendZQCmd (NBPtr);
+    }
+  }
+
+  // 18.Program F2x[1,0]7C[EnDramInit]=0
+  NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0);
+  NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
+  //
+  // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit
+  //
+  NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] (NBPtr, NBPtr);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS1 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]        Wl - Indicates if WL mode should be enabled
+ *     @param[in]        TargetDIMM - DIMM target for WL
+ */
+
+VOID
+MemTEMRS13 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       BOOLEAN Wl,
+  IN       UINT8 TargetDIMM
+  )
+{
+  UINT16 MrsAddress;
+  UINT8 MaxDimmPerCH;
+  UINT8 ChipSel;
+  UINT8  Value8;
+
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                        NBPtr->MCTPtr->SocketId,
+                                        NBPtr->ChannelPtr->ChannelID);
+  ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
+
+  // BA2=0,BA1=0,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
+
+  MrsAddress = 0;
+
+  // program MrsAddress[5,1]=output driver impedance control (DIC):
+  // based on F2x[1,0]84[DrvImpCtrl]
+  if (!(NBPtr->IsSupported[CheckDrvImpCtrl])) {
+    Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl);
+    if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+      MrsAddress |= ((UINT16) 1 << 5);
+    }
+    if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+      MrsAddress |= ((UINT16) 1 << 1);
+    }
+  } else {
+    MrsAddress |= ((UINT16) 1 << 1);
+  }
+  // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
+  // Different CS may have different RTT.
+  //
+  Value8 = NBPtr->MemNGetDramTerm (NBPtr, ChipSel);
+
+  //
+  // If Write Leveling this DIMM
+  //
+  if (Wl) {
+    if ((ChipSel / NBPtr->CsPerDelay) == TargetDIMM) {
+      // Program MrsAddress[7] = 1 for Write leveling enable
+      MrsAddress |= ((UINT16) 1 << 7);
+      if (ChipSel & 1) {
+        // Output buffer disabled, MrsAddress[7] (Qoff = 1)
+        MrsAddress |= ((UINT16) 1 << 12);
+      }
+      //  Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms
+      if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) {
+        Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel);
+      } else if (NBPtr->IsSupported[WlRttNomFor1of3Cfg] && (MaxDimmPerCH == 3)) {
+        // For some family, set Rtt_Nom = Rtt_Wr in one of three DIMMs per channel configurations
+        Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel);
+      }
+    }
+    NBPtr->FamilySpecificHook[WLMR1] (NBPtr, &MrsAddress);
+  }
+  //
+  // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs.
+  //
+  // All odd CS for 4 Dimm Systems
+  if (MaxDimmPerCH == 4) {
+    if (ChipSel & 0x01) {
+      Value8 = 0;
+    }
+  // CS 1 and 5 for 3 Dimm configs
+  } else if (MaxDimmPerCH == 3) {
+    if ((ChipSel == 1) || (ChipSel == 5)) {
+      Value8 = 0;
+    }
+  }
+  // All odd CS of any QR Dimms
+  if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
+    if (ChipSel & 0x01) {
+      Value8 = 0;
+    }
+  }
+  if ((Value8 & ((UINT8) 1 << 2)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 9);
+  }
+  if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 6);
+  }
+  if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 2);
+  }
+
+  // program MrsAddress[12]=output disable (QOFF):
+  // based on F2x[1,0]84[Qoff]
+
+  if (!NBPtr->IsSupported[CheckQoff]) {
+    if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) {
+      MrsAddress |= ((UINT16) 1 << 12);
+    }
+  }
+
+  // program MrsAddress[11]=TDQS:
+  // based on F2x[1,0]94[RDqsEn]
+
+  if ((NBPtr->DCTPtr->Timings.Dimmx4Present != 0) && (NBPtr->DCTPtr->Timings.Dimmx8Present != 0)) {
+    if (!(NBPtr->IsSupported[SetTDqsForx8DimmOnly]) || ((NBPtr->DCTPtr->Timings.Dimmx8Present & ((UINT8) 1 << (ChipSel >> 1))) != 0)) {
+      MrsAddress |= ((UINT16) 1 << 11);
+    }
+  }
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS2 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTEMRS23 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT32 MrsAddress;
+  UINT8 DramTermDyn;
+  UINT8 MaxDimmPerCH;
+  UINT8 ChipSel;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID );
+  ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
+
+  // BA2=0,BA1=1,BA0=0
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
+
+  // program MrsAddress[5:3]=CAS write latency (CWL):
+  MrsAddress = NBPtr->MemNGetMR2CWL (NBPtr);
+
+  // program MrsAddress[6]=auto self refresh method (ASR):
+  // program MrsAddress[7]=self refresh temperature range (SRT):
+  MrsAddress |= 1 << 6;
+  MrsAddress &= ( ~ (1 << 7));
+
+  // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
+  DramTermDyn = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel);
+  // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch
+  if (!(NBPtr->MCTPtr->Status[SbRegistered])) {
+    if (MaxDimmPerCH == 3) {
+      if (NBPtr->ChannelPtr->Dimms == 1) {
+        if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
+          DramTermDyn = 1;
+        }
+      }
+    }
+  }
+  MrsAddress |= (UINT16) DramTermDyn << 9;
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS3 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTEMRS33 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=1,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
+
+  // program MrsAddress[1:0]=multi purpose register address location
+  // (MPR Location):based on F2x[1,0]84[MprLoc]
+  // program MrsAddress[2]=multi purpose register
+  // (MPR):based on F2x[1,0]84[MprEn]
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This sets MRS value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTMRS3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT32 MrsAddress;
+  MEM_NB_BLOCK  *NBPtr;
+  UINT32 Ppd;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=0,BA0=0
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
+
+  // program MrsAddress[1:0]=burst length and control method
+  // (BL):based on F2x[1,0]84[BurstCtrl]
+  MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl);
+
+  // program MrsAddress[3]=1 (BT):interleaved
+  MrsAddress |= (UINT16) 1 << 3;
+
+  // program MrsAddress[6:4,2]=read CAS latency
+  MrsAddress |= NBPtr->MemNGetMR0CL (NBPtr);
+
+  // program MrsAddress[11:9]=write recovery for auto-precharge
+  MrsAddress |= NBPtr->MemNGetMR0WR (NBPtr);
+
+  // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel]
+  Ppd = NBPtr->GetBitField (NBPtr, BFPchgPDModeSel);
+  NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Ppd);
+  IDS_OPTION_HOOK (IDS_MEM_MR0, &Ppd, &TechPtr->NBPtr->MemPtr->StdHeader);
+  MrsAddress |= Ppd << 12;
+
+  // program MrsAddress[8]=1 (DLL):DLL reset
+  MrsAddress |= (UINT32) 1 << 8;
+
+  // During memory initialization, the value sent to MR0 is saved for S3 resume
+  NBPtr->MemNSaveMR0 (NBPtr, MrsAddress);
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This send all MR commands to a rank in sequence 2-3-1-0
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       ChipSel    - Target Chip Select
+ */
+
+VOID
+MemTSendAllMRCmds3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+
+  // 13.Send EMRS(2)
+  MemTEMRS23 (TechPtr);
+  AGESA_TESTPOINT (TpProcMemSendMRS2, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->SendMrsCmd (NBPtr);
+
+  // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
+  MemTEMRS33 (TechPtr);
+  AGESA_TESTPOINT (TpProcMemSendMRS3, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->SendMrsCmd (NBPtr);
+
+  // 15.Send EMRS(1).
+  MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1));
+  AGESA_TESTPOINT (TpProcMemSendMRS1, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->SendMrsCmd (NBPtr);
+
+  // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
+  MemTMRS3 (TechPtr);
+  AGESA_TESTPOINT (TpProcMemSendMRS0, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->SendMrsCmd (NBPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h
new file mode 100644
index 0000000000..5d2e11f539
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -0,0 +1,123 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtsdi3.h
+ *
+ * Technology software DRAM init for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTSDI3_H_
+#define _MTSDI3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemTEMRS33 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTMRS3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTEMRS13 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       BOOLEAN Wl,
+  IN       UINT8 TargetDIMM
+  );
+
+VOID
+MemTEMRS23 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTSDI3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
new file mode 100644
index 0000000000..4b799770bc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -0,0 +1,1221 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtspd3.c
+ *
+ * Technology SPD supporting functions for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mu.h"
+#include "mtspd3.h"
+#include "mftds.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemTCRCCheck3 (
+  IN OUT   UINT8 *SPDPtr
+  );
+
+UINT8
+STATIC
+MemTSPDGetTCL3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+STATIC
+MemTCheckBankAddr3 (
+  IN       UINT8 Encode,
+     OUT   UINT8 *Index
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DRAM mode
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that the DRAM mode is set to DDR3
+ */
+
+BOOLEAN
+MemTSetDramMode3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTDIMMPresence3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 *SpdBufferPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_NB_BLOCK *NBPtr;
+  BOOLEAN SPDCtrl;
+  UINT8 Devwidth;
+  UINT8 MaxDimms;
+  UINT8 NumDimmslots;
+  UINT8 Value8;
+  UINT16  DimmMask;
+  UINT32 DimmValidMask;
+
+  NBPtr = TechPtr->NBPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
+  DimmValidMask = 0;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      ChannelPtr->DimmQrPresent = 0;
+      //
+      // Get the maximum number of DIMMs
+      //
+      MaxDimms = MAX_DIMMS_PER_CHANNEL;
+      NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            MCTPtr->SocketId,
+                                            ChannelPtr->ChannelID);
+      DimmValidMask |= (NumDimmslots == 3) ? 0x7 : 0x3;
+
+      for (i = 0; i < MaxDimms; i++) {
+        //  Bitmask representing dimm #i.
+        DimmMask = (UINT16)1 << i;
+        //
+        if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) {
+          MCTPtr->DimmPresent |= DimmMask;
+          //
+          //  Check for valid checksum value
+          //
+          AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
+          if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) {
+            ChannelPtr->ChDimmValid |= DimmMask;
+            MCTPtr->DimmValid |= DimmMask;
+          } else if (NBPtr->IsSupported[excel847_0 ]) {
+            return FALSE;
+          } else {
+            // Current socket is set up to only support DDR3 dimms.
+            IDS_ERROR_TRAP;
+          }
+          if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) {
+            //
+            // NV_SPDCHK_RESTRT is set to 0,
+            // cannot ignore faulty SPD checksum
+            //
+            //  Indicate checksum error
+            ChannelPtr->DimmSpdCse |= DimmMask;
+            PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            SetMemError (AGESA_ERROR, MCTPtr);
+          }
+          //
+          //  Check module type information.
+          //
+          if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_LRDIMM) {
+            //
+            // LRDIMMS
+            //
+            if (i < NumDimmslots) {
+              ChannelPtr->LrDimmPresent |= DimmMask;
+              MCTPtr->LrDimmPresent |= DimmMask;
+
+              if (!UserOptions.CfgMemoryLRDimmCapable) {
+                PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+                IDS_ERROR_TRAP;
+              }
+              TechPtr->TechnologySpecificHook[LrdimmPresence] (TechPtr, &i);
+            }
+          }
+          if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) {
+            //
+            // RDIMMS
+            //
+            ChannelPtr->RegDimmPresent |= DimmMask;
+            MCTPtr->RegDimmPresent |= DimmMask;
+            if (!UserOptions.CfgMemoryRDimmCapable) {
+              PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+              IDS_ERROR_TRAP;
+            }
+          }
+          if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) {
+            PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            IDS_ERROR_TRAP;
+          }
+          if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) {
+            ChannelPtr->SODimmPresent |= DimmMask;
+            if (!UserOptions.CfgMemorySODimmCapable) {
+              PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+              IDS_ERROR_TRAP;
+            }
+          }
+          //
+          //  Check error correction type
+          //
+          if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) {
+            MCTPtr->DimmEccPresent |= DimmMask;  //  Dimm has ECC
+          }
+          //
+          //  Get the Dimm width data
+          //
+          Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7;
+          switch (Devwidth) {
+          case 0:
+            ChannelPtr->Dimmx4Present |= DimmMask;
+            if ((ChannelPtr->LrDimmPresent & DimmMask) == 0) {
+              //
+              // DimmNibbleAccess indicates that a DIMM will use nibble signaling and use nibble training.
+              // LRDIMMs will not use Nibble based signaling even if x4 parts are present.
+              //
+              if (i < NumDimmslots) {
+                ChannelPtr->DimmNibbleAccess |= DimmMask;
+              }
+            }
+            Devwidth = 4;
+            break;
+          case 1:
+            ChannelPtr->Dimmx8Present |= DimmMask;
+            Devwidth = 8;
+            break;
+          case 2:
+            ChannelPtr->Dimmx16Present |= DimmMask;
+            Devwidth = 16;
+            break;
+          default:
+            IDS_ERROR_TRAP;
+          }
+          //
+          //  Check for 'analysis probe installed'
+          // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK)
+          //
+          //  Determine the geometry of the DIMM module
+          // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT)
+          //
+          //  specify the number of ranks
+          //
+          Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
+          if (Value8 == 5) {
+            // Octal Rank
+            Value8 = 8;
+          }
+          //
+          // For LRDIMMS we will assume that if there are at least 4 Physical ranks, then it Could be used
+          // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will
+          // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks.
+          //
+          if ((ChannelPtr->LrDimmPresent & DimmMask) != 0) {
+            //
+            // LRDIMM Physical Ranks
+            //
+            ChannelPtr->LrdimmPhysicalRanks[i] = Value8;
+          }
+          if (Value8 > 2) {
+            if (!UserOptions.CfgMemoryQuadRankCapable) {
+              PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            }
+            //
+            // Mark this Dimm as Quad Rank
+            //
+            ChannelPtr->DimmQrPresent |= DimmMask;
+            Value8 = 2;
+          } else if (Value8 == 2) {
+            ChannelPtr->DimmDrPresent |= DimmMask;   //  Dual rank dimms
+          } else {
+            ChannelPtr->DimmSRPresent |= DimmMask;   //  Single rank dimms
+          }
+          //
+          //  Calculate bus loading per Channel
+          if (Devwidth == 16) {
+            Devwidth = 4;
+          } else if (Devwidth == 4) {
+            Devwidth = 16;
+          }
+          //
+          //  Double Addr bus load value for dual rank DIMMs (Unless LRDIMM)
+          //
+          if (((ChannelPtr->LrDimmPresent & DimmMask) == 0) && (Value8 == 2) ) {
+            Devwidth = Devwidth << 1;
+          }
+          //
+          ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
+          ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
+          if ((i < NumDimmslots) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) {
+            ChannelPtr->Dimms++;
+          }
+          //
+          // Check address mirror support for Unbuffered Dimms or LRDimms
+          //
+          if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) {
+            if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
+              ChannelPtr->DimmMirrorPresent |= DimmMask;
+            }
+          }
+          //
+          // Get byte62: Reference Raw Card information
+          //
+          ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F;
+          //
+          // Get control word values for RC3, RC4 and RC5
+          //
+          ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4;
+          ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F;
+          ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4;
+          //
+          // Temporarily store info. of SPD byte 63 into CtrlWrd02(s),
+          // and they will be used late to calculate real RC2 and RC8 value
+          //
+          ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
+          //
+          // Copy the number of registers to the Ps Block to persist across frequency changes
+          //
+          NBPtr->PsPtr->NumOfReg[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
+          //
+          // Workaround for early revisions of DIMMs which SPD byte 63 is 0
+          //
+          if (NBPtr->PsPtr->NumOfReg[i] == JED_UNDEFINED) {
+            NBPtr->PsPtr->NumOfReg[i] = 1;
+          }
+        } // if DIMM present
+      } // Dimm loop
+
+      if (Channel == 0) {
+        DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
+        DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent;
+        DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
+        DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
+        DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
+        DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent;
+        DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
+        DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
+        DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
+      }
+      if ((Channel != 1) || (Dct != 1)) {
+        MCTPtr->DimmPresent <<= 8;
+        MCTPtr->DimmValid <<= 8;
+        MCTPtr->RegDimmPresent <<= 8;
+        MCTPtr->LrDimmPresent <<= 8;
+        MCTPtr->DimmEccPresent <<= 8;
+        MCTPtr->DimmParPresent <<= 8;
+        DimmValidMask <<= 8;
+      }
+    } // Channel loop
+  } // DCT loop
+
+  //  If we have DIMMs, some further general characteristics checking
+  if (MCTPtr->DimmValid != 0) {
+    //  If there are registered dimms, all the dimms must be registered
+    if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
+      //  All dimms registered
+      MCTPtr->Status[SbRegistered] = TRUE;
+      MCTPtr->Status[SbParDimms] = TRUE;  //  All DDR3 RDIMMs are parity capable
+      TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing
+    } else if (MCTPtr->RegDimmPresent != 0) {
+      //  We have an illegal DIMM mismatch
+      PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_FATAL, MCTPtr);
+    }
+    //  If there are LrDimms, all the dimms must be LrDimms
+    if (MCTPtr->LrDimmPresent == (MCTPtr->DimmValid & DimmValidMask)) {
+      //  All dimms LRDIMMs
+      MCTPtr->Status[SbLrdimms] = TRUE;
+      MCTPtr->Status[SbParDimms] = TRUE;  //  All DDR3 RDIMMs are parity capable
+    } else if (MCTPtr->LrDimmPresent != 0) {
+      //  We have an illegal DIMM mismatch
+      PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_FATAL, MCTPtr);
+    }
+
+    //  check the ECC capability of the DIMMs
+    if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
+      MCTPtr->Status[SbEccDimms] = TRUE;  //  All dimms ECC capable
+    }
+  } else {
+  }
+
+  NBPtr->SwitchDCT (NBPtr, 0);
+  NBPtr->SwitchChannel (NBPtr, 0);
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function finds the maximum frequency that each channel is capable to run at.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDGetTargetSpeed3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferPtr;
+  UINT8 Dimm;
+  UINT8 Dct;
+  UINT8 Channel;
+  INT32 MTB_ps;
+  INT32 FTB_ps;
+  INT32 TCKmin_ps;
+  INT32 Value32;
+  MEM_NB_BLOCK *NBPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    TCKmin_ps = 0;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
+          MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+
+          // Determine tCKmin(all) which is the largest tCKmin
+          // value for all modules on the memory Channel (SPD byte 12).
+          //
+          MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR];
+          FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF);
+          Value32 = (MTB_ps * SpdBufferPtr[SPD_TCK]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TCK_FTB]) ;
+          if (TCKmin_ps < Value32) {
+            TCKmin_ps = Value32;
+          }
+        }
+      }
+    }
+    if (TCKmin_ps <= 938) {
+      DCTPtr->Timings.TargetSpeed = DDR2133_FREQUENCY;
+    } else if (TCKmin_ps <= 1071) {
+      DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY;
+    } else if (TCKmin_ps <= 1250) {
+      DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY;
+    } else if (TCKmin_ps <= 1500) {
+      DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY;
+    } else if (TCKmin_ps <= 1875) {
+      DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY;
+    } else if (TCKmin_ps <= 2500) {
+      DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY;
+    } else {
+      DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY;
+    }
+  }
+
+  // Ensure the target speed can be applied to all channels of the current node
+  NBPtr->SyncTargetSpeed (NBPtr);
+
+  // Set the start-up frequency
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed;
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
+ *   DIMM on Channel B), the overall DIMM population, and determine the width mode:
+ *   64-bit, 64-bit muxed, 128-bit.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDCalcWidth3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferAPtr;
+  UINT8 *SpdBufferBPtr;
+  MEM_NB_BLOCK *NBPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 i;
+  UINT16 DimmMask;
+  UINT8 UngangMode;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  UngangMode = UserOptions.CfgMemoryModeUnganged;
+  // Does not support ganged mode for DDR3 dimms
+  ASSERT (UngangMode);
+  IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
+
+  //  Check symmetry of channel A and channel B dimms for 128-bit mode
+  //  capability.
+  //
+  AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
+  i = 0;
+  if (!UngangMode) {
+    if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
+      for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
+        DimmMask = (UINT16)1 << i;
+        if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
+          NBPtr->SwitchDCT (NBPtr, 0);
+          MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i);
+          NBPtr->SwitchDCT (NBPtr, 1);
+          MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i);
+          // compare rows and columns
+          if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) {
+            break;
+          }
+          if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) {
+            break;
+          }
+          // compare ranks and devwidth
+          if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
+            break;
+          }
+        }
+      }
+    }
+    if (i < MAX_DIMMS_PER_CHANNEL) {
+      PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ALERT, MCTPtr);
+    } else {
+      NBPtr->Ganged = TRUE;
+      MCTPtr->GangedMode = TRUE;
+      MCTPtr->Status[Sb128bitmode] = TRUE;
+      NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
+    }
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       Initialize DCT Timing registers as per DIMM SPD.
+ *       For primary timing (T, CL) use best case T value.
+ *       For secondary timing params., use most aggressive settings
+ *           of slowest DIMM.
+ *
+ *   Note:
+ *   There are three components to determining "maximum frequency": SPD component,
+ *   Bus load component, and "Preset" max frequency component.
+ *   The SPD component is a function of the min cycle time specified by each DIMM,
+ *   and the interaction of cycle times from all DIMMs in conjunction with CAS
+ *   latency.  The SPD component only applies when user timing mode is 'Auto'.
+ *
+ *   The Bus load component is a limiting factor determined by electrical
+ *   characteristics on the bus as a result of varying number of device loads.  The
+ *   Bus load component is specific to each platform but may also be a function of
+ *   other factors.  The bus load component only applies when user timing mode is
+ * ' Auto'.
+ *
+ *   The Preset component is subdivided into three items and is the minimum of
+ *   the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
+ *   memclock mode is 'Limit', OEM build specification of the maximum frequency.
+ *   The Preset component only applies when user timing mode is 'Auto'.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTAutoCycTiming3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  CONST UINT8 SpdIndexes[] = {
+    SPD_TRCD,
+    SPD_TRP,
+    SPD_TRTP,
+    SPD_TRAS,
+    SPD_TRC,
+    SPD_TWR,
+    SPD_TRRD,
+    SPD_TWTR,
+    SPD_TFAW
+  };
+
+  CONST UINT8 SpdFTBIndexes[] = {
+    SPD_TRCD_FTB,
+    SPD_TRP_FTB,
+    0,
+    0,
+    SPD_TRC_FTB,
+    0,
+    0,
+    0,
+    0
+  };
+
+  UINT8  *SpdBufferPtr;
+  INT32  MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
+  UINT8  MiniMaxTrfc[4];
+
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 DimmMask;
+  INT32 Value32;
+  INT32 MTB_ps;
+  INT32 FTB_ps;
+  INT32 TCK_ps;
+  UINT8 i;
+  UINT8 j;
+  UINT8 Value8;
+  UINT8  *StatTmgPtr;
+  UINT16 *StatDimmTmgPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  // initialize mini-max arrays
+  for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
+    MiniMaxTmg[j] = 0;
+  }
+  for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
+    MiniMaxTrfc[j] = 0;
+  }
+
+  // ======================================================================
+  //  Get primary timing (CAS Latency and Cycle Time)
+  // ======================================================================
+  //  Get OEM specific load variant max
+  //
+
+  //======================================================================
+  // Gather all DIMM mini-max values for cycle timing data
+  //======================================================================
+  //
+  DimmMask = 1;
+  for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
+    if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
+      MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i);
+      MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR];
+      FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF);
+
+      for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
+        Value32 = (UINT16)SpdBufferPtr[SpdIndexes[j]];
+        if (SpdIndexes[j] == SPD_TRC) {
+          Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4;
+        } else if (SpdIndexes[j] == SPD_TRAS) {
+          Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8;
+        } else if (SpdIndexes[j] == SPD_TFAW) {
+          Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8;
+        }
+
+        Value32 *= MTB_ps;
+        if (SpdFTBIndexes[j] != 0) {
+          Value32 += (FTB_ps * (INT8) SpdBufferPtr[SpdFTBIndexes[j]]) ;
+        }
+        if (MiniMaxTmg[j] < Value32) {
+          MiniMaxTmg[j] = Value32;
+        }
+      }
+
+      //  get Trfc0 - Trfc3 values
+      Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F;
+      if (MiniMaxTrfc[i] < Value8) {
+        MiniMaxTrfc[i] = Value8;
+      }
+    }
+    DimmMask <<= 1;
+  }
+
+  // ======================================================================
+  //  Convert  DRAM CycleTiming values and store into DCT structure
+  // ======================================================================
+  //
+  TCK_ps = 1000500 / DCTPtr->Timings.Speed;
+
+  StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
+  StatTmgPtr = &DCTPtr->Timings.Trcd;
+  for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
+    Value32 = MiniMaxTmg[j];
+
+    MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK_ps - 1) / TCK_ps;
+
+    StatDimmTmgPtr[j] = (UINT16) (Value32 / (1000 / 40));
+    StatTmgPtr[j] = (UINT8) MiniMaxTmg[j];
+  }
+  DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
+  DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
+  DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
+  DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
+
+  DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr);
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  NBPtr->ProgramCycTimings (NBPtr);
+
+  MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the bank addressing, program Mask values and build a chip-select population map.
+ *   This routine programs PCI 0:24N:2x80 config register.
+ *   This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDSetBanks3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferPtr;
+  UINT8 i;
+  UINT8 ChipSel;
+  UINT8 DimmID;
+  UINT8 Value8;
+  UINT8 Rows;
+  UINT8 Cols;
+  UINT8 Ranks;
+  UINT8 Banks;
+  UINT32 BankAddrReg;
+  UINT32 CsMask;
+  UINT16 CSSpdCSE;
+  UINT16 CSExclude;
+  UINT16 DimmQRDR;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  BankAddrReg = 0;
+  CSSpdCSE = 0;
+  CSExclude = 0;
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    DimmID = ChipSel >> 1;
+
+    DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
+    if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) {
+      CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
+    }
+    if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
+      CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
+    }
+
+    if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) {
+      MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID);
+
+      //  Get the basic data
+      Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7;
+      Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7;
+      Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7;
+      Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
+      if (Ranks == 5) {
+        Ranks = 8;
+      }
+      //
+      // Configure the bank encoding
+      // Use a 6-bit key into a lookup table.
+      // Key (index) = RRRBCC, where CC is the number of Columns minus 9,
+      // RRR is the number of Rows minus 12, and B is the number of banks
+      // minus 3.
+      //
+      Value8 = Cols;
+      Value8 |= (Banks == 1) ? 4 : 0;
+      Value8 |= Rows << 3;
+
+      if (MemTCheckBankAddr3 (Value8, &i)) {
+        //
+        // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
+        // or 2pow(rows+cols+banks-5)-1
+        //
+        Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8;
+        if (MCTPtr->Status[Sb128bitmode]) {
+          Value8++;
+        }
+
+        DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
+
+        if (Ranks >= 2) {
+          DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
+        }
+        //
+        // Determine LRDIMM Rank Multiplication
+        //
+        if (TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] (TechPtr, &DimmID)) {
+          //
+          // Increase the CS Size by the rank multiplication factor
+          //
+          Value8 += ((NBPtr->ChannelPtr->LrDimmRankMult[DimmID]) >> 1);
+          CsMask = ((UINT32)1 << Value8) - 1;
+          CsMask &= NBPtr->CsRegMsk;
+          CsMask |= (NBPtr->GetBitField (NBPtr, BFRankDef0 + DimmID) & 0x03);
+        } else {
+          CsMask = ((UINT32)1 << Value8) - 1;
+          CsMask &= NBPtr->CsRegMsk;
+        }
+        //
+        //  Update the DRAM CS Mask and BankAddrReg for this chipselect
+        //
+        if ((DCTPtr->Timings.CsPresent & (UINT16)3 << ChipSel) != 0) {
+          NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask));
+          BankAddrReg |= ((UINT32)i << (ChipSel << 1));
+        }
+      } else {
+        //
+        // Dimm is not supported, as no address mapping is found.
+        //
+        DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
+        DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel;
+        if (Ranks >= 2) {
+          DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
+          DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1);
+        }
+        PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader);
+        SetMemError (AGESA_ERROR, MCTPtr);
+      }
+    } //if (MemTCheckBankAddr3 (Value8, &i)
+  }
+  // For ranks that need to be excluded, the loading of this rank should be considered
+  // in timing, so need to set CsPresent before setting CsTestFail
+  if ((CSSpdCSE != 0) || (CSExclude != 0)) {
+    if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader)) {
+      ASSERT (FALSE);
+    }
+  }
+
+  //  If there are no chip selects, we have an error situation.
+  if (DCTPtr->Timings.CsPresent == 0) {
+    PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, MCTPtr);
+  }
+
+  NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the low bit that will be swapped to enable CS interleaving
+ *
+ *     @param[in]   BankEnc - AddrMap Bank encoding from F2x80
+ *     @param[in]   *LowBit - pointer to low bit
+ *     @param[in]   *HiBit  - pointer hight bit
+ *
+ */
+
+VOID
+MemTGetCSIntLvAddr3 (
+  IN       UINT8 BankEnc,
+     OUT   UINT8 *LowBit,
+     OUT   UINT8 *HiBit
+  )
+{
+  CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9};
+  CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25};
+  ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
+  ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
+  //  return ArrCodes[BankEnc];
+  *LowBit = ArrCodesLo[BankEnc];
+  *HiBit = ArrCodesHi[BankEnc];
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function determines if the checksum is correct
+ *
+ *     @param[in]   *SPDPtr - Pointer to SPD data
+ *
+ *     @return    TRUE  - CRC check passes
+ *     @return    FALSE - CRC check fails
+ */
+
+BOOLEAN
+STATIC
+MemTCRCCheck3 (
+  IN OUT   UINT8 *SPDPtr
+  )
+{
+  UINT16 Crc;
+  INT16 i;
+  INT16 j;
+  INT16 Count;
+
+  if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) {
+    Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126;
+    Crc = 0;
+    for (j = 0; j < Count; j++) {
+      Crc = Crc ^ ((UINT16)SPDPtr[j] << 8);
+      for (i = 0; i < 8; i++) {
+        if (Crc & 0x8000) {
+          Crc = (Crc << 1) ^ 0x1021;
+        } else {
+          Crc = (Crc << 1);
+        }
+      }
+    }
+    if (*(UINT16 *) (SPDPtr + 126) == Crc) {
+      return TRUE;
+    }
+  }
+
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  CAS Latency
+ */
+
+UINT8
+STATIC
+MemTSPDGetTCL3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8  *SpdBufferPtr;
+  UINT8 CLdesired;
+  UINT8 CLactual;
+  UINT8 Dimm;
+  UINT8 Channel;
+  UINT16 CASLat;
+  UINT16 Mask16;
+  INT32 MTB_ps;
+  INT32 FTB_ps;
+  INT32 TAAmin_ps;
+  INT32 TCKproposed_ps;
+  INT32 Value32;
+  BOOLEAN CltFail;
+  MEM_NB_BLOCK *NBPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  CASLat = 0xFFFF;
+  TAAmin_ps = 0;
+  CltFail = FALSE;
+
+  for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+    NBPtr->SwitchChannel (NBPtr, Channel);
+    ChannelPtr = NBPtr->ChannelPtr;
+    for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+      if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
+        MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+
+        // Step 1: Determine the common set of supported CAS Latency
+        // values for all modules on the memory Channel using the CAS
+        // Latencies Supported in SPD bytes 14 and 15.
+        //
+        CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO];
+
+        // Step 2: Determine tAAmin(all) which is the largest tAAmin
+        // value for all modules on the memory Channel (SPD byte 16).
+        //
+        MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR];
+        FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF);
+        Value32 = (MTB_ps * SpdBufferPtr[SPD_TAA]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TAA_FTB]) ;
+        if (TAAmin_ps < Value32) {
+          TAAmin_ps = Value32;
+        }
+
+        // Step 3: Determine tCKmin(all) which is the largest tCKmin
+        // value for all modules on the memory Channel (SPD byte 12).
+        // * This step has been done in SPDGetTargetSpeed
+      }
+    }
+  }
+
+  TCKproposed_ps = 1000500 / DCTPtr->Timings.Speed;
+
+  // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax,
+  // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC
+  // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the
+  // next lower standard tCK value for calculating CLdesired.
+  // CLdesired = ceiling ( tAAmin(all) / tCKproposed )
+  // where tAAmin is defined in Byte 16. The ceiling function requires that the
+  // quotient be rounded up always.
+  //
+  CLdesired = (UINT8) ((TAAmin_ps + TCKproposed_ps - 1) / TCKproposed_ps);
+
+  // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal
+  // to CLdesired and is supported by all modules on the memory Channel as
+  // determined in step 1. If no such value exists, choose a higher tCKproposed
+  // value and repeat steps 4 and 5 until a solution is found.
+  //
+  CLactual = 4;
+  for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) {
+    if (CASLat & Mask16) {
+      if (CLdesired <= CLactual) {
+        break;
+      }
+    }
+    CLactual++;
+  }
+  if (Mask16 == 0x8000) {
+    CltFail = TRUE;
+  }
+
+  // Step 6: Once the calculation of CLactual is completed, the BIOS must also
+  // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns
+  // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If
+  // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found.
+  //
+  if ((TCKproposed_ps * CLactual) > 20000) {
+    CltFail = TRUE;
+  }
+
+  if (!CltFail) {
+    DCTPtr->Timings.CasL = CLactual;
+  } else {
+    //  Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin.
+    DCTPtr->Timings.CasL = 6;
+  }
+
+  return DCTPtr->Timings.CasL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function returns the encoded value of bank address.
+ *
+ *     @param[in]   Encode - RRRBCC, where CC is the number of Columns minus 9,
+ *                           RRR is the number of Rows minus 12, and B is the number of banks
+ *                           minus 3.
+ *     @param[out]  *Index - index in bank address table
+ *     @return      TRUE   - encoded value is found.
+ *                  FALSE  - encoded value is not found.
+ */
+
+BOOLEAN
+STATIC
+MemTCheckBankAddr3 (
+  IN       UINT8 Encode,
+     OUT   UINT8 *Index
+  )
+{
+  UINT8 i;
+  CONST UINT8 TabBankAddr[]  = {
+    0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11,
+    0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22
+  };
+
+  for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) {
+    if (Encode == TabBankAddr[i]) {
+      *Index = i;
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function returns a pointer to the SPD Buffer of a specific dimm on
+ *    the current channel.
+ *
+ *     @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
+ *     @param[in] Dimm - Dimm number
+ *
+ *
+ *     @return BOOLEAN - Value of DimmPresent
+ *                       TRUE = Dimm is present, pointer is valid
+ *                       FALSE = Dimm is not present, pointer has not been modified.
+ */
+
+BOOLEAN
+MemTGetDimmSpdBuffer3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 **SpdBuffer,
+  IN       UINT8 Dimm
+  )
+{
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SPDPtr;
+  BOOLEAN DimmPresent;
+
+  DimmPresent = FALSE;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
+  SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
+
+
+  if (SPDPtr != NULL) {
+    DimmPresent = SPDPtr->DimmPresent;
+    if (DimmPresent) {
+      *SpdBuffer = SPDPtr->Data;
+    }
+  }
+  return DimmPresent;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
new file mode 100644
index 0000000000..8eb9829238
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -0,0 +1,203 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtspd3.h
+ *
+ * Technology SPD support for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTSPD3_H_
+#define _MTSPD3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*===============================================================================
+ *   Jedec DDR III
+ *===============================================================================
+ */
+#define SPD_BYTE_USED     0
+#define SPD_TYPE         2              /* SPD byte read location */
+#define JED_DDR_SDRAM     7              /* Jedec defined bit field */
+#define JED_DDR2_SDRAM    8              /* Jedec defined bit field */
+#define JED_DDR3SDRAM    0xB            /* Jedec defined bit field */
+
+#define SPD_DIMM_TYPE    3
+#define SPD_ATTRIB      21
+#define JED_DIF_CK_MSK    0x20            /* Differential Clock Input */
+#define JED_RDIMM       1
+#define JED_MINIRDIMM   5
+#define JED_UDIMM       2
+#define JED_SODIMM       3
+#define JED_LRDIMM      0xB
+#define JED_UNDEFINED   0                /* Undefined value */
+
+#define SPD_L_BANKS      4               /* [7:4] number of [logical] banks on each device */
+#define SPD_DENSITY     4               /* bit 3:0 */
+#define SPD_ROW_SZ       5               /* bit 5:3 */
+#define SPD_COL_SZ       5               /* bit 2:0 */
+#define SPD_RANKS       7               /* bit 5:3 */
+#define SPD_DEV_WIDTH    7               /* bit 2:0 */
+#define SPD_ECCBITS     8               /* bit 4:3 */
+#define JED_ECC         8
+#define SPD_RAWCARD     62              /* bit 2:0 */
+#define SPD_ADDRMAP     63              /* bit 0 */
+
+#define SPD_CTLWRD03     70              /* bit 7:4 */
+#define SPD_CTLWRD04     71              /* bit 3:0 */
+#define SPD_CTLWRD05     71              /* bit 7:4 */
+
+#define SPD_FTB          9
+
+#define SPD_DIVIDENT    10
+#define SPD_DIVISOR     11
+
+#define SPD_TCK         12
+#define SPD_CASLO       14
+#define SPD_CASHI       15
+#define SPD_TAA         16
+
+#define SPD_TRP         20
+#define SPD_TRRD        19
+#define SPD_TRCD        18
+#define SPD_TRAS        22
+#define SPD_TWR         17
+#define SPD_TWTR        26
+#define SPD_TRTP        27
+#define SPD_TRC         23
+#define SPD_UPPER_TRC   21              /* bit 7:4 */
+#define SPD_UPPER_TRAS  21              /* bit 3:0 */
+#define SPD_TFAW        29
+#define SPD_UPPER_TFAW  28              /* bit 3:0 */
+
+#define SPD_TCK_FTB     34
+#define SPD_TAA_FTB     35
+#define SPD_TRCD_FTB    36
+#define SPD_TRP_FTB     37
+#define SPD_TRC_FTB     38
+
+/*-----------------------------
+ * Jedec DDR II related equates
+ *-----------------------------
+ */
+
+#define CL_DEF          4              /* Default value for failsafe operation. 4=CL 6.0 T */
+#define T_DEF           4              /* Default value for failsafe operation. 4=2.5ns (cycle time) */
+
+#define BIAS_TRTP_T      4
+#define BIAS_TRCD_T      5
+#define BIAS_TRAS_T      15
+#define BIAS_TRC_T       11
+#define BIAS_TRRD_T      4
+#define BIAS_TWR_T       4
+#define BIAS_TRP_T       5
+#define BIAS_TWTR_T      4
+#define BIAS_TFAW_T      14
+
+#define MIN_TRTP_T       4
+#define MAX_TRTP_T       7
+#define MIN_TRCD_T       5
+#define MAX_TRCD_T       12
+#define MIN_TRAS_T       15
+#define MAX_TRAS_T       30
+#define MIN_TRC_T        11
+#define MAX_TRC_T        42
+#define MIN_TRRD_T       4
+#define MAX_TRRD_T       7
+#define MIN_TWR_T        5
+#define MAX_TWR_T        12
+#define MIN_TRP_T        5
+#define MAX_TRP_T        12
+#define MIN_TWTR_T       4
+#define MAX_TWTR_T       7
+#define MIN_TFAW_T       16
+#define MAX_TFAW_T       32
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#endif  /* _MTSPD3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c
new file mode 100644
index 0000000000..09bc43cc2b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -0,0 +1,190 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttecc3.c
+ *
+ * Technology ECC byte support for registered DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DQS ECC timings for registered DDR3
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTSetDQSEccTmgsRDdr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Dimm;
+  UINT8 i;
+  UINT8 *WrDqsDly;
+  UINT16 *RcvEnDly;
+  UINT8 *RdDqsDly;
+  UINT8 *WrDatDly;
+  UINT8 EccByte;
+  INT16 TempValue;
+
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  EccByte = TechPtr->MaxByteLanes ();
+  NBPtr = TechPtr->NBPtr;
+
+  if (NBPtr->MCTPtr->NodeMemSize) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+          if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) {
+            i = Dimm * TechPtr->DlyTableWidth ();
+            WrDqsDly = &ChannelPtr->WrDqsDlys[i];
+            RcvEnDly = &ChannelPtr->RcvEnDlys[i];
+            RdDqsDly = &ChannelPtr->RdDqsDlys[i];
+            WrDatDly = &ChannelPtr->WrDatDlys[i];
+            // Receiver DQS Enable:
+            // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 -
+            //                                        [write DQS for bytelane 3 - write DQS for ECC]
+
+            TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]);
+            if (TempValue < 0) {
+              TempValue = 0;
+            }
+            RcvEnDly[EccByte] = (UINT16) TempValue;
+
+            // Read DQS:
+            // Read DQS for ECC bytelane = read DQS of byte lane 3
+            //
+            RdDqsDly[EccByte] = RdDqsDly[3];
+
+            // Write Data:
+            // Write Data for ECC bytelane = Write DQS for ECC +
+            //                               [write data for bytelane 3 - Write DQS for bytelane 3]
+            TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3]));
+            if (TempValue < 0) {
+              TempValue = 0;
+            }
+            WrDatDly[EccByte] = (UINT8) TempValue;
+
+            NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]);
+            NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]);
+            NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]);
+          }
+        }
+      }
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c
new file mode 100644
index 0000000000..45884a6c17
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -0,0 +1,742 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttwl3.c
+ *
+ * Technology Phy assisted write levelization for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mp.h"
+#include "mtsdi3.h"
+#include "mtlrdimm3.h"
+#include "merrhdl.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTWriteLevelizationHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTWLPerDimmHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTPrepareDIMMs3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 TargetDIMM,
+  IN       BOOLEAN Wl
+  );
+
+VOID
+STATIC
+MemTProcConfig3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTBeginWLTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of Phy assisted write levelization
+ *      for a specific node (DDR800).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTWriteLevelizationHw3 (TechPtr, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes second pass of Phy assisted write levelization
+ *      for a specific node (DDR1066 and above).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  // If current speed is higher than start-up speed, do second pass of WL
+  if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
+    return MemTWriteLevelizationHw3 (TechPtr, 2);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function prepares for Phy assisted training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTPreparePhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  //  Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1);
+  //  Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0);
+  //  Attempt to get the seeds value from PSC tables for WL and RxEn pass1 training if applicable.
+  if (!TechPtr->NBPtr->PsPtr->MemPGetPass1Seeds (TechPtr->NBPtr)) {
+    ASSERT (FALSE);
+  }
+
+  return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function revert to normal settings when exiting from Phy assisted training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTExitPhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  NBPtr = TechPtr->NBPtr;
+
+  //  13.Program F2x[1, 0]8C[DisAutoRefresh] = 0.
+  NBPtr->BrdcstSet (NBPtr, BFDisAutoRefresh, 0);
+  //  14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
+  NBPtr->BrdcstSet (NBPtr, BFZqcsInterval, 2);
+  NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] (NBPtr, NBPtr);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executed hardware based write levelization for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+STATIC
+MemTWriteLevelizationHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+
+  NBPtr = TechPtr->NBPtr;
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n");
+  AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader));
+  // Begin DQS Write timing training
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    TechPtr->WLCriticalDelay = 0x00;
+
+    //training for each Dimm/CS
+    for (ChipSel = 0; ChipSel < NBPtr->CsPerChannel; ChipSel = ChipSel + NBPtr->CsPerDelay) {
+      if ((DCTPtr->Timings.CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSel)) != 0) {
+        if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) {
+          IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+          MemTWLPerDimmHw3 (TechPtr, (ChipSel / NBPtr->CsPerDelay), Pass);
+        }
+      }
+    }
+
+    NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] (NBPtr, NULL);
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n");
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function initializes per DIMM write levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Dimm - DIMM to be trained
+ *     @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
+ *
+ */
+
+VOID
+STATIC
+MemTWLPerDimmHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  ASSERT (Dimm < (NBPtr->CsPerChannel / NBPtr->CsPerDelay));
+
+  // 1. A. Specify the target Dimm that is to be trained by programming
+  //     F2x[1, 0]9C_x08[TrDimmSel].
+  NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm);
+
+  TechPtr->TargetDIMM = Dimm;
+  NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL);
+  for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainWlPerNibble] (NBPtr, &Dimm)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) {
+    // 2. Prepare the DIMMs for write levelization using DDR3-defined
+    // MR commands.
+    MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE);
+
+    // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to
+    //     satisfy DDR3-defined internal DRAM timing.
+    NBPtr->WaitXMemClks (NBPtr, 40);
+
+    // 4. Configure the processor's DDR phy for write levelization training:
+    MemTProcConfig3 (TechPtr, Dimm, Pass);
+
+    // 5. Begin write levelization training
+    MemTBeginWLTrain3 (TechPtr, Dimm);
+  }
+  // 7. Program the target Dimm back to normal operation
+  MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function prepares the DIMMS for Write Levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] TargetDIMM - DIMM to be trained
+ *     @param[in] Wl - Indicates if WL mode should be enabled
+ *
+ */
+
+VOID
+STATIC
+MemTPrepareDIMMs3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 TargetDIMM,
+  IN       BOOLEAN Wl
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8 ChipSel;
+
+  NBPtr = TechPtr->NBPtr;
+
+  AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader));
+  ASSERT (TargetDIMM < (NBPtr->CsPerChannel / NBPtr->CsPerDelay));
+  TechPtr->TargetDIMM = TargetDIMM;
+  if (!(TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] (TechPtr, &Wl))) {
+    for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+      if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+        NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+        // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
+        MemTEMRS13 (TechPtr, Wl, TargetDIMM);
+        NBPtr->SendMrsCmd (NBPtr);
+        // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
+        MemTEMRS23 (TechPtr);
+        // Send command
+        NBPtr->SendMrsCmd (NBPtr);
+      }
+    }
+    if (Wl) {
+      // Program WrLvOdt for the Target DIMM (or CS)
+      NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[TargetDIMM]);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function programs seed values for Write Levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Dimm - DIMM to be trained
+ *     @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz)
+ *
+ */
+
+VOID
+STATIC
+MemTProcConfig3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 WrDqsDly;
+  // Memclk Delay incurred by register.
+  UINT8 MemClkRegDly;
+  UINT8 ByteLane;
+  UINT8 DefaultSeed;
+  UINT8 CurrentSeed;
+  UINT8 *Seed;
+  UINT8 RCW2;
+  UINT16 Speed;
+  INT16 WrDqsBias;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader));
+  RCW2 = ChannelPtr->CtrlWrd02[Dimm];
+  Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: ");
+  //  Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
+  //  the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
+  //  BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
+  //  use an initial total delay value.
+  if (Pass == 1) {
+    //
+    // Get the default value of seed
+    //
+    if (MCTPtr->Status[SbRegistered]) {
+      //
+      // RDIMM
+      //
+      if (Speed == DDR667_FREQUENCY) {
+        DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x3B : 0x4B;
+      } else {
+        DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51;
+      }
+    } else if (ChannelPtr->SODimmPresent != 0) {
+      //
+      // SODIMMM
+      //
+      DefaultSeed = 0x12;
+    } else if (MCTPtr->Status[SbLrdimms]) {
+      //
+      // LRDIMM
+      //
+      DefaultSeed = 0xF7;
+    } else {
+      //
+      // UDIMMM
+      //
+      DefaultSeed = 0x1A;
+    }
+
+    NBPtr->FamilySpecificHook[OverrideWLSeed] (NBPtr, &DefaultSeed);
+    ASSERT (Speed >= DDR667_FREQUENCY);
+
+    // Get platform override seed
+    Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID, Dimm,
+                                          &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader));
+    for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) {
+      // This includes ECC as byte 8
+      CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
+      ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed;
+
+      if (NBPtr->IsSupported[WLSeedAdjust]) {
+        if ((CurrentSeed & 0x20) != 0) {
+          // If (SeedGross is odd) then SeedPreGross = 1
+          CurrentSeed = (CurrentSeed & 0x1F) | 0x20;
+        } else {
+          // If (SeedGross is even) then SeedPreGross = 2
+          CurrentSeed = (CurrentSeed & 0x1F) | 0x40;
+        }
+      }
+
+      NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
+      IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed);
+    }
+  } else {
+    //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find
+    //the gross and fine delay initialization values at the target frequency. Use these values as the initial
+    //seed values when executing Pass 2, step #4.
+    for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) {
+      // This includes ECC as byte 8
+      WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane];
+      TechPtr->Bytelane = ByteLane;
+      NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] (NBPtr, &WrDqsDly);
+
+      if (MCTPtr->Status[SbRegistered]) {
+        //
+        // For Registered Dimms
+        //
+        MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30;
+      } else {
+        //
+        // Unbuffered Dimms and LRDIMMs
+        //
+        MemClkRegDly = 0;
+      }
+      //
+      // Recover any adjustmen to delay for WrDqDqsEarly
+      //
+      WrDqsBias = 0;
+      NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] (NBPtr, &WrDqsBias);
+
+      // Scale WrDqsDly to the next speed
+      WrDqsDly = (UINT16) (MemClkRegDly + ((((INT32) WrDqsDly - MemClkRegDly - WrDqsBias) * Speed) / TechPtr->PrevSpeed));
+
+      ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly;
+
+      if (NBPtr->IsSupported[WLSeedAdjust]) {
+        if ((WrDqsDly & 0x20) != 0) {
+          // If (SeedGross is odd) then SeedPreGross = 1
+          WrDqsDly = (WrDqsDly & 0x1F) | 0x20;
+        } else {
+          // If (SeedGross is even) then SeedPreGross = 2
+          WrDqsDly = (WrDqsDly & 0x1F) | 0x40;
+        }
+      }
+      NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly);
+      IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", WrDqsDly);
+    }
+  }
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function begins WL training for a specific DIMM
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Dimm - DIMM to be trained
+ *
+ */
+
+VOID
+STATIC
+MemTBeginWLTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 ByteLane;
+  UINT8 Seed;
+  UINT8 Delay;
+  INT16 Delay16;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  AGESA_TESTPOINT (TpProcMemWlTrainTargetDimm, &(MemPtr->StdHeader));
+  // Assert ODT pins for write leveling
+  NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1);
+
+  // Wait 10 MEMCLKs to allow for ODT signal settling.
+  NBPtr->WaitXMemClks (NBPtr, 10);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n");
+  // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
+  NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
+
+  //  Wait 200 MEMCLKs.
+  NBPtr->WaitXMemClks (NBPtr, 200);
+
+  //  Program F2x[1, 0]9C_x08[WrtLlTrEn]=0.
+  NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0);
+
+  //  Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
+  //  for the target Dimm and save these values.
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t  PRE: ");
+  for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+    // This includes ECC as byte 8
+    Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane];
+    Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
+    IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", Delay);
+
+    TechPtr->Bytelane = ByteLane;
+    TechPtr->TargetDIMM = Dimm;
+    NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] (NBPtr, &Delay);
+
+    if (NBPtr->IsSupported[WLSeedAdjust]) {
+      // Recover WrDqsGrossDly:
+      // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross
+      if ((Seed & 0x20) != 0) {
+        // If (SeedGross is odd) then SeedPreGross = 1
+        if ((NBPtr->IsSupported[WLNegativeDelay]) && ((Seed & 0x80) != 0)) {
+          // If the seed was negative, save the most negative delay in WLCriticalDelay
+          TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40);
+          Delay -= 0x40;
+        } else {
+          Delay += (Seed & 0xE0) - 0x20;
+        }
+      } else {
+        // If (SeedGross is even) then SeedPreGross = 2
+        if (((Seed & 0xE0) == 0) && (Delay < 0x40)) {
+          // If SeedGross is 0 and PhRecGrossDlyByte is less than SeedPreGross,
+          // we have a negative result and need to program the delay to 0
+          if (NBPtr->IsSupported[WLNegativeDelay]) {
+            //
+            // Save the lowest negative delay value across all Dimms and Bytelanes
+            //
+            TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40);
+            Delay -= 0x40;
+          } else {
+            Delay = 0;
+          }
+        } else {
+          if (NBPtr->GetBitField (NBPtr, BFWrDqDqsEarly) != 0) {
+            Delay = Delay + (Seed & 0xE0);
+            Delay16 = Delay - 0x40;
+            Delay = (UINT8)Delay16;
+            TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, Delay16);
+          } else {
+            Delay += (Seed & 0xE0) - 0x40;
+          }
+        }
+      }
+    } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
+      IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader));
+      // If seed has gross delay of 0 and PRE has gross delay of 3,
+      // then round the total delay of TxDqs to 0.
+      Delay = 0;
+    }
+
+    if ((!NBPtr->IsSupported[WLNegativeDelay]) && ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20)))) {
+      //
+      // If PRE comes back with more than Seed +/- 0x20, then this is an
+      //   unexpected condition.  Log the condition.
+      //
+      PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader);
+    }
+    NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
+    NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay;
+  }
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: ");
+    for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+  );
+
+  // Disable write leveling ODT pins
+  NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0);
+
+  // Wait 10 MEMCLKs to allow for ODT signal settling.
+  NBPtr->WaitXMemClks (NBPtr, 10);
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function programs register after Phy assisted training is finish.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTExitPhyAssistedTrainingClient3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8  Dct;
+  UINT8  ChipSel;
+  NBPtr = TechPtr->NBPtr;
+
+  NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr);
+  NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 1);
+  NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1);
+  NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n");
+  NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1);
+  NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  if (NBPtr->IsSupported[SetDllShutDown]) {
+    NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 0);
+  }
+
+  // Calculate Max Latency for both channels to prepare for position training
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
+      NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat);
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c
new file mode 100644
index 0000000000..23a7898037
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mt.c
+ *
+ * Common Technology file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemTDefaultTechnologyHook (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is the default return for non-training technology features
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ */
+BOOLEAN
+MemTFeatDef (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the TestFail bit for all CS that fail training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ */
+VOID
+MemTMarkTrainFail (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+
+  NBPtr = TechPtr->NBPtr;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.CsEnabled &= ~NBPtr->DCTPtr->Timings.CsTrainFail;
+    for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel ++) {
+      if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << ChipSel)) != 0) {
+        NBPtr->SetBitField (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (UINT32)1 << BFTestFail);
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the initial controller environment before training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  S_UINT64 SMsr;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2
+
+  LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);            // HWCR
+  TechPtr->HwcrLo = SMsr.lo;
+  SMsr.lo |= 0x00020000;                  // turn on HWCR.wrap32dis
+  SMsr.lo &= 0xFFFF7FFF;                  // turn off HWCR.SSEDIS
+  LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
+
+  TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn);
+  NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the final controller environment after training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  S_UINT64 SMsr;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg);
+
+  LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo = TechPtr->HwcrLo;
+  LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets all the bytelanes/nibbles to the same delay value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Dly - Delay value to set
+ *
+ */
+
+VOID
+MemTSetDQSDelayAllCSR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dly
+  )
+{
+  UINT8 i;
+  UINT8 MaxBytelanes;
+  MaxBytelanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8;
+
+  for (i = 0; i <  MaxBytelanes; i++) {
+    TechPtr->SetDQSDelayCSR (TechPtr, i, Dly);
+  }
+  TechPtr->NBPtr->FamilySpecificHook[RegAccessFence] (TechPtr->NBPtr, NULL);
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function is used to intialize common technology functions
+ *
+ *     @param[in,out]  *TechPtr     - Pointer to the MEM_TECH_BLOCK
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemTCommonTechInit (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 i;
+  for (i = 0; i < NumberOfTechHooks; i++) {
+    TechPtr->TechnologySpecificHook[i] = MemTDefaultTechnologyHook;
+  }
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function is an empty function used to intialize TechnologySpecificHook array
+ *
+ *     @param[in,out]  *TechPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return  FALSE - always
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemTDefaultTechnologyHook (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  return FALSE;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c
new file mode 100644
index 0000000000..55bfd0f6a0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c
@@ -0,0 +1,151 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mthdi.c
+ *
+ * Common technology hardware dram init support functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTHDI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates Hardware based dram initialization for both DCTs
+ *   at the same time.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTDramInitHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  NBPtr->BrdcstSet (NBPtr, BFInitDram, 1);
+  // Phy fence training
+  AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+      NBPtr->PhyFenceTraining (NBPtr);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
new file mode 100644
index 0000000000..73fdff40e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
@@ -0,0 +1,933 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttEdgeDetect.c
+ *
+ * DQS R/W position training utilizing Data Eye Edge Detection for optimization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "AdvancedApi.h"
+#include "GeneralServices.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mport.h"
+#include "mttEdgeDetect.h"
+#include "OptionMemory.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTEDGEDETECT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#define LAST_DELAY    (-128)
+#define INC_DELAY     1
+#define DEC_DELAY     0
+
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Sweep Table For Byte Training without insertion delay
+ *
+*/
+DQS_POS_SWEEP_TABLE SweepTableByte[] =
+{
+  //     Begin  End   Inc/Dec  Step  EndResult Edge
+  {      0x00,  0x1F, INC_DELAY,  4, 0xFFFF,   LEFT_EDGE},  /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS
+  { LAST_DELAY, 0x00, DEC_DELAY, -1, 0xFE00,   LEFT_EDGE},  ///  Then go back down to 0x00 by 1 until all FAIL
+  {      0x1F,  0x00, DEC_DELAY, -4, 0xFFFF,   RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS.
+  { LAST_DELAY, 0x1F, INC_DELAY,  1, 0xFE00,   RIGHT_EDGE}  ///  Then go back up by 1 until all FAIL.
+};
+/**
+ * Sweep Table For Byte Training with insertion delay
+ *
+*/
+DQS_POS_SWEEP_TABLE InsSweepTableByte[] =
+{
+  //     Begin  End   Inc/Dec  Step  EndResult Edge
+  {      0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE},  /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL
+  { LAST_DELAY, 0x1F, INC_DELAY,  1, 0xFFFF, LEFT_EDGE},  ///  Then go back up to 0x1F by 1 until all PASS
+  {      0x1F,  0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS.
+  { LAST_DELAY, 0x1F, INC_DELAY,  1, 0xFE00, RIGHT_EDGE}  ///  Then go back up by 1 until all FAIL.
+};
+
+BOOLEAN
+STATIC
+MemTTrainDQSRdWrEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+STATIC
+MemTInitTestPatternAddress (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  );
+
+BOOLEAN
+STATIC
+MemTContinueSweep (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  );
+
+BOOLEAN
+STATIC
+MemTSetNextDelay (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  );
+
+UINT8
+STATIC
+MemTScaleDelayVal (
+  IN OUT MEM_TECH_BLOCK *TechPtr,
+  IN INT8 Delay
+  );
+
+BOOLEAN
+STATIC
+MemTDataEyeSave (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr,
+  IN       UINT8 ByteLane
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function executes DQS position training for all a Memory channel using
+ *     the Edge Detection algorithm.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemTTrainDQSEdgeDetectSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  BOOLEAN Status;
+
+  Status = FALSE;
+  NBPtr = TechPtr->NBPtr;
+  TechPtr->TrainingType = TRN_DQS_POSITION;
+  //
+  // Initialize the Pattern
+  //
+  if (AGESA_SUCCESS == NBPtr->TrainingPatternInit (NBPtr)) {
+    //
+    // Setup hardware training engine (if applicable)
+    //
+    NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
+    //
+    // Start Edge Detection
+    //
+    Status |= MemTTrainDQSRdWrEdgeDetect (TechPtr);
+    //
+    // Finalize the Pattern
+    //
+    Status &= (AGESA_SUCCESS == NBPtr->TrainingPatternFinalize (NBPtr));
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This Executes Read DQS and Write Data Position training on a chip select pair
+ *  using the Edge Detection algorithm.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - No Errors occurred
+ *     @return  FALSE - Errors occurred
+
+ */
+
+BOOLEAN
+STATIC
+MemTTrainDQSRdWrEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8 WrDqDelay;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT8 i;
+  BOOLEAN Status;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+  //
+  // Set environment settings before training
+  //
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Read/Write Data Eye Edge Detection.\n");
+  MemTBeginTraining (TechPtr);
+  //
+  // Do Rd DQS /Wr Data Position training for all Dcts/Chipselects
+  //
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    //
+    // Chip Select Loop
+    //
+    TechPtr->RestartChipSel = -1;
+    for (ChipSel = 0; ChipSel < NBPtr->CsPerChannel; ChipSel = ChipSel + NBPtr->CsPerDelay ) {
+      //
+      // Init Bit Error Masks
+      //
+      LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
+        0xFF,
+        (MAX_BYTELANES_PER_CHANNEL * NBPtr->CsPerDelay),
+        &MemPtr->StdHeader);
+      if ( (NBPtr->MCTPtr->Status[SbLrdimms]) ? ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0) :
+           ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) ) {
+
+        TechPtr->ChipSel = ChipSel;
+        IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tIncrease WrDat, Train RdDqs:\n");
+
+        TechPtr->DqsRdWrPosSaved = 0;
+        //
+        // Use a list of Approximate Write Data delay values and train Read DQS Position for
+        // each until a valid Data eye is found.
+        //
+        Status = FALSE;
+        TimesFail = 0;
+        NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] (NBPtr, NBPtr);
+        ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) {
+          i = 0;
+          while (NBPtr->GetApproximateWriteDatDelay (NBPtr, i, &WrDqDelay)) {
+            TechPtr->SmallDqsPosWindow = FALSE;
+            //
+            // Set Write Delay approximation
+            //
+            TechPtr->Direction = DQS_WRITE_DIR;
+            IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrite Delay: %02x", WrDqDelay);
+            MemTSetDQSDelayAllCSR (TechPtr, WrDqDelay);
+            //
+            // Attempt Read Training
+            //
+            TechPtr->Direction = DQS_READ_DIR;
+            Status = memTrainSequenceDDR3[NBPtr->TrainingSequenceIndex].MemTechFeatBlock->RdPosTraining (TechPtr);
+            if (Status) {
+              //
+              // If Read DQS Training was successful, Train Write Data (DQ) Position
+              //
+              TechPtr->DqsRdWrPosSaved = 0;
+              IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tTrain WrDat:\n\n");
+              TechPtr->Direction = DQS_WRITE_DIR;
+              if (NBPtr->FamilySpecificHook[BeforeWrDatTrn] (NBPtr, &ChipSel)) {
+                Status = MemTTrainDQSEdgeDetect (TechPtr);
+              }
+              break;
+            }
+            i++;
+          }
+        ERROR_HANDLE_RETRAIN_END ((Status == FALSE), TimesFail)
+        }
+
+        //
+        // If we went through the table, Fail.
+        //
+        if (Status == FALSE) {
+          // On training failure, check and record whether training fails due to small window or no window
+          if (TechPtr->SmallDqsPosWindow) {
+            NBPtr->MCTPtr->ErrStatus[EsbSmallDqs] = TRUE;
+          } else {
+            NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE;
+          }
+
+          SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+          if (TechPtr->Direction == DQS_READ_DIR) {
+            PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_RD_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          } else {
+            PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_WR_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          }
+          NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ChipSel;
+          // If the even chip select failed training always fail the odd, if present.
+          if (((ChipSel & 0x01) == 0) && (NBPtr->CsPerDelay == 2)) {
+            if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << (ChipSel + 1))) {
+              NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << (ChipSel + 1);
+            }
+          }
+          if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) {
+            ASSERT (FALSE);
+          }
+        }
+      } else {
+      //
+      // Clear Bit Error Masks if these CS will not be trained.
+      //
+      LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
+        0x00,
+        (MAX_BYTELANES_PER_CHANNEL * NBPtr->CsPerDelay),
+        &NBPtr->MemPtr->StdHeader);
+      }
+    }
+  }
+  //
+  // Restore environment settings after training
+  //
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "End Read/Write Data Eye Edge Detection\n\n");
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function executes DQS position training for both read and write, using
+ *     the Edge Detection Algorithm.  This method searches for the beginning and end
+ *     of the Data Eye with out scanning every DSQ delay value. The following is a
+ *     detailed description of the algorithm:
+ *
+ *     Four-Stage Data Eye Sweep
+ *
+ *     -Search starts at Delay value of 0.
+ *     -Search left in steps of 4/32UI looking for all Byte lanes Passing. Left from zero rolls over to a negative value.
+ *     -Negative values are translated to the high end of the delay range, but using Insertion delay comparison.
+ *     -For each passing byte lane, freeze delay at first passing value, but set mask so next steps will not compare for byte lanes that previously passed
+ *     -Switch to search right in steps of 1/32UI looking for fail.
+ *     -For each lane, starting delay for 1/32 sweep right is first passing delay from 4/32 sweep left.
+ *     -For each failing byte lane, freeze delay at first failing value, but set mask so next steps will not compare for byte lanes that previously failed
+ *     -Search right until all byte lanes have failed
+ *     -For each lane, right edge used by BIOS will be first failing delay value minus 1/32
+
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+*/
+BOOLEAN
+MemTTrainDQSEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK         *NBPtr;
+  DIE_STRUCT           *MCTPtr;
+  DQS_POS_SWEEP_TABLE  *SweepTablePtr;
+  UINT8                SweepTableSize;
+  SWEEP_INFO           SweepData;
+  BOOLEAN              Status;
+  UINT16               CurrentResult;
+  UINT16               AlignedResult;
+  UINT16               OffsetResult;
+  UINT8                StageIndex;
+  UINT8                CsIndex;
+  UINT8                i;
+
+  Status = TRUE;
+  //
+  // Initialize Object Pointers
+  //
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  //
+  // Initialize stack variables
+  //
+  LibAmdMemFill (&SweepData, 0, sizeof (SWEEP_INFO), &NBPtr->MemPtr->StdHeader);
+  //
+  /// Get Pointer to Sweep Table
+  //
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    SweepTablePtr = InsSweepTableByte;
+    SweepTableSize = GET_SIZE_OF (InsSweepTableByte);
+  } else {
+    SweepTablePtr = SweepTableByte;
+    SweepTableSize = GET_SIZE_OF (SweepTableByte);
+  }
+
+  //
+  /// Set up the test Pattern, exit if no Memory
+  //
+  if (MemTInitTestPatternAddress (TechPtr, &SweepData) == FALSE) {
+    LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (TechPtr->ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
+      0,
+      (MAX_BYTELANES_PER_CHANNEL * NBPtr->CsPerDelay),
+      &NBPtr->MemPtr->StdHeader);
+    return FALSE;
+  }
+  //
+  // Clear Error Flag
+  //
+  SweepData.Error = FALSE;
+  NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] (NBPtr, NBPtr);
+  //
+  /// Process Sweep table, using entries from the table to determine Starting and Ending Delays
+  /// as well as the Step size and criteria for evaluating whether the correct result is found.
+  ///
+  /// Delay values at this level are an abstract range of values which gets scaled to the actual value
+  /// before it is written to the hardware. This allows NB specific code to handle the scaling as a
+  ///  function of frequency or other conditions.
+  //
+  for (StageIndex = 0; (StageIndex < SweepTableSize) && (SweepData.Error == FALSE); StageIndex++) {
+
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSTAGE: %d\t", StageIndex);
+    //
+    /// Initialize SweepData variables
+    //
+    SweepData.BeginDelay = SweepTablePtr->BeginDelay;
+    SweepData.EndDelay = SweepTablePtr->EndDelay;
+    SweepData.Step = 0;                                    /// Step Value will be 0 to start.
+    SweepData.EndResult = SweepTablePtr->EndResult;
+    if (!(MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining])) {
+      SweepData.EndResult |= 0x0100;
+    }
+    SweepData.Edge = SweepTablePtr->MinMax;
+    SweepData.InsertionDelayMsk = 0;
+    SweepData.ResultFound = 0x0000;
+    //
+    // Set Training Delays Pointer.
+    //
+    if (TechPtr->Direction == DQS_READ_DIR) {
+      SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->RdDqsMaxDlys : NBPtr->ChannelPtr->RdDqsMinDlys);
+    } else {
+      SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->WrDatMaxDlys : NBPtr->ChannelPtr->WrDatMinDlys);
+    };
+    //
+    /// Set initial TrnDelay Values if necessary
+    //
+    IDS_HDT_CONSOLE (MEM_FLOW, "Sweeping %s DQS, %s from ", (TechPtr->Direction == DQS_READ_DIR) ?"Read":"Write", (SweepTablePtr->ScanDir == INC_DELAY) ? "incrementing":"decrementing");
+    if (SweepData.BeginDelay != LAST_DELAY) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "%02x", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.BeginDelay));
+      for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); i++) {
+        SweepData.TrnDelays[i] = SweepData.BeginDelay;
+      }
+    } else {
+      IDS_HDT_CONSOLE (MEM_FLOW, "Current Delay");
+      SweepData.Step = SweepTablePtr->Step;
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, " by %02x, until all bytelanes %s.\n\n", (UINT16) MemTScaleDelayVal (TechPtr, ABS (SweepTablePtr->Step)), (SweepData.EndResult == 0xFFFF)?"PASS":"FAIL");
+
+    //-------------------------------------------------------------------
+    //   Sweep DQS Delays
+    //   MemTContinueSweep function returns false to break out of loop.
+    //   There are no other breaks out of this loop.
+    //-------------------------------------------------------------------
+    while (MemTContinueSweep (TechPtr, &SweepData)) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane    : 08 07 06 05 04 03 02 01 00\n");
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDQS Delays   : %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[8]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0])
+       );
+      //
+      /// Set Step Value
+      //
+      SweepData.Step = SweepTablePtr->Step;
+      CurrentResult = 0xFFFF;
+      //
+      /// Chip Select Loop: Test the Pattern for all populated CS that are controlled by the current delay registers
+      //
+      for (CsIndex = 0; CsIndex < NBPtr->CsPerDelay ; CsIndex++, TechPtr->ChipSel++) {
+        ASSERT (CsIndex < MAX_CS_PER_CHANNEL);
+        ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL);
+        if (SweepData.CsAddrValid[CsIndex] == TRUE) {
+          //
+          /// If this is a Write Dqs sweep, Write the pattern now.
+          //
+          if (TechPtr->Direction == DQS_WRITE_DIR) {
+            NBPtr->WritePattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength);
+          }
+          //
+          /// Read the Pattern Back
+          //
+          NBPtr->ReadPattern (NBPtr, TechPtr->TestBufPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength);
+          //
+          /// Compare the Pattern and Merge the results using InsertionDelayMsk
+          //
+          AlignedResult = NBPtr->CompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
+          CurrentResult &= AlignedResult | SweepData.InsertionDelayMsk;
+          if (SweepData.InsertionDelayMsk != 0) {
+            OffsetResult = NBPtr->InsDlyCompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
+            CurrentResult &= (OffsetResult | (~SweepData.InsertionDelayMsk));
+          }
+          //
+          /// Flush the Test Pattern
+          //
+          NBPtr->FlushPattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength);
+          NBPtr->FamilySpecificHook[ResetRxFifoPtr] (NBPtr, NBPtr);
+        }
+      } /// End Chip Select Loop
+      TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult       :  %c  %c  %c  %c  %c  %c  %c  %c  %c \n",
+        (SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (4))) ? ' ':(CurrentResult & ((UINT16) 1 << (4))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (3))) ? ' ':(CurrentResult & ((UINT16) 1 << (3))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.'
+        );
+      //
+      /// Merge current result into cumulative result and make it positive.
+      //
+      SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult);
+
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResultFound  :  %c  %c  %c  %c  %c  %c  %c  %c  %c \n\n",
+        (SweepData.ResultFound & ((UINT16) 1 << (8))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (6))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (5))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (4))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (3))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' '
+        );
+    } /// End of Delay Sweep
+    //
+    /// Place Final delay values at last passing delay.
+    //
+    if (SweepData.ResultFound == 0xFFFF) {
+      if ( ABS (SweepData.Step) == 1) {
+        for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
+          if ((SweepData.EndResult & ((UINT16) (1 << i))) == 0) {
+            SweepData.TrnDelays[i] = SweepData.TrnDelays[i] - SweepData.Step;
+          }
+        }
+      }
+    }
+    //
+    // Update Pointer to Sweep Table
+    //
+    SweepTablePtr++;
+  }///End of Edge Detect loop
+  //
+  /// If No Errors are detected, Calculate Data Eye Width and Center
+  //
+  if (SweepData.Error == FALSE) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tData Eye Results:\n\n");
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tByte     Left     Right\n");
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLane     Edge     Edge     Width     Center\n");
+    for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %0d", i);
+      TechPtr->Bytelane = i;
+      if (!MemTDataEyeSave (TechPtr, &SweepData, i)) {
+        break;
+      }
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+      if (SweepData.Error == TRUE) {
+        Status = FALSE;
+      }
+    }
+  } else {
+    Status = FALSE;
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t--DATA EYE NOT FOUND--\n\n");
+    NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] (NBPtr, &SweepData);
+  }
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     Initialize the Test Pattern Address for two chip selects and, if this
+ *     is a Write Data Eye, write the initial test pattern.
+ *
+ *     Test Address is stored in the Sweep info struct.  If Memory is not present
+ *     then return with False.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *
+ *     @return  BOOLEAN
+ *              TRUE  - Memory is present
+ *              FALSE - No memory present on this Chip Select pair.
+ *
+**
+ */
+BOOLEAN
+STATIC
+MemTInitTestPatternAddress (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8 ChipSel;
+  UINT8 CsIndex;
+  BOOLEAN BanksPresent;
+
+  NBPtr = TechPtr->NBPtr;
+  BanksPresent = FALSE;
+  ChipSel = TechPtr->ChipSel;
+  for (CsIndex = 0; CsIndex < NBPtr->CsPerDelay; ChipSel++, CsIndex++, TechPtr->ChipSel++) {
+    ASSERT (CsIndex < MAX_CS_PER_CHANNEL);
+    ASSERT (ChipSel < MAX_CS_PER_CHANNEL);
+    ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL);
+    //
+    /// If memory is present on this cs, get the test addr
+    //
+    if (NBPtr->GetSysAddr (NBPtr, ChipSel, &(SweepPtr->TestAddrRJ16[CsIndex]))) {
+      if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) {
+        BanksPresent = TRUE;
+        SweepPtr->CsAddrValid[CsIndex] = TRUE;
+        //
+        /// If this is a Read Dqs sweep, Write the pattern now.
+        //
+        if (TechPtr->Direction == DQS_READ_DIR) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "\tTestAddr: %x0000\n", SweepPtr->TestAddrRJ16[CsIndex]);
+          NBPtr->WritePattern (NBPtr, SweepPtr->TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength);
+        }
+      }
+    } else {
+      SweepPtr->CsAddrValid[CsIndex] = FALSE;
+    }
+  } /// End Chip Select Loop
+  TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
+  //
+  /// return FALSE if no ChipSelects present.
+  //
+  return BanksPresent;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *     Test Conditions for exiting the training loop, set the next delay value,
+ *     and return status
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *
+ *     @return  BOOLEAN
+ *              TRUE  - Continue to test with next delay setting
+ *              FALSE - Exit training loop.  Either the result has been found or
+ *                      end of delay range has been reached.
+*/
+BOOLEAN
+STATIC
+MemTContinueSweep (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  )
+{
+  BOOLEAN Status;
+  Status = FALSE;
+  if (SweepPtr->ResultFound != 0xFFFF) {
+    Status = MemTSetNextDelay (TechPtr, SweepPtr);
+  }
+  TechPtr->NBPtr->FamilySpecificHook[RegAccessFence] (TechPtr->NBPtr, NULL);
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the next delay value for each bytelane that needs to
+ *      be advanced.  It checks the bounds of the delay to see if we are at the
+ *      end of the range.  If we are to close to advance a whole step value, but
+ *      not at the boundary, then we set the delay to the boundary.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemTSetNextDelay (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  )
+{
+  DIE_STRUCT           *MCTPtr;
+  UINT8 i;
+
+  MCTPtr =  TechPtr->NBPtr->MCTPtr;
+  //
+  ///< Loop through bytelanes
+  //
+  for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
+    //
+    /// Skip Bytelanes that have already reached the desired result
+    //
+    if ( (SweepPtr->ResultFound  & ((UINT16)1 << i)) == 0) {
+      //
+      /// If a bytelane has reached the end, flag an error and exit
+      //
+      if (SweepPtr->TrnDelays[i] == SweepPtr->EndDelay) {
+        if ((SweepPtr->EndResult & ((UINT16) (1 << i))) != 0) {
+          MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE;
+          SweepPtr->Error = TRUE;
+        }
+        return FALSE;
+      }
+      //
+      /// If the Current delay value is less than a step away from EndDelay,
+      //
+      if ( ABS (SweepPtr->EndDelay - SweepPtr->TrnDelays[i]) < ABS (SweepPtr->Step)) {
+        /// set to EndDelay.
+        //
+        SweepPtr->TrnDelays[i] = SweepPtr->EndDelay;
+      } else {
+        //
+        /// Otherwise, add the step value to it
+        SweepPtr->TrnDelays[i] = SweepPtr->TrnDelays[i] + SweepPtr->Step;
+      }
+      //
+      /// Set InsertionDelayMsk bit if Delay < 0 for this bytelane
+      //
+      if (SweepPtr->TrnDelays[i] < 0) {
+        SweepPtr->InsertionDelayMsk |= ((UINT16) 1 << i);
+      } else {
+        SweepPtr->InsertionDelayMsk &= ~((UINT16) 1 << i);
+      }
+      //
+      /// Write the scaled value to the Delay Register
+      //
+      TechPtr->SetDQSDelayCSR (TechPtr, i, MemTScaleDelayVal (TechPtr, SweepPtr->TrnDelays[i]));
+    }
+  }
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function accepts a delay value in 32nd of a UI and converts it to an
+ *     actual register value, taking into consideration NB type, rd/wr,
+ *     and frequency.
+ *
+ *     Delay = (Min + (Delay * ( (Max - Min) / TRN_DELAY_MAX) )) & Mask
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       *Delay     - INT8 of delay value;
+ *
+ *     @return  UINT8 of the adjusted delay value
+*/
+UINT8
+STATIC
+MemTScaleDelayVal (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       INT8 Delay
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  TRN_DLY_PARMS Parms;
+  TRN_DLY_TYPE DelayType;
+  UINT8 NewDelay;
+  INT8 Factor;
+  INT8 ScaledDelay;
+
+  NBPtr = TechPtr->NBPtr;
+  //
+  // Determine Delay Type, Get Delay Parameters, and return scaled Delay value
+  //
+  DelayType = (TechPtr->Direction == DQS_WRITE_DIR) ? AccessWrDatDly : AccessRdDqsDly;
+  NBPtr->GetTrainDlyParms (NBPtr, DelayType, &Parms);
+  Factor = ((Parms.Max - Parms.Min) / TRN_DELAY_MAX);
+  ScaledDelay = Delay * Factor;
+  NewDelay = (Parms.Min + ScaledDelay) & Parms.Mask;
+  return NewDelay;
+}
+
+
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function calculates the Center of the Data eye for the specified byte lane
+ *       and stores its DQS Delay value for reference.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *     @param[in]       ByteLane  -  Bytelane number being targeted
+ *
+ */
+BOOLEAN
+STATIC
+MemTDataEyeSave (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr,
+  IN       UINT8 ByteLane
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 EyeCenter;
+  UINT8 DlyMin;
+  UINT8 DlyMax;
+  UINT8 EyeWidth;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChanPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChanPtr = NBPtr->ChannelPtr;
+
+  ASSERT (ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8));
+  //
+  // Calculate Data Eye edges, Width, and Center in real terms.
+  //
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMinDlys[ByteLane]);
+    DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMaxDlys[ByteLane]);
+    EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->RdDqsMaxDlys[ByteLane] - ChanPtr->RdDqsMinDlys[ByteLane]));
+    EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->RdDqsMinDlys[ByteLane] + ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2));
+    if (!NBPtr->FamilySpecificHook[RdDqsDlyRestartChk] (NBPtr, &EyeCenter)) {
+      return FALSE;
+    }
+    ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin;
+    ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax;
+    NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] (NBPtr, &EyeCenter);
+  } else {
+    DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMinDlys[ByteLane]);
+    DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMaxDlys[ByteLane]);
+    EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->WrDatMaxDlys[ByteLane] - ChanPtr->WrDatMinDlys[ByteLane]));
+    EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->WrDatMinDlys[ByteLane] + ChanPtr->WrDatMaxDlys[ByteLane] + 1) / 2));
+    ChanPtr->WrDatMinDlys[ByteLane] = DlyMin;
+    ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax;
+  }
+  //
+  // Flag error for small window.
+  //
+  if (EyeWidth < MemTScaleDelayVal (TechPtr, NBPtr->MinDataEyeWidth (NBPtr))) {
+    TechPtr->SmallDqsPosWindow = TRUE;
+    SweepPtr->Error = TRUE;
+    NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] (NBPtr, NULL);
+  }
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "        %02x       %02x       %02x         %02x", DlyMin, DlyMax, EyeWidth, EyeCenter);
+
+  TechPtr->SetDQSDelayCSR (TechPtr, ByteLane, EyeCenter);
+  if (!SweepPtr->Error) {
+    TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane;
+  }
+  TechPtr->DqsRdWrPosSaved |= 0xFE00;
+
+  Dimm = (TechPtr->ChipSel / NBPtr->CsPerDelay) * TechPtr->DlyTableWidth () + ByteLane;
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    ChanPtr->RdDqsDlys[Dimm] = EyeCenter;
+  } else {
+    ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm];
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h
new file mode 100644
index 0000000000..079534e68a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h
@@ -0,0 +1,144 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttEdgeDetect.h
+ *
+ * Technology Common Training Header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTTEDGEDETECT_H_
+#define _MTTEDGEDETECT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+#define SCAN_LEFT       0            ///<  Scan Down
+#define SCAN_RIGHT      1            ///<  Scan Up
+#define LEFT_EDGE       0            ///<  searching for the left edge
+#define RIGHT_EDGE      1            ///<  searching for the right edge
+
+#define SweepStages     4
+#define TRN_DELAY_MAX   31           ///<  Max Virtual delay value for DQS Position Training
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ *  Sweep Table Structure. ROM based table defining parameters for DQS position
+ *  training delay sweep.
+*/
+typedef struct {
+  INT8    BeginDelay;          ///<  Starting Delay Value
+  INT8    EndDelay;            ///<  Ending Delay Value
+  BOOLEAN ScanDir;             ///<  Scan Direction.  0 = down, 1 = up
+  INT8    Step;                ///<  Amount to increment delay value
+  UINT16  EndResult;           ///<  Result value to stop sweeping (to compare with failure mask)
+  BOOLEAN MinMax;              ///<  Flag indicating lower (left edge) or higher(right edge)
+} DQS_POS_SWEEP_TABLE;
+
+/**
+ * Sweep Information Struct - Used to track data through the DQS Delay Sweep
+ *
+*/
+typedef struct _SWEEP_INFO {
+  BOOLEAN Error;                               ///< Indicates an Error has been found
+  UINT32  TestAddrRJ16[MAX_CS_PER_CHANNEL];    ///< System address of chipselects RJ 16 bits (Addr[47:16])
+  BOOLEAN CsAddrValid[MAX_CS_PER_CHANNEL];     ///< Indicates which chipselects to test
+  INT8    BeginDelay;                          ///< Beginning Delay value (Virtual)
+  INT8    EndDelay;                            ///< Ending Delay value (Virtual)
+  INT8    Step;                                ///< Amount to Inc or Dec Virtual Delay value
+  BOOLEAN Edge;                                ///< Left or right edge (0 = LEFT, 1= RIGHT)
+  UINT16  EndResult;                           ///< Result value that will stop a Dqs Sweep
+  UINT16  InsertionDelayMsk;                   ///< Mask of Byte Lanes that should use ins. dly. comparison
+  UINT16  LaneMsk;                             ///< Mask indicating byte lanes to update
+  UINT16  ResultFound;                         ///< Mask indicating byte lanes where desired result was found on a sweep
+  INT8    *TrnDelays;                          ///< Delay Values for each byte (Virtual).  Points into the delay values
+} SWEEP_INFO;                                  ///< stored in the CH_DEF_STRUCT.
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#endif  /* _MTTEDGEDETECT_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c
new file mode 100644
index 0000000000..447be6bed1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c
@@ -0,0 +1,1510 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttdimmbt.c
+ *
+ * Technology Dimm Based Training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTDIMBT_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTInitDqsPos4RcvrEnByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+STATIC
+MemTSetRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  );
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+BOOLEAN
+STATIC
+MemTSaveRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  );
+
+VOID
+STATIC
+MemTResetDctWrPtrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+UINT16
+STATIC
+MemTCompare1ClPatternByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[]
+  );
+
+VOID
+STATIC
+MemTSkipChipSelPass1Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  );
+
+VOID
+STATIC
+MemTSkipChipSelPass2Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  );
+
+UINT8
+STATIC
+MemTMaxByteLanesByte ( VOID );
+
+UINT8
+STATIC
+MemTDlyTableWidthByte ( VOID );
+
+VOID
+STATIC
+MemTSetDqsDelayCsrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 Dly
+  );
+
+VOID
+STATIC
+MemTDqsWindowSaveByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 DlyMin,
+  IN       UINT8 DlyMax
+  );
+
+BOOLEAN
+STATIC
+MemTFindMaxRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  );
+
+UINT16
+STATIC
+MemTCompare1ClPatternOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT8 Side,
+  IN       UINT8 Receiver,
+  IN       BOOLEAN Side1En
+  );
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+VOID
+STATIC
+MemTSetRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  );
+
+VOID
+STATIC
+MemTLoadInitialRcvEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+UINT8
+STATIC
+MemTFindMinMaxGrossDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       TRN_DLY_TYPE TrnDlyType,
+  IN       BOOLEAN IfMax
+  );
+
+BOOLEAN
+exce856  (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function enables byte based training if called
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTDimmByteTrainInit (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 DctCount;
+  UINT8 ChannelCount;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  ASSERT ((NBPtr->CsPerDelay == 1) || (NBPtr->CsPerDelay == 2));
+
+  TechPtr->InitDQSPos4RcvrEn = MemTInitDqsPos4RcvrEnByte;
+  TechPtr->SetRcvrEnDly = MemTSetRcvrEnDlyByte;
+  TechPtr->LoadRcvrEnDly = MemTLoadRcvrEnDlyByte;
+  TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByte;
+  TechPtr->SaveRcvrEnDlyFilter = MemTSaveRcvrEnDlyByteFilterOpt;
+  TechPtr->ResetDCTWrPtr = MemTResetDctWrPtrByte;
+  TechPtr->Compare1ClPattern = MemTCompare1ClPatternByte;
+  TechPtr->SkipChipSelPass1 = MemTSkipChipSelPass1Byte;
+  TechPtr->SkipChipSelPass2 = MemTSkipChipSelPass2Byte;
+  TechPtr->MaxByteLanes = MemTMaxByteLanesByte;
+  TechPtr->DlyTableWidth = MemTDlyTableWidthByte;
+  TechPtr->SetDQSDelayCSR = MemTSetDqsDelayCsrByte;
+  TechPtr->DQSWindowSave = MemTDqsWindowSaveByte;
+  TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyByte;
+  TechPtr->Compare1ClPatternOpt = MemTCompare1ClPatternOptByte;
+  TechPtr->LoadRcvrEnDlyOpt = MemTLoadRcvrEnDlyOptByte;
+  TechPtr->SetRcvrEnDlyOpt = MemTSetRcvrEnDlyOptByte;
+  TechPtr->InitializeVariablesOpt = MemTInitializeVariablesOptByte;
+  TechPtr->GetMaxValueOpt = MemTGetMaxValueOptByte;
+  TechPtr->SetSweepErrorOpt = MemTSetSweepErrorOptByte;
+  TechPtr->CheckRcvrEnDlyLimitOpt = MemTCheckRcvrEnDlyLimitOptByte;
+  TechPtr->LoadInitialRcvrEnDlyOpt = MemTLoadInitialRcvEnDlyOptByte;
+  TechPtr->GetMinMaxGrossDly = MemTFindMinMaxGrossDlyByte;
+  // Dynamically allocate buffers for storing trained timings.
+  DctCount = MCTPtr->DctCount;
+  ChannelCount = MCTPtr->DctData[0].ChannelCount;
+  AllocHeapParams.RequestedBufferSize = ((DctCount * ChannelCount) *
+                                         ((MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES) +
+                                          (MAX_DELAYS * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
+                                           (MAX_DIMMS * MAX_NUMBER_LANES)
+                                          )
+                                         );
+
+  if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) {
+    AllocHeapParams.RequestedBufferSize *= 2;
+  }
+
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, MCTPtr->NodeId, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader) == AGESA_SUCCESS) {
+    for (Dct = 0; Dct < DctCount; Dct++) {
+      for (Channel = 0; Channel < ChannelCount; Channel++) {
+        MCTPtr->DctData[Dct].ChData[Channel].RowCount = MAX_DIMMS;
+        MCTPtr->DctData[Dct].ChData[Channel].ColumnCount = MAX_DELAYS;
+
+        MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+        MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_NUMBER_LANES);
+        MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS);
+        if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) {
+          MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlysMemPs1 = (UINT16 *) AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_NUMBER_LANES);
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlysMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+          MCTPtr->DctData[Dct].ChData[Channel].FailingBitMaskMemPs1 = AllocHeapParams.BufferPtr;
+          AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS);
+
+        }
+      }
+    }
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE);  // Could not dynamically allocate buffers for storing trained timings
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function initializes the DQS Positions in preparation for Receiver Enable Training.
+ *  Write Position is no delay, Read Position is 1/2 Memclock delay
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemTInitDqsPos4RcvrEnByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dimm;
+  UINT8 ByteLane;
+  UINT8 WrDqs;
+
+  for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+    for (ByteLane = 0; ByteLane < MAX_DELAYS; ByteLane++) {
+      WrDqs = TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane];
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs);
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), 0x3F);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ */
+
+VOID
+STATIC
+MemTSetRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  )
+{
+  UINT8 ByteLane;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function loads the DqsRcvEnDly from saved data and program to additional index
+ *  for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *
+ */
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT8 Dimm;
+  UINT16 Saved;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Dimm = Receiver >> 1;
+  Saved = TechPtr->DqsRcvEnSaved;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if (Saved & 1) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
+      ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]);
+    }
+    Saved >>= 1;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function saves passing DqsRcvEnDly values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       CmpResultRank0 - compare result for Rank 0
+ *     @param[in]       CmpResultRank1 - compare result for Rank 1
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+ */
+
+BOOLEAN
+STATIC
+MemTSaveRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Saved;
+  UINT8 Mask;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
+
+  Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@attention - false passes filter (subject to be replaced with a better solution)
+  Dimm = Receiver >> 1;
+  Mask = 1;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if (Passed & Mask) {
+      if (!(Saved & Mask)) {
+        ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20;     // @attention -1 pass only
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
+      }
+      Saved |= Mask;
+    }
+    Mask <<= 1;
+  }
+  TechPtr->DqsRcvEnSaved = Saved;
+
+  if (Saved == 0xFF) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function performs a filtering functionality and saves passing DqsRcvEnDly
+ *  values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       CmpResultRank0 - compare result for Rank 0
+ *     @param[in]       CmpResultRank1 - compare result for Rank 1
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+ */
+
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilter (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Saved;
+  UINT8 Mask;
+  UINT8 Dimm;
+  UINT8 MaxFilterDly;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_DCT_CACHE *DctCachePtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  DctCachePtr = TechPtr->NBPtr->DctCachePtr;
+
+  MaxFilterDly = TechPtr->MaxFilterDly;
+  Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
+
+  Dimm = Receiver >> 1;
+  Saved = (UINT8) TechPtr->DqsRcvEnSaved;
+  Mask = 1;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if ((Passed & Mask) != 0) {
+      DctCachePtr->RcvEnDlyCounts [i] += 1;
+      if ((Saved & Mask) == 0) {
+        ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20;
+        Saved |= Mask;
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
+      }
+    } else {
+      if (DctCachePtr->RcvEnDlyCounts [i] <= MaxFilterDly) {
+        DctCachePtr->RcvEnDlyCounts [i] = 0;
+        Saved &= ~Mask;
+      }
+    }
+    Mask <<= 1;
+  }
+
+  //-----------------------
+  TechPtr->DqsRcvEnSaved = (UINT16) Saved;
+
+  Saved = 0;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if (DctCachePtr->RcvEnDlyCounts [i] >= MaxFilterDly) {
+      Saved |= (UINT8) 1 << i;
+    }
+  }
+
+  if (Saved == 0xFF) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and return a pass/fail bitmap
+ *       for 8 Bytes
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *
+ *     @return  PASS - Bit map of results of comparison
+ */
+
+UINT16
+STATIC
+MemTCompare1ClPatternByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[]
+  )
+{
+  UINT16 i;
+  UINT16 j;
+  UINT16 Pass;
+  DIE_STRUCT *MCTPtr;
+
+  MCTPtr = TechPtr->NBPtr->MCTPtr;
+  if (MCTPtr->GangedMode && MCTPtr->Dct) {
+    j = 8;
+  } else {
+    j = 0;
+  }
+
+  Pass = 0xFFFF;
+  IDS_HDT_CONSOLE (MEM_FLOW, " -");
+  for (i = 0; i < 8; i++) {
+    if (Buffer[j] != Pattern[j]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (j % 8));    // clear bit n
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "  %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
+    j++;
+  }
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t        -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t        -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+  );
+
+  return Pass;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       The function resets the DCT input buffer write pointer.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver - Chip select
+ *
+ */
+
+VOID
+STATIC
+MemTResetDctWrPtrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT16 RcvEnDly;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    RcvEnDly = (UINT16) TechPtr->NBPtr->GetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i));
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i), RcvEnDly);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function skips odd chip select if training at 800MT or above.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       *ChipSelPtr - Pointer to variable contains Chip select index
+ *
+ */
+
+VOID
+STATIC
+MemTSkipChipSelPass1Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  // if the even chip select failed training, need to set CsTrainFail for odd chip select if present.
+  if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ((*ChipSelPtr) + 1))) {
+    if (NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << *ChipSelPtr)) {
+      NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((*ChipSelPtr) + 1);
+      if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+      }
+    }
+  }
+  (*ChipSelPtr)++;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  MemTSkipChipSelPass2Byte:
+ *
+ *       This function skips odd chip select if training at 800MT or above.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *ChipSelPtr - Pointer to variable contains Chip select index
+ *
+ */
+
+VOID
+STATIC
+MemTSkipChipSelPass2Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  )
+{
+  if (*ChipSelPtr & 1) {
+    *ChipSelPtr = MAX_CS_PER_CHANNEL;    // skip all successions
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function determines the maximum number of byte lanes
+ *
+ *     @return  Max number of Bytelanes
+ */
+
+UINT8
+STATIC
+MemTMaxByteLanesByte ( VOID )
+{
+  return MAX_BYTELANES;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
+ *
+ *     @return  Delay table width in bytes
+ */
+
+UINT8
+STATIC
+MemTDlyTableWidthByte ( VOID )
+{
+  return MAX_DELAYS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function writes the Delay value to a certain byte lane
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       ByteLane  -  Bytelane number being targeted
+ *     @param[in]       Dly - Delay value
+ *
+ */
+
+VOID
+STATIC
+MemTSetDqsDelayCsrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 Dly
+  )
+{
+  UINT8 Reg;
+  UINT8 Dimm;
+
+  ASSERT (ByteLane <= MAX_BYTELANES);
+
+  if (!(TechPtr->DqsRdWrPosSaved & ((UINT8)1 << ByteLane))) {
+    Dimm = TechPtr->ChipSel / TechPtr->NBPtr->CsPerDelay;
+
+    if (TechPtr->Direction == DQS_WRITE_DIR) {
+      Dly = Dly + ((UINT8) TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]);
+      Reg = AccessWrDatDly;
+    } else {
+      Reg = AccessRdDqsDly;
+    }
+
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, Reg, DIMM_BYTE_ACCESS (Dimm, ByteLane), Dly);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function programs the trained DQS delay for the specified byte lane
+ *       and stores its DQS window for reference.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       ByteLane  -  Bytelane number being targeted
+ *     @param[in]       DlyMin - Minimum delay value
+ *     @param[in]       DlyMax- Maximum delay value
+ *
+ */
+
+VOID
+STATIC
+MemTDqsWindowSaveByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 DlyMin,
+  IN       UINT8 DlyMax
+  )
+{
+  UINT8 DqsDelay;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChanPtr;
+
+  ASSERT (ByteLane <= MAX_BYTELANES);
+  ChanPtr = TechPtr->NBPtr->ChannelPtr;
+
+  DqsDelay = ((DlyMin + DlyMax + 1) / 2) & 0x3F;
+  MemTSetDqsDelayCsrByte (TechPtr, ByteLane, DqsDelay);
+  TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane;
+  TechPtr->DqsRdWrPosSaved |= 0xFF00;
+
+  Dimm = (TechPtr->ChipSel / TechPtr->NBPtr->CsPerDelay) * MAX_DELAYS + ByteLane;
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    ChanPtr->RdDqsDlys[Dimm] = DqsDelay;
+  } else {
+    ChanPtr->WrDatDlys[Dimm] = DqsDelay + ChanPtr->WrDqsDlys[Dimm];
+  }
+
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin;
+    ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax;
+  } else {
+    ChanPtr->WrDatMinDlys[ByteLane] = DlyMin;
+    ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax;
+  }
+
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function finds the DIMM that has the largest receiver enable delay.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[out]      *ChipSel   - Pointer to the Chip select that has the largest receiver enable delay.
+ *
+ *     @return   TRUE - A chip select can be found.
+ *     @return   FALSE - A chip select cannot be found.
+ */
+
+BOOLEAN
+STATIC
+MemTFindMaxRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  )
+{
+  UINT8  ChipSelect;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 MaxDly;
+  UINT8  MaxDlyCs;
+  BOOLEAN RetVal;
+
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  RetVal = FALSE;
+  MaxDly = 0;
+  MaxDlyCs = 0;
+  for (ChipSelect = 0; ChipSelect < NBPtr->CsPerChannel; ChipSelect = ChipSelect + NBPtr->CsPerDelay) {
+    if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSelect)) != 0) {
+      if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSelect)) == 0) {
+        // Only choose the dimm that does not fail training
+        for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
+          RcvEnDly = ChannelPtr->RcvEnDlys[ChipSelect / NBPtr->CsPerDelay * MAX_DELAYS + ByteLane];
+          if (RcvEnDly > MaxDly) {
+            MaxDly = RcvEnDly;
+            MaxDlyCs = ChipSelect;
+            RetVal = TRUE;
+          }
+        }
+      }
+    }
+  }
+
+  if (NBPtr->MCTPtr->Status[Sb128bitmode] != 0) {
+    //The RcvrEnDlys of DCT1 DIMMs should also be considered while ganging.
+    NBPtr->SwitchDCT (NBPtr, 1);
+    ChannelPtr = NBPtr->ChannelPtr;
+    for (ChipSelect = 0; ChipSelect < NBPtr->CsPerChannel; ChipSelect = ChipSelect + NBPtr->CsPerDelay) {
+      for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
+        RcvEnDly = ChannelPtr->RcvEnDlys[ChipSelect / NBPtr->CsPerDelay * MAX_DELAYS + ByteLane];
+        if (RcvEnDly > MaxDly) {
+          MaxDly = RcvEnDly;
+          MaxDlyCs = ChipSelect;
+        }
+      }
+    }
+    NBPtr->SwitchDCT (NBPtr, 0);
+  }
+
+  TechPtr->MaxDlyForMaxRdLat = MaxDly;
+  *ChipSel = MaxDlyCs;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[out]      *ChipSel   - Pointer to the Chip select that has the largest receiver enable delay
+ *                                   + Read DQS Delay.
+ *
+ *     @return   TRUE - A chip select can be found.
+ *     @return   FALSE - A chip select cannot be found.
+ */
+
+BOOLEAN
+MemTFindMaxRcvrEnDlyRdDqsDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  )
+{
+  UINT8  ChipSelect;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 RdDqsDly;
+  UINT16 TotalDly;
+  UINT16 MaxDly;
+  UINT8  MaxDlyCs;
+  BOOLEAN RetVal;
+
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  RetVal = FALSE;
+  MaxDly = 0;
+  MaxDlyCs = 0;
+  for (ChipSelect = 0; ChipSelect < NBPtr->CsPerChannel; ChipSelect = ChipSelect + NBPtr->CsPerDelay) {
+    if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSelect)) == 0) {
+      // Only choose the dimm that does not fail training
+      for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+        RcvEnDly = ChannelPtr->RcvEnDlys[ChipSelect / NBPtr->CsPerDelay * MAX_DELAYS + ByteLane];
+        // Before Dqs Position Training, this value is 0. So the maximum value for
+        // RdDqsDly needs to be added later when calculating the MaxRdLatency value
+        // after RcvEnDly training but before DQS Position Training.
+        RdDqsDly = ChannelPtr->RdDqsDlys[ChipSelect / NBPtr->CsPerDelay * MAX_DELAYS + ByteLane];
+        TotalDly = RcvEnDly + (RdDqsDly >> 1);
+        if (TotalDly > MaxDly) {
+          MaxDly = TotalDly;
+          MaxDlyCs = ChipSelect;
+          RetVal = TRUE;
+        }
+      }
+    }
+  }
+
+  TechPtr->MaxDlyForMaxRdLat = MaxDly;
+  *ChipSel = MaxDlyCs;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay for UNB
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[out]      *ChipSel   - Pointer to the Chip select that has the largest receiver enable delay
+ *                                   + Read DQS Delay.
+ *
+ *     @return   TRUE - A chip select can be found.
+ *     @return   FALSE - A chip select cannot be found.
+ */
+
+BOOLEAN
+MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  )
+{
+  UINT8  ChipSelect;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 RdDqsDly;
+  UINT16 TotalDly;
+  UINT16 MaxDly;
+  UINT8  MaxDlyCs;
+  BOOLEAN RetVal;
+  UINT16 *RcvEnDlyPtr;
+  UINT8 *RdDqsDlyPtr;
+
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+  RcvEnDlyPtr = ChannelPtr->RcvEnDlys;
+  RdDqsDlyPtr = ChannelPtr->RdDqsDlys;
+  if (NBPtr->MemPstate == MEMORY_PSTATE1) {
+    RcvEnDlyPtr = ChannelPtr->RcvEnDlysMemPs1;
+    RdDqsDlyPtr = ChannelPtr->RdDqsDlysMemPs1;
+  }
+
+  RetVal = FALSE;
+  MaxDly = 0;
+  MaxDlyCs = 0;
+  for (ChipSelect = 0; ChipSelect < NBPtr->CsPerChannel; ChipSelect = ChipSelect + NBPtr->CsPerDelay) {
+    if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSelect)) == 0) {
+      // Only choose the dimm that does not fail training
+      for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+        RcvEnDly = RcvEnDlyPtr[ChipSelect / NBPtr->CsPerDelay * MAX_DELAYS + ByteLane];
+        // Before Dqs Position Training, this value is 0. So the maximum value for
+        // RdDqsDly needs to be added later when calculating the MaxRdLatency value
+        // after RcvEnDly training but before DQS Position Training.
+        RdDqsDly = RdDqsDlyPtr[ChipSelect / NBPtr->CsPerDelay * MAX_DELAYS + ByteLane];
+        TotalDly = RcvEnDly + RdDqsDly;
+        if (TotalDly > MaxDly) {
+          MaxDly = TotalDly;
+          MaxDlyCs = ChipSelect;
+          RetVal = TRUE;
+        }
+      }
+    }
+  }
+
+  TechPtr->MaxDlyForMaxRdLat = MaxDly;
+  *ChipSel = MaxDlyCs;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function finds the minimum or maximum gross dly among all the bytes.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       TrnDlyType - Target Dly type
+ *     @param[in]       IfMax - If this is for maximum value or minimum
+ *
+ *     @return   minimum gross dly
+ */
+UINT8
+STATIC
+MemTFindMinMaxGrossDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       TRN_DLY_TYPE TrnDlyType,
+  IN       BOOLEAN IfMax
+  )
+{
+  UINT8 ChipSelect;
+  UINT8 ByteLane;
+  UINT16 CsEnabled;
+  UINT8 MinMaxGrossDly;
+  UINT8 TrnDly;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+  MinMaxGrossDly = IfMax ? 0 : 0xFF;
+
+  for (ChipSelect = 0; ChipSelect < NBPtr->CsPerChannel; ChipSelect = ChipSelect + NBPtr->CsPerDelay) {
+    if ((CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSelect)) != 0) {
+      for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
+        TrnDly = (UINT8) (GetTrainDlyFromHeapNb (NBPtr, TrnDlyType, DIMM_BYTE_ACCESS (ChipSelect / NBPtr->CsPerDelay, ByteLane)) >> 5);
+        if ((IfMax && (TrnDly > MinMaxGrossDly)) || (!IfMax && (TrnDly < MinMaxGrossDly))) {
+          MinMaxGrossDly = TrnDly;
+        }
+      }
+    }
+  }
+
+  return MinMaxGrossDly;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and return a pass/fail bitmap
+ *       for 8 Bytes for optimized receiver enable training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       Side - current side being targeted
+ *     @param[in]       Receiver - Current receiver value
+ *     @param[in]       Side1En - Indicates if the second side of the DIMM is being used
+ *     @return  PASS - Bit map of results of comparison
+ */
+
+UINT16
+STATIC
+MemTCompare1ClPatternOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT8 Side,
+  IN       UINT8 Receiver,
+  IN       BOOLEAN  Side1En
+  )
+{
+  UINT16 i;
+  UINT16 j;
+  UINT16 Pass;
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  MCTPtr = TechPtr->NBPtr->MCTPtr;
+
+  if (MCTPtr->GangedMode && MCTPtr->Dct) {
+    j = 8;
+  } else {
+    j = 0;
+  }
+
+  Pass = 0xFFFF;
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDelay[BL] -");
+  for (i = 0; i < 8; i++) {
+    IDS_HDT_CONSOLE (MEM_FLOW, " %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF);
+    if (Buffer[j] != Pattern[j]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (j % 8));    // clear bit n
+      TechPtr->DqsRcvEnFirstPassValOpt[i] = 0;
+      TechPtr->GetFirstPassValOpt[i] = FALSE;
+      TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
+      TechPtr->DqsRcvEnSavedOpt[i] = FALSE;
+      if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) {
+        if (Side == ((Side1En ? 4 : 2) - 1)) {
+          TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT;
+        }
+      }
+    } else {
+      if (TechPtr->FilterSidePassCountOpt[i] == ((Side1En ? 4 : 2) - 1)) {
+        //Only apply filter if all sides have passed
+        if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) {
+          if (TechPtr->GetFirstPassValOpt[i] == FALSE) {
+            // This is the first Pass, mark the start of filter check
+            TechPtr->DqsRcvEnFirstPassValOpt[i] = TechPtr->RcvrEnDlyOpt[i];
+            TechPtr->GetFirstPassValOpt[i] = TRUE;
+            TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
+            TechPtr->RcvrEnDlyOpt[i]++;
+          } else {
+            if ((TechPtr->RcvrEnDlyOpt[i] - TechPtr->DqsRcvEnFirstPassValOpt[i]) < FILTER_WINDOW_SIZE) {
+              if (TechPtr->IncBy1ForNextCountOpt[i] == FALSE) {
+                TechPtr->RcvrEnDlyOpt[i] += FILTER_SECOND_STAGE_COUNT;
+                TechPtr->IncBy1ForNextCountOpt[i] = TRUE;
+              } else {
+                TechPtr->RcvrEnDlyOpt[i]++;
+                TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
+              }
+            } else {
+              // End sweep and add offset to first pass
+              TechPtr->MaxRcvrEnDlyBlOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i];
+              TechPtr->RcvrEnDlyOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i] + FILTER_OFFSET_VALUE;
+              TechPtr->FilterStatusOpt[i] = DONE_FILTER;
+              TechPtr->FilterCountOpt++;
+            }
+          }
+        } else {
+          TechPtr->FilterSidePassCountOpt[i]++;
+        }
+      } else {
+        if (TechPtr->GetFirstPassValOpt[i] == FALSE) {
+          if (Side == ((Side1En ? 4 : 2) - 1)) {
+            TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT;
+          }
+        }
+        TechPtr->FilterSidePassCountOpt[i]++;
+      }
+      TechPtr->DqsRcvEnSavedOpt[i] = TRUE;
+      ChannelPtr->RcvEnDlys[(Receiver >> 1) * MAX_DELAYS + i] = TechPtr->RcvrEnDlyOpt[i];
+    }
+    if (Side == ((Side1En ? 4 : 2) - 1)) {
+      TechPtr->FilterSidePassCountOpt[i] = 0;
+    }
+    if (TechPtr->RcvrEnDlyOpt[i] >= TechPtr->RcvrEnDlyLimitOpt[i]) {
+      TechPtr->FilterCountOpt++;
+    }
+
+    j++;
+  }
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tPass/Fail -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "  %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Measured -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Expected -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]);
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+  );
+
+  return Pass;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *  This function initializes variables for optimized training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemTInitializeVariablesOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ByteLane;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    TechPtr->RcvrEnDlyLimitOpt[ByteLane] = FILTER_MAX_REC_EN_DLY_VALUE;      // @attention - limit depends on proc type
+    TechPtr->DqsRcvEnSavedOpt[ByteLane] = FALSE;
+    TechPtr->RcvrEnDlyOpt[ByteLane] = FILTER_NEW_RECEIVER_START_VALUE;
+    TechPtr->GetFirstPassValOpt[ByteLane] = FALSE;
+    TechPtr->DqsRcvEnFirstPassValOpt[ByteLane] = 0;
+    TechPtr->RevertPassValOpt[ByteLane] = FALSE;
+    TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] = 0;
+    TechPtr->FilterStatusOpt[ByteLane] = START_FILTER;
+    TechPtr->FilterCountOpt = 0;
+    TechPtr->FilterSidePassCountOpt[ByteLane] = 0;
+    TechPtr->IncBy1ForNextCountOpt[ByteLane] = FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function loads the DqsRcvEnDly from saved data and program to additional index
+ *  for optimized DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *
+ */
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Dimm = Receiver >> 1;
+  for (i = 0; i < 8; i++) {
+    if (TechPtr->DqsRcvEnSavedOpt[i]) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
+      ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ */
+
+VOID
+STATIC
+MemTSetRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  )
+{
+  UINT8 ByteLane;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    if (TechPtr->FilterStatusOpt[ByteLane] != DONE_FILTER) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), TechPtr->RcvrEnDlyOpt[ByteLane]);
+    }
+  }
+}
+/*-----------------------------------------------------------------------------
+ *
+ *  This sets any Errors generated from Dly sweep
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]   DCT   - current DCT
+ *     @param[in]   Receiver   - current receiver
+ *
+ *     @return     FALSE - Fatal error occurs.
+ *     @return     TRUE  - No fatal error occurs.
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemTSetSweepErrorOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT8 Dct,
+  IN       BOOLEAN ErrorCheck
+  )
+{
+  UINT8 ByteLane;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    if (TechPtr->RcvrEnDlyOpt[ByteLane] == TechPtr->RcvrEnDlyLimitOpt[ByteLane]) {
+      // no passing window
+      if (ErrorCheck) {
+        return FALSE;
+      }
+      PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, MCTPtr);
+    }
+    if (TechPtr->RcvrEnDlyOpt[ByteLane] > (TechPtr->RcvrEnDlyLimitOpt[ByteLane] - 1)) {
+      // passing window too narrow, too far delayed
+      if (ErrorCheck) {
+        return FALSE;
+      }
+      PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, MCTPtr);
+      DCTPtr->Timings.CsTrainFail |= (UINT16) (3 << Receiver) & DCTPtr->Timings.CsPresent;
+      MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+      if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &MemPtr->StdHeader)) {
+        ASSERT (FALSE);
+        return FALSE;
+      }
+    }
+  }
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *  This function determines the maximum receiver delay value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @retval  MaxRcvrValue - Maximum receiver delay value for all bytelanes
+ * ----------------------------------------------------------------------------
+ */
+
+UINT16
+MemTGetMaxValueOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ByteLane;
+  UINT16 MaxRcvrValue;
+  MaxRcvrValue = 0;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    if (TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] > MaxRcvrValue) {
+      MaxRcvrValue = TechPtr->MaxRcvrEnDlyBlOpt[ByteLane];
+    }
+  }
+  MaxRcvrValue += FILTER_OFFSET_VALUE;
+  return MaxRcvrValue;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *  This function determines if the sweep loop should complete.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @retval  TRUE - All bytelanes pass
+ *              FALSE - Some bytelanes fail
+ * ----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemTCheckRcvrEnDlyLimitOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  if (TechPtr->FilterCountOpt >= (UINT16)MAX_CS_PER_CHANNEL) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function load the result of write levelization training into RcvrEnDlyOpt,
+ *  using it as the initial value for Receiver DQS training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ */
+VOID
+STATIC
+MemTLoadInitialRcvEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 ByteLane;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    TechPtr->RcvrEnDlyOpt[ByteLane] = NBPtr->ChannelPtr->WrDqsDlys[((Receiver >> 1) * TechPtr->DlyTableWidth ()) + ByteLane];
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function finds the DIMM that has the largest receiver enable delay that are trained by PMU
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[out]      *ChipSel   - Pointer to the Chip select that has the largest receiver enable delay
+ *                                   + Read DQS Delay.
+ *
+ *     @return   TRUE - A chip select can be found.
+ *     @return   FALSE - A chip select cannot be found.
+ */
+
+BOOLEAN
+exce856  (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  )
+{
+  UINT8   ChipSelect;
+  BOOLEAN RetVal;
+  UINT16  MaxDly;
+  UINT8   MaxDlyCs;
+
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  RetVal = FALSE;
+  MaxDly = 0;
+  MaxDlyCs = 0;
+  for (ChipSelect = 0; ChipSelect < NBPtr->CsPerChannel; ChipSelect = ChipSelect + NBPtr->CsPerDelay) {
+    /// @todo Fix this when BKDG has updated algorithm
+    if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSelect)) != 0) {
+      MaxDly = 0;
+      MaxDlyCs = ChipSelect;
+      RetVal = TRUE;
+    }
+  }
+
+  TechPtr->MaxDlyForMaxRdLat = MaxDly;
+  *ChipSel = MaxDlyCs;
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c
new file mode 100644
index 0000000000..239b891be2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c
@@ -0,0 +1,252 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttecc.c
+ *
+ * Technology ECC byte support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTECC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTCalcDQSEccTmg (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Type,
+  IN OUT   VOID  *DlyArray
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DQS ECC timings
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTSetDQSEccTmgs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Dimm;
+  UINT8 i;
+
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  if (NBPtr->MCTPtr->NodeMemSize) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+          if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)1 << (Dimm * 2))) {
+            i = Dimm * TechPtr->DlyTableWidth ();
+            MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRcvEnDly, &ChannelPtr->RcvEnDlys[i]);
+            MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRdDqsDly, &ChannelPtr->RdDqsDlys[i]);
+            MemTCalcDQSEccTmg (TechPtr, Dimm, AccessWrDatDly, &ChannelPtr->WrDatDlys[i]);
+          }
+        }
+      }
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the DQS ECC timings
+ *
+ *     @param[in,out]   *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Dimm - Dimm number
+ *     @param[in]       Type - Type of DQS timing
+ *     @param[in,out]   *DlyArray - Pointer to the array of delays per this Dimm
+ *
+ */
+
+VOID
+STATIC
+MemTCalcDQSEccTmg (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Type,
+  IN OUT   VOID  *DlyArray
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 Scale;
+  UINT8 EccByte;
+  UINT16 ByteiDly;
+  UINT16 BytejDly;
+  UINT16 EccDly;
+  UINT8 *WrDqsDly;
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  EccByte = TechPtr->MaxByteLanes ();
+  i = (UINT8) (ChannelPtr->DctEccDqsLike & 0xFF);
+  j = (UINT8) (ChannelPtr->DctEccDqsLike >> 8);
+  Scale = ChannelPtr->DctEccDqsScale;
+  WrDqsDly = &ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth ()];
+
+  if (Type == AccessRcvEnDly) {
+    ByteiDly = ((UINT16 *) DlyArray)[i];
+    BytejDly = ((UINT16 *) DlyArray)[j];
+  } else {
+    ByteiDly = ((UINT8 *) DlyArray)[i];
+    BytejDly = ((UINT8 *) DlyArray)[j];
+  }
+
+  //
+  // For WrDatDly, Subtract TxDqs Delay to get
+  //  TxDq-TxDqs Delta, which is what should be averaged.
+  //
+  if (Type == AccessWrDatDly) {
+    ByteiDly = ByteiDly - WrDqsDly[i];
+    BytejDly = BytejDly - WrDqsDly[j];
+  }
+
+  if (BytejDly > ByteiDly) {
+    EccDly = ByteiDly + (UINT8) (((UINT16) (BytejDly - ByteiDly) * Scale + 0x77) / 0xFF);
+    //                                                            Round up --^
+  } else {
+    EccDly = BytejDly + (UINT8) (((UINT16) (ByteiDly - BytejDly) * (0xFF - Scale) + 0x77) / 0xFF);
+    //                                                                     Round up --^
+  }
+
+  if (Type == AccessRcvEnDly) {
+    ((UINT16 *) DlyArray)[EccByte] = EccDly;
+  } else {
+    ((UINT8 *) DlyArray)[EccByte] = (UINT8) EccDly;
+  }
+
+  //
+  // For WrDatDly, Add back the TxDqs value for ECC bytelane
+  //
+  if (Type == AccessWrDatDly) {
+    EccDly = EccDly + WrDqsDly[EccByte];
+  }
+
+  NBPtr->SetTrainDly (NBPtr, Type, DIMM_BYTE_ACCESS (Dimm, EccByte), EccDly);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c
new file mode 100644
index 0000000000..7a07ef4217
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c
@@ -0,0 +1,337 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtthrc.c
+ *
+ * Phy assisted DQS receiver enable training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTHRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define TpProcMemRcvrSetSeed TpProcMemRcvrSetDelay
+#define TpProcMemRcvrInitPRE TpProcMemRcvrStartSweep
+#define TpProcMemRcvrBackToBackRead TpProcMemRcvrTestPattern
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTProgramRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 Pass
+  );
+
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern UINT16 T1minToFreq[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of Phy assisted receiver enable training
+ *      for current node at DDR800 and below.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTDqsTrainRcvrEnHw (TechPtr, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes second pass of Phy assisted receiver enable training
+ *      for current node at DDR1066 and above.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  // If current speed is higher than start-up speed, do second pass of WL
+  if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
+    return MemTDqsTrainRcvrEnHw (TechPtr, 2);
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes Phy assisted receiver enable training for current node.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ */
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT32 TestAddrRJ16;
+  UINT8  Dct;
+  UINT8  ChipSel;
+  NBPtr = TechPtr->NBPtr;
+
+  TechPtr->TrainingType = TRN_RCVR_ENABLE;
+
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader));
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n");
+
+  // Set environment settings before training
+  MemTBeginTraining (TechPtr);
+  //
+  // Setup hardware training engine (if applicable)
+  //
+  NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    //training for each rank
+    for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; (NBPtr->MCTPtr->Status[SbLrdimms])? ChipSel += 2: ChipSel++) {
+      if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
+        if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) {
+          // 1.Prepare the DIMMs for training
+          NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel / NBPtr->CsPerDelay);
+
+          TechPtr->ChipSel = ChipSel;
+          TechPtr->Pass = Pass;
+          NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL);
+          for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainRxEnPerNibble] (NBPtr, &ChipSel)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) {
+            // 2.Prepare the phy for DQS receiver enable training.
+            IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+            IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x0000\n", TestAddrRJ16);
+            IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t     Byte:  00  01  02  03  04  05  06  07  ECC\n");
+
+            AGESA_TESTPOINT (TpProcMemRcvrSetSeed, &(NBPtr->MemPtr->StdHeader));
+            NBPtr->MemNPrepareRcvrEnDlySeed (NBPtr);
+
+            AGESA_TESTPOINT (TpProcMemRcvrInitPRE, &(NBPtr->MemPtr->StdHeader));
+            // 3.BIOS initiates the phy assisted receiver enable training
+            NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1);
+
+            // 4.BIOS begins sending out of back-to-back reads to create
+            //   a continuous stream of DQS edges on the DDR interface
+            AGESA_TESTPOINT (TpProcMemRcvrBackToBackRead, &(NBPtr->MemPtr->StdHeader));
+            NBPtr->GenHwRcvEnReads (NBPtr, TestAddrRJ16);
+
+            // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training.
+            NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0);
+
+            // 8.Get the gross and fine delay values.
+            // 9.Calculate the corresponding final delay values
+            MemTProgramRcvrEnDly (TechPtr, ChipSel, Pass);
+          }
+        }
+      }
+    }
+  }
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n");
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function calculates final RcvrEnDly for each rank
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  ChipSel - Rank to be trained
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ */
+VOID
+STATIC
+MemTProgramRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 CsPairRcvEnDly;
+  UINT16 RankRcvEnDly[9];
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t      PRE: ");
+  for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) {
+    RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane));
+    IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly);
+
+    RcvEnDly = RcvEnDly + TechPtr->DiffSeedGrossSeedPreGross[ByteLane];
+
+    // Add 1 UI to get to the midpoint of preamble
+    RcvEnDly += 0x20;
+    TechPtr->Bytelane = ByteLane;
+    RankRcvEnDly[ByteLane] = RcvEnDly;
+    if (NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] (NBPtr, &RcvEnDly)) {
+      if (((ChipSel & 1) == 1) && (NBPtr->CsPerDelay == 2)) {
+        // For each rank pair on a dual-rank DIMM, compute the average value of the total delays saved during the
+        //  training of each rank and program the result in D18F2x[1,0]9C_x0000_00[24:10][DqsRcvEnGrossDelay,
+        //  DqsRcvEnFineDelay].
+        CsPairRcvEnDly = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane];
+        RcvEnDly = (CsPairRcvEnDly + RcvEnDly + 1) / 2;
+      }
+    }
+    ChannelPtr->RcvEnDlys[(ChipSel / NBPtr->CsPerDelay) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly;
+    NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel / NBPtr->CsPerDelay), ByteLane), RcvEnDly);
+  }
+
+  IDS_HDT_CONSOLE_DEBUG_CODE (
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t     RxEn: ");
+    for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+      IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]);
+    }
+    if (NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] (NBPtr, NULL)) {
+      if (((ChipSel & 1) == 1) && (NBPtr->CsPerDelay == 2)) {
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t      Avg: ");
+        for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", ChannelPtr->RcvEnDlys[(ChipSel / NBPtr->CsPerDelay) * TechPtr->DlyTableWidth () + ByteLane]);
+        }
+      }
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+  )
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
new file mode 100644
index 0000000000..5be8187def
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -0,0 +1,649 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mtthrcSt.c
+ *
+ * Phy assisted DQS receiver enable seedless training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mttEdgeDetect.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE
+/*----------------------------------------------------------------------------
+3 *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTRdPosRxEnSeedSetDly3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT16 RcvEnDly,
+  IN OUT   UINT8 ByteLane
+  );
+
+VOID
+STATIC
+MemTRdPosRxEnSeedCheckRxEndly3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function checks each bytelane for no window error.
+ *
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemTTrackRxEnSeedlessRdWrNoWindBLError (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT8 i;
+  SWEEP_INFO SweepData;
+  SweepData = *(SWEEP_INFO*)OptParam;
+  for (i = 0; i < ((TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
+    //
+    /// Skip Bytelanes that have already reached the desired result
+    //
+    if ((SweepData.ResultFound & ((UINT16)1 << i)) == 0) {
+      if (SweepData.TrnDelays[i] == SweepData.EndDelay) {
+        if ((SweepData.EndResult & ((UINT16) (1 << i))) != 0) {
+          TechPtr->ByteLaneError[i] = TRUE;
+        } else {
+          TechPtr->ByteLaneError[i] = FALSE;
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *      This function checks each bytelane for small window error.
+ *
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   OptParam   - Optional parameter(Unused)
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemTTrackRxEnSeedlessRdWrSmallWindBLError (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  TechPtr->ByteLaneError[TechPtr->Bytelane] = TRUE;
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function sets the RxEn delay
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *RcvEnDly   - Receiver Enable Delay
+ *     @param[in,out]   *ByteLane   - Bytelane
+ *
+*/
+VOID
+STATIC
+MemTRdPosRxEnSeedSetDly3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT16 RcvEnDly,
+  IN OUT   UINT8 ByteLane
+  )
+{
+  TechPtr->NBPtr->ChannelPtr->RcvEnDlys[(TechPtr->ChipSel / TechPtr->NBPtr->CsPerDelay) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly;
+  TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel / TechPtr->NBPtr->CsPerDelay), ByteLane), RcvEnDly);
+  TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function determines if the currert RxEn delay settings have failed
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+*/
+VOID
+STATIC
+MemTRdPosRxEnSeedCheckRxEndly3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8  MaxDlyDimm;
+  TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &MaxDlyDimm);
+  TechPtr->NBPtr->SetMaxLatency (TechPtr->NBPtr, TechPtr->MaxDlyForMaxRdLat);
+  TechPtr->DqsRdWrPosSaved = 0;
+  MemTTrainDQSEdgeDetect (TechPtr);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function executes RdDQS training and if fails adjusts the RxEn Gross results for
+ *     each bytelane
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+*/
+BOOLEAN
+MemTRdPosWithRxEnDlySeeds3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8  ByteLane;
+  UINT16 PassTestRxEnDly[MAX_BYTELANES_PER_CHANNEL + 1];
+  UINT16 FailTestRxEnDly[MAX_BYTELANES_PER_CHANNEL + 1];
+  UINT16 FinalRxEnCycle[MAX_BYTELANES_PER_CHANNEL + 1];
+  UINT16 RxOrig[MAX_BYTELANES_PER_CHANNEL];
+  UINT8  i;
+  UINT8  j;
+  UINT8  NumBLWithTargetFound;
+  UINT8  MaxByteLanes;
+  INT16  RxEn;
+  BOOLEAN status;
+  BOOLEAN EsbNoDqsPosSave;
+  BOOLEAN OutOfRange[MAX_BYTELANES_PER_CHANNEL];
+  BOOLEAN ByteLanePass[MAX_BYTELANES_PER_CHANNEL];
+  BOOLEAN ByteLaneFail[MAX_BYTELANES_PER_CHANNEL];
+  BOOLEAN RxEnMemClkTested[MAX_BYTELANES_PER_CHANNEL][MAX_POS_RX_EN_SEED_GROSS_RANGE];
+  BOOLEAN RxEnMemClkSt[MAX_BYTELANES_PER_CHANNEL][MAX_POS_RX_EN_SEED_GROSS_RANGE];
+  BOOLEAN RxEnDlyTargetFound[MAX_BYTELANES_PER_CHANNEL];
+  BOOLEAN DlyWrittenToReg[MAX_BYTELANES_PER_CHANNEL];
+  UINT16 RxEnDlyTargetValue[MAX_BYTELANES_PER_CHANNEL];
+  UINT8 AllByteLanesOutOfRange;
+  UINT8 AllByteLanesSaved;
+  UINT8 TotalByteLanesCheckedForSaved;
+  UINT8  MemClkCycle;
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  NumBLWithTargetFound = 0;
+  status = FALSE;
+  EsbNoDqsPosSave = TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos];
+  NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_SUSPEND;
+  IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n");
+  // 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1.
+  NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t       Byte:  00  01  02  03  04  05  06  07  ECC\n");
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: ");
+  //
+  // Start sweep loops for RxEn Seedless Training
+  //
+  MaxByteLanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8;    //dmach
+  //
+  //Initialialize BL variables
+  //
+  for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+    OutOfRange[ByteLane] = FALSE;
+    ByteLanePass[ByteLane] = FALSE;
+    ByteLaneFail[ByteLane] = FALSE;
+    // 2. RxEnOrig = D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] result
+    RxOrig[ByteLane] = TechPtr->RxOrig[ByteLane]; // Original RxEn Dly based on PRE results
+    RxEnDlyTargetFound[ByteLane] = FALSE;
+    RxEnDlyTargetValue[ByteLane] = 0;
+    IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RxOrig[ByteLane]);
+    for (i = 0; i < MAX_POS_RX_EN_SEED_GROSS_RANGE; i++) {
+      RxEnMemClkTested[ByteLane][i] = FALSE;
+    }
+  }
+  // Start MemClk delay sweep
+  for (i = 0; i < MAX_POS_RX_EN_SEED_GROSS_RANGE; i++) {
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\ti: %02x\n", i);
+    // Start direction sweep (0, - Positive, 1 - negative)
+    for (j = 0; j < MAX_POS_RX_EN_SEED_GROSS_DIR; j++) {
+      // Edge detect may run twice to see Pass to fail transition
+      // It is not run if the value are already saved
+      // Fail test is only done if pass is found
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tj: %02x\n", j);
+      // Reset Bytelane Flags for next sweep
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        ByteLaneFail[ByteLane] = FALSE;
+        ByteLanePass[ByteLane] = FALSE;
+        OutOfRange[ByteLane] = FALSE;
+      }
+      if (i == 0 && j == 1) {
+        continue; // Since i & j are the same skip
+      }
+      IDS_HDT_CONSOLE_DEBUG_CODE (
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t             Byte:  00  01  02  03  04  05  06  07  ECC\n");
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t  Target BL Found: ");
+        for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+         IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", ((RxEnDlyTargetFound[ByteLane] == TRUE) ? 'Y' : 'N'));
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t  Target BL Value: ");
+        for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RxEnDlyTargetValue[ByteLane]);
+        }
+      );
+      //
+      //  Find the RxEn Delay for the Pass condition in the Pass to Fail transition
+      //              "PassTestRxEnDly"
+      //
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n");
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t  PassTestRxEnDly: ");
+      PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          // Calculate "PassTestRxEnDly" from  current "RxEnDly"
+          // 3. RxEnOffset = MOD(RxEnOrig + 0x10, 0x40)
+          RxEn = (j == 0) ? ((INT16)RxOrig[ByteLane] + 0x10 + (0x40*i)) : ((INT16)RxOrig[ByteLane] + 0x10 - (0x40*i));
+          // Check if RxEnDly is in a valid range
+          if ((RxEn >= NBPtr->MinRxEnSeedGross) && (RxEn <= NBPtr->MaxRxEnSeedTotal)) {
+            PassTestRxEnDly[ByteLane] = (UINT16)RxEn;
+            // 4. For each DqsRcvEn value beginning from RxEnOffset incrementing by 1 MEMCLK:
+            //    A. Program D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] with
+            //    the current value.
+            MemTRdPosRxEnSeedSetDly3 (TechPtr, PassTestRxEnDly[ByteLane], ByteLane);
+            OutOfRange[ByteLane] = FALSE;
+          } else {
+            OutOfRange[ByteLane] = TRUE;
+          }
+        } else {
+          PassTestRxEnDly[ByteLane] = RxEnDlyTargetValue[ByteLane];
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", PassTestRxEnDly[ByteLane]);
+      }
+      // Check if all BLs out of Range at "PassTestRxEnDly"
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t       OutOfRange: ");
+      AllByteLanesOutOfRange = 0;
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (OutOfRange[ByteLane]) {
+          AllByteLanesOutOfRange++;
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N');
+      }
+      if (AllByteLanesOutOfRange == MaxByteLanes) {
+        continue;  // All BLs out of range, so skip
+      }
+      // Check if all BLs saved Results  at "PassTestRxEnDly"
+      AllByteLanesSaved = 0;
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5);
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          if (!RxEnMemClkTested[ByteLane][MemClkCycle]) {
+            AllByteLanesSaved++;
+          }
+        }
+      }
+      // Check if "RxEnDlyValueForPassCond" passed
+      if (AllByteLanesSaved != 0) {
+        // At least one BL has not been saved, so check if "PassTestRxEnDly" passed
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Checking if PassTestRxEnDly Passes?\n\n");
+        // 4B. Perform 2.10.6.8.5 [DQS Position Training].
+        //     Record the result for the current DqsRcvEn setting as a pass or fail depending if a data eye is found.
+        MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr);
+        IDS_HDT_CONSOLE_DEBUG_CODE (
+          IDS_HDT_CONSOLE (MEM_FLOW, "\n\t             Byte:  00  01  02  03  04  05  06  07  ECC\n");
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\t     Err Status: ");
+          for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+            IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (TechPtr->ByteLaneError[ByteLane] == TRUE) ? 'F' : 'P');
+          }
+        );
+      } else {
+        // All BLs saved, so use saved results for "PassTestRxEnDly"
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tAll BLs Saved at PassTestRxEnDly\n");
+        IDS_HDT_CONSOLE_DEBUG_CODE (
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t             Byte:  00  01  02  03  04  05  06  07  ECC\n");
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t    Save Err Stat: ");
+          for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+            MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5);
+            IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", ((RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE) ? 'F' : 'P'));
+          }
+        );
+      }
+      // Update Saved values for "PassTestRxEnDly"
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          if (OutOfRange[ByteLane] == FALSE) {
+            MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5);
+            if (!RxEnMemClkTested[ByteLane][MemClkCycle]) {
+              RxEnMemClkTested[ByteLane][MemClkCycle] = TRUE;
+              RxEnMemClkSt[ByteLane][MemClkCycle] = TechPtr->ByteLaneError[ByteLane];
+            }
+          }
+        }
+      }
+      //
+      //  Find the RxEn Delay for the Fail condition in the Pass to Fail transition
+      //              "FailTestRxEnDly"
+      //
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        DlyWrittenToReg[ByteLane] = FALSE;
+      }
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        FailTestRxEnDly[ByteLane] = PassTestRxEnDly[ByteLane] + 0x40;
+      }
+      IDS_HDT_CONSOLE_DEBUG_CODE (
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t             Byte:  00  01  02  03  04  05  06  07  ECC\n");
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t  FailTestRxEnDly: ");
+        for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", FailTestRxEnDly[ByteLane]);
+        }
+      );
+      // Check if all BLs Saved Results at FailTestRxEnDly
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tSetting FailTestRxEnDly");
+      AllByteLanesSaved = 0;
+      TotalByteLanesCheckedForSaved = 0;
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+          // Check if RxEnDly + 40 is valid
+          if ((FailTestRxEnDly[ByteLane] >= NBPtr->MinRxEnSeedGross) && (FailTestRxEnDly[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) {
+            if (RxEnMemClkTested[ByteLane][MemClkCycle]) {
+              AllByteLanesSaved++;
+            }
+            OutOfRange[ByteLane] = FALSE;
+          } else {
+            OutOfRange[ByteLane] = TRUE;
+          }
+          TotalByteLanesCheckedForSaved++;
+        }
+      }
+      // Check if all BLs out of Range condition at FailTestRxEnDly
+      AllByteLanesOutOfRange = 0;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t       OutOfRange: ");
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (OutOfRange[ByteLane]) {
+          AllByteLanesOutOfRange++;
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N');
+      }
+      if (AllByteLanesOutOfRange == MaxByteLanes) {
+        continue;  // All BLs out of range, so skip
+      }
+      // Setting FailTestRxEnDly for any BL that was not saved
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t  FailTestRxEnDly: ");
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5);
+          // Check if New RxEnDly has Passed
+          if ((RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] : TechPtr->ByteLaneError[ByteLane]) == FALSE) {
+            if (OutOfRange[ByteLane] == FALSE) {
+              // BL has passed at "New RxEnDly", so check if "New RxEnDly" + 0x40 fails
+              MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+              if (!RxEnMemClkTested[ByteLane][MemClkCycle]) {
+                // Only Set Delays for ByteLanes that have not been already tested
+                MemTRdPosRxEnSeedSetDly3 (TechPtr, FailTestRxEnDly[ByteLane], ByteLane);
+                DlyWrittenToReg[ByteLane] = TRUE;
+                IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'Y');
+              } else {
+                IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'N');
+              }
+              ByteLanePass[ByteLane] = TRUE;
+            } else {
+              IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'O');
+            }
+          } else {
+            IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'F');
+          }
+        } else {
+          IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'N');
+        }
+      }
+      // Check if BLs that passed at PassTestRxEnDly fail at FailTestRxEnDly
+      if (AllByteLanesSaved != TotalByteLanesCheckedForSaved) {
+          // At least one BL has not been saved, so check if FailTestRxEnDly passed
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\n\t\t Checking if FailTestRxEnDly Fails?\n");
+        MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr);
+        IDS_HDT_CONSOLE_DEBUG_CODE (
+          IDS_HDT_CONSOLE (MEM_FLOW, "\n\t         Byte:  00  01  02  03  04  05  06  07  ECC\n");
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t     Err Status: ");
+          for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+            IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (TechPtr->ByteLaneError[ByteLane] == TRUE) ? 'F' : 'P');
+          }
+        );
+      } else {
+        // All BLs saved, so use saved results for FailTestRxEnDly
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tAll BLs Saved at PassTestRxEnDly\n");
+        IDS_HDT_CONSOLE_DEBUG_CODE (
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t               Byte:  00  01  02  03  04  05  06  07  ECC\n");
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t      Save Err Stat: ");
+          for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+            MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+            IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE) ? 'F' : 'P');
+          }
+        );
+      }
+      //
+      //  If BL failes at "FailTestRxEnDly" set FinalRxEnCycle
+      //
+      // Setting FinalRxEnCycle for any BL that Failed at FailTestRxEnDly
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n   Set FinalRxEnCycle: ");
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+          if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) {
+            FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10;
+            if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) {
+              // Since FailTestRxEnDly, we can set FinalRxEnCycle
+              MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane);
+              ByteLaneFail[ByteLane] = TRUE;
+              OutOfRange[ByteLane] = FALSE;
+              IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'Y');
+            } else {
+              OutOfRange[ByteLane] = TRUE;
+              IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'N');
+            }
+          } else {
+            IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'F');
+            OutOfRange[ByteLane] = FALSE;
+          }
+        } else {
+          IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", 'Y');
+        }
+      }
+      // Update Saved values for FailTestRxEnDly
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          if (OutOfRange[ByteLane] == FALSE) {
+            MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+            if (!RxEnMemClkTested[ByteLane][MemClkCycle] && DlyWrittenToReg[ByteLane]) {
+              RxEnMemClkTested[ByteLane][MemClkCycle] = TRUE;
+              RxEnMemClkSt[ByteLane][MemClkCycle] = TechPtr->ByteLaneError[ByteLane];
+            }
+          }
+        }
+      }
+      // Check for out of Range condition
+      AllByteLanesOutOfRange = 0;
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n\t       OutOfRange: ");
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (OutOfRange[ByteLane]) {
+          AllByteLanesOutOfRange++;
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N');
+      }
+      if (AllByteLanesOutOfRange == MaxByteLanes) {
+        continue; // All BLs out of range so skip
+      }
+      IDS_HDT_CONSOLE_DEBUG_CODE (
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n     FinalRxEnCycle: ");
+        for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+          IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", (UINT16) FinalRxEnCycle[ByteLane]);
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n       ByteLaneFail: ");
+        for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+          IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (ByteLaneFail[ByteLane] == TRUE) ? 'Y' : 'N');
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n       ByteLanePass: ");
+        for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+          IDS_HDT_CONSOLE (MEM_FLOW, " %c  ", (ByteLanePass[ByteLane] == TRUE) ? 'Y' : 'N');
+        }
+      );
+      //
+      // Check for exit condition
+      // PassTestRxEnDly = Pass and FailTestRxEnDly[ByteLane] = Fail
+      // If found, use "FinalRxEnCycle" as final RxEnDly value
+      //
+      // 5. Process the array of results and determine a pass-to-fail transition.
+      NumBLWithTargetFound = 0;
+      for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
+        if (RxEnDlyTargetFound[ByteLane] == FALSE) {
+          // Check if the current BL has found its target
+          if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) {
+            RxEnDlyTargetFound[ByteLane] = TRUE;
+            NumBLWithTargetFound++;
+            RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane];
+          } else {
+            RxEnDlyTargetFound[ByteLane] = FALSE;
+          }
+        } else {
+          // BL has already failed and passed, so increment both flags
+          NumBLWithTargetFound++;
+        }
+      }
+      IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+      // Check for exit condition
+      if (NumBLWithTargetFound == MaxByteLanes) {
+        // Exit condition found, so setting new RDQS based on RxEn-0x10 \n\n
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Setting new RDQS based on FinalRxEnCycle \n\n");
+        // 5 A. DqsRcvEnCycle = the total delay value of the pass result.
+        //   B. Program D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] =
+        //   DqsRcvEnCycle - 0x10.
+        NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED;
+        MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr);
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+        status = TRUE;
+        break;
+      } else {
+        status = FALSE;
+      }
+    }
+    // Check for exit condition
+    if (NumBLWithTargetFound == MaxByteLanes) {
+      status = TRUE;
+      break;
+    } else {
+      status = FALSE;
+    }
+    IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+  }
+  TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = EsbNoDqsPosSave;
+  if (i == MAX_POS_RX_EN_SEED_GROSS_RANGE) {
+    TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE;
+  }
+
+  // 6. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 0.
+  NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd HW RxEn Seedless training\n\n");
+  return status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c
new file mode 100644
index 0000000000..0ff87d7f07
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c
@@ -0,0 +1,285 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttml.c
+ *
+ * Technology Max Latency Training support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTML_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function trains Max latency for all dies
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainMaxLatency (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT32 TestAddrRJ16;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT8  *PatternBufPtr;
+  UINT8  *TestBufferPtr;
+  UINT8  CurrentNbPstate;
+  UINT16 CalcMaxLatDly;
+  UINT16 MaxLatDly;
+  UINT16 MaxLatLimit;
+  UINT16 Margin;
+  UINT16 CurTest;
+  UINT16 _CL_;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+  UINT16 i;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  MemPtr = NBPtr->MemPtr;
+  TechPtr->TrainingType = TRN_MAX_READ_LATENCY;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart MaxRdLat training\n");
+  // Set environment settings before training
+  AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader));
+  MemTBeginTraining (TechPtr);
+  //
+  // Initialize the Training Pattern
+  //
+  if (AGESA_SUCCESS != NBPtr->TrainingPatternInit (NBPtr)) {
+    return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+  }
+  TechPtr->PatternLength = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3;
+  //
+  // Setup hardware training engine (if applicable)
+  //
+  NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
+
+  MaxLatDly = 0;
+  _CL_ = TechPtr->PatternLength;
+  PatternBufPtr = TechPtr->PatternBufPtr;
+  TestBufferPtr = TechPtr->TestBufPtr;
+  //
+  // Begin max latency training
+  //
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) {
+      break;
+    }
+
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
+        TechPtr->ChipSel = ChipSel;
+        if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
+          IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+          IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to address: %04x0000\n", TestAddrRJ16);
+
+          // Write the test patterns
+          AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader));
+          NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_);
+
+          // Sweep max latency delays
+          NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &CalcMaxLatDly, &MaxLatLimit, &Margin);
+          AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader));
+
+          TimesFail = 0;
+          ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+          {
+            MaxLatDly = CalcMaxLatDly;
+            for (i = 0; i < (MaxLatLimit - CalcMaxLatDly); i++) {
+              NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
+              IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly);
+              TechPtr->ResetDCTWrPtr (TechPtr, 6);
+
+              AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader));
+              NBPtr->ReadPattern (NBPtr, TestBufferPtr, TestAddrRJ16, _CL_);
+              AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader));
+              CurTest = NBPtr->CompareTestPattern (NBPtr, TestBufferPtr, PatternBufPtr, _CL_ * 64);
+              NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_);
+
+              if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) {
+                // Reverse training decrements MaxLatDly whenever the test passes
+                // and uses the last passing MaxLatDly as left edge
+                if (CurTest == 0xFFFF) {
+                  IDS_HDT_CONSOLE (MEM_FLOW, "  P");
+                  if (MaxLatDly == 0) {
+                    break;
+                  } else {
+                    MaxLatDly--;
+                  }
+                }
+              } else {
+                // Traditional training increments MaxLatDly until the test passes
+                // and uses it as left edge
+                if (CurTest == 0xFFFF) {
+                  IDS_HDT_CONSOLE (MEM_FLOW, "  P");
+                  break;
+                } else {
+                  MaxLatDly++;
+                }
+              }
+              IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+            } // End of delay sweep
+            ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail)
+          }
+
+          AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader));
+
+          if (MaxLatDly >= MaxLatLimit) {
+            PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            SetMemError (AGESA_ERROR, MCTPtr);
+            NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent;
+            MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+            if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+              ASSERT (FALSE);
+              return FALSE;
+            }
+          } else {
+            NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] (NBPtr, &TestAddrRJ16);
+
+            MaxLatDly = MaxLatDly + Margin;
+            if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) {
+              MaxLatDly++;  // Add 1 to get back to the last passing value
+            }
+            // Set final delays
+            CurrentNbPstate = (UINT8) MemNGetBitFieldNb (NBPtr, BFCurNbPstate);
+            ASSERT (CurrentNbPstate <= 3);
+            NBPtr->ChannelPtr->DctMaxRdLat [CurrentNbPstate] = MaxLatDly;
+            NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
+            IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFinal MaxRdLat: %03x\n", MaxLatDly);
+
+          }
+        }
+      }
+    }
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "End MaxRdLat training\n\n");
+  //
+  // Finalize the Pattern
+  //
+  NBPtr->TrainingPatternFinalize (NBPtr);
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c
new file mode 100644
index 0000000000..1e9776aaf1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c
@@ -0,0 +1,452 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttoptsrc.c
+ *
+ * New Technology Software based DQS receiver enable training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTOPTSRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTDqsTrainOptRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+BOOLEAN
+MemTNewRevTrainingSupport (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of receiver enable training for all dies
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainOptRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTDqsTrainOptRcvrEnSw (TechPtr, 1);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes receiver enable training for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+STATIC
+MemTDqsTrainOptRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  _16BYTE_ALIGN  UINT8  PatternBuffer[6 * 64];
+  UINT8  TestBuffer[256];
+  UINT8  *PatternBufPtr[6];
+  UINT8  *TempPtr;
+  UINT32 TestAddrRJ16[4];
+  UINT32 TempAddrRJ16;
+  UINT32 RealAddr;
+  UINT16 CurTest[4];
+  UINT8 Dct;
+  UINT8 Receiver;
+  UINT8 i;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+  UINT16 RcvrEnDly;
+  UINT16 MaxRcvrEnDly;
+  UINT16 RcvrEnDlyLimit;
+  UINT16 MaxDelayCha;
+  BOOLEAN IsDualRank;
+  BOOLEAN S0En;
+  BOOLEAN S1En;
+
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  TechPtr->TrainingType = TRN_RCVR_ENABLE;
+
+
+  TempAddrRJ16 = 0;
+  TempPtr = NULL;
+  MaxDelayCha = 0;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Optimized SW RxEn training\n");
+  // Set environment settings before training
+  MemTBeginTraining (TechPtr);
+
+  PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer;
+  // These two patterns used for first Test Address
+  MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64);
+  // Second Cacheline used for Dummy Read is the inverse of
+  //  the first so that is is not mistaken for the real read
+  MemUFillTrainPattern (TestPattern1, PatternBufPtr[0] + 64, 64);
+  PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128;
+  // These two patterns used for second Test Address
+  MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64);
+  // Second Cacheline used for Dummy Read is the inverse of
+  //  the first so that is is not mistaken for the real read
+  MemUFillTrainPattern (TestPattern0, PatternBufPtr[1] + 64, 64);
+
+  // Fill pattern for flush after every sweep
+  PatternBufPtr[4] = PatternBufPtr[0] + 256;
+  MemUFillTrainPattern (TestPattern3, PatternBufPtr[4], 64);
+
+  // Fill pattern for initial dummy read
+  PatternBufPtr[5] = PatternBufPtr[0] + 320;
+  MemUFillTrainPattern (TestPattern4, PatternBufPtr[5], 64);
+
+
+  // Begin receiver enable training
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    // Set training bit
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1);
+
+    // Relax Max Latency before training
+    NBPtr->SetMaxLatency (NBPtr, 0xFFFF);
+
+    if (Pass == FIRST_PASS) {
+      TechPtr->InitDQSPos4RcvrEn (TechPtr);
+    }
+
+    // there are four receiver pairs, loosely associated with chipselects.
+    Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8;
+    for (; Receiver < 8; Receiver += 2) {
+      S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]);
+      S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]);
+      if (S0En) {
+        TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16;
+      }
+      if (S1En) {
+        TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16;
+      }
+      if (S0En && S1En) {
+        IsDualRank = TRUE;
+      } else {
+        IsDualRank = FALSE;
+      }
+      if (S0En || S1En) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver);
+
+        RcvrEnDlyLimit = 0x1FF;      // @attention - limit depends on proc type
+        TechPtr->DqsRcvEnSaved = 0;
+        RcvrEnDly = RcvrEnDlyLimit;
+        RealAddr = 0;
+
+        TechPtr->GetFirstPassVal = FALSE;
+        TechPtr->DqsRcvEnFirstPassVal = 0;
+        TechPtr->RevertPassVal = FALSE;
+        TechPtr->InitializeVariablesOpt (TechPtr);
+
+        // Write the test patterns
+        AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: ");
+        for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+          // One cacheline of data to be tested and one of dummy data
+          MemUWriteCachelines (RealAddr, PatternBufPtr[i], 2);
+          // This is dummy data with a different pattern used for the first dummy read.
+          MemUWriteCachelines (RealAddr + 128, PatternBufPtr[5], 1);
+          IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]);
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+
+        // Sweep receiver enable delays
+        AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
+        TimesFail = 0;
+        ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+        {
+          TechPtr->LoadInitialRcvrEnDlyOpt (TechPtr, Receiver);
+          while (!TechPtr->CheckRcvrEnDlyLimitOpt (TechPtr)) {
+            AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
+            TechPtr->SetRcvrEnDlyOpt (TechPtr, Receiver, RcvrEnDly);
+            // Read and compare the first beat of data
+            for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+              AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
+              RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+              //
+              // Issue dummy cacheline reads
+              //
+              MemUReadCachelines (TestBuffer + 128, RealAddr + 128, 1);
+              MemUReadCachelines (TestBuffer, RealAddr, 1);
+              MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr);
+              //
+              // Perform actual read which will be compared
+              //
+              MemUReadCachelines (TestBuffer + 64, RealAddr + 64, 1);
+              AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
+              CurTest[i] = TechPtr->Compare1ClPatternOpt (TechPtr, TestBuffer + 64 , PatternBufPtr[i] + 64, i, Receiver, S1En);
+              // Due to speculative execution during MemUReadCachelines, we must
+              //  flush one more cache line than we read.
+              MemUProcIOClFlush (TestAddrRJ16[i], 4, MemPtr);
+              TechPtr->ResetDCTWrPtr (TechPtr, Receiver);
+
+              //
+              // Swap the test pointers such that even and odd steps alternate.
+              //
+              if ((i % 2) == 0) {
+                TempPtr = PatternBufPtr[i];
+                PatternBufPtr[i] = PatternBufPtr[i + 1];
+
+                TempAddrRJ16 = TestAddrRJ16[i];
+                TestAddrRJ16[i] = TestAddrRJ16[i + 1];
+              } else {
+                PatternBufPtr[i] = TempPtr;
+                TestAddrRJ16[i] = TempAddrRJ16;
+              }
+            }
+          }   // End of delay sweep
+          ERROR_HANDLE_RETRAIN_END (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, TRUE), TimesFail)
+        }
+
+        if (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, FALSE)) {
+          return FALSE;
+        }
+
+        TechPtr->LoadRcvrEnDlyOpt (TechPtr, Receiver);     // set final delays
+        //
+        // Flush AA and 55 patterns by reading a dummy pattern to fill in FIFO
+        //
+        // Aquire a new FSBase, based on the last test address that we stored.
+        RealAddr = MemUSetUpperFSbase (TempAddrRJ16, MemPtr);
+        ASSERT (RealAddr != 0);
+        MemUWriteCachelines (RealAddr, PatternBufPtr[4], 1);
+        MemUWriteCachelines (RealAddr + 64, PatternBufPtr[4], 1);
+        MemUReadCachelines (TestBuffer, RealAddr, 2);
+        // Due to speculative execution during MemUReadCachelines, we must
+        //  flush one more cache line than we read.
+        MemUProcIOClFlush (TempAddrRJ16, 3, MemPtr);
+      }
+    }   // End while Receiver < 8
+
+    // Clear training bit when done
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
+
+    // Set Max Latency for both channels
+    MaxRcvrEnDly = TechPtr->GetMaxValueOpt (TechPtr);
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly);
+    if (MCTPtr->GangedMode) {
+      if (Dct == 0) {
+        MaxDelayCha = MaxRcvrEnDly;
+      } else if (MaxRcvrEnDly > MaxDelayCha) {
+        NBPtr->SwitchDCT (NBPtr, 0);
+        NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+      }
+    } else {
+      NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+    }
+    TechPtr->ResetDCTWrPtr (TechPtr, 6);
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "End Optimized SW RxEn training\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *  This function saves passing DqsRcvEnDly values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       cmpResultRank0 - compare result for Rank 0
+ *     @param[in]       cmpResultRank0 - compare result for Rank 1
+ *
+ *     @retval  TRUE - All bytelanes pass
+ *              FALSE - Some bytelanes fail
+ * ----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilterOpt (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
+
+  Dimm = Receiver >> 1;
+
+  if (TechPtr->GetFirstPassVal && (RcvEnDly - TechPtr->DqsRcvEnFirstPassVal) >= 0x30) {
+    for (i = 0; i < 8; i++) {
+      ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i] = TechPtr->DqsRcvEnFirstPassVal + NEW_RECEIVER_FINAL_OFFSETVALUE;
+    }
+    TechPtr->DqsRcvEnSaved = 0xFF;
+  }
+
+  if (Passed == 0xFF) {
+    if (!TechPtr->GetFirstPassVal) {
+      TechPtr->DqsRcvEnFirstPassVal = RcvEnDly;
+      TechPtr->GetFirstPassVal = TRUE;
+    }
+    return TRUE;
+  } else {
+    TechPtr->DqsRcvEnFirstPassVal = 0;
+
+    // We have got first passing value, but later, we meet with glitch
+    if (TechPtr->GetFirstPassVal) {
+      TechPtr->DqsRcvEnFirstPassVal = 0xFF;
+      TechPtr->GetFirstPassVal = FALSE;
+    }
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
new file mode 100644
index 0000000000..0b636e24ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
@@ -0,0 +1,372 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttsrc.c
+ *
+ * Technology Software based DQS receiver enable training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "GeneralServices.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTSRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of receiver enable training for all dies
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTDqsTrainRcvrEnSw (TechPtr, 1);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes receiver enable training for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  _16BYTE_ALIGN  UINT8  PatternBuffer[3 * 64];
+  UINT8  TestBuffer[120];
+  UINT8  *PatternBufPtr[4];
+  UINT8  *TempPtr;
+  UINT32 TestAddrRJ16[4];
+  UINT32 TempAddrRJ16;
+  UINT32 RealAddr;
+  UINT16 CurTest[4];
+  UINT8 Dct;
+  UINT8 Receiver;
+  UINT8 i;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+  UINT16 RcvrEnDly;
+  UINT16 MaxRcvrEnDly;
+  UINT16 RcvrEnDlyLimit;
+  UINT16 MaxDelayCha;
+  BOOLEAN IsDualRank;
+  BOOLEAN S0En;
+  BOOLEAN S1En;
+  UINT8 MaxFilterDly;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  TechPtr->TrainingType = TRN_RCVR_ENABLE;
+
+
+  TempAddrRJ16 = 0;
+  TempPtr = NULL;
+  MaxDelayCha = 0;
+  MaxFilterDly = TechPtr->MaxFilterDly;
+  RcvrEnDlyLimit = NBPtr->RcvrEnDlyLimit;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart SW RxEn training\n");
+  // Set environment settings before training
+  MemTBeginTraining (TechPtr);
+
+  PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer;
+  MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64);
+  PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128;
+  MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64);
+
+  // Begin receiver enable training
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
+  MaxRcvrEnDly = 0;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    // Set training bit
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1);
+
+    // Relax Max Latency before training
+    NBPtr->SetMaxLatency (NBPtr, 0xFFFF);
+
+    if (Pass == FIRST_PASS) {
+      TechPtr->InitDQSPos4RcvrEn (TechPtr);
+    }
+
+    // there are four receiver pairs, loosely associated with chipselects.
+    Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8;
+    for (; Receiver < 8; Receiver += 2) {
+      TechPtr->DqsRcvEnSaved = 0;
+      RcvrEnDly = RcvrEnDlyLimit;
+      S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]);
+      S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]);
+      if (S0En) {
+        TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16;
+      }
+      if (S1En) {
+        TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16;
+      }
+      if (S0En && S1En) {
+        IsDualRank = TRUE;
+      } else {
+        IsDualRank = FALSE;
+      }
+
+      if (S0En || S1En) {
+        IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver);
+
+        // Write the test patterns
+        AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
+        IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: ");
+        for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+          MemUWriteCachelines (RealAddr, PatternBufPtr[i], 1);
+          IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]);
+        }
+        IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+
+        // Initialize RcvrEnDly value and other DCT stored values
+        //                MCTPtr->DqsRcvEnPass = Pass ? 0xFF : 0;
+
+        // Sweep receiver enable delays
+        AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
+        TimesFail = 0;
+        ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+        {
+          for (RcvrEnDly = 0; RcvrEnDly < RcvrEnDlyLimit; RcvrEnDly++) {
+            AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
+            TechPtr->SetRcvrEnDly (TechPtr, Receiver, RcvrEnDly);
+            IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", RcvrEnDly);
+
+            // Read and compare the first beat of data
+            for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+              AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
+              RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+              MemUReadCachelines (TestBuffer, RealAddr, 1);
+              AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
+              CurTest[i] = TechPtr->Compare1ClPattern (TechPtr, TestBuffer, PatternBufPtr[i]);
+              // Due to speculative execution during MemUReadCachelines, we must
+              //  flush one more cache line than we read.
+              MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr);
+              TechPtr->ResetDCTWrPtr (TechPtr, Receiver);
+
+              //
+              // Swap the test pointers such that even and odd steps alternate.
+              //
+              if ((i % 2) == 0) {
+                TempPtr = PatternBufPtr[i];
+                PatternBufPtr[i] = PatternBufPtr[i + 1];
+
+                TempAddrRJ16 = TestAddrRJ16[i];
+                TestAddrRJ16[i] = TestAddrRJ16[i + 1];
+              } else {
+                PatternBufPtr[i] = TempPtr;
+                TestAddrRJ16[i] = TempAddrRJ16;
+              }
+            }
+
+            if (TechPtr->SaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, S0En ? (CurTest[0] & CurTest[1]) : 0xFFFF, S1En ? (CurTest[2] & CurTest[3]) : 0xFFFF)) {
+              // if all bytelanes pass
+              if (MaxRcvrEnDly < (RcvrEnDly - MaxFilterDly)) {
+                MaxRcvrEnDly = RcvrEnDly - MaxFilterDly;
+              }
+              break;
+            }
+          } // End of delay sweep
+          ERROR_HANDLE_RETRAIN_END ((RcvrEnDly > (RcvrEnDlyLimit - 1)), TimesFail)
+        }
+
+        if (RcvrEnDly == RcvrEnDlyLimit) {
+          // no passing window
+          PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ERROR, MCTPtr);
+        }
+
+        if (RcvrEnDly > (RcvrEnDlyLimit - 1)) {
+        // passing window too narrow, too far delayed
+          PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ERROR, MCTPtr);
+          DCTPtr->Timings.CsTrainFail |= DCTPtr->Timings.CsPresent & (UINT16) (3 << Receiver);
+          MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+          if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) {
+            ASSERT (FALSE);
+            return FALSE;
+          }
+        }
+      }
+
+      TechPtr->LoadRcvrEnDly (TechPtr, Receiver);     // set final delays
+    }   // End while Receiver < 8
+
+    // Clear training bit when done
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
+
+    // Set Max Latency for both channels
+    MaxRcvrEnDly += 0x20;  // @attention -
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly);
+    if (MCTPtr->GangedMode) {
+      if (Dct == 0) {
+        MaxDelayCha = MaxRcvrEnDly;
+      } else if (MaxRcvrEnDly > MaxDelayCha) {
+        NBPtr->SwitchDCT (NBPtr, 0);
+        NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+      }
+    } else {
+      NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+    }
+    TechPtr->ResetDCTWrPtr (TechPtr, 6);
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/ma.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/ma.h
new file mode 100644
index 0000000000..0a34f94c62
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/ma.h
@@ -0,0 +1,343 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * ma.h
+ *
+ * ARDK common header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MA_H_
+#define _MA_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+#define MAX_CS_PER_CHANNEL      8   ///< Max CS per channel
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/** MARDK Structure*/
+typedef struct {
+  UINT16   Speed;                  ///< Dram speed in MHz
+  UINT8    Loads;                  ///< Number of Data Loads
+  UINT32   AddrTmg;                ///< Address Timing value
+  UINT32   Odc;                    ///< Output Driver Compensation Value
+} PSCFG_ENTRY;
+
+/** MARDK Structure*/
+typedef struct {
+  UINT16   Speed;                  ///< Dram speed in MHz
+  UINT8    Loads;                  ///< Number of Data Loads
+  UINT32   AddrTmg;                ///< Address Timing value
+  UINT32   Odc;                    ///< Output Driver Compensation Value
+  UINT8    Dimms;                  ///< Number of Dimms
+} ADV_PSCFG_ENTRY;
+
+/** MARDK Structure for RDIMMs*/
+typedef struct {
+  UINT16   Speed;                  ///< Dram speed in MHz
+  UINT16   DIMMRankType;         ///< Bitmap of Ranks   //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
+  UINT32   AddrTmg;                ///< Address Timing value
+  UINT16   RC2RC8;                   ///< RC2 and RC8 value  //High byte: 1st pair value, Low byte: 2nd pair value
+  UINT8    Dimms;                  ///< Number of Dimms
+} ADV_R_PSCFG_ENTRY;
+
+/** MARDK Structure*/
+typedef struct {
+  UINT16   DIMMRankType;         ///< Bitmap of Ranks   //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
+  UINT32   PhyRODTCSLow;          ///< Fn2_9C 180
+  UINT32   PhyRODTCSHigh;         ///< Fn2_9C 181
+  UINT32   PhyWODTCSLow;          ///< Fn2_9C 182
+  UINT32   PhyWODTCSHigh;         ///< Fn2_9C 183
+  UINT8    Dimms;                  ///< Number of Dimms
+} ADV_PSCFG_ODT_ENTRY;
+
+/** MARDK Structure for Write Levelization ODT*/
+typedef struct {
+  UINT16   DIMMRankType;         ///< Bitmap of Ranks   //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
+  UINT8    PhyWrLvOdt[MAX_CS_PER_CHANNEL / 2];            ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm
+  UINT8    Dimms;                ///< Number of Dimms
+} ADV_R_PSCFG_WL_ODT_ENTRY;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+MemAGetPsCfgDef (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRDr2 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSDA2 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSRb3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgURb3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSPh3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUPh3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSLN3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgULN3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSON3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUON3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgROr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUOr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+UINT16
+MemAGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemRecNGetPsCfgDef (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+UINT16
+MemRecNGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemRecNGetPsCfgUDIMM3Nb (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemRecNGetPsCfgSODIMM3Nb (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemRecNGetPsCfgRDIMM3Nb (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+#endif  /* _MA_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/memPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/memPage.h
new file mode 100644
index 0000000000..cdabbf2537
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/memPage.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for Memory Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ ******************************************************************************
+ */
+
+/**
+ * @page memmain Memory Component Documentation
+ *
+ * Additional documentation for the Memory component consists of
+ *
+ * - Maintenance Guides:
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/merrhdl.h
new file mode 100644
index 0000000000..85edb98b69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/merrhdl.h
@@ -0,0 +1,130 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmerrhdl.h
+ *
+ * main error handling
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MMERRHDL_H_
+#define _MMERRHDL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define EXCLUDE_ALL_DCT 0xFF
+#define EXCLUDE_ALL_CHIPSEL  0xFF
+
+/// default times of training
+#define DEFAULT_TRAINING_TIMES 1
+
+/// number of us to wait in parallel training
+#define PARALLEL_TRAINING_TIMEOUT 60000000
+
+/// number of us to wait in PCI space access
+#define PCI_ACCESS_TIMEOUT 10000000
+/// number of us to wait in special PCI space access which takes much longer than others
+#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000
+
+/// Beginning of retrain handling, must be ended with the ending of the handling
+#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit)
+
+/// Ending of retrain handling
+#define ERROR_HANDLE_RETRAIN_END(condition, counter) \
+if (condition) { \
+  counter ++; \
+} else { \
+  break; \
+}
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemErrHandle (
+  IN       DIE_STRUCT *MCTPtr,
+  IN       UINT8  DCT,
+  IN       UINT16  ChipSelMask,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  /* _MMERRHDL_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h
new file mode 100644
index 0000000000..f60994a068
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h
@@ -0,0 +1,140 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfParallelTraining.h
+ *
+ * Header file for the parallel training feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFPARALLELTRAINING_H_
+#define _MFPARALLELTRAINING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+typedef BOOLEAN (*REMOTE_NBBLOCK_CONSTRUCTOR) (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+);
+
+///< This structure defines the environment on the AP for parallel training
+typedef struct _REMOTE_TRAINING_ENV {
+  IN OUT AMD_CONFIG_PARAMS StdHeader;                ///< Config pointer of BSP
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+  IN REMOTE_NBBLOCK_CONSTRUCTOR NBBlockCtor;         ///< NB Block constructor
+  IN MEM_FEAT_BLOCK_NB *FeatPtr;                     ///< Feature block pointer
+  IN UINT8 *TableBasedAlterations;                   ///< Point to an array of data bytes describing desired modifications to register settings
+  IN PSO_TABLE *PlatformMemoryConfiguration;                 ///< Point to platform config table
+  IN UINT32 HoleBase;                                ///< Used for Memtyping
+  IN UINT32 UmaSize;                               ///< Used for Memtyping
+  IN UINT16 BottomIo;                                ///< Used for Memtyping
+  IN UINT32 SysLimit;                                ///< Used for Memtyping
+  IN UINT8  BspSocket;                               ///< Socket number of BSP
+  IN UINT8  BspCore;                                 ///< Core number of BSP
+  IN DIE_STRUCT DieStruct;                           ///< Remote copy of Die Struct
+} REMOTE_TRAINING_ENV;
+
+///< This structure defines Die information
+typedef struct _DIE_INFO {
+  IN OUT UINT8 Socket;                               ///< Socket number
+  IN OUT UINT8 Core;                                 ///< Core number
+  IN OUT BOOLEAN Training;                           ///< Training Flag, 1 = Training has been started on this core
+} DIE_INFO;
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFParallelTraining (
+  IN OUT   REMOTE_TRAINING_ENV *EnvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif  /* _MFPARALLELTRAINING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h
new file mode 100644
index 0000000000..d617d40fa3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h
@@ -0,0 +1,108 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfStandardTraining.h
+ *
+ * Feature implementation of standard function which performs memory training
+ * from the BSP only
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFSTANDARDTRAINING_H_
+#define _MFSTANDARDTRAINING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFStandardTraining (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFSTANDARDTRAINING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h
new file mode 100644
index 0000000000..067145bea5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfmemclr.h
+ *
+ * Feature Functions For Memory Clear Operation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MFMEMCLR_H_
+#define _MFMEMCLR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFMctMemClr_Init (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemFMctMemClr_Sync (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFMEMCLR_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h
new file mode 100644
index 0000000000..2567e671e6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h
@@ -0,0 +1,398 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mfS3.h
+ *
+ * S3 resume memory related functions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/S3)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFS3_H_
+#define _MFS3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define PRESELFREF 0
+#define POSTSELFREF 1
+#define DCT0 0
+#define DCT1 1
+#define DCT0_MASK 0x1
+#define DCT1_MASK 0x2
+#define DCT0_NBPSTATE_SUPPORT_MASK 0x4
+#define DCT1_NBPSTATE_SUPPORT_MASK 0x8
+#define DCT0_DDR3_MASK 0x10
+#define DCT1_DDR3_MASK 0x20
+#define NODE_WITHOUT_DIMM_MASK 0x80
+#define DCT0_ANY_DIMM_MASK 0x55
+#define DCT1_ANY_DIMM_MASK 0xAA
+#define ANY_DIMM_MASK 0xFF
+
+#define DCT_PHY_FLAG 0
+#define DCT_EXTRA_FLAG 1
+#define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset)
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// struct for all the descriptor for pre exit self refresh and post exit self refresh
+typedef struct _DESCRIPTOR_GROUP {
+  PCI_DEVICE_DESCRIPTOR PCIDevice[2];  ///< PCI device descriptor
+  CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2];  ///< Conditional PCI device descriptor
+  MSR_DEVICE_DESCRIPTOR MSRDevice[2];  ///< MSR device descriptor
+  CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2];  ///< Conditional MSR device descriptor
+} DESCRIPTOR_GROUP;
+
+/// Northbridge block to be used in S3 resume and save.
+typedef struct _S3_MEM_NB_BLOCK {
+  UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap.
+  struct _MEM_NB_BLOCK *NBPtr;    ///< Pointer to the north bridge block.
+  VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register
+  VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting
+  VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting
+  UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register
+  BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh
+  VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base
+  AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device
+} S3_MEM_NB_BLOCK;
+
+/// Header for heap space to store the special case register.
+typedef struct _S3_SPECIAL_CASE_HEAP_HEADER {
+  UINT8 Node;  ///< Node ID for the the header
+  UINT8 Offset;  ///< Offset for the target node
+} S3_SPECIAL_CASE_HEAP_HEADER;
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdMemS3Resume (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+MemS3ResumeInitNB (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+MemS3Deallocate (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                     *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetDeviceList (
+  IN OUT   DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MemFS3Wait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNS3ResumeNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNS3ResumeClientNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNS3ResumeUNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNS3GetConPCIMaskNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+VOID
+MemNS3GetConPCIMaskUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+VOID
+MemNS3GetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3GetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3RestoreScrubNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Node
+  );
+
+AGESA_STATUS
+MemS3InitNB (
+  IN OUT   S3_MEM_NB_BLOCK **S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT **MemPtr,
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MemNS3DisNbPsDbgNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3EnNbPsDbg1Nb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetDynModeChangeNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3DisableChannelNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetDisAutoCompUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetPreDriverCalUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+BOOLEAN
+MemNS3DctCfgSelectUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *Dct
+  );
+
+VOID
+MemNS3GetNBPStateDepRegUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetNBPStateDepRegUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SaveNBRegiserUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3RestoreNBRegiserUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetMemClkFreqValUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3ChangeMemPStateContextNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetPhyClkDllFineClientNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3ForceNBP0Unb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3ReleaseNBPSUnb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+#endif //_MFS3_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h
new file mode 100644
index 0000000000..07526fd946
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mftds.h
+ *
+ * Memory Controller
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFTDS_H_
+#define _MFTDS_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemFInitTableDrive (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8     time
+  );
+#endif  /* _MFTDS_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h
new file mode 100644
index 0000000000..e4bebb7edd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h
@@ -0,0 +1,1378 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mm.h
+ *
+ * Common main functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MM_H_
+#define _MM_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+#define ALLOC_SOCKET_STRUCT_HANDLE    0
+#define ALLOC_DIE_STRUCT_HANDLE       1
+#define ALLOC_DCT_STRUCT_HANDLE       2
+#define ALLOC_CHL_STRUCT_HANDLE       3
+#define ALLOC_PLATFORM_PTR_HANDLE     4
+#define ALLOC_FORM_FACTOR_HANDLE      5
+#define ALLOC_TRN_DATA_HANDLE         6
+#define ALLOC_DIMM_DATA_HANDLE        7
+#define ALLOC_PAR_TRN_HANDLE          8
+#define ALLOC_NB_REG_TABLE            9
+#define ALLOC_DEVICE_INFO             10
+
+#define GENERATE_MEM_HANDLE(type, x, y, z) (\
+  AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \
+)
+
+/// Heap handle for each supported family's NB register table
+typedef enum {
+  NbRegTabDR,           ///< Heap handle for DR NB register table
+  NbRegTabDA,           ///< Heap handle for DA NB register table
+  NbRegTabC32,          ///< Heap handle for C32 NB register table
+  NbRegTabHY,           ///< Heap handle for HY NB register table
+  NbRegTabLN,           ///< Heap handle for LN NB register table
+  NbRegTabON,           ///< Heap handle for ON NB register table
+  NbRegTabOR,           ///< Heap handle for OR NB register table
+  NbRegTabTN,           ///< Heap handle for TN NB register table
+  NumberOfNbRegTables   ///< Number of families that have NB register tables
+} NB_REG_TAB_HANDLE;
+
+
+#define VOLT1_5_ENCODED_VAL 0
+#define VOLT1_35_ENCODED_VAL 1
+#define VOLT1_25_ENCODED_VAL 2
+#define CONVERT_VDDIO_TO_ENCODED(VddIo) (\
+  (VddIo == VOLT1_5) ? VOLT1_5_ENCODED_VAL : ((VddIo == VOLT1_35) ? VOLT1_35_ENCODED_VAL : ((VddIo == VOLT1_25) ? VOLT1_25_ENCODED_VAL : 0xFF)) \
+)
+#define CONVERT_ENCODED_TO_VDDIO(EncodedVal) (\
+  (EncodedVal == VOLT1_5_ENCODED_VAL) ? VOLT1_5 : ((EncodedVal == VOLT1_35_ENCODED_VAL) ? VOLT1_35 : ((EncodedVal == VOLT1_25_ENCODED_VAL) ? VOLT1_25 : VOLT_UNSUPPORTED)) \
+)
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Bit field names used in memory initialization
+typedef enum {
+  BFDevVendorIDReg,                     ///< Bit field DevVendorIDReg
+  BFNodeID,                             ///< Bit field NodeID
+  BFNodeCnt,                            ///< Bit field NodeCnt
+
+  BFDramBaseReg0,                       ///< Bit field DramBaseReg0
+  BFDramBaseReg1,                       ///< Bit field DramBaseReg1
+  BFDramBaseReg2,                       ///< Bit field DramBaseReg2
+  BFDramBaseReg3,                       ///< Bit field DramBaseReg3
+  BFDramBaseReg4,                       ///< Bit field DramBaseReg4
+  BFDramBaseReg5,                       ///< Bit field DramBaseReg5
+  BFDramBaseReg6,                       ///< Bit field DramBaseReg6
+  BFDramBaseReg7,                       ///< Bit field DramBaseReg7
+
+  BFDramLimitReg0,                      ///< Bit field DramLimitReg0
+  BFDramLimitReg1,                      ///< Bit field DramLimitReg1
+  BFDramLimitReg2,                      ///< Bit field DramLimitReg2
+  BFDramLimitReg3,                      ///< Bit field DramLimitReg3
+  BFDramLimitReg4,                      ///< Bit field DramLimitReg4
+  BFDramLimitReg5,                      ///< Bit field DramLimitReg5
+  BFDramLimitReg6,                      ///< Bit field DramLimitReg6
+  BFDramLimitReg7,                      ///< Bit field DramLimitReg7
+
+  BFDramBaseHiReg0,                     ///< Bit field DramBaseHiReg0
+  BFDramBaseHiReg1,                     ///< Bit field DramBaseHiReg1
+  BFDramBaseHiReg2,                     ///< Bit field DramBaseHiReg2
+  BFDramBaseHiReg3,                     ///< Bit field DramBaseHiReg3
+  BFDramBaseHiReg4,                     ///< Bit field DramBaseHiReg4
+  BFDramBaseHiReg5,                     ///< Bit field DramBaseHiReg5
+  BFDramBaseHiReg6,                     ///< Bit field DramBaseHiReg6
+  BFDramBaseHiReg7,                     ///< Bit field DramBaseHiReg7
+
+  BFDramLimitHiReg0,                    ///< Bit field DramLimitHiReg0
+  BFDramLimitHiReg1,                    ///< Bit field DramLimitHiReg1
+  BFDramLimitHiReg2,                    ///< Bit field DramLimitHiReg2
+  BFDramLimitHiReg3,                    ///< Bit field DramLimitHiReg3
+  BFDramLimitHiReg4,                    ///< Bit field DramLimitHiReg4
+  BFDramLimitHiReg5,                    ///< Bit field DramLimitHiReg5
+  BFDramLimitHiReg6,                    ///< Bit field DramLimitHiReg6
+  BFDramLimitHiReg7,                    ///< Bit field DramLimitHiReg7
+
+  BFDramHoleAddrReg,                    ///< Bit field DramHoleAddrReg
+
+  BFDramRngRE0,                         ///< Bit field DramBaseReg0 RE
+  BFDramRngRE1,                         ///< Bit field DramBaseReg1 RE
+  BFDramRngRE2,                         ///< Bit field DramBaseReg2 RE
+  BFDramRngRE3,                         ///< Bit field DramBaseReg3 RE
+  BFDramRngRE4,                         ///< Bit field DramBaseReg4 RE
+  BFDramRngRE5,                         ///< Bit field DramBaseReg5 RE
+  BFDramRngRE6,                         ///< Bit field DramBaseReg6 RE
+  BFDramRngRE7,                         ///< Bit field DramBaseReg7 RE
+
+  BFDramRngWE0,                         ///< Bit field DramBaseReg0 WE
+  BFDramRngWE1,                         ///< Bit field DramBaseReg1 WE
+  BFDramRngWE2,                         ///< Bit field DramBaseReg2 WE
+  BFDramRngWE3,                         ///< Bit field DramBaseReg3 WE
+  BFDramRngWE4,                         ///< Bit field DramBaseReg4 WE
+  BFDramRngWE5,                         ///< Bit field DramBaseReg5 WE
+  BFDramRngWE6,                         ///< Bit field DramBaseReg6 WE
+  BFDramRngWE7,                         ///< Bit field DramBaseReg7 WE
+
+  BFDramRngDstNode0,                    ///< Bit field Dram Range0 DstNode
+  BFDramRngDstNode1,                    ///< Bit field Dram Range1 DstNode
+  BFDramRngDstNode2,                    ///< Bit field Dram Range2 DstNode
+  BFDramRngDstNode3,                    ///< Bit field Dram Range3 DstNode
+  BFDramRngDstNode4,                    ///< Bit field Dram Range4 DstNode
+  BFDramRngDstNode5,                    ///< Bit field Dram Range5 DstNode
+  BFDramRngDstNode6,                    ///< Bit field Dram Range6 DstNode
+  BFDramRngDstNode7,                    ///< Bit field Dram Range7 DstNode
+
+  BFCSBaseAddr0Reg,                     ///< Bit field CSBaseAddr0Reg
+  BFCSBaseAddr1Reg,                     ///< Bit field CSBaseAddr1Reg
+  BFCSBaseAddr2Reg,                     ///< Bit field CSBaseAddr2Reg
+  BFCSBaseAddr3Reg,                     ///< Bit field CSBaseAddr3Reg
+  BFCSBaseAddr4Reg,                     ///< Bit field CSBaseAddr4Reg
+  BFCSBaseAddr5Reg,                     ///< Bit field CSBaseAddr5Reg
+  BFCSBaseAddr6Reg,                     ///< Bit field CSBaseAddr6Reg
+  BFCSBaseAddr7Reg,                     ///< Bit field CSBaseAddr7Reg
+
+  BFCSMask0Reg,                         ///< Bit field CSMask0Reg
+  BFCSMask1Reg,                         ///< Bit field CSMask1Reg
+  BFCSMask2Reg,                         ///< Bit field CSMask2Reg
+  BFCSMask3Reg,                         ///< Bit field CSMask3Reg
+
+  BFRankDef0,                           ///< Bit field RankDef 0
+  BFRankDef1,                           ///< Bit field RankDef 1
+  BFRankDef2,                           ///< Bit field RankDef 2
+  BFRankDef3,                           ///< Bit field RankDef 3
+
+  BFDramControlReg,                     ///< Bit field DramControlReg
+  BFDramInitRegReg,                     ///< Bit field DramInitRegReg
+  BFDramBankAddrReg,                    ///< Bit field DramBankAddrReg
+  BFDramMRSReg,                         ///< Bit field DramMRSReg
+  BFDramTimingLoReg,                    ///< Bit field DramTimingLoReg
+  BFDramTimingHiReg,                    ///< Bit field DramTimingHiReg
+  BFDramConfigLoReg,                    ///< Bit field DramConfigLoReg
+  BFDramConfigHiReg,                    ///< Bit field DramConfigHiReg
+  BFDctAddlOffsetReg,                   ///< Bit field DctAddlOffsetReg
+  BFDctAddlDataReg,                     ///< Bit field DctAddlDataReg
+  BFDctAccessDone,                      ///< Bit field DctAccessDone
+  BFDctAccessError,                     ///< Bit field DctAccessError
+  BFDctExtraOffsetReg,                  ///< Bit field DctExtraOffsetReg
+  BFDctExtraDataReg,                    ///< Bit field DctExtraDataReg
+  BFDctExtraAccessDone,                 ///< Bit field DctExtraAccessDone
+  BFDramConfigMiscReg,                  ///< Bit field DramConfigMiscReg
+  BFDramCtrlMiscReg2,                   ///< Bit field DramCtrlMiscReg2
+  BFMctCfgHiReg,                        ///< Bit field MctCfgHiReg
+  BFMctCfgLoReg,                        ///< Bit field MctCfgLoReg
+  BFExtMctCfgLoReg,                     ///< Bit field ExtMctCfgLoReg
+  BFExtMctCfgHiReg,                     ///< Bit field ExtMctCfgHiReg
+  BFDcqBwThrotWm,                       ///< Bit field DcqBwThrotWm
+  BFPrefFiveConf,                       ///< Bit field PrefFiveConf
+  BFPrefFourConf,                       ///< Bit field PrefFourConf
+  BFDcqBwThrotWm1,                      ///< Bit field DcqBwThrotWm1
+  BFDcqBwThrotWm2,                      ///< Bit field DcqBwThrotWm2
+
+  BFCSMapCKE,                           ///< Bit field CSMapCKE
+  BFTrdrdBan,                           ///< Bit field TrdrdBan
+  BFTzqcs,                              ///< Bit field Tzqcs
+  BFTzqoper,                            ///< Bit field Tzqoper
+
+  BFDramHoleBase,                       ///< Bit field DramHoleBase
+  BFDramHoleOffset,                     ///< Bit field DramHoleOffset
+  BFDramMemHoistValid,                  ///< Bit field DramMemHoistValid
+  BFDramHtHoleValid,                    ///< Bit field BFDramHtHoleValid
+  BFDramHoleValid,                      ///< Bit field DramHoleValid
+  BFDramBaseAddr,                       ///< Bit field DramBaseAddr
+  BFDramIntlvSel,                       ///< Bit field DramIntlvSel
+  BFDramLimitAddr,                      ///< Bit field DramLimitAddr
+  BFDramIntlvEn,                        ///< Bit field DramIntlvEn
+  BFMemPsSel,                           ///< Bit field MemPsSel
+  BFDctCfgSel,                          ///< Bit field DctCfgSel
+  BFRcvParErr,                          ///< Bit field RcvParErr
+
+  BFDctBaseReg0,                        ///< Bit field DctBaseReg0
+  BFDctBaseReg1,                        ///< Bit field DctBaseReg1
+  BFDctBaseReg2,                        ///< Bit field DctBaseReg2
+  BFDctBaseReg3,                        ///< Bit field DctBaseReg3
+
+  BFDctLimitReg0,                       ///< Bit field DctLimitReg0
+  BFDctLimitReg1,                       ///< Bit field DctLimitReg1
+  BFDctLimitReg2,                       ///< Bit field DctLimitReg2
+  BFDctLimitReg3,                       ///< Bit field DctLimitReg3
+
+  BFDctHighAddressOffsetReg0,           ///< Bit field DctHighAddressOffsetReg0
+  BFDctHighAddressOffsetReg1,           ///< Bit field DctHighAddressOffsetReg1
+  BFDctHighAddressOffsetReg2,           ///< Bit field DctHighAddressOffsetReg2
+  BFDctHighAddressOffsetReg3,           ///< Bit field DctHighAddressOffsetReg3
+
+
+
+  BFIdleCycLowLimit,                    ///< Bit field IdleCycLowLimit
+  BFPendRefPayback,                     ///< Bit field PendRefPayback
+  BFProcOdtDis,                         ///< Bit field ProcOdtDis
+
+
+
+  BFMcaNbCtlReg,                        ///< Bit field McaNbCtlReg
+  BFDramEccEn,                          ///< Bit field DramEccEn
+  BFSyncOnUcEccEn,                      ///< Bit field SyncOnUcEccEn
+  BFEccSymbolSize,                      ///< Bit field EccSymbolSize
+  BFMcaNbStatusLoReg,                   ///< Bit field McaNbStatusLoReg
+  BFMcaNbStatusHiReg,                   ///< Bit field McaNbStatusHiReg
+  BFDramScrub,                          ///< Bit field DramScrub
+  BFL2Scrub,                            ///< Bit field L2Scrub
+  BFDcacheScrub,                        ///< Bit field DcacheScrub
+  BFL3Scrub,                            ///< Bit field L3Scrub
+  BFScrubReDirEn,                       ///< Bit field ScrubReDirEn
+  BFScrubAddrLoReg,                     ///< Bit field ScrubAddrLoReg
+  BFScrubAddrHiReg,                     ///< Bit field ScrubAddrHiReg
+  BFC1ClkDivisor,                       ///< Bit field C1ClkDivisor
+  BFDisDatMsk,                          ///< Bit field DisDatMsk
+  BFNbFid,                              ///< Bit field NbFid
+  BFMTC1eEn,                            ///< Bit field MTC1eEn
+  BFL3Capable,                          ///< Bit field L3Capable
+  BFDisableL3,                          ///< Bit field DisableL3
+  BFEnhMemProtCap,                      ///< Bit field EnhMemProtCap
+  BFNbPsForceReq,                       ///< Bit field NbPsForceReq
+  BFNbPsCtrlDis,                        ///< Bit field NbPsCtrlDis
+  BFNbPsCap,                            ///< Bit field NbPsCap
+
+  BFNonSPDHi,                           ///< Bit field NonSPDHi
+  BFRdPtrInit,                          ///< Bit field RdPtrInit
+  BFAltVidC3MemClkTriEn,                ///< Bit field AltVidC3MemClkTriEn
+  BFDqsRcvEnTrain,                      ///< Bit field DqsRcvEnTrain
+  BFEarlyArbEn,                         ///< Bit field EarlyArbEn
+  BFMaxLatency,                         ///< Bit field either MaxRdLat or MaxAsyncLat
+
+  BFMrsAddress,                         ///< Bit field MrsAddress
+  BFMrsBank,                            ///< Bit field MrsBank
+  BFMrsChipSel,                         ///< Bit field MrsChipSel
+  BFSendPchgAll,                        ///< Bit field SendPchgAll
+  BFSendAutoRefresh,                    ///< Bit field SendAutoRefresh
+  BFSendMrsCmd,                         ///< Bit field SendMrsCmd
+  BFDeassertMemRstX,                    ///< Bit field DeassertMemRstX
+  BFAssertCke,                          ///< Bit field AssertCke
+  BFSendZQCmd,                          ///< Bit field SendZQCmd
+  BFSendCtrlWord,                       ///< Bit field SendCtrlWord
+  BFEnDramInit,                         ///< Bit field EnDramInit
+  BFMrsLevel,                           ///< Bit field MrsLevel
+  BFMrsQoff,                            ///< Bit field MrsQoff
+  BFMrsAddressHi,                       ///< Bit field MrsAddress [17:13]
+
+  BFBurstCtrl,                          ///< Bit field BurstCtrl
+  BFDrvImpCtrl,                         ///< Bit field DrvImpCtrl
+  BFDramTerm_DDR3,                      ///< Bit field DramTerm_DDR3
+  BFDramTermDyn,                        ///< Bit field DramTermDyn
+  BFQoff,                               ///< Bit field Qoff
+  BFASR,                                ///< Bit field ASR
+  BFSRT,                                ///< Bit field SRT
+  BFTcwl,                               ///< Bit field Tcwl
+  BFPchgPDModeSel,                      ///< Bit field PchgPDModeSel
+  BFLowPowerDefault,                    ///< Bit field LowPowerDefault
+
+  BFTwrDDR3,                            ///< Bit field TwrDDR3
+  BFTcl,                                ///< Bit field Tcl
+  BFTrcd,                               ///< Bit field Trcd
+  BFTrp,                                ///< Bit field Trp
+  BFTrtp,                               ///< Bit field Trtp
+  BFTras,                               ///< Bit field Tras
+  BFTrc,                                ///< Bit field Trc
+  BFTwr,                                ///< Bit field Twr
+  BFTrrd,                               ///< Bit field Trrd
+  BFMemClkDis,                          ///< Bit field MemClkDis
+  BFDramTiming0,                        ///< Bit field BFDramTiming0
+  BFDramTiming1,                        ///< Bit field BFDramTiming1
+  BFDramTiming2,                        ///< Bit field BFDramTiming2
+  BFDramTiming3,                        ///< Bit field BFDramTiming3
+  BFDramTiming4,                        ///< Bit field BFDramTiming4
+  BFDramTiming5,                        ///< Bit field BFDramTiming5
+  BFDramTiming6,                        ///< Bit field BFDramTiming6
+  BFDramTiming10,                       ///< Bit field BFDramTiming10
+  BFDramNBP0,                           ///< Bit field BFDramNBP0
+
+  BFNonSPD,                             ///< Bit field NonSPD
+  BFTrwtWB,                             ///< Bit field TrwtWB
+  BFTrwtTO,                             ///< Bit field TrwtTO
+  BFTwtr,                               ///< Bit field Twtr
+  BFTwrrd,                              ///< Bit field Twrrd
+  BFTwrrdHi,                            ///< Bit field TwrrdHi
+  BFTwrwr,                              ///< Bit field Twrwr
+  BFTwrwrHi,                            ///< Bit field TwrwrHi
+  BFTrdrdSD,                            ///< Bit field TrdrdSD
+  BFTwrwrSD,                            ///< Bit field TwrwrSD
+  BFTwrrdSD,                            ///< Bit field TwrrdSD
+  BFTmod,                               ///< Bit field Tmod
+  BFTmrd,                               ///< Bit field Tmrd
+  BFRdOdtTrnOnDly,                      ///< Bit field RdOdtTrnOnDly
+  BFRdOdtOnDuration,                    ///< Bit field RdOdtOnDuration
+  BFWrOdtTrnOnDly,                      ///< Bit field WrOdtTrnOnDly
+  BFWrOdtOnDuration,                    ///< Bit field WrOdtOnDuration
+  BFPrtlChPDDynDly,                     ///< Bit field PrtlChPDDynDly
+
+  BFAggrPDDelay,                        ///< Bit field AggrPDDelay
+  BFPchgPDEnDelay,                      ///< Bit field PchgPDEnDelay
+
+  BFTrdrd,                              ///< Bit field Trdrd
+  BFTrdrdHi,                            ///< Bit field TrdrdHi
+  BFTref,                               ///< Bit field Tref
+  BFDisAutoRefresh,                     ///< Bit field DisAutoRefresh
+  BFTrfc0,                              ///< Bit field Trfc0
+  BFTrfc1,                              ///< Bit field Trfc1
+  BFTrfc2,                              ///< Bit field Trfc2
+  BFTrfc3,                              ///< Bit field Trfc3
+
+  BFInitDram,                           ///< Bit field InitDram
+  BFExitSelfRef,                        ///< Bit field ExitSelfRef
+  BFDramTerm,                           ///< Bit field DramTerm
+  BFParEn,                              ///< Bit field ParEn
+  BFBurstLength32,                      ///< Bit field BurstLength32
+  BFWidth128,                           ///< Bit field Width128
+  BFX4Dimm,                             ///< Bit field X4Dimm
+  BFDimmEccEn,                          ///< Bit field DimmEccEn
+  BFUnBuffDimm,                         ///< Bit field UnBuffDimm
+  BFEnterSelfRef,                       ///< Bit field EnterSelfRef
+  BFDynPageCloseEn,                     ///< Bit field DynPageCloseEn
+  BFIdleCycInit,                        ///< Bit field IdleCycInit
+  BFFreqChgInProg,                      ///< Bit field FreqChgInProg
+  BFForceAutoPchg,                      ///< Bit field ForceAutoPchg
+  BFStagRefEn,                          ///< Bit field StagRefEn
+  BFPendRefPaybackS3En,                 ///< Bit field PendRefPaybackS3En
+  BFEnDispAutoPrecharge,                ///< Bit field EnDispAutoPrecharge
+  BFDisDllShutdownSR,                   ///< Bit field DisDllShutdownSR
+  BFDisSscClkGateData,                  ///< Bit field DisSscClkGateData
+  BFDisSscClkGateCmdAddr,               ///< Bit field DisSscClkGateCmdAddr
+  BFDisSimulRdWr,                       ///< Bit field DisSimulRdWr
+
+  BFMemClkFreq,                         ///< Bit field MemClkFreq
+  BFMemClkFreqVal,                      ///< Bit field MemClkFreqVal
+  BFDdr3Mode,                           ///< Bit field Ddr3Mode
+  BFLegacyBiosMode,                     ///< Bit field LegacyBiosMode
+  BFZqcsInterval,                       ///< Bit field ZqcsInterval
+  BFRDqsEn,                             ///< Bit field RDqsEn
+  BFDisDramInterface,                   ///< Bit field DisDramInterface
+  BFPowerDownEn,                        ///< Bit field PowerDownEn
+  BFPowerDownMode,                      ///< Bit field PowerDownMode
+  BFFourRankSoDimm,                     ///< Bit field FourRankSoDimm
+  BFDcqArbBypassEn,                     ///< Bit field DcqArbBypassEn
+  BFFourRankRDimm,                      ///< Bit field FourRankRDimm
+  BFSlowAccessMode,                     ///< Bit field SlowAccessMode
+  BFBankSwizzleMode,                    ///< Bit field BankSwizzleMode
+  BFDcqBypassMax,                       ///< Bit field DcqBypassMax
+  BFFourActWindow,                      ///< Bit field FourActWindow
+  BFDphyMemPsSelEn,                     ///< Bit field BFDphyMemPsSelEn
+
+  BFODTSEn,                             ///< Bit field ODTSEn
+  BFCmdThrottleMode,                    ///< Bit field CmdThrottleMode
+  BFBwCapEn,                            ///< Bit field BwCapEn
+
+  BFDdr3FourSocketCh,                   ///< Bit field Ddr3FourSocketCh
+  BFSubMemclkRegDly,                    ///< Bit field SubMemclkRegDly
+  BFOdtSwizzle,                         ///< Bit field OdtSwizzle
+  BFProgOdtEn,                          ///< Bit field ProgOdtEn
+  BFCtrlWordCS,                         ///< Bit field CtrlWordCS
+  BFRefChCmdMgtDis,                     ///< Bit field RefChCmdMgtDis
+  BFFastSelfRefEntryDis,                ///< Bit field FastSelfRefEntryDis
+  BFPrtlChPDEnhEn,                      ///< Bit field PrtlChPDEnhEn
+  BFAggrPDEn,                           ///< Bit field AggrPDEn
+  BFDataTxFifoWrDly,                    ///< Bit field DataTxFifoWrDly
+  BFWrDqDqsEarly,                       ///< Bit field WrDqDqsEarly
+  BFCSMux45,                            ///< Bit field CSMux45
+  BFCSMux67,                            ///< Bit field CSMux67
+  BFLrDimmMrsCtrl,                      ///< Bit field LrDimmMrsCtrl
+  BFExtendedParityEn,                   ///< Bit field ExtendedParityEn
+  BFLrDimmEnhRefEn,                     ///< Bit field LrDimmEnhRefEn
+  BFCSTimingMux67,                      ///< Bit field CSTimingMux67
+  BFLrDimmErrOutMonEn,                  ///< Bit field LrDimmErrOutMonEn
+
+  BFIntLvRgnSwapEn,                     ///< Bit field IntLvRgnSwapEn
+  BFIntLvRgnBaseAddr,                   ///< Bit field IntLvRgnBaseAddr
+  BFIntLvRgnLmtAddr,                    ///< Bit field IntLvRgnLmtAddr
+  BFIntLvRgnSize,                       ///< Bit field IntLvRgnSize
+
+  BFDctSelHiRngEn,                      ///< Bit field DctSelHiRngEn
+  BFDctSelHi,                           ///< Bit field DctSelHi
+  BFDctSelIntLvEn,                      ///< Bit field DctSelIntLvEn
+  BFMemClrInit,                         ///< Bit field MemClrInit
+  BFDctGangEn,                          ///< Bit field DctGangEn
+  BFDctDatIntLv,                        ///< Bit field DctDatIntLv
+  BFDctSelIntLvAddr,                    ///< Bit field DctSelIntLvAddr
+  BFDctSelIntLvAddrHi,                  ///< Bit field DctSelIntLvAddrHi
+  BFParallelMemClrEn,                   ///< Bit field ParallelMemClrEn
+  BFDramEnabled,                        ///< Bit field DramEnabled
+  BFMemClrBusy,                         ///< Bit field MemClrBusy
+  BFMemCleared,                         ///< Bit field MemCleared
+  BFDctSelBaseAddr,                     ///< Bit field DctSelBaseAddr
+  BFDctSelBaseOffset,                   ///< Bit field DctSelBaseOffset
+  BFDctSelBankSwap,                     ///< Bit field DctSelBankSwap
+
+  BFAdapPrefMissRatio,                  ///< Bit field AdapPrefMissRatio
+  BFAdapPrefPosStep,                    ///< Bit field AdapPrefPosStep
+  BFAdapPrefNegStep,                    ///< Bit field AdapPrefNegStep
+  BFCohPrefPrbLmt,                      ///< Bit field CohPrefPrbLmt
+
+  BFFlushWrOnS3StpGnt,                  ///< Bit field FlushWrOnS3StpGnt
+
+  BFPrefDramTrainDone,                  ///< Bit field PrefDramTrainDone
+  BFWrDramTrainMode,                    ///< Bit field WrDramTrainMode
+  BFMctPrefReqLimit,                    ///< Bit field MctPrefReqLimit
+  BFPrefDramTrainMode,                  ///< Bit field PrefDramTrainMode
+  BFDctWrLimit,                         ///< Bit field DctWrLimit
+  BFMctWrLimit,                         ///< Bit field MctWrLimit
+  BFDramTrainPdbDis,                    ///< Bit field DramTrainPdbDis
+  BFTrainLength,                        ///< Bit field TrainLength
+  BFRdTrainGo,                          ///< Bit field RdTrainGo
+  BFWrTrainGo,                          ///< Bit field WrTrainGo
+  BFWrTrainAdrPtrLo,                    ///< Bit field WrTrainAdrPtrLo
+  BFWrTrainAdrPtrHi,                    ///< Bit field WrTrainAdrPtrHi
+  BFWrTrainBufAddr,                     ///< Bit field WrTrainBufAddr
+  BFWrTrainBufDat,                      ///< Bit field WrTrainBufDat
+  BFFlushWr,                            ///< Bit field FlushWr
+  BFFlushWrOnStpGnt,                    ///< Bit field FlushWrOnStpGnt
+  BFPrefCpuDis,                         ///< Bit field PrefCpuDis
+  BFPrefIoDis,                          ///< Bit field PrefIoDis
+  BFTrainCmpSts,                        ///< Bit field TrainCmpSts
+  BFTrainCmpSts2,                       ///< Bit field TrainCmpSts2
+  BFTcbModeEn,                          ///< Bit field TcbModeEn
+  BFTraceModeEn,                        ///< Bit field TraceModeEn
+
+  BFAddrCmdDrvStren,                    ///< Bit field AddrCmdDrvStren
+  BFDataDrvStren,                       ///< Bit field DataDrvStren
+  BFCkeDrvStren,                        ///< Bit field CkeDrvStren
+  BFCsOdtDrvStren,                      ///< Bit field CsOdtDrvStren
+  BFClkDrvStren,                        ///< Bit field ClkDrvStren
+  BFDqsDrvStren,                        ///< Bit field DqsDrvStren
+  BFProcOdt,                              ///< Bit field ProcOdt
+  BFODCControl,                         ///< Bit field ODCControl
+  BFAddrTmgControl,                     ///< Bit field AddrTmgControl
+  BFAddrCmdFineDelay,                   ///< Bit field AddrCmdFineDelay
+
+  BFWrtLvTrEn,                          ///< Bit field WrtLvTrEn
+  BFWrtLvTrMode,                        ///< Bit field WrtLvTrMode
+  BFPhyFenceTrEn,                       ///< Bit field PhyFenceTrEn
+  BFTrDimmSel,                          ///< Bit field TrDimmSel
+  BFTrNibbleSel,                        ///< Bit field TrNibbleSel
+  BFFenceTrSel,                         ///< Bit field FenceTrSel
+  BFWrLvOdt,                            ///< Bit field WrLvOdt
+  BFWrLvOdtEn,                          ///< Bit field WrLvOdtEn
+  BFDqsRcvTrEn,                         ///< Bit field DqsRcvTrEn
+  BFDisAutoComp,                        ///< Bit field DisAutoComp
+  BFWrtLvErr,                           ///< Bit field WrtLvErr
+  BFODTAssertionCtl,                    ///< Bit field ODTAssertionCtl
+  BFNibbleTrainModeEn,                  ///< Bit field NibbleTrainModeEn
+  BFRankTrainModeEn,                    ///< Bit field RankTrainModeEn
+  BFPllMult,                            ///< Bit field PllMult
+  BFPllDiv,                             ///< Bit field PllDiv
+  BFDramPhyCtlReg,                      ///< Bit field Dram Phy Control Register
+
+  BFDramPhyStatusReg,                   ///< Bit field DramPhyStatusReg
+
+  BFD3Cmp2PCal,                         ///< Bit field D3Cmp2PCal
+  BFD3Cmp2NCal,                         ///< Bit field D3Cmp2NCal
+  BFD3Cmp1PCal,                         ///< Bit field D3Cmp1PCal
+  BFD3Cmp1NCal,                         ///< Bit field D3Cmp1NCal
+  BFD3Cmp0PCal,                         ///< Bit field D3Cmp0PCal
+  BFD3Cmp0NCal,                         ///< Bit field D3Cmp0NCal
+
+  BFPhyFence,                           ///< Bit field PhyFence
+  BFODTTri,                             ///< Bit field ODTTri
+  BFCKETri,                             ///< Bit field CKETri
+  BFChipSelTri,                         ///< Bit field ChipSelTri
+  BFPhyRODTCSLow,                       ///< Bit field PhyRODTCSLow
+  BFPhyRODTCSHigh,                      ///< Bit field PhyRODTCSHigh
+  BFPhyWODTCSLow,                       ///< Bit field PhyWODTCSLow
+  BFPhyWODTCSHigh,                      ///< Bit field PhyWODTCSHigh
+  BFUSPLLCtlAll,                        ///< Bit field USPLLCtlAll
+  BFDSPLLCtlAll,                        ///< Bit field DSPLLCtlAll
+  BFUSNibbleAlignEn,                    ///< Bit field USNibbleAlignEn
+  BFChnLinitClkEn,                      ///< Bit field ChnLinitClkEn
+
+  BFTSLinkSelect,                       ///< Bit field TSLinkSelect
+  BFTS2BitLockEn,                       ///< Bit field TS2BitLockEn
+  BFTS2En,                              ///< Bit field TS2En
+  BFTS1En,                              ///< Bit field TS1En
+  BFTS0LinkStarEn,                      ///< Bit field TS0LinkStarEn
+  BFTS0En,                              ///< Bit field TS0En
+
+  BFLinkTrainData,                      ///< Bit field LinkTrainData
+
+  BFRstRxFifoPtrs,                      ///< Bit field RstRxFifoPtrs
+  BFRxFifoPtrInit,                      ///< Bit field RxFifoPtrInit
+  BFRstTxFifoPtrs,                      ///< Bit field RstTxFifoPtrs
+  BFTxFifoPtrInit,                      ///< Bit field TxFifoPtrInit
+
+  BFLpbkCount,                          ///< Bit field LpbkCount
+  BFLpbkMap,                            ///< Bit field LpbkMap
+  BFSendLpbkMaintCmd,                   ///< Bit field SendLpbkMaintCmd
+  BFLpbkData,                           ///< Bit field LpbkData
+
+  BFMbRdPtrEn,                          ///< Bit field MbRdPtrEn
+  BFLnkLpBkLat,                         ///< Bit field LnkLpBkLat
+  BFLpbkRndTripLatDone,                 ///< Bit field LpbkRndTripLatDone
+  BFLnkLatTrainEn,                      ///< Bit field LnkLatTrainEn
+
+  BFDsPhyReset,                         ///< Bit field DsPhyReset
+  BFLinkReset,                          ///< Bit field LinkReset
+
+  BFPllLockTime,                        ///< Bit field PllLockTime
+  BFPllRegWaitTime,                     ///< Bit field PllRegWaitTime
+  BFNclkFreqDone,                       ///< Bit field NclkFreqDone
+  BFNbPs0NclkDiv,                       ///< Bit field NbPs0NclkDiv
+  BFNbPs1NclkDiv,                       ///< Bit field NbPs1NclkDiv
+  BFNbPsCsrAccSel,                      ///< Bit field NbPsCsrAccSel
+  BFNbPsDbgEn,                          ///< Bit field NbPsDbgEn
+  BFNclkRampWithDllRelock,              ///< Bit field NclkRampWithDllRelock
+
+  BFOnLineSpareControl,                 ///< Bit field OnLineSpareControl
+  BFDdrMaxRate,                         ///< Bit field DdrMaxRate
+
+  BFPhyDctCfgSelMode,                   ///< Bit field PhyDctCfgSelMode
+  BFNbPstateDis,                        ///< Bit field NbPstateDis
+  BFNbPsSel,                            ///< Bit field NbPsSel
+  BFNbPstateCtlReg,                     ///< Bit field NB Pstate Control register
+  BFSwNbPstateLoDis,                    ///< Bit field SwNbPstateLoDis
+  BFNbPstateLo,                         ///< Bit field NbPstateLo
+  BFNbPstateHi,                         ///< Bit field NbPstateHi
+  BFNbPstateMaxVal,                     ///< Bit field NbPstateMaxVal
+  BFCurNbPstate,                        ///< Bit field NbCurNbPstate
+
+  BFC6Base,                             ///< Bit field C6Base
+  BFC6DramLock,                         ///< Bit field C6DramLock
+  BFCC6SaveEn,                          ///< Bit field CC6SaveEn
+  BFCoreStateSaveDestNode,              ///< Bit field CoreStateSaveDestNode
+
+  BFRxPtrInitReq,                       ///< Bit field RxPtrInitReq
+  BFAddrCmdTriEn,                       ///< Bit field AddrCmdTriEn
+  BFForceCasToSlot0,                    ///< Bit field ForceCasToSlot0
+  BFDisCutThroughMode,                  ///< Bit field DisCutThroughMode
+  BFDbeSkidBufDis,                      ///< Bit field DbeSkidBufDis
+  BFDbeGskMemClkAlignMode,              ///< Bit field DbeGskMemClkAlignMode
+  BFEnCpuSerRdBehindNpIoWr,             ///< Bit field EnCpuSerRdBehindNpIoWr
+  BFDRAMPhyDLLControl,                  ///< Bit field DRAMPhyDLLControl
+  BFRxDLLWakeupTime,                    ///< Bit field RxDllWakeupTime
+  BFRxCPUpdPeriod,                      ///< Bit field RxCPUpdPeriod
+  BFRxMaxDurDllNoLock,                  ///< Bit field RxMaxDurDllNoLock
+  BFTxDLLWakeupTime,                    ///< Bit field TxDllWakeupTime
+  BFTxCPUpdPeriod,                      ///< Bit field TxCPUpdPeriod
+  BFTxMaxDurDllNoLock,                  ///< Bit field TxMaxDurDllNoLock
+  BFEnRxPadStandby,                     ///< Bit field EnRxPadStandby
+  BFMaxSkipErrTrain,                    ///< Bit field MaxSkipErrTrain
+  BFSlotSel,                            ///< Bit field SlotSel
+  BFSlot1ExtraClkEn,                    ///< Bit field Slot1ExtraClkEn
+  BFPtrInitReq,                         ///< Bit field PtrInitReq
+  BFChanVal,                            ///< Bit field ChanVal
+
+  BFMemTempHot,                         ///< Bit field MemTempHot
+  BFDoubleTrefRateEn,                   ///< Bit field DoubleTrefRateEn
+
+  BFAcpiPwrStsCtrlHi,                   ///< Bit field BFAcpiPwrStsCtrlHi
+  BFDramSrHysEn,                        ///< Bit field BFDramSrHysEn
+  BFDramSrHys,                          ///< Bit field BFDramSrHys
+  BFMemTriStateEn,                      ///< Bit field BFMemTriStateEn
+  BFDramSrEn,                           ///< Bit field BFDramSrEn
+
+  BFDeassertCke,                        ///< Bit field BFDeassertCke
+  BFFourRankRDimm0,                     ///< Bit field BFFourRankRDimm0
+  BFFourRankRDimm1,                     ///< Bit field BFFourRankRDimm1
+  BFTwrwrSdSc,                          ///< Bit field BFTwrwrSdSc
+  BFTwrwrSdDc,                          ///< Bit field BFTwrwrSdDc
+  BFTwrwrDd,                            ///< Bit field BFTwrwrDd
+  BFTrdrdSdSc,                          ///< Bit field BFTrdrdSdSc
+  BFTrdrdSdDc,                          ///< Bit field BFTrdrdSdDc
+  BFTrdrdDd,                            ///< Bit field BFTrdrdDd
+  BFTstag0,                             ///< Bit field BFTstag0
+  BFTstag1,                             ///< Bit field BFTstag1
+  BFTstag2,                             ///< Bit field BFTstag2
+  BFTstag3,                             ///< Bit field BFTstag3
+
+  BFDataPatGenSel,                      ///< Bit field DataPatGenSel
+  BFActPchgGenEn,                       ///< Bit field ActPchgGenEn
+  BFShmooRdDqsDly,                      ///< Bit field ShmooRdDqsDly
+
+  BFCmdSendInProg,                      ///< Bit field CmdSendInProg
+  BFSendCmd,                            ///< Bit field SendCmd
+  BFTestStatus,                         ///< Bit field TestStatus
+  BFCmdTgt,                             ///< Bit field CmdTgt
+  BFCmdType,                            ///< Bit field CmdType
+  BFStopOnErr,                          ///< Bit field StopOnErr
+  BFResetAllErr,                        ///< Bit field ResetAllErr
+  BFCmdTestEnable,                      ///< Bit field CmdTestEnable
+  BFTgtChipSelectA,                     ///< Bit field TgtChipSelectA
+  BFTgtBankA,                           ///< Bit field TgtBankA
+  BFTgtAddressHiA,                      ///< Bit field TgtAddressHiA
+  BFTgtAddressA,                        ///< Bit field TgtAddressA
+  BFTgtChipSelectB,                     ///< Bit field TgtChipSelectB
+  BFTgtBankB,                           ///< Bit field TgtBankB
+  BFTgtAddressHiB,                      ///< Bit field TgtAddressHiB
+  BFTgtAddressB,                        ///< Bit field TgtAddressB
+  BFBubbleCnt2,                         ///< Bit field BubbleCnt2
+  BFBubbleCnt,                          ///< Bit field BubbleCnt
+  BFCmdStreamLen,                       ///< Bit field CmdStreamLen
+  BFCmdCount,                           ///< Bit field CmdCount
+  BFErrDqNum,                           ///< Bit field ErrDQNum
+  BFErrCnt,                             ///< Bit field ErrCnt
+  BFNibbleErrSts,                       ///< Bit field NibbleErrSts
+  BFNibbleErr180Sts,                    ///< Bit field NibbleErr180Sts
+  BFDataPrbsSeed,                       ///< Bit field DataPrbsSeed
+  BFDramDqMaskLow,                      ///< Bit field DramDqMaskLow
+  BFDramDqMaskHigh,                     ///< Bit field DramDqMaskHigh
+  BFDramEccMask,                        ///< Bit field DramEccMask
+  BFDQPatOvrEn0,                        ///< Bit field DQPatOvrEn0
+  BFDQPatOvrEn1,                        ///< Bit field DQPatOvrEn1
+  BFXorPatOvr,                          ///< Bit field XorPatOvr
+  BFPatOvrVal,                          ///< Bit field PatOvrVal
+  BFEccPatOvrEn,                        ///< Bit field EccPatOvrEn
+  BFSendActCmd,                         ///< Bit field SendActCmd
+  BFSendPchgCmd,                        ///< Bit field SendPchgCmd
+  BFCmdChipSelect,                      ///< Bit field CmdChipSelect
+  BFCmdBank,                            ///< Bit field CmdBank
+  BFCmdAddress,                         ///< Bit field CmdAddress
+  BFErrBeatNum,                         ///< Bit Field ErrBeatNum
+  BFErrCmdNum,                          ///< Bit field BFErrCmdNum
+  BFDQErrLow,                           ///< Bit field DQSErrLow
+  BFDQErrHigh,                          ///< Bit field DQSErrHigh
+  BFEccErr,                             ///< Bit field EccErr
+  BFFastMstateDis,                      ///< Bit field FastMstateDis
+  BFDramUserDataPattern0,               ///< Bit field DramUserDataPattern0
+  BFDramUserDataPattern1,               ///< Bit field DramUserDataPattern1
+  BFDramUserDataPattern2,               ///< Bit field DramUserDataPattern2
+  BFDramUserDataPattern3,               ///< Bit field DramUserDataPattern3
+  BFActPchgSeq,                         ///< Bit field ActPchgSeq
+  BFActPchgCmdMin,                      ///< Bit field ActPchgCmdMin
+  BFDramCommandReg4,                    ///< Bit field DramCommandReg4
+  BFDramCommandReg5,                    ///< Bit field DramCommandReg5
+  BFNibbleErrStsSel,                    ///< Bit field NibbleErrStsSel
+  BFErrStsDly,                          ///< Bit field ErrStsDly
+  BFErrStsDly180,                       ///< Bit field ErrStsDly180
+
+  /* Bit fields for workarounds */
+  BFErr263,                             ///< Bit field Err263
+  BFErr350,                             ///< Bit field Err350
+  BFErr322I,                            ///< Bit field Err322I
+  BFErr322II,                           ///< Bit field Err322II
+  BFErratum468WorkaroundNotRequired,    ///< Bit field Erratum468WorkaroundNotRequired
+
+  /* Bit fields for Phy */
+  BFEccDLLConf,                         ///< Bit field EccDLLConf
+  BFProcOdtAdv,                         ///< Bit field ProcOdtAdv
+  BFEccDLLPwrDnConf,                    ///< Bit field EccDLLPwrDnConf
+  BFPhyPLLLockTime,                     ///< Bit field PhyPLLLockTime
+  BFPhyDLLLockTime,                     ///< Bit field PhyDLLLockTime
+  BFSkewMemClk,                         ///< Bit field SkewMemClk
+  BFPhyDLLControl,                      ///< Bit field BFPhyDLLControl
+  BFPhy0x0D080F0C,                      ///< Bit field BFPhy0x0D080F0C
+  BFPhy0x0D080F10,                      ///< Bit field BFPhy0x0D080F10
+  BFPhy0x0D080F11,                      ///< Bit field BFPhy0x0D080F11
+  BFPhy0x0D088F30,                      ///< Bit field BFPhy0x0D088F30
+  BFPhy0x0D08C030,                      ///< Bit field BFPhy0x0D08C030
+  BFPhy0x0D082F30,                      ///< Bit field BFPhy0x0D082F30
+  BFDiffTimingEn,                       ///< Bit Field DiffTimingEn
+  BFFence,                              ///< Bit Field Fence
+  BFDelay,                              ///< Bit Field Delay
+  BFFenceValue,                         ///< Bit Field FenceValue
+
+  BFPhy0x0D040F3E,                      ///< Bit field BFPhy0x0D040F3E
+  BFPhy0x0D042F3E,                      ///< Bit field BFPhy0x0D042F3E
+  BFPhy0x0D048F3E,                      ///< Bit field BFPhy0x0D048F3E
+  BFPhy0x0D04DF3E,                      ///< Bit field BFPhy0x0D04DF3E
+
+  BFPhyClkDllFine0,                   ///< Bit field ClkDllFineDly 0
+  BFPhyClkDllFine1,                   ///< Bit field ClkDllFineDly 1
+
+  BFPhyClkConfig0,                    ///< Bit field ClkConfig0
+  BFPhyClkConfig1,                    ///< Bit field ClkConfig1
+  BFPhyClkConfig2,                    ///< Bit field ClkConfig2
+  BFPhyClkConfig3,                    ///< Bit field ClkConfig3
+
+  BFPhy0x0D0F0F13,                      ///< Bit field BFPhy0x0D0F0F13
+  BFPhy0x0D0F0F13Bit0to7,               ///< Bit field BFPhy0x0D0F0F13Bit0to7
+  BFPhy0x0D0F0830,                      ///< Bit field BFPhy0x0D0F0830
+  BFPhy0x0D07812F,                      ///< Bit field BFPhy0x0D0F8108
+
+  BFDataRxVioLvl,                       ///< Bit field DataRxVioLvl
+  BFClkRxVioLvl,                        ///< Bit field ClkRxVioLvl
+  BFCmdRxVioLvl,                        ///< Bit field CmdRxVioLvl
+  BFAddrRxVioLvl,                       ///< Bit field AddrRxVioLvl
+  BFCmpVioLvl,                          ///< Bit field CmpVioLvl
+  BFCsrComparator,                      ///< Bit field CsrComparator
+  BFAlwaysEnDllClks,                    ///< Bit field AlwaysEnDllClks
+  BFPhy0x0D0FE00A,                      ///< Bit field Phy0x0D0FE00A
+  BFPllPdMode,                          ///< Bit fields SelCsrPllPdMode and CsrPhySrPllPdMode
+
+  BFDataFence2,                         ///< Bit field DataFence2
+  BFClkFence2,                          ///< Bit field ClkFence2
+  BFCmdFence2,                          ///< Bit field CmdFence2
+  BFAddrFence2,                         ///< Bit field AddrFence2
+
+  BFDataByteDMConf,                     ///< Bit field DataByteDMConf
+
+  BFAddrCmdTri,                         ///< Bit field BFAddrCmdTri
+  BFLowPowerDrvStrengthEn,              ///< Bit field BFLowPowerDrvStrengthEn
+  BFLevel,                              ///< Bit field Level
+
+  BFDbeGskFifoNumerator,                ///< Bit field DbeGskFifoNumerator
+  BFDbeGskFifoDenominator,              ///< Bit field DbeGskFifoDenominator
+  BFDataTxFifoSchedDlyNegSlot0,         ///< Bit field DataTxFifoSchedDlyNegSlot0
+  BFDataTxFifoSchedDlyNegSlot1,         ///< Bit field DataTxFifoSchedDlyNegSlot1
+  BFDataTxFifoSchedDlySlot0,            ///< Bit field DataTxFifoSchedDlySlot0
+  BFDataTxFifoSchedDlySlot1,            ///< Bit field DataTxFifoSchedDlySlot1
+
+  BFDisablePredriverCal,                ///< Bit field DisablePredriverCal
+  BFDataByteTxPreDriverCal,             ///< Bit field DataByteTxPreDriverCal
+  BFDataByteTxPreDriverCal2Pad1,        ///< Bit field DataByteTxPreDriverCal2Pad1
+  BFDataByteTxPreDriverCal2Pad2,        ///< Bit field DataByteTxPreDriverCal2Pad2
+  BFCmdAddr0TxPreDriverCal2Pad1,        ///< Bit field CmdAddr0TxPreDriverCal2Pad1
+  BFCmdAddr0TxPreDriverCal2Pad2,        ///< Bit field CmdAddr0TxPreDriverCal2Pad2
+  BFCmdAddr1TxPreDriverCal2Pad1,        ///< Bit field CmdAddr1TxPreDriverCal2Pad1
+  BFCmdAddr1TxPreDriverCal2Pad2,        ///< Bit field CmdAddr1TxPreDriverCal2Pad2
+  BFAddrTxPreDriverCal2Pad1,            ///< Bit field AddrTxPreDriverCal2Pad1
+  BFAddrTxPreDriverCal2Pad2,            ///< Bit field AddrTxPreDriverCal2Pad2
+  BFAddrTxPreDriverCal2Pad3,            ///< Bit field AddrTxPreDriverCal2Pad3
+  BFAddrTxPreDriverCal2Pad4,            ///< Bit field AddrTxPreDriverCal2Pad4
+  BFCmdAddr0TxPreDriverCalPad0,         ///< Bit field CmdAddr0TxPreDriverCalPad0
+  BFCmdAddr1TxPreDriverCalPad0,         ///< Bit field CmdAddr1TxPreDriverCalPad0
+  BFAddrTxPreDriverCalPad0,             ///< Bit field AddrTxPreDriverCalPad0
+  BFClock0TxPreDriverCalPad0,           ///< Bit field Clock0TxPreDriverCalPad0
+  BFClock1TxPreDriverCalPad0,           ///< Bit field Clock1TxPreDriverCalPad0
+  BFClock2TxPreDriverCalPad0,           ///< Bit field Clock2TxPreDriverCalPad0
+  BFPNOdtCal,                           ///< Bit field P/NOdtCal
+  BFPNDrvCal,                           ///< Bit field P/NDrvCal
+  BFCalVal,                             ///< Bit field CalVal
+  BFPStateToAccess,                     ///< Bit field PStateToAccess
+  BFCmpDebugPortConfig,                 ///< Bit Field for CMP Debug port config
+
+  BFTxp,                                ///< Bit field Txp
+  BFTxpdll,                             ///< Bit field Txpdll
+  BFDramPwrMngm1Reg,                    ///< Bit field DRAM Power Management 1 register
+  BFL3ScrbRedirDis,                     ///< Bit field L3ScrbRedirDis
+  BFDQOdt03,                            ///< Bit field DQ Odt 0-3
+  BFDQOdt47,                            ///< Bit field DQ Odt 4-7
+  BFTriDM,                              ///< Bit field TriDM
+
+  BFTcksrx,                             ///< Bit field Tcksrx
+  BFTcksre,                             ///< Bit field Tcksre
+  BFTckesr,                             ///< Bit field Tckesr
+  BFTpd,                                ///< Bit field Tpd
+
+  BFFixedErrataSkipPorFreqCap,          ///< Bit field FixedErrataSkipPorFreqCap
+  BFPerRankTimingEn,                    ///< Bit field PerRankTimingEn
+  BFMemPhyPllPdMode,                    ///< Bit field MemPhyPllPdMode
+  BFBankSwap,                           ///< Bit field BankSwap
+  BFBwCapCmdThrottleMode,               ///< Bit field BwCapCmdThrottleMode
+  BFRxChMntClkEn,                       ///< Bit field RxChMntClkEn
+  BFBlockRxDqsLock,                      ///< Bit field BlockRxDqsLock
+  BFRxSsbMntClkEn,                      ///< Bit field RxSsbMntClkEn
+  BFPhyPSMasterChannel,                 ///< Bit field PhyPSMasterChannel
+
+  BFVrefSel,                             ///< Bit field VrefSel
+  BFVrefDAC,                             ///< Bit field VrefDAC
+  BFDataByteRxDqsDLLDimm0Lane0,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 0
+  BFDataByteRxDqsDLLDimm0Lane1,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 1
+  BFDataByteRxDqsDLLDimm0Lane2,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 2
+  BFDataByteRxDqsDLLDimm0Lane3,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 3
+  BFDataByteRxDqsDLLDimm0Lane4,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 4
+  BFDataByteRxDqsDLLDimm0Lane5,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 5
+  BFDataByteRxDqsDLLDimm0Lane6,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 6
+  BFDataByteRxDqsDLLDimm0Lane7,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 7
+  BFDataByteRxDqsDLLDimm0Lane8,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 8
+  BFDataByteRxDqsDLLDimm0Lane9,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane 9
+  BFDataByteRxDqsDLLDimm0LaneA,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane A
+  BFDataByteRxDqsDLLDimm0LaneB,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane B
+  BFDataByteRxDqsDLLDimm0LaneC,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane C
+  BFDataByteRxDqsDLLDimm0LaneD,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane D
+  BFDataByteRxDqsDLLDimm0LaneE,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane E
+  BFDataByteRxDqsDLLDimm0LaneF,          ///< Bit field DataByteRxDqsDLL DIMM0 Lane F
+  BFDataByteRxDqsDLLDimm0Lane10,         ///< Bit field DataByteRxDqsDLL DIMM0 Lane 10
+  BFDataByteRxDqsDLLDimm0Lane11,         ///< Bit field DataByteRxDqsDLL DIMM0 Lane 11
+  BFDataByteRxDqsDLLDimm0Broadcast,      ///< Bit field DataByteRxDqsDLL DIMM0 Broadcast
+  BFDataByteRxDqsDLLDimm1Lane0,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 0
+  BFDataByteRxDqsDLLDimm1Lane1,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 1
+  BFDataByteRxDqsDLLDimm1Lane2,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 2
+  BFDataByteRxDqsDLLDimm1Lane3,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 3
+  BFDataByteRxDqsDLLDimm1Lane4,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 4
+  BFDataByteRxDqsDLLDimm1Lane5,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 5
+  BFDataByteRxDqsDLLDimm1Lane6,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 6
+  BFDataByteRxDqsDLLDimm1Lane7,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 7
+  BFDataByteRxDqsDLLDimm1Lane8,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 8
+  BFDataByteRxDqsDLLDimm1Lane9,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane 9
+  BFDataByteRxDqsDLLDimm1LaneA,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane A
+  BFDataByteRxDqsDLLDimm1LaneB,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane B
+  BFDataByteRxDqsDLLDimm1LaneC,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane C
+  BFDataByteRxDqsDLLDimm1LaneD,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane D
+  BFDataByteRxDqsDLLDimm1LaneE,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane E
+  BFDataByteRxDqsDLLDimm1LaneF,          ///< Bit field DataByteRxDqsDLL DIMM1 Lane F
+  BFDataByteRxDqsDLLDimm1Lane10,         ///< Bit field DataByteRxDqsDLL DIMM1 Lane 10
+  BFDataByteRxDqsDLLDimm1Lane11,         ///< Bit field DataByteRxDqsDLL DIMM1 Lane 11
+  BFDataByteRxDqsDLLDimm1Broadcast,      ///< Bit field DataByteRxDqsDLL DIMM1 Broadcast
+  BFDataByteRxDqsDLLDimm2Lane0,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 0
+  BFDataByteRxDqsDLLDimm2Lane1,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 1
+  BFDataByteRxDqsDLLDimm2Lane2,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 2
+  BFDataByteRxDqsDLLDimm2Lane3,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 3
+  BFDataByteRxDqsDLLDimm2Lane4,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 4
+  BFDataByteRxDqsDLLDimm2Lane5,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 5
+  BFDataByteRxDqsDLLDimm2Lane6,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 6
+  BFDataByteRxDqsDLLDimm2Lane7,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 7
+  BFDataByteRxDqsDLLDimm2Lane8,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 8
+  BFDataByteRxDqsDLLDimm2Lane9,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane 9
+  BFDataByteRxDqsDLLDimm2LaneA,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane A
+  BFDataByteRxDqsDLLDimm2LaneB,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane B
+  BFDataByteRxDqsDLLDimm2LaneC,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane C
+  BFDataByteRxDqsDLLDimm2LaneD,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane D
+  BFDataByteRxDqsDLLDimm2LaneE,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane E
+  BFDataByteRxDqsDLLDimm2LaneF,          ///< Bit field DataByteRxDqsDLL DIMM2 Lane F
+  BFDataByteRxDqsDLLDimm2Lane10,         ///< Bit field DataByteRxDqsDLL DIMM2 Lane 10
+  BFDataByteRxDqsDLLDimm2Lane11,         ///< Bit field DataByteRxDqsDLL DIMM2 Lane 11
+  BFDataByteRxDqsDLLDimm2Broadcast,      ///< Bit field DataByteRxDqsDLL DIMM2 Broadcast
+  BFDataByteRxDqsDLLDimm3Lane0,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 0
+  BFDataByteRxDqsDLLDimm3Lane1,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 1
+  BFDataByteRxDqsDLLDimm3Lane2,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 2
+  BFDataByteRxDqsDLLDimm3Lane3,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 3
+  BFDataByteRxDqsDLLDimm3Lane4,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 4
+  BFDataByteRxDqsDLLDimm3Lane5,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 5
+  BFDataByteRxDqsDLLDimm3Lane6,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 6
+  BFDataByteRxDqsDLLDimm3Lane7,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 7
+  BFDataByteRxDqsDLLDimm3Lane8,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 8
+  BFDataByteRxDqsDLLDimm3Lane9,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane 9
+  BFDataByteRxDqsDLLDimm3LaneA,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane A
+  BFDataByteRxDqsDLLDimm3LaneB,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane B
+  BFDataByteRxDqsDLLDimm3LaneC,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane C
+  BFDataByteRxDqsDLLDimm3LaneD,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane D
+  BFDataByteRxDqsDLLDimm3LaneE,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane E
+  BFDataByteRxDqsDLLDimm3LaneF,          ///< Bit field DataByteRxDqsDLL DIMM3 Lane F
+  BFDataByteRxDqsDLLDimm3Lane10,         ///< Bit field DataByteRxDqsDLL DIMM3 Lane 10
+  BFDataByteRxDqsDLLDimm3Lane11,         ///< Bit field DataByteRxDqsDLL DIMM3 Lane 11
+  BFDataByteRxDqsDLLDimm3Broadcast,      ///< Bit field DataByteRxDqsDLL DIMM3 Broadcast
+  BFDataByteDllPowerMgnByte0,           ///< Bit field DataByteDllPowerManagement for Byte 0
+  BFDataByteDllPowerMgnByte1,           ///< Bit field DataByteDllPowerManagement for Byte 1
+  BFDataByteDllPowerMgnByte2,           ///< Bit field DataByteDllPowerManagement for Byte 2
+  BFDataByteDllPowerMgnByte3,           ///< Bit field DataByteDllPowerManagement for Byte 3
+  BFDataByteDllPowerMgnByte4,           ///< Bit field DataByteDllPowerManagement for Byte 4
+  BFDataByteDllPowerMgnByte5,           ///< Bit field DataByteDllPowerManagement for Byte 5
+  BFDataByteDllPowerMgnByte6,           ///< Bit field DataByteDllPowerManagement for Byte 6
+  BFDataByteDllPowerMgnByte7,           ///< Bit field DataByteDllPowerManagement for Byte 7
+  BFDataByteDllPowerMgnByte8,           ///< Bit field DataByteDllPowerManagement for Byte ECC
+  BFDataByteDllPowerMgnByteAll,         ///< Bit field DataByteDllPowerManagement for all bytes
+  BFIoSkewMode,                         ///< Bit field for IoSkewMode
+  BFLfsrRollOver,                       ///< Bit field for LfsrRollOver
+  BFM1MemClkFreq,                       ///< Bit field M1MemClkFreq
+  BFRate,                               ///< Bit field Rate
+  BFFence2,                             ///< Bit field Fence2
+
+  BFNbVid0,                             ///< Bit field NbVid for NB Pstate 0
+  BFNbVid0Hi,                           ///< Bit field 7th bit of NbVid for NB Pstate 0
+  BFNbVid1,                             ///< Bit field NbVid for NB Pstate 1
+  BFNbVid1Hi,                           ///< Bit field 7th bit of NbVid for NB Pstate 1
+  BFNbVid2,                             ///< Bit field NbVid for NB Pstate 2
+  BFNbVid2Hi,                           ///< Bit field 7th bit of NbVid for NB Pstate 2
+  BFNbVid3,                             ///< Bit field NbVid for NB Pstate 3
+  BFNbVid3Hi,                           ///< Bit field 7th bit of NbVid for NB Pstate 3
+
+  BFMemPstate0,                         ///< Bit field MemPstate for NB Pstate 0
+  BFMemPstate1,                         ///< Bit field MemPstate for NB Pstate 1
+  BFMemPstate2,                         ///< Bit field MemPstate for NB Pstate 2
+  BFMemPstate3,                         ///< Bit field MemPstate for NB Pstate 3
+  BFMemPstateDis,                       ///< Bit field MemPstateDis
+  BFMultiNodeCpu,                        ///< Bit field for MultiNodeCpu( MCM capability)
+
+  BFRxBypass3rd4thStg,                  ///< Bit field RxBypass3rd4thStg
+  BFRx4thStgEn,                         ///< Bit field Rx4thStgEn
+  BFDllNoLock,                          ///< Bit field DllNoLock
+  BFEnSplitMctDatBuffers,               ///< Bit field EnSplitMctDatBuffers
+  BFGmcTokenLimit,                      ///< Bit fieid GmcTokenLimit
+  BFMctTokenLimit,                      ///< Bit field MctTokenLimit
+  BFGmcToDctControl1,                   ///< Bit field GmcToDctControl1
+  BFDllCSRBisaTrimDByte,                ///< Bit field DllCSRBisaTrimDByte
+  BFDllCSRBisaTrimClk,                  ///< Bit field DllCSRBisaTrimClk
+  BFDllCSRBisaTrimCsOdt,                ///< Bit field DllCSRBisaTrimCsOdt
+  BFDllCSRBisaTrimAByte2,               ///< Bit field DllCSRBisaTrimAByte2
+  BFReduceLoop,                         ///< Bit field ReduceLoop
+  BFEffArbDis,                          ///< Bit field EffArbDis
+  BFDramCommand0,                       ///< Bit field for DramCommand0 register
+  BFDramCommand2,                       ///< Bit field for DramCommand2 register
+  BFDramLoopbackAndTrainingControl,     ///< Bit field for DramLoopbackAndTrainingControl register
+  BFCurMemPstate,                       ///< Bit field CurMemPstate
+
+  BFMxMr0,                              ///< Bit field for MxMr0
+  BFMxMr1,                              ///< Bit field for MxMr1
+  BFMxMr2,                              ///< Bit field for MxMr2
+  BFMxMrsEn,                            ///< Bit field for MxMrsEn
+
+  BFUrgentTknDis,                       ///< Bit field for "UrgentTknDis"
+  BFUrGmcMinTokens,                     ///< Bit field for "UrGmcMinTokens"
+  BFUrGmcTokenLimit,                    ///< Bit field for "UrGmcTokenLimit"
+  BFUrMctTokenLimit,                    ///< Bit field for "UrMctTokenLimit"
+  BFUrMctMinTokens,                     ///< Bit field for "UrMctMinTokens"
+
+  BFChAM1FenceSave,                     ///< Bit field for "ChAM1FenceSave"
+  BFChBM1FenceSave,                     ///< Bit field for "ChBM1FenceSave"
+
+  BFMctEccDisLatOptEn,                  ///< Bit field for "MctEccDisLatOptEn"
+  BFCpuElevPrioDis,                     ///< Bit field for "CpuElevPrioDis"
+  BFNbOffsetTrim,                       ///< Bit field for "NbOffsetTrim"
+
+  BFMasterDct,                          ///< Bit field MasterDct
+  BFDramType,                           ///< Bit field DramType
+  BFPmuReset,                           ///< Bit field PmuReset
+  BFPmuStall,                           ///< Bit field PmuStall
+  BFMajorMode,                          ///< Bit field MajorMode
+  BFDqDqsMajorMode,                     ///< Bit field MajorMode on DqDqs Rx Control
+  BFVoltageLevel,                       ///< Bit field VoltageLevel
+  BFDqDqsVoltageLevel,                  ///< Bit field VoltageLevel on DqDqs Rx Control
+
+
+
+  // Reserved
+  BFReserved01,                         ///< Reserved 01
+  BFReserved02,                         ///< Reserved 02
+  BFReserved03,                         ///< Reserved 03
+  BFReserved04,                         ///< Reserved 04
+  BFReserved05,                         ///< Reserved 05
+  BFReserved06,                         ///< Reserved 06
+  BFReserved07,                         ///< Reserved 07
+  BFReserved08,                         ///< Reserved 08
+  BFReserved09,                         ///< Reserved 09
+  BFReserved10,                         ///< Reserved 10
+
+  BFReserved11,                         ///< Reserved 11
+  BFReserved12,                         ///< Reserved 12
+  BFReserved13,                         ///< Reserved 13
+  BFReserved14,                         ///< Reserved 14
+  BFReserved15,                         ///< Reserved 15
+  BFReserved16,                         ///< Reserved 16
+  BFReserved17,                         ///< Reserved 17
+  BFReserved18,                         ///< Reserved 18
+  BFReserved19,                         ///< Reserved 19
+  BFReserved20,                         ///< Reserved 20
+  BFIdsCmnMemReg,                       ///< Reserved for ids only, the value may dynamic change
+  BFDctSelBaseAddrReg,                  ///< Bit field DctSelBaseAddrReg
+  BFDctSelBaseOffsetReg,                ///< Bit field DctSelBaseOffsetReg
+
+  /* End of accessible list --- entries below this line are for private use ------------*/
+  BFEndOfList,                          ///< End of bit field list
+
+  // Only for Table Drive Support define.
+  BFRcvEnDly,       ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers
+  BFWrDatDly,       ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers
+  BFRdDqsDly,       ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers
+  BFWrDqsDly,       ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers
+  BFPhRecDly,       ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers
+  /* Do not define any entries beyond this point */
+  BFAbsLimit                            ///< Beyond this point is reserved for bit field manipulation
+
+} BIT_FIELD_NAME;
+
+/// Bit field aliases
+#define BFMainPllOpFreqId       BFNbFid
+#define BFNbDid                 BFNbPs0NclkDiv
+#define BFRdDramTrainMode       BFPrefDramTrainMode
+#define BFThrottleEn            BFCmdThrottleMode
+#define BFIntlvRegionEn         BFIntLvRgnSwapEn
+#define BFIntlvRegionBase       BFIntLvRgnBaseAddr
+#define BFIntlvRegionLimit      BFIntLvRgnLmtAddr
+#define BFRdOdtPatReg           BFPhyRODTCSLow
+#define BFWrOdtPatReg           BFPhyWODTCSLow
+#define BFLockDramCfg           BFC6DramLock
+#define BFRstRcvFifo            BFTwr
+#define BFDramCmd2Reg           BFCmdBank
+#define BFDramODTCtlReg         BFRdOdtTrnOnDly
+
+/// Bit field names per DRAM CS base address register
+typedef enum {
+  BFCSEnable = 0,               ///< Chip select enable
+  BFSpare = 1,                  ///< Spare rank
+  BFTestFail = 2,               ///< Memory test failed
+  BFOnDimmMirror = 3            ///< on-DIMM mirroring enable
+} CS_BASE_BIT_FIELD;
+
+/// Flag for exclude dimm
+typedef enum {
+  NORMAL,                       ///< Normal mode, exclude the dimm if there is new dimm failure
+  TRAINING,                     ///< Training mode, exclude dimms that fail during training after training is done
+  END_TRAINING                  ///< End training mode, exclude all dimms that failed during training
+} DIMM_EXCLUDE_FLAG;
+
+#define BSP_DIE   0
+#define MAX_NODES_SUPPORTED     8   ///< Maximum number of nodes in the system.
+#define MAX_CS_PER_CHANNEL      8   ///< Max CS per channel
+#define MAX_BYTELANES 8   ///< 8 byte lanes
+#define MAX_DELAYS    9   ///< 8 data bytes + 1 ECC byte
+#define MAX_DIMMS     4   ///< 4 DIMMs per channel
+
+#define VDDIO_DETERMINED      0xFF  ///< VDDIO has been determined yet. Further processing is not needed.
+
+///
+/// MEM_SHARED_DATA
+/// This structure defines the shared data area that is used by the memory
+/// code to share data between different northbridge objects. Each substructure
+/// in the data area defines how this data area is used by a different purpose.
+///
+/// There should only be one instance of this struct created for all of the memory
+/// code to use.
+///
+typedef struct _MEM_SHARED_DATA {
+
+  // System memory map data
+  UINT32  CurrentNodeSysBase;       ///< Base[47:16] (system address) DRAM base address for current node.
+  /// Memory map data for each node
+  BOOLEAN AllECC; ///< ECC support on the system
+  DIMM_EXCLUDE_FLAG DimmExcludeFlag;  ///< Control the exclude dimm behavior
+  UINT8 VoltageMap; ///< The commonly supported voltage map in the system
+
+  UINT8   TopNode;   ///< Node that has its memory  mapped to TOPMEM/TOPMEM2
+  BOOLEAN C6Enabled; ///< TRUE if   C6  is  enabled
+
+  /// Data structure for NB register table
+  struct {
+    UINT64  FamilyId;               ///< LogicalCpuid.Family
+    UINT32  *NBRegTable;            ///< Pointer to allocated buffer for NBRegTable
+  } NBRegMap[MAX_NODES_SUPPORTED];
+
+  /// Data structure for node map
+  struct {
+    BOOLEAN IsValid;                ///< TRUE if this node contains memory.
+    UINT32  SysBase;                ///< Base[47:16] (system address) DRAM base address of this node.
+    UINT32  SysLimit;               ///< Base[47:16] (system address) DRAM limit address of this node.
+  } NodeMap[MAX_NODES_SUPPORTED];
+  BOOLEAN UndoHoistingAbove1TB;     ///< Undo hoisting above 1TB
+
+  /// Data structure for node interleave feature
+  struct {
+    BOOLEAN IsValid;                ///< TRUE if the data in this structure is valid.
+    UINT8   NodeCnt;                ///< Number of nodes in the system.
+    UINT32  NodeMemSize;            ///< Total memory of this node.
+    UINT32  Dct0MemSize;            ///< Total memory of this DCT 0.
+    UINT8   NodeIntlvSel;           ///< Index to each node.
+  } NodeIntlv;
+} MEM_SHARED_DATA;
+
+///
+/// MEM_MAIN_DATA_BLOCK
+///
+typedef struct _MEM_MAIN_DATA_BLOCK {
+  struct _MEM_DATA_STRUCT *MemPtr;          ///< Pointer to customer shared data
+  struct _MEM_NB_BLOCK    *NBPtr;           ///< Pointer to array of NB Blocks
+  struct _MEM_TECH_BLOCK  *TechPtr;         ///< Pointer to array of Tech Blocks
+  struct _MEM_SHARED_DATA *mmSharedPtr;     ///< Pointer to shared data area.
+  UINT8           DieCount;                 ///< Total number of Dies installed
+} MEM_MAIN_DATA_BLOCK;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+node: Indicates the Node
+- Value ranges from 0-7, 0xF: for all nodes
+- Size - 4 Bits
+
+dct: Indicate the DRAM Controller
+- Value is 0, 1 (0xF: apply setting to all DCTs)
+- Size - 4 Bits
+
+dimm: This values specifies which DIMM register will be applied
+- The value varies from 0 to 3, 0xF: all DIMMs
+- Size - 4 Bits
+
+attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed)
+- 0: Do not change the current value in the register
+- 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined)
+- 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
+- 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
+- Size - 2 Bits
+
+time - Indicate the timing for the register which is written.
+- 0:  Write register value before Dram init
+- 1:  Write register value before memory training
+- 2:  Write register value after memory training
+- Size - 1 Bits
+
+bytelane: bytelane number
+- This determines specifies which bytelane register will be applied
+- Bit0 =1 - set value into Bytelane0
+- Bit1 =1 - set value into Bytelane1
+- Bit2 =1 - set value into Bytelane2
+...
+...
+- 0xFFFF: all bytelane
+- Size - 16 Bits.
+
+bfIndex: Indicate the bitfield index
+- Size - 16 Bits
+
+value - Value to be used
+- This can be an offset (sub or Add) or an override value.
+- Size - DWORD
+*/
+
+// Sample code
+// NBACCESS (MTBeforeDInit, MTNodes,  MTDct0, BFCSBaseAddr5Reg, MTOverride,   0x400001),
+// NBACCESS (MTBeforeTrn,   MTNodes,  MTDct1, BFCSBaseAddr7Reg, MTOverride,   0xFFFFFFFF),
+// DQSACCESS (MTAfterTrn,    MTNodes,  MTDcts, MTDIMM0,  MTBL1+MTBL2,    BFRcvEnDly, MTSubtract,   2),
+// DQSACCESS (MTAfterTrn,    MTNodes,  MTDct1, MTDIMM1,  MTBLNOECC,      BFRcvEnDly, MTAdd,        1),
+
+#define ENDMEMTDS  0, 0, 0, 0, 0, 0, 0xFFFFFFFFul, 0
+
+#define NBACCESS(time, node, dct, bitfield, attr, value) \
+{ (time), \
+  ((node) & 0x0F) | ((dct) << 4), \
+  (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \
+  (UINT8)((bitfield) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 8)  & 0x000000FF), \
+  (UINT8)(((bitfield) >> 16) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 24) & 0x000000FF), \
+  0, 0, \
+  (UINT8)((value) & 0x000000FF), \
+  (UINT8)(((value) >> 8)  & 0x000000FF), \
+  (UINT8)(((value) >> 16) & 0x000000FF), \
+  (UINT8)(((value) >> 24) & 0x000000FF), \
+  0, 0, 0 \
+}
+
+#define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \
+{ (time), \
+  ((node) & 0x0F) | ((dct) << 4), \
+  (((dimm) & 0x0F)  | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \
+  (UINT8)((bitfield) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 8)  & 0x000000FF), \
+  (UINT8)(((bitfield) >> 16) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 24) & 0x000000FF), \
+  (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \
+}
+
+#define DQS2DACCESS(time, node, dct, dimm, bitfield, attr, l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18) \
+{ (time), \
+  ((node) & 0x0F) | ((dct) << 4), \
+  (((dimm) & 0x0F)  | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \
+  (UINT8)((bitfield) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 8)  & 0x000000FF), \
+  (UINT8)(((bitfield) >> 16) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 24) & 0x000000FF), \
+  (l0, (l1), (l2), (l3), (l4), (l5), (l6), (l7), (l8), (l9), (l10), (l11), (l12), (l13), (l14), (l15), (l16), (l17), (l18) \
+}
+/// Type of modification supported by table driven support.
+typedef enum {
+  MTAuto,                       ///<  Do not change the current value in the register
+  MTOverride,                   ///<  Use the value provided in the table to override the current value in the register
+  MTSubtract,                   ///<  Subtract the value provided in the table as an offset to the current value in the register
+  MTAdd,                         ///<  Add the value provided in the table as an offset to the current value in the reg
+  MTAnd,                         ///<  And the value provided in the table as an offset to the current value in the reg
+  MTOr                         ///<  Or the value provided in the table as an offset to the current value in the reg
+} MTAttr;
+
+/// Time for table driven support to make modification.
+/// NOTE please keep the order of below MT points
+typedef enum {
+  MTBeforeInitializeMCT = 0,        ///<  00 Before InitializeMCT
+  MTAfterAutoCycTiming,             ///<  01 After Auto Cycle Timing
+  MTAfterPlatformSpec,              ///<  02 After Platform Specific Configuration
+  MTBeforeDInit,                    ///<  03 Before Dram init
+  MTBeforeTrn,                      ///<  04 Before memory training
+  MTAfterMemPstate1PartialTrn,      ///<  05 After partial training at starting frequency
+  MTAfterTrn,                       ///<  06 After memory training
+  MTAfterSwWLTrn,                   ///<  07 After SW Based WL Training
+  MTAfterHwWLTrnP1,                 ///<  08 After HW Based WL Training Part 1
+  MTAfterHwRxEnTrnP1,               ///<  09 After HW Based Receiver Enable Training Part 1
+  MTAfterFreqChg,                   ///<  10 After each frequency change
+  MTAfterHwWLTrnP2,                 ///<  11 After HW Based WL Training Part 2
+  MTAfterHwRxEnTrnP2,               ///<  12 After HW Based Receiver Enable Training Part 2
+  MTAfterSwRxEnTrn,                 ///<  13 After SW Based Receiver Enable Training
+  MTAfterDqsRwPosTrn,               ///<  14 After DQS Read/Write Position Training
+  MTAfterMaxRdLatTrn,               ///<  15 After Max Read Latency Training
+  MTAfterNbPstateChange,            ///<  16 After programming NB Pstate dependent registers
+  MTAfterInterleave,                ///<  17 After Programming Interleave registers
+  MTAfterSettingMemoryPstate1,      ///<  18 After programming registers for memory pstate 1
+  MTAfterFinalizeMCT,               ///<  19 After Finalize MCT Programming
+
+  MTValidTimePointLimit,        ///< Mark the upper bound of the supported time points
+  MTEnd = 0xFF ///< End of enum define.
+} MTTime;
+
+/// Node on which modification should be made by table driven support.
+typedef enum {
+  MTNode0, ///< Node 0.
+  MTNode1, ///< Node 1.
+  MTNode2, ///< Node 2.
+  MTNode3, ///< Node 3.
+  MTNode4, ///< Node 4.
+  MTNode5, ///< Node 5.
+  MTNode6, ///< Node 6.
+  MTNode7, ///< Node 7.
+  MTNodes = 0xF                   ///<  all nodes
+} MTNode;
+
+/// DCT on which modification should be made by table driven support.
+typedef enum {
+  MTDct0, ///< DCT 0.
+  MTDct1, ///< DCT 1.
+  MTDcts = 0x7,                   ///<  all dcts
+} MTDct;
+
+/// Dimm on which modification should be made by table driven support.
+typedef enum {
+  MTDIMM0, ///< Dimm 0.
+  MTDIMM1, ///< Dimm 1.
+  MTDIMM2, ///< Dimm 2.
+  MTDIMM3, ///< Dimm 3.
+  MTDIMMs = 0xF,                  ///<  all Dimms
+} MTDIMM;
+
+/// Bytelane on which modification should be made by table driven support.
+typedef enum {
+  MTBL0 = 0x1,                    ///<  set the value into Bytelane0
+  MTBL1 = 0x2,                    ///<  set the value into Bytelane1
+  MTBL2 = 0x4,                    ///<  set the value into Bytelane2
+  MTBL3 = 0x8,                    ///<  set the value into Bytelane3
+  MTBL4 = 0x10, ///< set the value into Bytelane4
+  MTBL5 = 0x20, ///< set the value into Bytelane5
+  MTBL6 = 0x40, ///< set the value into Bytelane6
+  MTBL7 = 0x80, ///< set the value into Bytelane7
+  MTBL8 = 0x100,                  ///<  set the value into ECC
+  MTBLNOECC = 0xFF,               ///<  all Bytelanes except ECC
+  MTBLs = 0xFFFF,                 ///<  all Bytelanes
+} MTBL;
+
+/// Values used to indicate which type of training is being done.
+typedef enum {
+  TRN_RCVR_ENABLE,                     ///< Reciever Enable Training
+  TRN_DQS_POSITION,                    ///< Read/Write DQS Position training
+  TRN_MAX_READ_LATENCY                 ///< Max read Latency training
+} TRAINING_TYPE;
+
+/// Memory Pstate
+typedef enum {
+  MEMORY_PSTATE0,   ///< Memory Pstate 0
+  MEMORY_PSTATE1,   ///< Memory Pstate 1
+} MEM_PSTATE;
+
+/// Memory Pstate Training Stage
+typedef enum {
+  MEMORY_PSTATE_1ST_STAGE = 0xF1,   ///< Memory Pstate processing stage 1, in which full training is done at DDR667
+  MEMORY_PSTATE_2ND_STAGE,          ///< Memory Pstate processing stage 2, in which partial trainig will be done at DDR800 - target speed
+  MEMORY_PSTATE_3RD_STAGE,          ///< Memory Pstate processing stage 3, in which full training will be done at target frequency and MaxRdLatency training will start
+  MEMORY_PSTATE_S3_STAGE            ///< Memory Pstate Processing in S3.
+} MEM_PSTATE_STAGE;
+
+/// RdDqsDly Retrain status
+typedef enum {
+  RDDQSDLY_RTN_NEEDED = 0xF1,       ///< RdDqsDly retrain may be needed
+  RDDQSDLY_RTN_SUSPEND,             ///< RdDqsDly retrain is suspected
+  RDDQSDLY_RTN_ONGOING              ///< RdDqsDly retrain condition is just detected
+} RDDQSDLY_RTN_STAT;
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+MemAmdFinalize (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+MemSocketScan (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+VOID
+SetMemError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  );
+
+VOID
+AmdMemInitDataStructDefRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+SetMemRecError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  );
+
+AGESA_STATUS
+memDefRetSuccess ( VOID );
+
+VOID
+AmdMemFunctionListDef (
+  IN OUT   VOID *pMemData
+  );
+#endif  /* _MM_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
new file mode 100644
index 0000000000..6174c98520
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
@@ -0,0 +1,1820 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mn.h
+ *
+ * Common Northbridge
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MN_H_
+#define _MN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define _4GB_RJ16           (((UINT32) 4) << (30 - 16))
+#define _1TB_RJ16           (((UINT32) 1) << (40 - 16))
+#define HT_REGION_BASE_RJ16 ((UINT32)0x00FD0000ul)
+
+#define DCT_ACCESS_WRITE (UINT32) 0x40000000ul
+#define MTRR_VALID  11
+#define THERMAL_OPT 31
+
+#define NB_ACCESS       0
+#define DCT_PHY_ACCESS  1
+#define DCT_EXTRA       2
+
+#define DCT_PHY_DIRECT  0xF1
+
+#define VT_MSK_VALUE 0
+#define VT_ARRAY     1
+/*---------------------------------------------
+ *   TSEFO - Type Start End Function Offset
+ *
+ *   31:30   Type of access        (2-bits)
+ *   29:29   Special               (1-bit)
+ *   28:28   Phy Direct            (1-bit)
+ *   27:27   Whole Register Access (1-bit)
+ *   26:26   Linked                (1-bit)
+ *   25:21   Start bit             (5-bits)
+ *   20:16   End bit               (5-bits)
+ *   15:00   Function_Offset/Index (16-bits)
+ *---------------------------------------------
+ */
+typedef UINT32 TSEFO;
+
+/**
+  MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex):
+
+  @param[in]    TableName
+  @param[in]    BitFieldIndex
+  @param[in]    a  Type of access.
+  @param[in]    b  Index of register (can be in Function_Offset format).
+  @param[in]    c  Highest bit of the bit field.
+  @param[in]    d  Lowest bit of the bit field.
+
+  @return   TSEFO  Access params encrypted in TSEFO format.
+--*/
+#define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \
+TableName[BitFieldIndex] = ( \
+  (a == DCT_PHY_DIRECT) ? ( \
+    (((UINT32) DCT_PHY_ACCESS) << 30) | (((UINT32) 1) << 28) | (((UINT32) b) & 0xFFFF) | (\
+      ((c == 15) && (d == 0)) ? ( \
+        (((UINT32) 1) << 27) | (((UINT32) b) & 0xF0000) \
+      ) : ( \
+        (c >= d) ? ( \
+          (((UINT32) c) << 21) | (((UINT32) d) << 16) \
+        ) : ( \
+          (((UINT32) d) << 21) | (((UINT32) c) << 16) \
+        ) \
+      ) \
+    ) \
+  ) : ( \
+    (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \
+      (((UINT32) b) >> 16) ? ( \
+        (((UINT32) 1) << 29) \
+      ) : ( \
+        (c >= d) ? ( \
+          (((UINT32) c) << 21) | (((UINT32) d) << 16) \
+        ) : ( \
+          (((UINT32) d) << 21) | (((UINT32) c) << 16) \
+        ) \
+      ) \
+    ) \
+  ) \
+)
+
+/**
+  LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex):
+  This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex,
+                        but NOT the other way around.
+  Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex.
+
+  @param[in]    TableName
+  @param[in]    LowerBitFieldIndex
+  @param[in]    HigherBitFieldIndex
+
+  @return   TSEFO  Access params encrypted in TSEFO format.
+--*/
+#define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \
+  ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \
+  TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \
+}
+
+// Indicate when a bitfield has multiple memory Pstate copy
+#define MULTI_MPSTATE_COPY_TSEFO(TableName, BitFieldName) \
+  TableName[BitFieldName] = TableName[BitFieldName] | (((UINT32) 1) << 29)
+
+#define TSEFO_TYPE(x)  ((UINT8) (((UINT32) (x) >> 30) & 0x03))
+#define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F))
+#define TSEFO_END(x)   ((UINT8) (((UINT32) (x) >> 16) & 0x1F))
+#define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF)
+#define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01))
+#define TSEFO_DIRECT_EN(x) ((UINT8) (((UINT32) (x) >> 28) & 0x01))
+#define TSEFO_WHOLE_REG_ACCESS(x) ((UINT8) (((UINT32) (x) >> 27) & 0x01))
+#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y))
+#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1))
+#define _NOT_USED_ 0
+
+/* */
+#define B0_DLY   0
+#define B1_DLY   1
+#define B2_DLY   2
+#define B3_DLY   3
+#define B4_DLY   4
+#define B5_DLY   5
+#define B6_DLY   6
+#define B7_DLY   7
+#define ECC_DLY  8
+
+#define DDR2_TRAIN_FLOW 0
+#define DDR3_TRAIN_FLOW 1
+
+//
+// Minimum Data Eye width in consecutive 32nds of a UI of
+// valid data
+//
+#define MIN_RD_DATAEYE_WIDTH_NB 4
+#define MIN_WR_DATAEYE_WIDTH_NB 4
+
+//
+// RELIABLE READ/WRITE MODE DEFINITIONS
+//
+#define PRECHARGE_ALL_BANKS 0xFF           ///< Use to specify PrechargeAll Command to Precharge Cmd Function
+#define CMD_TGT_A           0x00           ///< Issue Commands to Command Target A
+#define CMD_TGT_AB          0x01           ///< Issue Commands to Command Targets A and B
+#define CMD_TYPE_READ       0x00           ///< Read Command
+#define CMD_TYPE_WRITE      0x01           ///< Write Command
+#define CMD_TYPE_WR_RD      0x02           ///< Alternating Write and Read Commands
+#define CPG_BANK_ADDRESS_A  0x0            ///< Dimm Bank address used in Reliable RD/RW mode training
+#define CPG_BANK_ADDRESS_B  0x1            ///< Dimm Bank address used in Reliable RD/RW mode training
+#define CPG_ROW_ADDRESS_A   0x0            ///< Dimm Row address used in Reliable RD/RW mode training
+#define CPG_ROW_ADDRESS_B   0x0            ///< Dimm Row address used in Reliable RD/RW mode training
+#define CPG_COL_ADDRESS_A   0x0            ///< Dimm Column address used in Reliable RD/RW mode training
+#define CPG_COL_ADDRESS_B   0x0            ///< Dimm Column address used in Reliable RD/RW mode training
+#define CPG_COMPARE_MASK_LOW 0x00000000ul  ///< Dram DQMask[31:0] used to mask comparison on reads.  1=ignore
+#define CPG_COMPARE_MASK_HI  0x00000000ul  ///< Dram DQMask[63:32] used to mask comparison on reads.  1=ignore
+#define CPG_COMPARE_MASK_ECC 0x00          ///< Dram EccMask used to mask comparison on reads.  1=ignore
+#define PRBS_SEED_32        0x062221ul     ///< Data PRBS Seed
+#define PRBS_SEED_64        0x066665ul     ///< Data PRBS Seed
+#define PRBS_SEED_128       0x026666ul     ///< Data PRBS Seed
+#define PRBS_SEED_256       0x044443ul     ///< Data PRBS Seed
+
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Structure for Reliable Read/Write Mode Data
+/// These are values that may need to be referenced by the low level functions
+/// during training and are initialized at the begining of a particular type of training.
+typedef struct _RRW_SETTINGS {
+  UINT8 CmdTgt;                          ///< Value to program into CmdTgt
+  UINT8 TgtBankAddressA;                 ///< Target A Bank address
+  UINT32 TgtRowAddressA;                 ///< Target A Row address
+  UINT32 TgtColAddressA;                 ///< Target A Column address
+  UINT8 TgtBankAddressB;                 ///< Target B Bank address
+  UINT32 TgtRowAddressB;                 ///< Target B Row address
+  UINT32 TgtColAddressB;                 ///< Target B Column address
+  UINT32 CompareMaskLow;                 ///< Compare Mask Bits 31:0
+  UINT32 CompareMaskHigh;                ///< Compare Mask Bits 63:32
+  UINT8 CompareMaskEcc;                  ///< Compare Mask Ecc
+  UINT32 DataPrbsSeed;                   ///< PRBS Seed value
+} RRW_SETTINGS;
+
+/// DQS training related delays
+typedef enum {
+  AccessRcvEnDly,                       ///< Receiver enable delay
+  AccessWrDatDly,                       ///< Write data delay
+  AccessRdDqsDly,                       ///< Read DQS delay
+  AccessWrDqsDly,                       ///< Write DQS delay
+  AccessPhRecDly,                       ///< Phase recovery delay
+  excel845
+} TRN_DLY_TYPE;
+
+/// Training patterns for position training
+typedef enum {
+  POS_PATTERN_72B,                      ///< 72 bit pattern
+  POS_PATTERN_256B,                     ///< 256 bit pattern
+} POS_TRN_PATTERN_TYPE;
+
+/// ODT mode
+typedef enum {
+  MISSION_MODE,                         ///< ODT during mission mode
+  WRITE_LEVELING_MODE                   ///< ODT during write leveling
+} ODT_MODE;
+
+/*
+ *   DRBN - Dimm-Rank-Byte-Nibble
+ *   31:12   Reserved
+ *   11:09   Dimm       (3-bits)
+ *   08      Rank       (1-bit)
+ *   07:05   Reserved
+ *   04:01   Byte       (4-bits)
+ *   00      Nibble     (1-bit)
+ */
+typedef UINT32 DRBN;
+#define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \
+(((UINT32) (byte)) << 1) | ((UINT32) (nibble)) )
+#define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1))
+#define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble)))
+#define DIMM_NBBL_ACCESS(dimm, nibble) ((((UINT32) (dimm)) << 9) | ((UINT32) (nibble)))
+#define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07))
+#define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01))
+#define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F))
+#define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01))
+#define DRBN_DIMM_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x1F))
+
+/* Dimm Type mask */
+#define DT_X4       0x01
+#define DT_X8       0x02
+#define DT_X16      0x04
+#define DT_SR       0x10
+#define DT_DR       0x20
+#define DT_QR       0x40
+
+#define DT_ANY_X4   0x71
+#define DT_ANY_X8   0x72
+#define DT_ANY_X16  0x74
+#define DT_ANY_SR   0x17
+#define DT_ANY_DR   0x27
+#define DT_ANY_QR   0x47
+#define DT_ANY_SR_DR    (DT_ANY_SR | DT_ANY_DR)
+#define DT_ANY          (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR)
+
+/// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type
+///
+typedef struct _TRN_DLY_PARMS {
+  UINT8  Min;    ///< Minimum Value
+  UINT8  Max;    ///< Maximum Value
+  UINT8  Mask;   ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.)
+} TRN_DLY_PARMS;
+
+/// Structure for certain data saving needed for DCT.
+typedef struct {
+  UINT8  RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts
+  UINT32 PhRecReg[3];     ///< 3 Phase recovery control registers
+  BOOLEAN excel846;
+} MEM_DCT_CACHE;
+
+/// Structure for table driven support.
+typedef struct _MEM_TBL_ALIAS {
+  UINT8  time;            ///< Modification time.
+  UINT8  node:4;          ///< Node on which to make modification.
+  UINT8  dct:4;           ///< DCT on which to make modification.
+  UINT8  dimm:4;          ///< Dimm on which to make modification.
+  UINT8  attr:3;          ///< Attribute of modification.
+  UINT8  vtype:1;         ///< Flag indicating value type.
+  UINT32 bfindex;         ///< Bit field index that need to be modified.
+  union {                 ///< Union is defined to easy select between single and multiple bytelane cases.
+    struct {              ///< Sub-struct used for one bytelane value.
+      UINT16 bytelane:16; ///< Bytelane on which to make modification.
+      UINT32 value;       ///< Modified value.
+      UINT8 reserved[3];  ///< Reserved for this purpose
+    } s;                  ///< single value to one or multiple bytelanes
+    UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values
+  } data;
+} MEM_TABLE_ALIAS;
+
+/// Structure for Platform Specific Block.
+typedef struct _MEM_PS_BLOCK {
+  UINT8 DramTerm; ///< Dram Term
+  UINT8 QR_DramTerm; ///< Dram Term for QR
+  UINT8 DynamicDramTerm; ///< Dynamic Dram Term
+  UINT8 NumOfReg[MAX_DIMMS_PER_CHANNEL]; ///< Number of registers on each RDIMM (From SPD)
+  UINT8 MR0WR;  ///< MR0WR
+  UINT8 MR0CL31;  ///< MR0[CL][3:1]
+  UINT8 MR0CL0;  ///< MR0CL[0]
+  UINT8 RttNom[8];  ///< RttNom value for maximum 8 chipsels per channel
+  UINT8 RttWr[8];  ///< RttWr value for maximum 8 chipsels per channel
+  UINT8 F0RC8;  ///< F0RC8
+  UINT8 F1RC0;  ///< F1RC0
+  UINT8 F1RC1;  ///< F1RC1
+  UINT8 F1RC2;  ///< F1RC2
+  UINT8 RC10OpSpd;  ///< RC10[OperatingSpeed]
+  UINT8 LrdimmRowAddrBits[MAX_DIMMS_PER_CHANNEL]; ///< Effective Row address bits used by LRDIMMS
+  UINT16 SpeedLimit[VOLT1_25_ENCODED_VAL + 1];  ///< SpeedLimit of individual VDDIO
+  UINT8 WLSeedVal;  ///< Seed value of WL training extracted from PSC table
+  UINT16 HWRxENSeedVal;  ///< Seed value of HW RxEn training extracted from PSC table
+
+  /* PUBLIC functions */
+  BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info.
+  VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population.
+  BOOLEAN (*MemPGetPass1Seeds) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets pass1 seeds of WL and RxEn training.
+} MEM_PS_BLOCK;
+
+/// Structure parameters needed in frequency change of client NB.
+typedef struct _MEM_FREQ_CHANGE_PARAM {
+  UINT16 PllLockTimeDefault; ///< Default PllLockTime
+  UINT8  RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher
+  UINT8  RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz
+  UINT8  NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2
+  UINT8  MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2
+  UINT8  SyncTimeMul4x;         ///< Multiplier for SyncTime
+  UINT16 TDataProp800orHigher;  ///< TDataProp for frequency 800MHz or higher
+  UINT16 TDataPropLower800;     ///< TDataProp for frequency lower than 800MHz
+} MEM_FREQ_CHANGE_PARAM;
+
+/// List for NB items that are supported
+typedef enum {
+  SetSpareEn,                      ///< Sets spare enable
+  CheckSpareEn,                    ///< Spare enabled
+  SetDllShutDown,                  ///< Sets DllShutDown
+  CheckEccDLLPwrDnConfig,          ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted
+  DimmBasedOnSpeed,                ///< Checks to determine if Dimm number needs to be adjusted based on speed
+  CheckMaxDramRate,                ///< Checks to determine the maximum rate
+  Check1GAlign,                    ///< Checks to determine if 1 GB alignment is supported
+  DramModeBeforeDimmPres,          ///< Check to determine if DRAM mode needs to be set before dimm presence
+  DramModeAfterDimmPres,           ///< Check to determine if DRAM mode needs to be set after dimm presence
+  CheckClearOnDimmMirror,          ///< Check to determine if we need to clear on DIMM mirror
+  CheckDisDllShutdownSR,           ///< Check to determine if DisDllShutdown needs to be set
+  CheckMemClkCSPresent,            ///< Check to determine if chipselect needs to be set based on disabled memclocks
+  CheckChangeAvgValue,             ///< Check to determine if we need to change average value
+  CheckMaxRdDqsDlyPtr,             ///< Check to determine change Max Rd Dqs Delay
+  CheckPhyFenceTraining,           ///< Check to determine if we need to Phy Fence training
+  CheckGetMCTSysAddr,              ///< Check to determine if we need to GetMCTSysAddr
+  CheckSendAllMRCmds,              ///< Check to determine if we need to SendAllMRCmds
+  CheckFindPSOverideWithSocket,    ///< Check to determine if we need to Find PSOveride With Socket
+  CheckFindPSDct,                  ///< Check to determine if we need to Find PSOveride With DCT
+  CheckODTControls,                ///< Check to determine if we need to set ODT controls
+  CheckDummyCLRead,                ///< Check to determine if an extra dummy read is required
+  CheckDllStdBy,                   ///< Check to determine if setting DLL stand by is required
+  CheckSlewWithMarginImprv,        ///< Check to determine if setting of Slew With MarginImprv is required
+  CheckSlewWithoutMarginImprv,     ///< Check to determine if setting of Slew Without MarginImprv is required
+  CheckDllSpeedUp,                 ///< Check to determine if setting of Dll SpeedUp is required
+  CheckDllRegDis,                  ///< Check to determine if setting of DLL Regulator Disable is required
+  FenceTrnBeforeDramInit,          ///< Check to determine if fence training has been done before Dram init
+  WLSeedAdjust,                    ///< Check to determine if WL seed needs to be adjusted
+  UnifiedNbFence,                  ///< Check to determine if Phy fence is of Unified NB
+  AdjustTwr,                       ///< Check to determine if Twr needs to be adjusted
+  ChannelPDMode,                   ///< Check to determine if channel power down mode is the only that is supported
+  ForceEnMemHoleRemapping,         ///< Check to determine if we need to force enabling memory hole remapping
+  AdjustTrdrdSD,                   ///< Check to determine if we need to adjust TrdrdSD
+  ReverseMaxRdLatTrain,            ///< Check to determine if reverse (pass to fail) algorithm is supported for MaxRdLat training
+  SkipErrTrain,                    ///< Check to determine if skip error training is supported
+  DramSrHys,                       ///< Check to determine if DRAM SR hysteresis is supported
+  PchgPDMode,                      ///< Check to determine if Precharge powerdown mode is supported
+  EccByteTraining,                 ///< Check to determine if DRAM ECC Byte training
+  CheckDrvImpCtrl,                 ///< Check to determine if we need to set DrvImpCtrl
+  CheckDramTerm,                   ///< Check to determine if we need to set DramTerm
+  CheckDramTermDyn,                ///< Check to determine if we need to set DramTermDyn
+  CheckQoff,                       ///< Check to determine if we need to set Qoff
+  CheckSetSameDctODTsEn,           ///< Check to defermine if we need to set "ODTsEn" the same on each DCT
+  WLNegativeDelay,                 ///< Check to determine if the NB can tolerate a negtive WL delay value
+  SchedDlySlot1Extra,              ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK
+  TwoStageDramInit,                ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init.
+  ExtraPclkInMaxRdLat,             ///< Check to determine if an extra PCLK is needed for MaxRdLat
+  CsrPhyPllPdEn,                   ///< Check to determine if CSR Phy PLL Powerdown is enabled or not
+  AdjustTrc,                       ///< Check to determine if we need to adjust Trc
+  ProgramCsrComparator,            ///< Check to determine if we need to program CsrComparator with the same value as D18F2x09C_x0D0F_0[7:0]1F[RxVioLvl]
+  EnProcOdtAdvForUDIMM,            ///< Check to determine if we need to always enable ProcOdtAdv for UDIMM
+  SetTDqsForx8DimmOnly,            ///< Only set MR1[TDQS] for x8 DIMMs when x4 and x8 DIMMs are both present on a channel
+  WlRttNomFor1of3Cfg,              ///< Set Rtt_Nom = Rtt_Wr in one of three DIMMs per channel configurations
+  PerformanceOnly,                 ///< Only support performance policy, does not support battery life policy
+  AdjustTrp,                       ///< Check to determin if Trp needs to be adjusted
+  DllStaggerEn,                    ///< Check to determin if Dll Stagger should be turned on
+  ForcePhyToM0,                    ///< Force Phy to M0
+  excel847_0,
+  excel847_1,
+  excel848_0,
+  excel848_1,
+
+  EnumSize                         ///< Size of list
+} NB_SUPPORTED;
+
+/// List for family specific functions that are supported
+typedef enum {
+  BeforePhyFenceTraining,          ///< Family specific tasks before Phy Fence Training
+  BeforeMemClkFreqVal,             ///< hook before setting MemClkFreqVal bit
+  AfterMemClkFreqVal,              ///< Override PllMult and PllDiv
+  OverridePllMult,                 ///< Override PllMult
+  OverridePllDiv,                  ///< Override PllDiv
+  BeforeMemClr,                    ///< Before MemClr
+  SendMrsCmdsPerCs,                ///< Send MRS commands per CS
+  SetupHwTrainingEngine,           ///< Setup Hardware training engine for specific training type
+  OverrideRcvEnSeed,               ///< Override seed for hardware based RcvEn training
+  AddlMaxRdLatTrain,               ///< Perform additional MaxRdLat training if needed
+  ForceAutoComp,                   ///< Force Auto Comp
+  DetectMemPllError,               ///< Detect MemPll Divide by 3 bug
+  ReEnablePhyComp,                 ///< Re-Enable Phy Compensation after RcvEn Training
+  ExtractWLODT,                    ///< Extract WL ODT value thr given ODT pattern
+  DCTSelectSwitch,                 ///< Select DCT when we switch DCT
+  ScrubberErratum,                 ///< Erratum for setting scrubber rate
+  MR0_PPD,                         ///< Override MR0[PPD]
+  GetDdrMaxRate,                   ///< Interpret DdrMaxRate with Familiy-specific encoding
+  ExitPhyAssistedTraining,         ///< Perform family specific tasks when exiting phy assisted training
+  AfterSaveRestore,                ///< Action after save/restore execution
+  OverrideDataTxFifoWrDly,         ///< Override DataTxFifoWrDly based on training result of WrDatDly
+  OverrideRcvEnSeedPassN,          ///< Override seed for hardware based RcvEn training where N greater than 0
+  AfterMemClkFreqChg,              ///< Reprogram DIMMs' buffers after MEMCLK frequency change
+  AdjustTxpdll,                    ///< Adjust Txpdll value to encoded register value
+  CalcWrDqDqsEarly,                ///< Calculate WrDqDqsEarly
+  TrainWlPerNibble,                ///< Train Write Leveling per nibble
+  TrainWlPerNibbleAdjustWLDly,     ///< Train WL per nibble and adjust the WL delay
+  TrainWlPerNibbleSeed,             ///< Save the seed for WL nibble based training
+  TrainRxEnPerNibble,              ///< Train Rx Enable Training per nibble
+  TrainRxEnAdjustDlyPerNibble,     ///< Train Rx Enable Training nibble and adjust the RxEn delay
+  TrainRxEnGetAvgDlyPerNibble,     ///< Display Rx Enable Training average nibble value for each BL
+  InitPerNibbleTrn,                ///< Initiates Per Nibble Training.
+  BeforeSetCsTri,                  ///< Modify CS tri-state bit map.
+  ForceRdDqsPhaseB,                ///< Force RdDqsDly to phase B
+  SetDqsODT,                       ///< Set DQS ODT
+  DisLowPwrDrvStr,                 ///< Hook to skip setting LowPowerDriveStrengthEn
+  AdjustRdDqsDlyOffset,            ///< Adjust the bit offset of the RdDqsDly Bit Bitfield before writing and after reading
+  ResetRxFifoPtr,                  ///< Reset RxFifo pointer during Read DQS training
+  EnableParityAfterMemRst,         ///< Enable DRAM Address Parity after memory reset.
+  FinalizeVDDIO,                   ///< Finalize VDDIO
+  TrainingNibbleZero,              ///< Check for see Nibble zero is being trained (individually or with x8 training)
+  ProgOdtControl,                  ///< Calculate RdOdtTrnOnDly and RdOdtOnDuration
+  SetSkewMemClk,                   ///< Set SkewMemClk
+  OverrideWLSeed,                  ///< Override WL seed
+  AdjustCSIntLvLowAddr,            ///< Adjust CS interleaving low address
+  Adjust2DVrefStepSize,            ///< Adjusts the step size for Vref during 2D RdDqs training
+  Adjust2DRdDqsStepSize,           ///< Adjusts the step size for RdDqs during 2D RdDqs training
+  ReleaseNbPstate,                 ///< Release NB P-state
+  InitializeRxEnSeedlessTraining,  ///< Initializes RxEn Seedless Training
+  TrackRxEnSeedlessRdWrNoWindBLError,           ///< Track Bytelane Errors resulting from No window for RxEn Seedless Training
+  TrackRxEnSeedlessRdWrSmallWindBLError,        ///< Track Bytelane Errors resulting from Small window for RxEn Seedless Training
+  InitialzeRxEnSeedlessByteLaneError,           ///< Initializes ByteLaneError to False for RxEn Seedless Training
+  InitExtMMIOAddr,                 ///< Initializes extended MMIO address space
+  MemPstateStageChange,            ///< handle training when multiple memory pstate is supported
+  ProgramFence2RxDll,              ///< program RxDll in a different register
+  RdDqsDlyRestartChk,              ///< Check to see if we need to restart RdDqsDly
+  BeforeWrDatTrn,                  ///< Check to see if special handling is needed before WrDatDly Training
+  ForceLvDimmVoltage,              ///< Force LVDIMM voltage to 1.5V
+  BfAfExcludeDimm,                 ///< Workaround before and after excluding dimms
+  AdjustWrDqsBeforeSeedScaling,    ///< For some family, negative WL is compensated and WrDqs needs to be adjusted before seed scaling
+  OverridePrevPassRcvEnDly,        ///< Check to determine if we need override PrevPassRcvEnDly
+  AdjustRdPtrInit,                 ///< Adjust RdPtrInit value according to certain conditions
+  Adjust2DPhaseMaskBasedOnEcc,     ///< Adjusts the Phase Mask Based on ECC
+  FixupSysAddr,                    ///< Adjust physical address before identifying DIMM.
+  RegAccessFence,                  ///< Make sure previous phy registers writes are done
+  WLMR1,                           ///< Check to see if we need to do special things when sending MR1 during WL
+
+  NumberOfHooks                    ///< Size of list
+} FAMILY_SPECIFIC_FUNC_INDEX;
+
+///< Entry for SPD Timing
+typedef struct {
+  BIT_FIELD_NAME BitField;  ///< Bit field name of the timing
+  UINT8 Min; ///< Minimum value for timing
+  UINT8 Max; ///< Maximum value for timing
+  UINT8 Bias; ///< Bias from actual value
+  UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2)
+} CTENTRY;
+
+/// Structure for northbridge block.
+typedef struct _MEM_NB_BLOCK {
+  MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT.
+  MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT.
+  DIE_STRUCT *MCTPtr;             ///< point to current Node's MCT struct
+  DCT_STRUCT *DCTPtr;             ///< point to current Node's DCT struct
+  DCT_STRUCT *AllDCTPtr;          ///< point to all Node's DCT structs
+  CH_DEF_STRUCT *ChannelPtr;       ///< point to current channel data
+  SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT.
+  struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block.
+  struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block.
+  struct _MEM_SHARED_DATA *SharedPtr;     ///< Pointer to Memory scratchpad area
+  struct _MEM_NB_BLOCK    *AdjacentDieNBPtr;     ///< Pointer to Adjacent Die In same socket
+  BOOLEAN  DieEnabled[MAX_NODES_SUPPORTED];///< Indicates the Dies that are enabled
+  SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system.
+  DIE_STRUCT *AllNodeMCTPtr;      ///< point to all Node's MCT structs
+  UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode.
+  MEM_PS_BLOCK *PsPtr; ///< point to platform specific block
+  MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node.
+  MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change.
+
+  PCI_ADDR PciAddr;                ///< PCI address for this node
+  TSEFO *NBRegTable;               ///< contains all bit field definitions
+
+  UINT8 Node; ///< current node.
+  UINT8 Dct; ///< current DCT.
+  UINT8 Channel; ///< current channel.
+  UINT8 DctCount; ///< number of DCTs on the current NB.
+  UINT8 ChannelCount; ///< number of channels per DCT of the current NB.
+  UINT8 NodeCount; ///< number of Nodes supported
+  UINT8 CsPerDelay;   ///< number of CS controlled per set of delay registers.
+  UINT8 CsPerChannel; ///< number of CS per channel.
+  BOOLEAN Ganged; ///< mode for current MCT controller.
+  POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training.
+  BOOLEAN MemCleared; ///< memory clear flag.
+  UINT32  CPGInit; ///< continuous pattern generation flag.
+  UINT16  StartupSpeed; ///< startup speed for DDR3.
+  UINT16  RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take.
+  UINT32 McaNbCtlReg; ///< reserve MCA reports.
+  UINT32 VarMtrrHiMsk;   ///< variable MTRR mask for upper 32 bits.
+  UINT32 CsRegMsk;       ///< mask for CS base register
+  UINT32 NBClkFreq; ///< Current NB Clock frequency
+  UINT8  DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr
+  UINT8  TrainingSequenceIndex; ///< Index into the Training Sequence
+  RRW_SETTINGS RrwSettings;  ///<Settings for Reliable Read/Write mode
+  UINT8 TotalRdDQSDlyRange;   ///< Max number of RdDQS Delays
+  INT16 MinRxEnSeedGross; ///< Minimum value of the Receiver Enable
+  INT16 MaxRxEnSeedTotal; ///< Maximum value of the Receiver Enable
+  UINT8 TotalMaxVrefRange;       ///< Max number of Vref settings
+  UINT8 MaxSeedCount; ///< Max number of Data patterns to be generated
+  UINT8 Vref;            ///< Vref setting
+  UINT8 RdDqsDly;        ///< RdDQSDly setting
+  UINT16 MaxFreqVDDIO[VOLT1_25 + 1]; ///< Max Frequency each voltage supports.
+  UINT32 PhaseLaneMask;   ///< Lane Mask for Inphase and 180 phase registers
+  UINT8 MaxDiamondStep;  ///< Maximum Diamond step Size
+  UINT8 CurrentAggressorCSTarget[MAX_CHANNELS_PER_SOCKET]; ///< Current Aggressor CS targeted
+  UINT8 MaxAggressorCSEnabled[MAX_CHANNELS_PER_SOCKET]; ///< Maximum Number of Aggressor CS targeted
+  UINT8 MaxAggressorDimms[MAX_CHANNELS_PER_SOCKET];  ///< Maximum Number of Aggressor CS DIMMs
+  UINT8 InitialAggressorCSTarget[MAX_CHANNELS_PER_SOCKET];  ///< Initial Number of the first CS Aggressor
+  BOOLEAN OrigDisAutoRefreshState; ///< Original state of Dis Auto Refresh
+  BOOLEAN Execute1dMaxRdLatTraining;    ///< Indicates if 1D training should be executed
+  BOOLEAN Override2DTraining;                  ///< 2D training has been overriden
+
+  MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE.
+  MEM_DCT_CACHE *DctCachePtr;    ///< pointer to current Node's Node struct
+
+  /* Temporary storage */
+  BOOLEAN   ClToNbFlag;        ///< is used to restore ClLinesToNbDis bit after memory
+  UINT8     NbFreqChgState;    ///< is used as a state index in NB frequency change state machine
+  UINT32    NbPsCtlReg;        ///< is used to save/restore NB Pstate control register
+  MEM_PSTATE MemPstate;        ///< is used to save current memory Pstate context
+  MEM_PSTATE_STAGE MemPstateStage; ///< is used to save the current stage status of memory pstate
+  RDDQSDLY_RTN_STAT   RdDqsDlyRetrnStat;    ///< is used to check if RdDqsDly training needs to be restarted
+  CONST UINT32 *RecModeDefRegArray;   ///< points to an array of default register values that are set for recovery mode
+  struct _MEM_DRAM_INFO  *DevInfoArray;   ///< points to an array of DRAM device info
+
+  ///< Determines if code should be executed on a give NB
+  BOOLEAN IsSupported[EnumSize];
+  BOOLEAN (*FamilySpecificHook[NumberOfHooks]) (struct _MEM_NB_BLOCK *NBPtr, VOID *OptParam);   ///< This array of pointers point to
+                                                                                                ///< family specific functions.
+
+  /* PUBLIC functions */
+  VOID (*SwitchDCT) (struct _MEM_NB_BLOCK *NBPtr, UINT8 DCT); ///< Switch to current DCT.
+  VOID (*SwitchChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Channel); ///< Switch to current channel.
+  VOID (*SetMaxLatency) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxRcvEnDly); ///< Set Max Rd Latency.
+  VOID (*getMaxLatParams) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxDlyForMaxRdLat, UINT16 *MinDly, UINT16 *MaxDly, UINT16 *DlyBias); ///< retrieves the Max latency parameters.
+  BOOLEAN (*GetSysAddr) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver, UINT32 *Addr); ///< Get system address for training dimm.
+  BOOLEAN (*RankEnabled) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver); ///< Check if a rank has been enabled.
+  BOOLEAN (*InitializeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< MCT initialization.
+  BOOLEAN (*FinalizeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< sets final values in BUCFG and BUCFG2.
+  BOOLEAN (*InitMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< main entry call for memory initialization.
+  VOID (*SendMrsCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send MRS command.
+  VOID (*sendZQCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send ZQ command.
+  VOID (*TrainingFlow) (struct _MEM_NB_BLOCK *NBPtr); ///< Set the training flow control
+  VOID (*WritePattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT8 Pattern[], UINT16 ClCount); ///< Write training pattern.
+  VOID (*ReadPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT32 Address, UINT16 ClCount); ///< Read training pattern.
+  VOID (*GenHwRcvEnReads) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address);  ///< generates a continuous burst of reads during HW RcvEn training.
+  UINT16 (*CompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern.
+  UINT16 (*InsDlyCompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern using 1 beat offset to check for insertion delay
+  BOOLEAN (*StitchMemory) (struct _MEM_NB_BLOCK *NBPtr); ///< combines all the memory into a contiguous map.
+  VOID (*ProgramCycTimings) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with SPD timings.
+  BOOLEAN (*AutoConfig) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with configuration parameters
+  BOOLEAN (*PlatformSpec) (struct _MEM_NB_BLOCK *NBPtr); ///< programs platform specific parameters.
+  VOID (*DisableDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< disable a DCT if no dimm presents.
+  VOID (*StartupDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< start a DCT.
+  VOID (*SyncTargetSpeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Check and sync the target speed of all channels of this node.
+  VOID (*ChangeFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Frequency change sequence.
+  BOOLEAN (*RampUpFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change frequency to the next supported level.
+  BOOLEAN (*ChangeNbFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change NB frequency.
+  VOID (*PhyFenceTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy fence training.
+  BOOLEAN (*SyncDctsReady) (struct _MEM_NB_BLOCK *NBPtr); ///< Synchronize DCTs.
+  BOOLEAN (*HtMemMapInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Memory map initialization.
+  VOID (*SyncAddrMapToAllNodes) (struct _MEM_NB_BLOCK *NBPtr); ///< copies the Node 0 map to all the other nodes.
+  BOOLEAN (*CpuMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting.
+  VOID (*BeforeDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed before DQS training.
+  VOID (*AfterDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed after DQS training.
+  BOOLEAN (*OtherTiming) (struct _MEM_NB_BLOCK *NBPtr); ///< setting non-spd timing.
+  VOID (*UMAMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting needed for UMA platform.
+  VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support.
+  UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket.
+  VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT.
+  UINT32 (*GetSysAddrRec) ( VOID ); ///< Get system address for training.
+  VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node.
+  VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB.
+  VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size.
+  VOID (*GetTrainDlyParms) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, TRN_DLY_PARMS *Parms); ///< Retrieve Specific Delay range info for current NB under current conditions.
+  AGESA_STATUS (*TrainingPatternInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize the training Pattern
+  AGESA_STATUS (*TrainingPatternFinalize) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize the training Pattern
+  BOOLEAN (*GetApproximateWriteDatDelay) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Index, UINT8 *Value); ///< Retrieve the next WrDat Delay Approximation
+  VOID (*FlushPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT16 ClCount);  ///<Flush the training pattern
+  UINT8 (*MinDataEyeWidth) (struct _MEM_NB_BLOCK *NBPtr);  ///<Get Min Data Eye Width in 32nds of a UI
+  VOID (*MemNCapSpeedBatteryLife) (struct _MEM_NB_BLOCK *NBPtr); ///< Caps speed based on battery life check.
+  UINT32 (*GetUmaSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Get Uma Size
+  UINT8 (*GetMemClkFreqId) (struct _MEM_NB_BLOCK *NBPtr, UINT16 Speed); ///< Translate MemClk frequency in MHz to MemClkFreq value
+  VOID (*EnableSwapIntlvRgn) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Base, UINT32 Limit); ///< Enable swapped interleaving region
+  BOOLEAN (*ChangeNbFrequencyWrap) (struct _MEM_NB_BLOCK *NBPr, UINT32 NBPstate); ///< Wrapper for NB Pstate change function
+  VOID (*WaitXMemClks) (struct _MEM_NB_BLOCK *NBPr, UINT32 MemClkCount); ///< Waits a specified number of MemClks
+  VOID (*ProgramNbPsDependentRegs) (struct _MEM_NB_BLOCK *NBPtr); ///< Programs NB Pstate dependent registers
+  VOID (*AllocateC6Storage) (struct _MEM_NB_BLOCK *NBPtr); ///< Allocates DRAM region for Core C6
+
+  /* PUBLIC Get/Set register field functions */
+  UINT32 (*GetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName); ///< Pci register bit field read.
+  VOID (*SetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field write.
+  BOOLEAN (*BrdcstCheck) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast read.
+  VOID (*BrdcstSet) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast write.
+  VOID (*PollBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Field, UINT32 MicroSecond, BOOLEAN IfBroadCast); ///< Poll a Pci register bitfield.
+  UINT32 (*GetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar); ///< Training register bit field read.
+  VOID (*SetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Value); ///< Training register bit field write.
+  AGESA_STATUS (*InitRecovery) (struct _MEM_NB_BLOCK *NBPtr); ///< Recover mode memory init
+  VOID (*MemRecNInitializeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize MCT changes
+  VOID (*MemRecNFinalizeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize MCT changes
+  VOID (*MemNInitPhyComp) (struct _MEM_NB_BLOCK *NBPtr); ///< Init Phy compensation
+  VOID (*MemNBeforeDramInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Before Dram init
+  BOOLEAN (*MemNIsIdSupportedNb) (struct _MEM_NB_BLOCK *NBPtr, CPU_LOGICAL_ID *LogicalIdPtr); ///< Determines if a given CPU id is supported
+  BOOLEAN (*MemNPlatformSpecificFormFactorInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Platform specific functions
+  VOID (*MemNSetOtherTimingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Set non-spd timings
+  VOID (*MemNBeforePlatformSpecNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Apply settings prior to platform specific settings
+  UINT32 (*MemNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< Sets a register value
+  UINT32 (*MemNcmnGetSetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< Sets a training delay field
+  VOID (*MemPPhyFenceTrainingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy Fence training
+  VOID (*MemPNodeMemBoundaryNb) (struct _MEM_NB_BLOCK *NBPtr, UINT32 *NodeSysLimit); ///< Phy Fence training
+  UINT32 (*MemRecNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< This functions sets bit fields in recover mode
+  UINT32 (*MemRecNcmnGetSetTrainDlyNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< This functions sets bit fields in recover mode
+  VOID (*MemRecNSwitchDctNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< S3 Exit self refresh register
+  VOID (*MemNPFenceAdjustNb) (struct _MEM_NB_BLOCK *NBPtr, INT16 *Value16); ///< Adjust Avg PRE value of Phy fence training
+  VOID (*MemNPrepareRcvrEnDlySeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Seed valude for HW RxEn training
+  UINT8 (*MemNGetDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dram Term value
+  UINT8 (*MemNGetDynDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dynamic Dram Term value
+  VOID (*MemNSaveMR0) (struct _MEM_NB_BLOCK *NBPtr, UINT32 MrsAddress); ///< Save MR0 during memory initialization
+  UINT32 (*MemNGetMR0CL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[CL] value
+  UINT32 (*MemNGetMR0WR) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[WR] value
+  UINT32 (*MemNGetMR2CWL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR2[CWL] value
+  UINT32 (*InPhaseCompareRdDqs2DPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< InPhase Compare training pattern for RdDQS 2D training
+  UINT32 (*Phase180CompareRdDqs2DPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< 180 Compare training pattern for RdDQS 2D training
+  VOID (*AgressorContinuousWrites) (struct _MEM_NB_BLOCK *NBPtr, UINT8 SeedCount, BOOLEAN TurnOnInfinite); ///< Enables/Disables continuous writes on unused agressor channels
+  UINT32 (*GetPrbs2dRdDqsSeed) (struct _MEM_NB_BLOCK *NBPtr, UINT8 SeedCount); ///< Prbs Seed for 2d RdDqs training
+  VOID (*DisableInfiniteWritePattern) (struct _MEM_NB_BLOCK *NBPtr); ///< Disables infinite Write training pattern.
+  VOID (*EnableInfiniteWritePattern) (struct _MEM_NB_BLOCK *NBPtr); ///< Enables infinite training pattern.
+  VOID (*InitializeRdDqs2dVictimContinuousWrites) (struct _MEM_NB_BLOCK *NBPtr); ///< Initializes victim infinite training pattern for RdDqs2d Training.
+  VOID (*FinalizeRdDqs2dVictimContinuousWrites) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalizes victim infinite training pattern for RdDqs2d Training.
+  VOID (*InitializeRdDqs2dVictimChipSelContinuousWrites) (struct _MEM_NB_BLOCK *NBPtr); ///< Initializes victim infinite training pattern for RdDqs2d Training for victim CS.
+  VOID (*StartRdDqs2dVictimContinuousWrites) (struct _MEM_NB_BLOCK *NBPtr , UINT8 SeedCount); ///< Starts victim infinite training pattern for RdDqs2d Training.
+  BOOLEAN (*ConfigureDCTForGeneral) (struct _MEM_NB_BLOCK *NBPtr); ///< Configure DCT For General use.
+  BOOLEAN (*ConfigureDCTForTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< Configure DCT For Training.
+  BOOLEAN (*ConfigureDCTNonExplicitSeq) (struct _MEM_NB_BLOCK *NBPtr); ///< Configure DCT for Non Explicit Seq.
+  BOOLEAN (*SynchronizeChannels) (struct _MEM_NB_BLOCK *NBPtr); ///< Synchronize Channels.
+  BOOLEAN (*ConfigureDCTNormal) (struct _MEM_NB_BLOCK *NBPtr); ///< Configure DCT for Normal operation.
+  BOOLEAN (*MemN2DRdDQSDataCollection) (struct _MEM_NB_BLOCK *NBPtr); ///< 2D training data collection method
+  UINT32 (*MemNGetMemoryWidth) (struct _MEM_NB_BLOCK *NBPtr); ///< Get memory width
+} MEM_NB_BLOCK;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+MemNInitNBDataNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSwitchDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemNSwitchChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+UINT32
+MemNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  );
+
+VOID
+MemNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+BOOLEAN
+MemNBrdcstCheckNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNBrdcstSetNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+
+UINT32
+MemNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  );
+
+VOID
+MemNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+MemNRankEnabledNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver
+  );
+
+UINT8 MemNGetSocketRelativeChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  );
+
+VOID
+MemNPhyFenceTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNGetMCTSysAddrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver,
+  OUT      UINT32 *AddrPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNStitchMemoryNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDCTUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNStartupDCTUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNChangeFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNRampUpFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramCycTimingsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNGetMaxLatParamsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  );
+
+UINT16
+MemNTotalSyncComponentsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  );
+
+VOID
+MemNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSwapBitsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSwapBitsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNTrainPhyFenceNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitPhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNGetTrainDlyParmsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  );
+
+
+VOID
+MemNGetTrainDlyParmsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  );
+
+VOID
+MemNBeforeDQSTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNcmnGetSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+UINT32
+MemNcmnGetSetTrainDlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+UINT32
+MemNcmnGetSetTrainDlyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+VOID
+MemNSyncTargetSpeedNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNSyncDctsReadyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNHtMemMapInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTrdrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTwrwrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTwrrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTrwtTONb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTrwtWBNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPowerDownCtlNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNCPUMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNUMAMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSyncAddrMapToAllNodesNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNInitMCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNTechBlockSwitchNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemRecNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  );
+
+VOID
+MemRecNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+MemRecNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  );
+
+VOID
+MemRecNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+MemRecNAutoConfigNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemRecNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  );
+
+VOID
+MemRecNSetDramOdtNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       ODT_MODE OdtMode,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 TargetCS
+  );
+
+VOID
+MemRecNSendMrsCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+
+VOID
+MemRecNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNContReadPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+AGESA_STATUS
+MemRecNMemInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNCPUMemRecTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemRecNGetMCTSysAddrNb ( VOID );
+
+UINT32
+MemRecGetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+INT8
+MemNGetOptimalCGDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly1,
+  IN       TRN_DLY_TYPE TrnDly2
+  );
+
+VOID
+MemNPollBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field,
+  IN       UINT32 MicroSecond,
+  IN       BOOLEAN IfBroadCast
+  );
+
+VOID
+MemNSetEccSymbolSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDQSTiming3Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDQSTiming2Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNRecTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNRecTrainingFlowClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNRecTrainingFlowUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemRecNTotalSyncComponentsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNStartupDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+
+VOID
+MemRecNPhyVoltageLevelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+AGESA_STATUS
+MemNTrainingPatternInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNGetApproximateWriteDatDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Index,
+  IN OUT   UINT8 *Value
+  );
+
+AGESA_STATUS
+MemNTrainingPatternFinalizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNFlushPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+UINT8
+MemNCSPerDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNMinDataEyeWidthNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT16
+MemNCompareTestPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+UINT16
+MemNInsDlyCompareTestPatternNb (
+  IN       MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+
+UINT32
+MemNGetUmaSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNSetMTRRUmaRegionUCNb  (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 *BasePtr,
+  IN OUT   UINT32 *LimitPtr
+  );
+
+UINT8
+MemNGetMemClkFreqIdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  );
+
+UINT8
+MemNGetMemClkFreqIdClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  );
+
+UINT8
+MemNGetMemClkFreqIdUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  );
+
+UINT16
+MemNGetMemClkFreqUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 FreqId
+  );
+
+BOOLEAN
+MemNGetPlatformCfgNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramCycTimingsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+INT16
+MemNCalcCDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDlyType1,
+  IN       TRN_DLY_TYPE TrnDlyType2,
+  IN       BOOLEAN SameDimm,
+  IN       BOOLEAN DiffDimm
+  );
+
+VOID
+MemNChangeFrequencyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNChangeFrequencyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramNbPstateDependentRegistersUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramNbPstateDependentRegistersClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNAllocateC6StorageClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNAllocateC6StorageUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPhyVoltageLevelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPhyFenceTrainingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPFenceAdjustUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   INT16 *Value16
+  );
+
+VOID
+MemNInitPhyCompClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNTotalSyncComponentsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNEnableSwapIntlvRgnNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN          UINT32 Base,
+  IN          UINT32 Limit
+  );
+
+VOID
+MemNPhyPowerSavingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPhyPowerSavingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSetASRSRTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPrepareRcvrEnDlySeedNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNChangeNbFrequencyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNChangeNbFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWaitXMemClksNb (
+  IN OUT   MEM_NB_BLOCK  *NBPtr,
+  IN       UINT32 MemClkCount
+  );
+
+BOOLEAN
+memNSequenceDDR3Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT16
+GetTrainDlyFromHeapNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDlyType,
+  IN       DRBN Drbn
+  );
+
+BOOLEAN
+MemNTrainingFlowUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNSetupHwTrainingEngineUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID* OptParam
+  );
+
+BOOLEAN
+MemNBeforePhyFenceTrainingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNReEnablePhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+UINT8
+MemNGetDramTermNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  );
+
+UINT8
+MemNGetDynDramTermNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  );
+
+UINT32
+MemNGetMR0CLNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNGetMR0WRNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNGetMR2CWLNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDctCfgSelectUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *Dct
+  );
+
+BOOLEAN
+MemNGetMaxDdrRateUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       VOID *DdrMaxRate
+  );
+
+BOOLEAN
+MemRecNReEnablePhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+UINT32
+MemRecNcmnGetSetTrainDlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+VOID
+MemNSetTxpNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAdjustTxpdllClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNCalcWrDqDqsEarlyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+VOID
+MemNGetTrainDlyParmsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  );
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNChangeNbFrequencyWrapUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 NBPstate
+  );
+
+VOID
+MemNForcePhyToM0Unb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramCycTimingsUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNSetSkewMemClkUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+VOID
+MemNSendMrsCmdUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetDramTermTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  );
+
+UINT8
+MemNGetDynDramTermTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSel
+  );
+
+UINT32
+MemNGetMR2CWLUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNGetMR0CLTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNGetMR0WRTblDrvNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNRampUpFrequencyUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAfterSaveRestoreUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNAdjustRdDqsDlyOffsetUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *Offset
+  );
+
+BOOLEAN
+MemNCalcWrDqDqsEarlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNSlot1MaxRdLatTrainClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *TestAddrRJ16
+  );
+
+VOID
+MemNC6AdjustMSRs (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNInitializeRxEnSeedlessTrainingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNInitialzeRxEnSeedlessByteLaneErrorUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+VOID
+MemNPhyPowerSavingMPstateUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNChangeMemPStateContextNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSTATE MemPstate
+  );
+
+VOID
+MemNDramPowerMngTimingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *IsBefore
+  );
+
+
+BOOLEAN
+MemNAllocateNBRegTableNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       NB_REG_TAB_HANDLE  Handle
+  );
+
+VOID
+MemTResetRcvFifoUnb (
+  IN OUT   struct _MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dummy
+  );
+
+VOID
+MemRecNContReadPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemRecNContWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+UINT16
+MemRecNCompareTestPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+BOOLEAN
+MemNResetRxFifoPtrClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+
+UINT32
+MemNInPhaseCompareRdDqs2DPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+UINT32
+MemN180CompareRdDqs2DPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+VOID
+MemNAgressorContinuousWritesUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 SeedCount,
+  IN       BOOLEAN TurnOnInfinite
+  );
+
+UINT32
+MemNGetPrbs2dRdDqsSeedUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 SeedCount
+  );
+
+
+VOID
+MemNRrwPrechargeCmd (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 Bank
+  );
+
+VOID
+MemNRrwActivateCmd (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 Bank,
+  IN       UINT32 RowAddress
+  );
+
+VOID
+MemNStartRdDqs2dVictimContinuousWritesUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 SeedCount
+  );
+
+VOID
+MemNInitializeRdDqs2dVictimChipSelContinuousWritesUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNFinalizeRdDqs2dVictimContinuousWritesUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitializeRdDqs2dVictimContinuousWritesUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAdjustWrDqsBeforeSeedScalingUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *WrDqsBias
+  );
+
+BOOLEAN
+MemNDefaultFamilyHookNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+VOID
+MemNBrdcstSetUnConditionalNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+
+VOID
+MemNContReadPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNContWritePatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+UINT16
+MemNCompareTestPatternUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+UINT32
+MemNGetMemoryWidthUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MN_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h
new file mode 100644
index 0000000000..5cc4d5e055
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h
@@ -0,0 +1,356 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnreg.h
+ *
+ * Definitions for whole register tokens
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 61256 $ @e \$Date: 2011-11-03 15:06:11 -0500 (Thu, 03 Nov 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNREG_H_
+#define _MNREG_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Registers used in memory initialization
+typedef enum {
+  // NB_REG identifiers
+  NbRegRangeStart = BFEndOfList, ///< -------------------------- Start of NB_REG range
+  RegDramBase0,                  ///< Register DramBase0
+  RegDramLimit0,                 ///< Register DramLimit0
+  RegDramBaseHi0,                ///< Register DramBaseHi0
+  RegDramLimitHi0,               ///< Register DramLimitHi0
+  RegDramHoleAddr,               ///< Register DramHoleAddr
+  RegDctCfgSel,                  ///< Register DctCfgSel
+  RegDramBaseSysAddr,            ///< Register DramBaseSysAddr
+  RegDramLimitSysAddr,           ///< Register DramLimitSysAddr
+
+  RegDramCtlrBase0,              ///< Register DramCtlrBase0
+  RegDramCtlrBase1,              ///< Register DramCtlrBase1
+  RegDramCtlrBase2,              ///< Register DramCtlrBase2
+  RegDramCtlrBase3,              ///< Register DramCtlrBase3
+
+  RegDramCtlrLimit0,             ///< Register DramCtlrLimit0
+  RegDramCtlrLimit1,             ///< Register DramCtlrLimit1
+  RegDramCtlrLimit2,             ///< Register DramCtlrLimit2
+  RegDramCtlrLimit3,             ///< Register DramCtlrLimit3
+
+  RegDctHiAddrOffset0,           ///< Register DctHiAddrOffset0
+  RegDctHiAddrOffset1,           ///< Register DctHiAddrOffset1
+  RegDctHiAddrOffset2,           ///< Register DctHiAddrOffset2
+  RegDctHiAddrOffset3,           ///< Register DctHiAddrOffset3
+
+  RegDramCtl,                    ///< Register DramCtl
+  RegDramInit,                   ///< Register DramInit
+  RegDramBankAddr,               ///< Register DramBankAddr
+  RegDramMRS,                    ///< Register DramMRS
+  RegDramTmgLo,                  ///< Register DramTmgLo
+  RegDramTmgHi,                  ///< Register DramTmgHi
+  RegDramConfigLo,               ///< Register DramConfigLo
+  RegDramConfigHi,               ///< Register DramConfigHi
+
+  RegDctAddlOffset,              ///< Register DctAddlOffset
+  RegDctAddlData,                ///< Register DctAddlData
+  RegDctAddlOffsetBrdcst,        ///< Register DctAddlOffset for broadcast
+  RegDctAddlDataBrdcst,          ///< Register DctAddlData for broadcast
+
+  RegDctTempThrottle,            ///< Register DctTempThrottle
+  RegDramCtlrMisc2,              ///< Register DramCtlrMisc2
+  RegTraceBufferCtlr,            ///< Register TraceBufferCtlr
+  RegSwapIntLvRgn,               ///< Register SwapIntLvRgn
+  RegMctCfgLo,                   ///< Register MctCfgLo
+  RegMctCfgHi,                   ///< Register MctCfgHi
+  RegExtMctCfgLo,                ///< Register ExtMctCfgLo
+  RegExtMctCfgHi,                ///< Register ExtMctCfgHi
+  RegDramNbPstate,               ///< Register DramNbPstate
+
+  RegGmcToDctCtl0,               ///< Register GmcToDctCtl0
+  RegGmcToDctCtl1,               ///< Register GmcToDctCtl1
+  RegGmcToDctCtl2,               ///< Register GmcToDctCtl2
+
+  RegCSBaseAddr0,                ///< Register CSBaseAddr0
+  RegCSBaseAddr1,                ///< Register CSBaseAddr1
+  RegCSBaseAddr2,                ///< Register CSBaseAddr2
+  RegCSBaseAddr3,                ///< Register CSBaseAddr3
+  RegCSMask0,                    ///< Register CSMask0
+  RegCSMask1,                    ///< Register CSMask1
+  RegDramCtlrSelLo,              ///< Register DramCtlrSelLo
+  RegDramCtlrSelHi,              ///< Register DramCtlrSelHi
+
+  RegDdr3DramTmg0,               ///< Register Ddr3DramTmg0
+  RegDdr3DramTmg1,               ///< Register Ddr3DramTmg1
+  RegDdr3DramTmg2,               ///< Register Ddr3DramTmg2
+  RegDdr3DramTmg3,               ///< Register Ddr3DramTmg3
+  RegDdr3DramTmg4,               ///< Register Ddr3DramTmg4
+  RegDdr3DramTmg5,               ///< Register Ddr3DramTmg5
+  RegDdr3DramTmg6,               ///< Register Ddr3DramTmg6
+  RegDdr3DramTmg7,               ///< Register Ddr3DramTmg7
+  RegDdr3DramTmg8,               ///< Register Ddr3DramTmg8
+  RegDdr3DramTmg9,               ///< Register Ddr3DramTmg9
+  RegDdr3DramTmg10,              ///< Register Ddr3DramTmg10
+  RegDdr3DramPwrMng1,            ///< Register Ddr3DramPwrMng1
+  RegDdr3DramOdtCtl,             ///< Register Ddr3DramOdtClt
+  RegMemPsCtlSts,                ///< Register MemPsCtlSts
+
+  RegDramLpbkTrnCtl,             ///< Register DramLpbkTrnCtl
+  RegTargetABase,                ///< Register TargetABase
+  RegDramCmd0,                   ///< Register DramCmd0
+  RegDramCmd1,                   ///< Register DramCmd1
+  RegDramCmd2,                   ///< Register DramCmd2
+  RegDramPRBS,                   ///< Register DramPRBS
+  RegDramStatus1,                ///< Register DramStatus1
+  RegDramDqMaskLo,               ///< Register DramDqMaskLo
+  RegDramDqMaskHi,               ///< Register DramDqMaskHi
+  RegDQErrLo,                    ///< Register DQErrLo
+  RegDQErrHi,                    ///< Register DQErrHi
+
+  RegDramControl,                ///< Register DRAM Control
+
+
+  RegNbCap2,                     ///< Register NbCap2
+  RegNbPstateCtl,                ///< Register NbPstateCtl
+  RegNbPstateStatus,             ///< Register NbPstateStatus
+  RegNbPstate0,                  ///< Register NB Pstate 0
+  RegNbPstate1,                  ///< Register NB Pstate 1
+  RegNbPstate2,                  ///< Register NB Pstate 2
+  RegNbPstate3,                  ///< Register NB Pstate 3
+
+  NbRegRangeEnd,                 ///< -------------------------- End of NB_REG range
+
+                                 // DCT_PHY_REG identifiers
+  DctPhyRegRangeStart,           ///< -------------------------- Start of DCT_PHY_REG range
+  RegRxCtl1,                     ///< Register RxCtl1
+  RegDqDqsRxCtl,                 ///< Register DqDqsRxCtl
+  RegRdPtrInitVal,               ///< Register RdPtrInitVal
+  RegDataRdPtrInitVal,           ///< Register DataRdPtrInitVal
+  RegDataRdPtrOffset,            ///< Register DataRdPtrOffset
+
+
+  DctPhyRegRangeEnd,             ///< -------------------------- End of DCT_PHY_REG range
+
+  RegIdLimit                     ///< Total number of register identifiers
+
+} REG_BF_NAME;
+
+/// Bit field location
+typedef struct {
+  UINT32  LoBit: 6;         ///< Low bit of the bit field
+  UINT32  HiBit: 6;         ///< High bit of the bit field
+  UINT32  RegIndex: 10;     ///< Register that the bit field is on
+  UINT32  Reserved: 9;      ///< Reserved
+  UINT32  Linked: 1;        ///< 1: The bit field has high bits defined in the very next Bf identifier
+  ///< 0: The bit field has no further extension
+} BF_LOCATION;
+
+/**
+  REG_DEF(TableName, RegIndex, Addr)
+
+  @param[in]    TableName
+  @param[in]    RegIndex
+  @param[in]    Addr
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define REG_DEF(TableName, RegIndex, Addr) \
+  TableName[RegIndex] = Addr
+
+/**
+  _BF_DEF(TableName, RegIndex, BfIndex, Hi, Lo)
+
+  @param[in]    TableName
+  @param[in]    RegIndex
+  @param[in]    BfIndex
+  @param[in]    Hi
+  @param[in]    Lo
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define _BF_DEF(TableName, RegIndex, BfIndex, Hi, Lo) \
+  TableName[BfIndex] = ( \
+    ((UINT32) RegIndex << 12) | ( \
+      (Hi > Lo) ? (\
+        (((UINT32) Hi << 6) | (UINT32) Lo) \
+      ) : ( \
+        (((UINT32) Lo << 6) | (UINT32) Hi) \
+      ) \
+    ) \
+  )
+
+/**
+  LINK_BF(TableName, LowerBfIndex, HigherBfIndex):
+  This is one way link: any write to LowerBfIndex would write to HigherBfIndex,
+                        but NOT the other way around.
+  Requirement: LowerBfIndex must be declared *right* before HigherBfIndex.
+
+  @param[in]    TableName
+  @param[in]    LowerBfIndex
+  @param[in]    HigherBfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define LINK_BF(TableName, LowerBfIndex, HigherBfIndex) { \
+  ASSERT (LowerBfIndex < BFEndOfList); \
+  ASSERT (HigherBfIndex < BFEndOfList); \
+  ASSERT (LowerBfIndex == (HigherBfIndex - 1)) ; \
+  TableName[LowerBfIndex] |= ((UINT32) 1) << 31; \
+}
+
+/**
+  S3_SAVE_PRE_ESR(RegBfIndex)
+  Specifies that RegBfIndex should be saved for S3 resume
+
+  @param[in]    RegBfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define S3_SAVE_PRE_ESR(RegBfIndex)    ((RegBfIndex) | ((UINT32) 1 << 31))
+#define GET_PRE_ESR_FLAG(RegBfIndex)   (((RegBfIndex) >> 31) & 1)
+
+/**
+  S3_SAVE_POST_ESR(RegBfIndex)
+  Specifies that RegBfIndex should be saved for S3 resume
+
+  @param[in]    RegBfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define S3_SAVE_POST_ESR(RegBfIndex)   ((RegBfIndex) | ((UINT32) 1 << 30))
+#define GET_POST_ESR_FLAG(RegBfIndex)  (((RegBfIndex) >> 30) & 1)
+
+/**
+  VOLATILE_BF(RegBfIndex)
+  Specifies that RegBfIndex cannot be cached, but must be accessed right away.
+
+  @param[in]    RegBfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define VOLATILE_BF(RegBfIndex)           ((RegBfIndex) | ((UINT32) 1 << 28))
+#define GET_VOLATILE_BF_FLAG(RegBfIndex)  (((RegBfIndex) >> 28) & 1)
+
+#define BC_MEM_PS   0x4
+#define BC_NB_PS    0x1
+#define BC_DIS      0xF
+#define GET_BROADCAST_FLAG(BfIndex)   (((BfIndex) >> 20) & 0xF)
+#define GET_BROADCAST_OVERRIDE(BfIndex)  (((BfIndex) >> 16) & 0xF)
+
+/**
+  SINGLE_INST(BfIndex)
+  Specifies that set function should only broadcast to Mem Pstate p of bit field BfIndex
+
+  @param[in]    BfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define SINGLE_INST(BfIndex) ((BfIndex) | ((UINT32) BC_DIS << 20))
+
+/**
+  PER_MEM_PS(p, BfIndex)
+  Specifies that set function should only broadcast to Mem Pstate p of bit field BfIndex
+
+  @param[in]    p
+  @param[in]    BfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define PER_MEM_PS(p, BfIndex) ((BfIndex) | ((UINT32) (p) << 16) | ((UINT32) BC_MEM_PS << 20))
+
+/**
+  PER_NB_PS(p, BfIndex)
+  Specifies that set function should only broadcast to NB Pstate p of bit field BfIndex
+
+  @param[in]    p
+  @param[in]    BfIndex
+
+  @return   REG_BF_ENC  Access params encrypted in REG_BF_ENC format.
+--*/
+#define PER_NB_PS(p, BfIndex) ((BfIndex) | ((UINT32) (p) << 16) | ((UINT32) BC_NB_PS << 20))
+#define NB_PS_PMU   8
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif  /* _MNREG_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mp.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mp.h
new file mode 100644
index 0000000000..1d3a530b39
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mp.h
@@ -0,0 +1,635 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mp.h
+ *
+ * Platform Specific common header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _MP_H_
+#define _MP_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Type of an entry for Dram Term table
+typedef struct {
+  UINT32 Speed; ///< BitMap for the supported speed
+  UINT8  Dimms; ///< BitMap for supported number of dimm
+  UINT8  QR_Dimms; ///< BitMap for supported number of QR dimm
+  UINT8  DramTerm; ///< DramTerm value
+  UINT8  QR_DramTerm; ///< DramTerm value for QR
+  UINT8  DynamicDramTerm; ///< Dynamic DramTerm
+} DRAM_TERM_ENTRY;
+
+/// Type of an entry for POR speed limit table
+typedef struct {
+  UINT16   DIMMRankType;  ///< Bitmap of Ranks
+  UINT8    Dimms;  ///< Number of dimm
+  UINT16    SpeedLimit_1_5V; ///< POR speed limit for 1.5V
+  UINT16    SpeedLimit_1_35V; ///< POR speed limit for 1.35V
+  UINT16    SpeedLimit_1_25V; ///< POR speed limit for 1.25V
+} POR_SPEED_LIMIT;
+
+/// UDIMM&RDIMM Max. Frequency
+typedef union {
+  struct {                       ///< PSCFG_MAXFREQ_ENTRY
+    UINT8 DimmPerCh;             ///< Dimm slot per chanel
+    UINT16 Dimms:4;              ///< Number of Dimms on a channel
+    UINT16 SR:4;                 ///< Number of single-rank Dimm
+    UINT16 DR:4;                 ///< Number of dual-rank Dimm
+    UINT16 QR:4;                 ///< Number of quad-rank Dimm
+    UINT16 Speed1_5V;            ///< Speed limit with voltage 1.5V
+    UINT16 Speed1_35V;           ///< Speed limit with voltage 1.35V
+    UINT16 Speed1_25V;           ///< Speed limit with voltage 1.25V
+  } _MAXFREQ_ENTRY;
+  struct {
+    UINT8 DimmSlotPerCh;
+    UINT16 CDN;                  ///< Condition
+    UINT16 Speed[3];             ///< Speed limit
+  } MAXFREQ_ENTRY;
+} PSCFG_MAXFREQ_ENTRY;
+
+///  LRDIMM Max. Frequency
+typedef union {
+  struct {                       ///< PSCFG_LR_MAXFREQ_ENTRY
+    UINT8 DimmPerCh;             ///< Dimm slot per chanel
+    UINT16 Dimms:4;              ///< Number of Dimms on a channel
+    UINT16 LR:12;                ///< Number of LR-DIMM
+    UINT16 Speed1_5V;            ///< Speed limit with voltage 1.5V
+    UINT16 Speed1_35V;           ///< Speed limit with voltage 1.35V
+    UINT16 Speed1_25V;           ///< Speed limit with voltage 1.25V
+  } _LR_MAXFREQ_ENTRY;
+  struct {
+    UINT8 DimmSlotPerCh;
+    UINT16 CDN;
+    UINT16 Speed[3];
+  } LR_MAXFREQ_ENTRY;
+} PSCFG_LR_MAXFREQ_ENTRY;
+
+/// UDIMM&RDIMM RttNom and RttWr
+typedef struct {
+  UINT64 DimmPerCh:8;          ///< Dimm slot per chanel
+  UINT64 DDRrate:32;           ///< Bitmap of DDR rate
+  UINT64 VDDIO:4;              ///< Bitmap of VDDIO
+  UINT64 Dimm0:4;              ///< Bitmap of rank type of Dimm0
+  UINT64 Dimm1:4;              ///< Bitmap of rank type of Dimm1
+  UINT64 Dimm2:4;              ///< Bitmap of rank type of Dimm2
+  UINT64 Dimm:4;               ///< Bitmap of rank type of Dimm
+  UINT64 Rank:4;               ///< Bitmap of rank
+  UINT8 RttNom:3;              ///< Dram term
+  UINT8 RttWr:5;               ///< Dynamic dram term
+} PSCFG_RTT_ENTRY;
+
+/// LRDIMM RttNom and RttWr
+typedef struct {
+  UINT64 DimmPerCh:8;          ///< Dimm slot per chanel
+  UINT64 DDRrate:32;           ///< Bitmap of DDR rate
+  UINT64 VDDIO:4;              ///< Bitmap of VDDIO
+  UINT64 Dimm0:4;              ///< Dimm0 population
+  UINT64 Dimm1:4;              ///< Dimm1 population
+  UINT64 Dimm2:12;             ///< Dimm2 population
+  UINT8 RttNom:3;              ///< Dram term
+  UINT8 RttWr:5;               ///< Dynamic dram term
+} PSCFG_LR_RTT_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM ODT pattern OF 1 DPC
+typedef struct {
+  UINT16 Dimm0;                ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
+  UINT32 RdODTCSHigh;          ///< RdODTCSHigh
+  UINT32 RdODTCSLow;           ///< RdODTCSLow
+  UINT32 WrODTCSHigh;          ///< WrODTCSHigh
+  UINT32 WrODTCSLow;           ///< WrODTCSLow
+} PSCFG_1D_ODTPAT_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM ODT pattern OF 2 DPC
+typedef struct {
+  UINT16 Dimm0:4;              ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
+  UINT16 Dimm1:12;             ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
+  UINT32 RdODTCSHigh;          ///< RdODTCSHigh
+  UINT32 RdODTCSLow;           ///< RdODTCSLow
+  UINT32 WrODTCSHigh;          ///< WrODTCSHigh
+  UINT32 WrODTCSLow;           ///< WrODTCSLow
+} PSCFG_2D_ODTPAT_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM ODT pattern OF 3 DPC
+typedef struct {
+  UINT16 Dimm0:4;              ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
+  UINT16 Dimm1:4;              ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
+  UINT16 Dimm2:8;              ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM
+  UINT32 RdODTCSHigh;          ///< RdODTCSHigh
+  UINT32 RdODTCSLow;           ///< RdODTCSLow
+  UINT32 WrODTCSHigh;          ///< WrODTCSHigh
+  UINT32 WrODTCSLow;           ///< WrODTCSLow
+} PSCFG_3D_ODTPAT_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM SlowMode, AddrTmgCtl and ODC
+typedef struct {
+  UINT64 DimmPerCh:8;          ///< Dimm slot per channel
+  UINT64 DDRrate:32;           ///< Bitmap of DDR rate
+  UINT64 VDDIO:4;              ///< Bitmap of VDDIO
+  UINT64 Dimm0:4;              ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
+  UINT64 Dimm1:4;              ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
+  UINT64 Dimm2:11;             ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM
+  UINT64 SlowMode:1;           ///< SlowMode
+  UINT32 AddTmgCtl;            ///< AddTmgCtl
+  UINT32 ODC;                  ///< ODC
+} PSCFG_SAO_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM 2D training config entry
+typedef struct {
+  UINT64 DimmPerCh:8;          ///< Dimm per channel
+  UINT64 DDRrate:32;           ///< Bitmap of DDR rate
+  UINT64 VDDIO:4;              ///< Bitmap of VDDIO
+  UINT64 Dimm0:4;              ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
+  UINT64 Dimm1:4;              ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
+  UINT64 Dimm2:11;             ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM
+  UINT64 Enable2D:1;           ///< SlowMode
+} PSCFG_S2D_ENTRY;
+
+/// UDIMM&RDIMM MR0[WR]
+typedef struct {
+  UINT8 Timing;                ///< Fn2_22C_dct[1:0][Twr]
+  UINT8 Value;                 ///< MR0[WR] : bit0 - bit2 available
+} PSCFG_MR0WR_ENTRY;
+
+/// UDIMM&RDIMM MR0[CL]
+typedef struct {
+  UINT8 Timing;                ///< Fn2_200_dct[1:0][Tcl]
+  UINT8 Value:3;               ///< MR0[CL] : bit0 - bit2 CL[3:1]
+  UINT8 Value1:5;              ///< MR0[CL] : bit3 CL[0]
+} PSCFG_MR0CL_ENTRY;
+
+/// UDIMM&RDIMM MR2[IBT]
+typedef struct {
+  UINT64 DimmPerCh:4;          ///< Dimm per channel
+  UINT64 DDRrate:32;           ///< Bitmap of DDR rate
+  UINT64 VDDIO:4;              ///< Bitmap of VDDIO
+  UINT64 Dimm0:4;              ///< Bitmap of dimm0 rank type
+  UINT64 Dimm1:4;              ///< Bitmap of dimm1 rank type
+  UINT64 Dimm2:4;              ///< Bitmap of dimm2 rank type
+  UINT64 Dimm:4;               ///< Bitmap of rank type of Dimm
+  UINT64 NumOfReg:4;           ///< Number of registers
+  UINT64 IBT:4;                 ///< MR2[IBT] value
+} PSCFG_MR2IBT_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM Operating Speed
+typedef struct {
+  UINT32 DDRrate;              ///< Bitmap of DDR rate
+  UINT8 OPSPD;                 ///< RC10[OperatingSpeed]
+} PSCFG_OPSPD_ENTRY;
+
+/// LRDIMM IBT
+typedef struct {
+  UINT64 DimmPerCh:4;          ///< Dimm per channel
+  UINT64 DDRrate:32;           ///< Bitmap of DDR rate
+  UINT64 VDDIO:4;              ///< Bitmap of VDDIO
+  UINT64 Dimm0:4;              ///< Dimm0 population
+  UINT64 Dimm1:4;              ///< Dimm1 population
+  UINT64 Dimm2:4;              ///< Dimm2 population
+  UINT64 F0RC8:3;              ///< F0RC8
+  UINT64 F1RC0:3;              ///< F1RC0
+  UINT64 F1RC1:3;              ///< F1RC1
+  UINT64 F1RC2:3;              ///< F1RC2
+} PSCFG_L_IBT_ENTRY;
+
+/// LRDIMM F0RC13[NumPhysicalRanks]
+typedef struct {
+  UINT8 NumRanks:3;            ///< NumRanks
+  UINT8 NumPhyRanks:5;         ///< NumPhyRanks
+} PSCFG_L_NPR_ENTRY;
+
+/// LRDIMM F0RC13[NumLogicalRanks]
+typedef struct {
+  UINT16 NumPhyRanks:3;        ///< NumPhyRanks
+  UINT16 DramCap:4;            ///< DramCap
+  UINT16 NumDimmSlot:9;        ///< NumDimmSlot
+  UINT8 NumLogRanks;           ///< NumLogRanks
+} PSCFG_L_NLR_ENTRY;
+
+/// UDIMM&RDIMM&LRDIMM pass1 seed entry
+typedef struct {
+  UINT8 DimmPerCh;             ///< Dimm per channel
+  UINT8 Channel;               ///< Channel#
+  UINT16 SeedVal;              ///< Seed value
+} PSCFG_SEED_ENTRY;
+
+/// Platform specific configuration types
+typedef enum {
+  PSCFG_MAXFREQ,               ///< PSCFG_MAXFREQ
+  PSCFG_LR_MAXFREQ,            ///< PSCFG_LR_MAXFREQ
+  PSCFG_RTT,                   ///< PSCFG_RTT
+  PSCFG_LR_RTT,                ///< PSCFG_LR_RTT
+  PSCFG_ODT_PAT_1D,            ///< PSCFG_ODT_PAT_1D
+  PSCFG_ODT_PAT_2D,            ///< PSCFG_ODT_PAT_2D
+  PSCFG_ODT_PAT_3D,            ///< PSCFG_ODT_PAT_3D
+  PSCFG_LR_ODT_PAT_1D,         ///< PSCFG_LR_ODT_PAT_1D
+  PSCFG_LR_ODT_PAT_2D,         ///< PSCFG_LR_ODT_PAT_2D
+  PSCFG_LR_ODT_PAT_3D,         ///< PSCFG_LR_ODT_PAT_3D
+  PSCFG_SAO,                   ///< PSCFG_SAO
+  PSCFG_LR_SAO,                ///< PSCFG_LR_SAO
+  PSCFG_MR0WR,                 ///< PSCFG_MR0WR
+  PSCFG_MR0CL,                 ///< PSCFG_MR0CL
+  PSCFG_RC2IBT,                ///< PSCFG_RC2IBT
+  PSCFG_RC10OPSPD,             ///< PSCFG_RC10OPSPD
+  PSCFG_LR_IBT,                ///< PSCFG_LR_IBT
+  PSCFG_LR_NPR,                ///< PSCFG_LR_NPR
+  PSCFG_LR_NLR,                ///< PSCFG_LR_NLR
+  PSCFG_S2D,                   ///< PSCFG_S2D
+  PSCFG_WL_PASS1_SEED,         ///< PSCFG_WL_PASS1_SEED
+  PSCFG_HWRXEN_PASS1_SEED,     ///< PSCFG_HWRXEN_SEED
+
+  // The type of general table entries could be added between
+  // PSCFG_GEN_START and PSCFG_GEN_END so that the PSCGen routine
+  // is able to look for the entries per the PSCType.
+  PSCFG_GEN_START,             ///< PSCFG_GEN_START
+  PSCFG_CLKDIS,                ///< PSCFG_CLKDIS
+  PSCFG_CKETRI,                ///< PSCFG_CKETRI
+  PSCFG_ODTTRI,                ///< PSCFG_ODTTRI
+  PSCFG_CSTRI,                 ///< PSCFG_CSTRI
+  PSCFG_GEN_END                ///< PSCFG_GEN_END
+} PSCFG_TYPE;
+
+/// Dimm types
+typedef enum {
+  UDIMM_TYPE = 0x01,           ///< UDIMM_TYPE
+  RDIMM_TYPE = 0x02,           ///< RDIMM_TYPE
+  SODIMM_TYPE = 0x04,          ///< SODIMM_TYPE
+  LRDIMM_TYPE = 0x08,          ///< LRDIMM_TYPE
+  SODWN_SODIMM_TYPE = 0x10,    ///< SODWN_SODIMM_TYPE
+  DT_DONT_CARE = 0xFF          ///< DT_DONT_CARE
+} DIMM_TYPE;
+
+/// Number of DRAM devices or DIMM slots
+typedef enum {
+  _1DIMM = 0x01,               ///< _1DIMM
+  _2DIMM = 0x02,               ///< _2DIMM
+  _3DIMM = 0x04,               ///< _3DIMM
+  _4DIMM = 0x08,               ///< _4DIMM
+  _DIMM_NONE = 0xF0,           ///< _DIMM_NONE (no DIMM slot)
+  NOD_DONT_CARE = 0xFF         ///< NOD_DONT_CARE
+} NOD_SUPPORTED;
+
+/// Table header related definitions
+typedef struct {
+  PSCFG_TYPE PSCType;           ///< PSC Type
+  DIMM_TYPE DimmType;           ///< Dimm Type
+  NOD_SUPPORTED NumOfDimm;      ///< Numbef of dimm
+  CPU_LOGICAL_ID LogicalCpuid;  ///< Logical Cpuid
+  UINT8 PackageType;            ///< Package Type
+  TECHNOLOGY_TYPE TechType;     ///< Technology type
+} PSC_TBL_HEADER;
+
+/// Table entry
+typedef struct {
+  PSC_TBL_HEADER Header;        ///< PSC_TBL_HEADER
+  UINT8 TableSize;              ///< Table size
+  VOID *TBLPtr;                 ///< Pointer of the table
+} PSC_TBL_ENTRY;
+
+#define PT_DONT_CARE 0xFF
+#define NP 1
+#define V1_5  1
+#define V1_35  2
+#define V1_25  4
+#define VOLT_ALL (V1_5 | V1_35 | V1_25)
+#define DIMM_SR 2
+#define DIMM_DR 4
+#define DIMM_QR 8
+#define DIMM_LR 2
+#define R0 1
+#define R1 2
+#define R2 4
+#define R3 8
+#define CH_A 0x01
+#define CH_B 0x02
+#define CH_C 0x04
+#define CH_D 0x08
+#define CH_ALL 0x0F
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+MemPConstructPsUDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+BOOLEAN
+MemPGetDramTerm (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ArraySize,
+  IN       CONST DRAM_TERM_ENTRY *DramTermPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+
+AGESA_STATUS
+MemPConstructPsSDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSRb3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsURb3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSPh3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUPh3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSDA2 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSLN3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsULN3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRLN3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSON3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUON3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+UINT16
+MemPGetPorFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 FreqLimitSize,
+  IN       CONST POR_SPEED_LIMIT *FreqLimitPtr
+  );
+
+VOID
+MemPGetPORFreqLimitDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemPPSCFlow (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemPConstructRankTypeMap (
+  IN          UINT16 Dimm0,
+  IN          UINT16 Dimm1,
+  IN          UINT16 Dimm2,
+  IN OUT   UINT16 *RankTypeInTable
+ );
+
+BOOLEAN
+MemPIsIdSupported (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID LogicalId,
+  IN       UINT8 PackageType
+ );
+
+UINT16
+MemPGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  );
+
+BOOLEAN
+MemPRecPSCFlow (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemPRecConstructRankTypeMap (
+  IN          UINT16 Dimm0,
+  IN          UINT16 Dimm1,
+  IN          UINT16 Dimm2,
+  IN OUT   UINT16 *RankTypeInTable
+ );
+
+BOOLEAN
+MemPRecIsIdSupported (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID LogicalId,
+  IN       UINT8 PackageType
+ );
+
+UINT16
+MemPRecGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  );
+
+UINT16
+MemPProceedTblDrvOverride (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 ProceededPSOType
+  );
+
+BOOLEAN
+MemPGetPSCPass1Seed (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MP_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mport.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mport.h
new file mode 100644
index 0000000000..4c41a89403
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mport.h
@@ -0,0 +1,97 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mport.h
+ *
+ * API's to support different OS
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+ /*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ * ***************************************************************************
+ *
+ *===========================================================================
+ *  AMD Revision History
+ *  Initial Version
+ *
+ */
+#ifndef _MPORT_H_
+#define _MPORT_H_
+
+///< 64 bit data structure
+///< lo - Lower 32 bits
+///< hi - Upper 32 bits
+typedef struct {
+  UINT32 lo; ///< Lower 32 bits
+  UINT32 hi; ///< Upper 32 bits
+} S_UINT64;
+/*
+ *   SBDFO - Segment Bus Device Function Offset
+ *   31:28   Segment (4-bits)
+ *   27:20   Bus     (8-bits)
+ *   19:15   Device  (5-bits)
+ *   14:12   Function(3-bits)
+ *   11:00   Offset  (12-bits)
+ */
+typedef UINT32 SBDFO;
+
+#define GET_SIZE_OF(x)   (sizeof (x) / sizeof (x[0]))
+
+#endif /* _MPORT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mt.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mt.h
new file mode 100644
index 0000000000..67b1652c43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mt.h
@@ -0,0 +1,513 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mt.h
+ *
+ * Common Technology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MT_H_
+#define _MT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+#define FIRST_PASS      1
+#define SECOND_PASS     2
+#define BIGPAGE_X8_RJ16 0x80
+#define BIGPAGE_X8      0x800000ul
+#define DQS_FAIL        1
+#define DQS_PASS        0
+#define DQS_WRITE_DIR    1
+#define DQS_READ_DIR     0
+#define MIN_DQS_WNDW    3
+#define ST_UNSTEADY     0
+#define ST_STEADY       1
+#define ST_GROSS_SWEEP  2
+#define ST_FINE_SWEEP   3
+#define ST_FINISH       4
+#define NIBBLE_0        0
+#define NIBBLE_1        1
+
+#define MAX_BYTELANES_PER_CHANNEL   (8 + 1)  ///< Max Bytelanes per channel
+
+#define MAX_FILTER_DLY_DDR2 0x20
+#define MAX_FILTER_DLY_DDR3 0x28
+
+#define NEW_RECEIVER_START_VALUE  0x4
+#define NEW_RECEIVER_STEP_1       4
+#define NEW_RECEIVER_STEP_2       7
+
+#define NEW_RECEIVER_FINAL_OFFSETVALUE 5
+
+#define MAX_POS_RX_EN_SEED_GROSS_RANGE 0x20     ///< Max Range RxEn Seed Gross
+#define MAX_POS_RX_EN_SEED_GROSS_DIR 0x2       ///< Max RxEn Seed Gross Direction
+
+#define DBG_PRINT_STAGE           18                    // "Stage"
+#define DBG_PRINT_0_TO_64         23                    // "0...64"
+#define DBG_SPACES_4              21                    // 4 spaces
+#define DBG_POS_NEW_LINE          11                    // New Line for POS training
+#define DBG_WR_DLY                24                    // "Write Delay: "
+#define DBG_B_L_R_W_M             22                    // " Bytelane  Left   Right  Width  Middle"
+#define DBG_RX_EN_NEW_LINE        25                    // New Line for Rx En
+#define DBG_RX_EN_STAGE1          6                     // "Receiver Enable Training Stage 1:"
+#define DBG_RX_EN_STAGE2          7                     // "Receiver Enable Training Stage 2:"
+#define DBG_RX_EN_STAGE3          8                     // "Receiver Enable Training Stage 3:"
+#define DBG_DLY_PER_BL            9                     // "Dly per BL   -"
+#define DBG_A_B_DLY               10                    // "ALL BLs have Dly:"
+#define DBG_RCVR_PRT_VALUE        0x0010Ful             // PORT for RX EN training to print a value
+#define DBG_RX_POS_PRT_VALUE      0x0011Ful             // PORT for POS training to print a value
+
+#define DONE_FILTER 0           ///<  optimized receiver enable training glitch search complete
+#define START_FILTER 1          ///<  optimized receiver enable training start glitch filter search
+#define FILTER_FIRST_STAGE_COUNT 4 ///<  optimized receiver enable training glitch filter first stage count
+#define FILTER_SECOND_STAGE_COUNT 7  ///<  optimized receiver enable training glitch second stage count
+#define FILTER_OFFSET_VALUE 0x1C ///<  optimized receiver enable training glitch filter offset value int preamble
+#define FILTER_WINDOW_SIZE 0x28  ///< optimized receiver enable training glitch filter search window size
+#define FILTER_MAX_REC_EN_DLY_VALUE 0x1FF ///< optimized receiver enable glitch filter max receiver value
+#define FILTER_NEW_RECEIVER_START_VALUE  0x0    ///< optimized receiver enable glitch filter  Start value
+#define MAX_NUMBER_NIBBLES 18      ///< Maximum number of nibbles
+#define MAX_NUMBER_LANES 18      ///< Maximum number of lanes (nibbles or bytes)
+#define MAX_2D_VREF_ENTRIES  0x20        ///< Maximum number of vref entries
+#define MAX_RD_DQS_ENTRIES  0x40         ///< Maximum number of RDDQS Entries
+#define VREF_ADDITIONAL_STEP_SIZE  0x0         ///< Vref Additional Step size
+#define RDDQS_ADDITIONAL_STEP_SIZE  0x0         ///< RdDqs Additional Step size
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// List for Technology specific functions that are supported
+typedef enum {
+  WlTrainingPrepareLrdimm,          ///< Technology specific tasks to prepare LRDIMMs for Training
+  LrdimmControlRegInit,             ///< Technology specific tasks to send control words to initialize an LRDIMM
+  LrdimmFreqChgCtrlWrd,             ///< Technology specific tasks to send control words to reprogram LRDIMM's register
+  LrdimmSendAllMRCmds,              ///< Technology specific tasks to send all MR commands
+  LrdimmRankMultiplication,         ///< Determine Rank Multiplication to be used
+  LrdimmBuf2DramTrain,              ///< Perform buffer to DRAM training for LRDIMMs
+  LrdimmSyncTrainedDlys,            ///< Copy trained delay of the first rank of a QR LRDIMM to the third rank
+  LrdimmPresence,                   ///< Perform LRDIMM specific tasks at the time of Dimm Presence Detection
+
+  NumberOfTechHooks                    ///< Size of list
+} TECHNOLOGY_SPECIFIC_FUNC_INDEX;
+
+
+/// Structure for Technology block.
+typedef struct _MEM_TECH_BLOCK {
+  MEM_NB_BLOCK  *NBPtr; ///< point to northbridge block.
+  MEM_PARAMETER_STRUCT *RefPtr; ///< point to parameter list.
+
+  /* Temporary storage */
+  UINT32 HwcrLo; ///< value of HWCR.
+  UINT32 CR4reg; ///< CR4 register value.
+  UINT8  DramEcc; ///< value of Dram ECC bit.
+  UINT8  *TestBufPtr; ///< point to buffer to store read-back data.
+  UINT8  *PatternBufPtr; ///< point to pattern buffer.
+  UINT16 PatternLength; ///< the length of pattern buffer in cache lines.
+  UINT8  Direction; ///< direction during training.
+  UINT8  ChipSel; ///< chip select number.
+  INT8   RestartChipSel;    ///< is used to save the chipsel at which first RdDqsDly retrain is issued
+  UINT16 MaxDlyForMaxRdLat; ///< Largest possible value for Receiver enable delay.
+  UINT16 PrevSpeed; ///< Previous MemClk frequency
+  TRAINING_TYPE  TrainingType;  ///< Type of training currently being done
+  UINT8 TargetDIMM; ///< Target DIMM to being trained
+  INT16 WLCriticalDelay;  ///< Minimum WL Dly of all byte lanes and all DIMMs
+  UINT8 Bytelane; ///< Bytelane being trained
+  UINT8 TrnNibble; ///< Nibble being trained
+
+
+  UINT8  Pass; ///< current pass of training.
+  UINT16 DqsRdWrPosSaved;    ///< for position training byte lane saved flag
+  UINT16 DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  UINT16 DqsRcvEnSavedS1; ///< for TrainRcvrEn UINT8 lane saved flag
+  UINT16 DqsRcvEnFirstPassVal; ///< for TrainRcvrEn UINT8 lane saved flag
+  BOOLEAN GetFirstPassVal; ///< If the first passing value has been found.
+  BOOLEAN RevertPassVal; ///< Flag to restart training during training process when glitch is found.
+  UINT8 MaxFilterDly; ///< Maximum filter delay value for RcvrTraining.
+  UINT16 RcvrEnDlyOpt[MAX_BYTELANES_PER_CHANNEL];     ///< Receiver Enable delay for optimized filter
+  UINT16 MaxRcvrEnDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Max Receiver Enable delay for optimized filter
+  UINT16 RcvrEnDlyLimitOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay Limit for optimized filter
+  UINT16 FilterStatusOpt[MAX_BYTELANES_PER_CHANNEL];  ///< Filter status to indicate if a ByteLane is "DONE", "SKIP" or "CONTINUE"
+  UINT16 FilterCountOpt;  ///< Filter count to indicate the total number of ByteLanes completed
+  BOOLEAN DqsRcvEnSavedOpt[MAX_BYTELANES_PER_CHANNEL];      ///< for optimized TrainRcvrEn lane saved flag
+  UINT16 DqsRcvEnFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for TrainRcvrEn UINT8 lane saved flag for optimized
+  BOOLEAN GetFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< If the first passing value has been found for optimized.
+  BOOLEAN RevertPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Flag to restart training during training process when glitch is found for optimized.
+  UINT8 MaxFilterDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Maximum filter delay value for RcvrTraining for optimized.
+  BOOLEAN IncBy1ForNextCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Used to determine when to increment by 1 in second stage of opt. rec. en. training
+  UINT8 FilterSidePassCountOpt[MAX_BYTELANES_PER_CHANNEL];  ///< Indicates that previous side passed
+  UINT16 DiffSeedGrossSeedPreGross[MAX_BYTELANES_PER_CHANNEL];  ///< Gross difference between GrossSeed and SeedPreGross for HwRxEn Training.
+  UINT16 PrevPassRcvEnDly[MAX_BYTELANES_PER_CHANNEL];  ///< Receiver Enable Delay value from the previous pass
+  BOOLEAN SmallDqsPosWindow; ///< Status flag to record small DQS position window event
+  UINT8 WlNibbleDly[MAX_BYTELANES_PER_CHANNEL];  ///< Nibble based trainig results for Nibble 0 of Write Levelization
+  UINT16 WlNibble0Seed[MAX_BYTELANES_PER_CHANNEL];  ///< Nibble based trainig seed value for Nibble 0 Write Levelization
+  UINT16 RxEnNibbleDly[MAX_BYTELANES_PER_CHANNEL];  ///< Nibble based trainig results for Nibble 0 of Rx En training
+  BOOLEAN ByteLaneError[MAX_BYTELANES_PER_CHANNEL]; ///< Indicates that an error has occured on a bytelane
+  UINT16 RxOrig[MAX_BYTELANES_PER_CHANNEL];  ///< Original RxEn Delays for seedless training
+
+  /* PUBLIC functions */
+  VOID (*SendAllMRCmds) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ChipSel); ///< Send MRS command.
+  VOID (*FreqChgCtrlWrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Frequency change control word.
+  BOOLEAN (*SetDramMode) (struct _MEM_TECH_BLOCK *TechPtr); ///< Set dram mode (DDR2 or DDR3).
+  BOOLEAN (*DimmPresence) (struct _MEM_TECH_BLOCK *TechPtr); ///< determines if DIMMs present.
+  BOOLEAN (*SpdCalcWidth) (struct _MEM_TECH_BLOCK *TechPtr); ///< check the symmetry of DIMM pairs.
+  BOOLEAN (*SpdGetTargetSpeed) (struct _MEM_TECH_BLOCK *TechPtr); ///< get supported frequency.
+  BOOLEAN (*AutoCycTiming) (struct _MEM_TECH_BLOCK *TechPtr); ///< configure timing based on spd data.
+  BOOLEAN (*SpdSetBanks) (struct _MEM_TECH_BLOCK *TechPtr); ///< set bank address.
+  BOOLEAN (*SetDqsEccTmgs) (struct _MEM_TECH_BLOCK *TechPtr); ///< DQS training.
+  VOID (*GetCSIntLvAddr) (UINT8 BankEnc, UINT8 *LowBit, UINT8 *HiBit); ///< Get Chip select interleave address.
+  VOID (*AdjustTwrwr) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrwr for certain dimm technology.
+  VOID (*AdjustTwrrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrrd for certain dimm technology.
+  INT8 (*GetLD) (struct _MEM_TECH_BLOCK *TechPtr); ///< Get LD value for certain dimm technology.
+  VOID (*DramInit) (struct _MEM_TECH_BLOCK *TechPtr); ///< dram initialization.
+
+  /* PRIVATE functions */
+  VOID (*InitDQSPos4RcvrEn) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialize training register before training.
+  VOID (*SetRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
+  VOID (*LoadRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
+  BOOLEAN (*SaveRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< Save receiver enable delay register value.
+  BOOLEAN (*SaveRcvrEnDlyFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< saves passing DqsRcvEnDly values to the stack.
+  VOID (*ResetDCTWrPtr) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< resets the DCT input buffer write pointer.
+  UINT16 (*Compare1ClPattern) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[]); ///< Compare training pattern of 1 cache line.
+  VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
+  VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
+  UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter.
+  UINT8 (*MaxByteLanes) ( VOID ); ///< return maximum number of bytelanes.
+  VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR.
+  VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference.
+  BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value.
+  UINT8 (*DlyTableWidth) ( VOID ); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
+  UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line.
+  VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
+  VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
+  BOOLEAN (*CheckRcvrEnDlyLimitOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Find limit for all bytelanes
+  UINT16 (*GetMaxValueOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///<  Returns the max value of all bytelanes
+  VOID (*InitializeVariablesOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialized variables for optimized training
+  BOOLEAN (*SetSweepErrorOpt)(struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT8 DCT, BOOLEAN ErrorCheck); ///< records any errors generated from optimized sweep
+  VOID (*LoadInitialRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load the starting value for receiver DQS training.
+  BOOLEAN (*GetDimmSpdBuffer) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 **SpdBuffer, UINT8 Dimm); ///< Gets pointer to spd buffer for a dimm on the current channel, if present
+  UINT8 (*GetMinMaxGrossDly) (struct _MEM_TECH_BLOCK *TechPtr, TRN_DLY_TYPE TrnDlyType, BOOLEAN IfMax); ///< Gets the minimum or maximum gross dly value
+
+  /* Technology Specific Hooks */
+  BOOLEAN (*(TechnologySpecificHook[NumberOfTechHooks])) (struct _MEM_TECH_BLOCK *TechPtr, VOID *OptParam); ///< Technology specific functions
+} MEM_TECH_BLOCK;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemTDimmByteTrainInit (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainMaxLatency (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSetDQSEccTmgs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSetDQSEccTmgsRDdr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainDQSEdgeDetectSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainDQSEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDramInitSw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+VOID
+MemTDramInitHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+BOOLEAN
+MemTFeatDef (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilter (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  );
+
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilterOpt (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  );
+
+BOOLEAN
+MemTNewRevTrainingSupport (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainOptRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTPreparePhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTExitPhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTSetWrDatRdDqs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 WrDatDly
+  );
+
+VOID
+MemRecTTrainDQSPosSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTTrainRcvrEnHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTTrainRcvrEnHwSeedless (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSetSweepErrorOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT8 Dct,
+  IN       BOOLEAN ErrorCheck
+  );
+
+VOID
+MemTInitializeVariablesOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+UINT16
+MemTGetMaxValueOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTCheckRcvrEnDlyLimitOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTMarkTrainFail (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+);
+
+VOID
+MemTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTSetDQSDelayAllCSR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dly
+  );
+
+BOOLEAN
+MemTExitPhyAssistedTrainingClient3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTFindMaxRcvrEnDlyRdDqsDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  );
+
+BOOLEAN
+MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  );
+
+VOID
+MemTSendCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CmdNum,
+  IN       UINT8 Value
+  );
+
+VOID
+MemTCommonTechInit (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTLrdimmConstructor3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTRdPosWithRxEnDlySeeds3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrackRxEnSeedlessRdWrNoWindBLError (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemTTrackRxEnSeedlessRdWrSmallWindBLError (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   VOID *OptParam
+  );
+
+
+
+
+#endif  /* _MT_H_ */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h
new file mode 100644
index 0000000000..4582ab2493
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h
@@ -0,0 +1,290 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mu.h
+ *
+ * Utility support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+  *
+  * AMD is granting you permission to use this software (the Materials)
+  * pursuant to the terms and conditions of your Software License Agreement
+  * with AMD.  This header does *NOT* give you permission to use the Materials
+  * or any rights under AMD's intellectual property.  Your use of any portion
+  * of these Materials shall constitute your acceptance of those terms and
+  * conditions.  If you do not agree to the terms and conditions of the Software
+  * License Agreement, please do not use any portion of these Materials.
+  *
+  * CONFIDENTIALITY:  The Materials and all other information, identified as
+  * confidential and provided to you by AMD shall be kept confidential in
+  * accordance with the terms and conditions of the Software License Agreement.
+  *
+  * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+  * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+  * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+  * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+  * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+  * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+  * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+  * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+  * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+  * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+  * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+  * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+  * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+  *
+  * AMD does not assume any responsibility for any errors which may appear in
+  * the Materials or any other related information provided to you by AMD, or
+  * result from use of the Materials or any related information.
+  *
+  * You agree that you will not reverse engineer or decompile the Materials.
+  *
+  * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+  * further information, software, technical information, know-how, or show-how
+  * available to you.  Additionally, AMD retains the right to modify the
+  * Materials at any time, without notice, and is not obligated to provide such
+  * modified Materials to you.
+  *
+  * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+  * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+  * subject to the restrictions as set forth in FAR 52.227-14 and
+  * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+  * Government constitutes acknowledgement of AMD's proprietary rights in them.
+  *
+  * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+  * direct product thereof will be exported directly or indirectly, into any
+  * country prohibited by the United States Export Administration Act and the
+  * regulations thereunder, without the required authorization from the U.S.
+  * government nor will be used for any purpose prohibited by the same.
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MU_H_
+#define _MU_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+  #define PSO_ENTRY UINT8
+#endif
+
+//
+// Maximum value macro
+//
+#ifndef MAX
+  #define MAX(X, Y) (((X) < (Y)) ? (Y) : (X))
+#endif
+//
+// Minimum Value macro
+//
+#ifndef MIN
+  #define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
+#endif
+//
+// Absolute Value Macro
+//
+#ifndef ABS
+  #define ABS(X) (((X) < 0) ? (-(X)) : (X))
+#endif
+//
+// Taking ceiling of (a / b)
+//
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+//
+// Check if value x is a power of 2 or not
+//
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Test patterns for DQS training
+typedef enum {
+  TestPattern0,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern1,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern2,             ///< Test pattern used in second pass of receiver enable training
+  TestPatternJD1B,          ///< 72-bit test pattern used in position training (ganged mode)
+  TestPatternJD1A,          ///< 72-bit test pattern used in position training
+  TestPatternJD256B,        ///< 256-bit test pattern used in position training (ganged mode)
+  TestPatternJD256A,        ///< 256-bit test pattern used in position training
+  TestPatternML,            ///< Test pattern used in first pass of max latency training
+  TestPattern3,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern4              ///< Test pattern used in first pass of receiver enable training
+} TRAIN_PATTERN;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemUWriteCachelines (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemUReadCachelines (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemUDummyCLRead (
+  IN       UINT32 Address
+  );
+
+VOID
+MemUFlushPattern (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+
+VOID
+MemUFillTrainPattern (
+  IN       TRAIN_PATTERN Pattern,
+  IN       UINT8 Buffer[],
+  IN       UINT16 Size
+  );
+
+UINT32
+MemUSetUpperFSbase (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUSetTargetWTIO (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUResetTargetWTIO (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUProcIOClFlush (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUWait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUGetWrLvNblErr (
+  IN OUT   UINT16 *ErrBitmap,
+  IN       UINT32 TestAddr,
+  IN       UINT16 ClCount
+  );
+
+VOID
+AlignPointerTo16Byte (
+  IN OUT   UINT8 **BufferPtrPtr
+  );
+
+VOID *
+FindPSOverrideEntry (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       PSO_ENTRY EntryType,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID,
+  IN       UINT8 DimmID,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+GetMaxDimmsPerChannel (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN UINT8 ChannelID
+  );
+
+UINT8
+GetMaxSolderedDownDimmsPerChannel (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  );
+
+UINT8
+GetMaxChannelsPerSocket (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+GetMaxCSPerChannel (
+  IN      PSO_TABLE *PlatformMemoryConfiguration,
+  IN      UINT8 SocketID,
+  IN      UINT8 ChannelID
+  );
+
+UINT8
+GetSpdSocketIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+GetSpdChannelIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN UINT8 ChannelID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+GetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MemUMFenceInstr (VOID
+  );
+
+UINT32
+MemUnsToMemClk (
+  IN       MEMORY_BUS_SPEED Speed,
+  IN       UINT32 NumberOfns
+  );
+#endif  /* _MU_H_ */
+
+